[v1] TriCore Privilege Levels

[PATCH 0/4] TriCore Privilege Levels

Bastian Koppelmann posted 4 patches 11 months, 1 week ago

Diff against v2 v3 v4
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target/tricore/cpu.h       | 17 +++++++----
target/tricore/op_helper.c | 11 +++++++
target/tricore/translate.c | 61 ++++++++++++++++++++++++++++----------
3 files changed, 68 insertions(+), 21 deletions(-)

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[PATCH 0/4] TriCore Privilege Levels

Posted by Bastian Koppelmann 11 months, 1 week ago

Hi,

this patch series tries to properly implement privilege levels for the TriCore,
as discussed in
https://lore.kernel.org/qemu-devel/20230118090319.32n4uto7ogy3gfr6@schnipp.zuhause/.

While implementing privilege traps for the SV/UM1 only insns, I saw that
the RESTORE insn uses the wrong ICR.IE bit. So I fixed that as well.

Cheers,
Bastian

Bastian Koppelmann (4):
  target/tricore: Introduce priv tb flag
  target/tricore: Implement privilege level for all insns
  target/tricore: Honour privilege changes on PSW write
  target/tricore: Fix ICR.IE offset in RESTORE insn

 target/tricore/cpu.h       | 17 +++++++----
 target/tricore/op_helper.c | 11 +++++++
 target/tricore/translate.c | 61 ++++++++++++++++++++++++++++----------
 3 files changed, 68 insertions(+), 21 deletions(-)

-- 
2.40.1