From nobody Sat May 18 15:49:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1686690034; cv=none; d=zohomail.com; s=zohoarc; b=AR1EUJLhSyFnWrRMromSiYRsQ/5Eg4yQtmCjKgy1rHPz6bYotiWg0lxxWZcaEEUl7jZoZyHK8rFViLX0yJMdwBkD39DUrqng5QZ7LyFMwzba+iSiJFOb8ewwMEdnh8O40J57KfDG8bi45eezzMJTtuFWOe9XsuekztgtHZQ1+AU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686690034; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hdlVCgCsofoU3sFhayk2xbcE3ncEw8ypwrBf9jIXxPE=; b=KjHn4hgsPFJHBEfMg7LHGxo4EIK+eRmaVuHAGHJz9hub4C24VerndgAyGL4xnX9q/uRjK7PylyTwjydM0fO29CSu3aq9EdrL2YvqG7NMWQvKjxtNFBjjStOL9hD3h/PPuFRXIENQe9DPLzGDJXypj8XcIjEaOsz6WaqMYVc0vjc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686690034798464.9686509565013; Tue, 13 Jun 2023 14:00:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9B6p-0001yC-R9; Tue, 13 Jun 2023 16:59:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9B6n-0001xK-UH for qemu-devel@nongnu.org; Tue, 13 Jun 2023 16:59:21 -0400 Received: from mail-oi1-x22c.google.com ([2607:f8b0:4864:20::22c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q9B6l-0006ct-UT for qemu-devel@nongnu.org; Tue, 13 Jun 2023 16:59:21 -0400 Received: by mail-oi1-x22c.google.com with SMTP id 5614622812f47-39c7f7a151fso3436194b6e.0 for ; Tue, 13 Jun 2023 13:59:19 -0700 (PDT) Received: from grind.. ([177.170.117.210]) by smtp.gmail.com with ESMTPSA id q82-20020acaf255000000b003982a8a1e3fsm5619514oih.51.2023.06.13.13.59.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 13:59:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686689958; x=1689281958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hdlVCgCsofoU3sFhayk2xbcE3ncEw8ypwrBf9jIXxPE=; b=IikGr5frSWPiVYu+iUe//e1Jj8dnqyz5eb4uGSZPilsNlK6JqRE78EHkrcfMxOmqMt LK7gOOLGgTL11iyuTBEW/VEvfgldH2F3vlulagjn1P274tCQOeg4ZEQTgOBb1IEXmQXD 44184uT1u41xjOLi4d8wIA7FQR0Of6J4ro8ucDSLoBAEj+on9L9BjtZ5lsGsXha69TZ1 dcqR786B4vW8VJsZUwkdiZSbWhSZ9gxCVUPc7JzFw5OLVSfUqn3GwvMniO10BuTwur7W 7y9GPGRgya9uY06GMWsiO/JYlI+P7JP8lkyvmYgOVAZSGSJmw75GDkZKqB9/Mgo4/Cwq s7sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686689958; x=1689281958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hdlVCgCsofoU3sFhayk2xbcE3ncEw8ypwrBf9jIXxPE=; b=MbMKhr7IjZmEGjqR8NHI6H9HZL4iNBATgmc9QdnvlJIK1UYvaQANgP/9vr5qAYgjvj zR0fB9T3kCp4GCEkbq3OK/yFTCfpoj7ns0RFr2IXvLblb4xh7nTY7kKg+KJbxgxHBqvN h1/xAow7AS7EbRWXml1FisuzAmOAOx7g2wl3LNidv/wdtCJcxyEorof9FFZk9PqbhZt3 oQu52j7XbY6aCexrQx29vV1SQzpF1OCXydwnH2ck9Qf5cT0/7AMFryflNEkBmG/BGuWg +5q9pKvxMgVxZgcg1wanYBeqrYy5wvI3HydvHYauzBMwrvhD7CUJNPD0KIey9WIo3eF8 k2IQ== X-Gm-Message-State: AC+VfDygafRd9Ywb4+HcK/FAJqN1IfnBOvVELgGs2fX09g6z35yMSwLE HIHWxgswyyYSK5DWalr7EvGVQgPrpLdgN7SAIIA= X-Google-Smtp-Source: ACHHUZ46jxEeCBMk6z7agJztuoSYzJJmkWes2zncx0Xz3LKaHYu4/u6wiAbIihW5+BAcGZS/WisMRA== X-Received: by 2002:a05:6808:1881:b0:39c:7b95:ddc0 with SMTP id bi1-20020a056808188100b0039c7b95ddc0mr9937942oib.35.1686689958378; Tue, 13 Jun 2023 13:59:18 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 01/18] target/riscv: skip features setup for KVM CPUs Date: Tue, 13 Jun 2023 17:58:40 -0300 Message-Id: <20230613205857.495165-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613205857.495165-1-dbarboza@ventanamicro.com> References: <20230613205857.495165-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1686690037213100003 Content-Type: text/plain; charset="utf-8" As it is today it's not possible to use '-cpu host' if the RISC-V host has RVH enabled. This is the resulting error: $ sudo ./qemu/build/qemu-system-riscv64 \ -machine virt,accel=3Dkvm -m 2G -smp 1 \ -nographic -snapshot -kernel ./guest_imgs/Image \ -initrd ./guest_imgs/rootfs_kvm_riscv64.img \ -append "earlycon=3Dsbi root=3D/dev/ram rw" \ -cpu host qemu-system-riscv64: H extension requires priv spec 1.12.0 This happens because we're checking for priv spec for all CPUs, and since we're not setting env->priv_ver for the 'host' CPU, it's being default to zero (i.e. PRIV_SPEC_1_10_0). In reality env->priv_ver does not make sense when running with the KVM 'host' CPU. It's used to gate certain CSRs/extensions during translation to make them unavailable if the hart declares an older spec version. It doesn't have any other use. E.g. OpenSBI version 1.2 retrieves the spec checking if the CSR_MCOUNTEREN, CSR_MCOUNTINHIBIT and CSR_MENVCFG CSRs are available [1]. 'priv_ver' is just one example. We're doing a lot of feature validation and setup during riscv_cpu_realize() that it doesn't apply KVM CPUs. Validating the feature set for those CPUs is a KVM problem that should be handled in KVM specific code. The new riscv_cpu_realize_features() helper contains all validation logic that are not applicable to KVM CPUs. riscv_cpu_realize() verifies if we're dealing with a KVM CPU and, if not, execute the new helper to proceed with the usual realize() logic for all other CPUs. [1] lib/sbi/sbi_hart.c, hart_detect_features() Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 43 +++++++++++++++++++++++++++++++++---------- 1 file changed, 33 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 881bddf393..e904018644 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -331,6 +331,15 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) } #endif =20 +static bool riscv_running_kvm(void) +{ +#ifndef CONFIG_USER_ONLY + return kvm_enabled(); +#else + return false; +#endif +} + static void riscv_any_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); @@ -1304,20 +1313,12 @@ static void riscv_cpu_validate_misa_priv(CPURISCVSt= ate *env, Error **errp) } } =20 -static void riscv_cpu_realize(DeviceState *dev, Error **errp) +static void riscv_cpu_realize_features(DeviceState *dev, Error **errp) { - CPUState *cs =3D CPU(dev); RISCVCPU *cpu =3D RISCV_CPU(dev); CPURISCVState *env =3D &cpu->env; - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 - cpu_exec_realizefn(cs, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - riscv_cpu_validate_misa_mxl(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); @@ -1352,7 +1353,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) } =20 #ifndef CONFIG_USER_ONLY - cs->tcg_cflags |=3D CF_PCREL; + CPU(dev)->tcg_cflags |=3D CF_PCREL; =20 if (cpu->cfg.ext_sstc) { riscv_timer_init(cpu); @@ -1365,6 +1366,28 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) } } #endif +} + +static void riscv_cpu_realize(DeviceState *dev, Error **errp) +{ + CPUState *cs =3D CPU(dev); + RISCVCPU *cpu =3D RISCV_CPU(dev); + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); + Error *local_err =3D NULL; + + cpu_exec_realizefn(cs, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + + if (!riscv_running_kvm()) { + riscv_cpu_realize_features(dev, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + } =20 riscv_cpu_finalize_features(cpu, &local_err); if (local_err !=3D NULL) { --=20 2.40.1 From nobody Sat May 18 15:49:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1686690159; cv=none; d=zohomail.com; s=zohoarc; b=X25EZbuYWJkbN7efEaW9EZesUoVbsJYDGZr6naxtssIqBxbxDpww6IdWIq3QxvpUALuDeqj0Elz4SU+ibCGzZoAoJj+qg5u74mcwY1bq9vOMPHBmjfYVlWaI7MXPEffNih5TcgLXfOXQWrj6NbOcz9tflNvQokxkqXVeSwBfbhk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686690159; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OnHsil+rlJITNmRjajhe4WP+4n0ur2gd/ZeLsL06USo=; b=LZ5VSyQGU7Gfg7YMHt8pxb7RVnpXUaLw64jRhtSA8ZvUsQYzfaKN3xnJrXgafwsnkUWIwHJkr4ZX/obxjK3WskSCcYkvzZYmol34U9d9VjDrlEPisbcnNJTzgLhWwxSmkPAjvsecBgCo0g77xaeHPAspJEYXarRAK1BCFMNl8fE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686690159292324.03437718258886; Tue, 13 Jun 2023 14:02:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9B6t-0001z5-0m; Tue, 13 Jun 2023 16:59:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9B6r-0001yN-9d for qemu-devel@nongnu.org; Tue, 13 Jun 2023 16:59:25 -0400 Received: from mail-oo1-xc35.google.com ([2607:f8b0:4864:20::c35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q9B6o-0006dr-Ol for qemu-devel@nongnu.org; Tue, 13 Jun 2023 16:59:25 -0400 Received: by mail-oo1-xc35.google.com with SMTP id 006d021491bc7-55b2fb308bbso10710eaf.1 for ; Tue, 13 Jun 2023 13:59:22 -0700 (PDT) Received: from grind.. ([177.170.117.210]) by smtp.gmail.com with ESMTPSA id q82-20020acaf255000000b003982a8a1e3fsm5619514oih.51.2023.06.13.13.59.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 13:59:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686689961; x=1689281961; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OnHsil+rlJITNmRjajhe4WP+4n0ur2gd/ZeLsL06USo=; b=bobXsVpW7/Wv9slPkM/HRZExSBTz1VDd2DkVE5IPYA0XZV2O/eMkA/FbLTnGUgvXGF vkzgxHeuGbYhrMQQXnn2cbQvmgxHLpIhrjnYeCwlWpCc0zP21ogO/bRlFTLglZjbfH4a gQSMJjufFISUI5szaQzK73BG6SAmdCLfyU75l2IWnUzuhQI2C8AcN7XNM+jOQKBbILVy la3QMrgAwvnHvRAkxhTRTRgJfPlIqz/7JYB0HFGlUCfPsDu6GGaTqTUaqQAIg7fbM4kx shN4d/ov6L8ZijzPWKsRIWSmDYndP4u7WqUlPkxQthAS6HI0fphaVdcxJ83H5y+6F77T bzyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686689961; x=1689281961; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OnHsil+rlJITNmRjajhe4WP+4n0ur2gd/ZeLsL06USo=; b=Bnj5ZJbHUVJYZFdyNjWHHhsgvpApnOczQL3eKBWMrNSH7MQzpgVM1dLn39StDXw7kG 7zxy2XfgvofWApjss5p47tXpguu3jHxhExommR7TF/5iNM0bfkE/hQblwxGHRPMSgf0X oOBLLjbvt1CKgivwgy0eyaMRCjhs9vX/rMrEU0wbsX40PbVwD5m60AM87he4n7ErcWgZ mCk76+QGfyT+JHrNKEhJbHMGZ2tGzOiHUw+8A8ce/K51xmrRgrdoW6Y+/nRQawQ8/Jxl vMoaqBIsxvNB4PzuEQhGg1WVyXzu8LfYLAv4Ia2VnwlC5HcWXXUHWbG753o6YuuIPcXv McJQ== X-Gm-Message-State: AC+VfDzPpPmyD//WNHqjZr4O2zyJL3aRFflhKTspsACPL5UayQI5IjnR QhnQ890eo5ClrCLsSJoFBNatGsIBU4gNl20NVpU= X-Google-Smtp-Source: ACHHUZ4TxXeYPrVPQWW4qTka2gL5zqJ53LEdCOSTKvt0SJFDbpqtgbmZajOdaWzxEH0p+yrgTnEnnA== X-Received: by 2002:a05:6808:1291:b0:39b:dab1:4b32 with SMTP id a17-20020a056808129100b0039bdab14b32mr10761818oiw.0.1686689961244; Tue, 13 Jun 2023 13:59:21 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 02/18] hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set Date: Tue, 13 Jun 2023 17:58:41 -0300 Message-Id: <20230613205857.495165-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613205857.495165-1-dbarboza@ventanamicro.com> References: <20230613205857.495165-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c35; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1686690161155100001 Content-Type: text/plain; charset="utf-8" The absence of a satp mode in riscv_host_cpu_init() is causing the following error: $ sudo ./qemu/build/qemu-system-riscv64 -machine virt,accel=3Dkvm \ -m 2G -smp 1 -nographic -snapshot \ -kernel ./guest_imgs/Image \ -initrd ./guest_imgs/rootfs_kvm_riscv64.img \ -append "earlycon=3Dsbi root=3D/dev/ram rw" \ -cpu host ** ERROR:../target/riscv/cpu.c:320:satp_mode_str: code should not be reached Bail out! ERROR:../target/riscv/cpu.c:320:satp_mode_str: code should not be reached Aborted The error is triggered from create_fdt_socket_cpus() in hw/riscv/virt.c. It's trying to get satp_mode_str for a NULL cpu->cfg.satp_mode.map. For this KVM cpu we would need to inherit the satp supported modes from the RISC-V host. At this moment this is not possible because the KVM driver does not support it. And even when it does we can't just let this broken for every other older kernel. Since mmu-type is not a required node, according to [1], skip the 'mmu-type' FDT node if there's no satp_mode set. We'll revisit this logic when we can get satp information from KVM. [1] https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/= cpu.yaml Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- hw/riscv/virt.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 76c7a3ba3b..e80127d28a 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -243,13 +243,13 @@ static void create_fdt_socket_cpus(RISCVVirtState *s,= int socket, s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(ms->fdt, cpu_name); =20 - satp_mode_max =3D satp_mode_max_from_map( - s->soc[socket].harts[cpu].cfg.satp_mode.map); - sv_name =3D g_strdup_printf("riscv,%s", - satp_mode_str(satp_mode_max, is_32_bit)); - qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name); - g_free(sv_name); - + if (cpu_ptr->cfg.satp_mode.supported !=3D 0) { + satp_mode_max =3D satp_mode_max_from_map(cpu_ptr->cfg.satp_mod= e.map); + sv_name =3D g_strdup_printf("riscv,%s", + satp_mode_str(satp_mode_max, is_32_b= it)); + qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name= ); + g_free(sv_name); + } =20 name =3D riscv_isa_string(cpu_ptr); qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name); --=20 2.40.1 From nobody Sat May 18 15:49:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1686690054; cv=none; d=zohomail.com; s=zohoarc; b=GjjOqB8hn7x8CKEEheWu8+nl5lVtRK1DSj2jtkA8e7KsXoZ3TuhbkYSyIwqeKPyJBG9Ai6xeb/r6h3lMbjEZCpFwTlsLNw3+3NqQhYwFVLQ2vvvkpQF0wFk5nso0zGRur5iE37R75+nbOwjSqUKyzjTllOHflyGrnFUl9JCc24A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686690054; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1gamNTgRCK1Jybxt4tuq3/QyAcSnMglq0x9giTU3Zac=; b=Em7ufG7OUtx1Bxx6aDeWv3lJg2QhqjpVQ+07Ahqd3q2UVqglwXjnjioGTdEJzLHj8pNR+ZXIKo1PfveO6GkztXMPUc705b0GmQYsSl4CRq31FJGlVrwc31qEV/ydgl6Je9vpVovd2mSoDjhTGAuPOSHpamzKF7xhpI26woX+aTs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686690054104541.396144019761; Tue, 13 Jun 2023 14:00:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9B6u-00020z-Oa; Tue, 13 Jun 2023 16:59:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9B6t-00020m-JN for qemu-devel@nongnu.org; Tue, 13 Jun 2023 16:59:27 -0400 Received: from mail-oi1-x231.google.com ([2607:f8b0:4864:20::231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q9B6r-0006el-UX for qemu-devel@nongnu.org; Tue, 13 Jun 2023 16:59:27 -0400 Received: by mail-oi1-x231.google.com with SMTP id 5614622812f47-39c84863e34so3853710b6e.2 for ; Tue, 13 Jun 2023 13:59:25 -0700 (PDT) Received: from grind.. ([177.170.117.210]) by smtp.gmail.com with ESMTPSA id q82-20020acaf255000000b003982a8a1e3fsm5619514oih.51.2023.06.13.13.59.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 13:59:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686689964; x=1689281964; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1gamNTgRCK1Jybxt4tuq3/QyAcSnMglq0x9giTU3Zac=; b=Jn2uwApA9el0+9qKvAuVZd9nlFwhlxcf0a4xu7Eci6zh4g6/fAjwIL+l3fjJRnhEhY hEjSpEBftpBAuY2hWj/ZDL5/dgiRHm3oNxWX2c3D2Vzjqs6NJmAMIMVg1KMVL05OLnQl ia9LFHx+oG1LN2pvhJN493amF5ulYvlfnNyVqKWsBJfytEzicJJynB2cNBa05HQU3pL8 hlcOZHZ7MymHMMgu0Cog4CTF45GNUpCeI8z/8aUPel9MvBRUUC9ljjNZC4xNQy9EJrWM 7VCPgarPLxejfxlimM85+eHAf+bTYNyv6WQaOvGm1JgkI5fxrjyzPFJw47GoTIdtNoqj pvTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686689964; x=1689281964; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1gamNTgRCK1Jybxt4tuq3/QyAcSnMglq0x9giTU3Zac=; b=YcZ19iRQdZDMgaf1OBMHO/qPU6046SmMeLGt0KIbv7I3QckZrFhaPrfed+bPerUTvm bp09ijyWb5B2vg6hP39VlSrDEV2QifTcr11R7IeKYbBQDT9awgNVavv9vnbOYRXLYVXG 1L8MC9JwKTWoH+HASTNDr/qhtFiBWvfBZjhVyX2re+Lg9iXCEMyWfhRd6OIxpXYYwBn4 whDzN8kcl+Fo55PiQ9kInZYWm6agjjSgBauVLCXioI66oV0Kt09F3Pb9yW0YpZxg7eJ8 5NJNgZSr0wrDBt6Smmn4kLo0qXcCWbZRtN8WCn3HB2P5eJOACky+er2vhws/maxwAugi zLsg== X-Gm-Message-State: AC+VfDzJHXikJlNSmecF4RRmgI7mfWiqC3mBELlip+HzXsOp521tHGom szQTeS0eRmkaXdipkQ+sa0jJbubiTGb7pG9zY8o= X-Google-Smtp-Source: ACHHUZ5ZoA/1fZ4BJ8tb+p1feiz/Ow1Q8nw1Zf0AS+/zcQX+swWdD7+ko1OVLHHVeH+qyzN6wprxJw== X-Received: by 2002:a05:6808:2381:b0:398:1027:4fae with SMTP id bp1-20020a056808238100b0039810274faemr10397164oib.25.1686689964059; Tue, 13 Jun 2023 13:59:24 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 03/18] target/riscv/cpu.c: restrict 'mvendorid' value Date: Tue, 13 Jun 2023 17:58:42 -0300 Message-Id: <20230613205857.495165-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613205857.495165-1-dbarboza@ventanamicro.com> References: <20230613205857.495165-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1686690054662100001 Content-Type: text/plain; charset="utf-8" We're going to change the handling of mvendorid/marchid/mimpid by the KVM driver. Since these are always present in all CPUs let's put the same validation for everyone. It doesn't make sense to allow 'mvendorid' to be different than it is already set in named (vendor) CPUs. Generic (dynamic) CPUs can have any 'mvendorid' they want. Change 'mvendorid' to be a class property created via 'object_class_property_add', instead of using the DEFINE_PROP_UINT32() macro. This allow us to define a custom setter for it that will verify, for named CPUs, if mvendorid is different than it is already set by the CPU. This is the error thrown for the 'veyron-v1' CPU if 'mvendorid' is set to an invalid value: $ qemu-system-riscv64 -M virt -nographic -cpu veyron-v1,mvendorid=3D2 qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.mvendorid=3D2: Unable to change veyron-v1-riscv-cpu mvendorid (0x61f) Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e904018644..6a9a6d34eb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1734,7 +1734,6 @@ static void riscv_cpu_add_user_properties(Object *obj) static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 - DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID= ), DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), =20 @@ -1821,6 +1820,40 @@ static const struct TCGCPUOps riscv_tcg_ops =3D { #endif /* !CONFIG_USER_ONLY */ }; =20 +static bool riscv_cpu_is_dynamic(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; +} + +static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint32_t prev_val =3D cpu->cfg.mvendorid; + uint32_t value; + + if (!visit_type_uint32(v, name, &value, errp)) { + return; + } + + if (!dynamic_cpu && prev_val !=3D value) { + error_setg(errp, "Unable to change %s mvendorid (0x%x)", + object_get_typename(obj), prev_val); + return; + } + + cpu->cfg.mvendorid =3D value; +} + +static void cpu_get_mvendorid(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value =3D RISCV_CPU(obj)->cfg.mvendorid; + + visit_type_bool(v, name, &value, errp); +} + static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); @@ -1852,6 +1885,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; cc->tcg_ops =3D &riscv_tcg_ops; =20 + object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, + cpu_set_mvendorid, NULL, NULL); + device_class_set_props(dc, riscv_cpu_properties); } =20 --=20 2.40.1 From nobody Sat May 18 15:49:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1686690065; cv=none; d=zohomail.com; s=zohoarc; b=TV/MvtfzjmEpXwYDn+A/D7Pbzo+c3/eX3aUNRaQVjyMfJaNgZRSqNEqlkEfLHO6T52f22VR9XbJdsMbc8tQ4N3FeYJ/AkztfRYTHTmtTZUPVJsytmQe19VYhvl8fbXTtbEmW4enxqoFI2G3V13XX3WIEuJY3+7RNty9BSK7xn9U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686690065; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CLGO//MY4I5Oc61K3sYPrsApC28gAwnypQlxx+aTI6U=; b=EFCHRitWmv2pU0Jp8v2gEZEvAhywj5jIDoobmHTyTQca3EN+y3WINdlhtM1RWTIi1VSxPOxNkyOKfguGvPbzJgQCm1TE//YFvFv4PqNnHWEhHKa/LVvk/ru/8pg3s1vhE6FFmAReFukFLdX3cSYmZ/IH4v3eK5ASNMi6L1B2eqM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168669006595484.44005668072089; Tue, 13 Jun 2023 14:01:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9B6w-00021k-N9; Tue, 13 Jun 2023 16:59:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9B6v-00021a-VM for qemu-devel@nongnu.org; Tue, 13 Jun 2023 16:59:29 -0400 Received: from mail-oi1-x236.google.com ([2607:f8b0:4864:20::236]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q9B6u-0006gx-Co for qemu-devel@nongnu.org; Tue, 13 Jun 2023 16:59:29 -0400 Received: by mail-oi1-x236.google.com with SMTP id 5614622812f47-39c7f5706f0so3753080b6e.3 for ; Tue, 13 Jun 2023 13:59:28 -0700 (PDT) Received: from grind.. ([177.170.117.210]) by smtp.gmail.com with ESMTPSA id q82-20020acaf255000000b003982a8a1e3fsm5619514oih.51.2023.06.13.13.59.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 13:59:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686689967; x=1689281967; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CLGO//MY4I5Oc61K3sYPrsApC28gAwnypQlxx+aTI6U=; b=BuUDnV2/qLNu+TAJKF2icXMpNp4zm9hhydfScStUVor0OORd6eo1VXO8SrKnfgjD6H jrEvYxmMdKalp1idZMZTEwsUErW9tuivxduEcFAqLitg1QOpIFKqNOwWHfaQ1iXCm/mp ZxjdcaQ7ZNvGqxvMsu/dH35c3gxQIR8Lv6XOWoQWwWpiIBPfCINcXWfC757CFp0BVnqQ Y4urPmzjUI15VncqL1LMvfsP6WCzSXKrRZrv4QiTyaiVnmkW+kRU/mtU03Wso1JAibnG MGHeK97ZZ2TgG3rN3qCaAbnfqukYggiI3eUPP8GhFFnGntayuHPKL7BmM7IadRXHyUbS kADQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686689967; x=1689281967; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CLGO//MY4I5Oc61K3sYPrsApC28gAwnypQlxx+aTI6U=; b=KlsTE6ne8d2Xk5Mof3hlKngFHmlQ4TFF0nbOa1BICrungyEMeuxKC2kXO8qr1aKU1b mNUxC7+MtxzYQbbbleVu9+cZpbGAMi5c4wQCVb967wfQwauin2qHxObpHJhK/ol2CbeY KHRNa7K9oLxmslFrfuEEv/CdMhXTafFM7aokpPfp9V3D11c/FnqR5THUwT3oiCpG1cE0 fknm/sGzHLqWdFaW/KbnDi5XJoK34Ajc7mj5s0KGK/nt45TqbM+h0W2qMELlFJ+xmn+P 9LZCvYpOXbcqNmCkVZFlF/yRUhZl4YeXJk4uWIJNZWuEitPgJxwXdZCqUReavj+9z6f+ kbEw== X-Gm-Message-State: AC+VfDyItS/+P45Q1JFCE1+ngLVJTbt0gLCQF6FfTS16mhyNNl6eqdY2 B/e8+6nX1BEhTfmkclYpMBGU1dzQbheJVDhVvWA= X-Google-Smtp-Source: ACHHUZ5XO23URy6JkJef5jIw0lVQz+4a3jtpJ04nHAYmxWUaVnsufOGuqkG+HiH5p718Hlr0oV7rkw== X-Received: by 2002:a05:6808:1c8:b0:39c:5d03:6a5a with SMTP id x8-20020a05680801c800b0039c5d036a5amr8050479oic.7.1686689966895; Tue, 13 Jun 2023 13:59:26 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 04/18] target/riscv/cpu.c: restrict 'mimpid' value Date: Tue, 13 Jun 2023 17:58:43 -0300 Message-Id: <20230613205857.495165-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613205857.495165-1-dbarboza@ventanamicro.com> References: <20230613205857.495165-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1686690067557100005 Content-Type: text/plain; charset="utf-8" Following the same logic used with 'mvendorid' let's also restrict 'mimpid' for named CPUs. Generic CPUs keep setting the value freely. Note that we're getting rid of the default RISCV_CPU_MARCHID value. The reason is that this is not a good default since it's dynamic, changing with with every QEMU version, regardless of whether the actual implementation of the CPU changed from one QEMU version to the other. Named CPU should set it to a meaningful value instead and generic CPUs can set whatever they want. This is the error thrown for an invalid 'mimpid' value for the veyron-v1 CPU: $ ./qemu-system-riscv64 -M virt -nographic -cpu veyron-v1,mimpid=3D2 qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.mimpid=3D2: Unable to change veyron-v1-riscv-cpu mimpid (0x111) Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6a9a6d34eb..39c550682a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -42,7 +42,6 @@ #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ (QEMU_VERSION_MINOR << 8) | \ (QEMU_VERSION_MICRO)) -#define RISCV_CPU_MIMPID RISCV_CPU_MARCHID =20 static const char riscv_single_letter_exts[] =3D "IEMAFDQCPVH"; =20 @@ -1735,7 +1734,6 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID= ), - DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), @@ -1854,6 +1852,35 @@ static void cpu_get_mvendorid(Object *obj, Visitor *= v, const char *name, visit_type_bool(v, name, &value, errp); } =20 +static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint64_t prev_val =3D cpu->cfg.mimpid; + uint64_t value; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (!dynamic_cpu && prev_val !=3D value) { + error_setg(errp, "Unable to change %s mimpid (0x%lx)", + object_get_typename(obj), prev_val); + return; + } + + cpu->cfg.mimpid =3D value; +} + +static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value =3D RISCV_CPU(obj)->cfg.mimpid; + + visit_type_bool(v, name, &value, errp); +} + static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); @@ -1888,6 +1915,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, cpu_set_mvendorid, NULL, NULL); =20 + object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid, + cpu_set_mimpid, NULL, NULL); + device_class_set_props(dc, riscv_cpu_properties); } =20 --=20 2.40.1 From nobody Sat May 18 15:49:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1686690167; cv=none; d=zohomail.com; s=zohoarc; b=JAFKVpfQh+2qQ3Y5tXHxDGlxffAGDzuyKpp2fac+4keni0Wwezk4TDYh/KKs/hQB1gxFLVxDRii7LO73U8SfwDv0qeyqxUb+1AVj8cvCf+nWPygGvIrkzRJ0ZQxGq3XYtwhIGNs9jd0yOkEMbHdiJmzLgsn0V0jEPnV9Sfa1oWs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686690167; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hzf4sp0Mbi0CaaHlXXwQFemFEE/XbJHyvZ92xqH1v50=; b=ElVn9pBB9MP+GwjQ4H1QuUZ08lsKX+sclYwPzzeLjMtqPqHaM8gJbaJj11zXlm0+TyqCjuSk/8BynX67CqfIuMv8pAwzupclzuUQIy1n9kKbmKt5/0yHIfKg9y6+yzHlXg81RP1iqgZClJ/t/eb6hjVx0pofpMnQcRgI/7G2UJk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686690167635578.690707234281; Tue, 13 Jun 2023 14:02:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9B71-000238-B2; Tue, 13 Jun 2023 16:59:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9B6z-00022U-2r for qemu-devel@nongnu.org; Tue, 13 Jun 2023 16:59:33 -0400 Received: from mail-oi1-x22d.google.com ([2607:f8b0:4864:20::22d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q9B6x-0006hr-A4 for qemu-devel@nongnu.org; Tue, 13 Jun 2023 16:59:32 -0400 Received: by mail-oi1-x22d.google.com with SMTP id 5614622812f47-392116ae103so3715361b6e.0 for ; Tue, 13 Jun 2023 13:59:30 -0700 (PDT) Received: from grind.. ([177.170.117.210]) by smtp.gmail.com with ESMTPSA id q82-20020acaf255000000b003982a8a1e3fsm5619514oih.51.2023.06.13.13.59.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 13:59:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686689970; x=1689281970; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hzf4sp0Mbi0CaaHlXXwQFemFEE/XbJHyvZ92xqH1v50=; b=gAkBirEwiUipelIpFeyvcFXwOrqw9c4SdAc/AxO5PuwPptLVVNXttB6jpEQi3nUfd9 BU/z7gSNYhuhiW8WGDQ9omNOP2e3w6cgXTPJn7DI83ufUUljYHpAAPi+ZT5CiTEmUi8J 9w67kmvT9C0OwUDEqEoY+0am75+AM0PmybaNX9AtPghp6xBDmLMrsMB2ZJHCxUYkJfZp asYpAGtGHA2GPOEbCs8OhPzj1qPiZL3LkoZinD5vfE9cvbj9e59NsiywAYAJVE4lycmQ P4LW/3sdEHgmx5coFTX9wJECbWD+jaWe11InCyuaZ6hjh5Tyi5GTnPEXKQuFfUpczVtq 9vPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686689970; x=1689281970; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hzf4sp0Mbi0CaaHlXXwQFemFEE/XbJHyvZ92xqH1v50=; b=AaCVCkjjl7pNjT39g+SLRG6r7NkT+vrv/2n70V/5wW8/UTv0MU782imac7FrOiaIDl pAVd+5sqzghxRR2q4u48trYqpu0eOutsy++CIJdixU1gwn5vvMzNhCZcasoWRON7+ZHB eZn6GRiPGpGJ6op4U1Y2lEjDmsYnrDWeCuvCSUkUh+YaF8WuXUG2k+vJs0QNq0JAvV7C L8x9b7970KNr5swMvHZ71P4mbZCmXTnS0+xz8fQkNW/gVj062EeEY2+PsEGgzYjfvaVi aJX8dntiTVSnOga5NyvKpDDaJ6df7W6NMqfx4Ms1+ozSea/8ZI7FjihtgRnIUlHFXNvF Kxnw== X-Gm-Message-State: AC+VfDwsYzIraokKZa0kqiHe/8qSmCmji46XIq4a1+2Q02y77PY85Bwe kj4iee0ejt3Tn3rIu2dPQV95GiMWJupYDXNiHU4= X-Google-Smtp-Source: ACHHUZ5c4dmphFLTSvLMwNw9ldq+/2hvPEU+CGJJZ/Sb6GmYX9MIsJdrpjOadUudYqFAPGZQUrZY6w== X-Received: by 2002:a05:6808:1b06:b0:39a:abd1:36f5 with SMTP id bx6-20020a0568081b0600b0039aabd136f5mr10507343oib.31.1686689969895; Tue, 13 Jun 2023 13:59:29 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 05/18] target/riscv/cpu.c: restrict 'marchid' value Date: Tue, 13 Jun 2023 17:58:44 -0300 Message-Id: <20230613205857.495165-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613205857.495165-1-dbarboza@ventanamicro.com> References: <20230613205857.495165-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1686690169189100001 Content-Type: text/plain; charset="utf-8" 'marchid' shouldn't be set to a different value as previously set for named CPUs. For all other CPUs it shouldn't be freely set either - the spec requires that 'marchid' can't have the MSB (most significant bit) set and every other bit set to zero, i.e. 0x80000000 is an invalid 'marchid' value for 32 bit CPUs. As with 'mimpid', setting a default value based on the current QEMU version is not a good idea because it implies that the CPU implementation changes from one QEMU version to the other. Named CPUs should set 'marchid' to a meaningful value instead, and generic CPUs can set to any valid value. For the 'veyron-v1' CPU this is the error thrown if 'marchid' is set to a different val: $ ./build/qemu-system-riscv64 -M virt -nographic -cpu veyron-v1,marchid=3D0= x80000000 qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.marchid=3D0x800= 00000: Unable to change veyron-v1-riscv-cpu marchid (0x8000000000010000) And, for generics CPUs, this is the error when trying to set to an invalid val: $ ./build/qemu-system-riscv64 -M virt -nographic -cpu rv64,marchid=3D0x8000= 000000000000 qemu-system-riscv64: can't apply global rv64-riscv-cpu.marchid=3D0x80000000= 00000000: Unable to set marchid with MSB (64) bit set and the remaining bits zero Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 60 ++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 53 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 39c550682a..2eb793188c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -38,11 +38,6 @@ #include "tcg/tcg.h" =20 /* RISC-V CPU definitions */ - -#define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ - (QEMU_VERSION_MINOR << 8) | \ - (QEMU_VERSION_MICRO)) - static const char riscv_single_letter_exts[] =3D "IEMAFDQCPVH"; =20 struct isa_ext_data { @@ -1733,8 +1728,6 @@ static void riscv_cpu_add_user_properties(Object *obj) static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 - DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID= ), - #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif @@ -1881,6 +1874,56 @@ static void cpu_get_mimpid(Object *obj, Visitor *v, = const char *name, visit_type_bool(v, name, &value, errp); } =20 +static void cpu_set_marchid(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint64_t prev_val =3D cpu->cfg.marchid; + uint64_t value, invalid_val; + uint32_t mxlen =3D 0; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (!dynamic_cpu && prev_val !=3D value) { + error_setg(errp, "Unable to change %s marchid (0x%lx)", + object_get_typename(obj), prev_val); + return; + } + + switch (riscv_cpu_mxl(&cpu->env)) { + case MXL_RV32: + mxlen =3D 32; + break; + case MXL_RV64: + case MXL_RV128: + mxlen =3D 64; + break; + default: + g_assert_not_reached(); + } + + invalid_val =3D 1LL << (mxlen - 1); + + if (value =3D=3D invalid_val) { + error_setg(errp, "Unable to set marchid with MSB (%u) bit set " + "and the remaining bits zero", mxlen); + return; + } + + cpu->cfg.marchid =3D value; +} + +static void cpu_get_marchid(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value =3D RISCV_CPU(obj)->cfg.marchid; + + visit_type_bool(v, name, &value, errp); +} + static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); @@ -1918,6 +1961,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid, cpu_set_mimpid, NULL, NULL); =20 + object_class_property_add(c, "marchid", "uint64", cpu_get_marchid, + cpu_set_marchid, NULL, NULL); + device_class_set_props(dc, riscv_cpu_properties); } =20 --=20 2.40.1 From nobody Sat May 18 15:49:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1686690156; cv=none; d=zohomail.com; s=zohoarc; b=j0yNq+JXCkGpp86CwzpAkK5sdlkLcyDM3F8zbN5QS7D8bb8edU1b8KiFq4tGatpxn3Y4Q8E/SJWf9tTyeHCFLq0+d1bVocZOIHlj7jGCXcLDVUjfs8sd5KmBIeouqGHW/bar2K8D3Y3Ye2jLusIjlN3oKkdi6TgWI/PZe4F2lcM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686690156; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FhHRKSGEbq+mW0830UHFoCdz0qHGycuAYRPV+WamFZQ=; b=IVT5FVTGHqcHNorZ+KWOpuA2b/RR6m/1jbEHkLnmoyShTasMkGvcYZK0p0oeCPU3LXbQrG+U5wd7HUEKCfsNaF7F+ZJLPMlq8VUjadBhDrLtAbVPcgN+/6agg+TxHScVkU1cQnWWzQtvYsohIu0B3JFaqWtyZNYegHOPkmToiq0= ARC-Authentication-Results: i=1; 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([177.170.117.210]) by smtp.gmail.com with ESMTPSA id q82-20020acaf255000000b003982a8a1e3fsm5619514oih.51.2023.06.13.13.59.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 13:59:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686689973; x=1689281973; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FhHRKSGEbq+mW0830UHFoCdz0qHGycuAYRPV+WamFZQ=; b=eMF7JVUyBvh/d7YjOTAPY0z9V+1z4lVqpwgzcnK9mhBMGangZOW08LRZ8wJYP0bGgg 8T1ueY39ldvuon4qcbg76dlOe7TjHMiyO22h9B5vrBO/kwHKwHy5zxDwL756ao/gKfzu U/3WGjOz8IuJTHDdbUTQN8p9h5XBoYhhxR8W1Vc+WzHFu8w+SaYg1vnH9YEbfZQGFcP1 WzkHrdt6nYkLE0vs3vJsJeoCJPYy1reAWEo7fufTIlshf1cFEX4H7VWDFO6ZEAZltFU0 QTuQHzxvOnJ4TXIQ6hBRm32x87MkSNUjpCpc9YQM3FWw4CXvkhV45dLkKV79j7LhQjj7 dflg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686689973; x=1689281973; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FhHRKSGEbq+mW0830UHFoCdz0qHGycuAYRPV+WamFZQ=; b=aY5+U4yE9dIJpaOizYNgRX8vfhLBee3LkQY4VAFBezbgm/LoPUAbF4wNtu1YRPj6up cppbYb/L87kdKc26LjDWOVxJWpzGlXNLi0n8o83hD4B+P5CT2eILFmXBzEZvk9mNFgtc Wo0aw5liTXoAP9g9VrgftXkYyh856ZnJS/kgIEVXSUrPQSnUxD1HgN/gCLJIbvOdGl24 Nuqwbvf9qpiuJ3Ko2pxHustgNWhNazkbUzXMMXmtiRU5VO30f8RCVHxNSOIPJlgEwv5I 6jRZWDgp2vqL2A38chyNtd2Tb5ZLL4DxBPmXGtuYrz3PaKVulVJuUbvmT1J0aLcvuiZX e44w== X-Gm-Message-State: AC+VfDzD/9OCobQW5coIEK7a2DHDGKRgaziE4kdsepUYc0ROcPW9qA+w fqjD1wIWvpYJ92IEVVF58k9oxuPZJ3Bhbrpkh+g= X-Google-Smtp-Source: ACHHUZ5lgt/cmLaYBcN3W0k8gk2ILQ28jRMTaKWqs2Hz7tcyGM0eaTuaVmwokkMEvL7nvJzBmVPOQg== X-Received: by 2002:a05:6808:3020:b0:398:34da:daad with SMTP id ay32-20020a056808302000b0039834dadaadmr9336460oib.51.1686689972803; Tue, 13 Jun 2023 13:59:32 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 06/18] target/riscv: use KVM scratch CPUs to init KVM properties Date: Tue, 13 Jun 2023 17:58:45 -0300 Message-Id: <20230613205857.495165-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613205857.495165-1-dbarboza@ventanamicro.com> References: <20230613205857.495165-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1686690157155100001 Content-Type: text/plain; charset="utf-8" Certain validations, such as the validations done for the machine IDs (mvendorid/marchid/mimpid), are done before starting the CPU. Non-dynamic (named) CPUs tries to match user input with a preset default. As it is today we can't prefetch a KVM default for these cases because we're only able to read/write KVM regs after the vcpu is spinning. Our target/arm friends use a concept called "scratch CPU", which consists of creating a vcpu for doing queries and validations and so on, which is discarded shortly after use [1]. This is a suitable solution for what we need so let's implement it in target/riscv as well. kvm_riscv_init_machine_ids() will be used to do any pre-launch setup for KVM CPUs, via riscv_cpu_add_user_properties(). The function will create a KVM scratch CPU, fetch KVM regs that work as default values for user properties, and then discard the scratch CPU afterwards. We're starting by initializing 'mvendorid'. This concept will be used to init other KVM specific properties in the next patches as well. [1] target/arm/kvm.c, kvm_arm_create_scratch_host_vcpu() Suggested-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Acked-by: Alistair Francis --- target/riscv/cpu.c | 4 ++ target/riscv/kvm.c | 85 ++++++++++++++++++++++++++++++++++++++++ target/riscv/kvm_riscv.h | 1 + 3 files changed, 90 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2eb793188c..0b25d53bbe 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1714,6 +1714,10 @@ static void riscv_cpu_add_user_properties(Object *ob= j) Property *prop; DeviceState *dev =3D DEVICE(obj); =20 + if (riscv_running_kvm()) { + kvm_riscv_init_user_properties(obj); + } + riscv_cpu_add_misa_properties(obj); =20 for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 0f932a5b96..37f0f70794 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -309,6 +309,91 @@ static void kvm_riscv_put_regs_timer(CPUState *cs) env->kvm_timer_dirty =3D false; } =20 +typedef struct KVMScratchCPU { + int kvmfd; + int vmfd; + int cpufd; +} KVMScratchCPU; + +/* + * Heavily inspired by kvm_arm_create_scratch_host_vcpu() + * from target/arm/kvm.c. + */ +static bool kvm_riscv_create_scratch_vcpu(KVMScratchCPU *scratch) +{ + int kvmfd =3D -1, vmfd =3D -1, cpufd =3D -1; + + kvmfd =3D qemu_open_old("/dev/kvm", O_RDWR); + if (kvmfd < 0) { + goto err; + } + do { + vmfd =3D ioctl(kvmfd, KVM_CREATE_VM, 0); + } while (vmfd =3D=3D -1 && errno =3D=3D EINTR); + if (vmfd < 0) { + goto err; + } + cpufd =3D ioctl(vmfd, KVM_CREATE_VCPU, 0); + if (cpufd < 0) { + goto err; + } + + scratch->kvmfd =3D kvmfd; + scratch->vmfd =3D vmfd; + scratch->cpufd =3D cpufd; + + return true; + + err: + if (cpufd >=3D 0) { + close(cpufd); + } + if (vmfd >=3D 0) { + close(vmfd); + } + if (kvmfd >=3D 0) { + close(kvmfd); + } + + return false; +} + +static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch) +{ + close(scratch->cpufd); + close(scratch->vmfd); + close(scratch->kvmfd); +} + +static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcp= u) +{ + CPURISCVState *env =3D &cpu->env; + struct kvm_one_reg reg; + int ret; + + reg.id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, + KVM_REG_RISCV_CONFIG_REG(mvendorid)); + reg.addr =3D (uint64_t)&cpu->cfg.mvendorid; + ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); + if (ret !=3D 0) { + error_report("Unable to retrieve mvendorid from host, error %d", r= et); + } +} + +void kvm_riscv_init_user_properties(Object *cpu_obj) +{ + RISCVCPU *cpu =3D RISCV_CPU(cpu_obj); + KVMScratchCPU kvmcpu; + + if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { + return; + } + + kvm_riscv_init_machine_ids(cpu, &kvmcpu); + + kvm_riscv_destroy_scratch_vcpu(&kvmcpu); +} + const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_LAST_INFO }; diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index ed281bdce0..e3ba935808 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -19,6 +19,7 @@ #ifndef QEMU_KVM_RISCV_H #define QEMU_KVM_RISCV_H =20 +void kvm_riscv_init_user_properties(Object *cpu_obj); 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([177.170.117.210]) by smtp.gmail.com with ESMTPSA id q82-20020acaf255000000b003982a8a1e3fsm5619514oih.51.2023.06.13.13.59.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 13:59:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686689976; x=1689281976; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v8ASDdryGzeW4hp9SEkr1lUwKwLm1J02DfoYsDtoqkc=; b=UjinlDWB3gCmXc1MMpGtcHDA/5FwB5WXZWe+Ei0fDlbYPee+wJgYlYIwGqfmnPXGrg S9nUD2GmW/wejFP4pF3/iAxDEFRzGvhsHSof9WT/slQZMaqyd4kgPAT8VYu0hPpYzEYJ uBshTaksrZ524c0AIGzHu10J2HJlG9OxnFinp6sxM2RwUdzwGg5p1gHGlx7ouYkYd+F4 w1yLw36cOD7Y5loEiZ8PVPTF74aSccskJgmtNSgqhxcHSx2hg/we4qO2y4gCoKWPg1zI y1diS+0XAeu4S+H+vYemV45k1YAoMo5k4R/U/c5cT4k7aypMvMeJ3SU7tYGpaztiBCzi qd4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686689976; x=1689281976; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v8ASDdryGzeW4hp9SEkr1lUwKwLm1J02DfoYsDtoqkc=; b=MLM244Wg0PLoJGHK9F0ATVD6qs6rRvY+Esm7tGfg7aUbclaqdkEJunr4R3V5xA7HvO wJi+KLGZ8vrasoetSi/rCJd2KhDp8aym224z7fYnKTm21HJdB1oW++deS3z1y2KsG0sJ Y1J8LzXBXjlWPo/QV7nUEbVlKg/d4CSa+T/+oS1+40rfjLx9Ti+6M0wP6TerdV6oDG++ hmkd1rCrGSwkWbnWIxOI0Bczv2Ddp8vgyHfkJzY1pPoM4wXlI9RlVTP0OPrIzoAKO5dX po/HAxEzgzF/r08yERuR27zYA/NsBqQgL3IW1/IelmYtKINeb6CFuOCEsyVFM9HLVPl3 Z4kg== X-Gm-Message-State: AC+VfDynDO7C1aTGb9ZHxXIWu/ACJMCEim/Bk1I+pPmjEHJGNpHMfOU9 9Tgn4kQ/YgkbfULFfYer57JKSxHvLYYmJe9TZNU= X-Google-Smtp-Source: ACHHUZ41GFd+nj3Bi9072pQvD6FNFARj+UctTWaJXxiYR1lBp+Iai5ZSkxj0Xkpg9QAeYsG9yBCO1g== X-Received: by 2002:a4a:ead4:0:b0:558:ae64:6533 with SMTP id s20-20020a4aead4000000b00558ae646533mr8663273ooh.8.1686689976037; Tue, 13 Jun 2023 13:59:36 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 07/18] target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids() Date: Tue, 13 Jun 2023 17:58:46 -0300 Message-Id: <20230613205857.495165-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613205857.495165-1-dbarboza@ventanamicro.com> References: <20230613205857.495165-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1686690086755100001 Content-Type: text/plain; charset="utf-8" Allow 'marchid' and 'mimpid' to also be initialized in kvm_riscv_init_machine_ids(). After this change, the handling of mvendorid/marchid/mimpid for the 'host' CPU type will be equal to what we already have for TCG named CPUs, i.e. the user is not able to set these values to a different val than the one that is already preset. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Acked-by: Alistair Francis --- target/riscv/kvm.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 37f0f70794..cd2974c663 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -378,6 +378,22 @@ static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, = KVMScratchCPU *kvmcpu) if (ret !=3D 0) { error_report("Unable to retrieve mvendorid from host, error %d", r= et); } + + reg.id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, + KVM_REG_RISCV_CONFIG_REG(marchid)); + reg.addr =3D (uint64_t)&cpu->cfg.marchid; + ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); + if (ret !=3D 0) { + error_report("Unable to retrieve marchid from host, error %d", ret= ); + } + + reg.id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, + KVM_REG_RISCV_CONFIG_REG(mimpid)); + reg.addr =3D (uint64_t)&cpu->cfg.mimpid; + ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); + if (ret !=3D 0) { + error_report("Unable to retrieve mimpid from host, error %d", ret); + } } =20 void kvm_riscv_init_user_properties(Object *cpu_obj) --=20 2.40.1 From nobody Sat May 18 15:49:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1686690074; cv=none; d=zohomail.com; s=zohoarc; b=oEb7hWtBVPkSG3ZzwiaCwJwZNDPu9IS+rR19sEL/ZpxKrA9C5UgVN2KxhwEeVOSvKts3y8C3PPCqA8Mn8hRaOCxz/XJ4B1jmKXJbomk+JBIDngD6pUcS6OZjO8Pxc0VDAvNUQXq/KNDDxQQLE9CQKS2aeMQtB6TDydi1+S/sX+Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686690074; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Iv3WV4ASh2/ahyZmDoMdg8LOeNDDBGDihd9nx6jCt9Y=; b=KCMj1cC3v2IXtxCzH57WHIHjW0KGseSE5HeOYsaTuMBu2gqOhtCZkLVfE2JVSSeodkcchCLPrF8MNyJogxXEatMZeCJlvdn9wYww/G0UC31Li3df6wlIMzaghOiuzdOfegig7tM1Gll/RvOgAQGKrV4mriJonqrPPTcP1JYrjjY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686690074065253.01572381751623; Tue, 13 Jun 2023 14:01:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9B79-00025s-ID; Tue, 13 Jun 2023 16:59:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9B78-000258-2o for qemu-devel@nongnu.org; Tue, 13 Jun 2023 16:59:42 -0400 Received: from mail-oi1-x233.google.com ([2607:f8b0:4864:20::233]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q9B76-0006ji-JP for qemu-devel@nongnu.org; Tue, 13 Jun 2023 16:59:41 -0400 Received: by mail-oi1-x233.google.com with SMTP id 5614622812f47-39caf0082f3so3091596b6e.3 for ; Tue, 13 Jun 2023 13:59:40 -0700 (PDT) Received: from grind.. ([177.170.117.210]) by smtp.gmail.com with ESMTPSA id q82-20020acaf255000000b003982a8a1e3fsm5619514oih.51.2023.06.13.13.59.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 13:59:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686689979; x=1689281979; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Iv3WV4ASh2/ahyZmDoMdg8LOeNDDBGDihd9nx6jCt9Y=; b=DNnaJJila+09lZzGsNJPuMmK47ygXH0IaFKC+A9MFBMYyEiHr+jo5iC+9HQ4df0eDx hjKspODqUjbLM1QZuazPKA65UhQPOkkJMudv5PtmHQwfKUrzwfg4RXcKSvqUVx+XvGkO 9YfoLJjZZezb/FQ/vm82NiZYHNG1TJaExHCSj48JBv3o2XTPmDiHXAGZddn9XXfbnvsq L706AUSZSIObf4k7TK8muF54GupsOUQHC9MA4F3nTo/Vn0SfWXrNOHd2vCbp6npIbeRM pEBqvZlQ8bvQietiiwnkPo5r5K5J4IKKmjtmI011OzU+3FjGdupCI62LtTt5ls6DYdgh wFoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686689979; x=1689281979; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Iv3WV4ASh2/ahyZmDoMdg8LOeNDDBGDihd9nx6jCt9Y=; b=Q7TsCtfwjkgK21a/9ZMkhPXLR4K3N3/dB1JxlOOCUeri5l0KhYe9avWiasHl4QB1I0 0EtJXq9Az/vzFfgde02/jo76CC+CAU/Np5dPqVsLhF3wk9GtSqFFWrRfhY3JeqxHcTsB EzZnSyhyPKjOQc5WBUB1aGQP0uXJHhVNJGYqht9/kqyiWNOk/Ap+j1ZvC1nE+h6L5qgQ CN2B9RbJadK3N4IH/dFt4QIncOKt4nBDaXJU7yQO8Tydx4eJ/Dgew3lx8cBQJ4wVnZVz RyQqhosrunfVMNdHPNYE6SIQfLE5As3isYw5K3c/dBmzv/mi3O/RlZtH/ZbubYxyX1T8 rArA== X-Gm-Message-State: AC+VfDyfofpSYIdz6hUKV7mQbALSU4YVZRTsNUKQDMQOxy4XTtxMBjkF jXoUSttFP36YPNTmvcNINgOadM8s1s2wk/+nhxg= X-Google-Smtp-Source: ACHHUZ7fIvReVkhNEuxlnmn13lH9NWMLwu481prR1cQChdhfcO1BNrYa6vdlEs1CPzpfqWqJtXFoSA== X-Received: by 2002:a54:4588:0:b0:39a:b77b:b43b with SMTP id z8-20020a544588000000b0039ab77bb43bmr7881536oib.55.1686689978959; Tue, 13 Jun 2023 13:59:38 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 08/18] target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs Date: Tue, 13 Jun 2023 17:58:47 -0300 Message-Id: <20230613205857.495165-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613205857.495165-1-dbarboza@ventanamicro.com> References: <20230613205857.495165-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1686690074728100001 Content-Type: text/plain; charset="utf-8" After changing user validation for mvendorid/marchid/mimpid to guarantee that the value is validated on user input time, coupled with the work in fetching KVM default values for them by using a scratch CPU, we're certain that the values in cpu->cfg.(mvendorid|marchid|mimpid) are already good to be written back to KVM. There's no need to write the values back for 'host' type CPUs since the values can't be changed, so let's do that just for generic CPUs. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Acked-by: Alistair Francis --- target/riscv/kvm.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index cd2974c663..602727cdfd 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -495,6 +495,33 @@ void kvm_arch_init_irq_routing(KVMState *s) { } =20 +static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) +{ + CPURISCVState *env =3D &cpu->env; + uint64_t id; + int ret; + + id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, + KVM_REG_RISCV_CONFIG_REG(mvendorid)); + ret =3D kvm_set_one_reg(cs, id, &cpu->cfg.mvendorid); + if (ret !=3D 0) { + return ret; + } + + id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, + KVM_REG_RISCV_CONFIG_REG(marchid)); + ret =3D kvm_set_one_reg(cs, id, &cpu->cfg.marchid); + if (ret !=3D 0) { + return ret; + } + + id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, + KVM_REG_RISCV_CONFIG_REG(mimpid)); + ret =3D kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); + + return ret; +} + int kvm_arch_init_vcpu(CPUState *cs) { int ret =3D 0; @@ -513,6 +540,10 @@ int kvm_arch_init_vcpu(CPUState *cs) } env->misa_ext =3D isa; =20 + if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { + ret =3D kvm_vcpu_set_machine_ids(cpu, cs); + } + return ret; } =20 --=20 2.40.1 From nobody Sat May 18 15:49:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1686690068; cv=none; d=zohomail.com; s=zohoarc; b=fpTe2g1uJ+xTYFASyYHV+0aHP0De076A4M2YhkeEnY+l2guBbRcNtT3aEgzgxgNPIJcE+6rDQWQAxKPQWP3SkN7VSvHPI/fPWkj6e0hagrGJT//Q2Cq6ZzMZG3tdH+W4/T9Xp1GvTtzqtFEkj9ARf4m2EWcpQYeQUA6bqVBcOHs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686690068; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7BFCfo0HGKkFmJVQPVF5IuVIhGV9LkXg0Cc3rc8YZxU=; b=dUL6Dg6kTlhgstLsLj5DYMBiNdOpsS0JIGMMll1PC3b71PRK0bhIhlLaZyHdvbkBu7YTKyAWv0kMRYhCy0VSj8oNopGwwXzmKCvYbRXs/lsywQXYWGhqYaWeJ1ulTHCxmgzswZiPkyLUhFCfMxrLkwgcJRcroiZV9K8qpHLOtVI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686690068606250.29366102669303; Tue, 13 Jun 2023 14:01:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9B7D-00026n-Ua; Tue, 13 Jun 2023 16:59:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9B7C-000265-4m for qemu-devel@nongnu.org; Tue, 13 Jun 2023 16:59:46 -0400 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q9B79-0006kG-NG for qemu-devel@nongnu.org; Tue, 13 Jun 2023 16:59:45 -0400 Received: by mail-oi1-x22b.google.com with SMTP id 5614622812f47-39c77cf32deso3305529b6e.0 for ; Tue, 13 Jun 2023 13:59:43 -0700 (PDT) Received: from grind.. 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Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- include/standard-headers/linux/const.h | 2 +- include/standard-headers/linux/virtio_blk.h | 18 +++---- .../standard-headers/linux/virtio_config.h | 6 +++ include/standard-headers/linux/virtio_net.h | 1 + linux-headers/asm-arm64/kvm.h | 33 ++++++++++++ linux-headers/asm-riscv/kvm.h | 53 ++++++++++++++++++- linux-headers/asm-riscv/unistd.h | 9 ++++ linux-headers/asm-s390/unistd_32.h | 1 + linux-headers/asm-s390/unistd_64.h | 1 + linux-headers/asm-x86/kvm.h | 3 ++ linux-headers/linux/const.h | 2 +- linux-headers/linux/kvm.h | 12 +++-- linux-headers/linux/psp-sev.h | 7 +++ linux-headers/linux/userfaultfd.h | 17 +++++- 14 files changed, 149 insertions(+), 16 deletions(-) diff --git a/include/standard-headers/linux/const.h b/include/standard-head= ers/linux/const.h index 5e48987251..1eb84b5087 100644 --- a/include/standard-headers/linux/const.h +++ b/include/standard-headers/linux/const.h @@ -28,7 +28,7 @@ #define _BITUL(x) (_UL(1) << (x)) #define _BITULL(x) (_ULL(1) << (x)) =20 -#define __ALIGN_KERNEL(x, a) __ALIGN_KERNEL_MASK(x, (typeof(x))(a) - 1) +#define __ALIGN_KERNEL(x, a) __ALIGN_KERNEL_MASK(x, (__typeof__(x))(a) - = 1) #define __ALIGN_KERNEL_MASK(x, mask) (((x) + (mask)) & ~(mask)) =20 #define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) diff --git a/include/standard-headers/linux/virtio_blk.h b/include/standard= -headers/linux/virtio_blk.h index 7155b1a470..d7be3cf5e4 100644 --- a/include/standard-headers/linux/virtio_blk.h +++ b/include/standard-headers/linux/virtio_blk.h @@ -138,11 +138,11 @@ struct virtio_blk_config { =20 /* Zoned block device characteristics (if VIRTIO_BLK_F_ZONED) */ struct virtio_blk_zoned_characteristics { - uint32_t zone_sectors; - uint32_t max_open_zones; - uint32_t max_active_zones; - uint32_t max_append_sectors; - uint32_t write_granularity; + __virtio32 zone_sectors; + __virtio32 max_open_zones; + __virtio32 max_active_zones; + __virtio32 max_append_sectors; + __virtio32 write_granularity; uint8_t model; uint8_t unused2[3]; } zoned; @@ -239,11 +239,11 @@ struct virtio_blk_outhdr { */ struct virtio_blk_zone_descriptor { /* Zone capacity */ - uint64_t z_cap; + __virtio64 z_cap; /* The starting sector of the zone */ - uint64_t z_start; + __virtio64 z_start; /* Zone write pointer position in sectors */ - uint64_t z_wp; + __virtio64 z_wp; /* Zone type */ uint8_t z_type; /* Zone state */ @@ -252,7 +252,7 @@ struct virtio_blk_zone_descriptor { }; =20 struct virtio_blk_zone_report { - uint64_t nr_zones; + __virtio64 nr_zones; uint8_t reserved[56]; struct virtio_blk_zone_descriptor zones[]; }; diff --git a/include/standard-headers/linux/virtio_config.h b/include/stand= ard-headers/linux/virtio_config.h index 965ee6ae23..8a7d0dc8b0 100644 --- a/include/standard-headers/linux/virtio_config.h +++ b/include/standard-headers/linux/virtio_config.h @@ -97,6 +97,12 @@ */ #define VIRTIO_F_SR_IOV 37 =20 +/* + * This feature indicates that the driver passes extra data (besides + * identifying the virtqueue) in its device notifications. + */ +#define VIRTIO_F_NOTIFICATION_DATA 38 + /* * This feature indicates that the driver can reset a queue individually. */ diff --git a/include/standard-headers/linux/virtio_net.h b/include/standard= -headers/linux/virtio_net.h index c0e797067a..2325485f2c 100644 --- a/include/standard-headers/linux/virtio_net.h +++ b/include/standard-headers/linux/virtio_net.h @@ -61,6 +61,7 @@ #define VIRTIO_NET_F_GUEST_USO6 55 /* Guest can handle USOv6 in. */ #define VIRTIO_NET_F_HOST_USO 56 /* Host can handle USO in. */ #define VIRTIO_NET_F_HASH_REPORT 57 /* Supports hash report */ +#define VIRTIO_NET_F_GUEST_HDRLEN 59 /* Guest provides the exact hdr_len = value. */ #define VIRTIO_NET_F_RSS 60 /* Supports RSS RX steering */ #define VIRTIO_NET_F_RSC_EXT 61 /* extended coalescing info */ #define VIRTIO_NET_F_STANDBY 62 /* Act as standby for another device diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h index d7e7bb885e..38e5957526 100644 --- a/linux-headers/asm-arm64/kvm.h +++ b/linux-headers/asm-arm64/kvm.h @@ -198,6 +198,15 @@ struct kvm_arm_copy_mte_tags { __u64 reserved[2]; }; =20 +/* + * Counter/Timer offset structure. Describe the virtual/physical offset. + * To be used with KVM_ARM_SET_COUNTER_OFFSET. + */ +struct kvm_arm_counter_offset { + __u64 counter_offset; + __u64 reserved; +}; + #define KVM_ARM_TAGS_TO_GUEST 0 #define KVM_ARM_TAGS_FROM_GUEST 1 =20 @@ -363,6 +372,10 @@ enum { KVM_REG_ARM_VENDOR_HYP_BIT_PTP =3D 1, }; =20 +/* Device Control API on vm fd */ +#define KVM_ARM_VM_SMCCC_CTRL 0 +#define KVM_ARM_VM_SMCCC_FILTER 0 + /* Device Control API: ARM VGIC */ #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 @@ -402,6 +415,8 @@ enum { #define KVM_ARM_VCPU_TIMER_CTRL 1 #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 +#define KVM_ARM_VCPU_TIMER_IRQ_HVTIMER 2 +#define KVM_ARM_VCPU_TIMER_IRQ_HPTIMER 3 #define KVM_ARM_VCPU_PVTIME_CTRL 2 #define KVM_ARM_VCPU_PVTIME_IPA 0 =20 @@ -458,6 +473,24 @@ enum { /* run->fail_entry.hardware_entry_failure_reason codes. */ #define KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED (1ULL << 0) =20 +enum kvm_smccc_filter_action { + KVM_SMCCC_FILTER_HANDLE =3D 0, + KVM_SMCCC_FILTER_DENY, + KVM_SMCCC_FILTER_FWD_TO_USER, + +}; + +struct kvm_smccc_filter { + __u32 base; + __u32 nr_functions; + __u8 action; + __u8 pad[15]; +}; + +/* arm64-specific KVM_EXIT_HYPERCALL flags */ +#define KVM_HYPERCALL_EXIT_SMC (1U << 0) +#define KVM_HYPERCALL_EXIT_16BIT (1U << 1) + #endif =20 #endif /* __ARM_KVM_H__ */ diff --git a/linux-headers/asm-riscv/kvm.h b/linux-headers/asm-riscv/kvm.h index 92af6f3f05..f92790c948 100644 --- a/linux-headers/asm-riscv/kvm.h +++ b/linux-headers/asm-riscv/kvm.h @@ -12,6 +12,7 @@ #ifndef __ASSEMBLY__ =20 #include +#include #include =20 #define __KVM_HAVE_READONLY_MEM @@ -52,6 +53,7 @@ struct kvm_riscv_config { unsigned long mvendorid; unsigned long marchid; unsigned long mimpid; + unsigned long zicboz_block_size; }; =20 /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ @@ -64,7 +66,7 @@ struct kvm_riscv_core { #define KVM_RISCV_MODE_S 1 #define KVM_RISCV_MODE_U 0 =20 -/* CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ +/* General CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ struct kvm_riscv_csr { unsigned long sstatus; unsigned long sie; @@ -78,6 +80,17 @@ struct kvm_riscv_csr { unsigned long scounteren; }; =20 +/* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ +struct kvm_riscv_aia_csr { + unsigned long siselect; + unsigned long iprio1; + unsigned long iprio2; + unsigned long sieh; + unsigned long siph; + unsigned long iprio1h; + unsigned long iprio2h; +}; + /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ struct kvm_riscv_timer { __u64 frequency; @@ -105,9 +118,29 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_SVINVAL, KVM_RISCV_ISA_EXT_ZIHINTPAUSE, KVM_RISCV_ISA_EXT_ZICBOM, + KVM_RISCV_ISA_EXT_ZICBOZ, + KVM_RISCV_ISA_EXT_ZBB, + KVM_RISCV_ISA_EXT_SSAIA, KVM_RISCV_ISA_EXT_MAX, }; =20 +/* + * SBI extension IDs specific to KVM. This is not the same as the SBI + * extension IDs defined by the RISC-V SBI specification. + */ +enum KVM_RISCV_SBI_EXT_ID { + KVM_RISCV_SBI_EXT_V01 =3D 0, + KVM_RISCV_SBI_EXT_TIME, + KVM_RISCV_SBI_EXT_IPI, + KVM_RISCV_SBI_EXT_RFENCE, + KVM_RISCV_SBI_EXT_SRST, + KVM_RISCV_SBI_EXT_HSM, + KVM_RISCV_SBI_EXT_PMU, + KVM_RISCV_SBI_EXT_EXPERIMENTAL, + KVM_RISCV_SBI_EXT_VENDOR, + KVM_RISCV_SBI_EXT_MAX, +}; + /* Possible states for kvm_riscv_timer */ #define KVM_RISCV_TIMER_STATE_OFF 0 #define KVM_RISCV_TIMER_STATE_ON 1 @@ -118,6 +151,8 @@ enum KVM_RISCV_ISA_EXT_ID { /* If you need to interpret the index values, here is the key: */ #define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000 #define KVM_REG_RISCV_TYPE_SHIFT 24 +#define KVM_REG_RISCV_SUBTYPE_MASK 0x0000000000FF0000 +#define KVM_REG_RISCV_SUBTYPE_SHIFT 16 =20 /* Config registers are mapped as type 1 */ #define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT) @@ -131,8 +166,12 @@ enum KVM_RISCV_ISA_EXT_ID { =20 /* Control and status registers are mapped as type 3 */ #define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT) +#define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) +#define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) #define KVM_REG_RISCV_CSR_REG(name) \ (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long)) +#define KVM_REG_RISCV_CSR_AIA_REG(name) \ + (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long)) =20 /* Timer registers are mapped as type 4 */ #define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT) @@ -152,6 +191,18 @@ enum KVM_RISCV_ISA_EXT_ID { /* ISA Extension registers are mapped as type 7 */ #define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT) =20 +/* SBI extension registers are mapped as type 8 */ +#define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT) +#define KVM_REG_RISCV_SBI_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) +#define KVM_REG_RISCV_SBI_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) +#define KVM_REG_RISCV_SBI_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) +#define KVM_REG_RISCV_SBI_MULTI_REG(__ext_id) \ + ((__ext_id) / __BITS_PER_LONG) +#define KVM_REG_RISCV_SBI_MULTI_MASK(__ext_id) \ + (1UL << ((__ext_id) % __BITS_PER_LONG)) +#define KVM_REG_RISCV_SBI_MULTI_REG_LAST \ + KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1) + #endif =20 #endif /* __LINUX_KVM_RISCV_H */ diff --git a/linux-headers/asm-riscv/unistd.h b/linux-headers/asm-riscv/uni= std.h index 73d7cdd2ec..950ab3fd44 100644 --- a/linux-headers/asm-riscv/unistd.h +++ b/linux-headers/asm-riscv/unistd.h @@ -43,3 +43,12 @@ #define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15) #endif __SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache) + +/* + * Allows userspace to query the kernel for CPU architecture and + * microarchitecture details across a given set of CPUs. + */ +#ifndef __NR_riscv_hwprobe +#define __NR_riscv_hwprobe (__NR_arch_specific_syscall + 14) +#endif +__SYSCALL(__NR_riscv_hwprobe, sys_riscv_hwprobe) diff --git a/linux-headers/asm-s390/unistd_32.h b/linux-headers/asm-s390/un= istd_32.h index 8e644d65f5..800f3adb20 100644 --- a/linux-headers/asm-s390/unistd_32.h +++ b/linux-headers/asm-s390/unistd_32.h @@ -419,6 +419,7 @@ #define __NR_landlock_create_ruleset 444 #define __NR_landlock_add_rule 445 #define __NR_landlock_restrict_self 446 +#define __NR_memfd_secret 447 #define __NR_process_mrelease 448 #define __NR_futex_waitv 449 #define __NR_set_mempolicy_home_node 450 diff --git a/linux-headers/asm-s390/unistd_64.h b/linux-headers/asm-s390/un= istd_64.h index 51da542fec..399a605901 100644 --- a/linux-headers/asm-s390/unistd_64.h +++ b/linux-headers/asm-s390/unistd_64.h @@ -367,6 +367,7 @@ #define __NR_landlock_create_ruleset 444 #define __NR_landlock_add_rule 445 #define __NR_landlock_restrict_self 446 +#define __NR_memfd_secret 447 #define __NR_process_mrelease 448 #define __NR_futex_waitv 449 #define __NR_set_mempolicy_home_node 450 diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h index 2937e7bf69..2b3a8f7bd2 100644 --- a/linux-headers/asm-x86/kvm.h +++ b/linux-headers/asm-x86/kvm.h @@ -557,4 +557,7 @@ struct kvm_pmu_event_filter { #define KVM_VCPU_TSC_CTRL 0 /* control group for the timestamp counter (TS= C) */ #define KVM_VCPU_TSC_OFFSET 0 /* attribute for the TSC offset */ =20 +/* x86-specific KVM_EXIT_HYPERCALL flags. */ +#define KVM_EXIT_HYPERCALL_LONG_MODE BIT(0) + #endif /* _ASM_X86_KVM_H */ diff --git a/linux-headers/linux/const.h b/linux-headers/linux/const.h index 5e48987251..1eb84b5087 100644 --- a/linux-headers/linux/const.h +++ b/linux-headers/linux/const.h @@ -28,7 +28,7 @@ #define _BITUL(x) (_UL(1) << (x)) #define _BITULL(x) (_ULL(1) << (x)) =20 -#define __ALIGN_KERNEL(x, a) __ALIGN_KERNEL_MASK(x, (typeof(x))(a) - 1) +#define __ALIGN_KERNEL(x, a) __ALIGN_KERNEL_MASK(x, (__typeof__(x))(a) - = 1) #define __ALIGN_KERNEL_MASK(x, mask) (((x) + (mask)) & ~(mask)) =20 #define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index 599de3c6e3..65b145b317 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -341,8 +341,11 @@ struct kvm_run { __u64 nr; __u64 args[6]; __u64 ret; - __u32 longmode; - __u32 pad; + + union { + __u32 longmode; + __u64 flags; + }; } hypercall; /* KVM_EXIT_TPR_ACCESS */ struct { @@ -1182,6 +1185,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_S390_PROTECTED_ASYNC_DISABLE 224 #define KVM_CAP_DIRTY_LOG_RING_WITH_BITMAP 225 #define KVM_CAP_PMU_EVENT_MASKED_EVENTS 226 +#define KVM_CAP_COUNTER_OFFSET 227 =20 #ifdef KVM_CAP_IRQ_ROUTING =20 @@ -1449,7 +1453,7 @@ struct kvm_vfio_spapr_tce { #define KVM_CREATE_VCPU _IO(KVMIO, 0x41) #define KVM_GET_DIRTY_LOG _IOW(KVMIO, 0x42, struct kvm_dirty_log) #define KVM_SET_NR_MMU_PAGES _IO(KVMIO, 0x44) -#define KVM_GET_NR_MMU_PAGES _IO(KVMIO, 0x45) +#define KVM_GET_NR_MMU_PAGES _IO(KVMIO, 0x45) /* deprecated */ #define KVM_SET_USER_MEMORY_REGION _IOW(KVMIO, 0x46, \ struct kvm_userspace_memory_region) #define KVM_SET_TSS_ADDR _IO(KVMIO, 0x47) @@ -1541,6 +1545,8 @@ struct kvm_s390_ucas_mapping { #define KVM_SET_PMU_EVENT_FILTER _IOW(KVMIO, 0xb2, struct kvm_pmu_event_= filter) #define KVM_PPC_SVM_OFF _IO(KVMIO, 0xb3) #define KVM_ARM_MTE_COPY_TAGS _IOR(KVMIO, 0xb4, struct kvm_arm_copy_mte= _tags) +/* Available with KVM_CAP_COUNTER_OFFSET */ +#define KVM_ARM_SET_COUNTER_OFFSET _IOW(KVMIO, 0xb5, struct kvm_arm_count= er_offset) =20 /* ioctl for vm fd */ #define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device) diff --git a/linux-headers/linux/psp-sev.h b/linux-headers/linux/psp-sev.h index 51d8b3940e..12ccb70099 100644 --- a/linux-headers/linux/psp-sev.h +++ b/linux-headers/linux/psp-sev.h @@ -36,6 +36,13 @@ enum { * SEV Firmware status code */ typedef enum { + /* + * This error code is not in the SEV spec. Its purpose is to convey that + * there was an error that prevented the SEV firmware from being called. + * The SEV API error codes are 16 bits, so the -1 value will not overlap + * with possible values from the specification. + */ + SEV_RET_NO_FW_CALL =3D -1, SEV_RET_SUCCESS =3D 0, SEV_RET_INVALID_PLATFORM_STATE, SEV_RET_INVALID_GUEST_STATE, diff --git a/linux-headers/linux/userfaultfd.h b/linux-headers/linux/userfa= ultfd.h index ba5d0df52f..14e402263a 100644 --- a/linux-headers/linux/userfaultfd.h +++ b/linux-headers/linux/userfaultfd.h @@ -38,7 +38,8 @@ UFFD_FEATURE_MINOR_HUGETLBFS | \ UFFD_FEATURE_MINOR_SHMEM | \ UFFD_FEATURE_EXACT_ADDRESS | \ - UFFD_FEATURE_WP_HUGETLBFS_SHMEM) + UFFD_FEATURE_WP_HUGETLBFS_SHMEM | \ + UFFD_FEATURE_WP_UNPOPULATED) #define UFFD_API_IOCTLS \ ((__u64)1 << _UFFDIO_REGISTER | \ (__u64)1 << _UFFDIO_UNREGISTER | \ @@ -203,6 +204,12 @@ struct uffdio_api { * * UFFD_FEATURE_WP_HUGETLBFS_SHMEM indicates that userfaultfd * write-protection mode is supported on both shmem and hugetlbfs. + * + * UFFD_FEATURE_WP_UNPOPULATED indicates that userfaultfd + * write-protection mode will always apply to unpopulated pages + * (i.e. empty ptes). This will be the default behavior for shmem + * & hugetlbfs, so this flag only affects anonymous memory behavior + * when userfault write-protection mode is registered. */ #define UFFD_FEATURE_PAGEFAULT_FLAG_WP (1<<0) #define UFFD_FEATURE_EVENT_FORK (1<<1) @@ -217,6 +224,7 @@ struct uffdio_api { #define UFFD_FEATURE_MINOR_SHMEM (1<<10) #define UFFD_FEATURE_EXACT_ADDRESS (1<<11) #define UFFD_FEATURE_WP_HUGETLBFS_SHMEM (1<<12) +#define UFFD_FEATURE_WP_UNPOPULATED (1<<13) __u64 features; =20 __u64 ioctls; @@ -297,6 +305,13 @@ struct uffdio_writeprotect { struct uffdio_continue { struct uffdio_range range; #define UFFDIO_CONTINUE_MODE_DONTWAKE ((__u64)1<<0) + /* + * UFFDIO_CONTINUE_MODE_WP will map the page write protected on + * the fly. UFFDIO_CONTINUE_MODE_WP is available only if the + * write protected ioctl is implemented for the range + * according to the uffdio_register.ioctls. + */ +#define UFFDIO_CONTINUE_MODE_WP ((__u64)1<<1) __u64 mode; =20 /* --=20 2.40.1 From nobody Sat May 18 15:49:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1686690065; cv=none; d=zohomail.com; s=zohoarc; b=RaSRwowaHrPHnngJAITfDOqSZb8N5wpSpPWP3Dw0cE535uQObhoqmZtcS2j1h9v60SgwXkWCQ5Gl97Au1dnyjA24KY6DdEE09bvQOY/tRky/EDNJ6MHT0HGVottcloeRsELnjNkc5lTFRwkReLoZKWODmvFFiut80La5zULpzZ0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686690065; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6y8l+qgZYKHF40Q3lIRPCdTWnb4sLgxntQ7wIOvnirE=; b=kkpvaGJESilD3y7IKuHBfwpsswXSx5oZ5soHxyTsxaWs2zFKeu8NFJF3z74xJmJkjPO3X9ul/fDOm4ex1jX9f1innozplDxj4b7FwMPmPOjtIjBQzxTrGZqfyNmKq4UBNIcWhIVjy744ZxNIuY48FsoSnpbUF1eepg6Kzo660ks= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686690065960917.1821133775604; Tue, 13 Jun 2023 14:01:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9B7H-00027G-It; Tue, 13 Jun 2023 16:59:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9B7G-00026v-7g for qemu-devel@nongnu.org; Tue, 13 Jun 2023 16:59:50 -0400 Received: from mail-oo1-xc36.google.com ([2607:f8b0:4864:20::c36]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q9B7C-0006kj-GA for qemu-devel@nongnu.org; Tue, 13 Jun 2023 16:59:49 -0400 Received: by mail-oo1-xc36.google.com with SMTP id 006d021491bc7-5556e2bddf9so8904eaf.1 for ; Tue, 13 Jun 2023 13:59:46 -0700 (PDT) Received: from grind.. ([177.170.117.210]) by smtp.gmail.com with ESMTPSA id q82-20020acaf255000000b003982a8a1e3fsm5619514oih.51.2023.06.13.13.59.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 13:59:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686689985; x=1689281985; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6y8l+qgZYKHF40Q3lIRPCdTWnb4sLgxntQ7wIOvnirE=; b=IKzJJ9XEqTKFlnygBBaE9cUrhzRwhbe5KqXKmdQZFHFQ3n1QvF1ZVkpCyfOSB00mAK lcrKyT/i3Vi3gnyVtEYQA7g06We3gsokoLF2egouuKoWo0rdcWpVBVjnMmEjfDcjRR/b eNU0UIbY5rLjyPzzle1mTbC03/WBVn8WQKrb/BNogbL8O0hZxsWmmb0qatDTfN0chYTg GvL4rV3eOz5YI8gCPSer3TNkwvhJtU56tUGZy4xAS//ASVKMVucoloM1X0SFelak7HvF 7mofJPLSpW6rjjxnqVcTjjjP0HbdjwTmiRN5AFV2Dq6FDOFR9kbQRkcr5O+O2YKLOSbg nzVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686689985; x=1689281985; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6y8l+qgZYKHF40Q3lIRPCdTWnb4sLgxntQ7wIOvnirE=; b=B9KicuOPuQ8uznx/DvSnxDp7r9gwfe2F08B0ES2g5PWyKf0KtS5fUaU1kpauyu0eYD dt/WfmzMxuiYMzwlSQTfcAAuzx2PJHyJl1GwCHkrnesR/uOVW2FdZ+LbwHsmq7kfGSQa bvDymCUMfgd7le5DHauLkrmy2Bl/cUfHlPyhwTgFHpDAzbyvS/uOiYOeuZcu7f8SKVY4 VZ7jrl1UUpDEHbnhVkohlz7bqZPn4rKy2PgWlZvdQeTEeXsiU7j3btVtgTU+FReZ7tad kZR3jtbz4hnEQj98iQj+CqQlgoN+yQfVZ4f4bIoF5fjJ9ocpI6p60BSbJ7eRzu3lNboU 16Ug== X-Gm-Message-State: AC+VfDyFselejjXEJhk+JG4vk7JSdDWkLFGd/LY7YcT243DtlzZ6/S1q PF7YV1Ux+Kr6atkB8cv/fGhrhoIy5ti5toWjo9A= X-Google-Smtp-Source: ACHHUZ4pORLxgdOhoUvOiCG73HcN3OEBtriGjJOzpGeIa2dxHJrc6RDtpyZDl5DxdLqJ6iyJFE+tIQ== X-Received: by 2002:a05:6808:158c:b0:397:f94e:4321 with SMTP id t12-20020a056808158c00b00397f94e4321mr9880625oiw.23.1686689984878; Tue, 13 Jun 2023 13:59:44 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 10/18] target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU Date: Tue, 13 Jun 2023 17:58:49 -0300 Message-Id: <20230613205857.495165-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613205857.495165-1-dbarboza@ventanamicro.com> References: <20230613205857.495165-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1686690066858100001 Content-Type: text/plain; charset="utf-8" At this moment we're retrieving env->misa_ext during kvm_arch_init_cpu(), leaving env->misa_ext_mask behind. We want to set env->misa_ext_mask, and we want to set it as early as possible. The reason is that we're going to use it in the validation process of the KVM MISA properties we're going to add next. Setting it during arch_init_cpu() is too late for user validation. Move the code to a new helper that is going to be called during init() time, via kvm_riscv_init_user_properties(), like we're already doing for the machine ID properties. Set both misa_ext and misa_ext_mask to the same value retrieved by the 'isa' config reg. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Acked-by: Alistair Francis --- target/riscv/kvm.c | 34 +++++++++++++++++++++++----------- 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 602727cdfd..4d0808cb9a 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -396,6 +396,28 @@ static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, = KVMScratchCPU *kvmcpu) } } =20 +static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, + KVMScratchCPU *kvmcpu) +{ + CPURISCVState *env =3D &cpu->env; + struct kvm_one_reg reg; + int ret; + + reg.id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, + KVM_REG_RISCV_CONFIG_REG(isa)); + reg.addr =3D (uint64_t)&env->misa_ext_mask; + ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); + + if (ret) { + error_report("Unable to fetch ISA register from KVM, " + "error %d", ret); + kvm_riscv_destroy_scratch_vcpu(kvmcpu); + exit(EXIT_FAILURE); + } + + env->misa_ext =3D env->misa_ext_mask; +} + void kvm_riscv_init_user_properties(Object *cpu_obj) { RISCVCPU *cpu =3D RISCV_CPU(cpu_obj); @@ -406,6 +428,7 @@ void kvm_riscv_init_user_properties(Object *cpu_obj) } =20 kvm_riscv_init_machine_ids(cpu, &kvmcpu); + kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); =20 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); } @@ -525,21 +548,10 @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CP= UState *cs) int kvm_arch_init_vcpu(CPUState *cs) { int ret =3D 0; - target_ulong isa; RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - uint64_t id; =20 qemu_add_vm_change_state_handler(kvm_riscv_vm_state_change, cs); =20 - id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, - KVM_REG_RISCV_CONFIG_REG(isa)); - ret =3D kvm_get_one_reg(cs, id, &isa); - if (ret) { - return ret; - } - env->misa_ext =3D isa; - if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { ret =3D kvm_vcpu_set_machine_ids(cpu, cs); } --=20 2.40.1 From nobody Sat May 18 15:49:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1686690192; cv=none; d=zohomail.com; s=zohoarc; b=frx0LbDFl3Kf/ZOee0Fv0TQCPR0ijpsPk8/H4g+V+6B6RXXL96uToq29ZK7lWl7zB7a3daHXQGYKt5Sfd2MySF4WL69npRU4fhTEjVdP6La6id5dS1YXx74hfJHotxq669JuI3UXWY3ewK/+ru9CCXK1rXMlUKVM+Y6z4ytngIk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686690192; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6dm9P/uUTs4MZ/sIEWKFivbNK7+MeEV1c5lZeWHAirE=; b=GYHTnES1MJWdQ2F847BdlJ2PLON1gWZlr3aBszFQ6bNgfO2GIddjwpwNvXg+nXra0gqJz936Tgt+YHFHIAPsY+1ITFbBtg8DP/gM7gi1vLqciKooEYKWm1zfbPOaAXWJO+YiUAOxq7jBui1aeGpOnq0spKrlX4FE9iiYTLxrIGA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686690192677196.45111372315876; Tue, 13 Jun 2023 14:03:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9B7L-00028U-7s; Tue, 13 Jun 2023 16:59:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9B7H-00027n-QD for qemu-devel@nongnu.org; Tue, 13 Jun 2023 16:59:52 -0400 Received: from mail-oi1-x232.google.com ([2607:f8b0:4864:20::232]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q9B7F-0006lW-V9 for qemu-devel@nongnu.org; Tue, 13 Jun 2023 16:59:51 -0400 Received: by mail-oi1-x232.google.com with SMTP id 5614622812f47-39cd0c3e8deso2132443b6e.1 for ; Tue, 13 Jun 2023 13:59:49 -0700 (PDT) Received: from grind.. ([177.170.117.210]) by smtp.gmail.com with ESMTPSA id q82-20020acaf255000000b003982a8a1e3fsm5619514oih.51.2023.06.13.13.59.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 13:59:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686689988; x=1689281988; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6dm9P/uUTs4MZ/sIEWKFivbNK7+MeEV1c5lZeWHAirE=; b=my29xTiGSZ0o+EDUbInF1MH+oXijkbRVJ6n3GTkyGoDM00AEqJjlUGSlXNueWWgCUh e7xCu87/0uYKruSWA8kpH7+Z95Cw+2Km57CPG8fEW432MgbQLWdvl/KUmiR1NUWmScQn wgETCm1r1tI1TRHuv2eAKatfztK8MQZvMVSpa76zclFLSfHweRr8djVXJTZX+dibIuB+ BLqXSJuKmS8SiWf9tdtxCo1idf+HBbXxRJohUUhUf7GoEYqa4ccKvuMX1ZXSqpn/abuT 07LCqDHNu1MdPmwu7y05fzuthQjJ8zMT3i/MGBvQQmgP2eAvaMCpFYyf+N6wL2JPZreh TURA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686689988; x=1689281988; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6dm9P/uUTs4MZ/sIEWKFivbNK7+MeEV1c5lZeWHAirE=; b=L034FPRynQ30XkVTYzaUGVCZ4G66RBv1LCHCdUBopbc86o6k8ZpkD1gyTLCtekAAZr YmpqAYHdLBVy6bE76ZrQaWsglbUx6LDjd2bJCi7WWX9pJ1WIgOYyiQddNn0wi0RGFEs/ 9sfHgyhzcfbMuI+SwFyLXcNOR8Ifot/YrSbYXr1eP1wb7CbSBvfElEuknDowJVUI3R2B slfGnMUbrpVHVFc02eDNQ29QGz69L7XmcGqo4ck8l93dPosNSLxPQ4fxeO2s/5Wd9Ago XTzN+bHLUjWljXAcsCKvcXr4TmFz+f5OqytAZlanXG/HTSI/vZnJj4CP4TI7wdkAEakT clsg== X-Gm-Message-State: AC+VfDzi55JxTnyoDslwsvyR/LOt7pFu/rL108NswcVi1kVSQuRe8Z3l K+DCC0ek3R3T+sx/jVwjYY8DTUF0hku5Pa5ySQA= X-Google-Smtp-Source: ACHHUZ4bafB2LDVm22U926k2U+KwzhxaRXRXju2gtRrUrLxORIXYrvwHnWLeC/nl7sMCayHwBpg46g== X-Received: by 2002:a05:6808:f91:b0:398:f76:36a5 with SMTP id o17-20020a0568080f9100b003980f7636a5mr9469574oiw.56.1686689988215; Tue, 13 Jun 2023 13:59:48 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 11/18] target/riscv/cpu: add misa_ext_infos[] Date: Tue, 13 Jun 2023 17:58:50 -0300 Message-Id: <20230613205857.495165-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613205857.495165-1-dbarboza@ventanamicro.com> References: <20230613205857.495165-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1686690194453100001 Content-Type: text/plain; charset="utf-8" Next patch will add KVM specific user properties for both MISA and multi-letter extensions. For MISA extensions we want to make use of what is already available in misa_ext_cfgs[] to avoid code repetition. The new misa_ext_infos[] array will hold name and description for each MISA extension that misa_ext_cfgs[] is declaring. We'll then use this new array in KVM code to avoid duplicating strings. There's nothing holding us back from doing the same with multi-letter extensions. For now doing just with MISA extensions is enough. Suggested-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 44 ++++++++++++++++++-------------------------- target/riscv/cpu.h | 22 +++++++++++++++++++++- 2 files changed, 39 insertions(+), 27 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0b25d53bbe..edaf052f25 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1562,33 +1562,25 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visit= or *v, const char *name, visit_type_bool(v, name, &value, errp); } =20 +#define MISA_CFG(_bit, _enabled) \ + {.name =3D misa_ext_infos[_bit].name, \ + .description =3D misa_ext_infos[_bit].description, \ + .misa_bit =3D _bit, .enabled =3D _enabled} + static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { - {.name =3D "a", .description =3D "Atomic instructions", - .misa_bit =3D RVA, .enabled =3D true}, - {.name =3D "c", .description =3D "Compressed instructions", - .misa_bit =3D RVC, .enabled =3D true}, - {.name =3D "d", .description =3D "Double-precision float point", - .misa_bit =3D RVD, .enabled =3D true}, - {.name =3D "f", .description =3D "Single-precision float point", - .misa_bit =3D RVF, .enabled =3D true}, - {.name =3D "i", .description =3D "Base integer instruction set", - .misa_bit =3D RVI, .enabled =3D true}, - {.name =3D "e", .description =3D "Base integer instruction set (embedd= ed)", - .misa_bit =3D RVE, .enabled =3D false}, - {.name =3D "m", .description =3D "Integer multiplication and division", - .misa_bit =3D RVM, .enabled =3D true}, - {.name =3D "s", .description =3D "Supervisor-level instructions", - .misa_bit =3D RVS, .enabled =3D true}, - {.name =3D "u", .description =3D "User-level instructions", - .misa_bit =3D RVU, .enabled =3D true}, - {.name =3D "h", .description =3D "Hypervisor", - .misa_bit =3D RVH, .enabled =3D true}, - {.name =3D "x-j", .description =3D "Dynamic translated languages", - .misa_bit =3D RVJ, .enabled =3D false}, - {.name =3D "v", .description =3D "Vector operations", - .misa_bit =3D RVV, .enabled =3D false}, - {.name =3D "g", .description =3D "General purpose (IMAFD_Zicsr_Zifence= i)", - .misa_bit =3D RVG, .enabled =3D false}, + MISA_CFG(RVA, true), + MISA_CFG(RVC, true), + MISA_CFG(RVD, true), + MISA_CFG(RVF, true), + MISA_CFG(RVI, true), + MISA_CFG(RVE, false), + MISA_CFG(RVM, true), + MISA_CFG(RVS, true), + MISA_CFG(RVU, true), + MISA_CFG(RVH, true), + MISA_CFG(RVJ, false), + MISA_CFG(RVV, false), + MISA_CFG(RVG, false), }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e3e08d315f..6d2acea478 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -41,7 +41,7 @@ =20 #define RV(x) ((target_ulong)1 << (x - 'A')) =20 -/* Consider updating misa_ext_cfgs[] when adding new MISA bits here */ +/* Consider updating misa_ext_infos[] when adding new MISA bits here */ #define RVI RV('I') #define RVE RV('E') /* E and I are mutually exclusive */ #define RVM RV('M') @@ -56,6 +56,26 @@ #define RVJ RV('J') #define RVG RV('G') =20 +typedef struct misa_ext_info { + const char *name; + const char *description; +} MISAExtInfo; + +static const MISAExtInfo misa_ext_infos[] =3D { + [RVA] =3D {"a", "Atomic instructions"}, + [RVC] =3D {"c", "Compressed instructions"}, + [RVD] =3D {"d", "Double-precision float point"}, + [RVF] =3D {"f", "Single-precision float point"}, + [RVI] =3D {"i", "Base integer instruction set"}, + [RVE] =3D {"e", "Base integer instruction set (embedded)"}, + [RVM] =3D {"m", "Integer multiplication and division"}, + [RVS] =3D {"s", "Supervisor-level instructions"}, + [RVU] =3D {"u", "User-level instructions"}, + [RVH] =3D {"h", "Hypervisor"}, + [RVJ] =3D {"x-j", "Dynamic translated languages"}, + [RVV] =3D {"v", "Vector operations"}, + [RVG] =3D {"g", "General purpose (IMAFD_Zicsr_Zifencei)"}, +}; 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([177.170.117.210]) by smtp.gmail.com with ESMTPSA id q82-20020acaf255000000b003982a8a1e3fsm5619514oih.51.2023.06.13.13.59.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 13:59:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686689991; x=1689281991; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/HhEZIp35mkxQyh7s7sm6RzEn8Kadlavjt1IL8PO4As=; b=mDg/2LzBlzSHYlbg1/OwEH2OYsa6kT5Z4M79mtCF5eJVMyabnW0cMh9zu6/ujVqGq6 3LJc6W23XGegxQ4MaiwR8KauYAU6Uu6WZjcwkW8r6oN6MbhxIymL34vsThYKfiymBhnk yMjOWms+aVib1IPNyxkJV0EyxsDJOElXHtE7j6U5P7+mPsUgbx/+df7anMjGgd4a9uOl V04C7O2eDBykc62DFW6Z+oIPLIcsfSgIbXzJ2CA96luPPAbhUdd8TdSJrLkzhwTmiwdP +ql82Kg++Ga/7CG3UajhQHCjF4e39QTvh3B0PxJSydYvA5Oby+t2bJAJs5piUkhtuKpV Q+bQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686689991; x=1689281991; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/HhEZIp35mkxQyh7s7sm6RzEn8Kadlavjt1IL8PO4As=; b=l4Tjcrvw3DXy3QvHQ7MI+8BbNjII6B7NR0bQHTGjATIIwLM6gKgmYdjBazTrJb3PJv gNYA038vnARNuZ93aTwmqVsX6TsLSZmAh2+RIWSBhsjVRoQ3u8GvaI/rRX+qERgBuQaO TuATdal6jKbLYlfLYH/zFtmCnYexnFsuXFnU4015rv00CUoJIQHaYFgqOoXI8KSrNNmn 0BenDLBP+zEdqzQSEYr/Iidr232R9caUzKsSFtXPrREgljCMx/tnmZvuEUgy2bZZrpDy jRtMKgdOvmznBunl+PNfcjzZ97OEtcQWpxuR7WgbUpFMvN1yrM9klgD5ZlaBSBotfZ1+ JUXA== X-Gm-Message-State: AC+VfDyE/1sleoZ4G+nwVjkHgc6EkKyf+/oelI3B2ZsD1exQoTvrjtph s5B5Uei2/koe3sSKY/W/nKKjfP7CQPW1TP8pT5o= X-Google-Smtp-Source: ACHHUZ5sQmmsutJmG3uLhOJnEH52Nos+nPdaOt8xc0NbZkjIK60x8z0vsRTQn/+n8uQgjaq8XtPZZg== X-Received: by 2002:aca:f009:0:b0:399:ed2a:f4b5 with SMTP id o9-20020acaf009000000b00399ed2af4b5mr5335053oih.24.1686689991186; Tue, 13 Jun 2023 13:59:51 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 12/18] target/riscv: add KVM specific MISA properties Date: Tue, 13 Jun 2023 17:58:51 -0300 Message-Id: <20230613205857.495165-13-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613205857.495165-1-dbarboza@ventanamicro.com> References: <20230613205857.495165-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1686690091723100007 Content-Type: text/plain; charset="utf-8" Using all TCG user properties in KVM is tricky. First because KVM supports only a small subset of what TCG provides, so most of the cpu->cfg flags do nothing for KVM. Second, and more important, we don't have a way of telling if any given value is an user input or not. For TCG this has a small impact since we just validating everything and error out if needed. But for KVM it would be good to know if a given value was set by the user or if it's a value already provided by KVM. Otherwise we don't know how to handle failed kvm_set_one_regs() when writing the configurations back. These characteristics make it overly complicated to use the same user facing flags for both KVM and TCG. A simpler approach is to create KVM specific properties that have specialized logic, forking KVM and TCG use cases for those cases only. Fully separating KVM/TCG properties is unneeded at this point - in fact we want the user experience to be as equal as possible, regardless of the acceleration chosen. We'll start this fork with the MISA properties, adding the MISA bits that the KVM driver currently supports. A new KVMCPUConfig type is introduced. It'll hold general information about an extension. For MISA extensions we're going to use the newly created misa_ext_infos[] to populate their name and description. 'offset' holds the MISA bit (RVA, RVC, ...). We're calling it 'offset' instead of 'misa_bit' because this same KVMCPUConfig struct will be used to multi-letter extensions later on. This new type also holds a 'user_set' flag. This flag will be set when the user set an option that's different than what is already configured in the host, requiring KVM intervention to write the regs back during kvm_arch_init_vcpu(). Similar mechanics will be implemented for multi-letter extensions as well. There is no need to duplicate more code than necessary, so we're going to use the existing kvm_riscv_init_user_properties() to add the KVM specific properties. Any code that is adding a TCG user prop is then changed slightly to verify first if there's a KVM prop with the same name already added. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 10 ++++++ target/riscv/kvm.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 86 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index edaf052f25..a4f3ed0c17 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1590,6 +1590,11 @@ static void riscv_cpu_add_misa_properties(Object *cp= u_obj) for (i =3D 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { const RISCVCPUMisaExtConfig *misa_cfg =3D &misa_ext_cfgs[i]; =20 + /* Check if KVM didn't create the property already */ + if (object_property_find(cpu_obj, misa_cfg->name)) { + continue; + } + object_property_add(cpu_obj, misa_cfg->name, "bool", cpu_get_misa_ext_cfg, cpu_set_misa_ext_cfg, @@ -1713,6 +1718,11 @@ static void riscv_cpu_add_user_properties(Object *ob= j) riscv_cpu_add_misa_properties(obj); =20 for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { + /* Check if KVM didn't create the property already */ + if (object_property_find(obj, prop->name)) { + continue; + } + qdev_property_add_static(dev, prop); } =20 diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 4d0808cb9a..53042a0e86 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -22,8 +22,10 @@ #include =20 #include "qemu/timer.h" +#include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" +#include "qapi/visitor.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" #include "sysemu/kvm_int.h" @@ -105,6 +107,79 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, u= int64_t type, } \ } while (0) =20 +typedef struct KVMCPUConfig { + const char *name; + const char *description; + target_ulong offset; + int kvm_reg_id; + bool user_set; +} KVMCPUConfig; + +#define KVM_MISA_CFG(_bit, _reg_id) \ + {.name =3D misa_ext_infos[_bit].name, \ + .description =3D misa_ext_infos[_bit].description, \ + .offset =3D _bit, .kvm_reg_id =3D _reg_id} + +/* KVM ISA extensions */ +static KVMCPUConfig kvm_misa_ext_cfgs[] =3D { + KVM_MISA_CFG(RVA, KVM_RISCV_ISA_EXT_A), + KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C), + KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D), + KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F), + KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), + KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), + KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), +}; + +static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, + const char *name, + void *opaque, Error **errp) +{ + KVMCPUConfig *misa_ext_cfg =3D opaque; + target_ulong misa_bit =3D misa_ext_cfg->offset; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + bool value, host_bit; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + host_bit =3D env->misa_ext_mask & misa_bit; + + if (value =3D=3D host_bit) { + return; + } + + if (!value) { + misa_ext_cfg->user_set =3D true; + return; + } + + /* + * Forbid users to enable extensions that aren't + * available in the hart. + */ + error_setg(errp, "Enabling MISA bit '%s' is not allowed: it's not " + "enabled in the host", misa_ext_cfg->name); +} + +static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { + KVMCPUConfig *misa_cfg =3D &kvm_misa_ext_cfgs[i]; + + object_property_add(cpu_obj, misa_cfg->name, "bool", + NULL, + kvm_cpu_set_misa_ext_cfg, + NULL, misa_cfg); + object_property_set_description(cpu_obj, misa_cfg->name, + misa_cfg->description); + } +} + static int kvm_riscv_get_regs_core(CPUState *cs) { int ret =3D 0; @@ -427,6 +502,7 @@ void kvm_riscv_init_user_properties(Object *cpu_obj) return; } =20 + kvm_riscv_add_cpu_user_properties(cpu_obj); kvm_riscv_init_machine_ids(cpu, &kvmcpu); kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); =20 --=20 2.40.1 From nobody Sat May 18 15:49:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1686690222; cv=none; d=zohomail.com; s=zohoarc; b=R9rXLVZrJyhag77k78r+Wi6MEKIVt5dGOavhaQ+wIh9mcnmTbg9OKT757m4eXx3zwm9O7DOoWeF0zo4p7xJD3aLFcwupNLI2LQG0Wznhj04fgY2GH7MGDr8XWCPp1gxsDe5o6grUW4tZQyV0XAxAVm+8SHxvilk7j4C3Qchb34c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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([177.170.117.210]) by smtp.gmail.com with ESMTPSA id q82-20020acaf255000000b003982a8a1e3fsm5619514oih.51.2023.06.13.13.59.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 13:59:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686689994; x=1689281994; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Nomoe5wOs8QQV5HVn+Gft6DhZTpJdTHe9i9Z3CiNkW4=; b=IjBYKIrhGtpyo4AImSJ+vInPTyBsCFIQ8kxGYBhn65UhuiBIoc5D1krrZYnzDSizRo 9XFFWA6LQOyYoBMe7O8ZdFjqMlJxvTOPyxVOfAOETvS9l7hCMpCkUXeuIfXi81pToNkM Nwnqrw7+w4Jr1rnaC4YAEUxsVXcMSwGsN2Vtj1xPdPofn3co+erkBzxEoAaUsOo+dh7q rvsQ3laea6zpVzya0t772lDxi9ikXNNup5lXG3VEp7Gvz+3pmzAUlJMradeg/gynuwio 42ZVjDzE1fcQsQZsgfzSAmFG5qJO9IJTxM9uPGW+2xEVgxvc8uebJJw0Gv+hZbbrdkSC ndwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686689994; x=1689281994; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Nomoe5wOs8QQV5HVn+Gft6DhZTpJdTHe9i9Z3CiNkW4=; b=JKWLIPYAhVqsE+I3oqsJ2M+XJ+D8E611bqZ7FbsQ7hgHF9YXr1+zun/tOypSahehdx 7M7VYD/193y9GBxtf0kC2fXMXGdPbwKtV6ywfYZ903xaeaFUkU/Y5MdCAzo8Oqnj/UIr CQE6S1AK06Jpmr/DjjDpOPLcfH3R4+ghMIvM0o4m48258GRKk94MlGA6NYxxjqSYw3S/ mu5iWF/dRxtq0R+Ai37NbYhLeolSH85O0F0UrODI7hrvcBEFim5ipQIkaVHro9wyu8w3 vH1aeHDIIcQJBOonnslhBhfyabCJj6yynC+GqFApqMufvJix/e+Dc88s37j30XjO4D0v LT/A== X-Gm-Message-State: AC+VfDwYoMxXhVLYeKgAHEbAxPZdRYTvGfjIco78nlPHTZAbj9vMyEf1 wqo4bPPZfDL4bVsf64JIRxbM9eCv1FEGk8WmrbY= X-Google-Smtp-Source: ACHHUZ6T4/Lyt8ClbL3t3PRjSAz+sXeA//56Leslm8Kup9EUDoo4MLg2vw6AhEG8O2324eAvmuvMFw== X-Received: by 2002:a05:6808:d4e:b0:39a:abe8:afb9 with SMTP id w14-20020a0568080d4e00b0039aabe8afb9mr10355980oik.42.1686689994011; Tue, 13 Jun 2023 13:59:54 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 13/18] target/riscv/kvm.c: update KVM MISA bits Date: Tue, 13 Jun 2023 17:58:52 -0300 Message-Id: <20230613205857.495165-14-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613205857.495165-1-dbarboza@ventanamicro.com> References: <20230613205857.495165-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1686690225855100005 Content-Type: text/plain; charset="utf-8" Our design philosophy with KVM properties can be resumed in two main decisions based on KVM interface availability and what the user wants to do: - if the user disables an extension that the host KVM module doesn't know about (i.e. it doesn't implement the kvm_get_one_reg() interface), keep booting the CPU. This will avoid users having to deal with issues with older KVM versions while disabling features they don't care; - for any other case we're going to error out immediately. If the user wants to enable a feature that KVM doesn't know about this a problem that is worth aborting - the user must know that the feature wasn't enabled in the hart. Likewise, if KVM knows about the extension, the user wants to enable/disable it, and we fail to do it so, that's also a problem we can't shrug it off. For MISA bits we're going to be a little more conservative: we won't even try enabling bits that aren't already available in the host. The ioctl() is so likely to fail that's not worth trying. This check is already done in the previous patch, in kvm_cpu_set_misa_ext_cfg(), thus we don't need to worry about it now. In kvm_riscv_update_cpu_misa_ext() we'll go through every potential user option and do as follows: - if the user didn't set the property or set to the same value of the host, do nothing; - Disable the given extension in KVM. Error out if anything goes wrong. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 53042a0e86..ea38f91b92 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -164,6 +164,41 @@ static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visi= tor *v, "enabled in the host", misa_ext_cfg->name); } =20 +static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) +{ + CPURISCVState *env =3D &cpu->env; + uint64_t id, reg; + int i, ret; + + for (i =3D 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { + KVMCPUConfig *misa_cfg =3D &kvm_misa_ext_cfgs[i]; + target_ulong misa_bit =3D misa_cfg->offset; + + if (!misa_cfg->user_set) { + continue; + } + + /* If we're here we're going to disable the MISA bit */ + reg =3D 0; + id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, + misa_cfg->kvm_reg_id); + ret =3D kvm_set_one_reg(cs, id, ®); + if (ret !=3D 0) { + /* + * We're not checking for -EINVAL because if the bit is + * about to be disabled means that it was already enabled + * by KVM, something that we determined by fetching the + * 'isa' register during init() time. Any error at this + * point is worth aborting. + */ + error_report("Unable to set KVM reg %s, error %d", + misa_cfg->name, ret); + exit(EXIT_FAILURE); + } + env->misa_ext &=3D ~misa_bit; + } +} + static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) { int i; @@ -630,8 +665,13 @@ int kvm_arch_init_vcpu(CPUState *cs) =20 if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { ret =3D kvm_vcpu_set_machine_ids(cpu, cs); + if (ret !=3D 0) { + return ret; + } } =20 + kvm_riscv_update_cpu_misa_ext(cpu, cs); + return ret; } =20 --=20 2.40.1 From nobody Sat May 18 15:49:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1686690216; cv=none; d=zohomail.com; s=zohoarc; b=L2M5y/U8GA5pejZjWRKGnSQ3KCWC4LyQUesKzsuMJgD44F4OFA5FyHy2aoW5hJ9ixiRN1m+ruNBd4eCb/W6b6Bix0djDhAXql2iMAFyPBEDSV+Ah7hBflKNYtnxAVQXERp9tgeLyDWOVR05OvpQfrOiDZRmCSoV3EBIQHRM77Yg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686690216; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FQXUHpfhKXsZLrVEkzfz5QY6BTefTtPb8Xc7FDHjjSs=; b=Q+EeHNRs8q2h4F3v04PiWws7qLZ3WI4XUI/E6XkRqKc64K71vWKw3vPib0uhMgpO3Cs9fWUDZR/1DFStHXHzOmRDJupaGIrJEi6lT0WTJg3iy3dSgLHayVn32u06LCl1Kvl03JyA2Sbmqr4kfcOyNRJ+FfCqOrMEdW60/IFqYLM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686690216459567.1787580780801; Tue, 13 Jun 2023 14:03:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9B7X-0002CW-AQ; Tue, 13 Jun 2023 17:00:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9B7T-0002Ak-3b for qemu-devel@nongnu.org; Tue, 13 Jun 2023 17:00:03 -0400 Received: from mail-oi1-x230.google.com ([2607:f8b0:4864:20::230]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q9B7O-0006nE-GI for qemu-devel@nongnu.org; Tue, 13 Jun 2023 17:00:01 -0400 Received: by mail-oi1-x230.google.com with SMTP id 5614622812f47-39c7f78c237so3850666b6e.3 for ; Tue, 13 Jun 2023 13:59:57 -0700 (PDT) Received: from grind.. ([177.170.117.210]) by smtp.gmail.com with ESMTPSA id q82-20020acaf255000000b003982a8a1e3fsm5619514oih.51.2023.06.13.13.59.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 13:59:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686689997; x=1689281997; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FQXUHpfhKXsZLrVEkzfz5QY6BTefTtPb8Xc7FDHjjSs=; b=UsPQsYS2ejPC3GW9nRh+Nq41NbkCbdYuCRnRBH6exLCwaJH8SgzXHGIq5X2KMMmk49 Vuwl3hLXXxDb4SlADkYfMczHWZtkdQO/OjMu/tQ6852NUYTwoBCalUhZqtLjOjLKXxwO fC3F4A0Vn5oEQW4OCB4XgofU8882iBt5oAzrIs3+G5hDq43OUSKS0dEfQshyk1fwJoRz bsrCR8oPmF8v45E4LfGZnBMw1vK7PqeEPsD9EMiJnmsI3yL7CaOP+nxc0C8HdqKanFpF 94j4P160/9JodKN9jnS4L/x7K/JzjGCvp24wzmenLP/qJ0IxlOJL820LoWsuVfome6FB HBBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686689997; x=1689281997; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FQXUHpfhKXsZLrVEkzfz5QY6BTefTtPb8Xc7FDHjjSs=; b=hNCZoj+bHe7awUeJbGJmOxEIaY3OAQm9jun3H/6algBwxlcXwMAhnECqwdIt173TwF 6ZnNdt6YY1IBwT1HTfqV1b9creiH7M7b9L8P2Aa8ytC/mg2E3WFJD1ffOcqDwe6Hg5FZ tHanpa9Dl6Nd/hSTXsjGHKBIxr+8V6b5HOGlbOG36fb8OeaOkNdaO//JtmI+JTSA8Y10 r49jePqg9bsuGxMZzRwnud3qA0YP+W+6UFZ41OpPNpesJLR0H64dtLGxlXojkJEXTAGQ Bsnrq3qRnVQrLrGNlIh/FPg9oOjoKtLc9ekFmgybnY3zJtZwmsYTQMQX176zMIdypFwm SZjw== X-Gm-Message-State: AC+VfDxvIEecDrQFOVxzjVdn5GI7u7g0AGq6laZPc8SJuE7hVXi/KdYK PIdFAMVsjN7sKZptiRAjYffeN2/7zLO1RmSvaWQ= X-Google-Smtp-Source: ACHHUZ5KiuUxsfQZE2yYGb7YKuKLxW5BqamgxMrb7aFPohiHuXNkTZgN1fflH89EQpWcaIKU2F2t2Q== X-Received: by 2002:a05:6808:2381:b0:398:1027:4fae with SMTP id bp1-20020a056808238100b0039810274faemr10398382oib.25.1686689996973; Tue, 13 Jun 2023 13:59:56 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 14/18] target/riscv/kvm.c: add multi-letter extension KVM properties Date: Tue, 13 Jun 2023 17:58:53 -0300 Message-Id: <20230613205857.495165-15-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613205857.495165-1-dbarboza@ventanamicro.com> References: <20230613205857.495165-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1686690217387100001 Content-Type: text/plain; charset="utf-8" Let's add KVM user properties for the multi-letter extensions that KVM currently supports: zicbom, zicboz, zihintpause, zbb, ssaia, sstc, svinval and svpbmt. As with MISA extensions, we're using the KVMCPUConfig type to hold information about the state of each extension. However, multi-letter extensions have more cases to cover than MISA extensions, so we're adding an extra 'supported' flag as well. This flag will reflect if a given extension is supported by KVM, i.e. KVM knows how to handle it. This is determined during KVM extension discovery in kvm_riscv_init_multiext_cfg(), where we test for EINVAL errors. Any other error different from EINVAL will cause an abort. The use of the 'user_set' is similar to what we already do with MISA extensions: the flag set only if the user is changing the extension state. The 'supported' flag will be used later on to make an exception for users that are disabling multi-letter extensions that are unknown to KVM. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm.c | 124 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 124 insertions(+) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index ea38f91b92..63bf97fbff 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -113,6 +113,7 @@ typedef struct KVMCPUConfig { target_ulong offset; int kvm_reg_id; bool user_set; + bool supported; } KVMCPUConfig; =20 #define KVM_MISA_CFG(_bit, _reg_id) \ @@ -199,6 +200,86 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cp= u, CPUState *cs) } } =20 +#define CPUCFG(_prop) offsetof(struct RISCVCPUConfig, _prop) + +#define KVM_EXT_CFG(_name, _prop, _reg_id) \ + {.name =3D _name, .offset =3D CPUCFG(_prop), \ + .kvm_reg_id =3D _reg_id} +/* + * KVM ISA Multi-letter extensions. We care about the order + * since it'll be used to create the ISA string later on. + * We follow the same ordering rules of isa_edata_arr[] + * from target/riscv/cpu.c. + */ +static KVMCPUConfig kvm_multi_ext_cfgs[] =3D { + KVM_EXT_CFG("zicbom", ext_icbom, KVM_RISCV_ISA_EXT_ZICBOM), + KVM_EXT_CFG("zicboz", ext_icboz, KVM_RISCV_ISA_EXT_ZICBOZ), + KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPA= USE), + KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB), + KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA), + KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC), + KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL), + KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), +}; + +static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, + uint32_t val) +{ + int cpu_cfg_offset =3D multi_ext->offset; + bool *ext_enabled =3D (void *)&cpu->cfg + cpu_cfg_offset; + + *ext_enabled =3D val; +} + +static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, + KVMCPUConfig *multi_ext) +{ + int cpu_cfg_offset =3D multi_ext->offset; + bool *ext_enabled =3D (void *)&cpu->cfg + cpu_cfg_offset; + + return *ext_enabled; +} + +static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, + const char *name, + void *opaque, Error **errp) +{ + KVMCPUConfig *multi_ext_cfg =3D opaque; + RISCVCPU *cpu =3D RISCV_CPU(obj); + bool value, host_val; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + host_val =3D kvm_cpu_cfg_get(cpu, multi_ext_cfg); + + /* + * Ignore if the user is setting the same value + * as the host. + */ + if (value =3D=3D host_val) { + return; + } + + if (!multi_ext_cfg->supported) { + /* + * Error out if the user is trying to enable an + * extension that KVM doesn't support. Ignore + * option otherwise. + */ + if (value) { + error_setg(errp, "KVM does not support disabling extension %s", + multi_ext_cfg->name); + } + + return; + } + + multi_ext_cfg->user_set =3D true; + kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); +} + static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) { int i; @@ -213,6 +294,15 @@ static void kvm_riscv_add_cpu_user_properties(Object *= cpu_obj) object_property_set_description(cpu_obj, misa_cfg->name, misa_cfg->description); } + + for (i =3D 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { + KVMCPUConfig *multi_cfg =3D &kvm_multi_ext_cfgs[i]; + + object_property_add(cpu_obj, multi_cfg->name, "bool", + NULL, + kvm_cpu_set_multi_ext_cfg, + NULL, multi_cfg); + } } =20 static int kvm_riscv_get_regs_core(CPUState *cs) @@ -528,6 +618,39 @@ static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, env->misa_ext =3D env->misa_ext_mask; } =20 +static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmc= pu) +{ + CPURISCVState *env =3D &cpu->env; + uint64_t val; + int i, ret; + + for (i =3D 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { + KVMCPUConfig *multi_ext_cfg =3D &kvm_multi_ext_cfgs[i]; + struct kvm_one_reg reg; + + reg.id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, + multi_ext_cfg->kvm_reg_id); + reg.addr =3D (uint64_t)&val; + ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); + if (ret !=3D 0) { + if (ret =3D=3D -EINVAL) { + /* Silently default to 'false' if KVM does not support it.= */ + multi_ext_cfg->supported =3D false; + val =3D false; + } else { + error_report("Unable to read ISA_EXT KVM register %s, " + "error %d", multi_ext_cfg->name, ret); + kvm_riscv_destroy_scratch_vcpu(kvmcpu); + exit(EXIT_FAILURE); + } + } else { + multi_ext_cfg->supported =3D true; + } + + kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); + } +} + void kvm_riscv_init_user_properties(Object *cpu_obj) { RISCVCPU *cpu =3D RISCV_CPU(cpu_obj); @@ -540,6 +663,7 @@ void kvm_riscv_init_user_properties(Object *cpu_obj) kvm_riscv_add_cpu_user_properties(cpu_obj); kvm_riscv_init_machine_ids(cpu, &kvmcpu); kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); + kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); =20 kvm_riscv_destroy_scratch_vcpu(&kvmcpu); } --=20 2.40.1 From nobody Sat May 18 15:49:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1686690149; cv=none; d=zohomail.com; s=zohoarc; b=XLXOgLS3SIllKCWdx5FaD6LV4smtdtwFPqeP+qosAMZvC9MXcsqpk+N8cnGXbP0a20b3FOEhE2Ma1IHppns8CKkvdQiSOtDebdNV48uPrk24n7yS1d/UPaKeqDvTT+VFBQ8yXiJ5Ji+ZM2ZF/s08mkxn4kRS6qMjZjQ/xgJHvvU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686690149; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uYaVWv8GHKldx7H8e2qrZO0GFJvC2VkmhQVsLqD8/jI=; b=cjEE3BltH8GFOAXSh2iBpbr6IRVPX6wa2/ggIbmoR5M2eC5pssAP8TbDtON30JtDjmhgkhHA4uvUEXWZrSHmHWTOtreKFsnVvBJ0j4O6WNFgAA7ux8DADKZbMkm/UU3SJPhAweNmHuxz2Njncne4eO2NqTjcbJ6At0sW+MqdAwc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686690149811730.7611454698264; Tue, 13 Jun 2023 14:02:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9B7a-0002Do-I6; Tue, 13 Jun 2023 17:00:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9B7W-0002Bf-1Y for qemu-devel@nongnu.org; Tue, 13 Jun 2023 17:00:06 -0400 Received: from mail-oi1-x22e.google.com ([2607:f8b0:4864:20::22e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q9B7T-0006nc-4W for qemu-devel@nongnu.org; Tue, 13 Jun 2023 17:00:05 -0400 Received: by mail-oi1-x22e.google.com with SMTP id 5614622812f47-392116b8f31so3108015b6e.2 for ; Tue, 13 Jun 2023 14:00:01 -0700 (PDT) Received: from grind.. ([177.170.117.210]) by smtp.gmail.com with ESMTPSA id q82-20020acaf255000000b003982a8a1e3fsm5619514oih.51.2023.06.13.13.59.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 13:59:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686690000; x=1689282000; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uYaVWv8GHKldx7H8e2qrZO0GFJvC2VkmhQVsLqD8/jI=; b=fQ2Tqpx2VNvGWbu4GUvZblWxIwTN6Tbuqoy/Enq4ZaYi7Oya28MZfuxzQvEHjTaSZC zCtyXJIJ421npX5PbfQYgWw6Cn8nFwTneRlROVJaHbr2PEFlmxBIrHS09gdbtl5Xz3Wg 1NqVGZxLN5Q2+TvfIqLvRcny+T636fuQFo2UAJyP87gQX+0sGyNkJI0wxVPujpvTxUMX QJ1Tm4RTvZn5lndGKQxCUj5V8Ka3rckdXBks8l5nqLBwuUpHeg2LMqKNqUbYoc5cXhjF 0DKjHYViV0AZUioe3SnmTgZ1NkzwTR9S5a/HEXQAYYMjcN96s2MFBoXv2nAqxqKHXIDU FCrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686690000; x=1689282000; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uYaVWv8GHKldx7H8e2qrZO0GFJvC2VkmhQVsLqD8/jI=; b=cQ6YAXM1QtIsQPl7Qjq9D6vyg5YjObBvXmckDVK+5qf8Wcx2vTODjvbG4/NSCcaYRO ab/181jnMrXKRm0Hnl/tX+fQoHTKOfOzsRRsDG3+ZVBBZzBX6jEoB5/tP+8QHpKK3I84 6AromOAnkSZF49TwZrC01DX+L2rchG72hhlbX1hkCHX1T6dc3v21cUBehqbOcazZB5di mblbFpMc2a8GktcNRLyT7gsi4VcZGCh8eBRjfzalrdOhVjg+eWF+ki6araUPA0uWhenW Jxe6Jlqw7aMW06SboCQ1QTEuiOnUv2Y//6RCnMOteikhmHWft3FS9AkgCPKk8YwpftPd /WqA== X-Gm-Message-State: AC+VfDwdS6w3UsUAHCzLncAgiJpsN2ufxeboh3qn0J+hAFUmu9ioafrL qTgAA7pKp5mNEZkSmVUfpfIcbGjlHkK8F/fkbpM= X-Google-Smtp-Source: ACHHUZ64PtxrDP/YEJKBBjfEgxQRJXUwSW2oNBfhqLHxqKMRJH7UUGs1cZh1xUBB1/V8gzPq7p6FZg== X-Received: by 2002:a05:6808:1b06:b0:39a:be57:964b with SMTP id bx6-20020a0568081b0600b0039abe57964bmr10494933oib.13.1686690000077; Tue, 13 Jun 2023 14:00:00 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 15/18] target/riscv: make riscv_isa_string_ext() KVM compatible Date: Tue, 13 Jun 2023 17:58:54 -0300 Message-Id: <20230613205857.495165-16-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613205857.495165-1-dbarboza@ventanamicro.com> References: <20230613205857.495165-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1686690151109100001 Content-Type: text/plain; charset="utf-8" The isa_edata_arr[] is used by riscv_isa_string_ext() to create the riscv,isa DT attribute. isa_edata_arr[] is kept in sync with the TCG property vector riscv_cpu_extensions[], i.e. all TCG properties from this vector that has a riscv,isa representation are included in isa_edata_arr[]. KVM doesn't implement all TCG properties, but allow them to be created anyway to not force an API change between TCG and KVM guests. Some of these TCG-only extensions are defaulted to 'true', and users are also allowed to enable them. KVM doesn't care, but riscv_isa_string_ext() does. The result is that these TCG-only enabled extensions will appear in the riscv,isa DT string under KVM. To avoid code repetition and re-use riscv_isa_string_ext() for KVM guests we'll make a couple of tweaks: - set env->priv_ver to 'LATEST' for the KVM 'host' CPU. This is needed because riscv_isa_string_ext() makes a priv check for each extension before including them in the ISA string. KVM doesn't care about env->priv_ver, since it's part of the TCG-only CPU validation, so this change is benign for KVM; - add a new 'kvm_available' flag in isa_ext_data struct. This flag is set via a new ISA_EXT_DATA_ENTRY_KVM macro to report that, for a given extension, KVM also supports it. riscv_isa_string_ext() then can check if a given extension is known by KVM and skip it if it's not. This will allow us to re-use riscv_isa_string_ext() for KVM guests. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a4f3ed0c17..a773c09645 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -44,11 +44,15 @@ struct isa_ext_data { const char *name; int min_version; int ext_enable_offset; + bool kvm_available; }; =20 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} =20 +#define ISA_EXT_DATA_ENTRY_KVM(_name, _min_ver, _prop) \ + {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop), true} + /* * Here are the ordering rules of extension naming defined by RISC-V * specification : @@ -68,14 +72,17 @@ struct isa_ext_data { * * Single letter extensions are checked in riscv_cpu_validate_misa_priv() * instead. + * + * ISA_EXT_DATA_ENTRY_KVM() is used to indicate that the extension is + * also known by the KVM driver. If unsure, use ISA_EXT_DATA_ENTRY(). */ static const struct isa_ext_data isa_edata_arr[] =3D { - ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), - ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), + ISA_EXT_DATA_ENTRY_KVM(zicbom, PRIV_VERSION_1_12_0, ext_icbom), + ISA_EXT_DATA_ENTRY_KVM(zicboz, PRIV_VERSION_1_12_0, ext_icboz), ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), - ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), + ISA_EXT_DATA_ENTRY_KVM(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpau= se), ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh), ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin), @@ -89,7 +96,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp), ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt), ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba), - ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb), + ISA_EXT_DATA_ENTRY_KVM(zbb, PRIV_VERSION_1_12_0, ext_zbb), ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc), ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb), ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc), @@ -114,13 +121,13 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), - ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), + ISA_EXT_DATA_ENTRY_KVM(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), - ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), + ISA_EXT_DATA_ENTRY_KVM(sstc, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), - ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), + ISA_EXT_DATA_ENTRY_KVM(svinval, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), - ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY_KVM(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), @@ -586,6 +593,7 @@ static void riscv_host_cpu_init(Object *obj) set_misa(env, MXL_RV64, 0); #endif riscv_cpu_add_user_properties(obj); + env->priv_ver =3D PRIV_VERSION_LATEST; } #endif =20 @@ -1981,6 +1989,10 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char= **isa_str, int i; =20 for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { + if (riscv_running_kvm() && !isa_edata_arr[i].kvm_available) { + continue; + } + if (cpu->env.priv_ver >=3D isa_edata_arr[i].min_version && isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { new =3D g_strconcat(old, "_", isa_edata_arr[i].name, NULL); --=20 2.40.1 From nobody Sat May 18 15:49:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1686690108; cv=none; d=zohomail.com; s=zohoarc; b=g7hwaTGFRQKqICTUAjJWk1Wzi+i4G6s3absVdc7xE0nk+mqpOxVEFH/IxUDjmGh7o8/JUKsVE7zq4G3GZeC4lOYWL7ClUamPB4Pruf7/oRvefQZCglgpTp6yMW1crB7g7+c3lwWqpFjlME2SrQviqoXaU+TneYdFr2O1DSz1uo4= ARC-Message-Signature: i=1; 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([177.170.117.210]) by smtp.gmail.com with ESMTPSA id q82-20020acaf255000000b003982a8a1e3fsm5619514oih.51.2023.06.13.14.00.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 14:00:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686690003; x=1689282003; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ubJxPOXGsOZcqy3wEgQyj8Qt7Aaplc3qbF8C5aVIw88=; b=pHQMXa7D95mUZhK9LC44c/dPu+1E6/N7uS26U28Cq3/FiLURqVxkq9OE4vzI5Yrbpl Du4OLqG87/cqpEqq9oXZ1vvKPT9GV0ZxNtXxiz1w7iK3TZAp8sg03lcgZe7gt5KJsfcM ooBYS72Nj1+CBvvs3Gy9VQh/b6Qf21CPgnZtHVSippfSKRUSCmGi7Feytethl7dyEGtO 6s8LiTWQ9VbeyxwJgnwkz3wDmRqrp5R58V2wlN+wCiaVqizztcINqv0pYrk4YS0V0ZXQ YX7ha9Gx2+/Kw5umKQ2wVfMgbRZNxz+De6k5jrGc1sfd4FTnmN62FsTxxsmKD4v+L8mm Xh8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686690003; x=1689282003; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ubJxPOXGsOZcqy3wEgQyj8Qt7Aaplc3qbF8C5aVIw88=; b=lV8e4xdJeIZgyGqXSDUHLaTHL5ESOfFfRqeQlluWCrtgcVMqrlZNGUXjWxdeOecFm5 9gZju1bwAm+DdbjesdhN6ogQX+wJGfi5y7bctJOtt6BTjKc4CRHND6QOeKnPNBlESMQk 8w3HA3gaoNWYaqkxXLtPvq9CiFRq9GBCC+/O40FxiOXGq5BcT4wVNKqIzaNR7HgJ0rFw YAddl4Qz1GLM0CoRYwMCDowEskL+MLBIeF5CazjFjsfrLrRVlBbHoSOoTLwQkPG3yVOa WevorIA4x+LapIPw/pROhKlPMhDEa4pnpVu58ctDm6Y2jMnWbTQQ8XPm/XgBmBj6hhrM D7sA== X-Gm-Message-State: AC+VfDzqhvaugpE+G95zI0smd1FqjPWwwl6oqbJMQQ/T0CZnxUA2+hN2 Jbwyl1Hm9SxHhGYDqkShg6S+YOZcOtcqBtiqoIU= X-Google-Smtp-Source: ACHHUZ4qc7qwjZn3adT+HR8OjvIE9Fx3eeCrcfSYh01FG1GUajgC7XSpTB/FuzPtB7RrK8cAM7YX/Q== X-Received: by 2002:a05:6808:209e:b0:39e:7885:e2f6 with SMTP id s30-20020a056808209e00b0039e7885e2f6mr154842oiw.24.1686690003062; Tue, 13 Jun 2023 14:00:03 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 16/18] target/riscv: update multi-letter extension KVM properties Date: Tue, 13 Jun 2023 17:58:55 -0300 Message-Id: <20230613205857.495165-17-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613205857.495165-1-dbarboza@ventanamicro.com> References: <20230613205857.495165-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1686690111049100001 Content-Type: text/plain; charset="utf-8" We're now ready to update the multi-letter extensions status for KVM. kvm_riscv_update_cpu_cfg_isa_ext() is called called during vcpu creation time to verify which user options changes host defaults (via the 'user_set' flag) and tries to write them back to KVM. Failure to commit a change to KVM is only ignored in case KVM doesn't know about the extension (-EINVAL error code) and the user wanted to disable the given extension. Otherwise we're going to abort the boot process. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 63bf97fbff..0b6dff70de 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -280,6 +280,32 @@ static void kvm_cpu_set_multi_ext_cfg(Object *obj, Vis= itor *v, kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); } =20 +static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) +{ + CPURISCVState *env =3D &cpu->env; + uint64_t id, reg; + int i, ret; + + for (i =3D 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { + KVMCPUConfig *multi_ext_cfg =3D &kvm_multi_ext_cfgs[i]; + + if (!multi_ext_cfg->user_set) { + continue; + } + + id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, + multi_ext_cfg->kvm_reg_id); + reg =3D kvm_cpu_cfg_get(cpu, multi_ext_cfg); + ret =3D kvm_set_one_reg(cs, id, ®); + if (ret !=3D 0) { + error_report("Unable to %s extension %s in KVM, error %d", + reg ? "enable" : "disable", + multi_ext_cfg->name, ret); + exit(EXIT_FAILURE); + } + } +} + static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) { int i; @@ -795,6 +821,7 @@ int kvm_arch_init_vcpu(CPUState *cs) } =20 kvm_riscv_update_cpu_misa_ext(cpu, cs); + kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs); =20 return ret; } --=20 2.40.1 From nobody Sat May 18 15:49:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1686690061; cv=none; d=zohomail.com; s=zohoarc; b=dV482hHs46c0UkyUhCP7t9tLxTfyiemrBcMhWEID29TKRkbxh3NXEjATLFh2nxXR1iG5wxD8OQ3C75kJF9gPcu8xzruBcFrkzD6ypK15rpvD9FWmCXlsZEqYFBQg7JwSDNZKkSYytWfyVNHnWFkfOiWabUZj7tRFLOlN4qZPFTw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686690061; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=H0U/9VUYOqkOwDSfCUTSeHKJW94lpdunrJEDcr8kuBY=; b=IxO2kUt4DGT5iMJkgFMcr3TA3FXWRu5a4TrceZIyDKqDdxCON2e5Mi/RD9M251l5n2TCbw/3ZpETbHhI8bUdBsh67HFPqGBfE79qnAjhRcNjUUjBTSTbqzTtm3e7Xp65dB6tpgSQsLtFK3WWbyrklJJd5IFrR7JCdnaJ7WBiWNY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686690061109755.8677740798458; Tue, 13 Jun 2023 14:01:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9B7d-0002Uq-8e; Tue, 13 Jun 2023 17:00:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9B7Z-0002Jk-Pw for qemu-devel@nongnu.org; Tue, 13 Jun 2023 17:00:10 -0400 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q9B7X-00071i-IO for qemu-devel@nongnu.org; Tue, 13 Jun 2023 17:00:09 -0400 Received: by mail-oi1-x22b.google.com with SMTP id 5614622812f47-39c7f7a66abso3317319b6e.0 for ; Tue, 13 Jun 2023 14:00:07 -0700 (PDT) Received: from grind.. ([177.170.117.210]) by smtp.gmail.com with ESMTPSA id q82-20020acaf255000000b003982a8a1e3fsm5619514oih.51.2023.06.13.14.00.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 14:00:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686690006; x=1689282006; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H0U/9VUYOqkOwDSfCUTSeHKJW94lpdunrJEDcr8kuBY=; b=KfnerICI1kpskFBIbjEji0xNAFXe2nZBoAamvQtwxZAGMnfxMYa7aCRT3nTCR/J/dA 5qklBjYYfQfVzvw1jRrJAoSypz/BSldMCnJqtrPxRviyX7zTBJY9SO5za3kGhtWMizdN lAhqPsmc8XTrL5qRBX8lUVrhFcWPiEDN3vuT7by7gF+riH5LR2A2D/nJV6sipZk1X7Za QNeU8MWb+CsYO7LtIYLcuLgus66/653VMMj1rQ9mf8gVSvChSbrA2inZ9u5lu+RfMISk JE6blGYH2uCm9KRq++CqFmP5TSQhyFlQ7O0VD+RkQ/5z1LyGW86s2ucXFgSqP2oxjv0j ZlXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686690006; x=1689282006; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H0U/9VUYOqkOwDSfCUTSeHKJW94lpdunrJEDcr8kuBY=; b=Mb9NlIRz3+6qfQzAAlj+7d0ODUVAhA0A2p4lNkgG0t3DqwGFucY2cR9PMLbewocUKw yqUfX30KLw9oDwMxaK6ckncKaUdbgcT/EyZ0c3qo8rotzbno3sFxa7SauNejca9y7Gv4 mLj/Sc1ZyhPXkMd8F4+HhtArTazHXCbd5x10vVPJTFpMAy75hslegXmmhEyJeHKurGxB CTsgBG/nfhWplg4C9UoffvsHRwA5JPy43aZms0t6VAAiHqIrwP3R9x2wWeeLjH3r1TyJ J4ylY7BwpiE8V8TnC93YKPSKXrqEGp6wCPLFE92nALuw4HY6BK44UHRXzMzk04tfHv7h lJKw== X-Gm-Message-State: AC+VfDw2pXwBCQV2HwHnG5SG5lJZFLON4tZ0i3hDW7SkUyCDiIy6p11h xS8Z7My3ss/19s5Ono2gf3k9R/rB1h+rjUQSVIk= X-Google-Smtp-Source: ACHHUZ6AszZlRuAody4/NGFueRXKjrmTb3VdUxGyYFDFoMonfbsn6EHMAn6ci5Ts1MsAKkwPnObcPQ== X-Received: by 2002:a05:6808:220c:b0:39a:98bc:10e8 with SMTP id bd12-20020a056808220c00b0039a98bc10e8mr5322684oib.28.1686690006320; Tue, 13 Jun 2023 14:00:06 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 17/18] target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper Date: Tue, 13 Jun 2023 17:58:56 -0300 Message-Id: <20230613205857.495165-18-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613205857.495165-1-dbarboza@ventanamicro.com> References: <20230613205857.495165-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1686690062710100001 Content-Type: text/plain; charset="utf-8" There are 2 places in which we need to get a pointer to a certain property of the cpu->cfg struct based on property offset. Next patch will add a couple more. Create a helper to avoid repeating this code over and over. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 0b6dff70de..3a9f7b0722 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -222,11 +222,15 @@ static KVMCPUConfig kvm_multi_ext_cfgs[] =3D { KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT), }; =20 +static void *kvmconfig_get_cfg_addr(RISCVCPU *cpu, KVMCPUConfig *kvmcfg) +{ + return (void *)&cpu->cfg + kvmcfg->offset; +} + static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig *multi_ext, uint32_t val) { - int cpu_cfg_offset =3D multi_ext->offset; - bool *ext_enabled =3D (void *)&cpu->cfg + cpu_cfg_offset; + bool *ext_enabled =3D kvmconfig_get_cfg_addr(cpu, multi_ext); =20 *ext_enabled =3D val; } @@ -234,8 +238,7 @@ static void kvm_cpu_cfg_set(RISCVCPU *cpu, KVMCPUConfig= *multi_ext, static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, KVMCPUConfig *multi_ext) { - int cpu_cfg_offset =3D multi_ext->offset; - bool *ext_enabled =3D (void *)&cpu->cfg + cpu_cfg_offset; + bool *ext_enabled =3D kvmconfig_get_cfg_addr(cpu, multi_ext); =20 return *ext_enabled; } --=20 2.40.1 From nobody Sat May 18 15:49:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1686690080; cv=none; d=zohomail.com; s=zohoarc; b=AbeDofSOY14+BoT+2aJUB9jJMAs4LSg7qS/ANxnkSV/6zaTUGq3TVIfUUwYtqNztwASvuR4uoz9OuGLU74uQH0wqkP9QN0AwnV3MOvPyDq7Qpm1C4H985vVSIsl2QE/RPPVK0XkAv8K+198oWyEPTdQOJKHkNUC98Hu8toP4S70= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686690080; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UmgHpltBv9j1kQYmnmMbSI6QLFwM8nliDr4+gOdlKMM=; b=M+nRKYdNmXMMJ4XLNc1wPNE18Kq9EvPfYg4lFEr04h0q4PsNmnPrJbTHXTSUpsd8RGqoaO4gmAFSfw51ca9lFOyNzEbAuwX/VXfJi1sJYkFBQKQ1Q8nFRXvmOem1sLB9v9UCdqkFCeff87ZLL0GiZOP3PHMEFNkK2ED/pv5Jdpg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686690080488367.78193677224044; Tue, 13 Jun 2023 14:01:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9B86-0002mE-Ew; Tue, 13 Jun 2023 17:00:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9B7n-0002a5-AS for qemu-devel@nongnu.org; Tue, 13 Jun 2023 17:00:24 -0400 Received: from mail-oo1-xc2c.google.com ([2607:f8b0:4864:20::c2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q9B7c-00072f-GA for qemu-devel@nongnu.org; Tue, 13 Jun 2023 17:00:16 -0400 Received: by mail-oo1-xc2c.google.com with SMTP id 006d021491bc7-558b70c715cso5639eaf.2 for ; Tue, 13 Jun 2023 14:00:10 -0700 (PDT) Received: from grind.. ([177.170.117.210]) by smtp.gmail.com with ESMTPSA id q82-20020acaf255000000b003982a8a1e3fsm5619514oih.51.2023.06.13.14.00.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 14:00:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686690009; x=1689282009; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UmgHpltBv9j1kQYmnmMbSI6QLFwM8nliDr4+gOdlKMM=; b=OiSbzSP+i8t9gMDNPfXBjgHrcg7DtQkD9TpsB3g8RCYld29j+I/VGmCZsQ6PhnWafv tCQ/8C3PrDoECWb+bqtYWod78925eVZepAsD4/9bXtSFNPsLlylYLJgzCGm/SAoNmyVh Nh0HiRfi833dWHylsSJNlPFW+Hi2OBYsjLdlY8PrRCO1KV203UqOdnx4gMFkx9ZlvxDk WxcOSWi1yTWjCQx/QMbt8K8UBJTYBcKOZYdqlzM35jQHztEAUnh4MlyPN4CqggI7ACtW v/VErxyA/2Mo84iHyjo+QyCyqSCTwGPxnvB1kHjXSaEUWQG1Y7qLVw2x++nEn/QJQyhF Hfww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686690009; x=1689282009; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UmgHpltBv9j1kQYmnmMbSI6QLFwM8nliDr4+gOdlKMM=; b=bDIB0wSgtLoQJfnnzfstITnSajQlQf1XpwU5R1PnU4aEXjm6JYaqMvnhTacO2/FwAm waIPSnILd66Gm5xtAirOEYPxGAySI4hEVONzRV+QlJOe+oolSS3LdaB/KXiUPK+11q8W jTjfyY/oAprVPN8qE4hAStdcjkGlPlFh1kV+cr9RwUJA8xp6+dRSodj3QwJIKq/aeSYP ImZm0KzvM1eFEwVHa0Fkjl1Jzn8YG6sF4P2RUKmZNP3rncR/LK1Im18VGxKR9UjvlNHN S25TbK4cH9ctUT6nFRsly+j1RGzCrp9MGD/S1vVK8H22KIlS1ALJ2gAFf9GwPyB1ldz2 hf/g== X-Gm-Message-State: AC+VfDyQISNflAPAcfvq6x5H8hLf80USTCKm6HIvzl16E5BOSw2+B4Nr abIh3wlgyOzGocx7NFT9pEnM6uG4yKiaBb1/T7Q= X-Google-Smtp-Source: ACHHUZ5znRE0Z3ovRGdDc1jTfVk3HEk3omp1zMa1Xo/LiVFcLLo2rK3C1p3GlPy9vDQUWz+5GZvVTw== X-Received: by 2002:a05:6808:1885:b0:395:eed6:5193 with SMTP id bi5-20020a056808188500b00395eed65193mr9038410oib.10.1686690009234; Tue, 13 Jun 2023 14:00:09 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 18/18] target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM Date: Tue, 13 Jun 2023 17:58:57 -0300 Message-Id: <20230613205857.495165-19-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230613205857.495165-1-dbarboza@ventanamicro.com> References: <20230613205857.495165-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1686690080863100001 Content-Type: text/plain; charset="utf-8" If we don't set a proper cbom_blocksize|cboz_blocksize in the FDT the Linux Kernel will fail to detect the availability of the CBOM/CBOZ extensions, regardless of the contents of the 'riscv,isa' DT prop. The FDT is being written using the cpu->cfg.cbom|z_blocksize attributes, so let's expose them as user properties like it is already done with TCG. This will also require us to determine proper blocksize values during init() time since the FDT is already created during realize(). We'll take a ride in kvm_riscv_init_multiext_cfg() to do it. Note that we don't need to fetch both cbom and cboz blocksizes every time: check for their parent extensions (icbom and icboz) and only read the blocksizes if needed. In contrast with cbom/z_blocksize properties from TCG, the user is not able to set any value that is different from the 'host' value when running KVM. KVM can be particularly harsh dealing with it: a ENOTSUPP can be thrown for the mere attempt of executing kvm_set_one_reg() for these 2 regs. Hopefully, we don't need to call kvm_set_one_reg() for these regs. We'll check if the user input matches the host value in kvm_cpu_set_cbomz_blksize(), the set() accessor for both blocksize properties. We'll fail fast since it's already known to not be supported. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 3a9f7b0722..ccd2375d8d 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -283,6 +283,42 @@ static void kvm_cpu_set_multi_ext_cfg(Object *obj, Vis= itor *v, kvm_cpu_cfg_set(cpu, multi_ext_cfg, value); } =20 +static KVMCPUConfig kvm_cbom_blocksize =3D { + .name =3D "cbom_blocksize", + .offset =3D CPUCFG(cbom_blocksize), + .kvm_reg_id =3D KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) +}; + +static KVMCPUConfig kvm_cboz_blocksize =3D { + .name =3D "cboz_blocksize", + .offset =3D CPUCFG(cboz_blocksize), + .kvm_reg_id =3D KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) +}; + +static void kvm_cpu_set_cbomz_blksize(Object *obj, Visitor *v, + const char *name, + void *opaque, Error **errp) +{ + KVMCPUConfig *cbomz_cfg =3D opaque; + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint16_t value, *host_val; + + if (!visit_type_uint16(v, name, &value, errp)) { + return; + } + + host_val =3D kvmconfig_get_cfg_addr(cpu, cbomz_cfg); + + if (value !=3D *host_val) { + error_report("Unable to set %s to a different value than " + "the host (%u)", + cbomz_cfg->name, *host_val); + exit(EXIT_FAILURE); + } + + cbomz_cfg->user_set =3D true; +} + static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) { CPURISCVState *env =3D &cpu->env; @@ -332,6 +368,14 @@ static void kvm_riscv_add_cpu_user_properties(Object *= cpu_obj) kvm_cpu_set_multi_ext_cfg, NULL, multi_cfg); } + + object_property_add(cpu_obj, "cbom_blocksize", "uint16", + NULL, kvm_cpu_set_cbomz_blksize, + NULL, &kvm_cbom_blocksize); + + object_property_add(cpu_obj, "cboz_blocksize", "uint16", + NULL, kvm_cpu_set_cbomz_blksize, + NULL, &kvm_cboz_blocksize); } =20 static int kvm_riscv_get_regs_core(CPUState *cs) @@ -647,6 +691,24 @@ static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, env->misa_ext =3D env->misa_ext_mask; } =20 +static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvm= cpu, + KVMCPUConfig *cbomz_cfg) +{ + CPURISCVState *env =3D &cpu->env; + struct kvm_one_reg reg; + int ret; + + reg.id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, + cbomz_cfg->kvm_reg_id); + reg.addr =3D (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); + ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); + if (ret !=3D 0) { + error_report("Unable to read KVM reg %s, error %d", + cbomz_cfg->name, ret); + exit(EXIT_FAILURE); + } +} + static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmc= pu) { CPURISCVState *env =3D &cpu->env; @@ -678,6 +740,14 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu,= KVMScratchCPU *kvmcpu) =20 kvm_cpu_cfg_set(cpu, multi_ext_cfg, val); } + + if (cpu->cfg.ext_icbom) { + kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cbom_blocksize); + } + + if (cpu->cfg.ext_icboz) { + kvm_riscv_read_cbomz_blksize(cpu, kvmcpu, &kvm_cboz_blocksize); + } } =20 void kvm_riscv_init_user_properties(Object *cpu_obj) --=20 2.40.1