From nobody Sat May 18 07:48:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1686116860; cv=none; d=zohomail.com; s=zohoarc; b=kse1k5mOHPXUjJqVpFq6qdVvRzxAjl2YR8XrJXuhUJkFK7OGOQhXQ6Dyfg3iA5+RmyBj2npWcKcvWqXR/gnOz7xxV1Hj8DotRMhYsJSnPeHY8XyfQDI851C0rah8DfBPejxgTcosX7RydFXwRo11FvrevwP+8dS+ebnULUzt1i4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1686116860; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fM6xm9cm+jVnnUxuzo389UJoVj8WYs/QWurw8xhZSYY=; b=TnccuOjfIKnSVW8fxNCvQt229V1RRotUGT75MTwE2eeFR50Hmy2HSf2Uix0FuIvFN5Bpw2e6TpKzuyAWBD4DF6f+VWj51R5YbLziICEG58/1rZV3keJMWrd6wdL/3JXrut8bIyBzKIPQ0LTB9pPGRAmy87aevjL+aqgGX68F0Yo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686116860439691.786567020567; Tue, 6 Jun 2023 22:47:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6m0n-0003rR-5r; Wed, 07 Jun 2023 01:47:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6m0l-0003qx-2e for qemu-devel@nongnu.org; Wed, 07 Jun 2023 01:47:11 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6m0Y-0006Pm-9H for qemu-devel@nongnu.org; Wed, 07 Jun 2023 01:47:10 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-653bed78635so181562b3a.0 for ; Tue, 06 Jun 2023 22:46:57 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:b7fa:ce59:1445:805a]) by smtp.gmail.com with ESMTPSA id fe16-20020a056a002f1000b0064d48d98260sm7640310pfb.156.2023.06.06.22.46.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jun 2023 22:46:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686116817; x=1688708817; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fM6xm9cm+jVnnUxuzo389UJoVj8WYs/QWurw8xhZSYY=; b=EcTQxN5e4VNg3qltERrM8V7IoiCjq8v/0GXouFi+rHMC1etHj5p/oWVkV5jGYU6IPD 7SqGrokY+C8gZkpdKeWM6s8rzbOxY26dd/wBRE1Xlw48u9yoll6D5txsTjux4aIaptq0 2WknH4DKRreZJzlceTScQ9FT6gmgQ9ehE1jm5IWckQTC1oPlbLFxdRDSM3Z/AVL/bWk9 yBvYztY+vAVxATnQFF4yQpgGN8O4WQpohXYBeEj5ioENmVdoM+qyotf7bpUZ2gPdIpaf xsmmSJeFRhc4H+7wc55wLKRRSIIGv0y/83gK75QXutHRuA32O+PpxFST1UV45ieYSL2x jZkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686116817; x=1688708817; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fM6xm9cm+jVnnUxuzo389UJoVj8WYs/QWurw8xhZSYY=; b=gMnF387Fc+ZNtH8RnmRhdPpuVYslgLCbFcPgXQ7sLxxSH2fU6LpA4Whl49cXFgUJ1C bANrOAkhA/KQnwUYctZ40wvcjJ6BtsM0o5/Z7Rgsqv8Pm7mHAnzPinAj4iqwQ9jPSGY+ IjFLv/wiuI0dzt0hEqI397EyAkmDqYX14z8r3mNHXuF3L0skJ0+a4nHAI81PJqIR37fg TDlFREfctNrDg4q54FRK4+1jLrQOck7iYwUnrENi6ahfN7hhA8GcgZ3XmcdTn505sXtb m9hSXO72kyrPFRwGne98470DgqQKAuH8rhmqC2pP1UWrPsopx+bE0KLh9iBqI8HYY2bH +zpA== X-Gm-Message-State: AC+VfDxb89aRJeR2YR54l7UsPhIDtzYaVOn+PCi1UCek0LswZylyzpVB 2s1Uwto4tLEZXCSMmg9MJMXMkCIIenJRPeiOeVQ= X-Google-Smtp-Source: ACHHUZ6wwjhFWTVi/vbmd9xIZ8S1zuJ/CN27hxPcVb7H8Hswi5yX09oOGRBjnF+LdueaJRUF1gj0iw== X-Received: by 2002:a05:6a20:4425:b0:103:b585:b587 with SMTP id ce37-20020a056a20442500b00103b585b587mr2203146pzb.13.1686116816587; Tue, 06 Jun 2023 22:46:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: sw@weilnetz.de Subject: [PATCH 1/2] tcg/tci: Adjust passing of MemOpIdx Date: Tue, 6 Jun 2023 22:46:53 -0700 Message-Id: <20230607054654.622010-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230607054654.622010-1-richard.henderson@linaro.org> References: <20230607054654.622010-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686116862266100002 Content-Type: text/plain; charset="utf-8" Since adding MO_ATOM_MASK, the maximum MemOpIdx requires 15 bits, which overflows the 12 bit field allocated for TCI memory ops. Expand the field to 16 bits for 2-operand memory ops, and place the value in TCG_REG_TMP for 3-operand memory ops (same as we already do for 4-operand memory ops). Cures a debug assert for aarch64, with FEAT_LSE enabled. Signed-off-by: Richard Henderson --- tcg/tci.c | 30 +++++++++++++----------------- tcg/tci/tcg-target.c.inc | 21 ++++----------------- 2 files changed, 17 insertions(+), 34 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 813572ff39..4640902c88 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -106,7 +106,7 @@ static void tci_args_rrm(uint32_t insn, TCGReg *r0, { *r0 =3D extract32(insn, 8, 4); *r1 =3D extract32(insn, 12, 4); - *m2 =3D extract32(insn, 20, 12); + *m2 =3D extract32(insn, 16, 16); } =20 static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2) @@ -141,15 +141,6 @@ static void tci_args_rrrc(uint32_t insn, *c3 =3D extract32(insn, 20, 4); } =20 -static void tci_args_rrrm(uint32_t insn, - TCGReg *r0, TCGReg *r1, TCGReg *r2, MemOpIdx *m3) -{ - *r0 =3D extract32(insn, 8, 4); - *r1 =3D extract32(insn, 12, 4); - *r2 =3D extract32(insn, 16, 4); - *m3 =3D extract32(insn, 20, 12); -} - static void tci_args_rrrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2, uint8_t *i3, uint8_t *i4) { @@ -929,8 +920,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; } else { - tci_args_rrrm(insn, &r0, &r1, &r2, &oi); + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); taddr =3D tci_uint64(regs[r2], regs[r1]); + oi =3D regs[r3]; } do_ld_i32: regs[r0] =3D tci_qemu_ld(env, taddr, oi, tb_ptr); @@ -941,8 +933,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D (uint32_t)regs[r1]; } else { - tci_args_rrrm(insn, &r0, &r1, &r2, &oi); + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); taddr =3D (uint32_t)regs[r2]; + oi =3D regs[r3]; } goto do_ld_i64; case INDEX_op_qemu_ld_a64_i64: @@ -972,8 +965,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchStat= e *env, tci_args_rrm(insn, &r0, &r1, &oi); taddr =3D regs[r1]; } else { - tci_args_rrrm(insn, &r0, &r1, &r2, &oi); + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); taddr =3D tci_uint64(regs[r2], regs[r1]); + oi =3D regs[r3]; } do_st_i32: tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr); @@ -985,9 +979,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchSta= te *env, tmp64 =3D regs[r0]; taddr =3D (uint32_t)regs[r1]; } else { - tci_args_rrrm(insn, &r0, &r1, &r2, &oi); + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); tmp64 =3D tci_uint64(regs[r1], regs[r0]); taddr =3D (uint32_t)regs[r2]; + oi =3D regs[r3]; } goto do_st_i64; case INDEX_op_qemu_st_a64_i64: @@ -1293,9 +1288,10 @@ int print_insn_tci(bfd_vma addr, disassemble_info *i= nfo) op_name, str_r(r0), str_r(r1), oi); break; case 3: - tci_args_rrrm(insn, &r0, &r1, &r2, &oi); - info->fprintf_func(info->stream, "%-12s %s, %s, %s, %x", - op_name, str_r(r0), str_r(r1), str_r(r2), o= i); + tci_args_rrrr(insn, &r0, &r1, &r2, &r3); + info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s", + op_name, str_r(r0), str_r(r1), + str_r(r2), str_r(r3)); break; case 4: tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index c9516a5e8b..5b456e1277 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -331,11 +331,11 @@ static void tcg_out_op_rrm(TCGContext *s, TCGOpcode o= p, { tcg_insn_unit insn =3D 0; =20 - tcg_debug_assert(m2 =3D=3D extract32(m2, 0, 12)); + tcg_debug_assert(m2 =3D=3D extract32(m2, 0, 16)); insn =3D deposit32(insn, 0, 8, op); insn =3D deposit32(insn, 8, 4, r0); insn =3D deposit32(insn, 12, 4, r1); - insn =3D deposit32(insn, 20, 12, m2); + insn =3D deposit32(insn, 16, 16, m2); tcg_out32(s, insn); } =20 @@ -392,20 +392,6 @@ static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode o= p, tcg_out32(s, insn); } =20 -static void tcg_out_op_rrrm(TCGContext *s, TCGOpcode op, - TCGReg r0, TCGReg r1, TCGReg r2, TCGArg m3) -{ - tcg_insn_unit insn =3D 0; - - tcg_debug_assert(m3 =3D=3D extract32(m3, 0, 12)); - insn =3D deposit32(insn, 0, 8, op); - insn =3D deposit32(insn, 8, 4, r0); - insn =3D deposit32(insn, 12, 4, r1); - insn =3D deposit32(insn, 16, 4, r2); - insn =3D deposit32(insn, 20, 12, m3); - tcg_out32(s, insn); -} - static void tcg_out_op_rrrbb(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, uint8_t b3, uint8_t b4) { @@ -860,7 +846,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_op_rrm(s, opc, args[0], args[1], args[2]); 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([2602:ae:1598:4c01:b7fa:ce59:1445:805a]) by smtp.gmail.com with ESMTPSA id fe16-20020a056a002f1000b0064d48d98260sm7640310pfb.156.2023.06.06.22.46.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jun 2023 22:46:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686116817; x=1688708817; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9WHe7sC6PSzbBVXVvmOEhsfQw8NBoIdms7kVdUmUQa0=; b=oH7fmUiFi661eVwIwCBhLOzmznBXlf4PnY1eaqtmOl9xXzLB1et/EOdL7JObK8Ak1D JV8k87B8IJfsUtzOoFVG9kkp2jVs1hLp2UvAnVCBCzuuZ3yQqWS8xcAHfr5n2w/pw+yq hCDlgyxmHyeyY6XyxpgkZc3qhQupBLtZD3jIt/23560Wn+GEj+Oaao8Ylrallt2JXITC 5xa5kwVhXT8e9+HvdLWp6g9dYNCt6jFWKxWaoxRyQIh3OKDTx4L6XdDZ2CrFWNPsofBj DI+dboTnYnsvoJRb0TI76tXpi9nHhpBvNLihDZ76o9swkCml5ttGu/Nop29FrdzDKJng ndHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686116818; x=1688708818; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9WHe7sC6PSzbBVXVvmOEhsfQw8NBoIdms7kVdUmUQa0=; b=kHUS3RvT5Zb67khnTM6UFIhVRfya9rholAOb/V3J5P4nHytgoftJsMqhWpR/PHivRq Oqb5lZebCPxXtu0A4lGIOVGX28NZcF1P9SCJBRXm+KMvE0RoBWCUeCpkKKPVOWfI9AL9 HavBVEh0x2hg8uRmiMUGfwIF38LiZIGe477AZnkFXDksdHGAygckB1vLXFgq7UkwXQEI UewddnsBE+Gl7vyXL3BVVW3MwIjb5k5KdGT9s7mj+UjKVmX/8iqRoyTUYmEIja0cYDw+ juCYUb0l0UXAyxNJqProx+aP4427gbGpdpFcW6nnmwkXZssqdOFaMFVQCtS4iSFlj097 UEUA== X-Gm-Message-State: AC+VfDxuW/AmELIajlqG16c4UsufTdfiwgILZzmPIsqFFegCBbkmIpOr jEEL7sxBtW50Y8t8gZOf6dA3Mxq1HMAlDxUfTKI= X-Google-Smtp-Source: ACHHUZ7q1/+YqkZxhbZgVq3kS1N8iaYUUe8KiViC8Yr1Idgmo6FPbBoQpsvC3FUYvbxWNs8qgK5vNw== X-Received: by 2002:aca:2219:0:b0:39a:a99a:2195 with SMTP id b25-20020aca2219000000b0039aa99a2195mr4585490oic.31.1686116817586; Tue, 06 Jun 2023 22:46:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: sw@weilnetz.de Subject: [PATCH 2/2] tcg/tci: Adjust call-clobbered regs for int128_t Date: Tue, 6 Jun 2023 22:46:54 -0700 Message-Id: <20230607054654.622010-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230607054654.622010-1-richard.henderson@linaro.org> References: <20230607054654.622010-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1686116858253100006 Content-Type: text/plain; charset="utf-8" We require either 2 or 4 registers to hold int128_t. Failure to do so results in a register allocation assert. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tci/tcg-target.c.inc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 5b456e1277..0037f904f1 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -179,8 +179,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcod= e op) } =20 static const int tcg_target_reg_alloc_order[] =3D { - TCG_REG_R2, - TCG_REG_R3, TCG_REG_R4, TCG_REG_R5, TCG_REG_R6, @@ -193,6 +191,9 @@ static const int tcg_target_reg_alloc_order[] =3D { TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, + /* Either 2 or 4 of these are call clobbered, so use them last. */ + TCG_REG_R3, + TCG_REG_R2, TCG_REG_R1, TCG_REG_R0, }; @@ -934,11 +935,11 @@ static void tcg_target_init(TCGContext *s) /* * The interpreter "registers" are in the local stack frame and * cannot be clobbered by the called helper functions. However, - * the interpreter assumes a 64-bit return value and assigns to + * the interpreter assumes a 128-bit return value and assigns to * the return value registers. */ tcg_target_call_clobber_regs =3D - MAKE_64BIT_MASK(TCG_REG_R0, 64 / TCG_TARGET_REG_BITS); + MAKE_64BIT_MASK(TCG_REG_R0, 128 / TCG_TARGET_REG_BITS); =20 s->reserved_regs =3D 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); --=20 2.34.1