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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=npiggin@gmail.com; helo=mail-oi1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1685835447847100007 Content-Type: text/plain; charset="utf-8" The chiptod is a pervasive facility which can keep TOD (time-of-day), synchronise it across multiple chips, and can move that TOD to or from the core timebase units. This driver implements basic emulation of chiptod registers sufficient to successfully run the skiboot chiptod synchronisation procedure (with the following TFMR and timebase state-machine implementation). The main way chiptod affects the rest of the system (relevant to the powernv model) is to interact with the timebase facility in the cores, influencing the timebase state machine and registers. The way this chiptod driver implements that interaction is with two new flags in the CPUPPCState env, one is use for the core timebase to indicate it is ready to receive a TOD from chiptod, the other used by chiptod to indicate that it has sent TOD to the core timebase. The core timebase will be implemented in later changes. Signed-off-by: Nicholas Piggin --- hw/ppc/meson.build | 1 + hw/ppc/pnv.c | 38 +++ hw/ppc/pnv_chiptod.c | 488 +++++++++++++++++++++++++++++++++++ hw/ppc/pnv_xscom.c | 2 + hw/ppc/trace-events | 4 + include/hw/ppc/pnv_chip.h | 3 + include/hw/ppc/pnv_chiptod.h | 64 +++++ include/hw/ppc/pnv_core.h | 3 + include/hw/ppc/pnv_xscom.h | 9 + target/ppc/cpu.h | 6 + 10 files changed, 618 insertions(+) create mode 100644 hw/ppc/pnv_chiptod.c create mode 100644 include/hw/ppc/pnv_chiptod.h diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build index c927337da0..afbf90e6da 100644 --- a/hw/ppc/meson.build +++ b/hw/ppc/meson.build @@ -45,6 +45,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files( 'pnv_core.c', 'pnv_lpc.c', 'pnv_psi.c', + 'pnv_chiptod.c', 'pnv_occ.c', 'pnv_sbe.c', 'pnv_bmc.c', diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index dbdeba6c31..ce5e7d7582 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1414,6 +1414,8 @@ static void pnv_chip_power9_instance_init(Object *obj) =20 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); =20 + object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHI= PTOD); + object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); =20 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); @@ -1558,6 +1560,15 @@ static void pnv_chip_power9_realize(DeviceState *dev= , Error **errp) chip->dt_isa_nodename =3D g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0= ", (uint64_t) PNV9_LPCM_BASE(chip= )); =20 + /* ChipTOD */ + object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), + &error_abort); + if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, + &chip9->chiptod.xscom_regs); + /* Create the simplified OCC model */ if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { return; @@ -1644,6 +1655,7 @@ static void pnv_chip_power10_instance_init(Object *ob= j) "xive-fabric"); object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); + object_initialize_child(obj, "chiptod", &chip10->chiptod, TYPE_PNV10_C= HIPTOD); object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER= ); @@ -1773,6 +1785,15 @@ static void pnv_chip_power10_realize(DeviceState *de= v, Error **errp) chip->dt_isa_nodename =3D g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0= ", (uint64_t) PNV10_LPCM_BASE(chi= p)); =20 + /* ChipTOD */ + object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip= ), + &error_abort); + if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { + return; + } + pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, + &chip10->chiptod.xscom_regs); + /* Create the simplified OCC model */ if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { return; @@ -1938,6 +1959,23 @@ static void pnv_chip_core_realize(PnvChip *chip, Err= or **errp) } } =20 +PnvCore *pnv_get_vcpu_by_xscom_base(PnvChip *chip, uint32_t xscom_base) +{ + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); + int i; + + for (i =3D 0; i < chip->nr_cores; i++) { + PnvCore *pc =3D chip->cores[i]; + CPUCore *cc =3D CPU_CORE(pc); + int core_hwid =3D cc->core_id; + + if (pcc->xscom_core_base(chip, core_hwid) =3D=3D xscom_base) { + return pc; + } + } + return NULL; +} + static void pnv_chip_realize(DeviceState *dev, Error **errp) { PnvChip *chip =3D PNV_CHIP(dev); diff --git a/hw/ppc/pnv_chiptod.c b/hw/ppc/pnv_chiptod.c new file mode 100644 index 0000000000..04ef703e0f --- /dev/null +++ b/hw/ppc/pnv_chiptod.c @@ -0,0 +1,488 @@ +/* + * QEMU PowerPC PowerNV Emulation of some CHIPTOD behaviour + * + * Copyright (c) 2022-2023, IBM Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, version 2, as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "target/ppc/cpu.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/ppc/fdt.h" +#include "hw/ppc/ppc.h" +#include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_chip.h" +#include "hw/ppc/pnv_core.h" +#include "hw/ppc/pnv_xscom.h" +#include "hw/ppc/pnv_chiptod.h" +#include "trace.h" + +#include + +/* TOD chip XSCOM addresses */ +#define TOD_M_PATH_CTRL_REG 0x00000000 /* Master Path ctrl reg= */ +#define TOD_PRI_PORT_0_CTRL_REG 0x00000001 /* Primary port0 ctrl r= eg */ +#define TOD_PRI_PORT_1_CTRL_REG 0x00000002 /* Primary port1 ctrl r= eg */ +#define TOD_SEC_PORT_0_CTRL_REG 0x00000003 /* Secondary p0 ctrl re= g */ +#define TOD_SEC_PORT_1_CTRL_REG 0x00000004 /* Secondary p1 ctrl re= g */ +#define TOD_S_PATH_CTRL_REG 0x00000005 /* Slave Path ctrl reg = */ +#define TOD_I_PATH_CTRL_REG 0x00000006 /* Internal Path ctrl r= eg */ + +/* -- TOD primary/secondary master/slave control register -- */ +#define TOD_PSS_MSS_CTRL_REG 0x00000007 + +/* -- TOD primary/secondary master/slave status register -- */ +#define TOD_PSS_MSS_STATUS_REG 0x00000008 + +/* TOD chip XSCOM addresses */ +#define TOD_CHIP_CTRL_REG 0x00000010 /* Chip control reg */ + +#define TOD_TX_TTYPE_0_REG 0x00000011 +#define TOD_TX_TTYPE_1_REG 0x00000012 /* PSS switch reg */ +#define TOD_TX_TTYPE_2_REG 0x00000013 /* Enable step checkers= */ +#define TOD_TX_TTYPE_3_REG 0x00000014 /* Request TOD reg */ +#define TOD_TX_TTYPE_4_REG 0x00000015 /* Send TOD reg */ +#define TOD_TX_TTYPE_5_REG 0x00000016 /* Invalidate TOD reg */ + +#define TOD_MOVE_TOD_TO_TB_REG 0x00000017 +#define TOD_LOAD_TOD_MOD_REG 0x00000018 +#define TOD_LOAD_TOD_REG 0x00000021 +#define TOD_FSM_REG 0x00000024 + +#define TOD_TX_TTYPE_CTRL_REG 0x00000027 /* TX TTYPE Control reg= */ +#define TOD_TX_TTYPE_PIB_SLAVE_ADDR PPC_BITMASK(26, 31) + +/* -- TOD Error interrupt register -- */ +#define TOD_ERROR_REG 0x00000030 + +/* PC unit PIB address which recieves the timebase transfer from TOD */ +#define PC_TOD 0x4A3 + +static uint64_t pnv_chiptod_xscom_read(void *opaque, hwaddr addr, + unsigned size) +{ + PnvChipTOD *chiptod =3D PNV_CHIPTOD(opaque); + uint32_t offset =3D addr >> 3; + uint64_t val =3D 0; + + switch (offset) { + case TOD_PSS_MSS_STATUS_REG: + /* + * ChipTOD does not support configurations other than primary + * master, does not support errors, etc. + */ + val |=3D PPC_BITMASK(6,10); /* STEP checker validity */ + val |=3D PPC_BIT(12); /* Primary config master path select */ + val |=3D PPC_BIT(20); /* Is running */ + val |=3D PPC_BIT(21); /* Is using primary config */ + val |=3D PPC_BIT(26); /* Is using master path select */ + + if (chiptod->primary) { + val |=3D PPC_BIT(23); /* Is active master */ + } else if (chiptod->secondary) { + val |=3D PPC_BIT(24); /* Is backup master */ + } + break; + case TOD_PSS_MSS_CTRL_REG: + val =3D chiptod->pss_mss_ctrl_reg; + break; + case TOD_TX_TTYPE_CTRL_REG: + val =3D 0; + break; + case TOD_ERROR_REG: + val =3D chiptod->tod_error; + break; + case TOD_FSM_REG: + if (chiptod->tod_state =3D=3D tod_running) { + val |=3D PPC_BIT(4); + } + break; + default: + qemu_log_mask(LOG_UNIMP, "pnv_chiptod: unimplemented register: Ox%" + HWADDR_PRIx "\n", addr >> 3); + } + + trace_pnv_chiptod_xscom_read(addr >> 3, val); + + return val; +} + +static void chiptod_power9_send_remotes(PnvChipTOD *chiptod) +{ + PnvMachineState *pnv =3D PNV_MACHINE(qdev_get_machine()); + int i; + + for (i =3D 0; i < pnv->num_chips; i++) { + Pnv9Chip *chip9 =3D PNV9_CHIP(pnv->chips[i]); + if (&chip9->chiptod !=3D chiptod) { + chip9->chiptod.tod_state =3D tod_running; + } + } +} + +static void chiptod_power10_send_remotes(PnvChipTOD *chiptod) +{ + PnvMachineState *pnv =3D PNV_MACHINE(qdev_get_machine()); + int i; + + for (i =3D 0; i < pnv->num_chips; i++) { + Pnv10Chip *chip10 =3D PNV10_CHIP(pnv->chips[i]); + if (&chip10->chiptod !=3D chiptod) { + chip10->chiptod.tod_state =3D tod_running; + } + } +} + +static void chiptod_power9_invalidate_remotes(PnvChipTOD *chiptod) +{ + PnvMachineState *pnv =3D PNV_MACHINE(qdev_get_machine()); + int i; + + for (i =3D 0; i < pnv->num_chips; i++) { + Pnv9Chip *chip9 =3D PNV9_CHIP(pnv->chips[i]); + if (&chip9->chiptod !=3D chiptod) { + chip9->chiptod.tod_state =3D tod_not_set; + } + } +} + +static void chiptod_power10_invalidate_remotes(PnvChipTOD *chiptod) +{ + PnvMachineState *pnv =3D PNV_MACHINE(qdev_get_machine()); + int i; + + for (i =3D 0; i < pnv->num_chips; i++) { + Pnv10Chip *chip10 =3D PNV10_CHIP(pnv->chips[i]); + if (&chip10->chiptod !=3D chiptod) { + chip10->chiptod.tod_state =3D tod_not_set; + } + } +} + +static void pnv_chiptod_xscom_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size, + bool is_power9) +{ + PnvChipTOD *chiptod =3D PNV_CHIPTOD(opaque); + uint32_t offset =3D addr >> 3; + + trace_pnv_chiptod_xscom_write(addr >> 3, val); + + switch (offset) { + case TOD_PSS_MSS_CTRL_REG: + /* Is this correct? */ + if (chiptod->primary) { + val |=3D PPC_BIT(1); /* TOD is master */ + } else { + val &=3D ~PPC_BIT(1); + } + val |=3D PPC_BIT(2); /* Drawer is master (don't simulate multi-dra= wer) */ + chiptod->pss_mss_ctrl_reg =3D val & PPC_BITMASK(0, 31); + break; + + case TOD_TX_TTYPE_CTRL_REG: + if (val & PPC_BIT(35)) { /* SCOM addressing */ + uint32_t addr =3D val >> 32; + uint32_t reg =3D addr & 0xfff; + PnvCore *pc; + + if (reg !=3D PC_TOD) { + qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: SCOM addressi= ng: " + "unimplemented slave register 0x%" PRIx32 "\= n", + reg); + return; + } + + /* + * This may not deal with P10 big-core addressing at the momen= t. + * The big-core code in skiboot syncs small cores, but it targ= ets + * the even PIR (first small-core) when syncing second small-c= ore. + */ + pc =3D pnv_get_vcpu_by_xscom_base(chiptod->chip, addr & ~0xfff= ); + if (pc) { + /* + * If TCG implements SMT, TFMR is a per-core SPR and should + * be updated such that it is reflected in all threads. + * Same for TB if the chiptod model ever actually adjusted= it. + */ + chiptod->slave_cpu_target =3D pc->threads[0]; + } else { + chiptod->slave_cpu_target =3D NULL; + qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write r= eg" + " TOD_TX_TTYPE_CTRL_REG val 0x%" PRIx64 + " invalid slave PIR\n", val); + } + + } else { /* PIR addressing */ + uint32_t pir; + + if (!is_power9) { + qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: PIR addressin= g" + " is only implemented for POWER9\n"); + return; + } + + pir =3D (GETFIELD(TOD_TX_TTYPE_PIB_SLAVE_ADDR, val) & 0x1f) <<= 2; + chiptod->slave_cpu_target =3D ppc_get_vcpu_by_pir(pir); + if (chiptod->slave_cpu_target =3D=3D NULL) { + qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write r= eg" + " TOD_TX_TTYPE_CTRL_REG val 0x%" PRIx64 + " invalid slave PIR 0x%" PRIx32 "\n", val, p= ir); + } + } + break; + case TOD_ERROR_REG: + chiptod->tod_error &=3D ~val; + break; + case TOD_LOAD_TOD_MOD_REG: + if (!(val & PPC_BIT(0))) { + qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg" + " TOD_LOAD_TOD_MOD_REG with bad val 0x%016lx\n",= val); + } else { + chiptod->tod_state =3D tod_not_set; + } + break; + case TOD_LOAD_TOD_REG: + chiptod->tod_state =3D tod_running; + break; + case TOD_MOVE_TOD_TO_TB_REG: + if (!(val & PPC_BIT(0))) { + qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg" + " TOD_MOVE_TOD_TO_TB_REG with bad val 0x%016lx\n= ", + val); + } else if (chiptod->slave_cpu_target =3D=3D NULL) { + qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write reg" + " TOD_MOVE_TOD_TO_TB_REG with no slave target\n"= ); + } else { + PowerPCCPU *cpu =3D chiptod->slave_cpu_target; + CPUPPCState *env =3D &cpu->env; + + if (env->tb_ready_for_tod) { + env->tod_sent_to_tb =3D 1; + } else { + qemu_log_mask(LOG_GUEST_ERROR, "pnv_chiptod: xscom write r= eg" + " TOD_MOVE_TOD_TO_TB_REG with TB not ready t= o" + " receive TOD\n"); + } + } + break; + case TOD_TX_TTYPE_4_REG: + if (is_power9) { + chiptod_power9_send_remotes(chiptod); + } else { + chiptod_power10_send_remotes(chiptod); + } + break; + case TOD_TX_TTYPE_5_REG: + if (is_power9) { + chiptod_power9_invalidate_remotes(chiptod); + } else { + chiptod_power10_invalidate_remotes(chiptod); + } + break; + default: + qemu_log_mask(LOG_UNIMP, "pnv_chiptod: unimplemented register: Ox%" + HWADDR_PRIx "\n", addr >> 3); + } +} + +static void pnv_chiptod_power9_xscom_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + pnv_chiptod_xscom_write(opaque, addr, val, size, true); +} + +static const MemoryRegionOps pnv_chiptod_power9_xscom_ops =3D { + .read =3D pnv_chiptod_xscom_read, + .write =3D pnv_chiptod_power9_xscom_write, + .valid.min_access_size =3D 8, + .valid.max_access_size =3D 8, + .impl.min_access_size =3D 8, + .impl.max_access_size =3D 8, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + +static int pnv_chiptod_dt_xscom(PnvXScomInterface *dev, void *fdt, + int xscom_offset, + const char compat[], size_t compat_size) +{ + PnvChipTOD *chiptod =3D PNV_CHIPTOD(dev); + g_autofree char *name =3D NULL; + int offset; + uint32_t lpc_pcba =3D PNV9_XSCOM_CHIPTOD_BASE; + uint32_t reg[] =3D { + cpu_to_be32(lpc_pcba), + cpu_to_be32(PNV9_XSCOM_CHIPTOD_SIZE) + }; + + name =3D g_strdup_printf("chiptod@%x", lpc_pcba); + offset =3D fdt_add_subnode(fdt, xscom_offset, name); + _FDT(offset); + + if (chiptod->primary) { + _FDT((fdt_setprop(fdt, offset, "primary", NULL, 0))); + } else if (chiptod->secondary) { + _FDT((fdt_setprop(fdt, offset, "secondary", NULL, 0))); + } + + _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); + _FDT((fdt_setprop(fdt, offset, "compatible", compat, compat_size))); + return 0; +} + +static int pnv_chiptod_power9_dt_xscom(PnvXScomInterface *dev, void *fdt, + int xscom_offset) +{ + const char compat[] =3D "ibm,power-chiptod\0ibm,power9-chiptod"; + + return pnv_chiptod_dt_xscom(dev, fdt, xscom_offset, compat, sizeof(com= pat)); +} + +static Property pnv_chiptod_properties[] =3D { + DEFINE_PROP_LINK("chip", PnvChipTOD , chip, TYPE_PNV_CHIP, PnvChip *), + DEFINE_PROP_END_OF_LIST(), +}; + +static void pnv_chiptod_power9_class_init(ObjectClass *klass, void *data) +{ + PnvChipTODClass *pctc =3D PNV_CHIPTOD_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + PnvXScomInterfaceClass *xdc =3D PNV_XSCOM_INTERFACE_CLASS(klass); + + dc->desc =3D "PowerNV ChipTOD Controller (POWER9)"; + device_class_set_props(dc, pnv_chiptod_properties); + + xdc->dt_xscom =3D pnv_chiptod_power9_dt_xscom; + + pctc->xscom_size =3D PNV_XSCOM_CHIPTOD_SIZE; + pctc->xscom_ops =3D &pnv_chiptod_power9_xscom_ops; +} + +static const TypeInfo pnv_chiptod_power9_type_info =3D { + .name =3D TYPE_PNV9_CHIPTOD, + .parent =3D TYPE_PNV_CHIPTOD, + .instance_size =3D sizeof(PnvChipTOD), + .class_init =3D pnv_chiptod_power9_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_PNV_XSCOM_INTERFACE }, + { } + } +}; + +static void pnv_chiptod_power10_xscom_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + pnv_chiptod_xscom_write(opaque, addr, val, size, false); +} + +static const MemoryRegionOps pnv_chiptod_power10_xscom_ops =3D { + .read =3D pnv_chiptod_xscom_read, + .write =3D pnv_chiptod_power10_xscom_write, + .valid.min_access_size =3D 8, + .valid.max_access_size =3D 8, + .impl.min_access_size =3D 8, + .impl.max_access_size =3D 8, + .endianness =3D DEVICE_BIG_ENDIAN, +}; + +static int pnv_chiptod_power10_dt_xscom(PnvXScomInterface *dev, void *fdt, + int xscom_offset) +{ + const char compat[] =3D "ibm,power-chiptod\0ibm,power10-chiptod"; + + return pnv_chiptod_dt_xscom(dev, fdt, xscom_offset, compat, sizeof(com= pat)); +} + +static void pnv_chiptod_power10_class_init(ObjectClass *klass, void *data) +{ + PnvChipTODClass *pctc =3D PNV_CHIPTOD_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + PnvXScomInterfaceClass *xdc =3D PNV_XSCOM_INTERFACE_CLASS(klass); + + dc->desc =3D "PowerNV ChipTOD Controller (POWER10)"; + device_class_set_props(dc, pnv_chiptod_properties); + + xdc->dt_xscom =3D pnv_chiptod_power10_dt_xscom; + + pctc->xscom_size =3D PNV_XSCOM_CHIPTOD_SIZE; + pctc->xscom_ops =3D &pnv_chiptod_power10_xscom_ops; +} + +static const TypeInfo pnv_chiptod_power10_type_info =3D { + .name =3D TYPE_PNV10_CHIPTOD, + .parent =3D TYPE_PNV_CHIPTOD, + .instance_size =3D sizeof(PnvChipTOD), + .class_init =3D pnv_chiptod_power10_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_PNV_XSCOM_INTERFACE }, + { } + } +}; + +static void pnv_chiptod_realize(DeviceState *dev, Error **errp) +{ + static bool got_primary =3D false; + static bool got_secondary =3D false; + + PnvChipTOD *chiptod =3D PNV_CHIPTOD(dev); + PnvChipTODClass *pctc =3D PNV_CHIPTOD_GET_CLASS(chiptod); + + if (!got_primary) { + got_primary =3D true; + chiptod->primary =3D true; + chiptod->pss_mss_ctrl_reg |=3D PPC_BIT(1); /* TOD is master */ + } else if (!got_secondary) { + got_secondary =3D true; + chiptod->secondary =3D true; + } + /* Drawer is master (we do not simulate multi-drawer) */ + chiptod->pss_mss_ctrl_reg |=3D PPC_BIT(2); + chiptod->tod_state =3D tod_running; + + /* XScom regions for ChipTOD registers */ + pnv_xscom_region_init(&chiptod->xscom_regs, OBJECT(dev), + pctc->xscom_ops, chiptod, "xscom-chiptod", + pctc->xscom_size); +} + +static void pnv_chiptod_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D pnv_chiptod_realize; + dc->desc =3D "PowerNV ChipTOD Controller"; + dc->user_creatable =3D false; +} + +static const TypeInfo pnv_chiptod_type_info =3D { + .name =3D TYPE_PNV_CHIPTOD, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(PnvChipTOD), + .class_init =3D pnv_chiptod_class_init, + .class_size =3D sizeof(PnvChipTODClass), + .abstract =3D true, +}; + +static void pnv_chiptod_register_types(void) +{ + type_register_static(&pnv_chiptod_type_info); + type_register_static(&pnv_chiptod_power9_type_info); + type_register_static(&pnv_chiptod_power10_type_info); +} + +type_init(pnv_chiptod_register_types); diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index d820e05e40..5bbbd3a7a9 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -298,6 +298,8 @@ int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_off= set, _FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0))); if (chip->chip_id =3D=3D 0) { _FDT((fdt_setprop(fdt, xscom_offset, "primary", NULL, 0))); + } else if (chip->chip_id =3D=3D 1) { + _FDT((fdt_setprop(fdt, xscom_offset, "secondary", NULL, 0))); } =20 args.fdt =3D fdt; diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index f670e8906c..57c4f265ef 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -95,6 +95,10 @@ vof_write(uint32_t ih, unsigned cb, const char *msg) "ih= =3D0x%x [%u] \"%s\"" vof_avail(uint64_t start, uint64_t end, uint64_t size) "0x%"PRIx64"..0x%"P= RIx64" size=3D0x%"PRIx64 vof_claimed(uint64_t start, uint64_t end, uint64_t size) "0x%"PRIx64"..0x%= "PRIx64" size=3D0x%"PRIx64 =20 +# pnv_chiptod.c +pnv_chiptod_xscom_read(uint64_t addr, uint64_t val) "addr 0x%" PRIx64 " va= l 0x%" PRIx64 +pnv_chiptod_xscom_write(uint64_t addr, uint64_t val) "addr 0x%" PRIx64 " v= al 0x%" PRIx64 + # pnv_sbe.c pnv_sbe_xscom_ctrl_read(uint64_t addr, uint64_t val) "addr 0x%" PRIx64 " v= al 0x%" PRIx64 pnv_sbe_xscom_ctrl_write(uint64_t addr, uint64_t val) "addr 0x%" PRIx64 " = val 0x%" PRIx64 diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h index 53e1d921d7..d22c013e7d 100644 --- a/include/hw/ppc/pnv_chip.h +++ b/include/hw/ppc/pnv_chip.h @@ -2,6 +2,7 @@ #define PPC_PNV_CHIP_H =20 #include "hw/pci-host/pnv_phb4.h" +#include "hw/ppc/pnv_chiptod.h" #include "hw/ppc/pnv_core.h" #include "hw/ppc/pnv_homer.h" #include "hw/ppc/pnv_lpc.h" @@ -77,6 +78,7 @@ struct Pnv9Chip { PnvXive xive; Pnv9Psi psi; PnvLpcController lpc; + PnvChipTOD chiptod; PnvOCC occ; PnvSBE sbe; PnvHomer homer; @@ -106,6 +108,7 @@ struct Pnv10Chip { PnvXive2 xive; Pnv9Psi psi; PnvLpcController lpc; + PnvChipTOD chiptod; PnvOCC occ; PnvSBE sbe; PnvHomer homer; diff --git a/include/hw/ppc/pnv_chiptod.h b/include/hw/ppc/pnv_chiptod.h new file mode 100644 index 0000000000..6723b07d93 --- /dev/null +++ b/include/hw/ppc/pnv_chiptod.h @@ -0,0 +1,64 @@ +/* + * QEMU PowerPC PowerNV Emulation of some CHIPTOD behaviour + * + * Copyright (c) 2022-2023, IBM Corporation. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef PPC_PNV_CHIPTOD_H +#define PPC_PNV_CHIPTOD_H + +#include "qom/object.h" + +#define TYPE_PNV_CHIPTOD "pnv-chiptod" +OBJECT_DECLARE_TYPE(PnvChipTOD, PnvChipTODClass, PNV_CHIPTOD) +#define TYPE_PNV9_CHIPTOD TYPE_PNV_CHIPTOD "-POWER9" +DECLARE_INSTANCE_CHECKER(PnvChipTOD, PNV9_CHIPTOD, TYPE_PNV9_CHIPTOD) +#define TYPE_PNV10_CHIPTOD TYPE_PNV_CHIPTOD "-POWER10" +DECLARE_INSTANCE_CHECKER(PnvChipTOD, PNV10_CHIPTOD, TYPE_PNV10_CHIPTOD) + +enum tod_state { + tod_error =3D 0, + tod_not_set =3D 7, + tod_not_set_step =3D 11, + tod_running =3D 2, + tod_running_step =3D 10, + tod_running_sync =3D 14, + tod_wait_for_sync =3D 13, + tod_stopped =3D 1, +}; + +struct PnvChipTOD { + DeviceState xd; + + PnvChip *chip; + MemoryRegion xscom_regs; + + bool primary; + bool secondary; + enum tod_state tod_state; + uint64_t tod_error; + uint64_t pss_mss_ctrl_reg; + PowerPCCPU *slave_cpu_target; +}; + +struct PnvChipTODClass { + DeviceClass parent_class; + + int xscom_size; + const MemoryRegionOps *xscom_ops; +}; + +#endif /* PPC_PNV_CHIPTOD_H */ diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index 3d75706e95..832b339ed6 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -69,4 +69,7 @@ struct PnvQuad { uint32_t quad_id; MemoryRegion xscom_regs; }; + +PnvCore *pnv_get_vcpu_by_xscom_base(PnvChip *chip, uint32_t xscom_base); + #endif /* PPC_PNV_CORE_H */ diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index cbe848d27b..530f89af55 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -64,6 +64,9 @@ struct PnvXScomInterfaceClass { #define PNV_XSCOM_PSIHB_BASE 0x2010900 #define PNV_XSCOM_PSIHB_SIZE 0x20 =20 +#define PNV_XSCOM_CHIPTOD_BASE 0x0040000 +#define PNV_XSCOM_CHIPTOD_SIZE 0x31 + #define PNV_XSCOM_OCC_BASE 0x0066000 #define PNV_XSCOM_OCC_SIZE 0x6000 =20 @@ -90,6 +93,9 @@ struct PnvXScomInterfaceClass { ((uint64_t)(((core) & 0x1C) + 0x40) << 22) #define PNV9_XSCOM_EQ_SIZE 0x100000 =20 +#define PNV9_XSCOM_CHIPTOD_BASE PNV_XSCOM_CHIPTOD_BASE +#define PNV9_XSCOM_CHIPTOD_SIZE PNV_XSCOM_CHIPTOD_SIZE + #define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE #define PNV9_XSCOM_OCC_SIZE 0x8000 =20 @@ -138,6 +144,9 @@ struct PnvXScomInterfaceClass { #define PNV10_XSCOM_PSIHB_BASE 0x3011D00 #define PNV10_XSCOM_PSIHB_SIZE 0x100 =20 +#define PNV10_XSCOM_CHIPTOD_BASE PNV9_XSCOM_CHIPTOD_BASE +#define PNV10_XSCOM_CHIPTOD_SIZE PNV9_XSCOM_CHIPTOD_SIZE + #define PNV10_XSCOM_OCC_BASE PNV9_XSCOM_OCC_BASE #define PNV10_XSCOM_OCC_SIZE PNV9_XSCOM_OCC_SIZE =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 8c30c59a56..d73cce8474 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1172,6 +1172,12 @@ struct CPUArchState { uint32_t tlb_need_flush; /* Delayed flush needed */ #define TLB_NEED_LOCAL_FLUSH 0x1 #define TLB_NEED_GLOBAL_FLUSH 0x2 + +#if defined(TARGET_PPC64) + /* PowerNV chiptod / timebase facility state. */ + int tb_ready_for_tod; /* core TB ready to receive TOD from chiptod */ + int tod_sent_to_tb; /* chiptod sent TOD to the core TB */ +#endif #endif =20 /* Other registers */ --=20 2.40.1 From nobody Fri May 17 11:05:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1685835445; cv=none; d=zohomail.com; s=zohoarc; b=Cyxpg9+3ydBWkaWfS1jRWE40V/tLJXXY+j1BjbgC8OE2iQo0ImctzUhMYb4T0DCjma/Js1HMq5jZBdUHrez/lxIyjwbMfSPhMOl2JoolJgK3WMalTFZeBOLmLe0X4uncVFXcGAyo6H8jJR/hoSmUqZk/fZG6MRihPbkP/k21I9o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Sat, 03 Jun 2023 16:36:31 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH 2/4] target/ppc: Tidy POWER book4 SPR registration Date: Sun, 4 Jun 2023 09:36:10 +1000 Message-Id: <20230603233612.125879-3-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230603233612.125879-1-npiggin@gmail.com> References: <20230603233612.125879-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=npiggin@gmail.com; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1685835447235100005 Content-Type: text/plain; charset="utf-8" POWER book4 (implementation-specific) SPRs are sometimes in their own functions, but in other cases are mixed with architected SPRs. Do some spring cleaning on these. Signed-off-by: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater --- target/ppc/cpu_init.c | 92 ++++++++++++++++++++++++++++--------------- 1 file changed, 60 insertions(+), 32 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index e9717b8169..da0f7a7159 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5374,31 +5374,6 @@ static void register_book3s_ids_sprs(CPUPPCState *en= v) &spr_read_generic, SPR_NOACCESS, &spr_read_generic, NULL, 0x00000000); - spr_register_hv(env, SPR_HID0, "HID0", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_core_write_generic, - 0x00000000); - spr_register_hv(env, SPR_TSCR, "TSCR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic32, - 0x00000000); - spr_register_hv(env, SPR_HMER, "HMER", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_hmer, - 0x00000000); - spr_register_hv(env, SPR_HMEER, "HMEER", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); - spr_register_hv(env, SPR_TFMR, "TFMR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); spr_register_hv(env, SPR_LPIDR, "LPIDR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, @@ -5454,11 +5429,6 @@ static void register_book3s_ids_sprs(CPUPPCState *en= v) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); - spr_register_hv(env, SPR_LDBAR, "LDBAR", - SPR_NOACCESS, SPR_NOACCESS, - SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, - 0x00000000); } =20 static void register_rmor_sprs(CPUPPCState *env) @@ -5665,14 +5635,65 @@ static void register_power8_ic_sprs(CPUPPCState *en= v) #endif } =20 +/* SPRs specific to IBM POWER CPUs */ +static void register_power_common_book4_sprs(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + spr_register_hv(env, SPR_HID0, "HID0", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_core_write_generic, + 0x00000000); + spr_register_hv(env, SPR_TSCR, "TSCR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic32, + 0x00000000); + spr_register_hv(env, SPR_HMER, "HMER", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_hmer, + 0x00000000); + spr_register_hv(env, SPR_HMEER, "HMEER", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_TFMR, "TFMR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_LDBAR, "LDBAR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); +#endif +} + +static void register_power9_book4_sprs(CPUPPCState *env) +{ + /* Add a number of P9 book4 registers */ + register_power_common_book4_sprs(env); +#if !defined(CONFIG_USER_ONLY) + spr_register_kvm(env, SPR_WORT, "WORT", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_WORT, 0); +#endif +} + static void register_power8_book4_sprs(CPUPPCState *env) { /* Add a number of P8 book4 registers */ + register_power_common_book4_sprs(env); #if !defined(CONFIG_USER_ONLY) spr_register_kvm(env, SPR_ACOP, "ACOP", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, KVM_REG_PPC_ACOP, 0); + /* PID is only in BookE in ISA v2.07 */ spr_register_kvm(env, SPR_BOOKS_PID, "PID", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_pidr, @@ -5688,10 +5709,12 @@ static void register_power7_book4_sprs(CPUPPCState = *env) { /* Add a number of P7 book4 registers */ #if !defined(CONFIG_USER_ONLY) + register_power_common_book4_sprs(env); spr_register_kvm(env, SPR_ACOP, "ACOP", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, KVM_REG_PPC_ACOP, 0); + /* PID is only in BookE in ISA v2.06 */ spr_register_kvm(env, SPR_BOOKS_PID, "PID", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic32, @@ -5725,6 +5748,11 @@ static void register_power9_mmu_sprs(CPUPPCState *en= v) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x0000000000000000); + /* PID is part of the BookS ISA from v3.0 */ + spr_register_kvm(env, SPR_BOOKS_PID, "PID", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_pidr, + KVM_REG_PPC_PID, 0); #endif } =20 @@ -6278,7 +6306,7 @@ static void init_proc_POWER9(CPUPPCState *env) register_power8_dpdes_sprs(env); register_vtb_sprs(env); register_power8_ic_sprs(env); - register_power8_book4_sprs(env); + register_power9_book4_sprs(env); register_power8_rpr_sprs(env); register_power9_mmu_sprs(env); =20 @@ -6471,7 +6499,7 @@ static void init_proc_POWER10(CPUPPCState *env) register_power8_dpdes_sprs(env); register_vtb_sprs(env); register_power8_ic_sprs(env); - register_power8_book4_sprs(env); + register_power9_book4_sprs(env); register_power8_rpr_sprs(env); register_power9_mmu_sprs(env); register_power10_hash_sprs(env); --=20 2.40.1 From nobody Fri May 17 11:05:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::b2e; envelope-from=npiggin@gmail.com; helo=mail-yb1-xb2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1685835461748100003 Content-Type: text/plain; charset="utf-8" TFMR is the Time Facility Management Register which is specific to POWER CPUs, and used for the purpose of timebase management (generally by firmware, not the OS). This adds an initial simple TFMR register, which will form part of the core timebase facility model in the next patch. Signed-off-by: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater --- target/ppc/cpu_init.c | 2 +- target/ppc/helper.h | 2 ++ target/ppc/spr_common.h | 2 ++ target/ppc/timebase_helper.c | 13 +++++++++++++ target/ppc/translate.c | 10 ++++++++++ 5 files changed, 28 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index da0f7a7159..37088021d2 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5662,7 +5662,7 @@ static void register_power_common_book4_sprs(CPUPPCSt= ate *env) spr_register_hv(env, SPR_TFMR, "TFMR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_tfmr, &spr_write_tfmr, 0x00000000); spr_register_hv(env, SPR_LDBAR, "LDBAR", SPR_NOACCESS, SPR_NOACCESS, diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 16bb485c1a..166cacb3f9 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -746,6 +746,8 @@ DEF_HELPER_2(store_40x_dbcr0, void, env, tl) DEF_HELPER_2(store_40x_sler, void, env, tl) DEF_HELPER_FLAGS_2(store_booke_tcr, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_2(store_booke_tsr, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_1(load_tfmr, tl, env) +DEF_HELPER_2(store_tfmr, void, env, tl) DEF_HELPER_3(store_ibatl, void, env, i32, tl) DEF_HELPER_3(store_ibatu, void, env, i32, tl) DEF_HELPER_3(store_dbatl, void, env, i32, tl) diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h index d6c679cd99..8ab17123a4 100644 --- a/target/ppc/spr_common.h +++ b/target/ppc/spr_common.h @@ -196,6 +196,8 @@ void spr_write_ebb(DisasContext *ctx, int sprn, int gpr= n); void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn); void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn); void spr_write_hmer(DisasContext *ctx, int sprn, int gprn); +void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn); +void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn); void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn); void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn); #endif diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c index de1ee85e0b..34b1d5ad05 100644 --- a/target/ppc/timebase_helper.c +++ b/target/ppc/timebase_helper.c @@ -270,6 +270,19 @@ void helper_store_booke_tsr(CPUPPCState *env, target_u= long val) store_booke_tsr(env, val); } =20 +#if defined(TARGET_PPC64) +/* POWER processor Timebase Facility */ +target_ulong helper_load_tfmr(CPUPPCState *env) +{ + return env->spr[SPR_TFMR]; +} + +void helper_store_tfmr(CPUPPCState *env, target_ulong val) +{ + env->spr[SPR_TFMR] =3D val; +} +#endif + /*************************************************************************= ****/ /* Embedded PowerPC specific helpers */ =20 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 8b312b46e0..9dcd66eac8 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1255,6 +1255,16 @@ void spr_write_hmer(DisasContext *ctx, int sprn, int= gprn) spr_store_dump_spr(sprn); } =20 +void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) +{ + gen_helper_load_tfmr(cpu_gpr[gprn], cpu_env); +} + +void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_tfmr(cpu_env, cpu_gpr[gprn]); +} + void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) { gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); --=20 2.40.1 From nobody Fri May 17 11:05:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1685835448; cv=none; d=zohomail.com; s=zohoarc; b=AfmTo3l4YUZwnbb2DRN/hxYsi90w9bHP1Cq3A7jLJ4159wd5bzpxvuXska6IIFU1o23kijTHOuwM2TWw+p4NWQOHbGPZea7A21uYo3uMIEW02BRCdp8Gk/xqzM30VP9WNdnBC3mCKfri8miByqoNat8Lo3btr0elpo57dcZ74GI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Sat, 03 Jun 2023 16:36:38 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH 4/4] target/ppc: Implement core timebase state machine and TFMR Date: Sun, 4 Jun 2023 09:36:12 +1000 Message-Id: <20230603233612.125879-5-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230603233612.125879-1-npiggin@gmail.com> References: <20230603233612.125879-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1685835450196100002 Content-Type: text/plain; charset="utf-8" This implements the core timebase state machine, which is the core side of the time-of-day system in POWER processors. This facility is operated by control fields in the TFMR register, which also contains status fields. The core timebase interacts with the chiptod hardware, primarily to receive TOD updates, to synchronise timebase with other cores. This model does not actually update TB values with TOD or updates received from the chiptod, as timebases are always synchronised. It does step through the states required to perform the update. There are several asynchronous state transitions. These are modelled using using mfTFMR to drive state changes, because it is expected that firmware poll the register to wait for those states. This is good enough to test basic firmware behaviour without adding real timers. The values chosen are arbitrary. Signed-off-by: Nicholas Piggin Acked-by: C=C3=A9dric Le Goater --- target/ppc/cpu.h | 34 ++++++++ target/ppc/timebase_helper.c | 147 ++++++++++++++++++++++++++++++++++- 2 files changed, 179 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index d73cce8474..b1520ea4db 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1177,6 +1177,13 @@ struct CPUArchState { /* PowerNV chiptod / timebase facility state. */ int tb_ready_for_tod; /* core TB ready to receive TOD from chiptod */ int tod_sent_to_tb; /* chiptod sent TOD to the core TB */ + + /* + * Timers for async events are simulated by mfTFAC because TFAC is to = be + * polled for event. + */ + int tb_state_timer; + int tb_sync_pulse_timer; #endif #endif =20 @@ -2527,6 +2534,33 @@ enum { HMER_XSCOM_STATUS_MASK =3D PPC_BITMASK(21, 23), }; =20 +/* TFMR */ +enum { + TFMR_CONTROL_MASK =3D PPC_BITMASK(0, 24), + TFMR_MASK_HMI =3D PPC_BIT(10), + TFMR_TB_ECLIPZ =3D PPC_BIT(14), + TFMR_LOAD_TOD_MOD =3D PPC_BIT(16), + TFMR_MOVE_CHIP_TOD_TO_TB =3D PPC_BIT(18), + TFMR_CLEAR_TB_ERRORS =3D PPC_BIT(24), + TFMR_STATUS_MASK =3D PPC_BITMASK(25, 63), + TFMR_TBST_ENCODED =3D PPC_BITMASK(28, 31), /* TBST =3D TB St= ate */ + TFMR_TBST_LAST =3D PPC_BITMASK(32, 35), /* Previous TBST = */ + TFMR_TB_ENABLED =3D PPC_BIT(40), + TFMR_TB_VALID =3D PPC_BIT(41), + TFMR_TB_SYNC_OCCURED =3D PPC_BIT(42), +}; + +/* TFMR TBST */ +enum { + TBST_RESET =3D 0x0, + TBST_SEND_TOD_MOD =3D 0x1, + TBST_NOT_SET =3D 0x2, + TBST_SYNC_WAIT =3D 0x6, + TBST_GET_TOD =3D 0x7, + TBST_TB_RUNNING =3D 0x8, + TBST_TB_ERROR =3D 0x9, +}; + /*************************************************************************= ****/ =20 #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300)) diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c index 34b1d5ad05..11a06fafe6 100644 --- a/target/ppc/timebase_helper.c +++ b/target/ppc/timebase_helper.c @@ -272,14 +272,157 @@ void helper_store_booke_tsr(CPUPPCState *env, target= _ulong val) =20 #if defined(TARGET_PPC64) /* POWER processor Timebase Facility */ +static unsigned int tfmr_get_tb_state(uint64_t tfmr) +{ + return (tfmr & TFMR_TBST_ENCODED) >> (63 - 31); +} + +static uint64_t tfmr_new_tb_state(uint64_t tfmr, unsigned int tbst) +{ + tfmr &=3D ~TFMR_TBST_LAST; + tfmr |=3D (tfmr & TFMR_TBST_ENCODED) >> 4; /* move state to last state= */ + tfmr &=3D ~TFMR_TBST_ENCODED; + tfmr |=3D (uint64_t)tbst << (63 - 31); /* move new state to state */ + + if (tbst =3D=3D TBST_TB_RUNNING) { + tfmr |=3D TFMR_TB_VALID; + } else { + tfmr &=3D ~TFMR_TB_VALID; + } + + return tfmr; +} + +static void tb_state_machine_step(CPUPPCState *env) +{ + uint64_t tfmr =3D env->spr[SPR_TFMR]; + unsigned int tbst =3D tfmr_get_tb_state(tfmr); + + if (!(tfmr & TFMR_TB_ECLIPZ) || tbst =3D=3D TBST_TB_ERROR) { + return; + } + + if (env->tb_sync_pulse_timer) { + env->tb_sync_pulse_timer--; + } else { + tfmr |=3D TFMR_TB_SYNC_OCCURED; + env->spr[SPR_TFMR] =3D tfmr; + } + + if (env->tb_state_timer) { + env->tb_state_timer--; + return; + } + + if (tfmr & TFMR_LOAD_TOD_MOD) { + tfmr &=3D ~TFMR_LOAD_TOD_MOD; + if (tbst =3D=3D TBST_GET_TOD) { + tfmr =3D tfmr_new_tb_state(tfmr, TBST_TB_ERROR); + } else { + tfmr =3D tfmr_new_tb_state(tfmr, TBST_SEND_TOD_MOD); + /* State seems to transition immediately */ + tfmr =3D tfmr_new_tb_state(tfmr, TBST_NOT_SET); + } + } else if (tfmr & TFMR_MOVE_CHIP_TOD_TO_TB) { + if (tbst =3D=3D TBST_SYNC_WAIT) { + tfmr =3D tfmr_new_tb_state(tfmr, TBST_GET_TOD); + env->tb_state_timer =3D 3; + } else if (tbst =3D=3D TBST_GET_TOD) { + if (env->tod_sent_to_tb) { + tfmr =3D tfmr_new_tb_state(tfmr, TBST_TB_RUNNING); + tfmr &=3D ~TFMR_MOVE_CHIP_TOD_TO_TB; + env->tb_ready_for_tod =3D 0; + env->tod_sent_to_tb =3D 0; + } + } else { + qemu_log_mask(LOG_GUEST_ERROR, "TFMR error: MOVE_CHIP_TOD_TO_T= B " + "state machine in invalid state 0x%x\n", tbst); + tfmr =3D tfmr_new_tb_state(tfmr, TBST_TB_ERROR); + env->tb_ready_for_tod =3D 0; + } + } + + env->spr[SPR_TFMR] =3D tfmr; +} + target_ulong helper_load_tfmr(CPUPPCState *env) { - return env->spr[SPR_TFMR]; + tb_state_machine_step(env); + + return env->spr[SPR_TFMR] | TFMR_TB_ECLIPZ; } =20 void helper_store_tfmr(CPUPPCState *env, target_ulong val) { - env->spr[SPR_TFMR] =3D val; + uint64_t tfmr =3D env->spr[SPR_TFMR]; + unsigned int tbst =3D tfmr_get_tb_state(tfmr); + + if (!(val & TFMR_TB_ECLIPZ)) { + qemu_log_mask(LOG_UNIMP, "TFMR non-ECLIPZ mode not implemented\n"); + tfmr &=3D ~TFMR_TBST_ENCODED; + tfmr &=3D ~TFMR_TBST_LAST; + goto out; + } + + /* Update control bits */ + tfmr =3D (tfmr & ~TFMR_CONTROL_MASK) | (val & TFMR_CONTROL_MASK); + + /* mtspr always clears this */ + tfmr &=3D ~TFMR_TB_SYNC_OCCURED; + env->tb_sync_pulse_timer =3D 1; + + /* + * We don't implement any of the error status bits that can be + * cleared by writing 1 to them. TB error injection / simulation + * would have to implement some. + * + * Also don't implement mfTB failing when the TB state machine is + * not running. + */ + + if (((tfmr | val) & (TFMR_LOAD_TOD_MOD | TFMR_MOVE_CHIP_TOD_TO_TB)) = =3D=3D + (TFMR_LOAD_TOD_MOD | TFMR_MOVE_CHIP_TOD_TO_TB)) { + qemu_log_mask(LOG_GUEST_ERROR, "TFMR error: LOAD_TOD_MOD and " + "MOVE_CHIP_TOD_TO_TB both set\n"); + tfmr =3D tfmr_new_tb_state(tfmr, TBST_TB_ERROR); + env->tb_ready_for_tod =3D 0; + goto out; + } + + if (tfmr & TFMR_CLEAR_TB_ERRORS) { + tfmr =3D tfmr_new_tb_state(tfmr, TBST_RESET); + tfmr &=3D ~TFMR_CLEAR_TB_ERRORS; + tfmr &=3D ~TFMR_LOAD_TOD_MOD; + tfmr &=3D ~TFMR_MOVE_CHIP_TOD_TO_TB; + env->tb_ready_for_tod =3D 0; + env->tod_sent_to_tb =3D 0; + goto out; + } + + if (tbst =3D=3D TBST_TB_ERROR) { + qemu_log_mask(LOG_GUEST_ERROR, "TFMR error: mtspr TFMR in TB_ERROR" + " state\n"); + return; + } + + if (tfmr & TFMR_LOAD_TOD_MOD) { + env->tb_state_timer =3D 3; + } else if (tfmr & TFMR_MOVE_CHIP_TOD_TO_TB) { + if (tbst =3D=3D TBST_NOT_SET) { + tfmr =3D tfmr_new_tb_state(tfmr, TBST_SYNC_WAIT); + env->tb_ready_for_tod =3D 1; + env->tb_state_timer =3D 3; + } else { + qemu_log_mask(LOG_GUEST_ERROR, "TFMR error: MOVE_CHIP_TOD_TO_T= B " + "not in TB not set state 0x%x\n= ", + tbst); + tfmr =3D tfmr_new_tb_state(tfmr, TBST_TB_ERROR); + env->tb_ready_for_tod =3D 0; + } + } + +out: + env->spr[SPR_TFMR] =3D tfmr; } #endif =20 --=20 2.40.1