[v1] Various xive fixes

[PATCH 0/4] Various xive fixes

Frederic Barrat posted 4 patches 11 months, 2 weeks ago

Diff against v2
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git fetch https://github.com/patchew-project/qemu tags/patchew/20230530161129.313258-1-fbarrat@linux.ibm.com

Maintainers: "Cédric Le Goater" <clg@kaod.org>

There is a newer version of this series

hw/intc/pnv_xive2.c      | 20 +++++++++++++++++++-
hw/intc/pnv_xive2_regs.h |  8 ++++++++
hw/intc/xive.c           | 18 ++++++++++++++++++
3 files changed, 45 insertions(+), 1 deletion(-)

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[PATCH 0/4] Various xive fixes

Posted by Frederic Barrat 11 months, 2 weeks ago

A set of small fixes for the interrupt controller (xive2) on P10.

Frederic Barrat (4):
  pnv/xive2: Add definition for TCTXT Config register
  pnv/xive2: Add definition for the ESB cache configuration register
  pnv/xive2: Allow writes to the Physical Thread Enable registers
  pnv/xive2: Handle TIMA access through all ports

 hw/intc/pnv_xive2.c      | 20 +++++++++++++++++++-
 hw/intc/pnv_xive2_regs.h |  8 ++++++++
 hw/intc/xive.c           | 18 ++++++++++++++++++
 3 files changed, 45 insertions(+), 1 deletion(-)

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2.40.1