[v1] target/riscv: Fix mstatus related problems

[PATCH 0/4] target/riscv: Fix mstatus related problems

Weiwei Li posted 4 patches 11 months, 2 weeks ago

Diff against v2
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target/riscv/cpu_helper.c |  5 +++--
target/riscv/csr.c        | 14 ++++----------
target/riscv/op_helper.c  |  3 ++-
3 files changed, 9 insertions(+), 13 deletions(-)

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[PATCH 0/4] target/riscv: Fix mstatus related problems

Posted by Weiwei Li 11 months, 2 weeks ago

This patchset tries to fix some problems in the fields of mstatus, such as make MPV only work when MPP != PRM.

The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-mpv-upstream

Weiwei Li (4):
  target/riscv: Make MPV only work when MPP != PRV_M
  target/riscv: Remove check on mode for MPRV
  target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled
  target/riscv: Remove redundant assignment to SXL

 target/riscv/cpu_helper.c |  5 +++--
 target/riscv/csr.c        | 14 ++++----------
 target/riscv/op_helper.c  |  3 ++-
 3 files changed, 9 insertions(+), 13 deletions(-)

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2.25.1