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([2602:ae:1598:4c01:6b03:9af2:33c1:3d6b]) by smtp.gmail.com with ESMTPSA id n22-20020a62e516000000b00646fab782c0sm6547092pff.210.2023.05.23.22.46.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 22:46:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684907209; x=1687499209; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=xqNgAlNSZoTMywGnlWbqoYWYpph+41DXiIIaWWRLiIk=; b=udf2rF+xlapVOEre9AdcWRMNQiSvUrEnVyt1jmh0pNRnFskV3AUhRiOJuSlUmmy4x7 Dx+0BXDXGtuGZWqr7TRSc7Y+TmrcTIupCfU9xfo7H1RPRmACoKaegG8H+rXtjPEakau2 Z2mlqC+0MBIR47igSUsF0Puppm3ZOibTvDMsGjQ0g41BENbgIR1s45u1QSstRqoWZafl RQyoRdwwcrmceTzOcDoKoF5eb0zjrcNyXnBudmIBJHQ7mFag+bNENo+1DtbSDhCvFmFO fzJBcSoRULTKnYKTHoXEAidZd+yhhLxIkaLXsfvvpstubyfzbCkNduxBimGKvna6s+LZ AqSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684907209; x=1687499209; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=xqNgAlNSZoTMywGnlWbqoYWYpph+41DXiIIaWWRLiIk=; b=iET0+CDPPp+sr9N5PQ1EYcC3RMXGZMg04mDKsJtHALmoTqSjBgFpA2l0GpkrxMNFB5 VeB1GF2ORzYfRg+ZPVl6POt0Cg30+UXxYw8yzVvmB6oQxOV0jOOvU8Rii0/WRJhD05Td +VxCyOESdqC10d350wEf97FM91iePWKb4QEPK6NkBCItR76ohjSw4MvUOExkYGaGQ/4x /UMPpiCSLvU455ldnZlqVtb38lKW9SDGkN/QeY2Rla0cB1+3C0YfTSubsGmcmh4d4h15 05HGkg7351VVbPvto+P9XWlbXtZoS2zlckU1IN1mc6kvJJeqlA7LbFJWaDUHhp7GkKGQ HZSw== X-Gm-Message-State: AC+VfDwKMqPNXoMHIR+Z+J3Se9UQQ9Z9HGeknqi7J2mkJ0bKklO1IAlw IxCqE+voVHAvz+UbMKauTqzVCxWLFX8Za9Utw1E= X-Google-Smtp-Source: ACHHUZ60PcpncYmfNKEu1fBEue56kshGk8JPNGnyYtQY2ZQiAmqyU3lxlkbfYJBRcMIcSzJjTq7M0w== X-Received: by 2002:a05:6a00:181e:b0:64d:2c58:f86f with SMTP id y30-20020a056a00181e00b0064d2c58f86fmr2104450pfa.0.1684907209157; Tue, 23 May 2023 22:46:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: fanwj@mail.ustc.edu.cn, laurent@vivier.eu Subject: [PATCH] linux-user/i386: Properly align signal frame Date: Tue, 23 May 2023 22:46:47 -0700 Message-Id: <20230524054647.1093758-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684907236633100001 Content-Type: text/plain; charset="utf-8" The beginning of the structure, with pretaddr, should be just below 16-byte alignment. Disconnect fpstate from sigframe, just like the kernel does. Signed-off-by: Richard Henderson --- linux-user/i386/signal.c | 104 +++++++++++++++++-------------- tests/tcg/x86_64/sigstack.c | 33 ++++++++++ tests/tcg/x86_64/Makefile.target | 1 + 3 files changed, 90 insertions(+), 48 deletions(-) create mode 100644 tests/tcg/x86_64/sigstack.c diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c index 60fa07d6f9..c49467de78 100644 --- a/linux-user/i386/signal.c +++ b/linux-user/i386/signal.c @@ -191,16 +191,7 @@ struct sigframe { struct target_fpstate fpstate_unused; abi_ulong extramask[TARGET_NSIG_WORDS-1]; char retcode[8]; - - /* - * This field will be 16-byte aligned in memory. Applying QEMU_ALIGNED - * to it ensures that the base of the frame has an appropriate alignme= nt - * too. - */ - struct target_fpstate fpstate QEMU_ALIGNED(8); }; -#define TARGET_SIGFRAME_FXSAVE_OFFSET ( = \ - offsetof(struct sigframe, fpstate) + TARGET_FPSTATE_FXSAVE_OFFSET) =20 struct rt_sigframe { abi_ulong pretcode; @@ -210,27 +201,21 @@ struct rt_sigframe { struct target_siginfo info; struct target_ucontext uc; char retcode[8]; - struct target_fpstate fpstate QEMU_ALIGNED(8); }; -#define TARGET_RT_SIGFRAME_FXSAVE_OFFSET ( = \ - offsetof(struct rt_sigframe, fpstate) + TARGET_FPSTATE_FXSAVE_OFFSET) #else - struct rt_sigframe { abi_ulong pretcode; struct target_ucontext uc; struct target_siginfo info; - struct target_fpstate fpstate QEMU_ALIGNED(16); }; -#define TARGET_RT_SIGFRAME_FXSAVE_OFFSET ( = \ - offsetof(struct rt_sigframe, fpstate) + TARGET_FPSTATE_FXSAVE_OFFSET) #endif =20 /* * Set up a signal frame. */ =20 -static void xsave_sigcontext(CPUX86State *env, struct target_fpstate_fxsav= e *fxsave, +static void xsave_sigcontext(CPUX86State *env, + struct target_fpstate_fxsave *fxsave, abi_ulong fxsave_addr) { if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { @@ -266,8 +251,9 @@ static void xsave_sigcontext(CPUX86State *env, struct t= arget_fpstate_fxsave *fxs } =20 static void setup_sigcontext(struct target_sigcontext *sc, - struct target_fpstate *fpstate, CPUX86State *env, abi_ulong mask, - abi_ulong fpstate_addr) + struct target_fpstate *fpstate, + CPUX86State *env, abi_ulong mask, + abi_ulong fpstate_addr) { CPUState *cs =3D env_cpu(env); #ifndef TARGET_X86_64 @@ -347,10 +333,11 @@ static void setup_sigcontext(struct target_sigcontext= *sc, * Determine which stack to use.. */ =20 -static inline abi_ulong -get_sigframe(struct target_sigaction *ka, CPUX86State *env, size_t fxsave_= offset) +static abi_ulong get_sigframe(struct target_sigaction *ka, CPUX86State *en= v, + size_t *frame_size, abi_ulong *fpsave_addr) { - unsigned long esp; + abi_ulong esp, orig; + size_t fpsave_size; =20 /* Default to using normal stack */ esp =3D get_sp_from_cpustate(env); @@ -371,16 +358,23 @@ get_sigframe(struct target_sigaction *ka, CPUX86State= *env, size_t fxsave_offset } #endif } + orig =3D esp; =20 - if (!(env->features[FEAT_1_EDX] & CPUID_FXSR)) { - return (esp - (fxsave_offset + TARGET_FXSAVE_SIZE)) & -8ul; - } else if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { - return ((esp - TARGET_FXSAVE_SIZE) & -16ul) - fxsave_offset; + if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { + fpsave_size =3D TARGET_FXSAVE_SIZE; + esp =3D ROUND_DOWN(esp - fpsave_size, 16); } else { - size_t xstate_size =3D - xsave_area_size(env->xcr0, false) + TARGET_FP_XSTATE_MAGIC2= _SIZE; - return ((esp - xstate_size) & -64ul) - fxsave_offset; + fpsave_size =3D xsave_area_size(env->xcr0, false) + + TARGET_FP_XSTATE_MAGIC2_SIZE; + esp =3D ROUND_DOWN(esp - fpsave_size, 64); } + *fpsave_addr =3D esp; + + esp =3D esp - *frame_size + sizeof(abi_ulong); + esp =3D ROUND_DOWN(esp, 16) - sizeof(abi_ulong); + + *frame_size =3D orig - esp; + return esp; } =20 #ifndef TARGET_X86_64 @@ -405,26 +399,34 @@ void setup_frame(int sig, struct target_sigaction *ka, target_sigset_t *set, CPUX86State *env) { abi_ulong frame_addr; + abi_ulong fpstate_addr; + size_t frame_size; struct sigframe *frame; + struct target_fpstate *fpstate; int i; =20 - frame_addr =3D get_sigframe(ka, env, TARGET_SIGFRAME_FXSAVE_OFFSET); + frame_size =3D sizeof(struct sigframe); + frame_addr =3D get_sigframe(ka, env, &frame_size, &fpstate_addr); trace_user_setup_frame(env, frame_addr); =20 - if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) + frame =3D lock_user(VERIFY_WRITE, frame_addr, frame_size, false); + if (!frame) { goto give_sigsegv; + } + fpstate =3D (void *)frame + (fpstate_addr - frame_addr); =20 __put_user(sig, &frame->sig); =20 - setup_sigcontext(&frame->sc, &frame->fpstate, env, set->sig[0], - frame_addr + offsetof(struct sigframe, fpstate)); + setup_sigcontext(&frame->sc, fpstate, env, set->sig[0], fpstate_addr); =20 - for(i =3D 1; i < TARGET_NSIG_WORDS; i++) { + for (i =3D 1; i < TARGET_NSIG_WORDS; i++) { __put_user(set->sig[i], &frame->extramask[i - 1]); } =20 - /* Set up to return from userspace. If provided, use a stub - already in userspace. */ + /* + * Set up to return from userspace. + * If provided, use a stub already in userspace. + */ if (ka->sa_flags & TARGET_SA_RESTORER) { __put_user(ka->sa_restorer, &frame->pretcode); } else { @@ -443,11 +445,10 @@ void setup_frame(int sig, struct target_sigaction *ka, cpu_x86_load_seg(env, R_CS, __USER_CS); env->eflags &=3D ~TF_MASK; =20 - unlock_user_struct(frame, frame_addr, 1); - + unlock_user(frame, frame_addr, frame_size); return; =20 -give_sigsegv: + give_sigsegv: force_sigsegv(sig); } #endif @@ -458,17 +459,24 @@ void setup_rt_frame(int sig, struct target_sigaction = *ka, target_sigset_t *set, CPUX86State *env) { abi_ulong frame_addr; + abi_ulong fpstate_addr; + size_t frame_size; #ifndef TARGET_X86_64 abi_ulong addr; #endif struct rt_sigframe *frame; + struct target_fpstate *fpstate; int i; =20 - frame_addr =3D get_sigframe(ka, env, TARGET_RT_SIGFRAME_FXSAVE_OFFSET); + frame_size =3D sizeof(struct rt_sigframe); + frame_addr =3D get_sigframe(ka, env, &frame_size, &fpstate_addr); trace_user_setup_rt_frame(env, frame_addr); =20 - if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) + frame =3D lock_user(VERIFY_WRITE, frame_addr, frame_size, false); + if (!frame) { goto give_sigsegv; + } + fpstate =3D (void *)frame + (fpstate_addr - frame_addr); =20 /* These fields are only in rt_sigframe on 32 bit */ #ifndef TARGET_X86_64 @@ -490,10 +498,10 @@ void setup_rt_frame(int sig, struct target_sigaction = *ka, } __put_user(0, &frame->uc.tuc_link); target_save_altstack(&frame->uc.tuc_stack, env); - setup_sigcontext(&frame->uc.tuc_mcontext, &frame->fpstate, env, - set->sig[0], frame_addr + offsetof(struct rt_sigframe, fpstate= )); + setup_sigcontext(&frame->uc.tuc_mcontext, fpstate, env, + set->sig[0], fpstate_addr); =20 - for(i =3D 0; i < TARGET_NSIG_WORDS; i++) { + for (i =3D 0; i < TARGET_NSIG_WORDS; i++) { __put_user(set->sig[i], &frame->uc.tuc_sigmask.sig[i]); } =20 @@ -533,15 +541,15 @@ void setup_rt_frame(int sig, struct target_sigaction = *ka, cpu_x86_load_seg(env, R_SS, __USER_DS); env->eflags &=3D ~TF_MASK; =20 - unlock_user_struct(frame, frame_addr, 1); - + unlock_user(frame, frame_addr, frame_size); return; =20 -give_sigsegv: + give_sigsegv: force_sigsegv(sig); } =20 -static int xrstor_sigcontext(CPUX86State *env, struct target_fpstate_fxsav= e *fxsave, +static int xrstor_sigcontext(CPUX86State *env, + struct target_fpstate_fxsave *fxsave, abi_ulong fxsave_addr) { if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { diff --git a/tests/tcg/x86_64/sigstack.c b/tests/tcg/x86_64/sigstack.c new file mode 100644 index 0000000000..06cb847569 --- /dev/null +++ b/tests/tcg/x86_64/sigstack.c @@ -0,0 +1,33 @@ +#include +#include +#include +#include + +void __attribute__((noinline)) bar(void) +{ + exit(EXIT_SUCCESS); +} + +void __attribute__((noinline, ms_abi)) foo(void) +{ + /* + * With ms_abi, there are call-saved xmm registers, which are forced + * to the stack around the call to sysv_abi bar(). If the signal + * stack frame is not properly aligned, movaps will raise #GP. + */ + bar(); +} + +void sighandler(int num) +{ + void* sp =3D __builtin_dwarf_cfa(); + assert((uintptr_t)sp % 16 =3D=3D 0); + foo(); +} + +int main(void) +{ + signal(SIGUSR1, sighandler); + raise(SIGUSR1); + abort(); +} diff --git a/tests/tcg/x86_64/Makefile.target b/tests/tcg/x86_64/Makefile.t= arget index e64aab1b81..d961599f64 100644 --- a/tests/tcg/x86_64/Makefile.target +++ b/tests/tcg/x86_64/Makefile.target @@ -13,6 +13,7 @@ X86_64_TESTS +=3D vsyscall X86_64_TESTS +=3D noexec X86_64_TESTS +=3D cmpxchg X86_64_TESTS +=3D adox +X86_64_TESTS +=3D sigstack TESTS=3D$(MULTIARCH_TESTS) $(X86_64_TESTS) test-x86_64 else TESTS=3D$(MULTIARCH_TESTS) --=20 2.34.1