From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684886611; cv=none; d=zohomail.com; s=zohoarc; b=C1ZSrQOBU/TfT2s01gQl+cQH3sjVB74yKt4OE1ETKez7Vg6Bu/xHhi4yumkjg7Ria4JaguGWlObyHNz+FmCMZ0PXGTQ0Gpz+SBNVBPAQHiRdMcR+qJJbrc6aqQHg+wRDdiRyBWS04gVsjKLiPhvSin/Qp/EyH616Rb7Ty0fd2Wk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684886611; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aakLzzWxnODN03CeAWkwF35STfpMNitCSr/+QT2v02E=; b=UrzM02Bg/JfAMT/zEj4goo0F+HyIHKJVvj5xtr9Z0tWzJOXVN1HAtwOlHJapbod13G+SOAprhH08NyJ0WS3oeU0NTuv+C/9315g8HzncBAtUwyys9vgrHqRuYj75Y9WJuvefhIP+CIj+3d9c3/3Gwj/c2Y6SfIyAe8Gc004gh3I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684886611770805.8600809385773; Tue, 23 May 2023 17:03:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1btL-00048V-0a; Tue, 23 May 2023 19:58:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1btJ-000486-WB for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:10 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1btI-0001lW-Cx for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:09 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-64d41d8bc63so123776b3a.0 for ; Tue, 23 May 2023 16:58:08 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886287; x=1687478287; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aakLzzWxnODN03CeAWkwF35STfpMNitCSr/+QT2v02E=; b=daGukKKAqTHYk8i4H0mEXfHFnA8qwm91DqbBbnvIvFNf/AGCKQkZ34TjB/gt3C6gzV Fk1VgYCebp9mu8WfkdPMm9Tw2GOeyyayyuyJQf6E8afF/XYIjYSNhlRfO8yGzZYirWDP 9RXH9zVECj5d5SD8fuz7FDowG4QP8rUDprtBDPt/GmWfWrHhyL1jjcYyTwhnP8i51L+W 52D4O1q+QOqci1/iunADc2EmEUGjomFC33zQhEiWpHYa09SeqoslDDcu70/Rvf/SB5jj pJGYGl3rMW/fj7r3NVX21kOEPbySkSt8WHWiqwIXaS/4/l7X5jgsxAakrwR25z8RYMyW nLGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886287; x=1687478287; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aakLzzWxnODN03CeAWkwF35STfpMNitCSr/+QT2v02E=; b=VdQrLLyUmrJYETPXfsYwnURXpjuTrQEmop5fyxYDxfv14hhB3b9eao3XxN3pWRSDOy ybNyYrEdfdnJ32ZgLsZofuH83pCFon1/DcCxHujCCbljXIVdMjG9PbEvxJc1ReBM6U20 /GllVDfEVINoSWGe2+vHTmW0J3w34Xj/Fjwl72fBk5z04PnTT6roX1AEWlHe2UP6yXGq CmTj5G1AcpbIdEHasss4FrvaL4V0pBseF0enzb2LULt0JnEn7r+v6Kgvj1/pzjfG6yKw WFY4Y+7SO6E7McXMA18NxRecRk1470PXFzwKtEcU0mygt6vo8w8mlZa8+kHdX61qEEGW uEIw== X-Gm-Message-State: AC+VfDxfrsBRcEld8K9GnwPG0eMhxdYkwk5zXQ/HTmdwQ2jCHDXjKiUm KOI//yYDJXngTSNqIqPu9cQID8pvYjdhWKgZ/Qk= X-Google-Smtp-Source: ACHHUZ4gJsHOUEHRD0QO3Q5dXQ6sgILp9a0/6JC6cZ5qWjr0QyKswJVg9WRSQOvAbyzRgU4VKKEqBA== X-Received: by 2002:a05:6a00:2341:b0:643:b489:246d with SMTP id j1-20020a056a00234100b00643b489246dmr901213pfj.3.1684886287131; Tue, 23 May 2023 16:58:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Juan Quintela Subject: [PULL 01/28] util: Introduce host-specific cpuinfo.h Date: Tue, 23 May 2023 16:57:37 -0700 Message-Id: <20230523235804.747803-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886613537100003 The entire contents of the header is host-specific, but the existence of such a header is not, which could prevent some host specific ifdefs at the top of the file for the include. Add host/include/{arch,generic} to the project arguments. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Juan Quintela Signed-off-by: Richard Henderson --- host/include/generic/host/cpuinfo.h | 4 ++++ meson.build | 10 ++++++++++ 2 files changed, 14 insertions(+) create mode 100644 host/include/generic/host/cpuinfo.h diff --git a/host/include/generic/host/cpuinfo.h b/host/include/generic/hos= t/cpuinfo.h new file mode 100644 index 0000000000..eca672064a --- /dev/null +++ b/host/include/generic/host/cpuinfo.h @@ -0,0 +1,4 @@ +/* + * No host specific cpu indentification. + * SPDX-License-Identifier: GPL-2.0-or-later + */ diff --git a/meson.build b/meson.build index 0a5cdefd4d..c516b911d9 100644 --- a/meson.build +++ b/meson.build @@ -512,6 +512,16 @@ add_project_arguments('-iquote', '.', '-iquote', meson.current_source_dir() / 'include', language: all_languages) =20 +# If a host-specific include directory exists, list that first... +host_include =3D meson.current_source_dir() / 'host/include/' +if fs.is_dir(host_include / host_arch) + add_project_arguments('-iquote', host_include / host_arch, + language: all_languages) +endif +# ... followed by the generic fallback. +add_project_arguments('-iquote', host_include / 'generic', + language: all_languages) + sparse =3D find_program('cgcc', required: get_option('sparse')) if sparse.found() run_target('sparse', --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684886368; cv=none; d=zohomail.com; s=zohoarc; b=i8HfdUYYS6i8QNy9qaYdXYMQYXwI9SQ94rn8ZRocG252cW/h7e8Qybb3BDBtVCuJT3av73jTljtUj6tlHmtEiXiA/Cqbne6PedALWR16LyXxBfNMVr3t4QvrakFW89W9dxS1LVyhbzos8d2+JJXYlGujB1LsINFt3u8t9sJ0tDM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684886368; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RQ5heHg0RSRXp+2eZoaWh9Mm0ksGiV5zBT4WyA0hiYs=; b=EBIhmkNp/BcaXmFrPebvjRPwwjfKeWk9REvMhsHubbdLZuSN5bJ2RS/TlHQHGG2/fBFIvR1ANlpYgBMuCbz7NQ+oZ2mZya9aQI4MivxQrrMMBFu73WudZLx7zgq0VcUIdrkIP2wnCGSo9FfCnkvxsW2D1KUQn8sPb3ZwnfxHzyg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684886368321232.72687756063397; Tue, 23 May 2023 16:59:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1btO-00049q-19; Tue, 23 May 2023 19:58:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1btL-00048m-LJ for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:11 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1btJ-0001ln-Be for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:11 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-64d2981e3abso113736b3a.1 for ; Tue, 23 May 2023 16:58:08 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886288; x=1687478288; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RQ5heHg0RSRXp+2eZoaWh9Mm0ksGiV5zBT4WyA0hiYs=; b=u0HOZ97D2wxiQ4nG+8gb2cBk/pnRIuq4y2HgC17EGhOeGdEruzW14kJ+Q2vezobBW5 MB6BzroFBZqCchZ8PuXErTOSnAzYZ6qYI2fx6y52opKqj6EE+goi3rx3KDnaBqGx8+DV /5/KB+B0N0zkPnzn5Kr83+i5dI/e4kt/5fl05TAGCYdYt5b7D17pSjzDjUU98eX8SDrF k1qbOy1HleDrfnGTUU4rKN78NwUx1u/7ta/qyv8PRwT5m2x6MjnitF8DZDgPwB+VkiL3 n4+tYl1H3VFL70UCcDBUPIKHp4DHzJe8aiqX19pFwpqVW6cxsHz+UYM5UOwIZmT1RIVy yswg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886288; x=1687478288; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RQ5heHg0RSRXp+2eZoaWh9Mm0ksGiV5zBT4WyA0hiYs=; b=aCSdq7wdr1WMr0CyySP96PDXGCVbYFxwrJwoPXuEw+/s0nn9JcG8PpvCuTl53EVseT GwCEg3dg6AMMoSxyXb0ckRnO9cKZIev3ZimicMABcIzlKQD69ldaAudvBvEmr6AczTgG n/UTUkGAhmTXvNNC3nqrtqmuI1Wo3VxqAMFaErRHlyTGwW6uMaExwG4wxj3QadPt/tF7 XvuJEp5xqfWTtNmszKWpZz58QaZpEuuJpQl6xQ1gYTITZM3k4ghwDWmOZRvYFDwEzj44 rxNGDzGF++ocrRdXnJkVK45geldXxXfS9WwQQ9cw5L1sFMwXkGV5jphMSk2lhPnpnUOV knxA== X-Gm-Message-State: AC+VfDwjMY9IATBUVqyiOp/Fk8amKIS5c1RutTL00u4xuQE5UNIARPr7 61y1Hmt9UiLeeSM2D+Ij/0ArjW93SdwW8Sa9miI= X-Google-Smtp-Source: ACHHUZ4s4dpG8TBcJZ7wPgIKgaLbb0k+Ug6lZFAqIQkKGFWD77fWJv7aA5zIh/LtwCrgRe2iJ7o6Fw== X-Received: by 2002:a05:6a00:a11:b0:64a:4bfa:6b8d with SMTP id p17-20020a056a000a1100b0064a4bfa6b8dmr858896pfh.6.1684886287902; Tue, 23 May 2023 16:58:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Juan Quintela Subject: [PULL 02/28] util: Add cpuinfo-i386.c Date: Tue, 23 May 2023 16:57:38 -0700 Message-Id: <20230523235804.747803-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886370492100010 Add cpuinfo.h for i386 and x86_64, and the initialization for that in util/. Populate that with a slightly altered copy of the tcg host probing code. Other uses of cpuid.h will be adjusted one patch at a time. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Juan Quintela Signed-off-by: Richard Henderson --- host/include/i386/host/cpuinfo.h | 38 ++++++++++++ host/include/x86_64/host/cpuinfo.h | 1 + util/cpuinfo-i386.c | 97 ++++++++++++++++++++++++++++++ MAINTAINERS | 2 + util/meson.build | 4 ++ 5 files changed, 142 insertions(+) create mode 100644 host/include/i386/host/cpuinfo.h create mode 100644 host/include/x86_64/host/cpuinfo.h create mode 100644 util/cpuinfo-i386.c diff --git a/host/include/i386/host/cpuinfo.h b/host/include/i386/host/cpui= nfo.h new file mode 100644 index 0000000000..e6f7461378 --- /dev/null +++ b/host/include/i386/host/cpuinfo.h @@ -0,0 +1,38 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * Host specific cpu indentification for x86. + */ + +#ifndef HOST_CPUINFO_H +#define HOST_CPUINFO_H + +/* Digested version of */ + +#define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */ +#define CPUINFO_CMOV (1u << 1) +#define CPUINFO_MOVBE (1u << 2) +#define CPUINFO_LZCNT (1u << 3) +#define CPUINFO_POPCNT (1u << 4) +#define CPUINFO_BMI1 (1u << 5) +#define CPUINFO_BMI2 (1u << 6) +#define CPUINFO_SSE2 (1u << 7) +#define CPUINFO_SSE4 (1u << 8) +#define CPUINFO_AVX1 (1u << 9) +#define CPUINFO_AVX2 (1u << 10) +#define CPUINFO_AVX512F (1u << 11) +#define CPUINFO_AVX512VL (1u << 12) +#define CPUINFO_AVX512BW (1u << 13) +#define CPUINFO_AVX512DQ (1u << 14) +#define CPUINFO_AVX512VBMI2 (1u << 15) +#define CPUINFO_ATOMIC_VMOVDQA (1u << 16) + +/* Initialized with a constructor. */ +extern unsigned cpuinfo; + +/* + * We cannot rely on constructor ordering, so other constructors must + * use the function interface rather than the variable above. + */ +unsigned cpuinfo_init(void); + +#endif /* HOST_CPUINFO_H */ diff --git a/host/include/x86_64/host/cpuinfo.h b/host/include/x86_64/host/= cpuinfo.h new file mode 100644 index 0000000000..67debab9a0 --- /dev/null +++ b/host/include/x86_64/host/cpuinfo.h @@ -0,0 +1 @@ +#include "host/include/i386/host/cpuinfo.h" diff --git a/util/cpuinfo-i386.c b/util/cpuinfo-i386.c new file mode 100644 index 0000000000..434319aa71 --- /dev/null +++ b/util/cpuinfo-i386.c @@ -0,0 +1,97 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * Host specific cpu indentification for x86. + */ + +#include "qemu/osdep.h" +#include "host/cpuinfo.h" +#ifdef CONFIG_CPUID_H +# include "qemu/cpuid.h" +#endif + +unsigned cpuinfo; + +/* Called both as constructor and (possibly) via other constructors. */ +unsigned __attribute__((constructor)) cpuinfo_init(void) +{ + unsigned info =3D cpuinfo; + + if (info) { + return info; + } + +#ifdef CONFIG_CPUID_H + unsigned max, a, b, c, d, b7 =3D 0, c7 =3D 0; + + max =3D __get_cpuid_max(0, 0); + + if (max >=3D 7) { + __cpuid_count(7, 0, a, b7, c7, d); + info |=3D (b7 & bit_BMI ? CPUINFO_BMI1 : 0); + info |=3D (b7 & bit_BMI2 ? CPUINFO_BMI2 : 0); + } + + if (max >=3D 1) { + __cpuid(1, a, b, c, d); + + info |=3D (d & bit_CMOV ? CPUINFO_CMOV : 0); + info |=3D (d & bit_SSE2 ? CPUINFO_SSE2 : 0); + info |=3D (c & bit_SSE4_1 ? CPUINFO_SSE4 : 0); + info |=3D (c & bit_MOVBE ? CPUINFO_MOVBE : 0); + info |=3D (c & bit_POPCNT ? CPUINFO_POPCNT : 0); + + /* For AVX features, we must check available and usable. */ + if ((c & bit_AVX) && (c & bit_OSXSAVE)) { + unsigned bv =3D xgetbv_low(0); + + if ((bv & 6) =3D=3D 6) { + info |=3D CPUINFO_AVX1; + info |=3D (b7 & bit_AVX2 ? CPUINFO_AVX2 : 0); + + if ((bv & 0xe0) =3D=3D 0xe0) { + info |=3D (b7 & bit_AVX512F ? CPUINFO_AVX512F : 0); + info |=3D (b7 & bit_AVX512VL ? CPUINFO_AVX512VL : 0); + info |=3D (b7 & bit_AVX512BW ? CPUINFO_AVX512BW : 0); + info |=3D (b7 & bit_AVX512DQ ? CPUINFO_AVX512DQ : 0); + info |=3D (c7 & bit_AVX512VBMI2 ? CPUINFO_AVX512VBMI2 = : 0); + } + + /* + * The Intel SDM has added: + * Processors that enumerate support for Intel=C2=AE AVX + * (by setting the feature flag CPUID.01H:ECX.AVX[bit 28= ]) + * guarantee that the 16-byte memory operations performed + * by the following instructions will always be carried + * out atomically: + * - MOVAPD, MOVAPS, and MOVDQA. + * - VMOVAPD, VMOVAPS, and VMOVDQA when encoded with VEX= .128. + * - VMOVAPD, VMOVAPS, VMOVDQA32, and VMOVDQA64 when enc= oded + * with EVEX.128 and k0 (masking disabled). + * Note that these instructions require the linear address= es + * of their memory operands to be 16-byte aligned. + * + * AMD has provided an even stronger guarantee that proces= sors + * with AVX provide 16-byte atomicity for all cachable, + * naturally aligned single loads and stores, e.g. MOVDQU. + * + * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D1046= 88 + */ + __cpuid(0, a, b, c, d); + if (c =3D=3D signature_INTEL_ecx || c =3D=3D signature_AMD= _ecx) { + info |=3D CPUINFO_ATOMIC_VMOVDQA; + } + } + } + } + + max =3D __get_cpuid_max(0x8000000, 0); + if (max >=3D 1) { + __cpuid(0x80000001, a, b, c, d); + info |=3D (c & bit_LZCNT ? CPUINFO_LZCNT : 0); + } +#endif + + info |=3D CPUINFO_ALWAYS; + cpuinfo =3D info; + return info; +} diff --git a/MAINTAINERS b/MAINTAINERS index 6addabdec4..1a32066231 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -157,6 +157,8 @@ F: include/exec/helper*.h F: include/sysemu/cpus.h F: include/sysemu/tcg.h F: include/hw/core/tcg-cpu-ops.h +F: host/include/*/host/cpuinfo.h +F: util/cpuinfo-*.c =20 FPU emulation M: Aurelien Jarno diff --git a/util/meson.build b/util/meson.build index e1f1c39e10..b3be9fad5d 100644 --- a/util/meson.build +++ b/util/meson.build @@ -108,3 +108,7 @@ if have_block endif util_ss.add(when: 'CONFIG_LINUX', if_true: files('vfio-helpers.c')) endif + +if cpu in ['x86', 'x86_64'] + util_ss.add(files('cpuinfo-i386.c')) +endif --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684886369; cv=none; d=zohomail.com; s=zohoarc; b=ZB8165tn59bp2uAazmPl/GmW96PkBBniPyRJx0b3/bc/tmSCGNm+gFoIEu23dNjZqHj65apoJhPj9EiNmjAOPrsdtManocJzrL5Xa46AoZjEyp482Cv4U1elLqJViapZaF7qNLzhMHuyte1r/f4izGEH08HcCBIvF+QjQCGsf2Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684886369; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iKNcUlS+jlCWq7+Fad+OkxpU1yvQUoyJQ2LbUV5SS1s=; b=cKz9/G/Bkr2SYWHLyC1SJ8Jegltcr06dUId1CSfYv249uxdx84OzW/nTg/2PL5ucxbod5HKHZCJfdhj9UstCaS+MRvbNaLxbPYTMtYXQ2nlBNDI+D1k0pxa87adMecJC0DjpvtdQH3Up6PR+93cXJ+8OT14H21iMj7ccUT8KeXY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684886369441210.72236753398; Tue, 23 May 2023 16:59:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1btP-0004A5-R5; Tue, 23 May 2023 19:58:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1btN-00049C-2D for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:13 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1btL-0001lx-6K for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:12 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-64d4e45971bso103255b3a.2 for ; Tue, 23 May 2023 16:58:09 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886289; x=1687478289; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iKNcUlS+jlCWq7+Fad+OkxpU1yvQUoyJQ2LbUV5SS1s=; b=cquaSiaOcprG0bGUsTM2Clzcl210IPOulVn5QWVWpeGSw0rBR939mu/P/pVyOkjx65 S9q2bGIEIR4q8qEVK4ecWGBGhgqssj0IoFJUfBIYx1n/h7C9zLnIEudj5Ap5HdWRUtUv FuP1t9+ku/oYkLYO6P/oxIP7vt5W07miLNOitI6Uxpk013LM8nTY8cuGW24KXUTUt2YK +WiK5MuirP1yXHsIHesZdXno9df27Ts8QMCITro/4oq0c7KE7KDsL+T4P8IdoTq0T3gw BrdVYgQYNl23xflDElfDbeeuvun6WtfcEyzf4JqsXCuZmM4Rj1HgsLVCzwqieFjeP+Ug SA7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886289; x=1687478289; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iKNcUlS+jlCWq7+Fad+OkxpU1yvQUoyJQ2LbUV5SS1s=; b=Rgo3zyR5VeImXyOFQ1ycD8CposYsg/tc6HXHg/0IHZLhYAWWWoIAsEo03FgN5U6eMN viTPpSzI/OwHw6baR9olPvyf5/n+UzQ9mSPx/zjBeER+L5SIirMEpnbX6YV0+KIu/ESp sRwiPHKs8y9ijdBIKgZ0H4c/QmYCfcr6RYRdDIEWpUAGhpmUliS1Ol7YV8mAymQ/bj5G WVWYhuIKKR5E+H6espGnSgFflyMlqLVw0NuDUBw9o9KW2D2X+cN5qUS8e+dN0k7b3Z8D TFgIpmeeI55XeahnFUqOMevezVwX3flqfmuHO2qX/tco2Dam16T0YBr6mCxnN2/OdJz/ HSMQ== X-Gm-Message-State: AC+VfDzqVXskb/nfhgHiLxNko/kXXCfyKR1C0UXOQ3wWWksflvl4PedQ pT0uIfpKEPygIowYtFHlGIIbxWM3GT1bEao+2jE= X-Google-Smtp-Source: ACHHUZ65xfktdE82Q6Ql+MSQzmNm13mbXt349D0LMoi7x7zX8pESm7aS++a7LZl1Qojw4zgMoywAtg== X-Received: by 2002:a05:6a20:9144:b0:10c:9773:5e6 with SMTP id x4-20020a056a20914400b0010c977305e6mr3346690pzc.47.1684886288781; Tue, 23 May 2023 16:58:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell Subject: [PULL 03/28] util: Add i386 CPUINFO_ATOMIC_VMOVDQU Date: Tue, 23 May 2023 16:57:39 -0700 Message-Id: <20230523235804.747803-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886370474100008 Add a bit to indicate when VMOVDQU is also atomic if aligned. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- host/include/i386/host/cpuinfo.h | 1 + util/cpuinfo-i386.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/host/include/i386/host/cpuinfo.h b/host/include/i386/host/cpui= nfo.h index e6f7461378..a6537123cf 100644 --- a/host/include/i386/host/cpuinfo.h +++ b/host/include/i386/host/cpuinfo.h @@ -25,6 +25,7 @@ #define CPUINFO_AVX512DQ (1u << 14) #define CPUINFO_AVX512VBMI2 (1u << 15) #define CPUINFO_ATOMIC_VMOVDQA (1u << 16) +#define CPUINFO_ATOMIC_VMOVDQU (1u << 17) =20 /* Initialized with a constructor. */ extern unsigned cpuinfo; diff --git a/util/cpuinfo-i386.c b/util/cpuinfo-i386.c index 434319aa71..ab6143d9e7 100644 --- a/util/cpuinfo-i386.c +++ b/util/cpuinfo-i386.c @@ -77,8 +77,10 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D1046= 88 */ __cpuid(0, a, b, c, d); - if (c =3D=3D signature_INTEL_ecx || c =3D=3D signature_AMD= _ecx) { + if (c =3D=3D signature_INTEL_ecx) { info |=3D CPUINFO_ATOMIC_VMOVDQA; + } else if (c =3D=3D signature_AMD_ecx) { + info |=3D CPUINFO_ATOMIC_VMOVDQA | CPUINFO_ATOMIC_VMOV= DQU; } } } --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684886412; cv=none; d=zohomail.com; s=zohoarc; b=T6qBk3B4PIZAxZpGJVcGAUU2QDBRwWp6rKH2vAApW6hulo+O5VZU2dA8q66FPLbUL0yaNzf5IcOXvEKBifWWcJG6+idM7Z3nLJnWPptnCaMzDSAzyR7rAAq78T6zqZ2dt7kXdXT+i6aBXSa9u5o+bC2rHOMwQ29Bu7Q9tlSe5r0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684886412; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fNltB/G3SYnM9LIr136aCnwE2L2dmhiWgdnpUaCwfho=; b=Cmftyqo6QQVBfl08hM4QXE03AoKfEFDtmXU0EU+Avr43Gqzcab0tXzHYGi0z/Wb1Y4U58CoKB06l5jgEaUEY4I16JIub3vgM5QZQSsbbpGbg4qMbMR52iS65vxoxRUQP7tvCt9lIEMMa4H3AExPfVQMra3cCqX8+9vcqvMz938o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684886412067425.6214806507504; Tue, 23 May 2023 17:00:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1btP-00049s-Le; Tue, 23 May 2023 19:58:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1btN-00049H-6d for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:13 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1btK-0001lP-Im for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:12 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-64d5f65a2f7so103779b3a.1 for ; Tue, 23 May 2023 16:58:10 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886290; x=1687478290; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fNltB/G3SYnM9LIr136aCnwE2L2dmhiWgdnpUaCwfho=; b=AnVhpm9ReBbCL+EEtrUykR0hoODvFuE/C2deP90ik8l/duWh+umh7fmd2VRmyRI1YL 7H2Z26QMgzJhqWBMWpWDMXUt4Ddw18fwrHKUThrpjhIRnNTcg6tZaWblwylUDtnaEahg +B0k1MxBxG+9f/w7mJQxzAJywJcm83Vw3nQchWzV4iNzYJqKqF4ZlabRLr7Qf4V4BaNM xAk8Z/2e7nQcbyYQ90IHKHwcFqMNjoQe75eDdXi8Vbk/O2MJZ5KzHTcUf7bPKkRMC88U 114lN/IWQOuy9CBDZLAHyzSDN6o+HuO56zM+PWod0tlPVUKHeMmlkBUodUIuEb4CNDNJ Tmvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886290; x=1687478290; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fNltB/G3SYnM9LIr136aCnwE2L2dmhiWgdnpUaCwfho=; b=Ca8CZpUXVGAKI6RUhJ66rjrXAa1JAw7YRZVL6k74W9maGpcqJn79LLkI7UPjjNtyRh uGPb7d4bRX8PFKhvpkSZ8vRVmDNIfWGWodbw7hzJ9z9chDhBYnnR+5Qs0Qv5ts5aamJQ tkRE9xrZ1NN0l8ZiIa8tGA8qzaraJjB7svie7cY8euEJdzdQxiraMGXoMJ9fuHDcUTWY B73kbk9307kMlDa65J/6LSEP55gnE1C0YhjlsJsvuXutspdqWkfTTj0U5xlj9xqtf3kq 95ivcY+u50p1WeOxVyivmqqz5lijW4SHvmICezOWx77KD7pwaG+hp12ZIzHzuB2ciYfe h1cw== X-Gm-Message-State: AC+VfDzWfJ7Ro8+rbXJmhVSQFHlKnXFqWsBFumEgYkYs6TIXb4bsy0eW YzKUbz7TuC/oUUK0qM6fxzR4TT+Q6fsZx1x1CMI= X-Google-Smtp-Source: ACHHUZ4cZR8YXBlLB/4chLShVY2iLAom/N1wVlmJW3i7w4tM95JTrt7JX9Beaet1D4q5LOa7011hZQ== X-Received: by 2002:a05:6a00:17a9:b0:647:4dee:62b7 with SMTP id s41-20020a056a0017a900b006474dee62b7mr861795pfg.29.1684886289763; Tue, 23 May 2023 16:58:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell Subject: [PULL 04/28] tcg/i386: Use host/cpuinfo.h Date: Tue, 23 May 2023 16:57:40 -0700 Message-Id: <20230523235804.747803-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886412725100001 Use the CPUINFO_* bits instead of the individual boolean variables that we had been using. Remove all of the init code that was moved over to cpuinfo-i386.c. Note that have_avx512* check both AVX512{F,VL}, as we had previously done during tcg_target_init. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 28 +++++---- tcg/i386/tcg-target.c.inc | 123 ++------------------------------------ 2 files changed, 22 insertions(+), 129 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 0b5a2c68c5..0106946996 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -25,6 +25,8 @@ #ifndef I386_TCG_TARGET_H #define I386_TCG_TARGET_H =20 +#include "host/cpuinfo.h" + #define TCG_TARGET_INSN_UNIT_SIZE 1 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 31 =20 @@ -111,16 +113,22 @@ typedef enum { # define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF #endif =20 -extern bool have_bmi1; -extern bool have_popcnt; -extern bool have_avx1; -extern bool have_avx2; -extern bool have_avx512bw; -extern bool have_avx512dq; -extern bool have_avx512vbmi2; -extern bool have_avx512vl; -extern bool have_movbe; -extern bool have_atomic16; +#define have_bmi1 (cpuinfo & CPUINFO_BMI1) +#define have_popcnt (cpuinfo & CPUINFO_POPCNT) +#define have_avx1 (cpuinfo & CPUINFO_AVX1) +#define have_avx2 (cpuinfo & CPUINFO_AVX2) +#define have_movbe (cpuinfo & CPUINFO_MOVBE) +#define have_atomic16 (cpuinfo & CPUINFO_ATOMIC_VMOVDQA) + +/* + * There are interesting instructions in AVX512, so long as we have AVX512= VL, + * which indicates support for EVEX on sizes smaller than 512 bits. + */ +#define have_avx512vl ((cpuinfo & CPUINFO_AVX512VL) && \ + (cpuinfo & CPUINFO_AVX512F)) +#define have_avx512bw ((cpuinfo & CPUINFO_AVX512BW) && have_avx512vl) +#define have_avx512dq ((cpuinfo & CPUINFO_AVX512DQ) && have_avx512vl) +#define have_avx512vbmi2 ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512v= l) =20 /* optional instructions */ #define TCG_TARGET_HAS_div2_i32 1 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 8b9a5f00e5..bfe9d98b7e 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -158,42 +158,14 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnK= ind kind, int slot) # define SOFTMMU_RESERVE_REGS 0 #endif =20 -/* The host compiler should supply to enable runtime features - detection, as we're not going to go so far as our own inline assembly. - If not available, default values will be assumed. */ -#if defined(CONFIG_CPUID_H) -#include "qemu/cpuid.h" -#endif - /* For 64-bit, we always know that CMOV is available. */ #if TCG_TARGET_REG_BITS =3D=3D 64 -# define have_cmov 1 -#elif defined(CONFIG_CPUID_H) -static bool have_cmov; +# define have_cmov true #else -# define have_cmov 0 -#endif - -/* We need these symbols in tcg-target.h, and we can't properly conditiona= lize - it there. Therefore we always define the variable. */ -bool have_bmi1; -bool have_popcnt; -bool have_avx1; -bool have_avx2; -bool have_avx512bw; -bool have_avx512dq; -bool have_avx512vbmi2; -bool have_avx512vl; -bool have_movbe; -bool have_atomic16; - -#ifdef CONFIG_CPUID_H -static bool have_bmi2; -static bool have_lzcnt; -#else -# define have_bmi2 0 -# define have_lzcnt 0 +# define have_cmov (cpuinfo & CPUINFO_CMOV) #endif +#define have_bmi2 (cpuinfo & CPUINFO_BMI2) +#define have_lzcnt (cpuinfo & CPUINFO_LZCNT) =20 static const tcg_insn_unit *tb_ret_addr; =20 @@ -3961,93 +3933,6 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int c= ount) =20 static void tcg_target_init(TCGContext *s) { -#ifdef CONFIG_CPUID_H - unsigned a, b, c, d, b7 =3D 0, c7 =3D 0; - unsigned max =3D __get_cpuid_max(0, 0); - - if (max >=3D 7) { - /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */ - __cpuid_count(7, 0, a, b7, c7, d); - have_bmi1 =3D (b7 & bit_BMI) !=3D 0; - have_bmi2 =3D (b7 & bit_BMI2) !=3D 0; - } - - if (max >=3D 1) { - __cpuid(1, a, b, c, d); -#ifndef have_cmov - /* For 32-bit, 99% certainty that we're running on hardware that - supports cmov, but we still need to check. In case cmov is not - available, we'll use a small forward branch. */ - have_cmov =3D (d & bit_CMOV) !=3D 0; -#endif - - /* MOVBE is only available on Intel Atom and Haswell CPUs, so we - need to probe for it. */ - have_movbe =3D (c & bit_MOVBE) !=3D 0; - have_popcnt =3D (c & bit_POPCNT) !=3D 0; - - /* There are a number of things we must check before we can be - sure of not hitting invalid opcode. */ - if (c & bit_OSXSAVE) { - unsigned bv =3D xgetbv_low(0); - - if ((bv & 6) =3D=3D 6) { - have_avx1 =3D (c & bit_AVX) !=3D 0; - have_avx2 =3D (b7 & bit_AVX2) !=3D 0; - - /* - * There are interesting instructions in AVX512, so long - * as we have AVX512VL, which indicates support for EVEX - * on sizes smaller than 512 bits. We are required to - * check that OPMASK and all extended ZMM state are enabled - * even if we're not using them -- the insns will fault. - */ - if ((bv & 0xe0) =3D=3D 0xe0 - && (b7 & bit_AVX512F) - && (b7 & bit_AVX512VL)) { - have_avx512vl =3D true; - have_avx512bw =3D (b7 & bit_AVX512BW) !=3D 0; - have_avx512dq =3D (b7 & bit_AVX512DQ) !=3D 0; - have_avx512vbmi2 =3D (c7 & bit_AVX512VBMI2) !=3D 0; - } - - /* - * The Intel SDM has added: - * Processors that enumerate support for Intel=C2=AE AVX - * (by setting the feature flag CPUID.01H:ECX.AVX[bit 28= ]) - * guarantee that the 16-byte memory operations performed - * by the following instructions will always be carried - * out atomically: - * - MOVAPD, MOVAPS, and MOVDQA. - * - VMOVAPD, VMOVAPS, and VMOVDQA when encoded with VEX= .128. - * - VMOVAPD, VMOVAPS, VMOVDQA32, and VMOVDQA64 when enc= oded - * with EVEX.128 and k0 (masking disabled). - * Note that these instructions require the linear address= es - * of their memory operands to be 16-byte aligned. - * - * AMD has provided an even stronger guarantee that proces= sors - * with AVX provide 16-byte atomicity for all cachable, - * naturally aligned single loads and stores, e.g. MOVDQU. - * - * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D1046= 88 - */ - if (have_avx1) { - __cpuid(0, a, b, c, d); - have_atomic16 =3D (c =3D=3D signature_INTEL_ecx || - c =3D=3D signature_AMD_ecx); - } - } - } - } - - max =3D __get_cpuid_max(0x8000000, 0); - if (max >=3D 1) { - __cpuid(0x80000001, a, b, c, d); - /* LZCNT was introduced with AMD Barcelona and Intel Haswell CPUs.= */ - have_lzcnt =3D (c & bit_LZCNT) !=3D 0; - } -#endif /* CONFIG_CPUID_H */ - tcg_target_available_regs[TCG_TYPE_I32] =3D ALL_GENERAL_REGS; if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_target_available_regs[TCG_TYPE_I64] =3D ALL_GENERAL_REGS; --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684886594; cv=none; d=zohomail.com; s=zohoarc; b=JSbhJadigxjj0JFCCcUVaEXK+MK+/TSZc793uI/LajqZehef8BK1HsmkG+Ea7gmUm2OwIeqCs4MypK9THjqF2kYb1j2hvoGP7I7nxBpHIIDU5fd+nSVp4UrQlY0olU4cDY6rQJAeGBqIpCnMq/eccfu/4rtCKH/lYb5ExncbEeA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684886594; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gwqzAqYyG1v/CLSJnBrdO2SKYW9ZIlSrgikgMj70uNU=; b=Gd3TYAlALwCfLOUuMqTZlha5emHTA4kJ6oNrVqF94NQF4MCuO9oBICYmdDLQKFo2gE8rTnSXIeCird9Wwo92xHPzzC5yOox+YDkZ/VRRnOj8c0oueWyw+BTBVl/r+6N9D55QIC24VoZnw/gB++Xk8HHgmZpiuilEpRF0+fs1coA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684886594180227.46695496738153; Tue, 23 May 2023 17:03:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1btQ-0004AH-Bf; Tue, 23 May 2023 19:58:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1btN-00049K-7z for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:13 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1btL-0001lW-CP for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:13 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-64d41d8bc63so123795b3a.0 for ; Tue, 23 May 2023 16:58:10 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886290; x=1687478290; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gwqzAqYyG1v/CLSJnBrdO2SKYW9ZIlSrgikgMj70uNU=; b=FWeNWG4cNcUys1RRJSCkPiuhiBSdj4U2gARVGzWbhsH5qO2/l9bt44HtE8iyr4wD2G Vaa1QgXdFADfci0eNNKhlAoz8RiHNl96DfA2Ay9skYCWfeL2B2GLARVi5+kPdC6QIhtp HlSffnMTeTziT1tRjNmfxNeyGKSvVh6YPQ+4sDNpXpS02e6HLkzD0lWp2NeiySe9Xzau jUbPaxDxGiAd36FerUK8xtWRbSmpLFnxar8fB1zM7mGHH2mIRN0V4SW+A7WqPPsr1Knv 77K7LT92z9vSXhHjFrCzMqwwwx8D0xYkRfoy4QwB7sK17CFzeJXFMmn1/L8bAAnMW2Oj Ir1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886290; x=1687478290; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gwqzAqYyG1v/CLSJnBrdO2SKYW9ZIlSrgikgMj70uNU=; b=YgZ3uYoSBPBHMYbkqZKcosVQCKoJiCG2JnDVTu+knADj4KOkqboiftrOY1vVfZapoo hTWt8wdId/bsYniz+Nu5aO6+MwdTT+MR9tJQjIro3GJQCQEr3G1rcC/WFDwIDAev3eC6 Ko29M1HfXZfmn2lncyfooFOJslIU1vWhw4jqdlA8UPq8alUG+ve1CUtTCJmw0oNfradY cELtGa47nyBmlrBcGFVo7+FKrS/ZYKJissfK/0/JrZs6jnaLyVl5fe/Axfl3jnG/mirR ijljiFfGs4v5xX8GoXBCYhn8/AHzCVEFA3iyeiMVoWqfNDnxBmky6kDXhdFurDH0ktVj Gmrg== X-Gm-Message-State: AC+VfDyCUUkFcrUHZkLif0jE5U6I4QDYB6DLP65kSgQ0EpBnJVdHEmsv vd+NK0bPIcynx5yVJhKQomE9v3S9zHMbSQHgDc8= X-Google-Smtp-Source: ACHHUZ4KHgK0FZfe9zNEyMUKKlub1uSCZUtXc7tHm8GGLY6VhtA7FIDM/fZ4R1DKU8OGq1OBbNXkTA== X-Received: by 2002:a05:6a00:2386:b0:641:3ca2:1aec with SMTP id f6-20020a056a00238600b006413ca21aecmr983960pfc.27.1684886290528; Tue, 23 May 2023 16:58:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 05/28] util/bufferiszero: Use i386 host/cpuinfo.h Date: Tue, 23 May 2023 16:57:41 -0700 Message-Id: <20230523235804.747803-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886595713100001 Use cpuinfo_init() during init_accel(), and the variable cpuinfo during test_buffer_is_zero_next_accel(). Adjust the logic that cycles through the set of accelerators for testing. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- util/bufferiszero.c | 127 ++++++++++++++++---------------------------- 1 file changed, 46 insertions(+), 81 deletions(-) diff --git a/util/bufferiszero.c b/util/bufferiszero.c index 1886bc5ba4..3e6a5dfd63 100644 --- a/util/bufferiszero.c +++ b/util/bufferiszero.c @@ -24,6 +24,7 @@ #include "qemu/osdep.h" #include "qemu/cutils.h" #include "qemu/bswap.h" +#include "host/cpuinfo.h" =20 static bool buffer_zero_int(const void *buf, size_t len) @@ -184,111 +185,75 @@ buffer_zero_avx512(const void *buf, size_t len) } #endif /* CONFIG_AVX512F_OPT */ =20 - -/* Note that for test_buffer_is_zero_next_accel, the most preferred - * ISA must have the least significant bit. - */ -#define CACHE_AVX512F 1 -#define CACHE_AVX2 2 -#define CACHE_SSE4 4 -#define CACHE_SSE2 8 - -/* Make sure that these variables are appropriately initialized when +/* + * Make sure that these variables are appropriately initialized when * SSE2 is enabled on the compiler command-line, but the compiler is * too old to support CONFIG_AVX2_OPT. */ #if defined(CONFIG_AVX512F_OPT) || defined(CONFIG_AVX2_OPT) -# define INIT_CACHE 0 -# define INIT_ACCEL buffer_zero_int +# define INIT_USED 0 +# define INIT_LENGTH 0 +# define INIT_ACCEL buffer_zero_int #else # ifndef __SSE2__ # error "ISA selection confusion" # endif -# define INIT_CACHE CACHE_SSE2 -# define INIT_ACCEL buffer_zero_sse2 +# define INIT_USED CPUINFO_SSE2 +# define INIT_LENGTH 64 +# define INIT_ACCEL buffer_zero_sse2 #endif =20 -static unsigned cpuid_cache =3D INIT_CACHE; +static unsigned used_accel =3D INIT_USED; +static unsigned length_to_accel =3D INIT_LENGTH; static bool (*buffer_accel)(const void *, size_t) =3D INIT_ACCEL; -static int length_to_accel =3D 64; =20 -static void init_accel(unsigned cache) +static unsigned __attribute__((noinline)) +select_accel_cpuinfo(unsigned info) { - bool (*fn)(const void *, size_t) =3D buffer_zero_int; - if (cache & CACHE_SSE2) { - fn =3D buffer_zero_sse2; - length_to_accel =3D 64; - } -#ifdef CONFIG_AVX2_OPT - if (cache & CACHE_SSE4) { - fn =3D buffer_zero_sse4; - length_to_accel =3D 64; - } - if (cache & CACHE_AVX2) { - fn =3D buffer_zero_avx2; - length_to_accel =3D 128; - } -#endif + /* Array is sorted in order of algorithm preference. */ + static const struct { + unsigned bit; + unsigned len; + bool (*fn)(const void *, size_t); + } all[] =3D { #ifdef CONFIG_AVX512F_OPT - if (cache & CACHE_AVX512F) { - fn =3D buffer_zero_avx512; - length_to_accel =3D 256; - } + { CPUINFO_AVX512F, 256, buffer_zero_avx512 }, #endif - buffer_accel =3D fn; +#ifdef CONFIG_AVX2_OPT + { CPUINFO_AVX2, 128, buffer_zero_avx2 }, + { CPUINFO_SSE4, 64, buffer_zero_sse4 }, +#endif + { CPUINFO_SSE2, 64, buffer_zero_sse2 }, + { CPUINFO_ALWAYS, 0, buffer_zero_int }, + }; + + for (unsigned i =3D 0; i < ARRAY_SIZE(all); ++i) { + if (info & all[i].bit) { + length_to_accel =3D all[i].len; + buffer_accel =3D all[i].fn; + return all[i].bit; + } + } + return 0; } =20 #if defined(CONFIG_AVX512F_OPT) || defined(CONFIG_AVX2_OPT) -#include "qemu/cpuid.h" - -static void __attribute__((constructor)) init_cpuid_cache(void) +static void __attribute__((constructor)) init_accel(void) { - unsigned max =3D __get_cpuid_max(0, NULL); - int a, b, c, d; - unsigned cache =3D 0; - - if (max >=3D 1) { - __cpuid(1, a, b, c, d); - if (d & bit_SSE2) { - cache |=3D CACHE_SSE2; - } - if (c & bit_SSE4_1) { - cache |=3D CACHE_SSE4; - } - - /* We must check that AVX is not just available, but usable. */ - if ((c & bit_OSXSAVE) && (c & bit_AVX) && max >=3D 7) { - unsigned bv =3D xgetbv_low(0); - __cpuid_count(7, 0, a, b, c, d); - if ((bv & 0x6) =3D=3D 0x6 && (b & bit_AVX2)) { - cache |=3D CACHE_AVX2; - } - /* 0xe6: - * XCR0[7:5] =3D 111b (OPMASK state, upper 256-bit of ZMM0-ZMM= 15 - * and ZMM16-ZMM31 state are enabled by OS) - * XCR0[2:1] =3D 11b (XMM state and YMM state are enabled by O= S) - */ - if ((bv & 0xe6) =3D=3D 0xe6 && (b & bit_AVX512F)) { - cache |=3D CACHE_AVX512F; - } - } - } - cpuid_cache =3D cache; - init_accel(cache); + used_accel =3D select_accel_cpuinfo(cpuinfo_init()); } #endif /* CONFIG_AVX2_OPT */ =20 bool test_buffer_is_zero_next_accel(void) { - /* If no bits set, we just tested buffer_zero_int, and there - are no more acceleration options to test. */ - if (cpuid_cache =3D=3D 0) { - return false; - } - /* Disable the accelerator we used before and select a new one. */ - cpuid_cache &=3D cpuid_cache - 1; - init_accel(cpuid_cache); - return true; + /* + * Accumulate the accelerators that we've already tested, and + * remove them from the set to test this round. We'll get back + * a zero from select_accel_cpuinfo when there are no more. + */ + unsigned used =3D select_accel_cpuinfo(cpuinfo & ~used_accel); + used_accel |=3D used; + return used; } =20 static bool select_accel_fn(const void *buf, size_t len) --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684886418; cv=none; d=zohomail.com; s=zohoarc; b=aia34OHeBRX273V3c/wG3TQeRdAS/j2dwsnIBszqd5KFi+ZmvV6jPgC8uzaqG4l2wpsrAEBJCcSiWllLTkLNG9+MIxaVzXMM6sU2ulO1Rb5v0w/bilbDBibCLeOyF3ZX2BFEy7JaObSk3xqIHOPfvvm3s1xULxqlSzD12KBORWg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684886418; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7ye0/RXUVZWBrvEwXDswgbk/0qm/ligDVrCm5lhuZP0=; b=ZWDWO0FjDQ7ZVWoebiq1Bmhqz3w+uVnlNHCuu9Np55YaFdnx2zuk4b8w5nh3kZBgABs78KTRmX/vUxoAot5c8i3PB5zHCY04Ozlq7Okky/MPdMDG7bgHZTHmh/wUMngsZaUF6QaMw+7D60CjxO4gmWT4yXBlZyqcZhugoRrDVjM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684886418164311.06142935780895; Tue, 23 May 2023 17:00:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1btU-0004BK-OW; Tue, 23 May 2023 19:58:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1btO-00049r-EK for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:15 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1btM-0001mh-HL for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:14 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-64d3491609fso102340b3a.3 for ; Tue, 23 May 2023 16:58:12 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886291; x=1687478291; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7ye0/RXUVZWBrvEwXDswgbk/0qm/ligDVrCm5lhuZP0=; b=iEdq+DMv47db3W/6eb6wJDsYOz+GsrBJzgUBX6t/3H0Z8BdUkOqfrdhWaeVzFpRiWe +qrxn1YbIkStcws9d7S5jAh0c0uPA+xz7eSmXvvz7KHZQYA2xzDPaWkKiW7Rst5kivpc Ze9bV1uyLLFw0bp1HYLaf3D2bkshXf07aH4VypfV1LbpIFPf0yQX4vuxaS7jq0QOYoH0 I9ohpZyQkowp2dt7IeMQi0Lws9m0i97O8jWuktxJAVUTgQyDNwdXtYv8w7mBUJiF0B7m zMwZ4krQjtXKL5lM+c0gsC/Bfr64uCYpiCQAhoT/xMxGpz58fT8bk8bWQTMWV+lKhekm MDbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886291; x=1687478291; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7ye0/RXUVZWBrvEwXDswgbk/0qm/ligDVrCm5lhuZP0=; b=Clx3jhT/JSGYu4LebTmbF5WAfXWgG5DM00g7RBv56GPDOSVsvt/JWkRvRudhLqhtQB FhnvhgvCwO6+rJ+xNoAwWoKo+BDOAr8oukebrcAtZmN+jZiEujXeUVTMXarMKstRa4jy Y6eBBP9DphO/WQvJoeLBVZoHsdVwYhAbe6yCpn+lXvFKKqe/basACp9vcE2d+cbPfT2w bQd4xVvIHIYcsflFmGWc/gTNzGUMusmrTCoeyahy5ANaCsCP7bTWjoGV2CW1sGAiRelB 1T3sNaYPeH7L/OZPmcbFIQ/5Yar8m5ZrTWguPBIETyWMyOjsgtfC8U82dQOgRIgYe7yf Yd5A== X-Gm-Message-State: AC+VfDy45Uu35x7kccN4ISSEki9Z42QJAtffdoBqiy2N+OqMpnw3FdiN e9oSMwstDQK0VBCtj4r9lvaGzzDOw+lSt5R8F+4= X-Google-Smtp-Source: ACHHUZ5l8z10pfzFMfFyXZMqJ5zDTu4Ugw63P3UyNkmRxspvGKCySle5QTowCoE0GdoUZrIaUbDPtQ== X-Received: by 2002:a05:6a00:22c2:b0:64c:c5f9:1533 with SMTP id f2-20020a056a0022c200b0064cc5f91533mr1048118pfj.33.1684886291261; Tue, 23 May 2023 16:58:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Juan Quintela Subject: [PULL 06/28] migration/xbzrle: Shuffle function order Date: Tue, 23 May 2023 16:57:42 -0700 Message-Id: <20230523235804.747803-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886419842100003 Place the CONFIG_AVX512BW_OPT block at the top, which will aid function selection in the next patch. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Juan Quintela Signed-off-by: Richard Henderson --- migration/xbzrle.c | 244 ++++++++++++++++++++++----------------------- 1 file changed, 122 insertions(+), 122 deletions(-) diff --git a/migration/xbzrle.c b/migration/xbzrle.c index 258e4959c9..751b5428f7 100644 --- a/migration/xbzrle.c +++ b/migration/xbzrle.c @@ -15,6 +15,128 @@ #include "qemu/host-utils.h" #include "xbzrle.h" =20 +#if defined(CONFIG_AVX512BW_OPT) +#include + +int __attribute__((target("avx512bw"))) +xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t *new_buf, int slen, + uint8_t *dst, int dlen) +{ + uint32_t zrun_len =3D 0, nzrun_len =3D 0; + int d =3D 0, i =3D 0, num =3D 0; + uint8_t *nzrun_start =3D NULL; + /* add 1 to include residual part in main loop */ + uint32_t count512s =3D (slen >> 6) + 1; + /* countResidual is tail of data, i.e., countResidual =3D slen % 64 */ + uint32_t count_residual =3D slen & 0b111111; + bool never_same =3D true; + uint64_t mask_residual =3D 1; + mask_residual <<=3D count_residual; + mask_residual -=3D 1; + __m512i r =3D _mm512_set1_epi32(0); + + while (count512s) { + int bytes_to_check =3D 64; + uint64_t mask =3D 0xffffffffffffffff; + if (count512s =3D=3D 1) { + bytes_to_check =3D count_residual; + mask =3D mask_residual; + } + __m512i old_data =3D _mm512_mask_loadu_epi8(r, + mask, old_buf + i); + __m512i new_data =3D _mm512_mask_loadu_epi8(r, + mask, new_buf + i); + uint64_t comp =3D _mm512_cmpeq_epi8_mask(old_data, new_data); + count512s--; + + bool is_same =3D (comp & 0x1); + while (bytes_to_check) { + if (d + 2 > dlen) { + return -1; + } + if (is_same) { + if (nzrun_len) { + d +=3D uleb128_encode_small(dst + d, nzrun_len); + if (d + nzrun_len > dlen) { + return -1; + } + nzrun_start =3D new_buf + i - nzrun_len; + memcpy(dst + d, nzrun_start, nzrun_len); + d +=3D nzrun_len; + nzrun_len =3D 0; + } + /* 64 data at a time for speed */ + if (count512s && (comp =3D=3D 0xffffffffffffffff)) { + i +=3D 64; + zrun_len +=3D 64; + break; + } + never_same =3D false; + num =3D ctz64(~comp); + num =3D (num < bytes_to_check) ? num : bytes_to_check; + zrun_len +=3D num; + bytes_to_check -=3D num; + comp >>=3D num; + i +=3D num; + if (bytes_to_check) { + /* still has different data after same data */ + d +=3D uleb128_encode_small(dst + d, zrun_len); + zrun_len =3D 0; + } else { + break; + } + } + if (never_same || zrun_len) { + /* + * never_same only acts if + * data begins with diff in first count512s + */ + d +=3D uleb128_encode_small(dst + d, zrun_len); + zrun_len =3D 0; + never_same =3D false; + } + /* has diff, 64 data at a time for speed */ + if ((bytes_to_check =3D=3D 64) && (comp =3D=3D 0x0)) { + i +=3D 64; + nzrun_len +=3D 64; + break; + } + num =3D ctz64(comp); + num =3D (num < bytes_to_check) ? num : bytes_to_check; + nzrun_len +=3D num; + bytes_to_check -=3D num; + comp >>=3D num; + i +=3D num; + if (bytes_to_check) { + /* mask like 111000 */ + d +=3D uleb128_encode_small(dst + d, nzrun_len); + /* overflow */ + if (d + nzrun_len > dlen) { + return -1; + } + nzrun_start =3D new_buf + i - nzrun_len; + memcpy(dst + d, nzrun_start, nzrun_len); + d +=3D nzrun_len; + nzrun_len =3D 0; + is_same =3D true; + } + } + } + + if (nzrun_len !=3D 0) { + d +=3D uleb128_encode_small(dst + d, nzrun_len); + /* overflow */ + if (d + nzrun_len > dlen) { + return -1; + } + nzrun_start =3D new_buf + i - nzrun_len; + memcpy(dst + d, nzrun_start, nzrun_len); + d +=3D nzrun_len; + } + return d; +} +#endif + /* page =3D zrun nzrun | zrun nzrun page @@ -175,125 +297,3 @@ int xbzrle_decode_buffer(uint8_t *src, int slen, uint= 8_t *dst, int dlen) =20 return d; } - -#if defined(CONFIG_AVX512BW_OPT) -#include - -int __attribute__((target("avx512bw"))) -xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t *new_buf, int slen, - uint8_t *dst, int dlen) -{ - uint32_t zrun_len =3D 0, nzrun_len =3D 0; - int d =3D 0, i =3D 0, num =3D 0; - uint8_t *nzrun_start =3D NULL; - /* add 1 to include residual part in main loop */ - uint32_t count512s =3D (slen >> 6) + 1; - /* countResidual is tail of data, i.e., countResidual =3D slen % 64 */ - uint32_t count_residual =3D slen & 0b111111; - bool never_same =3D true; - uint64_t mask_residual =3D 1; - mask_residual <<=3D count_residual; - mask_residual -=3D 1; - __m512i r =3D _mm512_set1_epi32(0); - - while (count512s) { - int bytes_to_check =3D 64; - uint64_t mask =3D 0xffffffffffffffff; - if (count512s =3D=3D 1) { - bytes_to_check =3D count_residual; - mask =3D mask_residual; - } - __m512i old_data =3D _mm512_mask_loadu_epi8(r, - mask, old_buf + i); - __m512i new_data =3D _mm512_mask_loadu_epi8(r, - mask, new_buf + i); - uint64_t comp =3D _mm512_cmpeq_epi8_mask(old_data, new_data); - count512s--; - - bool is_same =3D (comp & 0x1); - while (bytes_to_check) { - if (d + 2 > dlen) { - return -1; - } - if (is_same) { - if (nzrun_len) { - d +=3D uleb128_encode_small(dst + d, nzrun_len); - if (d + nzrun_len > dlen) { - return -1; - } - nzrun_start =3D new_buf + i - nzrun_len; - memcpy(dst + d, nzrun_start, nzrun_len); - d +=3D nzrun_len; - nzrun_len =3D 0; - } - /* 64 data at a time for speed */ - if (count512s && (comp =3D=3D 0xffffffffffffffff)) { - i +=3D 64; - zrun_len +=3D 64; - break; - } - never_same =3D false; - num =3D ctz64(~comp); - num =3D (num < bytes_to_check) ? num : bytes_to_check; - zrun_len +=3D num; - bytes_to_check -=3D num; - comp >>=3D num; - i +=3D num; - if (bytes_to_check) { - /* still has different data after same data */ - d +=3D uleb128_encode_small(dst + d, zrun_len); - zrun_len =3D 0; - } else { - break; - } - } - if (never_same || zrun_len) { - /* - * never_same only acts if - * data begins with diff in first count512s - */ - d +=3D uleb128_encode_small(dst + d, zrun_len); - zrun_len =3D 0; - never_same =3D false; - } - /* has diff, 64 data at a time for speed */ - if ((bytes_to_check =3D=3D 64) && (comp =3D=3D 0x0)) { - i +=3D 64; - nzrun_len +=3D 64; - break; - } - num =3D ctz64(comp); - num =3D (num < bytes_to_check) ? num : bytes_to_check; - nzrun_len +=3D num; - bytes_to_check -=3D num; - comp >>=3D num; - i +=3D num; - if (bytes_to_check) { - /* mask like 111000 */ - d +=3D uleb128_encode_small(dst + d, nzrun_len); - /* overflow */ - if (d + nzrun_len > dlen) { - return -1; - } - nzrun_start =3D new_buf + i - nzrun_len; - memcpy(dst + d, nzrun_start, nzrun_len); - d +=3D nzrun_len; - nzrun_len =3D 0; - is_same =3D true; - } - } - } - - if (nzrun_len !=3D 0) { - d +=3D uleb128_encode_small(dst + d, nzrun_len); - /* overflow */ - if (d + nzrun_len > dlen) { - return -1; - } - nzrun_start =3D new_buf + i - nzrun_len; - memcpy(dst + d, nzrun_start, nzrun_len); - d +=3D nzrun_len; - } - return d; -} -#endif --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684886622; cv=none; d=zohomail.com; s=zohoarc; b=C4gKIZp+7r2lMMbtTfOizDL+a3U12zrP7ODJQViWkMH4YoquwJ3ZV4hOjD7d6zbAsZS2TbXX0AWg/TpSfcZz0vTYxjmarTHTxPIkxTgixFtIiwGlcczhLpfyTAmR+le15NiJVdmj/q/5l5WWJFbf3DAYok1taiaW5GSojjE4sac= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684886622; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vatX/eqgfBkmzTBE7D9o3RP4GGfUvt6lQl1eSLzfC3w=; b=Sse3k2OLkf0CvMKISo9Lew4pmBMaFbPXjjidOnUa6w+FuxyOGTm/H1FNBUEqnF9KbptRSVxCPd03R/L87xf/vML2sUPpc0UwZCEyXr9Q61lf2HczkteCWz8aHVMZvjet31U8RF4AnGuEONp7vBw75oP0UJNOLe4MbeDuVzoHgAE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684886622383727.0899693691541; Tue, 23 May 2023 17:03:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1btV-0004Be-Hk; Tue, 23 May 2023 19:58:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1btQ-0004AY-OY for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:17 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1btN-0001mr-NB for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:16 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-64d5b4c400fso155746b3a.1 for ; Tue, 23 May 2023 16:58:13 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886292; x=1687478292; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vatX/eqgfBkmzTBE7D9o3RP4GGfUvt6lQl1eSLzfC3w=; b=H/tRtZyINE/1jWeKxNKpBBykoUyxlcsd9ARYEjukjaZIheadhRtXQqXD6xht2Ge8I4 x89pkoKsEeo0Rhw3YHGL1UT5q/itr39fDLHgYNVB46+STRB56/q+7yOmMFM5zKeNR+H/ T2JCvDrXRyDdcbusXB2PYtmEKuoZTjtgFcL3gCKtAgVRWpDgmtQxCrX1Yeeuf8ovlFiu +pG6DMc2wKOi0Insilrmj95GNQbcVxA4/Fqp5HDdkDmaLBrpXAbbE1lDL9QozP9LEKm+ GvXEHR74go/wt3P3qEVQuvXklV/ffy0XKNkpZQa1BAaA34uMaSu+D1OXKXEaBheOgl8C EdVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886292; x=1687478292; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vatX/eqgfBkmzTBE7D9o3RP4GGfUvt6lQl1eSLzfC3w=; b=NQiZXmIKH6fcS28ZVMmW2oq+nOHQ+Y/HmtH2tg2DZft1YhQtcCJw1C7Dqv3681ihpu 3ZlTLqq66ViCGv+eQLbj5YhIPcE85j02j3qhzs1VZn4YNK8OjQoo1es0SynE3RI88l/S VajrnkuPOR7geRiciokXCW7k91mG4a9QKDTXDy3+/7VVtejxyGxx8u0y7oUkSYU98Pbd q3/ewE8RCqp7n2CurWizLxyFM58cN8S5Sr9yO3As7rI8zUJ6tXP5CrcKHRcjAH3PtFRV //E1uCrh/qWGKZoXfCsek2HwDprYMPBttDq5F661fVwuZy1aTpZAHn9+haMnMJqfY/jb OApw== X-Gm-Message-State: AC+VfDz4QOY6PExliP1PQM3u2ekqHUl4BXnQQdZisnUzaBPzAM/6K+bk /vL4gUzraKl6mEmOCPgOOZKJByV3mCAwnMxXU1g= X-Google-Smtp-Source: ACHHUZ5YebWULZv/IjOqavF7WmDKWKOQoo2wdPiBG9b2LLghf2ClSKg8st2QW/fn3uQhU08/bLiIYw== X-Received: by 2002:a05:6a00:2389:b0:636:e52f:631e with SMTP id f9-20020a056a00238900b00636e52f631emr847911pfc.1.1684886292152; Tue, 23 May 2023 16:58:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Juan Quintela Subject: [PULL 07/28] migration/xbzrle: Use i386 host/cpuinfo.h Date: Tue, 23 May 2023 16:57:43 -0700 Message-Id: <20230523235804.747803-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886623750100009 Perform the function selection once, and only if CONFIG_AVX512_OPT is enabled. Centralize the selection to xbzrle.c, instead of spreading the init across 3 files. Remove xbzrle-bench.c. The benefit of being able to benchmark the different implementations is less important than not peeking into the internals of the implementation. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Juan Quintela Signed-off-by: Richard Henderson --- migration/xbzrle.h | 5 +- migration/ram.c | 34 +-- migration/xbzrle.c | 26 +- tests/bench/xbzrle-bench.c | 469 ------------------------------------- tests/unit/test-xbzrle.c | 49 +--- tests/bench/meson.build | 6 - 6 files changed, 39 insertions(+), 550 deletions(-) delete mode 100644 tests/bench/xbzrle-bench.c diff --git a/migration/xbzrle.h b/migration/xbzrle.h index 6feb49160a..39e651b9ec 100644 --- a/migration/xbzrle.h +++ b/migration/xbzrle.h @@ -18,8 +18,5 @@ int xbzrle_encode_buffer(uint8_t *old_buf, uint8_t *new_b= uf, int slen, uint8_t *dst, int dlen); =20 int xbzrle_decode_buffer(uint8_t *src, int slen, uint8_t *dst, int dlen); -#if defined(CONFIG_AVX512BW_OPT) -int xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t *new_buf, int sl= en, - uint8_t *dst, int dlen); -#endif + #endif diff --git a/migration/ram.c b/migration/ram.c index 9fb076fa58..88a6c82e63 100644 --- a/migration/ram.c +++ b/migration/ram.c @@ -90,34 +90,6 @@ #define RAM_SAVE_FLAG_MULTIFD_FLUSH 0x200 /* We can't use any flag that is bigger than 0x200 */ =20 -int (*xbzrle_encode_buffer_func)(uint8_t *, uint8_t *, int, - uint8_t *, int) =3D xbzrle_encode_buffer; -#if defined(CONFIG_AVX512BW_OPT) -#include "qemu/cpuid.h" -static void __attribute__((constructor)) init_cpu_flag(void) -{ - unsigned max =3D __get_cpuid_max(0, NULL); - int a, b, c, d; - if (max >=3D 1) { - __cpuid(1, a, b, c, d); - /* We must check that AVX is not just available, but usable. */ - if ((c & bit_OSXSAVE) && (c & bit_AVX) && max >=3D 7) { - int bv; - __asm("xgetbv" : "=3Da"(bv), "=3Dd"(d) : "c"(0)); - __cpuid_count(7, 0, a, b, c, d); - /* 0xe6: - * XCR0[7:5] =3D 111b (OPMASK state, upper 256-bit of ZMM0-ZMM= 15 - * and ZMM16-ZMM31 state are enabled by OS) - * XCR0[2:1] =3D 11b (XMM state and YMM state are enabled by O= S) - */ - if ((bv & 0xe6) =3D=3D 0xe6 && (b & bit_AVX512BW)) { - xbzrle_encode_buffer_func =3D xbzrle_encode_buffer_avx512; - } - } - } -} -#endif - XBZRLECacheStats xbzrle_counters; =20 /* used by the search for pages to send */ @@ -660,9 +632,9 @@ static int save_xbzrle_page(RAMState *rs, PageSearchSta= tus *pss, memcpy(XBZRLE.current_buf, *current_data, TARGET_PAGE_SIZE); =20 /* XBZRLE encoding (if there is no overflow) */ - encoded_len =3D xbzrle_encode_buffer_func(prev_cached_page, XBZRLE.cur= rent_buf, - TARGET_PAGE_SIZE, XBZRLE.encod= ed_buf, - TARGET_PAGE_SIZE); + encoded_len =3D xbzrle_encode_buffer(prev_cached_page, XBZRLE.current_= buf, + TARGET_PAGE_SIZE, XBZRLE.encoded_bu= f, + TARGET_PAGE_SIZE); =20 /* * Update the cache contents, so that it corresponds to the data diff --git a/migration/xbzrle.c b/migration/xbzrle.c index 751b5428f7..3eddcf249b 100644 --- a/migration/xbzrle.c +++ b/migration/xbzrle.c @@ -17,8 +17,9 @@ =20 #if defined(CONFIG_AVX512BW_OPT) #include +#include "host/cpuinfo.h" =20 -int __attribute__((target("avx512bw"))) +static int __attribute__((target("avx512bw"))) xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t *new_buf, int slen, uint8_t *dst, int dlen) { @@ -135,6 +136,29 @@ xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t = *new_buf, int slen, } return d; } + +static int xbzrle_encode_buffer_int(uint8_t *old_buf, uint8_t *new_buf, + int slen, uint8_t *dst, int dlen); + +static int (*accel_func)(uint8_t *, uint8_t *, int, uint8_t *, int); + +static void __attribute__((constructor)) init_accel(void) +{ + unsigned info =3D cpuinfo_init(); + if (info & CPUINFO_AVX512BW) { + accel_func =3D xbzrle_encode_buffer_avx512; + } else { + accel_func =3D xbzrle_encode_buffer_int; + } +} + +int xbzrle_encode_buffer(uint8_t *old_buf, uint8_t *new_buf, int slen, + uint8_t *dst, int dlen) +{ + return accel_func(old_buf, new_buf, slen, dst, dlen); +} + +#define xbzrle_encode_buffer xbzrle_encode_buffer_int #endif =20 /* diff --git a/tests/bench/xbzrle-bench.c b/tests/bench/xbzrle-bench.c deleted file mode 100644 index 8848a3a32d..0000000000 --- a/tests/bench/xbzrle-bench.c +++ /dev/null @@ -1,469 +0,0 @@ -/* - * Xor Based Zero Run Length Encoding unit tests. - * - * Copyright 2013 Red Hat, Inc. and/or its affiliates - * - * Authors: - * Orit Wasserman - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - * - */ -#include "qemu/osdep.h" -#include "qemu/cutils.h" -#include "../migration/xbzrle.h" - -#if defined(CONFIG_AVX512BW_OPT) -#define XBZRLE_PAGE_SIZE 4096 -static bool is_cpu_support_avx512bw; -#include "qemu/cpuid.h" -static void __attribute__((constructor)) init_cpu_flag(void) -{ - unsigned max =3D __get_cpuid_max(0, NULL); - int a, b, c, d; - is_cpu_support_avx512bw =3D false; - if (max >=3D 1) { - __cpuid(1, a, b, c, d); - /* We must check that AVX is not just available, but usable. */ - if ((c & bit_OSXSAVE) && (c & bit_AVX) && max >=3D 7) { - int bv; - __asm("xgetbv" : "=3Da"(bv), "=3Dd"(d) : "c"(0)); - __cpuid_count(7, 0, a, b, c, d); - /* 0xe6: - * XCR0[7:5] =3D 111b (OPMASK state, upper 256-bit of ZMM0-ZMM= 15 - * and ZMM16-ZMM31 state are enabled by OS) - * XCR0[2:1] =3D 11b (XMM state and YMM state are enabled by O= S) - */ - if ((bv & 0xe6) =3D=3D 0xe6 && (b & bit_AVX512BW)) { - is_cpu_support_avx512bw =3D true; - } - } - } - return ; -} - -struct ResTime { - float t_raw; - float t_512; -}; - - -/* Function prototypes -int xbzrle_encode_buffer_avx512(uint8_t *old_buf, uint8_t *new_buf, int sl= en, - uint8_t *dst, int dlen); -*/ -static void encode_decode_zero(struct ResTime *res) -{ - uint8_t *buffer =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *compressed =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *buffer512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *compressed512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - int i =3D 0; - int dlen =3D 0, dlen512 =3D 0; - int diff_len =3D g_test_rand_int_range(0, XBZRLE_PAGE_SIZE - 1006); - - for (i =3D diff_len; i > 0; i--) { - buffer[1000 + i] =3D i; - buffer512[1000 + i] =3D i; - } - - buffer[1000 + diff_len + 3] =3D 103; - buffer[1000 + diff_len + 5] =3D 105; - - buffer512[1000 + diff_len + 3] =3D 103; - buffer512[1000 + diff_len + 5] =3D 105; - - /* encode zero page */ - time_t t_start, t_end, t_start512, t_end512; - t_start =3D clock(); - dlen =3D xbzrle_encode_buffer(buffer, buffer, XBZRLE_PAGE_SIZE, compre= ssed, - XBZRLE_PAGE_SIZE); - t_end =3D clock(); - float time_val =3D difftime(t_end, t_start); - g_assert(dlen =3D=3D 0); - - t_start512 =3D clock(); - dlen512 =3D xbzrle_encode_buffer_avx512(buffer512, buffer512, XBZRLE_P= AGE_SIZE, - compressed512, XBZRLE_PAGE_SIZE); - t_end512 =3D clock(); - float time_val512 =3D difftime(t_end512, t_start512); - g_assert(dlen512 =3D=3D 0); - - res->t_raw =3D time_val; - res->t_512 =3D time_val512; - - g_free(buffer); - g_free(compressed); - g_free(buffer512); - g_free(compressed512); - -} - -static void test_encode_decode_zero_avx512(void) -{ - int i; - float time_raw =3D 0.0, time_512 =3D 0.0; - struct ResTime res; - for (i =3D 0; i < 10000; i++) { - encode_decode_zero(&res); - time_raw +=3D res.t_raw; - time_512 +=3D res.t_512; - } - printf("Zero test:\n"); - printf("Raw xbzrle_encode time is %f ms\n", time_raw); - printf("512 xbzrle_encode time is %f ms\n", time_512); -} - -static void encode_decode_unchanged(struct ResTime *res) -{ - uint8_t *compressed =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *test =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *compressed512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *test512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - int i =3D 0; - int dlen =3D 0, dlen512 =3D 0; - int diff_len =3D g_test_rand_int_range(0, XBZRLE_PAGE_SIZE - 1006); - - for (i =3D diff_len; i > 0; i--) { - test[1000 + i] =3D i + 4; - test512[1000 + i] =3D i + 4; - } - - test[1000 + diff_len + 3] =3D 107; - test[1000 + diff_len + 5] =3D 109; - - test512[1000 + diff_len + 3] =3D 107; - test512[1000 + diff_len + 5] =3D 109; - - /* test unchanged buffer */ - time_t t_start, t_end, t_start512, t_end512; - t_start =3D clock(); - dlen =3D xbzrle_encode_buffer(test, test, XBZRLE_PAGE_SIZE, compressed, - XBZRLE_PAGE_SIZE); - t_end =3D clock(); - float time_val =3D difftime(t_end, t_start); - g_assert(dlen =3D=3D 0); - - t_start512 =3D clock(); - dlen512 =3D xbzrle_encode_buffer_avx512(test512, test512, XBZRLE_PAGE_= SIZE, - compressed512, XBZRLE_PAGE_SIZE); - t_end512 =3D clock(); - float time_val512 =3D difftime(t_end512, t_start512); - g_assert(dlen512 =3D=3D 0); - - res->t_raw =3D time_val; - res->t_512 =3D time_val512; - - g_free(test); - g_free(compressed); - g_free(test512); - g_free(compressed512); - -} - -static void test_encode_decode_unchanged_avx512(void) -{ - int i; - float time_raw =3D 0.0, time_512 =3D 0.0; - struct ResTime res; - for (i =3D 0; i < 10000; i++) { - encode_decode_unchanged(&res); - time_raw +=3D res.t_raw; - time_512 +=3D res.t_512; - } - printf("Unchanged test:\n"); - printf("Raw xbzrle_encode time is %f ms\n", time_raw); - printf("512 xbzrle_encode time is %f ms\n", time_512); -} - -static void encode_decode_1_byte(struct ResTime *res) -{ - uint8_t *buffer =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *test =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *compressed =3D g_malloc(XBZRLE_PAGE_SIZE); - uint8_t *buffer512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *test512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *compressed512 =3D g_malloc(XBZRLE_PAGE_SIZE); - int dlen =3D 0, rc =3D 0, dlen512 =3D 0, rc512 =3D 0; - uint8_t buf[2]; - uint8_t buf512[2]; - - test[XBZRLE_PAGE_SIZE - 1] =3D 1; - test512[XBZRLE_PAGE_SIZE - 1] =3D 1; - - time_t t_start, t_end, t_start512, t_end512; - t_start =3D clock(); - dlen =3D xbzrle_encode_buffer(buffer, test, XBZRLE_PAGE_SIZE, compress= ed, - XBZRLE_PAGE_SIZE); - t_end =3D clock(); - float time_val =3D difftime(t_end, t_start); - g_assert(dlen =3D=3D (uleb128_encode_small(&buf[0], 4095) + 2)); - - rc =3D xbzrle_decode_buffer(compressed, dlen, buffer, XBZRLE_PAGE_SIZE= ); - g_assert(rc =3D=3D XBZRLE_PAGE_SIZE); - g_assert(memcmp(test, buffer, XBZRLE_PAGE_SIZE) =3D=3D 0); - - t_start512 =3D clock(); - dlen512 =3D xbzrle_encode_buffer_avx512(buffer512, test512, XBZRLE_PAG= E_SIZE, - compressed512, XBZRLE_PAGE_SIZE); - t_end512 =3D clock(); - float time_val512 =3D difftime(t_end512, t_start512); - g_assert(dlen512 =3D=3D (uleb128_encode_small(&buf512[0], 4095) + 2)); - - rc512 =3D xbzrle_decode_buffer(compressed512, dlen512, buffer512, - XBZRLE_PAGE_SIZE); - g_assert(rc512 =3D=3D XBZRLE_PAGE_SIZE); - g_assert(memcmp(test512, buffer512, XBZRLE_PAGE_SIZE) =3D=3D 0); - - res->t_raw =3D time_val; - res->t_512 =3D time_val512; - - g_free(buffer); - g_free(compressed); - g_free(test); - g_free(buffer512); - g_free(compressed512); - g_free(test512); - -} - -static void test_encode_decode_1_byte_avx512(void) -{ - int i; - float time_raw =3D 0.0, time_512 =3D 0.0; - struct ResTime res; - for (i =3D 0; i < 10000; i++) { - encode_decode_1_byte(&res); - time_raw +=3D res.t_raw; - time_512 +=3D res.t_512; - } - printf("1 byte test:\n"); - printf("Raw xbzrle_encode time is %f ms\n", time_raw); - printf("512 xbzrle_encode time is %f ms\n", time_512); -} - -static void encode_decode_overflow(struct ResTime *res) -{ - uint8_t *compressed =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *test =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *buffer =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *compressed512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *test512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *buffer512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - int i =3D 0, rc =3D 0, rc512 =3D 0; - - for (i =3D 0; i < XBZRLE_PAGE_SIZE / 2 - 1; i++) { - test[i * 2] =3D 1; - test512[i * 2] =3D 1; - } - - /* encode overflow */ - time_t t_start, t_end, t_start512, t_end512; - t_start =3D clock(); - rc =3D xbzrle_encode_buffer(buffer, test, XBZRLE_PAGE_SIZE, compressed, - XBZRLE_PAGE_SIZE); - t_end =3D clock(); - float time_val =3D difftime(t_end, t_start); - g_assert(rc =3D=3D -1); - - t_start512 =3D clock(); - rc512 =3D xbzrle_encode_buffer_avx512(buffer512, test512, XBZRLE_PAGE_= SIZE, - compressed512, XBZRLE_PAGE_SIZE); - t_end512 =3D clock(); - float time_val512 =3D difftime(t_end512, t_start512); - g_assert(rc512 =3D=3D -1); - - res->t_raw =3D time_val; - res->t_512 =3D time_val512; - - g_free(buffer); - g_free(compressed); - g_free(test); - g_free(buffer512); - g_free(compressed512); - g_free(test512); - -} - -static void test_encode_decode_overflow_avx512(void) -{ - int i; - float time_raw =3D 0.0, time_512 =3D 0.0; - struct ResTime res; - for (i =3D 0; i < 10000; i++) { - encode_decode_overflow(&res); - time_raw +=3D res.t_raw; - time_512 +=3D res.t_512; - } - printf("Overflow test:\n"); - printf("Raw xbzrle_encode time is %f ms\n", time_raw); - printf("512 xbzrle_encode time is %f ms\n", time_512); -} - -static void encode_decode_range_avx512(struct ResTime *res) -{ - uint8_t *buffer =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *compressed =3D g_malloc(XBZRLE_PAGE_SIZE); - uint8_t *test =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *buffer512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *compressed512 =3D g_malloc(XBZRLE_PAGE_SIZE); - uint8_t *test512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - int i =3D 0, rc =3D 0, rc512 =3D 0; - int dlen =3D 0, dlen512 =3D 0; - - int diff_len =3D g_test_rand_int_range(0, XBZRLE_PAGE_SIZE - 1006); - - for (i =3D diff_len; i > 0; i--) { - buffer[1000 + i] =3D i; - test[1000 + i] =3D i + 4; - buffer512[1000 + i] =3D i; - test512[1000 + i] =3D i + 4; - } - - buffer[1000 + diff_len + 3] =3D 103; - test[1000 + diff_len + 3] =3D 107; - - buffer[1000 + diff_len + 5] =3D 105; - test[1000 + diff_len + 5] =3D 109; - - buffer512[1000 + diff_len + 3] =3D 103; - test512[1000 + diff_len + 3] =3D 107; - - buffer512[1000 + diff_len + 5] =3D 105; - test512[1000 + diff_len + 5] =3D 109; - - /* test encode/decode */ - time_t t_start, t_end, t_start512, t_end512; - t_start =3D clock(); - dlen =3D xbzrle_encode_buffer(test, buffer, XBZRLE_PAGE_SIZE, compress= ed, - XBZRLE_PAGE_SIZE); - t_end =3D clock(); - float time_val =3D difftime(t_end, t_start); - rc =3D xbzrle_decode_buffer(compressed, dlen, test, XBZRLE_PAGE_SIZE); - g_assert(rc < XBZRLE_PAGE_SIZE); - g_assert(memcmp(test, buffer, XBZRLE_PAGE_SIZE) =3D=3D 0); - - t_start512 =3D clock(); - dlen512 =3D xbzrle_encode_buffer_avx512(test512, buffer512, XBZRLE_PAG= E_SIZE, - compressed512, XBZRLE_PAGE_SIZE); - t_end512 =3D clock(); - float time_val512 =3D difftime(t_end512, t_start512); - rc512 =3D xbzrle_decode_buffer(compressed512, dlen512, test512, XBZRLE= _PAGE_SIZE); - g_assert(rc512 < XBZRLE_PAGE_SIZE); - g_assert(memcmp(test512, buffer512, XBZRLE_PAGE_SIZE) =3D=3D 0); - - res->t_raw =3D time_val; - res->t_512 =3D time_val512; - - g_free(buffer); - g_free(compressed); - g_free(test); - g_free(buffer512); - g_free(compressed512); - g_free(test512); - -} - -static void test_encode_decode_avx512(void) -{ - int i; - float time_raw =3D 0.0, time_512 =3D 0.0; - struct ResTime res; - for (i =3D 0; i < 10000; i++) { - encode_decode_range_avx512(&res); - time_raw +=3D res.t_raw; - time_512 +=3D res.t_512; - } - printf("Encode decode test:\n"); - printf("Raw xbzrle_encode time is %f ms\n", time_raw); - printf("512 xbzrle_encode time is %f ms\n", time_512); -} - -static void encode_decode_random(struct ResTime *res) -{ - uint8_t *buffer =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *compressed =3D g_malloc(XBZRLE_PAGE_SIZE); - uint8_t *test =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *buffer512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - uint8_t *compressed512 =3D g_malloc(XBZRLE_PAGE_SIZE); - uint8_t *test512 =3D g_malloc0(XBZRLE_PAGE_SIZE); - int i =3D 0, rc =3D 0, rc512 =3D 0; - int dlen =3D 0, dlen512 =3D 0; - - int diff_len =3D g_test_rand_int_range(0, XBZRLE_PAGE_SIZE - 1); - /* store the index of diff */ - int dirty_index[diff_len]; - for (int j =3D 0; j < diff_len; j++) { - dirty_index[j] =3D g_test_rand_int_range(0, XBZRLE_PAGE_SIZE - 1); - } - for (i =3D diff_len - 1; i >=3D 0; i--) { - buffer[dirty_index[i]] =3D i; - test[dirty_index[i]] =3D i + 4; - buffer512[dirty_index[i]] =3D i; - test512[dirty_index[i]] =3D i + 4; - } - - time_t t_start, t_end, t_start512, t_end512; - t_start =3D clock(); - dlen =3D xbzrle_encode_buffer(test, buffer, XBZRLE_PAGE_SIZE, compress= ed, - XBZRLE_PAGE_SIZE); - t_end =3D clock(); - float time_val =3D difftime(t_end, t_start); - rc =3D xbzrle_decode_buffer(compressed, dlen, test, XBZRLE_PAGE_SIZE); - g_assert(rc < XBZRLE_PAGE_SIZE); - - t_start512 =3D clock(); - dlen512 =3D xbzrle_encode_buffer_avx512(test512, buffer512, XBZRLE_PAG= E_SIZE, - compressed512, XBZRLE_PAGE_SIZE); - t_end512 =3D clock(); - float time_val512 =3D difftime(t_end512, t_start512); - rc512 =3D xbzrle_decode_buffer(compressed512, dlen512, test512, XBZRLE= _PAGE_SIZE); - g_assert(rc512 < XBZRLE_PAGE_SIZE); - - res->t_raw =3D time_val; - res->t_512 =3D time_val512; - - g_free(buffer); - g_free(compressed); - g_free(test); - g_free(buffer512); - g_free(compressed512); - g_free(test512); - -} - -static void test_encode_decode_random_avx512(void) -{ - int i; - float time_raw =3D 0.0, time_512 =3D 0.0; - struct ResTime res; - for (i =3D 0; i < 10000; i++) { - encode_decode_random(&res); - time_raw +=3D res.t_raw; - time_512 +=3D res.t_512; - } - printf("Random test:\n"); - printf("Raw xbzrle_encode time is %f ms\n", time_raw); - printf("512 xbzrle_encode time is %f ms\n", time_512); -} -#endif - -int main(int argc, char **argv) -{ - g_test_init(&argc, &argv, NULL); - g_test_rand_int(); - #if defined(CONFIG_AVX512BW_OPT) - if (likely(is_cpu_support_avx512bw)) { - g_test_add_func("/xbzrle/encode_decode_zero", test_encode_decode_z= ero_avx512); - g_test_add_func("/xbzrle/encode_decode_unchanged", - test_encode_decode_unchanged_avx512); - g_test_add_func("/xbzrle/encode_decode_1_byte", test_encode_decode= _1_byte_avx512); - g_test_add_func("/xbzrle/encode_decode_overflow", - test_encode_decode_overflow_avx512); - g_test_add_func("/xbzrle/encode_decode", test_encode_decode_avx512= ); - g_test_add_func("/xbzrle/encode_decode_random", test_encode_decode= _random_avx512); - } - #endif - return g_test_run(); -} diff --git a/tests/unit/test-xbzrle.c b/tests/unit/test-xbzrle.c index 547046d093..b6996de69a 100644 --- a/tests/unit/test-xbzrle.c +++ b/tests/unit/test-xbzrle.c @@ -16,35 +16,6 @@ =20 #define XBZRLE_PAGE_SIZE 4096 =20 -int (*xbzrle_encode_buffer_func)(uint8_t *, uint8_t *, int, - uint8_t *, int) =3D xbzrle_encode_buffer; -#if defined(CONFIG_AVX512BW_OPT) -#include "qemu/cpuid.h" -static void __attribute__((constructor)) init_cpu_flag(void) -{ - unsigned max =3D __get_cpuid_max(0, NULL); - int a, b, c, d; - if (max >=3D 1) { - __cpuid(1, a, b, c, d); - /* We must check that AVX is not just available, but usable. */ - if ((c & bit_OSXSAVE) && (c & bit_AVX) && max >=3D 7) { - int bv; - __asm("xgetbv" : "=3Da"(bv), "=3Dd"(d) : "c"(0)); - __cpuid_count(7, 0, a, b, c, d); - /* 0xe6: - * XCR0[7:5] =3D 111b (OPMASK state, upper 256-bit of ZMM0-ZMM= 15 - * and ZMM16-ZMM31 state are enabled by OS) - * XCR0[2:1] =3D 11b (XMM state and YMM state are enabled by O= S) - */ - if ((bv & 0xe6) =3D=3D 0xe6 && (b & bit_AVX512BW)) { - xbzrle_encode_buffer_func =3D xbzrle_encode_buffer_avx512; - } - } - } - return ; -} -#endif - static void test_uleb(void) { uint32_t i, val; @@ -83,8 +54,8 @@ static void test_encode_decode_zero(void) buffer[1000 + diff_len + 5] =3D 105; =20 /* encode zero page */ - dlen =3D xbzrle_encode_buffer_func(buffer, buffer, XBZRLE_PAGE_SIZE, c= ompressed, - XBZRLE_PAGE_SIZE); + dlen =3D xbzrle_encode_buffer(buffer, buffer, XBZRLE_PAGE_SIZE, + compressed, XBZRLE_PAGE_SIZE); g_assert(dlen =3D=3D 0); =20 g_free(buffer); @@ -107,8 +78,8 @@ static void test_encode_decode_unchanged(void) test[1000 + diff_len + 5] =3D 109; =20 /* test unchanged buffer */ - dlen =3D xbzrle_encode_buffer_func(test, test, XBZRLE_PAGE_SIZE, compr= essed, - XBZRLE_PAGE_SIZE); + dlen =3D xbzrle_encode_buffer(test, test, XBZRLE_PAGE_SIZE, + compressed, XBZRLE_PAGE_SIZE); g_assert(dlen =3D=3D 0); =20 g_free(test); @@ -125,8 +96,8 @@ static void test_encode_decode_1_byte(void) =20 test[XBZRLE_PAGE_SIZE - 1] =3D 1; =20 - dlen =3D xbzrle_encode_buffer_func(buffer, test, XBZRLE_PAGE_SIZE, com= pressed, - XBZRLE_PAGE_SIZE); + dlen =3D xbzrle_encode_buffer(buffer, test, XBZRLE_PAGE_SIZE, + compressed, XBZRLE_PAGE_SIZE); g_assert(dlen =3D=3D (uleb128_encode_small(&buf[0], 4095) + 2)); =20 rc =3D xbzrle_decode_buffer(compressed, dlen, buffer, XBZRLE_PAGE_SIZE= ); @@ -150,8 +121,8 @@ static void test_encode_decode_overflow(void) } =20 /* encode overflow */ - rc =3D xbzrle_encode_buffer_func(buffer, test, XBZRLE_PAGE_SIZE, compr= essed, - XBZRLE_PAGE_SIZE); + rc =3D xbzrle_encode_buffer(buffer, test, XBZRLE_PAGE_SIZE, + compressed, XBZRLE_PAGE_SIZE); g_assert(rc =3D=3D -1); =20 g_free(buffer); @@ -181,8 +152,8 @@ static void encode_decode_range(void) test[1000 + diff_len + 5] =3D 109; =20 /* test encode/decode */ - dlen =3D xbzrle_encode_buffer_func(test, buffer, XBZRLE_PAGE_SIZE, com= pressed, - XBZRLE_PAGE_SIZE); + dlen =3D xbzrle_encode_buffer(test, buffer, XBZRLE_PAGE_SIZE, + compressed, XBZRLE_PAGE_SIZE); =20 rc =3D xbzrle_decode_buffer(compressed, dlen, test, XBZRLE_PAGE_SIZE); g_assert(rc < XBZRLE_PAGE_SIZE); diff --git a/tests/bench/meson.build b/tests/bench/meson.build index 4e6b469066..3c799dbd98 100644 --- a/tests/bench/meson.build +++ b/tests/bench/meson.build @@ -3,12 +3,6 @@ qht_bench =3D executable('qht-bench', sources: 'qht-bench.c', dependencies: [qemuutil]) =20 -if have_system -xbzrle_bench =3D executable('xbzrle-bench', - sources: 'xbzrle-bench.c', - dependencies: [qemuutil,migration]) -endif - qtree_bench =3D executable('qtree-bench', sources: 'qtree-bench.c', dependencies: [qemuutil]) --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684886557; cv=none; d=zohomail.com; s=zohoarc; b=fPuJR1mHcCH97OaYThdrzX40VwWHzBsFJnT76uOI/k31AUREqhiarweHXGHVp60lDIgY1ui1z2ztCTm6ztrmoUkQaZYC0gNn2H46xLi+olm+G942xJQqBHAdVR536Zpx1+fUyWeP+pTrAmm22EusH25YnYHrQ9+IrSkxm+odeyE= ARC-Message-Signature: i=1; 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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886293; x=1687478293; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5NPPUIfqUUProwPvLNu4WRjkBGZQ5T7snCtTOmOPzCQ=; b=mMe2ymQU+AX7q8YXfaVoCwnU38b3C8qCz7odieA3HTpQdpDmUeKa1pCKlgHyQ03HI0 lCmp07XIpW6sA8rCV1JYWKP1orZP8idDSsywc/cDHM49YbzuCYLWwvyyPZsthdDOIQki dld6KvkyfZajVxz7K/5+20pevdV/5B11Tl6Q2DQdhsaNXYw3eeFahGYiAGWGWCfZ9kvQ xpXbu9VKzUUWAqGU64cM2CdykWloc3t+AclVKnXZkm1I80V2xkz083ab/FdOr0ZrYE9Q LASIT3WXAmQSyIdeMJ3TjC9hHhVpVjh8MgHRhe4NQnBtwlU3nqjurgDsc6Y/2xkQvgD5 QK4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886293; x=1687478293; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5NPPUIfqUUProwPvLNu4WRjkBGZQ5T7snCtTOmOPzCQ=; b=UAOZETPbJsbkQYuruwmqJndiaJYEgg6E4VIKUsrUqw0cJ9mCf0WPzNuqgLqTp4TnRf 2xnbOMEerYBT2KYYmLB+UkGoLg5jiFWy7EwJz5wVuTXSr3G5abje1Wqd0eK9evks+aGu urFg1GKbfYK8wrFyO37eF+DS+SOknOpDIsHzEGH5XQeMwhLKqgEewYqIon0R9iirsMvA whi+ApPu0D389VwfYBZLhwcp9MDJ8IYmELSzuaoJEcjaEv+j7TJVB5h86qHXReT16Q8s 6tT1/TBUoORGfto/H+vuwTyX3BR194e+B+lOjaVvkmdpntzvxuYti86XFiS2s10T5mzw ncgw== X-Gm-Message-State: AC+VfDzx2k3tWO1rZzGAyGpPrA2OQyiR153U7c6reypkdqZ3NU+gzyWz 8qixr5puOpBC0NxNIg3cLHYmDQLyDQj4+z0Encw= X-Google-Smtp-Source: ACHHUZ7lxihtFkR6tNUjUslTE5MFlDedr0U2hluhkAjWv/2RlVIsid6VsjGwgdJN2SHGlOqq5Gxtvg== X-Received: by 2002:a05:6a00:9a3:b0:64d:2da5:4d2d with SMTP id u35-20020a056a0009a300b0064d2da54d2dmr892279pfg.25.1684886292983; Tue, 23 May 2023 16:58:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Juan Quintela Subject: [PULL 08/28] migration: Build migration_files once Date: Tue, 23 May 2023 16:57:44 -0700 Message-Id: <20230523235804.747803-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886559308100011 The items in migration_files are built for libmigration and included info softmmu_ss from there; no need to also include them directly. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Juan Quintela Signed-off-by: Richard Henderson --- migration/meson.build | 1 - 1 file changed, 1 deletion(-) diff --git a/migration/meson.build b/migration/meson.build index a8e01e70ae..8ba6e420fe 100644 --- a/migration/meson.build +++ b/migration/meson.build @@ -8,7 +8,6 @@ migration_files =3D files( 'qemu-file.c', 'yank_functions.c', ) -softmmu_ss.add(migration_files) =20 softmmu_ss.add(files( 'block-dirty-bitmap.c', --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684886522; cv=none; d=zohomail.com; s=zohoarc; b=XM2NyBeBa3nC4+PD30LgUHRxyE5rxql2ZdiYsdKShWybzxXWjkNzSneERyZT6jzjMowVkYREhd1UMh7pptzOkwu5LWuZIUmxzoKhiwjBrO1XlLer/TDtNA1kgy9eAQOmY00Nd50VceQCOTqadXiO1ENULD87G55Hcxaz98bUScY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684886522; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ppi4rk/AH+QDMHWJ5jhDequ555UfCn+9EzJcV8hnNs0=; b=LxC8bRHDrCxCO28xQlUEXI14pMEdojfYnyu7aWnVf9lN8oraDpG3oOF5ymT0E5AoGFXR+NJlPmay3lhIylZ1X7bhhxs5JrdDj76IS3qusSZvMEAZ9knH+NL6UdRnw2YtMytS5YTuvcxqVa7LaE4O0Fq4GwjPHn6xJWAhtORlf3E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684886522605415.86708887150473; Tue, 23 May 2023 17:02:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1btV-0004Bg-HX; Tue, 23 May 2023 19:58:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1btS-0004B6-IE for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:18 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1btP-0001nR-3T for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:16 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-64d3bc502ddso181320b3a.0 for ; Tue, 23 May 2023 16:58:14 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886294; x=1687478294; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ppi4rk/AH+QDMHWJ5jhDequ555UfCn+9EzJcV8hnNs0=; b=HQU0/m4xgq+oy/d4zax5F1jImKMhAj4qPgTJROBalsmYlWr5OecO+ztDYZg2xlP6px VFvZ6/amDw13BUFdtf1uqaiH6lObaYNTrUMDq4qtKUr5ODGioWXbykj0/i/qz2ywZS1H Iz9eV2ftzqZ2Ba9HgfBZKT6TWr1zfsXUIkgmzExfugikaBb6Ww5Dxt+T7oY2OaWUiiyF XW1gugxMRNk+hpW7/8+AcbGlb5BGDc29uutwYKKxu0WSkLIZJHpwWZ9A1AIAkZBUoh1y 9mMtiznqRGMjUYpcB4LJEcWT9sPYE93eVikgKhWAKENo7fMh67RpRaDSF3Myu/2Pdqqn sDwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886294; x=1687478294; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ppi4rk/AH+QDMHWJ5jhDequ555UfCn+9EzJcV8hnNs0=; b=JmC3C/yTjmt/GTv2a41xHGWf4l96ymMBIAsL1HdRhfnwtpicNMkZbCKpOoZ/+eQB+8 pQoKhKFg41gomr6mkyFXC72vyQ70Sde9uC78/VtRDV8b6ZN0ydRioBBYemr309et8GXN NL21IdTV2DHeVrtammRWNcRqFvhrAQk76uQIsf1recoCpf+tOOL9bP9zMIGUZJJh25q3 aWIjfPETgnl97gOMhz6qdchw39P4tY682UnU+VcWll4L8qckPkyUkNzMUQDvmiyXrbbf S9YNG9nRojGpMjfv523YVkKkLEB1p0EN4W5W+2D8GLAWemEV3x2JNJ639u4XJ0hkrfzG EvtQ== X-Gm-Message-State: AC+VfDzMcFX5f7iFmplC0CpA0Ju5wgKTtp1ZzM4E7aAe4EMiarn/Agwv Si0K2IONPhn0h5bpv3OoCtTrlZu4DScsof8KfOc= X-Google-Smtp-Source: ACHHUZ4BHHwto49se/MCEKpKjyTU5vSjNGQhmShQQ5TPUGHYK7Gs3y9OGrt2RFVMXsE1nj2qtm0YuA== X-Received: by 2002:a05:6a00:2d95:b0:646:74ce:a36c with SMTP id fb21-20020a056a002d9500b0064674cea36cmr850447pfb.8.1684886293833; Tue, 23 May 2023 16:58:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell Subject: [PULL 09/28] util: Add cpuinfo-aarch64.c Date: Tue, 23 May 2023 16:57:45 -0700 Message-Id: <20230523235804.747803-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886523150100001 Move the code from tcg/. The only use of these bits so far is with respect to the atomicity of tcg operations. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- host/include/aarch64/host/cpuinfo.h | 22 ++++++++++ tcg/aarch64/tcg-target.h | 6 ++- util/cpuinfo-aarch64.c | 67 +++++++++++++++++++++++++++++ tcg/aarch64/tcg-target.c.inc | 40 ----------------- util/meson.build | 4 +- 5 files changed, 96 insertions(+), 43 deletions(-) create mode 100644 host/include/aarch64/host/cpuinfo.h create mode 100644 util/cpuinfo-aarch64.c diff --git a/host/include/aarch64/host/cpuinfo.h b/host/include/aarch64/hos= t/cpuinfo.h new file mode 100644 index 0000000000..82227890b4 --- /dev/null +++ b/host/include/aarch64/host/cpuinfo.h @@ -0,0 +1,22 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * Host specific cpu indentification for AArch64. + */ + +#ifndef HOST_CPUINFO_H +#define HOST_CPUINFO_H + +#define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */ +#define CPUINFO_LSE (1u << 1) +#define CPUINFO_LSE2 (1u << 2) + +/* Initialized with a constructor. */ +extern unsigned cpuinfo; + +/* + * We cannot rely on constructor ordering, so other constructors must + * use the function interface rather than the variable above. + */ +unsigned cpuinfo_init(void); + +#endif /* HOST_CPUINFO_H */ diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 74ee2ed255..d5f7614880 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -13,6 +13,8 @@ #ifndef AARCH64_TCG_TARGET_H #define AARCH64_TCG_TARGET_H =20 +#include "host/cpuinfo.h" + #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 24 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) @@ -57,8 +59,8 @@ typedef enum { #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 -extern bool have_lse; -extern bool have_lse2; +#define have_lse (cpuinfo & CPUINFO_LSE) +#define have_lse2 (cpuinfo & CPUINFO_LSE2) =20 /* optional instructions */ #define TCG_TARGET_HAS_div_i32 1 diff --git a/util/cpuinfo-aarch64.c b/util/cpuinfo-aarch64.c new file mode 100644 index 0000000000..f99acb7884 --- /dev/null +++ b/util/cpuinfo-aarch64.c @@ -0,0 +1,67 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * Host specific cpu indentification for AArch64. + */ + +#include "qemu/osdep.h" +#include "host/cpuinfo.h" + +#ifdef CONFIG_LINUX +# ifdef CONFIG_GETAUXVAL +# include +# else +# include +# include "elf.h" +# endif +#endif +#ifdef CONFIG_DARWIN +# include +#endif + +unsigned cpuinfo; + +#ifdef CONFIG_DARWIN +static bool sysctl_for_bool(const char *name) +{ + int val =3D 0; + size_t len =3D sizeof(val); + + if (sysctlbyname(name, &val, &len, NULL, 0) =3D=3D 0) { + return val !=3D 0; + } + + /* + * We might in the future ask for properties not present in older kern= els, + * but we're only asking about static properties, all of which should = be + * 'int'. So we shouln't see ENOMEM (val too small), or any of the ot= her + * more exotic errors. + */ + assert(errno =3D=3D ENOENT); + return false; +} +#endif + +/* Called both as constructor and (possibly) via other constructors. */ +unsigned __attribute__((constructor)) cpuinfo_init(void) +{ + unsigned info =3D cpuinfo; + + if (info) { + return info; + } + + info =3D CPUINFO_ALWAYS; + +#ifdef CONFIG_LINUX + unsigned long hwcap =3D qemu_getauxval(AT_HWCAP); + info |=3D (hwcap & HWCAP_ATOMICS ? CPUINFO_LSE : 0); + info |=3D (hwcap & HWCAP_USCAT ? CPUINFO_LSE2 : 0); +#endif +#ifdef CONFIG_DARWIN + info |=3D sysctl_for_bool("hw.optional.arm.FEAT_LSE") * CPUINFO_LSE; + info |=3D sysctl_for_bool("hw.optional.arm.FEAT_LSE2") * CPUINFO_LSE2; +#endif + + cpuinfo =3D info; + return info; +} diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index bc6b99a1bd..84283665e7 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -13,12 +13,6 @@ #include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" #include "qemu/bitops.h" -#ifdef __linux__ -#include -#endif -#ifdef CONFIG_DARWIN -#include -#endif =20 /* We're going to re-use TCGType in setting of the SF bit, which controls the size of the operation performed. If we know the values match, it @@ -77,9 +71,6 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind = kind, int slot) return TCG_REG_X0 + slot; } =20 -bool have_lse; -bool have_lse2; - #define TCG_REG_TMP TCG_REG_X30 #define TCG_VEC_TMP TCG_REG_V31 =20 @@ -2878,39 +2869,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) } } =20 -#ifdef CONFIG_DARWIN -static bool sysctl_for_bool(const char *name) -{ - int val =3D 0; - size_t len =3D sizeof(val); - - if (sysctlbyname(name, &val, &len, NULL, 0) =3D=3D 0) { - return val !=3D 0; - } - - /* - * We might in the future ask for properties not present in older kern= els, - * but we're only asking about static properties, all of which should = be - * 'int'. So we shouln't see ENOMEM (val too small), or any of the ot= her - * more exotic errors. - */ - assert(errno =3D=3D ENOENT); - return false; -} -#endif - static void tcg_target_init(TCGContext *s) { -#ifdef __linux__ - unsigned long hwcap =3D qemu_getauxval(AT_HWCAP); - have_lse =3D hwcap & HWCAP_ATOMICS; - have_lse2 =3D hwcap & HWCAP_USCAT; -#endif -#ifdef CONFIG_DARWIN - have_lse =3D sysctl_for_bool("hw.optional.arm.FEAT_LSE"); - have_lse2 =3D sysctl_for_bool("hw.optional.arm.FEAT_LSE2"); -#endif - tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffffu; tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffffu; tcg_target_available_regs[TCG_TYPE_V64] =3D 0xffffffff00000000ull; diff --git a/util/meson.build b/util/meson.build index b3be9fad5d..3a93071d27 100644 --- a/util/meson.build +++ b/util/meson.build @@ -109,6 +109,8 @@ if have_block util_ss.add(when: 'CONFIG_LINUX', if_true: files('vfio-helpers.c')) endif =20 -if cpu in ['x86', 'x86_64'] +if cpu =3D=3D 'aarch64' + util_ss.add(files('cpuinfo-aarch64.c')) +elif cpu in ['x86', 'x86_64'] util_ss.add(files('cpuinfo-i386.c')) endif --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684886622; cv=none; d=zohomail.com; s=zohoarc; b=K8kcYcDQ1uQuLF08rF/g/MwHU0PK2T9Je99TgGTliXcnWH4RO1cSYwPC3xb75ZLJofKxbN0thFip6irfak5ml7tJVjBgwR9wEATdghJJkL7kkEJ4+b1BNHz+Do5JUdqcGuXH790vOB9YdgktbDGe90SD5ceg67m8Rs3nkhEx8lo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684886622; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yUAsUnFho/cwZWVFrY9aBytCBOU03OnLc6iH8Ijw6TM=; b=Q4Kcx7OhQjckWYuWN2EeBljaHFSxjrT6/tMkHhZ2zqlI4pSgTwmAc1pGzEsTooTLtFsU4zeyI1Cgs3dE2V7MumF5KlcvoORh6sCMhBjBmtt2pJJHIH00GeCXZKZcvGRyTXmkFHXH/yZ0kGE1k0HXaBz6WlLv+zs+5TmBayX620Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684886622686164.3757036420975; Tue, 23 May 2023 17:03:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1btU-0004BS-Ob; Tue, 23 May 2023 19:58:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1btS-0004B7-I2 for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:18 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1btP-0001ng-Tu for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:18 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-64d426e63baso168574b3a.0 for ; Tue, 23 May 2023 16:58:15 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886294; x=1687478294; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yUAsUnFho/cwZWVFrY9aBytCBOU03OnLc6iH8Ijw6TM=; b=xHGz/5sByi8KwcR8zbSrOflisl1C1z9fwcFk8/o9CPeeBaI2/tmOK73Z9V0mlU9u4p 59apUiqg3Hffr5gbH2IUE6kPrh3sxyKidTzYmDYzmkR+N6/E/VSG4wn6fKRpECkJEiJi XKMGNGUa6Dcxf8n8u9qrFunU6N8SXxU3+A0Vsi8oDrLY5JE+mDHIpXM+n97IE2DHo/TW 7Yls/LNybTWXbdBCRYcREJNaRF72YuYlqycu0nDYfDCZOaIy9o3huFg3r1s6tRcH2YOb 20zzfB0SuzNMa1I4ZyWhN7f2V4VwBvJoRHy1qDL+NQIw5udSR5iZu+Z11hkhYJQJ0YxB gBBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886294; x=1687478294; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yUAsUnFho/cwZWVFrY9aBytCBOU03OnLc6iH8Ijw6TM=; b=X2QxajybhR2MrMzYVsbO7Dh/XEXosCcpmav5pA5z6S1GZjcWdvXJURR5djdQBCJyE4 ktbD6NqkMWpipaO8MJLwHikgSf1TN1zIfmDJWssZ0UGH12QabwSW3RZaCTdkieH2nFSQ DdpOlHesjZjxQTbxyeP7vBCTrqzke3FbChvn6ay/14SlpbklPPUCcY7dpQNCN/aqVvQZ tNcLKyDiGE2RkQKwINjYWZB08ZWS8EXJ1v2VrvBbJ7yPac6ELxcx552k9YA7otMzhVCD LMwSTC01Rca/NI8ts3DRSX3bR139ZUKcEBKkhSWI5PpS+/dKYcDGI979QjbRqZqloiUl 5BIA== X-Gm-Message-State: AC+VfDz6AuxJ+GDQXv8+mUcfgHu2NyVYV90t2WyyPp5iMwSrJQWip1PO 2StdT64fTH3qgieogaa7SuJn6KbJGTMzWZxobes= X-Google-Smtp-Source: ACHHUZ7/OyLCjN/Oeq8bFzi6G0P5x8cggCHgyktGuavcjWjNTtRVwbvv4aHOFcf8oYC1h+LOCwMu3Q== X-Received: by 2002:a05:6a00:2305:b0:63b:4313:f8c4 with SMTP id h5-20020a056a00230500b0063b4313f8c4mr902490pfh.9.1684886294538; Tue, 23 May 2023 16:58:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 10/28] include/host: Split out atomic128-cas.h Date: Tue, 23 May 2023 16:57:46 -0700 Message-Id: <20230523235804.747803-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886624306100011 Separates the aarch64-specific portion into its own file. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- host/include/aarch64/host/atomic128-cas.h | 43 ++++++++++++++++++ host/include/generic/host/atomic128-cas.h | 43 ++++++++++++++++++ include/qemu/atomic128.h | 55 +---------------------- 3 files changed, 87 insertions(+), 54 deletions(-) create mode 100644 host/include/aarch64/host/atomic128-cas.h create mode 100644 host/include/generic/host/atomic128-cas.h diff --git a/host/include/aarch64/host/atomic128-cas.h b/host/include/aarch= 64/host/atomic128-cas.h new file mode 100644 index 0000000000..80de58e06d --- /dev/null +++ b/host/include/aarch64/host/atomic128-cas.h @@ -0,0 +1,43 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * Compare-and-swap for 128-bit atomic operations, AArch64 version. + * + * Copyright (C) 2018, 2023 Linaro, Ltd. + * + * See docs/devel/atomics.rst for discussion about the guarantees each + * atomic primitive is meant to provide. + */ + +#ifndef AARCH64_ATOMIC128_CAS_H +#define AARCH64_ATOMIC128_CAS_H + +/* Through gcc 10, aarch64 has no support for 128-bit atomics. */ +#if defined(CONFIG_ATOMIC128) || defined(CONFIG_CMPXCHG128) +#include "host/include/generic/host/atomic128-cas.h" +#else +static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) +{ + uint64_t cmpl =3D int128_getlo(cmp), cmph =3D int128_gethi(cmp); + uint64_t newl =3D int128_getlo(new), newh =3D int128_gethi(new); + uint64_t oldl, oldh; + uint32_t tmp; + + asm("0: ldaxp %[oldl], %[oldh], %[mem]\n\t" + "cmp %[oldl], %[cmpl]\n\t" + "ccmp %[oldh], %[cmph], #0, eq\n\t" + "b.ne 1f\n\t" + "stlxp %w[tmp], %[newl], %[newh], %[mem]\n\t" + "cbnz %w[tmp], 0b\n" + "1:" + : [mem] "+m"(*ptr), [tmp] "=3D&r"(tmp), + [oldl] "=3D&r"(oldl), [oldh] "=3D&r"(oldh) + : [cmpl] "r"(cmpl), [cmph] "r"(cmph), + [newl] "r"(newl), [newh] "r"(newh) + : "memory", "cc"); + + return int128_make128(oldl, oldh); +} +# define HAVE_CMPXCHG128 1 +#endif + +#endif /* AARCH64_ATOMIC128_CAS_H */ diff --git a/host/include/generic/host/atomic128-cas.h b/host/include/gener= ic/host/atomic128-cas.h new file mode 100644 index 0000000000..513622fe34 --- /dev/null +++ b/host/include/generic/host/atomic128-cas.h @@ -0,0 +1,43 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * Compare-and-swap for 128-bit atomic operations, generic version. + * + * Copyright (C) 2018, 2023 Linaro, Ltd. + * + * See docs/devel/atomics.rst for discussion about the guarantees each + * atomic primitive is meant to provide. + */ + +#ifndef HOST_ATOMIC128_CAS_H +#define HOST_ATOMIC128_CAS_H + +#if defined(CONFIG_ATOMIC128) +static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) +{ + Int128Alias r, c, n; + + c.s =3D cmp; + n.s =3D new; + r.i =3D qatomic_cmpxchg__nocheck((__int128_t *)ptr, c.i, n.i); + return r.s; +} +# define HAVE_CMPXCHG128 1 +#elif defined(CONFIG_CMPXCHG128) +static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) +{ + Int128Alias r, c, n; + + c.s =3D cmp; + n.s =3D new; + r.i =3D __sync_val_compare_and_swap_16((__int128_t *)ptr, c.i, n.i); + return r.s; +} +# define HAVE_CMPXCHG128 1 +#else +/* Fallback definition that must be optimized away, or error. */ +Int128 QEMU_ERROR("unsupported atomic") + atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new); +# define HAVE_CMPXCHG128 0 +#endif + +#endif /* HOST_ATOMIC128_CAS_H */ diff --git a/include/qemu/atomic128.h b/include/qemu/atomic128.h index d0ba0b9c65..10a2322c44 100644 --- a/include/qemu/atomic128.h +++ b/include/qemu/atomic128.h @@ -41,60 +41,7 @@ * Therefore, special case each platform. */ =20 -#if defined(CONFIG_ATOMIC128) -static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) -{ - Int128Alias r, c, n; - - c.s =3D cmp; - n.s =3D new; - r.i =3D qatomic_cmpxchg__nocheck((__int128_t *)ptr, c.i, n.i); - return r.s; -} -# define HAVE_CMPXCHG128 1 -#elif defined(CONFIG_CMPXCHG128) -static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) -{ - Int128Alias r, c, n; - - c.s =3D cmp; - n.s =3D new; - r.i =3D __sync_val_compare_and_swap_16((__int128_t *)ptr, c.i, n.i); - return r.s; -} -# define HAVE_CMPXCHG128 1 -#elif defined(__aarch64__) -/* Through gcc 8, aarch64 has no support for 128-bit at all. */ -static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) -{ - uint64_t cmpl =3D int128_getlo(cmp), cmph =3D int128_gethi(cmp); - uint64_t newl =3D int128_getlo(new), newh =3D int128_gethi(new); - uint64_t oldl, oldh; - uint32_t tmp; - - asm("0: ldaxp %[oldl], %[oldh], %[mem]\n\t" - "cmp %[oldl], %[cmpl]\n\t" - "ccmp %[oldh], %[cmph], #0, eq\n\t" - "b.ne 1f\n\t" - "stlxp %w[tmp], %[newl], %[newh], %[mem]\n\t" - "cbnz %w[tmp], 0b\n" - "1:" - : [mem] "+m"(*ptr), [tmp] "=3D&r"(tmp), - [oldl] "=3D&r"(oldl), [oldh] "=3D&r"(oldh) - : [cmpl] "r"(cmpl), [cmph] "r"(cmph), - [newl] "r"(newl), [newh] "r"(newh) - : "memory", "cc"); - - return int128_make128(oldl, oldh); -} -# define HAVE_CMPXCHG128 1 -#else -/* Fallback definition that must be optimized away, or error. */ -Int128 QEMU_ERROR("unsupported atomic") - atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new); -# define HAVE_CMPXCHG128 0 -#endif /* Some definition for HAVE_CMPXCHG128 */ - +#include "host/atomic128-cas.h" =20 #if defined(CONFIG_ATOMIC128) static inline Int128 atomic16_read(Int128 *ptr) --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684886392; cv=none; d=zohomail.com; s=zohoarc; b=jOzR3hwBEI8I5ZldQkopzlnhCKXbtxCxbzJRbfHfWmzEOXf/lYG66cMqAzT/lKqvmwow5mv0ZEzpcBra0HEtFpbX/i+R1k1taZvfLtlMumbCeDRs/dDobMHViAiBhxRt3PiD6QHvgmDujVwexOwYF7CV6J7VQk/705TwQh0F3fY= ARC-Message-Signature: i=1; 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Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- host/include/aarch64/host/atomic128-ldst.h | 49 ++++++++++++++ host/include/generic/host/atomic128-ldst.h | 57 +++++++++++++++++ include/qemu/atomic128.h | 74 +--------------------- 3 files changed, 107 insertions(+), 73 deletions(-) create mode 100644 host/include/aarch64/host/atomic128-ldst.h create mode 100644 host/include/generic/host/atomic128-ldst.h diff --git a/host/include/aarch64/host/atomic128-ldst.h b/host/include/aarc= h64/host/atomic128-ldst.h new file mode 100644 index 0000000000..bd61fce50d --- /dev/null +++ b/host/include/aarch64/host/atomic128-ldst.h @@ -0,0 +1,49 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * Load/store for 128-bit atomic operations, AArch64 version. + * + * Copyright (C) 2018, 2023 Linaro, Ltd. + * + * See docs/devel/atomics.rst for discussion about the guarantees each + * atomic primitive is meant to provide. + */ + +#ifndef AARCH64_ATOMIC128_LDST_H +#define AARCH64_ATOMIC128_LDST_H + +/* Through gcc 10, aarch64 has no support for 128-bit atomics. */ +#if !defined(CONFIG_ATOMIC128) && !defined(CONFIG_USER_ONLY) +/* We can do better than cmpxchg for AArch64. */ +static inline Int128 atomic16_read(Int128 *ptr) +{ + uint64_t l, h; + uint32_t tmp; + + /* The load must be paired with the store to guarantee not tearing. */ + asm("0: ldxp %[l], %[h], %[mem]\n\t" + "stxp %w[tmp], %[l], %[h], %[mem]\n\t" + "cbnz %w[tmp], 0b" + : [mem] "+m"(*ptr), [tmp] "=3Dr"(tmp), [l] "=3Dr"(l), [h] "=3Dr"(h= )); + + return int128_make128(l, h); +} + +static inline void atomic16_set(Int128 *ptr, Int128 val) +{ + uint64_t l =3D int128_getlo(val), h =3D int128_gethi(val); + uint64_t t1, t2; + + /* Load into temporaries to acquire the exclusive access lock. */ + asm("0: ldxp %[t1], %[t2], %[mem]\n\t" + "stxp %w[t1], %[l], %[h], %[mem]\n\t" + "cbnz %w[t1], 0b" + : [mem] "+m"(*ptr), [t1] "=3D&r"(t1), [t2] "=3D&r"(t2) + : [l] "r"(l), [h] "r"(h)); +} + +# define HAVE_ATOMIC128 1 +#else +#include "host/include/generic/host/atomic128-ldst.h" +#endif + +#endif /* AARCH64_ATOMIC128_LDST_H */ diff --git a/host/include/generic/host/atomic128-ldst.h b/host/include/gene= ric/host/atomic128-ldst.h new file mode 100644 index 0000000000..e7354a9255 --- /dev/null +++ b/host/include/generic/host/atomic128-ldst.h @@ -0,0 +1,57 @@ +/* + * SPDX-License-Identifier: GPL-2.0-or-later + * Load/store for 128-bit atomic operations, generic version. + * + * Copyright (C) 2018, 2023 Linaro, Ltd. + * + * See docs/devel/atomics.rst for discussion about the guarantees each + * atomic primitive is meant to provide. + */ + +#ifndef HOST_ATOMIC128_LDST_H +#define HOST_ATOMIC128_LDST_H + +#if defined(CONFIG_ATOMIC128) +static inline Int128 atomic16_read(Int128 *ptr) +{ + Int128Alias r; + + r.i =3D qatomic_read__nocheck((__int128_t *)ptr); + return r.s; +} + +static inline void atomic16_set(Int128 *ptr, Int128 val) +{ + Int128Alias v; + + v.s =3D val; + qatomic_set__nocheck((__int128_t *)ptr, v.i); +} + +# define HAVE_ATOMIC128 1 +#elif !defined(CONFIG_USER_ONLY) && HAVE_CMPXCHG128 +static inline Int128 atomic16_read(Int128 *ptr) +{ + /* Maybe replace 0 with 0, returning the old value. */ + Int128 z =3D int128_make64(0); + return atomic16_cmpxchg(ptr, z, z); +} + +static inline void atomic16_set(Int128 *ptr, Int128 val) +{ + Int128 old =3D *ptr, cmp; + do { + cmp =3D old; + old =3D atomic16_cmpxchg(ptr, cmp, val); + } while (int128_ne(old, cmp)); +} + +# define HAVE_ATOMIC128 1 +#else +/* Fallback definitions that must be optimized away, or error. */ +Int128 QEMU_ERROR("unsupported atomic") atomic16_read(Int128 *ptr); +void QEMU_ERROR("unsupported atomic") atomic16_set(Int128 *ptr, Int128 val= ); +# define HAVE_ATOMIC128 0 +#endif + +#endif /* HOST_ATOMIC128_LDST_H */ diff --git a/include/qemu/atomic128.h b/include/qemu/atomic128.h index 10a2322c44..3a8adb4d47 100644 --- a/include/qemu/atomic128.h +++ b/include/qemu/atomic128.h @@ -42,78 +42,6 @@ */ =20 #include "host/atomic128-cas.h" - -#if defined(CONFIG_ATOMIC128) -static inline Int128 atomic16_read(Int128 *ptr) -{ - Int128Alias r; - - r.i =3D qatomic_read__nocheck((__int128_t *)ptr); - return r.s; -} - -static inline void atomic16_set(Int128 *ptr, Int128 val) -{ - Int128Alias v; - - v.s =3D val; - qatomic_set__nocheck((__int128_t *)ptr, v.i); -} - -# define HAVE_ATOMIC128 1 -#elif !defined(CONFIG_USER_ONLY) && defined(__aarch64__) -/* We can do better than cmpxchg for AArch64. */ -static inline Int128 atomic16_read(Int128 *ptr) -{ - uint64_t l, h; - uint32_t tmp; - - /* The load must be paired with the store to guarantee not tearing. */ - asm("0: ldxp %[l], %[h], %[mem]\n\t" - "stxp %w[tmp], %[l], %[h], %[mem]\n\t" - "cbnz %w[tmp], 0b" - : [mem] "+m"(*ptr), [tmp] "=3Dr"(tmp), [l] "=3Dr"(l), [h] "=3Dr"(h= )); - - return int128_make128(l, h); -} - -static inline void atomic16_set(Int128 *ptr, Int128 val) -{ - uint64_t l =3D int128_getlo(val), h =3D int128_gethi(val); - uint64_t t1, t2; - - /* Load into temporaries to acquire the exclusive access lock. */ - asm("0: ldxp %[t1], %[t2], %[mem]\n\t" - "stxp %w[t1], %[l], %[h], %[mem]\n\t" - "cbnz %w[t1], 0b" - : [mem] "+m"(*ptr), [t1] "=3D&r"(t1), [t2] "=3D&r"(t2) - : [l] "r"(l), [h] "r"(h)); -} - -# define HAVE_ATOMIC128 1 -#elif !defined(CONFIG_USER_ONLY) && HAVE_CMPXCHG128 -static inline Int128 atomic16_read(Int128 *ptr) -{ - /* Maybe replace 0 with 0, returning the old value. */ - Int128 z =3D int128_make64(0); - return atomic16_cmpxchg(ptr, z, z); -} - -static inline void atomic16_set(Int128 *ptr, Int128 val) -{ - Int128 old =3D *ptr, cmp; - do { - cmp =3D old; - old =3D atomic16_cmpxchg(ptr, cmp, val); - } while (int128_ne(old, cmp)); -} - -# define HAVE_ATOMIC128 1 -#else -/* Fallback definitions that must be optimized away, or error. */ -Int128 QEMU_ERROR("unsupported atomic") atomic16_read(Int128 *ptr); -void QEMU_ERROR("unsupported atomic") atomic16_set(Int128 *ptr, Int128 val= ); -# define HAVE_ATOMIC128 0 -#endif /* Some definition for HAVE_ATOMIC128 */ +#include "host/atomic128-ldst.h" =20 #endif /* QEMU_ATOMIC128_H */ --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886296; x=1687478296; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y+VrjHOrusR8Ccf+/cO3Nyi/RyoonOjF8bnygB9K0pI=; b=czmXDrrh7tx4ODpM2K55eUXihYngN0Yvrr7nO96dMcUYopRf6gxylD0zaN5xpi1OnV vbscGG7lX41pGF/ZDnpKaj5eBPhS2cvrOfelTJTHTNvz8m4z8lcYF4hRisDv/6w8U8Y2 6x1q+9VgRtEd8JcGlY9vhsdOsVcS6yvhFC+CbjjRv2lJQaPvAiropuyNrluoahzO+xfj lSDnNTJH8/PcRJa/EvLJCbOTSr0RQs7P0yjYCDO1sIJ5fCHpQ/sGeqleXDEk8QT36zWB glFWSrds4yIt6Et202k+qLk1fmOZpu+3zJuE2jBgGlagaCpNNLmLGPuVJmLiUaUpAn4z oWrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886296; x=1687478296; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y+VrjHOrusR8Ccf+/cO3Nyi/RyoonOjF8bnygB9K0pI=; b=QXO/GuCVKOXX1oXDp6WuvqPGh08Bk9Pk3+zukS7PN7lgW1M97ycopnhLnXcoxxbd9T Mv+U0vkuTTnjI/fpWxGRV+vE6w5JozEdDJOBO6t1Z1qh2e0HSYBO1J7nx2SJPXOLOIal f6jUuQY6+1wJ3BFesx+HnYqFZJUJdKtzXm2CNsB1Tt4tBcm68L6OA7sBET/H9HmO6E0M SOldlOrADSbN5Ht5gIMxArpR9A8MGdCdUANooyZx6YO0bRDuSvx1iNcAnS0dPb2eloXw F38Vn44TcCK1rV6hOC8hnK05xp/VR82eLSUI0CNIpWBC3gB2vIPSqgcHFZbOpKYA2gNa ForQ== X-Gm-Message-State: AC+VfDzttWitd6iIRLwJlXeCEW6JubaqOUjYxJ+hM204YkEHDaJJEJpM B/YhNVz5hf0Wa2jz94YnhXGLkHBDTQvDBxm+tI4= X-Google-Smtp-Source: ACHHUZ48IrMm0O1RKgG+G50+EkFkvUPF7dJdX2L3UyoKUHB70jDICYjMAf1x2SBjWoLT/8FhRuhSew== X-Received: by 2002:a05:6a00:1303:b0:64c:c5c0:6e01 with SMTP id j3-20020a056a00130300b0064cc5c06e01mr815871pfu.31.1684886296215; Tue, 23 May 2023 16:58:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 12/28] meson: Fix detect atomic128 support with optimization Date: Tue, 23 May 2023 16:57:48 -0700 Message-Id: <20230523235804.747803-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886557346100006 Silly typo: sizeof(16) !=3D 16. Fixes: e61f1efeb730 ("meson: Detect atomic128 support with optimization") Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meson.build b/meson.build index c516b911d9..ef181ff2df 100644 --- a/meson.build +++ b/meson.build @@ -2557,7 +2557,7 @@ if has_int128 # __alignof(unsigned __int128) for the host. atomic_test_128 =3D ''' int main(int ac, char **av) { - unsigned __int128 *p =3D __builtin_assume_aligned(av[ac - 1], sizeof= (16)); + unsigned __int128 *p =3D __builtin_assume_aligned(av[ac - 1], 16); p[1] =3D __atomic_load_n(&p[0], __ATOMIC_RELAXED); __atomic_store_n(&p[2], p[3], __ATOMIC_RELAXED); __atomic_compare_exchange_n(&p[4], &p[5], p[6], 0, __ATOMIC_RELAXED,= __ATOMIC_RELAXED); --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684886379; cv=none; d=zohomail.com; s=zohoarc; b=bpamS4Rwup12TZNfQJGGsOZTrF120GzQjqc4DD+iR9HEILl7a1mk8HGiFsx2Sv1PQWEUwr9hpIvAOdEPtPmTsw06nZDI5/f/HIrPpADizU5F0bdqmTFBXs+T0CHMJv8RH2aiQI5pdONIiMig3+V3qXeOerKLGYPym2WBxD7VxwA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684886379; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aogPOmsEhm0MdLF+4QigUXcDKAmB1zj3Jt8w7MYTUqY=; b=YRlcbGphAX4CZLEQHG1kytm+dO2rSlYReZs5+d0aurlvcvL29GgJsv3aawwVJJx29lk60zANhC3+VKYF4Y1lEnh777q5WfyTQso2yqpnzVrfPiUHcbzkTJpX+dnaJsdAOo78ulddIDHs1K1OYmqFn/Yybqajl4w9hj4qOb8b9vM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684886379328879.4119609561471; Tue, 23 May 2023 16:59:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1btl-0004JG-LE; Tue, 23 May 2023 19:58:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1bth-0004H5-0b for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:33 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1btT-0001oO-Ch for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:32 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-64d3fbb8c1cso147401b3a.3 for ; Tue, 23 May 2023 16:58:17 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886297; x=1687478297; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aogPOmsEhm0MdLF+4QigUXcDKAmB1zj3Jt8w7MYTUqY=; b=RWuNM3GTtX1sB1wNqRER6I1vPvGWRwQqV4gQi5EW7cfOzFEVKL+vkm4KrLPdz4G4o5 tiKMjJ1C5emmY3X8OvpBT0rhkXun8lypULXtfU89Zm5ESVRqC2qhCOQjF0Xy6UdVTHra MFccp3Ksr62k/LRrSes+25C4THjN++PzCy72UwlVHtxhBVPpBtCltzJmMUTRJZEuZmu3 cohp66KMSsGwMAc9UUtHZHAoF0vlB5ucUiXPVdNUXx6EtpO84YYkxzxqyviYszten83B 3Fr+6bcbtlFzHUpNZXGtMstJHp59+19htR7TTDTL74D2BMdU0rfT/CHiz03ygeKcWVRu vxPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886297; x=1687478297; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aogPOmsEhm0MdLF+4QigUXcDKAmB1zj3Jt8w7MYTUqY=; b=KCqnT9z6mX59BgYeVXqFa9o5mt7WdpycIx2dqAfsT5s2vjbjWf76We+R6JS7hERWP9 HeOioflXJfwEZzbS+J7QITxEHg2O214+nbqh8E0HlU3hFg3EGWA4ShlfQQr9ud/jo0/j RlQyXgTT0DyY0wNfPFCNk42yRgNCkep7rcYrwpeIpK70rUyjOnNMoJPiYbNouTWlL5HM e9Q2plxyHiLupTHKfXBx71xIHJes2EMUDLPVsolPd1O0EYOuU5U/Nn1nDM6PbM5feyJE rDJ/Cm0v8Q8Niixifw6gaN3idFPXIgTKQJAPHVPoEzUteKagZrRy6Us7jaygINfZstvh Bglg== X-Gm-Message-State: AC+VfDx4gOPIyQoS3vQ7sniLgHnSt6Mec7/TLuhG7zsot1LC2FXajK5/ K7bW0nL1FsNi06o1PZloirtsubhvX7HgWTaAMHc= X-Google-Smtp-Source: ACHHUZ6JhkOcbF4FCZunKH+lJbWOWAXKqD8Lu1ioByGzFSTBothhA0Gj6N7fQDis0BLp9X6C6aC/gw== X-Received: by 2002:a05:6a00:218f:b0:64d:2e8a:4cc1 with SMTP id h15-20020a056a00218f00b0064d2e8a4cc1mr782458pfi.27.1684886297069; Tue, 23 May 2023 16:58:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 13/28] include/qemu: Move CONFIG_ATOMIC128_OPT handling to atomic128.h Date: Tue, 23 May 2023 16:57:49 -0700 Message-Id: <20230523235804.747803-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886380824100001 Not only the routines in ldst_atomicity.c.inc need markup, but also the ones in the headers. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- host/include/generic/host/atomic128-cas.h | 12 ++++++++---- host/include/generic/host/atomic128-ldst.h | 18 ++++++++++++------ include/qemu/atomic128.h | 17 +++++++++++++++++ accel/tcg/ldst_atomicity.c.inc | 17 ----------------- 4 files changed, 37 insertions(+), 27 deletions(-) diff --git a/host/include/generic/host/atomic128-cas.h b/host/include/gener= ic/host/atomic128-cas.h index 513622fe34..991d3da082 100644 --- a/host/include/generic/host/atomic128-cas.h +++ b/host/include/generic/host/atomic128-cas.h @@ -12,24 +12,28 @@ #define HOST_ATOMIC128_CAS_H =20 #if defined(CONFIG_ATOMIC128) -static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) +static inline Int128 ATTRIBUTE_ATOMIC128_OPT +atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) { + __int128_t *ptr_align =3D __builtin_assume_aligned(ptr, 16); Int128Alias r, c, n; =20 c.s =3D cmp; n.s =3D new; - r.i =3D qatomic_cmpxchg__nocheck((__int128_t *)ptr, c.i, n.i); + r.i =3D qatomic_cmpxchg__nocheck(ptr_align, c.i, n.i); return r.s; } # define HAVE_CMPXCHG128 1 #elif defined(CONFIG_CMPXCHG128) -static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) +static inline Int128 ATTRIBUTE_ATOMIC128_OPT +atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) { + __int128_t *ptr_align =3D __builtin_assume_aligned(ptr, 16); Int128Alias r, c, n; =20 c.s =3D cmp; n.s =3D new; - r.i =3D __sync_val_compare_and_swap_16((__int128_t *)ptr, c.i, n.i); + r.i =3D __sync_val_compare_and_swap_16(ptr_align, c.i, n.i); return r.s; } # define HAVE_CMPXCHG128 1 diff --git a/host/include/generic/host/atomic128-ldst.h b/host/include/gene= ric/host/atomic128-ldst.h index e7354a9255..46911dfb61 100644 --- a/host/include/generic/host/atomic128-ldst.h +++ b/host/include/generic/host/atomic128-ldst.h @@ -12,32 +12,38 @@ #define HOST_ATOMIC128_LDST_H =20 #if defined(CONFIG_ATOMIC128) -static inline Int128 atomic16_read(Int128 *ptr) +static inline Int128 ATTRIBUTE_ATOMIC128_OPT +atomic16_read(Int128 *ptr) { + __int128_t *ptr_align =3D __builtin_assume_aligned(ptr, 16); Int128Alias r; =20 - r.i =3D qatomic_read__nocheck((__int128_t *)ptr); + r.i =3D qatomic_read__nocheck(ptr_align); return r.s; } =20 -static inline void atomic16_set(Int128 *ptr, Int128 val) +static inline void ATTRIBUTE_ATOMIC128_OPT +atomic16_set(Int128 *ptr, Int128 val) { + __int128_t *ptr_align =3D __builtin_assume_aligned(ptr, 16); Int128Alias v; =20 v.s =3D val; - qatomic_set__nocheck((__int128_t *)ptr, v.i); + qatomic_set__nocheck(ptr_align, v.i); } =20 # define HAVE_ATOMIC128 1 #elif !defined(CONFIG_USER_ONLY) && HAVE_CMPXCHG128 -static inline Int128 atomic16_read(Int128 *ptr) +static inline Int128 ATTRIBUTE_ATOMIC128_OPT +atomic16_read(Int128 *ptr) { /* Maybe replace 0 with 0, returning the old value. */ Int128 z =3D int128_make64(0); return atomic16_cmpxchg(ptr, z, z); } =20 -static inline void atomic16_set(Int128 *ptr, Int128 val) +static inline void ATTRIBUTE_ATOMIC128_OPT +atomic16_set(Int128 *ptr, Int128 val) { Int128 old =3D *ptr, cmp; do { diff --git a/include/qemu/atomic128.h b/include/qemu/atomic128.h index 3a8adb4d47..34554bf0ac 100644 --- a/include/qemu/atomic128.h +++ b/include/qemu/atomic128.h @@ -15,6 +15,23 @@ =20 #include "qemu/int128.h" =20 +/* + * If __alignof(unsigned __int128) < 16, GCC may refuse to inline atomics + * that are supported by the host, e.g. s390x. We can force the pointer to + * have our known alignment with __builtin_assume_aligned, however prior to + * GCC 13 that was only reliable with optimization enabled. See + * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D107389 + */ +#if defined(CONFIG_ATOMIC128_OPT) +# if !defined(__OPTIMIZE__) +# define ATTRIBUTE_ATOMIC128_OPT __attribute__((optimize("O1"))) +# endif +# define CONFIG_ATOMIC128 +#endif +#ifndef ATTRIBUTE_ATOMIC128_OPT +# define ATTRIBUTE_ATOMIC128_OPT +#endif + /* * GCC is a house divided about supporting large atomic operations. * diff --git a/accel/tcg/ldst_atomicity.c.inc b/accel/tcg/ldst_atomicity.c.inc index ba5db7c366..b89631bbef 100644 --- a/accel/tcg/ldst_atomicity.c.inc +++ b/accel/tcg/ldst_atomicity.c.inc @@ -16,23 +16,6 @@ #endif #define HAVE_al8_fast (ATOMIC_REG_SIZE >=3D 8) =20 -/* - * If __alignof(unsigned __int128) < 16, GCC may refuse to inline atomics - * that are supported by the host, e.g. s390x. We can force the pointer to - * have our known alignment with __builtin_assume_aligned, however prior to - * GCC 13 that was only reliable with optimization enabled. See - * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D107389 - */ -#if defined(CONFIG_ATOMIC128_OPT) -# if !defined(__OPTIMIZE__) -# define ATTRIBUTE_ATOMIC128_OPT __attribute__((optimize("O1"))) -# endif -# define CONFIG_ATOMIC128 -#endif -#ifndef ATTRIBUTE_ATOMIC128_OPT -# define ATTRIBUTE_ATOMIC128_OPT -#endif - #if defined(CONFIG_ATOMIC128) # define HAVE_al16_fast true #else --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684886400938651.8903695487494; Tue, 23 May 2023 17:00:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1btl-0004Jb-VF; Tue, 23 May 2023 19:58:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1bth-0004H7-53 for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:33 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1btU-0001oW-Cd for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:32 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-64a9335a8e7so99315b3a.0 for ; Tue, 23 May 2023 16:58:19 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886298; x=1687478298; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qDyUFs0sCPOBnTeZd0UtyIPfkyRMGJGfSbxncKQ9k00=; b=zwm5gfOgRLXGIanGIPtENvhuq6GsicA6raVjz1fDehlaWoCl3IbS2wdwnF0btXOzCb pZCBwcF+0WDPjnV0/dKMFPe+YrZkOJZTV8WttlG975IEYDqGAs9rObvWIQv6is4/vTyI uhyhtgX/kbfqWBmED17TkZk/tIdnGCJEFoYPY5Aqxt03Ka5ErtTrsHbsorH2LedDfo4T vA410wojyZbUyQishAyAIfLodwl8ze51lWFq6dVmLzMPX5XgBS51e5ojYPmhM6lKkVu3 X5YfA7rogudTN82JxaEFwyxSS2WzH/TA6fNOifEkqLHqxy8TitoMt5aCeMx9dH2Om+O3 F7cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886298; x=1687478298; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qDyUFs0sCPOBnTeZd0UtyIPfkyRMGJGfSbxncKQ9k00=; b=BGOkA01atvUEaa6KZZGl3sRhUnt3TQ1GcZg4tU/l86lPti+/PbqRRoQs94kqRMtahx 8O6v6ZkYCUS5/TK98rtc7hWbgu299YrBBAtwMhS53lnmXLXV0tFnvbDJojO8Jjy+Z+fq lQ+Hf3Ky3SwbLEW91501dcOORwoS+8Yw3QWxEBoOzx7rZBs//oMTKW4RT9YShtjInxg6 uR1XES0/aQlCQUFy/ns7uq5Un+2DWwVcPu/HNiLu8V1xljlTpGbztOGDla0e3m8YSow8 wUyEQ75FBgB13E5sllUlR9Cjg8kszUj7Pxs6c8nrmQZE2gwcfJBJvgh4baa7dpSHdkyj HxfA== X-Gm-Message-State: AC+VfDzx9QASl/Qmjl5q4HMTBIAi4dr8S7k88SimwgaH+Ao6MD4Bixhx vf1jtPUSjLjSwKk4HAfqd0lPCPmKZnj+q5A1QeU= X-Google-Smtp-Source: ACHHUZ728fTqW99pivFhjBxujafGa8W7N6HS9qicWQ2wa3z0CCg9QDqxYKN1wF9k+jpCVv/Efn7SDw== X-Received: by 2002:a05:6a20:7f91:b0:ff:ca91:68ee with SMTP id d17-20020a056a207f9100b000ffca9168eemr16795724pzj.9.1684886297841; Tue, 23 May 2023 16:58:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 14/28] target/ppc: Use tcg_gen_qemu_{ld, st}_i128 for LQARX, LQ, STQ Date: Tue, 23 May 2023 16:57:50 -0700 Message-Id: <20230523235804.747803-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1684886402739100002 No need to roll our own, as this is now provided by tcg. This was the last use of retxl, so remove that too. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 1 - target/ppc/helper.h | 9 ---- target/ppc/mem_helper.c | 48 -------------------- target/ppc/translate.c | 34 ++------------- target/ppc/translate/fixedpoint-impl.c.inc | 51 +++------------------- 5 files changed, 11 insertions(+), 132 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 1c02596d9f..0f9f2e1a0c 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1124,7 +1124,6 @@ struct CPUArchState { /* used to speed-up TLB assist handlers */ =20 target_ulong nip; /* next instruction pointer */ - uint64_t retxh; /* high part of 128-bit helper return */ =20 /* when a memory exception occurs, the access type is stored here */ int access_type; diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 0beaca5c7a..38efbc351c 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -810,12 +810,3 @@ DEF_HELPER_4(DSCLIQ, void, env, fprp, fprp, i32) =20 DEF_HELPER_1(tbegin, void, env) DEF_HELPER_FLAGS_1(fixup_thrm, TCG_CALL_NO_RWG, void, env) - -#ifdef TARGET_PPC64 -DEF_HELPER_FLAGS_3(lq_le_parallel, TCG_CALL_NO_WG, i64, env, tl, i32) -DEF_HELPER_FLAGS_3(lq_be_parallel, TCG_CALL_NO_WG, i64, env, tl, i32) -DEF_HELPER_FLAGS_5(stq_le_parallel, TCG_CALL_NO_WG, - void, env, tl, i64, i64, i32) -DEF_HELPER_FLAGS_5(stq_be_parallel, TCG_CALL_NO_WG, - void, env, tl, i64, i64, i32) -#endif diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 1578887a8f..46eae65819 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -367,54 +367,6 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ulo= ng addr, uint32_t reg, return i; } =20 -#ifdef TARGET_PPC64 -uint64_t helper_lq_le_parallel(CPUPPCState *env, target_ulong addr, - uint32_t opidx) -{ - Int128 ret; - - /* We will have raised EXCP_ATOMIC from the translator. */ - assert(HAVE_ATOMIC128); - ret =3D cpu_atomic_ldo_le_mmu(env, addr, opidx, GETPC()); - env->retxh =3D int128_gethi(ret); - return int128_getlo(ret); -} - -uint64_t helper_lq_be_parallel(CPUPPCState *env, target_ulong addr, - uint32_t opidx) -{ - Int128 ret; - - /* We will have raised EXCP_ATOMIC from the translator. */ - assert(HAVE_ATOMIC128); - ret =3D cpu_atomic_ldo_be_mmu(env, addr, opidx, GETPC()); - env->retxh =3D int128_gethi(ret); - return int128_getlo(ret); -} - -void helper_stq_le_parallel(CPUPPCState *env, target_ulong addr, - uint64_t lo, uint64_t hi, uint32_t opidx) -{ - Int128 val; - - /* We will have raised EXCP_ATOMIC from the translator. */ - assert(HAVE_ATOMIC128); - val =3D int128_make128(lo, hi); - cpu_atomic_sto_le_mmu(env, addr, val, opidx, GETPC()); -} - -void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr, - uint64_t lo, uint64_t hi, uint32_t opidx) -{ - Int128 val; - - /* We will have raised EXCP_ATOMIC from the translator. */ - assert(HAVE_ATOMIC128); - val =3D int128_make128(lo, hi); - cpu_atomic_sto_be_mmu(env, addr, val, opidx, GETPC()); -} -#endif - /*************************************************************************= ****/ /* Altivec extension helpers */ #if HOST_BIG_ENDIAN diff --git a/target/ppc/translate.c b/target/ppc/translate.c index f603f1a939..1720570b9b 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -3757,6 +3757,7 @@ static void gen_lqarx(DisasContext *ctx) { int rd =3D rD(ctx->opcode); TCGv EA, hi, lo; + TCGv_i128 t16; =20 if (unlikely((rd & 1) || (rd =3D=3D rA(ctx->opcode)) || (rd =3D=3D rB(ctx->opcode)))) { @@ -3772,36 +3773,9 @@ static void gen_lqarx(DisasContext *ctx) lo =3D cpu_gpr[rd + 1]; hi =3D cpu_gpr[rd]; =20 - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - if (HAVE_ATOMIC128) { - TCGv_i32 oi =3D tcg_temp_new_i32(); - if (ctx->le_mode) { - tcg_gen_movi_i32(oi, make_memop_idx(MO_LE | MO_128 | MO_AL= IGN, - ctx->mem_idx)); - gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); - } else { - tcg_gen_movi_i32(oi, make_memop_idx(MO_BE | MO_128 | MO_AL= IGN, - ctx->mem_idx)); - gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); - } - tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); - } else { - /* Restart with exclusive lock. */ - gen_helper_exit_atomic(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; - return; - } - } else if (ctx->le_mode) { - tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEUQ | MO_ALIGN_16); - tcg_gen_mov_tl(cpu_reserve, EA); - gen_addr_add(ctx, EA, EA, 8); - tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEUQ); - } else { - tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEUQ | MO_ALIGN_16); - tcg_gen_mov_tl(cpu_reserve, EA); - gen_addr_add(ctx, EA, EA, 8); - tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEUQ); - } + t16 =3D tcg_temp_new_i128(); + tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIG= N)); + tcg_gen_extr_i128_i64(lo, hi, t16); =20 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 02d86b77a8..f47f1a50e8 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -72,7 +72,7 @@ static bool do_ldst_quad(DisasContext *ctx, arg_D *a, boo= l store, bool prefixed) #if defined(TARGET_PPC64) TCGv ea; TCGv_i64 low_addr_gpr, high_addr_gpr; - MemOp mop; + TCGv_i128 t16; =20 REQUIRE_INSNS_FLAGS(ctx, 64BX); =20 @@ -101,51 +101,14 @@ static bool do_ldst_quad(DisasContext *ctx, arg_D *a,= bool store, bool prefixed) low_addr_gpr =3D cpu_gpr[a->rt + 1]; high_addr_gpr =3D cpu_gpr[a->rt]; } + t16 =3D tcg_temp_new_i128(); =20 - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - if (HAVE_ATOMIC128) { - mop =3D DEF_MEMOP(MO_128); - TCGv_i32 oi =3D tcg_constant_i32(make_memop_idx(mop, ctx->mem_= idx)); - if (store) { - if (ctx->le_mode) { - gen_helper_stq_le_parallel(cpu_env, ea, low_addr_gpr, - high_addr_gpr, oi); - } else { - gen_helper_stq_be_parallel(cpu_env, ea, high_addr_gpr, - low_addr_gpr, oi); - - } - } else { - if (ctx->le_mode) { - gen_helper_lq_le_parallel(low_addr_gpr, cpu_env, ea, o= i); - tcg_gen_ld_i64(high_addr_gpr, cpu_env, - offsetof(CPUPPCState, retxh)); - } else { - gen_helper_lq_be_parallel(high_addr_gpr, cpu_env, ea, = oi); - tcg_gen_ld_i64(low_addr_gpr, cpu_env, - offsetof(CPUPPCState, retxh)); - } - } - } else { - /* Restart with exclusive lock. */ - gen_helper_exit_atomic(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; - } + if (store) { + tcg_gen_concat_i64_i128(t16, low_addr_gpr, high_addr_gpr); + tcg_gen_qemu_st_i128(t16, ea, ctx->mem_idx, DEF_MEMOP(MO_128)); } else { - mop =3D DEF_MEMOP(MO_UQ); - if (store) { - tcg_gen_qemu_st_i64(low_addr_gpr, ea, ctx->mem_idx, mop); - } else { - tcg_gen_qemu_ld_i64(low_addr_gpr, ea, ctx->mem_idx, mop); - } - - gen_addr_add(ctx, ea, ea, 8); - - if (store) { - tcg_gen_qemu_st_i64(high_addr_gpr, ea, ctx->mem_idx, mop); - } else { - tcg_gen_qemu_ld_i64(high_addr_gpr, ea, ctx->mem_idx, mop); - } + tcg_gen_qemu_ld_i128(t16, ea, ctx->mem_idx, DEF_MEMOP(MO_128)); + tcg_gen_extr_i128_i64(low_addr_gpr, high_addr_gpr, t16); } #else qemu_build_not_reached(); --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684886368552271.7227291878347; Tue, 23 May 2023 16:59:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1bu5-0004Nk-Vc; Tue, 23 May 2023 19:58:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1bth-0004H6-1g for qemu-devel@nongnu.org; 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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886298; x=1687478298; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jLExgig/sSvVFxDtwQ48pSfnJZWfkAOeqOv3WT/bVOU=; b=TEkpFkDkkS7h/xnsz+yHgeAlguY9+7RqVtgGql73cI224Y4rk8q1Q8J5PgEm0nkFAj nENN/UjUsjm9Vfc09uUTqLV0S07E1cV2b3LfBCjW8FUO/PuxV+AzCXzMoJj2xrnxNQh5 sECn9W4NotWGu4Y1KfWj80j5hCEvFLMWlvFZbLTRfq7vJnr86hBbuVteiZU2NLpxhliW BiWMI1n73lFPmq9oaX3CLUuLYZSdf0c5BQSOrXWSpH04ftS3EGxUS/xBSefzLA7Q56Wj qF+ndR3OnPVvfI9dEGRVkD4xrmm+mZEz9oz9gXtYN9CnkVCP7ozetylyMdvPINRZVOo9 csBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886298; x=1687478298; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jLExgig/sSvVFxDtwQ48pSfnJZWfkAOeqOv3WT/bVOU=; b=CTLiFbY/mWYEhc8GXII6eN/qN0HTEWR6Q92Ub81ihnrvsPOu+oDHWOg4IH2t4I9h0W jucqaT6ROxthOj02r+uncUG+6NA5uYMw5GQCT8PruND3WQ5luDowcUh5Qa9lC/0q3Rus cQLMPgRZuvOluQtGG1CqNXKikhrD7oVI34kObzRQ9llXDZ1cmsAZnmu9mn9Rp+QInrto ZZ08tGaP0KxkL+pwyOCVlj4NG+1buq7CcViO6KhWZpkf/jmmlnfYcZ6lvrhtOQPO+HJ/ A/35uYL8JM0P78sYsBmWofYnfDak4vlgrvfcG2B0in/o/Ye6RdjXPwrR92ecv2L5gq42 bTAQ== X-Gm-Message-State: AC+VfDwRAzwZErmf3gpEG+yqdRLbAOvPnytW01p0BYXy2kFC+2G58xwr Bj/xEpwFC1tqbmVwOfPo6ADg6WlcjFPbcWEiAvU= X-Google-Smtp-Source: ACHHUZ6fgE7Ra4zcxErjGVSyUiEeAEnhx5blR0ATS7i1cL9fVlLivmvwBOK7wAWRr3+XKsXVbTq5Cw== X-Received: by 2002:a05:6a00:a1a:b0:64a:f8c9:a421 with SMTP id p26-20020a056a000a1a00b0064af8c9a421mr1021711pfh.32.1684886298549; Tue, 23 May 2023 16:58:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Hildenbrand Subject: [PULL 15/28] target/s390x: Use tcg_gen_qemu_{ld, st}_i128 for LPQ, STPQ Date: Tue, 23 May 2023 16:57:51 -0700 Message-Id: <20230523235804.747803-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1684886370473100007 No need to roll our own, as this is now provided by tcg. This was the last use of retxl, so remove that too. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/cpu.h | 3 -- target/s390x/helper.h | 4 --- target/s390x/tcg/mem_helper.c | 61 -------------------------------- target/s390x/tcg/translate.c | 30 +++++----------- target/s390x/tcg/insn-data.h.inc | 2 +- 5 files changed, 9 insertions(+), 91 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index c47e7adcb1..f130c29f83 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -76,9 +76,6 @@ struct CPUArchState { =20 float_status fpu_status; /* passed to softfloat lib */ =20 - /* The low part of a 128-bit return, or remainder of a divide. */ - uint64_t retxl; - PSW psw; =20 S390CrashReason crash_reason; diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 341bc51ec2..7529e725f2 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -108,10 +108,6 @@ DEF_HELPER_FLAGS_2(sfas, TCG_CALL_NO_WG, void, env, i6= 4) DEF_HELPER_FLAGS_2(srnm, TCG_CALL_NO_WG, void, env, i64) DEF_HELPER_FLAGS_1(popcnt, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_2(stfle, i32, env, i64) -DEF_HELPER_FLAGS_2(lpq, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_2(lpq_parallel, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_4(stpq, TCG_CALL_NO_WG, void, env, i64, i64, i64) -DEF_HELPER_FLAGS_4(stpq_parallel, TCG_CALL_NO_WG, void, env, i64, i64, i64) DEF_HELPER_4(mvcos, i32, env, i64, i64, i64) DEF_HELPER_4(cu12, i32, env, i32, i32, i32) DEF_HELPER_4(cu14, i32, env, i32, i32, i32) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 8b58b8d88d..0e0d66b3b6 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -2398,67 +2398,6 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t ad= dr) } #endif =20 -/* load pair from quadword */ -uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t addr) -{ - uintptr_t ra =3D GETPC(); - uint64_t hi, lo; - - check_alignment(env, addr, 16, ra); - hi =3D cpu_ldq_data_ra(env, addr + 0, ra); - lo =3D cpu_ldq_data_ra(env, addr + 8, ra); - - env->retxl =3D lo; - return hi; -} - -uint64_t HELPER(lpq_parallel)(CPUS390XState *env, uint64_t addr) -{ - uintptr_t ra =3D GETPC(); - uint64_t hi, lo; - int mem_idx; - MemOpIdx oi; - Int128 v; - - assert(HAVE_ATOMIC128); - - mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_TEUQ | MO_ALIGN_16, mem_idx); - v =3D cpu_atomic_ldo_be_mmu(env, addr, oi, ra); - hi =3D int128_gethi(v); - lo =3D int128_getlo(v); - - env->retxl =3D lo; - return hi; -} - -/* store pair to quadword */ -void HELPER(stpq)(CPUS390XState *env, uint64_t addr, - uint64_t low, uint64_t high) -{ - uintptr_t ra =3D GETPC(); - - check_alignment(env, addr, 16, ra); - cpu_stq_data_ra(env, addr + 0, high, ra); - cpu_stq_data_ra(env, addr + 8, low, ra); -} - -void HELPER(stpq_parallel)(CPUS390XState *env, uint64_t addr, - uint64_t low, uint64_t high) -{ - uintptr_t ra =3D GETPC(); - int mem_idx; - MemOpIdx oi; - Int128 v; - - assert(HAVE_ATOMIC128); - - mem_idx =3D cpu_mmu_index(env, false); - oi =3D make_memop_idx(MO_TEUQ | MO_ALIGN_16, mem_idx); - v =3D int128_make128(low, high); - cpu_atomic_sto_be_mmu(env, addr, v, oi, ra); -} - /* Execute instruction. This instruction executes an insn modified with the contents of r1. It does not change the executed instruction in mem= ory; it does not change the program counter. diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index d6670e6a87..3eb3708d55 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -335,11 +335,6 @@ static void store_freg32_i64(int reg, TCGv_i64 v) tcg_gen_st32_i64(v, cpu_env, freg32_offset(reg)); } =20 -static void return_low128(TCGv_i64 dest) -{ - tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl)); -} - static void update_psw_addr(DisasContext *s) { /* psw.addr */ @@ -3130,15 +3125,9 @@ static DisasJumpType op_lpd(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_lpq(DisasContext *s, DisasOps *o) { - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_lpq(o->out, cpu_env, o->in2); - } else if (HAVE_ATOMIC128) { - gen_helper_lpq_parallel(o->out, cpu_env, o->in2); - } else { - gen_helper_exit_atomic(cpu_env); - return DISAS_NORETURN; - } - return_low128(o->out2); + o->out_128 =3D tcg_temp_new_i128(); + tcg_gen_qemu_ld_i128(o->out_128, o->in2, get_mem_index(s), + MO_TE | MO_128 | MO_ALIGN); return DISAS_NEXT; } =20 @@ -4533,14 +4522,11 @@ static DisasJumpType op_stmh(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_stpq(DisasContext *s, DisasOps *o) { - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_stpq(cpu_env, o->in2, o->out2, o->out); - } else if (HAVE_ATOMIC128) { - gen_helper_stpq_parallel(cpu_env, o->in2, o->out2, o->out); - } else { - gen_helper_exit_atomic(cpu_env); - return DISAS_NORETURN; - } + TCGv_i128 t16 =3D tcg_temp_new_i128(); + + tcg_gen_concat_i64_i128(t16, o->out2, o->out); + tcg_gen_qemu_st_i128(t16, o->in2, get_mem_index(s), + MO_TE | MO_128 | MO_ALIGN); return DISAS_NEXT; } =20 diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.= h.inc index 1f1ac742a9..bcc70d99ba 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -570,7 +570,7 @@ D(0xc804, LPD, SSF, ILA, 0, 0, new_P, r3_P32, lpd, 0, MO_TEUL) D(0xc805, LPDG, SSF, ILA, 0, 0, new_P, r3_P64, lpd, 0, MO_TEUQ) /* LOAD PAIR FROM QUADWORD */ - C(0xe38f, LPQ, RXY_a, Z, 0, a2, r1_P, 0, lpq, 0) + C(0xe38f, LPQ, RXY_a, Z, 0, a2, 0, r1_D64, lpq, 0) /* LOAD POSITIVE */ C(0x1000, LPR, RR_a, Z, 0, r2_32s, new, r1_32, abs, abs32) C(0xb900, LPGR, RRE, Z, 0, r2, r1, 0, abs, abs64) --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684886859; cv=none; d=zohomail.com; s=zohoarc; b=kxj8sIsFQQiginBa5nId3ZcCdHanKjol9+BgScpJPxbByiJI3za1Ra7N7nKbJECWAB12bQCyfRBFmmjZuaFSOV51ZlI/VWwE6JapQGEnucBYuwTYyw+qNFY82k50VuJoNfFIZVcpBmjPJLRXzx/xZcYvGZMI7pdKH3lR2yraWuY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684886859; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GVDyu1oYCGf+OD0d59Mxeocg+USbpsSUkgPTmIhL5kQ=; b=jG0QVChn1SkZ0bu39NNe8pthW4qBBW3nuAnFBKeT/nzszgzFG2NVmnWnOmWdNN5A4zDMX0ojb0Yy+b3SVWGsBDVbqyrExamUX3kK4iEVUCz5OpvTTFNbiv8LnySY7zXExWqZKjRNkgClA9kh6QckdHuaqplqrzw4VL3iTafBz0s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684886859268751.9166595494838; Tue, 23 May 2023 17:07:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1btn-0004Kv-NL; Tue, 23 May 2023 19:58:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1btk-0004Hz-Tt for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:36 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1btU-0001p2-Sc for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:35 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-64d247a023aso102390b3a.2 for ; Tue, 23 May 2023 16:58:20 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886299; x=1687478299; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GVDyu1oYCGf+OD0d59Mxeocg+USbpsSUkgPTmIhL5kQ=; b=dBXtp3xh/XhB0Uodr+R/RpjvReog32U0tWS7SI3zJEDSIFGGAOZEW21Sv0X2Ijd3Zx 3VwoIG3cGaro1dv8hBdUV1ldjS3Ph2iCiYf4xCfRuzaY14++MgEqxyeQGUmxeOEnlncR NBXULwh6LYamEbXsw4uT6BsEqvw5QmlJKwOIXUMNxRwbfZ+Op0B1XHL7ND3LW8IMQj/X EZRUrgNs8BGv6rUMyADie1aSt365sCH9C1zFM8uBT/YXG3uJpw7YxvN1JTUls0CsyFPP IjLbgpLJzEVYN1gL3GorH6C9kab8Zq1oqF26HxFpueXT4CL0sb7OLue+08pIvOIG2Le2 oQJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886299; x=1687478299; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GVDyu1oYCGf+OD0d59Mxeocg+USbpsSUkgPTmIhL5kQ=; b=TOyKho+j8iirR+4LlGXhYSrTYG+yp8o5cuLssFIHGtqRFr/1VgJB9gRpgTGPy+Xitx wCzymjwdX6AXC+yABYYH2A7iZBTOjiauuTq+EIDDcAjAYWX1Xi89UWxNlphTQL5BFyvO eHtF/XXNoVyTN+331r//1lcB280eOooXH/s8qGyawrjt3FRhYF6VQlVHppDi+oaymjH4 4Hppc3MrWU/HnYtC1WjwfaJTqWrl4hdzlnA9AKiZg/i0kV6lR5jOfHkPcopg7HguWLbW dD5Wla/FhAarUSK2AFX7dp/dLncH3A4twJHMLAjM5K1U2M57meNYOP+COzTPmBgdU4SG Gn1w== X-Gm-Message-State: AC+VfDyqDQPCh6obXN45aLQwPOpCItwrI4ij6WwnmFMZancStj8rkE9O 7S2dCPAo41u18Fyr4e4o4eoiYInrF3YLXKlUie0= X-Google-Smtp-Source: ACHHUZ4xHWS5GqBqTbFSaT+JjByrqdvUvSTMT/MZz3M2ZI2oBEB/Mvx7OglSxzjzKaQR0Sh0Odtz5w== X-Received: by 2002:a05:6a00:985:b0:647:370c:2c2a with SMTP id u5-20020a056a00098500b00647370c2c2amr1034079pfg.6.1684886299405; Tue, 23 May 2023 16:58:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 16/28] accel/tcg: Unify cpu_{ld,st}*_{be,le}_mmu Date: Tue, 23 May 2023 16:57:52 -0700 Message-Id: <20230523235804.747803-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886861099100014 With the current structure of cputlb.c, there is no difference between the little-endian and big-endian entry points, aside from the assert. Unify the pairs of functions. The only use of the functions with explicit endianness was in target/sparc64, and that was only to satisfy the assert: the correct endianness is already built into memop. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 58 ++----- accel/tcg/cputlb.c | 122 +++----------- accel/tcg/user-exec.c | 322 ++++++++++-------------------------- target/arm/tcg/m_helper.c | 4 +- target/sparc/ldst_helper.c | 18 +- accel/tcg/ldst_common.c.inc | 24 +-- 6 files changed, 137 insertions(+), 411 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 7c867c94c3..fc1d3d9301 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -207,43 +207,21 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr = ptr, uint64_t val, int mmu_idx, uintptr_t ra); =20 uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_t= ra); -uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr ptr, - MemOpIdx oi, uintptr_t ra); -uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr ptr, - MemOpIdx oi, uintptr_t ra); -uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr ptr, - MemOpIdx oi, uintptr_t ra); -uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr ptr, - MemOpIdx oi, uintptr_t ra); -uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr ptr, - MemOpIdx oi, uintptr_t ra); -uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr ptr, - MemOpIdx oi, uintptr_t ra); - -Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra); -Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra); +uint16_t cpu_ldw_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_= t ra); +uint32_t cpu_ldl_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_= t ra); +uint64_t cpu_ldq_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_= t ra); +Int128 cpu_ld16_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_= t ra); =20 void cpu_stb_mmu(CPUArchState *env, abi_ptr ptr, uint8_t val, MemOpIdx oi, uintptr_t ra); -void cpu_stw_be_mmu(CPUArchState *env, abi_ptr ptr, uint16_t val, - MemOpIdx oi, uintptr_t ra); -void cpu_stl_be_mmu(CPUArchState *env, abi_ptr ptr, uint32_t val, - MemOpIdx oi, uintptr_t ra); -void cpu_stq_be_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val, - MemOpIdx oi, uintptr_t ra); -void cpu_stw_le_mmu(CPUArchState *env, abi_ptr ptr, uint16_t val, - MemOpIdx oi, uintptr_t ra); -void cpu_stl_le_mmu(CPUArchState *env, abi_ptr ptr, uint32_t val, - MemOpIdx oi, uintptr_t ra); -void cpu_stq_le_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val, - MemOpIdx oi, uintptr_t ra); - -void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr, Int128 val, - MemOpIdx oi, uintptr_t ra); -void cpu_st16_le_mmu(CPUArchState *env, abi_ptr addr, Int128 val, - MemOpIdx oi, uintptr_t ra); +void cpu_stw_mmu(CPUArchState *env, abi_ptr ptr, uint16_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stl_mmu(CPUArchState *env, abi_ptr ptr, uint32_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_stq_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val, + MemOpIdx oi, uintptr_t ra); +void cpu_st16_mmu(CPUArchState *env, abi_ptr addr, Int128 val, + MemOpIdx oi, uintptr_t ra); =20 uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, uint32_t cmpv, uint32_t newv, @@ -416,9 +394,6 @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env,= uintptr_t mmu_idx, # define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra # define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra # define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra -# define cpu_ldw_mmu cpu_ldw_be_mmu -# define cpu_ldl_mmu cpu_ldl_be_mmu -# define cpu_ldq_mmu cpu_ldq_be_mmu # define cpu_stw_data cpu_stw_be_data # define cpu_stl_data cpu_stl_be_data # define cpu_stq_data cpu_stq_be_data @@ -428,9 +403,6 @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env,= uintptr_t mmu_idx, # define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra # define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra # define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra -# define cpu_stw_mmu cpu_stw_be_mmu -# define cpu_stl_mmu cpu_stl_be_mmu -# define cpu_stq_mmu cpu_stq_be_mmu #else # define cpu_lduw_data cpu_lduw_le_data # define cpu_ldsw_data cpu_ldsw_le_data @@ -444,9 +416,6 @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env,= uintptr_t mmu_idx, # define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra # define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra # define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra -# define cpu_ldw_mmu cpu_ldw_le_mmu -# define cpu_ldl_mmu cpu_ldl_le_mmu -# define cpu_ldq_mmu cpu_ldq_le_mmu # define cpu_stw_data cpu_stw_le_data # define cpu_stl_data cpu_stl_le_data # define cpu_stq_data cpu_stq_le_data @@ -456,9 +425,6 @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env,= uintptr_t mmu_idx, # define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra # define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra # define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra -# define cpu_stw_mmu cpu_stw_le_mmu -# define cpu_stl_mmu cpu_stl_le_mmu -# define cpu_stq_mmu cpu_stq_le_mmu #endif =20 uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr, diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index ae0fbcdee2..b1e13d165c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2575,89 +2575,45 @@ uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr= , MemOpIdx oi, uintptr_t ra) return ret; } =20 -uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) +uint16_t cpu_ldw_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { uint16_t ret; =20 - tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_BEUW= ); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); ret =3D do_ld2_mmu(env, addr, oi, ra, MMU_DATA_LOAD); plugin_load_cb(env, addr, oi); return ret; } =20 -uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) +uint32_t cpu_ldl_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { uint32_t ret; =20 - tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_BEUL= ); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); ret =3D do_ld4_mmu(env, addr, oi, ra, MMU_DATA_LOAD); plugin_load_cb(env, addr, oi); return ret; } =20 -uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) +uint64_t cpu_ldq_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { uint64_t ret; =20 - tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_BEUQ= ); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); ret =3D do_ld8_mmu(env, addr, oi, ra, MMU_DATA_LOAD); plugin_load_cb(env, addr, oi); return ret; } =20 -uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) -{ - uint16_t ret; - - tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_LEUW= ); - ret =3D do_ld2_mmu(env, addr, oi, ra, MMU_DATA_LOAD); - plugin_load_cb(env, addr, oi); - return ret; -} - -uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) -{ - uint32_t ret; - - tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_LEUL= ); - ret =3D do_ld4_mmu(env, addr, oi, ra, MMU_DATA_LOAD); - plugin_load_cb(env, addr, oi); - return ret; -} - -uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) -{ - uint64_t ret; - - tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_LEUQ= ); - ret =3D do_ld8_mmu(env, addr, oi, ra, MMU_DATA_LOAD); - plugin_load_cb(env, addr, oi); - return ret; -} - -Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) +Int128 cpu_ld16_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { Int128 ret; =20 - tcg_debug_assert((get_memop(oi) & (MO_BSWAP|MO_SIZE)) =3D=3D (MO_BE|MO= _128)); - ret =3D do_ld16_mmu(env, addr, oi, ra); - plugin_load_cb(env, addr, oi); - return ret; -} - -Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) -{ - Int128 ret; - - tcg_debug_assert((get_memop(oi) & (MO_BSWAP|MO_SIZE)) =3D=3D (MO_LE|MO= _128)); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); ret =3D do_ld16_mmu(env, addr, oi, ra); plugin_load_cb(env, addr, oi); return ret; @@ -3045,66 +3001,34 @@ void cpu_stb_mmu(CPUArchState *env, target_ulong ad= dr, uint8_t val, plugin_store_cb(env, addr, oi); } =20 -void cpu_stw_be_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - MemOpIdx oi, uintptr_t retaddr) +void cpu_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + MemOpIdx oi, uintptr_t retaddr) { - tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_BEUW= ); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); do_st2_mmu(env, addr, val, oi, retaddr); plugin_store_cb(env, addr, oi); } =20 -void cpu_stl_be_mmu(CPUArchState *env, target_ulong addr, uint32_t val, +void cpu_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { - tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_BEUL= ); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); do_st4_mmu(env, addr, val, oi, retaddr); plugin_store_cb(env, addr, oi); } =20 -void cpu_stq_be_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - MemOpIdx oi, uintptr_t retaddr) +void cpu_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr) { - tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_BEUQ= ); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); do_st8_mmu(env, addr, val, oi, retaddr); plugin_store_cb(env, addr, oi); } =20 -void cpu_stw_le_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - MemOpIdx oi, uintptr_t retaddr) +void cpu_st16_mmu(CPUArchState *env, target_ulong addr, Int128 val, + MemOpIdx oi, uintptr_t retaddr) { - tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_LEUW= ); - do_st2_mmu(env, addr, val, oi, retaddr); - plugin_store_cb(env, addr, oi); -} - -void cpu_stl_le_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - MemOpIdx oi, uintptr_t retaddr) -{ - tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_LEUL= ); - do_st4_mmu(env, addr, val, oi, retaddr); - plugin_store_cb(env, addr, oi); -} - -void cpu_stq_le_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - MemOpIdx oi, uintptr_t retaddr) -{ - tcg_debug_assert((get_memop(oi) & (MO_BSWAP | MO_SIZE)) =3D=3D MO_LEUQ= ); - do_st8_mmu(env, addr, val, oi, retaddr); - plugin_store_cb(env, addr, oi); -} - -void cpu_st16_be_mmu(CPUArchState *env, target_ulong addr, Int128 val, - MemOpIdx oi, uintptr_t retaddr) -{ - tcg_debug_assert((get_memop(oi) & (MO_BSWAP|MO_SIZE)) =3D=3D (MO_BE|MO= _128)); - do_st16_mmu(env, addr, val, oi, retaddr); - plugin_store_cb(env, addr, oi); -} - -void cpu_st16_le_mmu(CPUArchState *env, target_ulong addr, Int128 val, - MemOpIdx oi, uintptr_t retaddr) -{ - tcg_debug_assert((get_memop(oi) & (MO_BSWAP|MO_SIZE)) =3D=3D (MO_LE|MO= _128)); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); do_st16_mmu(env, addr, val, oi, retaddr); plugin_store_cb(env, addr, oi); } diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 36ad8284a5..19c2849c21 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -940,8 +940,8 @@ uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, return ret; } =20 -static uint16_t do_ld2_he_mmu(CPUArchState *env, abi_ptr addr, - MemOp mop, uintptr_t ra) +static uint16_t do_ld2_mmu(CPUArchState *env, abi_ptr addr, + MemOp mop, uintptr_t ra) { void *haddr; uint16_t ret; @@ -950,59 +950,35 @@ static uint16_t do_ld2_he_mmu(CPUArchState *env, abi_= ptr addr, haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD); ret =3D load_atom_2(env, ra, haddr, mop); clear_helper_retaddr(); + + if (mop & MO_BSWAP) { + ret =3D bswap16(ret); + } return ret; } =20 tcg_target_ulong helper_lduw_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { - MemOp mop =3D get_memop(oi); - uint16_t ret =3D do_ld2_he_mmu(env, addr, mop, ra); - - if (mop & MO_BSWAP) { - ret =3D bswap16(ret); - } - return ret; + return do_ld2_mmu(env, addr, get_memop(oi), ra); } =20 tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { - MemOp mop =3D get_memop(oi); - int16_t ret =3D do_ld2_he_mmu(env, addr, mop, ra); + return (int16_t)do_ld2_mmu(env, addr, get_memop(oi), ra); +} =20 - if (mop & MO_BSWAP) { - ret =3D bswap16(ret); - } +uint16_t cpu_ldw_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + uint16_t ret =3D do_ld2_mmu(env, addr, get_memop(oi), ra); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 -uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) -{ - MemOp mop =3D get_memop(oi); - uint16_t ret; - - tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_BE); - ret =3D do_ld2_he_mmu(env, addr, mop, ra); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return cpu_to_be16(ret); -} - -uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) -{ - MemOp mop =3D get_memop(oi); - uint16_t ret; - - tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_LE); - ret =3D do_ld2_he_mmu(env, addr, mop, ra); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return cpu_to_le16(ret); -} - -static uint32_t do_ld4_he_mmu(CPUArchState *env, abi_ptr addr, - MemOp mop, uintptr_t ra) +static uint32_t do_ld4_mmu(CPUArchState *env, abi_ptr addr, + MemOp mop, uintptr_t ra) { void *haddr; uint32_t ret; @@ -1011,59 +987,35 @@ static uint32_t do_ld4_he_mmu(CPUArchState *env, abi= _ptr addr, haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD); ret =3D load_atom_4(env, ra, haddr, mop); clear_helper_retaddr(); + + if (mop & MO_BSWAP) { + ret =3D bswap32(ret); + } return ret; } =20 tcg_target_ulong helper_ldul_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { - MemOp mop =3D get_memop(oi); - uint32_t ret =3D do_ld4_he_mmu(env, addr, mop, ra); - - if (mop & MO_BSWAP) { - ret =3D bswap32(ret); - } - return ret; + return do_ld4_mmu(env, addr, get_memop(oi), ra); } =20 tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { - MemOp mop =3D get_memop(oi); - int32_t ret =3D do_ld4_he_mmu(env, addr, mop, ra); + return (int32_t)do_ld4_mmu(env, addr, get_memop(oi), ra); +} =20 - if (mop & MO_BSWAP) { - ret =3D bswap32(ret); - } +uint32_t cpu_ldl_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + uint32_t ret =3D do_ld4_mmu(env, addr, get_memop(oi), ra); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 -uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) -{ - MemOp mop =3D get_memop(oi); - uint32_t ret; - - tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_BE); - ret =3D do_ld4_he_mmu(env, addr, mop, ra); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return cpu_to_be32(ret); -} - -uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) -{ - MemOp mop =3D get_memop(oi); - uint32_t ret; - - tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_LE); - ret =3D do_ld4_he_mmu(env, addr, mop, ra); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return cpu_to_le32(ret); -} - -static uint64_t do_ld8_he_mmu(CPUArchState *env, abi_ptr addr, - MemOp mop, uintptr_t ra) +static uint64_t do_ld8_mmu(CPUArchState *env, abi_ptr addr, + MemOp mop, uintptr_t ra) { void *haddr; uint64_t ret; @@ -1072,14 +1024,6 @@ static uint64_t do_ld8_he_mmu(CPUArchState *env, abi= _ptr addr, haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD); ret =3D load_atom_8(env, ra, haddr, mop); clear_helper_retaddr(); - return ret; -} - -uint64_t helper_ldq_mmu(CPUArchState *env, uint64_t addr, - MemOpIdx oi, uintptr_t ra) -{ - MemOp mop =3D get_memop(oi); - uint64_t ret =3D do_ld8_he_mmu(env, addr, mop, ra); =20 if (mop & MO_BSWAP) { ret =3D bswap64(ret); @@ -1087,32 +1031,22 @@ uint64_t helper_ldq_mmu(CPUArchState *env, uint64_t= addr, return ret; } =20 -uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr addr, +uint64_t helper_ldq_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { - MemOp mop =3D get_memop(oi); - uint64_t ret; - - tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_BE); - ret =3D do_ld8_he_mmu(env, addr, mop, ra); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return cpu_to_be64(ret); + return do_ld8_mmu(env, addr, get_memop(oi), ra); } =20 -uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) +uint64_t cpu_ldq_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - MemOp mop =3D get_memop(oi); - uint64_t ret; - - tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_LE); - ret =3D do_ld8_he_mmu(env, addr, mop, ra); + uint64_t ret =3D do_ld8_mmu(env, addr, get_memop(oi), ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return cpu_to_le64(ret); + return ret; } =20 -static Int128 do_ld16_he_mmu(CPUArchState *env, abi_ptr addr, - MemOp mop, uintptr_t ra) +static Int128 do_ld16_mmu(CPUArchState *env, abi_ptr addr, + MemOp mop, uintptr_t ra) { void *haddr; Int128 ret; @@ -1121,14 +1055,6 @@ static Int128 do_ld16_he_mmu(CPUArchState *env, abi_= ptr addr, haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD); ret =3D load_atom_16(env, ra, haddr, mop); clear_helper_retaddr(); - return ret; -} - -Int128 helper_ld16_mmu(CPUArchState *env, uint64_t addr, - MemOpIdx oi, uintptr_t ra) -{ - MemOp mop =3D get_memop(oi); - Int128 ret =3D do_ld16_he_mmu(env, addr, mop, ra); =20 if (mop & MO_BSWAP) { ret =3D bswap128(ret); @@ -1136,38 +1062,22 @@ Int128 helper_ld16_mmu(CPUArchState *env, uint64_t = addr, return ret; } =20 +Int128 helper_ld16_mmu(CPUArchState *env, uint64_t addr, + MemOpIdx oi, uintptr_t ra) +{ + return do_ld16_mmu(env, addr, get_memop(oi), ra); +} + Int128 helper_ld_i128(CPUArchState *env, uint64_t addr, MemOpIdx oi) { return helper_ld16_mmu(env, addr, oi, GETPC()); } =20 -Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) +Int128 cpu_ld16_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { - MemOp mop =3D get_memop(oi); - Int128 ret; - - tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_BE); - ret =3D do_ld16_he_mmu(env, addr, mop, ra); + Int128 ret =3D do_ld16_mmu(env, addr, get_memop(oi), ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - if (!HOST_BIG_ENDIAN) { - ret =3D bswap128(ret); - } - return ret; -} - -Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) -{ - MemOp mop =3D get_memop(oi); - Int128 ret; - - tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_LE); - ret =3D do_ld16_he_mmu(env, addr, mop, ra); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - if (HOST_BIG_ENDIAN) { - ret =3D bswap128(ret); - } return ret; } =20 @@ -1195,13 +1105,17 @@ void cpu_stb_mmu(CPUArchState *env, abi_ptr addr, u= int8_t val, qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -static void do_st2_he_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, - MemOp mop, uintptr_t ra) +static void do_st2_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, + MemOp mop, uintptr_t ra) { void *haddr; =20 tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_16); haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_STORE); + + if (mop & MO_BSWAP) { + val =3D bswap16(val); + } store_atom_2(env, ra, haddr, mop, val); clear_helper_retaddr(); } @@ -1209,41 +1123,27 @@ static void do_st2_he_mmu(CPUArchState *env, abi_pt= r addr, uint16_t val, void helper_stw_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t ra) { - MemOp mop =3D get_memop(oi); - - if (mop & MO_BSWAP) { - val =3D bswap16(val); - } - do_st2_he_mmu(env, addr, val, mop, ra); + do_st2_mmu(env, addr, val, get_memop(oi), ra); } =20 -void cpu_stw_be_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, +void cpu_stw_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, MemOpIdx oi, uintptr_t ra) { - MemOp mop =3D get_memop(oi); - - tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_BE); - do_st2_he_mmu(env, addr, be16_to_cpu(val), mop, ra); + do_st2_mmu(env, addr, val, get_memop(oi), ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -void cpu_stw_le_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, - MemOpIdx oi, uintptr_t ra) -{ - MemOp mop =3D get_memop(oi); - - tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_LE); - do_st2_he_mmu(env, addr, le16_to_cpu(val), mop, ra); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); -} - -static void do_st4_he_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, - MemOp mop, uintptr_t ra) +static void do_st4_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, + MemOp mop, uintptr_t ra) { void *haddr; =20 tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_32); haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_STORE); + + if (mop & MO_BSWAP) { + val =3D bswap32(val); + } store_atom_4(env, ra, haddr, mop, val); clear_helper_retaddr(); } @@ -1251,41 +1151,27 @@ static void do_st4_he_mmu(CPUArchState *env, abi_pt= r addr, uint32_t val, void helper_stl_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t ra) { - MemOp mop =3D get_memop(oi); - - if (mop & MO_BSWAP) { - val =3D bswap32(val); - } - do_st4_he_mmu(env, addr, val, mop, ra); + do_st4_mmu(env, addr, val, get_memop(oi), ra); } =20 -void cpu_stl_be_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, - MemOpIdx oi, uintptr_t ra) +void cpu_stl_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, + MemOpIdx oi, uintptr_t ra) { - MemOp mop =3D get_memop(oi); - - tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_BE); - do_st4_he_mmu(env, addr, be32_to_cpu(val), mop, ra); + do_st4_mmu(env, addr, val, get_memop(oi), ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -void cpu_stl_le_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, - MemOpIdx oi, uintptr_t ra) -{ - MemOp mop =3D get_memop(oi); - - tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_LE); - do_st4_he_mmu(env, addr, le32_to_cpu(val), mop, ra); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); -} - -static void do_st8_he_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, - MemOp mop, uintptr_t ra) +static void do_st8_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, + MemOp mop, uintptr_t ra) { void *haddr; =20 tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_64); haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_STORE); + + if (mop & MO_BSWAP) { + val =3D bswap64(val); + } store_atom_8(env, ra, haddr, mop, val); clear_helper_retaddr(); } @@ -1293,41 +1179,27 @@ static void do_st8_he_mmu(CPUArchState *env, abi_pt= r addr, uint64_t val, void helper_stq_mmu(CPUArchState *env, uint64_t addr, uint64_t val, MemOpIdx oi, uintptr_t ra) { - MemOp mop =3D get_memop(oi); - - if (mop & MO_BSWAP) { - val =3D bswap64(val); - } - do_st8_he_mmu(env, addr, val, mop, ra); + do_st8_mmu(env, addr, val, get_memop(oi), ra); } =20 -void cpu_stq_be_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, +void cpu_stq_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, MemOpIdx oi, uintptr_t ra) { - MemOp mop =3D get_memop(oi); - - tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_BE); - do_st8_he_mmu(env, addr, cpu_to_be64(val), mop, ra); + do_st8_mmu(env, addr, val, get_memop(oi), ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -void cpu_stq_le_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, - MemOpIdx oi, uintptr_t ra) -{ - MemOp mop =3D get_memop(oi); - - tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_LE); - do_st8_he_mmu(env, addr, cpu_to_le64(val), mop, ra); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); -} - -static void do_st16_he_mmu(CPUArchState *env, abi_ptr addr, Int128 val, - MemOp mop, uintptr_t ra) +static void do_st16_mmu(CPUArchState *env, abi_ptr addr, Int128 val, + MemOp mop, uintptr_t ra) { void *haddr; =20 tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_128); haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_STORE); + + if (mop & MO_BSWAP) { + val =3D bswap128(val); + } store_atom_16(env, ra, haddr, mop, val); clear_helper_retaddr(); } @@ -1335,12 +1207,7 @@ static void do_st16_he_mmu(CPUArchState *env, abi_pt= r addr, Int128 val, void helper_st16_mmu(CPUArchState *env, uint64_t addr, Int128 val, MemOpIdx oi, uintptr_t ra) { - MemOp mop =3D get_memop(oi); - - if (mop & MO_BSWAP) { - val =3D bswap128(val); - } - do_st16_he_mmu(env, addr, val, mop, ra); + do_st16_mmu(env, addr, val, get_memop(oi), ra); } =20 void helper_st_i128(CPUArchState *env, uint64_t addr, Int128 val, MemOpIdx= oi) @@ -1348,29 +1215,10 @@ void helper_st_i128(CPUArchState *env, uint64_t add= r, Int128 val, MemOpIdx oi) helper_st16_mmu(env, addr, val, oi, GETPC()); } =20 -void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr, - Int128 val, MemOpIdx oi, uintptr_t ra) +void cpu_st16_mmu(CPUArchState *env, abi_ptr addr, + Int128 val, MemOpIdx oi, uintptr_t ra) { - MemOp mop =3D get_memop(oi); - - tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_BE); - if (!HOST_BIG_ENDIAN) { - val =3D bswap128(val); - } - do_st16_he_mmu(env, addr, val, mop, ra); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_st16_le_mmu(CPUArchState *env, abi_ptr addr, - Int128 val, MemOpIdx oi, uintptr_t ra) -{ - MemOp mop =3D get_memop(oi); - - tcg_debug_assert((mop & MO_BSWAP) =3D=3D MO_LE); - if (HOST_BIG_ENDIAN) { - val =3D bswap128(val); - } - do_st16_he_mmu(env, addr, val, mop, ra); + do_st16_mmu(env, addr, val, get_memop(oi), ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 9758f225d6..9cef70e5c9 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -1937,8 +1937,8 @@ static bool do_v7m_function_return(ARMCPU *cpu) */ mmu_idx =3D arm_v7m_mmu_idx_for_secstate(env, true); oi =3D make_memop_idx(MO_LEUL, arm_to_core_mmu_idx(mmu_idx)); - newpc =3D cpu_ldl_le_mmu(env, frameptr, oi, 0); - newpsr =3D cpu_ldl_le_mmu(env, frameptr + 4, oi, 0); + newpc =3D cpu_ldl_mmu(env, frameptr, oi, 0); + newpsr =3D cpu_ldl_mmu(env, frameptr + 4, oi, 0); =20 /* Consistency checks on new IPSR */ newpsr_exc =3D newpsr & XPSR_EXCP; diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 7972d56a72..981a47d8bb 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1334,25 +1334,13 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_u= long addr, ret =3D cpu_ldb_mmu(env, addr, oi, GETPC()); break; case 2: - if (asi & 8) { - ret =3D cpu_ldw_le_mmu(env, addr, oi, GETPC()); - } else { - ret =3D cpu_ldw_be_mmu(env, addr, oi, GETPC()); - } + ret =3D cpu_ldw_mmu(env, addr, oi, GETPC()); break; case 4: - if (asi & 8) { - ret =3D cpu_ldl_le_mmu(env, addr, oi, GETPC()); - } else { - ret =3D cpu_ldl_be_mmu(env, addr, oi, GETPC()); - } + ret =3D cpu_ldl_mmu(env, addr, oi, GETPC()); break; case 8: - if (asi & 8) { - ret =3D cpu_ldq_le_mmu(env, addr, oi, GETPC()); - } else { - ret =3D cpu_ldq_be_mmu(env, addr, oi, GETPC()); - } + ret =3D cpu_ldq_mmu(env, addr, oi, GETPC()); break; default: g_assert_not_reached(); diff --git a/accel/tcg/ldst_common.c.inc b/accel/tcg/ldst_common.c.inc index 6ac8d871a3..5f8144b33a 100644 --- a/accel/tcg/ldst_common.c.inc +++ b/accel/tcg/ldst_common.c.inc @@ -26,7 +26,7 @@ uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr= addr, int mmu_idx, uintptr_t ra) { MemOpIdx oi =3D make_memop_idx(MO_BEUW | MO_UNALN, mmu_idx); - return cpu_ldw_be_mmu(env, addr, oi, ra); + return cpu_ldw_mmu(env, addr, oi, ra); } =20 int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, @@ -39,21 +39,21 @@ uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_pt= r addr, int mmu_idx, uintptr_t ra) { MemOpIdx oi =3D make_memop_idx(MO_BEUL | MO_UNALN, mmu_idx); - return cpu_ldl_be_mmu(env, addr, oi, ra); + return cpu_ldl_mmu(env, addr, oi, ra); } =20 uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, int mmu_idx, uintptr_t ra) { MemOpIdx oi =3D make_memop_idx(MO_BEUQ | MO_UNALN, mmu_idx); - return cpu_ldq_be_mmu(env, addr, oi, ra); + return cpu_ldq_mmu(env, addr, oi, ra); } =20 uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, int mmu_idx, uintptr_t ra) { MemOpIdx oi =3D make_memop_idx(MO_LEUW | MO_UNALN, mmu_idx); - return cpu_ldw_le_mmu(env, addr, oi, ra); + return cpu_ldw_mmu(env, addr, oi, ra); } =20 int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, @@ -66,14 +66,14 @@ uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_pt= r addr, int mmu_idx, uintptr_t ra) { MemOpIdx oi =3D make_memop_idx(MO_LEUL | MO_UNALN, mmu_idx); - return cpu_ldl_le_mmu(env, addr, oi, ra); + return cpu_ldl_mmu(env, addr, oi, ra); } =20 uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, int mmu_idx, uintptr_t ra) { MemOpIdx oi =3D make_memop_idx(MO_LEUQ | MO_UNALN, mmu_idx); - return cpu_ldq_le_mmu(env, addr, oi, ra); + return cpu_ldq_mmu(env, addr, oi, ra); } =20 void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, @@ -87,42 +87,42 @@ void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr ad= dr, uint32_t val, int mmu_idx, uintptr_t ra) { MemOpIdx oi =3D make_memop_idx(MO_BEUW | MO_UNALN, mmu_idx); - cpu_stw_be_mmu(env, addr, val, oi, ra); + cpu_stw_mmu(env, addr, val, oi, ra); } =20 void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, int mmu_idx, uintptr_t ra) { MemOpIdx oi =3D make_memop_idx(MO_BEUL | MO_UNALN, mmu_idx); - cpu_stl_be_mmu(env, addr, val, oi, ra); + cpu_stl_mmu(env, addr, val, oi, ra); } =20 void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, int mmu_idx, uintptr_t ra) { MemOpIdx oi =3D make_memop_idx(MO_BEUQ | MO_UNALN, mmu_idx); - cpu_stq_be_mmu(env, addr, val, oi, ra); + cpu_stq_mmu(env, addr, val, oi, ra); } =20 void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, int mmu_idx, uintptr_t ra) { MemOpIdx oi =3D make_memop_idx(MO_LEUW | MO_UNALN, mmu_idx); - cpu_stw_le_mmu(env, addr, val, oi, ra); + cpu_stw_mmu(env, addr, val, oi, ra); } =20 void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val, int mmu_idx, uintptr_t ra) { MemOpIdx oi =3D make_memop_idx(MO_LEUL | MO_UNALN, mmu_idx); - cpu_stl_le_mmu(env, addr, val, oi, ra); + cpu_stl_mmu(env, addr, val, oi, ra); } =20 void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val, int mmu_idx, uintptr_t ra) { MemOpIdx oi =3D make_memop_idx(MO_LEUQ | MO_UNALN, mmu_idx); - cpu_stq_le_mmu(env, addr, val, oi, ra); + cpu_stq_mmu(env, addr, val, oi, ra); } =20 /*--------------------------*/ --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886300; x=1687478300; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6h4wH/HlwcEwYXgME8pcPio0lwnlB9jo/ZTVy+Ahgvg=; b=bp3j6DLr0gnH0zMmKntQnuVQSbCusjDje6OmQMmJD4IPUAPh2ccM2awGE8URClRYEy RyeU3D+gQOLY1HTesdp9dZ9yVcKLNOFoPA8ZJz/prWJl/6sIXtWoTXKiOCJPsNsmp9xy 5q2N1K9m2MZ0a7szg8vv/ld9Ip3WSaO4A+ab0K2MSLbwrfqGhApWIIOdWngVpx9O1qbv sqIDO7kmy7blGGxrVMwjgGONblrVOiLvgzYOFiiJRb6L40wNtBXRjC+GkFt9Onvnk7WM Ck6cDHAEuBUeoeQ5mHj1xxOJ/9/f1uXfm2Schff9CpAzeyEu3JdXxWkwX4xMp+aUpqxG 8CfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886300; x=1687478300; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6h4wH/HlwcEwYXgME8pcPio0lwnlB9jo/ZTVy+Ahgvg=; b=U6RZaUktGqUSl9ovqrIASRXNEsOunFKtJtsWw8VR/t9ATxi3V8nu+Pqr0Nrj5QMhIO qjaH86XhoKqhDd+pToPEGyrL8Q6ny3rzyhby+tIhidYSopwEjxSvlwGRpWhE9PW033e0 /ISIYqNwo7OxilJStEtXooM0z4dWGHCce0wFsjJHN+qBnfZ8ujSL7WjAmN/+Y6hBWOwU /CcMxYSPKBh5NvtbEJocJ4u05NwTjw3lQRJLo56VxNrP6jdQwdwt2ofC0SjygrxyXm4t PaL5xYXUo1tYI1IbmoEwsvlBa2p2Y1F3j8cZKQB0cWjYkz4T/M6rhOv6/lWOIFuyF9ud 7CcQ== X-Gm-Message-State: AC+VfDwW0r6EUQtqEC8dcA5yKw32j15UhpZT5JGSH+FBD61zHeNZRLP3 LmoNObtLVpuK1dKFCmxMKNakXqlzmYh+93stYq0= X-Google-Smtp-Source: ACHHUZ79X6Rp00cWP6xtRid8SCviP7mRU6rGDS24J8PmFWRgq0jZv1OrQo/c20x3WjF+VwwzTZvEVA== X-Received: by 2002:aa7:88d4:0:b0:64c:ecf7:f49a with SMTP id k20-20020aa788d4000000b0064cecf7f49amr909425pff.21.1684886300361; Tue, 23 May 2023 16:58:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Hildenbrand Subject: [PULL 17/28] target/s390x: Use cpu_{ld,st}*_mmu in do_csst Date: Tue, 23 May 2023 16:57:53 -0700 Message-Id: <20230523235804.747803-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886623705100007 Use cpu_ld16_mmu and cpu_st16_mmu to eliminate the special case, and change all of the *_data_ra functions to match. Note that we check the alignment of both compare and store pointers at the top of the function, so MO_ALIGN* may be safely removed from the individual memory operations. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 66 ++++++++++++++--------------------- 1 file changed, 27 insertions(+), 39 deletions(-) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 0e0d66b3b6..c757612244 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1737,6 +1737,11 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t= r3, uint64_t a1, uint64_t a2, bool parallel) { uint32_t mem_idx =3D cpu_mmu_index(env, false); + MemOpIdx oi16 =3D make_memop_idx(MO_TE | MO_128, mem_idx); + MemOpIdx oi8 =3D make_memop_idx(MO_TE | MO_64, mem_idx); + MemOpIdx oi4 =3D make_memop_idx(MO_TE | MO_32, mem_idx); + MemOpIdx oi2 =3D make_memop_idx(MO_TE | MO_16, mem_idx); + MemOpIdx oi1 =3D make_memop_idx(MO_8, mem_idx); uintptr_t ra =3D GETPC(); uint32_t fc =3D extract32(env->regs[0], 0, 8); uint32_t sc =3D extract32(env->regs[0], 8, 8); @@ -1780,15 +1785,17 @@ static uint32_t do_csst(CPUS390XState *env, uint32_= t r3, uint64_t a1, } } =20 - /* All loads happen before all stores. For simplicity, load the entire - store value area from the parameter list. */ - svh =3D cpu_ldq_data_ra(env, pl + 16, ra); - svl =3D cpu_ldq_data_ra(env, pl + 24, ra); + /* + * All loads happen before all stores. For simplicity, load the entire + * store value area from the parameter list. + */ + svh =3D cpu_ldq_mmu(env, pl + 16, oi8, ra); + svl =3D cpu_ldq_mmu(env, pl + 24, oi8, ra); =20 switch (fc) { case 0: { - uint32_t nv =3D cpu_ldl_data_ra(env, pl, ra); + uint32_t nv =3D cpu_ldl_mmu(env, pl, oi4, ra); uint32_t cv =3D env->regs[r3]; uint32_t ov; =20 @@ -1801,8 +1808,8 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, ov =3D cpu_atomic_cmpxchgl_be_mmu(env, a1, cv, nv, oi, ra); #endif } else { - ov =3D cpu_ldl_data_ra(env, a1, ra); - cpu_stl_data_ra(env, a1, (ov =3D=3D cv ? nv : ov), ra); + ov =3D cpu_ldl_mmu(env, a1, oi4, ra); + cpu_stl_mmu(env, a1, (ov =3D=3D cv ? nv : ov), oi4, ra); } cc =3D (ov !=3D cv); env->regs[r3] =3D deposit64(env->regs[r3], 32, 32, ov); @@ -1811,21 +1818,20 @@ static uint32_t do_csst(CPUS390XState *env, uint32_= t r3, uint64_t a1, =20 case 1: { - uint64_t nv =3D cpu_ldq_data_ra(env, pl, ra); + uint64_t nv =3D cpu_ldq_mmu(env, pl, oi8, ra); uint64_t cv =3D env->regs[r3]; uint64_t ov; =20 if (parallel) { #ifdef CONFIG_ATOMIC64 - MemOpIdx oi =3D make_memop_idx(MO_TEUQ | MO_ALIGN, mem_idx= ); - ov =3D cpu_atomic_cmpxchgq_be_mmu(env, a1, cv, nv, oi, ra); + ov =3D cpu_atomic_cmpxchgq_be_mmu(env, a1, cv, nv, oi8, ra= ); #else /* Note that we asserted !parallel above. */ g_assert_not_reached(); #endif } else { - ov =3D cpu_ldq_data_ra(env, a1, ra); - cpu_stq_data_ra(env, a1, (ov =3D=3D cv ? nv : ov), ra); + ov =3D cpu_ldq_mmu(env, a1, oi8, ra); + cpu_stq_mmu(env, a1, (ov =3D=3D cv ? nv : ov), oi8, ra); } cc =3D (ov !=3D cv); env->regs[r3] =3D ov; @@ -1834,27 +1840,19 @@ static uint32_t do_csst(CPUS390XState *env, uint32_= t r3, uint64_t a1, =20 case 2: { - uint64_t nvh =3D cpu_ldq_data_ra(env, pl, ra); - uint64_t nvl =3D cpu_ldq_data_ra(env, pl + 8, ra); - Int128 nv =3D int128_make128(nvl, nvh); + Int128 nv =3D cpu_ld16_mmu(env, pl, oi16, ra); Int128 cv =3D int128_make128(env->regs[r3 + 1], env->regs[r3]); Int128 ov; =20 if (!parallel) { - uint64_t oh =3D cpu_ldq_data_ra(env, a1 + 0, ra); - uint64_t ol =3D cpu_ldq_data_ra(env, a1 + 8, ra); - - ov =3D int128_make128(ol, oh); + ov =3D cpu_ld16_mmu(env, a1, oi16, ra); cc =3D !int128_eq(ov, cv); if (cc) { nv =3D ov; } - - cpu_stq_data_ra(env, a1 + 0, int128_gethi(nv), ra); - cpu_stq_data_ra(env, a1 + 8, int128_getlo(nv), ra); + cpu_st16_mmu(env, a1, nv, oi16, ra); } else if (HAVE_CMPXCHG128) { - MemOpIdx oi =3D make_memop_idx(MO_TE | MO_128 | MO_ALIGN, = mem_idx); - ov =3D cpu_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, ra); + ov =3D cpu_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi16, r= a); cc =3D !int128_eq(ov, cv); } else { /* Note that we asserted !parallel above. */ @@ -1876,29 +1874,19 @@ static uint32_t do_csst(CPUS390XState *env, uint32_= t r3, uint64_t a1, if (cc =3D=3D 0) { switch (sc) { case 0: - cpu_stb_data_ra(env, a2, svh >> 56, ra); + cpu_stb_mmu(env, a2, svh >> 56, oi1, ra); break; case 1: - cpu_stw_data_ra(env, a2, svh >> 48, ra); + cpu_stw_mmu(env, a2, svh >> 48, oi2, ra); break; case 2: - cpu_stl_data_ra(env, a2, svh >> 32, ra); + cpu_stl_mmu(env, a2, svh >> 32, oi4, ra); break; case 3: - cpu_stq_data_ra(env, a2, svh, ra); + cpu_stq_mmu(env, a2, svh, oi8, ra); break; case 4: - if (!parallel) { - cpu_stq_data_ra(env, a2 + 0, svh, ra); - cpu_stq_data_ra(env, a2 + 8, svl, ra); - } else if (HAVE_ATOMIC128) { - MemOpIdx oi =3D make_memop_idx(MO_TEUQ | MO_ALIGN_16, mem_= idx); - Int128 sv =3D int128_make128(svl, svh); - cpu_atomic_sto_be_mmu(env, a2, sv, oi, ra); - } else { - /* Note that we asserted !parallel above. */ - g_assert_not_reached(); - } + cpu_st16_mmu(env, a2, int128_make128(svl, svh), oi16, ra); break; default: g_assert_not_reached(); --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684886554; cv=none; d=zohomail.com; s=zohoarc; b=A+/K+JZrsUdndCisNl63xOv3OzW+wMPb+FZ8Kt0bMk+3CLeJ7nnKkYjeyO33wf9bYpfDbGXTTYTfH9Vpc2fhMp0V5bjVVd4I1uwwG4ul92l77R0D2GWMaxFkh7NMeCOXOC7euYt4FnoETS8BTAypJKAnlT0i84+qL0+yQnXm2kY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684886554; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Sc7213RLRuctojtWLbzPuqzsIJI6tjTB/1Lhu64ZbUY=; b=GJH50VN4oZ/KSiE/vxAWeB6R94JvoiNWjXygbVdNinh9uiEvKgEJGP1/V7hBeMcaDDZ1+IFbYIIg8iJcbTBy4P3SOAKMV0YpqbvPvXILnsFd2DCNZ2L1EJhFKPanH+o+9+ULwBHOcFyOy7jwP8jpsdY/IbVSsOZ3Kk6L/rMkb9g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684886554968520.0442724622129; Tue, 23 May 2023 17:02:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1btm-0004K5-JQ; Tue, 23 May 2023 19:58:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1btk-0004Hv-Qh for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:36 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1btX-0001pT-Gy for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:34 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-64d3fdcadb8so95291b3a.3 for ; Tue, 23 May 2023 16:58:23 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886301; x=1687478301; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Sc7213RLRuctojtWLbzPuqzsIJI6tjTB/1Lhu64ZbUY=; b=ih/DCthxb31OTF9pCYXZnZMk8uXpq7ya8Rh32cV5Z/Y2P7O9raWWuh0O2LhKddpau8 HA2tDYZUL9m37IMLnQ82jFPOQA1OXqKwztx1ApmOJKNlK5ilhlQXQ3PxSLOawbhVTmuP bXpBbCwyuhtMk31QJKtQCpMbS5q92e9aZZaHsvimepUBSAxmzKn8bfdMiRJ/NAzedVqa iSzmieAR2LxEC7aJMeVoApWSxJQOlBlQnwkFOQoI3i+/n2RLjk2KM6nkI2K4tAU3ig4O btmrvWzfrMu8JbKd/KAQOrF/1WKKXrzUa0qiY+FZ4ELLDcLyk88bi5qjp4CxSUp9JOyJ VZBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886301; x=1687478301; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Sc7213RLRuctojtWLbzPuqzsIJI6tjTB/1Lhu64ZbUY=; b=gBi148VxQkmsOXBFSI9FIZBgMK+cfh3jmf2YmZKzPpOJabaUJmF6foFHNXUcxHi9Vk 7klLB4WR/g4Pc2OvD6I4aGNzpxk0gveia00cuWFCWKrG3uW/tbtVcB+kv6VfqOQb37GG GdO6g5yscijH65GvgnASktk9XOrkO0VHwe8JKWSt5KtRlsQ0DefeYUAYKGLM9IxsUaKC i7j9i0VKctRUzG6JKCcKjYS8I0xnFLFX5ypEDuKEp9vtJM1ssVzbAW6bIfEfHyG4Gvg1 +/p4Yr64CjFJXkYtPkPQy8FmcGayhO8oAp0sGTHCcxh15WRJVVk0a8png6on/uVnVLOa 2I+g== X-Gm-Message-State: AC+VfDziW7tu1Jdsn5rmMr1MLaamHQl1YTAoIn0mwgLauJp+0ZQ71hv2 DMCZMbrKGiB7+MR7XTm0ROp/HUsXMUQdxhhAyMA= X-Google-Smtp-Source: ACHHUZ7fkjMjIKvkBPo8apAsBDuDkUgkiyzS0SI2SJQ2Emmqrw3Xaj3SReZU2oz+XNqgspycbJ4asw== X-Received: by 2002:a05:6a00:842:b0:64d:5cc5:fa67 with SMTP id q2-20020a056a00084200b0064d5cc5fa67mr804085pfk.17.1684886301235; Tue, 23 May 2023 16:58:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Hildenbrand Subject: [PULL 18/28] target/s390x: Always use cpu_atomic_cmpxchgl_be_mmu in do_csst Date: Tue, 23 May 2023 16:57:54 -0700 Message-Id: <20230523235804.747803-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886555344100001 Eliminate the CONFIG_USER_ONLY specialization. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/tcg/mem_helper.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index c757612244..aa8ec6ba6d 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1800,13 +1800,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t= r3, uint64_t a1, uint32_t ov; =20 if (parallel) { -#ifdef CONFIG_USER_ONLY - uint32_t *haddr =3D g2h(env_cpu(env), a1); - ov =3D qatomic_cmpxchg__nocheck(haddr, cv, nv); -#else - MemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mem_idx= ); - ov =3D cpu_atomic_cmpxchgl_be_mmu(env, a1, cv, nv, oi, ra); -#endif + ov =3D cpu_atomic_cmpxchgl_be_mmu(env, a1, cv, nv, oi4, ra= ); } else { ov =3D cpu_ldl_mmu(env, a1, oi4, ra); cpu_stl_mmu(env, a1, (ov =3D=3D cv ? nv : ov), oi4, ra); --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684886415; cv=none; d=zohomail.com; s=zohoarc; b=AkNyFF0z6jaEx2Z2Wwo4T2WyEcCkjA+q8868ebLA9eHf3MYxz5xLhhZED5kaXeBUMYH1ezQ/9X4IKsZjDZ0cyk0YBnGr5O2aYqtkYIWRTIvJNTXgEWEFpCAJEvzLMoJ3QJQ+7NPYW/DtRlzWSLyBcQfMfQg8bCd8bTTq07+3mxU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684886415; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CuRyDk0Qj/U/m/Fk9xebGBVdcrGRTNv4rYYxEUzzoxI=; b=LzwwLmWhakf+rIeG6RA67IpqKwJCPqIlGy1+HuZg11Kn1JSSupAIrFWIwauVevNizsCTR+sDfE3j5STAteKGNqq35kJx78WqRzwl1a9FoQ8cy/KCP4swYeMfGS8lqMYFU3jRtWftgXXP+W7e7sKd3BbtiiYQ0btTC3qhY8D1eTk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684886415330488.41744725593185; Tue, 23 May 2023 17:00:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1btx-0004MG-5t; Tue, 23 May 2023 19:58:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1btk-0004Hw-RT for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:36 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1btX-0001nE-Ex for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:34 -0400 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-64d4e4598f0so147454b3a.2 for ; Tue, 23 May 2023 16:58:22 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886302; x=1687478302; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CuRyDk0Qj/U/m/Fk9xebGBVdcrGRTNv4rYYxEUzzoxI=; b=H8GxB9qFWv8yWGLeU0JrA+0ZDfFUkOxgMACD8doJGDPncleM2w/b9n9FUgR6YJbwOd N2/CAQNBvcSGrpTAh5aenEmOpfrOi9jNo00hDX0jGSSSUJg4ZbVDv+t1K+W5dgArmRc+ xMZwxXZ1ZHdEH9f6zLmfkSQ7ZaorhGhVF5SgDpTWE8f9+3/L0DougXh7b3ox+ZTIJhvy FzNaLrXFL5+IPe13jHQodthww/KE3h46b4txZtKdyOx1TEMbgjgSTogEFepxTZh3WaWS O+I5DWjtm4XjDdkxAgerYTVXepyePLgcCFMH27GdLZNYLbmfjynfkOEFvxoWCJTZFw84 i1PQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886302; x=1687478302; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CuRyDk0Qj/U/m/Fk9xebGBVdcrGRTNv4rYYxEUzzoxI=; b=bAXlvZ1KdhBDJ9RTBewCJdhaac4X65F8GEpZAVVJgVfuCM9L+T8Jo+iMSfCOlO37YQ nf3Gp8+3KIZJzzusDhgjl2B9dXZPymf9dvdgTK6hPPiI9U3Hfk8AHYjVB8JUySY3j8Pa VrqqdrnRc2VS5Gbm0G7iHKeiuQMOUs+UEiBuvWXbZRLmoUBIf7TxbcfYKfIQg+1dMhRf iLuTAV0vmctS24rMdjhZmERcMi97hohJvRJweaiLE3UV6PgcXBaytryhyq5twq1t/hUO 8NRwUM/UHQBXQIpAEbilf+TVQrKxWgTQ+n83O5H71CKZHjcA8pjCIBQTHEjFiObwRDHN Zysw== X-Gm-Message-State: AC+VfDyzIwsdcBceJfTrsg3NQXN1drUpDEljiTOVwxYVzsW2Kp+LH8ya VTyOw3nI3b4fmVOdckbKIHlU+VTNh0VUhJpLx/I= X-Google-Smtp-Source: ACHHUZ4Ur/I5njRqoEoj+L7Ru6aHMOThYIlOasIb/xUVqouWCf8FbYkwP1HCZ5CbrZViSM5W3tTIyw== X-Received: by 2002:a05:6a00:842:b0:64f:4197:8d93 with SMTP id q2-20020a056a00084200b0064f41978d93mr848640pfk.24.1684886302013; Tue, 23 May 2023 16:58:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 19/28] accel/tcg: Remove cpu_atomic_{ld,st}o_*_mmu Date: Tue, 23 May 2023 16:57:55 -0700 Message-Id: <20230523235804.747803-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886416806100002 Atomic load/store of 128-byte quantities is now handled by cpu_{ld,st}16_mmu. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 61 +++-------------------------------- include/exec/cpu_ldst.h | 9 ------ accel/tcg/atomic_common.c.inc | 14 -------- 3 files changed, 4 insertions(+), 80 deletions(-) diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index 404a530f7c..30eee9d066 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -87,33 +87,7 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_= ulong addr, return ret; } =20 -#if DATA_SIZE >=3D 16 -#if HAVE_ATOMIC128 -ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) -{ - DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, - PAGE_READ, retaddr); - DATA_TYPE val; - - val =3D atomic16_read(haddr); - ATOMIC_MMU_CLEANUP; - atomic_trace_ld_post(env, addr, oi); - return val; -} - -void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val, - MemOpIdx oi, uintptr_t retaddr) -{ - DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, - PAGE_WRITE, retaddr); - - atomic16_set(haddr, val); - ATOMIC_MMU_CLEANUP; - atomic_trace_st_post(env, addr, oi); -} -#endif -#else +#if DATA_SIZE < 16 ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE = val, MemOpIdx oi, uintptr_t retaddr) { @@ -188,7 +162,7 @@ GEN_ATOMIC_HELPER_FN(smax_fetch, MAX, SDATA_TYPE, new) GEN_ATOMIC_HELPER_FN(umax_fetch, MAX, DATA_TYPE, new) =20 #undef GEN_ATOMIC_HELPER_FN -#endif /* DATA SIZE >=3D 16 */ +#endif /* DATA SIZE < 16 */ =20 #undef END =20 @@ -220,34 +194,7 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, targe= t_ulong addr, return BSWAP(ret); } =20 -#if DATA_SIZE >=3D 16 -#if HAVE_ATOMIC128 -ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) -{ - DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, - PAGE_READ, retaddr); - DATA_TYPE val; - - val =3D atomic16_read(haddr); - ATOMIC_MMU_CLEANUP; - atomic_trace_ld_post(env, addr, oi); - return BSWAP(val); -} - -void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val, - MemOpIdx oi, uintptr_t retaddr) -{ - DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, - PAGE_WRITE, retaddr); - - val =3D BSWAP(val); - atomic16_set(haddr, val); - ATOMIC_MMU_CLEANUP; - atomic_trace_st_post(env, addr, oi); -} -#endif -#else +#if DATA_SIZE < 16 ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE = val, MemOpIdx oi, uintptr_t retaddr) { @@ -326,7 +273,7 @@ GEN_ATOMIC_HELPER_FN(add_fetch, ADD, DATA_TYPE, new) #undef ADD =20 #undef GEN_ATOMIC_HELPER_FN -#endif /* DATA_SIZE >=3D 16 */ +#endif /* DATA_SIZE < 16 */ =20 #undef END #endif /* DATA_SIZE > 1 */ diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index fc1d3d9301..5939688f69 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -300,15 +300,6 @@ Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, t= arget_ulong addr, Int128 cmpv, Int128 newv, MemOpIdx oi, uintptr_t retaddr); =20 -Int128 cpu_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -Int128 cpu_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr); -void cpu_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 va= l, - MemOpIdx oi, uintptr_t retaddr); -void cpu_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 va= l, - MemOpIdx oi, uintptr_t retaddr); - #if defined(CONFIG_USER_ONLY) =20 extern __thread uintptr_t helper_retaddr; diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc index fe0eea018f..f255c9e215 100644 --- a/accel/tcg/atomic_common.c.inc +++ b/accel/tcg/atomic_common.c.inc @@ -19,20 +19,6 @@ static void atomic_trace_rmw_post(CPUArchState *env, uin= t64_t addr, qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_RW); } =20 -#if HAVE_ATOMIC128 -static void atomic_trace_ld_post(CPUArchState *env, uint64_t addr, - MemOpIdx oi) -{ - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); -} - -static void atomic_trace_st_post(CPUArchState *env, uint64_t addr, - MemOpIdx oi) -{ - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); -} -#endif - /* * Atomic helpers callable from TCG. * These have a common interface and all defer to cpu_atomic_* --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886303; x=1687478303; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bUiC8B941VenGp4T2O+nh8vsCtJVXe6reCgoVgugxCk=; b=Hu/3xqcNLofOAinlf5QDsZRG23c+EI+wgQ1l/tjkhqCR4+zIVOjkWwlEhyrmaHuqT7 KezY99ENvFkureoalFzwjb83Ubop0w8d/kFmzGZTe5mBshEBiUPDzmtyr4pUmQoGYlb0 9BtFmfQWQs0smLwPWNRa/rpqDvQ3hrbkXb3lEnk0B2ju0TqcfLWLM34E1eQdCCzWeVLJ SM5ApzovHDYxcQ0j77MBR5XhvtkZY7affmasSBUxnbmWYIujuFoxjna/wUnqpnaZdY6A uBg3K72vpQ6gpCwfmguUq0WMPynT4dlQYi12AwZuBBbIpRQyzt3EWeLQhicXBqQixUzj MBvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886303; x=1687478303; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bUiC8B941VenGp4T2O+nh8vsCtJVXe6reCgoVgugxCk=; b=V9yoaTws71qXZ4bSHCI8xame5OCDOCi2wIOPCUDXFIlJF68e1T/gbPrt88HpaGzzTf QgiHIkT3GWcaFY/mxuEW7qSmz+B7vnVZCgnMxZlaHUXsTy2NrBS4BDnJ7RO6W2c42T+r rshDFSAd436UWPpUgphzWSN8NBwgJ1q0O1/QkFcC2Ca2267DtgvGQuBsFJ8pXTl74XHs ZPa1ejTfxRNOhShC7X/CfGUjT2+jw0+hKmalXkveEQ9h6Gszjja3LJDgcrKX0MEtVyhP jtodKrmIgF5RD4vYRcFhVyssjJYUOKB7TBYMYrwZd9CiTeinCww8W16ZEXD/kLG9zLCN /mjw== X-Gm-Message-State: AC+VfDw/smfcwnGmt23NY4IWBYJ2Sq3o4g4PUJ8Ax6vNZf/X9kbkbV8u EGJVKsbtcH/lzfvD0hRIQ1wZafdt1FNpAsbq7kk= X-Google-Smtp-Source: ACHHUZ6I78vjlEoEbYE1M6QBUw+lbZ6Ppzl6750qsfp/wvVU6tlWvRduVrT6emXToJ8HjHerAiL2eA== X-Received: by 2002:a05:6a00:148a:b0:63c:1be4:5086 with SMTP id v10-20020a056a00148a00b0063c1be45086mr1028975pfu.6.1684886302731; Tue, 23 May 2023 16:58:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 20/28] accel/tcg: Remove prot argument to atomic_mmu_lookup Date: Tue, 23 May 2023 16:57:56 -0700 Message-Id: <20230523235804.747803-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886859375100005 Now that load/store are gone, we're always passing PAGE_READ | PAGE_WRITE for RMW atomic operations. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 32 ++++++-------- accel/tcg/cputlb.c | 85 ++++++++++++++----------------------- accel/tcg/user-exec.c | 8 +--- 3 files changed, 45 insertions(+), 80 deletions(-) diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index 30eee9d066..e312acd16d 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -73,8 +73,7 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_u= long addr, ABI_TYPE cmpv, ABI_TYPE newv, MemOpIdx oi, uintptr_t retaddr) { - DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, - PAGE_READ | PAGE_WRITE, retaddr); + DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retad= dr); DATA_TYPE ret; =20 #if DATA_SIZE =3D=3D 16 @@ -91,8 +90,7 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_u= long addr, ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE = val, MemOpIdx oi, uintptr_t retaddr) { - DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, - PAGE_READ | PAGE_WRITE, retaddr); + DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retad= dr); DATA_TYPE ret; =20 ret =3D qatomic_xchg__nocheck(haddr, val); @@ -105,9 +103,8 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ul= ong addr, ABI_TYPE val, ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \ { \ - DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \ - PAGE_READ | PAGE_WRITE, retaddr);= \ - DATA_TYPE ret; \ + DATA_TYPE *haddr, ret; \ + haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr); \ ret =3D qatomic_##X(haddr, val); \ ATOMIC_MMU_CLEANUP; \ atomic_trace_rmw_post(env, addr, oi); \ @@ -137,9 +134,8 @@ GEN_ATOMIC_HELPER(xor_fetch) ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \ { \ - XDATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \ - PAGE_READ | PAGE_WRITE, retaddr)= ; \ - XDATA_TYPE cmp, old, new, val =3D xval; \ + XDATA_TYPE *haddr, cmp, old, new, val =3D xval; \ + haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr); \ smp_mb(); \ cmp =3D qatomic_read__nocheck(haddr); \ do { \ @@ -180,8 +176,7 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target= _ulong addr, ABI_TYPE cmpv, ABI_TYPE newv, MemOpIdx oi, uintptr_t retaddr) { - DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, - PAGE_READ | PAGE_WRITE, retaddr); + DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retad= dr); DATA_TYPE ret; =20 #if DATA_SIZE =3D=3D 16 @@ -198,8 +193,7 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target= _ulong addr, ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE = val, MemOpIdx oi, uintptr_t retaddr) { - DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, - PAGE_READ | PAGE_WRITE, retaddr); + DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retad= dr); ABI_TYPE ret; =20 ret =3D qatomic_xchg__nocheck(haddr, BSWAP(val)); @@ -212,9 +206,8 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ul= ong addr, ABI_TYPE val, ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \ { \ - DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \ - PAGE_READ | PAGE_WRITE, retaddr);= \ - DATA_TYPE ret; \ + DATA_TYPE *haddr, ret; \ + haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr); \ ret =3D qatomic_##X(haddr, BSWAP(val)); \ ATOMIC_MMU_CLEANUP; \ atomic_trace_rmw_post(env, addr, oi); \ @@ -241,9 +234,8 @@ GEN_ATOMIC_HELPER(xor_fetch) ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \ { \ - XDATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \ - PAGE_READ | PAGE_WRITE, retaddr)= ; \ - XDATA_TYPE ldo, ldn, old, new, val =3D xval; \ + XDATA_TYPE *haddr, ldo, ldn, old, new, val =3D xval; \ + haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr); \ smp_mb(); \ ldn =3D qatomic_read__nocheck(haddr); \ do { \ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b1e13d165c..9cb0b697d1 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1896,12 +1896,9 @@ static bool mmu_lookup(CPUArchState *env, target_ulo= ng addr, MemOpIdx oi, /* * Probe for an atomic operation. Do not allow unaligned operations, * or io operations to proceed. Return the host address. - * - * @prot may be PAGE_READ, PAGE_WRITE, or PAGE_READ|PAGE_WRITE. */ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, - MemOpIdx oi, int size, int prot, - uintptr_t retaddr) + MemOpIdx oi, int size, uintptr_t retaddr) { uintptr_t mmu_idx =3D get_mmuidx(oi); MemOp mop =3D get_memop(oi); @@ -1937,54 +1934,37 @@ static void *atomic_mmu_lookup(CPUArchState *env, t= arget_ulong addr, tlbe =3D tlb_entry(env, mmu_idx, addr); =20 /* Check TLB entry and enforce page permissions. */ - if (prot & PAGE_WRITE) { - tlb_addr =3D tlb_addr_write(tlbe); - if (!tlb_hit(tlb_addr, addr)) { - if (!victim_tlb_hit(env, mmu_idx, index, MMU_DATA_STORE, - addr & TARGET_PAGE_MASK)) { - tlb_fill(env_cpu(env), addr, size, - MMU_DATA_STORE, mmu_idx, retaddr); - index =3D tlb_index(env, mmu_idx, addr); - tlbe =3D tlb_entry(env, mmu_idx, addr); - } - tlb_addr =3D tlb_addr_write(tlbe) & ~TLB_INVALID_MASK; - } - - if (prot & PAGE_READ) { - /* - * Let the guest notice RMW on a write-only page. - * We have just verified that the page is writable. - * Subpage lookups may have left TLB_INVALID_MASK set, - * but addr_read will only be -1 if PAGE_READ was unset. - */ - if (unlikely(tlbe->addr_read =3D=3D -1)) { - tlb_fill(env_cpu(env), addr, size, - MMU_DATA_LOAD, mmu_idx, retaddr); - /* - * Since we don't support reads and writes to different - * addresses, and we do have the proper page loaded for - * write, this shouldn't ever return. But just in case, - * handle via stop-the-world. - */ - goto stop_the_world; - } - /* Collect TLB_WATCHPOINT for read. */ - tlb_addr |=3D tlbe->addr_read; - } - } else /* if (prot & PAGE_READ) */ { - tlb_addr =3D tlbe->addr_read; - if (!tlb_hit(tlb_addr, addr)) { - if (!victim_tlb_hit(env, mmu_idx, index, MMU_DATA_LOAD, - addr & TARGET_PAGE_MASK)) { - tlb_fill(env_cpu(env), addr, size, - MMU_DATA_LOAD, mmu_idx, retaddr); - index =3D tlb_index(env, mmu_idx, addr); - tlbe =3D tlb_entry(env, mmu_idx, addr); - } - tlb_addr =3D tlbe->addr_read & ~TLB_INVALID_MASK; + tlb_addr =3D tlb_addr_write(tlbe); + if (!tlb_hit(tlb_addr, addr)) { + if (!victim_tlb_hit(env, mmu_idx, index, MMU_DATA_STORE, + addr & TARGET_PAGE_MASK)) { + tlb_fill(env_cpu(env), addr, size, + MMU_DATA_STORE, mmu_idx, retaddr); + index =3D tlb_index(env, mmu_idx, addr); + tlbe =3D tlb_entry(env, mmu_idx, addr); } + tlb_addr =3D tlb_addr_write(tlbe) & ~TLB_INVALID_MASK; } =20 + /* + * Let the guest notice RMW on a write-only page. + * We have just verified that the page is writable. + * Subpage lookups may have left TLB_INVALID_MASK set, + * but addr_read will only be -1 if PAGE_READ was unset. + */ + if (unlikely(tlbe->addr_read =3D=3D -1)) { + tlb_fill(env_cpu(env), addr, size, MMU_DATA_LOAD, mmu_idx, retaddr= ); + /* + * Since we don't support reads and writes to different + * addresses, and we do have the proper page loaded for + * write, this shouldn't ever return. But just in case, + * handle via stop-the-world. + */ + goto stop_the_world; + } + /* Collect TLB_WATCHPOINT for read. */ + tlb_addr |=3D tlbe->addr_read; + /* Notice an IO access or a needs-MMU-lookup access */ if (unlikely(tlb_addr & (TLB_MMIO | TLB_DISCARD_WRITE))) { /* There's really nothing that can be done to @@ -2000,11 +1980,8 @@ static void *atomic_mmu_lookup(CPUArchState *env, ta= rget_ulong addr, } =20 if (unlikely(tlb_addr & TLB_WATCHPOINT)) { - QEMU_BUILD_BUG_ON(PAGE_READ !=3D BP_MEM_READ); - QEMU_BUILD_BUG_ON(PAGE_WRITE !=3D BP_MEM_WRITE); - /* therefore prot =3D=3D watchpoint bits */ - cpu_check_watchpoint(env_cpu(env), addr, size, - full->attrs, prot, retaddr); + cpu_check_watchpoint(env_cpu(env), addr, size, full->attrs, + BP_MEM_READ | BP_MEM_WRITE, retaddr); } =20 return hostaddr; diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 19c2849c21..1e085b1210 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1323,12 +1323,9 @@ uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr= addr, =20 /* * Do not allow unaligned operations to proceed. Return the host address. - * - * @prot may be PAGE_READ, PAGE_WRITE, or PAGE_READ|PAGE_WRITE. */ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, - MemOpIdx oi, int size, int prot, - uintptr_t retaddr) + MemOpIdx oi, int size, uintptr_t retaddr) { MemOp mop =3D get_memop(oi); int a_bits =3D get_alignment_bits(mop); @@ -1336,8 +1333,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, =20 /* Enforce guest required alignment. */ if (unlikely(addr & ((1 << a_bits) - 1))) { - MMUAccessType t =3D prot =3D=3D PAGE_READ ? MMU_DATA_LOAD : MMU_DA= TA_STORE; - cpu_loop_exit_sigbus(env_cpu(env), addr, t, retaddr); + cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_STORE, retaddr); } =20 /* Enforce qemu required alignment. */ --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684886702; cv=none; d=zohomail.com; s=zohoarc; b=ZfGG+Sxtyd8itnSVnVlO7MwWZERCTr4QSS41v07aMGOQQYZQDiyG7tp2a9C8f2aPIMw+E2ga+3wH+rLpJIKWrIRGYAdvb7iBGefQpHItNUYzzewIKZK1jBbB/ZmAlCTCMV7jxQ+Czs/S7No3OSC6i71ijXlFONBcR+4uVhc77sg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684886702; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rkYVlK3RdF9zN2MHNE1wKJqPl/6YEBFQeP4y1IxzryQ=; b=ZK0wxWtfJXKVNGB6Ec2wa40XwRXbhJS8n9JCN752HybvVRMsHhx4H32foKfrfsuMlW5D4qr0aDZn2y1GLRYrhQeLstRpYjG274PfIpnI6DFoHx0xM4rWb49Ctl6HnlEC9Uev4FLFpqiG6J+hq9bFojawvfdqhXqxIprGiPZtDVg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684886702669691.1373214130516; Tue, 23 May 2023 17:05:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1btm-0004Jm-Cp; Tue, 23 May 2023 19:58:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1btk-0004Ht-PK for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:36 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1btY-0001mr-Gk for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:35 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-64d5b4c400fso155913b3a.1 for ; Tue, 23 May 2023 16:58:24 -0700 (PDT) Received: from stoup.. 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Use the matching CONFIG_* symbols for that purpose. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- host/include/aarch64/host/atomic128-cas.h | 2 ++ host/include/generic/host/atomic128-ldst.h | 2 +- accel/tcg/cputlb.c | 2 +- accel/tcg/user-exec.c | 2 +- 4 files changed, 5 insertions(+), 3 deletions(-) diff --git a/host/include/aarch64/host/atomic128-cas.h b/host/include/aarch= 64/host/atomic128-cas.h index 80de58e06d..58630107bc 100644 --- a/host/include/aarch64/host/atomic128-cas.h +++ b/host/include/aarch64/host/atomic128-cas.h @@ -37,6 +37,8 @@ static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128= cmp, Int128 new) =20 return int128_make128(oldl, oldh); } + +# define CONFIG_CMPXCHG128 1 # define HAVE_CMPXCHG128 1 #endif =20 diff --git a/host/include/generic/host/atomic128-ldst.h b/host/include/gene= ric/host/atomic128-ldst.h index 46911dfb61..06a62e9dd0 100644 --- a/host/include/generic/host/atomic128-ldst.h +++ b/host/include/generic/host/atomic128-ldst.h @@ -33,7 +33,7 @@ atomic16_set(Int128 *ptr, Int128 val) } =20 # define HAVE_ATOMIC128 1 -#elif !defined(CONFIG_USER_ONLY) && HAVE_CMPXCHG128 +#elif defined(CONFIG_CMPXCHG128) && !defined(CONFIG_USER_ONLY) static inline Int128 ATTRIBUTE_ATOMIC128_OPT atomic16_read(Int128 *ptr) { diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 9cb0b697d1..0bd06bf894 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -3038,7 +3038,7 @@ void cpu_st16_mmu(CPUArchState *env, target_ulong add= r, Int128 val, #include "atomic_template.h" #endif =20 -#if HAVE_CMPXCHG128 || HAVE_ATOMIC128 +#if defined(CONFIG_ATOMIC128) || defined(CONFIG_CMPXCHG128) #define DATA_SIZE 16 #include "atomic_template.h" #endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 1e085b1210..dc8d6b5d40 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1371,7 +1371,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, #include "atomic_template.h" #endif =20 -#if HAVE_ATOMIC128 || HAVE_CMPXCHG128 +#if defined(CONFIG_ATOMIC128) || defined(CONFIG_CMPXCHG128) #define DATA_SIZE 16 #include "atomic_template.h" #endif --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684886406; cv=none; d=zohomail.com; s=zohoarc; b=aC7Pot1kWZKNrtYvoQR8i81/8FSW5F2z9IKA5te2suGud9xsKtIOzNiBPBRK6Ps1vtXpYj97Zy1Zo6tUwosVK4vZROw6kKjZElP/q6+1Wzrd+iJ86c0AcvtCylZFzR4VLBRXGyazCr9Hrq4fwIoSc32eyfxHNtAhaXSa2IaZ7sw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684886406; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JA7ZHKOHjO/TjL2EciXYRkAGdweiOEKASZl+z4Fq7S0=; b=PWVfOdeNgYlqKHI5gmGXQnzrj92rkAnBH9JeIsB8kQDMVmLdyWygrNOhmRAAUH9rYthKCd6i6EnBqaOU72rlOaj+b5AOd4114DtUA4Iu1pTIjSZ2lwCMAEDoJA3UGOxV0MJUVMyoiCSo6WojorHCcqb7/F1o4335KJRBbktB2HY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684886406322398.3530367682441; Tue, 23 May 2023 17:00:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1bu6-0004O3-V0; Tue, 23 May 2023 19:58:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1btk-0004Hy-U3 for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:36 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1btZ-0001lP-DU for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:35 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-64d5f65a2f7so103919b3a.1 for ; Tue, 23 May 2023 16:58:25 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886304; x=1687478304; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JA7ZHKOHjO/TjL2EciXYRkAGdweiOEKASZl+z4Fq7S0=; b=HsfCWTPbyQWVr6NasuMkIPGUMONIH8vo6Fk3Nga0Pwfzid/gbpb9ovHejfk99c/wSO 6BKX5Bxc6eFuo90UvKy7unoGDL/muZEGVjlpuF42WPi4zHaBPFENNv6lqRfS6ug9f3l1 5rdw9rmq62k4L78GnzPDJh3If8B07R8UvYMYY0CpiKOFgHvZPFcKi4rW+/in7jwQvyrh c9ChqQNeoOPaZ3XeQQssqYTMikuXpEI2gOHixNuwCVXhdVVpMA4avzrr3r20TyVAhEoL Hg109su8QHk3+NAM7YGeIjmjmzAf+i04AoHuwM6W3ex3xYpRmEs4aJYUGCqDVkBqQXvg oDIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886304; x=1687478304; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JA7ZHKOHjO/TjL2EciXYRkAGdweiOEKASZl+z4Fq7S0=; b=E9F2tyfqeBqmYum5osBC5L7ruA/RWuAoZbIKWC9a7EbhvRl44Rp/UL/+cAkuBxoI4C 6+gqgQC7HPo+6D75d0Z5jOcKWOssB/pnvvDzL8Wd0Nudg+jX2tKVZ229zBKLDdqB4w+R lxZI4bUvoANVmGVMGtqPlzOLrIr/vqayO4qF85CcaH5GJoUjS/u09QuZvUoLoKcGRnSe 2VcMv6gaPJ4rs+luW1oMwsvWeKPCKdaowW4FTv6lwrxu2J6Avv5jDDCfXFKUAcxtnl71 Y7FvZTt19VhJEeavp87asvTQtbfQBS20U/npe6X7QPuldlgIpG400mQX4DrCePGe+ufB wM5w== X-Gm-Message-State: AC+VfDzShchF4aP0hfuurE1fQZBDO3UEpCNb1Car02gCRU4L8UVeD5eh th2/bCWjGEG01vYiBy4UxFVGzLL2MFGSHoY5E3I= X-Google-Smtp-Source: ACHHUZ5Z1ayIBW+eOUtxzm4vDVdCkcu29UHedS98+m23Jl1A70gOaeOTNthikVcpN9M9aXDdFvmfcQ== X-Received: by 2002:a05:6a00:1596:b0:63b:8778:99e4 with SMTP id u22-20020a056a00159600b0063b877899e4mr1160431pfk.2.1684886304650; Tue, 23 May 2023 16:58:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 22/28] qemu/atomic128: Split atomic16_read Date: Tue, 23 May 2023 16:57:58 -0700 Message-Id: <20230523235804.747803-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886407789100003 Create both atomic16_read_ro and atomic16_read_rw. Previously we pretended that we had atomic16_read in system mode, because we "know" that all ram is always writable to the host. Now, expose read-only and read-write versions all of the time. For aarch64, do not fall back to __atomic_read_16 even if supported by the compiler, to work around a clang bug. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- host/include/aarch64/host/atomic128-ldst.h | 21 ++++++++------- host/include/generic/host/atomic128-ldst.h | 31 ++++++++++++++++------ target/s390x/tcg/mem_helper.c | 2 +- 3 files changed, 36 insertions(+), 18 deletions(-) diff --git a/host/include/aarch64/host/atomic128-ldst.h b/host/include/aarc= h64/host/atomic128-ldst.h index bd61fce50d..4b1360de39 100644 --- a/host/include/aarch64/host/atomic128-ldst.h +++ b/host/include/aarch64/host/atomic128-ldst.h @@ -11,10 +11,18 @@ #ifndef AARCH64_ATOMIC128_LDST_H #define AARCH64_ATOMIC128_LDST_H =20 -/* Through gcc 10, aarch64 has no support for 128-bit atomics. */ -#if !defined(CONFIG_ATOMIC128) && !defined(CONFIG_USER_ONLY) -/* We can do better than cmpxchg for AArch64. */ -static inline Int128 atomic16_read(Int128 *ptr) +/* + * Through gcc 10, aarch64 has no support for 128-bit atomics. + * Through clang 16, without -march=3Darmv8.4-a, __atomic_load_16 + * is incorrectly expanded to a read-write operation. + */ + +#define HAVE_ATOMIC128_RO 0 +#define HAVE_ATOMIC128_RW 1 + +Int128 QEMU_ERROR("unsupported atomic") atomic16_read_ro(const Int128 *ptr= ); + +static inline Int128 atomic16_read_rw(Int128 *ptr) { uint64_t l, h; uint32_t tmp; @@ -41,9 +49,4 @@ static inline void atomic16_set(Int128 *ptr, Int128 val) : [l] "r"(l), [h] "r"(h)); } =20 -# define HAVE_ATOMIC128 1 -#else -#include "host/include/generic/host/atomic128-ldst.h" -#endif - #endif /* AARCH64_ATOMIC128_LDST_H */ diff --git a/host/include/generic/host/atomic128-ldst.h b/host/include/gene= ric/host/atomic128-ldst.h index 06a62e9dd0..79d208b7a4 100644 --- a/host/include/generic/host/atomic128-ldst.h +++ b/host/include/generic/host/atomic128-ldst.h @@ -12,16 +12,25 @@ #define HOST_ATOMIC128_LDST_H =20 #if defined(CONFIG_ATOMIC128) +# define HAVE_ATOMIC128_RO 1 +# define HAVE_ATOMIC128_RW 1 + static inline Int128 ATTRIBUTE_ATOMIC128_OPT -atomic16_read(Int128 *ptr) +atomic16_read_ro(const Int128 *ptr) { - __int128_t *ptr_align =3D __builtin_assume_aligned(ptr, 16); + const __int128_t *ptr_align =3D __builtin_assume_aligned(ptr, 16); Int128Alias r; =20 r.i =3D qatomic_read__nocheck(ptr_align); return r.s; } =20 +static inline Int128 ATTRIBUTE_ATOMIC128_OPT +atomic16_read_rw(Int128 *ptr) +{ + return atomic16_read_ro(ptr); +} + static inline void ATTRIBUTE_ATOMIC128_OPT atomic16_set(Int128 *ptr, Int128 val) { @@ -32,10 +41,14 @@ atomic16_set(Int128 *ptr, Int128 val) qatomic_set__nocheck(ptr_align, v.i); } =20 -# define HAVE_ATOMIC128 1 -#elif defined(CONFIG_CMPXCHG128) && !defined(CONFIG_USER_ONLY) +#elif defined(CONFIG_CMPXCHG128) +# define HAVE_ATOMIC128_RO 0 +# define HAVE_ATOMIC128_RW 1 + +Int128 QEMU_ERROR("unsupported atomic") atomic16_read_ro(const Int128 *ptr= ); + static inline Int128 ATTRIBUTE_ATOMIC128_OPT -atomic16_read(Int128 *ptr) +atomic16_read_rw(Int128 *ptr) { /* Maybe replace 0 with 0, returning the old value. */ Int128 z =3D int128_make64(0); @@ -52,12 +65,14 @@ atomic16_set(Int128 *ptr, Int128 val) } while (int128_ne(old, cmp)); } =20 -# define HAVE_ATOMIC128 1 #else +# define HAVE_ATOMIC128_RO 0 +# define HAVE_ATOMIC128_RW 0 + /* Fallback definitions that must be optimized away, or error. */ -Int128 QEMU_ERROR("unsupported atomic") atomic16_read(Int128 *ptr); +Int128 QEMU_ERROR("unsupported atomic") atomic16_read_ro(const Int128 *ptr= ); +Int128 QEMU_ERROR("unsupported atomic") atomic16_read_rw(Int128 *ptr); void QEMU_ERROR("unsupported atomic") atomic16_set(Int128 *ptr, Int128 val= ); -# define HAVE_ATOMIC128 0 #endif =20 #endif /* HOST_ATOMIC128_LDST_H */ diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index aa8ec6ba6d..d02ec861d8 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1780,7 +1780,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, max =3D 3; #endif if ((HAVE_CMPXCHG128 ? 0 : fc + 2 > max) || - (HAVE_ATOMIC128 ? 0 : sc > max)) { + (HAVE_ATOMIC128_RW ? 0 : sc > max)) { cpu_loop_exit_atomic(env_cpu(env), ra); } } --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684886861; cv=none; d=zohomail.com; s=zohoarc; b=cykqlN2M0YfmfwNWBwdEI7iDV4fowMvNaAONCjqJ/R4gssnPR0o5zJ2TToJEjKAvGjvPM+oX8+/zQhReOXcWwlSFa6hibRvlubpQDOlxMMykifZNIZQeUiVtMtaBTBYfwU/ruD6MVTXBSe051n+RHp0ne4rvHJAcftvd0+5q/ZU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684886861; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=b5v8Jw3T9w8HbbAUjH4p5nPo8yur91Ib1kP6ESGvdT8=; b=BqPotWVc5UW5d+6YzqyqNR5L22oLup9zDsyFON2MXY9ORf7zlWZnQ0WmpQrRmJnaQtniiplC5STZp0TiFV/xpS3exqEWsO25GQSV51H0U112e/Zesh7qAb6qhBID76o+WDBDa3Shgvu18cmCuDPY5fFF+nSNI0fDxGjXU7ogCd4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168488686197158.30343798814147; Tue, 23 May 2023 17:07:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1bu7-0004O9-5R; Tue, 23 May 2023 19:58:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1btl-0004JA-Ik for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:37 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1bta-0001rX-T4 for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:37 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-64d44b198baso104091b3a.0 for ; Tue, 23 May 2023 16:58:26 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886305; x=1687478305; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b5v8Jw3T9w8HbbAUjH4p5nPo8yur91Ib1kP6ESGvdT8=; b=SAZ95qdo2K2OaAuWf2wnqkyNwkdBMdn1qAMkOHs0ZYjsoeagJ745LCfhnWsmRgwPET 5unrCNAb3a2oL4F+eMmzKJ3ZDUwE7pSoLLMznLWnYrG7cMJvw6g0L02BFaEfhPVuiu3S GUj7kJJj9AWZqliQQCkAG8v2J0cl1D1A2RtQwcNZ3RpO5qkscNtjyIq52nZpoXeJfWw/ r/32cwlzOQPOUGTONxJJszvcNXQxjO2xPf7xCMmPAGsnQvwiTVzH7RnYq+hRUhb5JYu8 jcUyEj8kQgOq9k/zuZvH3rpw5LdwrjADG0ZlfcZnQr0WlqJuG+Um1xM6cPsnJASdQYgL 6a/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886305; x=1687478305; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b5v8Jw3T9w8HbbAUjH4p5nPo8yur91Ib1kP6ESGvdT8=; b=XQ3AF2+NhqVUAKq+KStKWH4dC6WyemcNtr6JUSgt3h7RH/fvW3i2sbjk9crArVB09l rPkkC0bYnxrSxvlEoRs035gT6Kbg3BU0cW8xF6DqVxyoPfzVdIpAyPQVpyQF/BQfIkR/ KxUNpMjzVcF6Mp+tygRQB3gaMRsKkDbHHJnUiHnl/+7u3eR0RIR3XIiis3rJ4O3AGDir Zs9xqQztmZjWJEDffaWMMIepH432NYnDqbbAEipf7xnRGhxJBbW69subte5h0D0kIXis H74B0W5cqIcqSkFRTEpTG3XoA3T0pvNRdakSBcmGHZQCZ+xtN+cax/lZRO7mA8O+5Vh0 VRew== X-Gm-Message-State: AC+VfDwotjDGqGPWauL3frUT2MzF8mvhh7xAU0EZFWmCb+8tRvZW/oiA fo3SEDfLKNsj/bUEozIOSRcpXRqbGUymo/mu9rg= X-Google-Smtp-Source: ACHHUZ5T4+tyoxLiy2XCQ5bcNgPpTriORlTKa1nJlna3A3/JdzxI9g73LSGN6Osg/Xp9u7GwvmRBmA== X-Received: by 2002:a05:6a00:24c8:b0:64f:31cd:4e4a with SMTP id d8-20020a056a0024c800b0064f31cd4e4amr708123pfv.12.1684886305488; Tue, 23 May 2023 16:58:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 23/28] accel/tcg: Correctly use atomic128.h in ldst_atomicity.c.inc Date: Tue, 23 May 2023 16:57:59 -0700 Message-Id: <20230523235804.747803-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886862770100018 Remove the locally defined load_atomic16 and store_atomic16, along with HAVE_al16 and HAVE_al16_fast in favor of the routines defined in atomic128.h. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 2 +- accel/tcg/ldst_atomicity.c.inc | 118 +++++++-------------------------- 2 files changed, 24 insertions(+), 96 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 0bd06bf894..90c72c9940 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2712,7 +2712,7 @@ static uint64_t do_st16_leN(CPUArchState *env, MMULoo= kupPageData *p, =20 case MO_ATOM_WITHIN16_PAIR: /* Since size > 8, this is the half that must be atomic. */ - if (!HAVE_al16) { + if (!HAVE_ATOMIC128_RW) { cpu_loop_exit_atomic(env_cpu(env), ra); } return store_whole_le16(p->haddr, p->size, val_le); diff --git a/accel/tcg/ldst_atomicity.c.inc b/accel/tcg/ldst_atomicity.c.inc index b89631bbef..0f6b3f8ab6 100644 --- a/accel/tcg/ldst_atomicity.c.inc +++ b/accel/tcg/ldst_atomicity.c.inc @@ -16,18 +16,6 @@ #endif #define HAVE_al8_fast (ATOMIC_REG_SIZE >=3D 8) =20 -#if defined(CONFIG_ATOMIC128) -# define HAVE_al16_fast true -#else -# define HAVE_al16_fast false -#endif -#if defined(CONFIG_ATOMIC128) || defined(CONFIG_CMPXCHG128) -# define HAVE_al16 true -#else -# define HAVE_al16 false -#endif - - /** * required_atomicity: * @@ -146,26 +134,6 @@ static inline uint64_t load_atomic8(void *pv) return qatomic_read__nocheck(p); } =20 -/** - * load_atomic16: - * @pv: host address - * - * Atomically load 16 aligned bytes from @pv. - */ -static inline Int128 ATTRIBUTE_ATOMIC128_OPT -load_atomic16(void *pv) -{ -#ifdef CONFIG_ATOMIC128 - __uint128_t *p =3D __builtin_assume_aligned(pv, 16); - Int128Alias r; - - r.u =3D qatomic_read__nocheck(p); - return r.s; -#else - qemu_build_not_reached(); -#endif -} - /** * load_atomic8_or_exit: * @env: cpu context @@ -211,8 +179,8 @@ static Int128 load_atomic16_or_exit(CPUArchState *env, = uintptr_t ra, void *pv) { Int128 *p =3D __builtin_assume_aligned(pv, 16); =20 - if (HAVE_al16_fast) { - return load_atomic16(p); + if (HAVE_ATOMIC128_RO) { + return atomic16_read_ro(p); } =20 #ifdef CONFIG_USER_ONLY @@ -232,14 +200,9 @@ static Int128 load_atomic16_or_exit(CPUArchState *env,= uintptr_t ra, void *pv) * In system mode all guest pages are writable, and for user-only * we have just checked writability. Try cmpxchg. */ -#if defined(CONFIG_CMPXCHG128) - /* Swap 0 with 0, with the side-effect of returning the old value. */ - { - Int128Alias r; - r.u =3D __sync_val_compare_and_swap_16((__uint128_t *)p, 0, 0); - return r.s; + if (HAVE_ATOMIC128_RW) { + return atomic16_read_rw(p); } -#endif =20 /* Ultimate fallback: re-execute in serial context. */ cpu_loop_exit_atomic(env_cpu(env), ra); @@ -360,11 +323,10 @@ static uint64_t load_atom_extract_al16_or_exit(CPUArc= hState *env, uintptr_t ra, static inline uint64_t ATTRIBUTE_ATOMIC128_OPT load_atom_extract_al16_or_al8(void *pv, int s) { -#if defined(CONFIG_ATOMIC128) uintptr_t pi =3D (uintptr_t)pv; int o =3D pi & 7; int shr =3D (HOST_BIG_ENDIAN ? 16 - s - o : o) * 8; - __uint128_t r; + Int128 r; =20 pv =3D (void *)(pi & ~7); if (pi & 8) { @@ -373,18 +335,14 @@ load_atom_extract_al16_or_al8(void *pv, int s) uint64_t b =3D qatomic_read__nocheck(p8 + 1); =20 if (HOST_BIG_ENDIAN) { - r =3D ((__uint128_t)a << 64) | b; + r =3D int128_make128(b, a); } else { - r =3D ((__uint128_t)b << 64) | a; + r =3D int128_make128(a, b); } } else { - __uint128_t *p16 =3D __builtin_assume_aligned(pv, 16, 0); - r =3D qatomic_read__nocheck(p16); + r =3D atomic16_read_ro(pv); } - return r >> shr; -#else - qemu_build_not_reached(); -#endif + return int128_getlo(int128_urshift(r, shr)); } =20 /** @@ -472,7 +430,7 @@ static uint16_t load_atom_2(CPUArchState *env, uintptr_= t ra, if (likely((pi & 1) =3D=3D 0)) { return load_atomic2(pv); } - if (HAVE_al16_fast) { + if (HAVE_ATOMIC128_RO) { return load_atom_extract_al16_or_al8(pv, 2); } =20 @@ -511,7 +469,7 @@ static uint32_t load_atom_4(CPUArchState *env, uintptr_= t ra, if (likely((pi & 3) =3D=3D 0)) { return load_atomic4(pv); } - if (HAVE_al16_fast) { + if (HAVE_ATOMIC128_RO) { return load_atom_extract_al16_or_al8(pv, 4); } =20 @@ -557,7 +515,7 @@ static uint64_t load_atom_8(CPUArchState *env, uintptr_= t ra, if (HAVE_al8 && likely((pi & 7) =3D=3D 0)) { return load_atomic8(pv); } - if (HAVE_al16_fast) { + if (HAVE_ATOMIC128_RO) { return load_atom_extract_al16_or_al8(pv, 8); } =20 @@ -607,8 +565,8 @@ static Int128 load_atom_16(CPUArchState *env, uintptr_t= ra, * If the host does not support 16-byte atomics, wait until we have * examined the atomicity parameters below. */ - if (HAVE_al16_fast && likely((pi & 15) =3D=3D 0)) { - return load_atomic16(pv); + if (HAVE_ATOMIC128_RO && likely((pi & 15) =3D=3D 0)) { + return atomic16_read_ro(pv); } =20 atmax =3D required_atomicity(env, pi, memop); @@ -687,36 +645,6 @@ static inline void store_atomic8(void *pv, uint64_t va= l) qatomic_set__nocheck(p, val); } =20 -/** - * store_atomic16: - * @pv: host address - * @val: value to store - * - * Atomically store 16 aligned bytes to @pv. - */ -static inline void ATTRIBUTE_ATOMIC128_OPT -store_atomic16(void *pv, Int128Alias val) -{ -#if defined(CONFIG_ATOMIC128) - __uint128_t *pu =3D __builtin_assume_aligned(pv, 16); - qatomic_set__nocheck(pu, val.u); -#elif defined(CONFIG_CMPXCHG128) - __uint128_t *pu =3D __builtin_assume_aligned(pv, 16); - __uint128_t o; - - /* - * Without CONFIG_ATOMIC128, __atomic_compare_exchange_n will always - * defer to libatomic, so we must use __sync_*_compare_and_swap_16 - * and accept the sequential consistency that comes with it. - */ - do { - o =3D *pu; - } while (!__sync_bool_compare_and_swap_16(pu, o, val.u)); -#else - qemu_build_not_reached(); -#endif -} - /** * store_atom_4x2 */ @@ -957,7 +885,7 @@ static uint64_t store_whole_le16(void *pv, int size, In= t128 val_le) int sh =3D o * 8; Int128 m, v; =20 - qemu_build_assert(HAVE_al16); + qemu_build_assert(HAVE_ATOMIC128_RW); =20 /* Like MAKE_64BIT_MASK(0, sz), but larger. */ if (sz <=3D 64) { @@ -1017,7 +945,7 @@ static void store_atom_2(CPUArchState *env, uintptr_t = ra, return; } } else if ((pi & 15) =3D=3D 7) { - if (HAVE_al16) { + if (HAVE_ATOMIC128_RW) { Int128 v =3D int128_lshift(int128_make64(val), 56); Int128 m =3D int128_lshift(int128_make64(0xffff), 56); store_atom_insert_al16(pv - 7, v, m); @@ -1086,7 +1014,7 @@ static void store_atom_4(CPUArchState *env, uintptr_t= ra, return; } } else { - if (HAVE_al16) { + if (HAVE_ATOMIC128_RW) { store_whole_le16(pv, 4, int128_make64(cpu_to_le32(val))); return; } @@ -1151,7 +1079,7 @@ static void store_atom_8(CPUArchState *env, uintptr_t= ra, } break; case MO_64: - if (HAVE_al16) { + if (HAVE_ATOMIC128_RW) { store_whole_le16(pv, 8, int128_make64(cpu_to_le64(val))); return; } @@ -1177,8 +1105,8 @@ static void store_atom_16(CPUArchState *env, uintptr_= t ra, uint64_t a, b; int atmax; =20 - if (HAVE_al16_fast && likely((pi & 15) =3D=3D 0)) { - store_atomic16(pv, val); + if (HAVE_ATOMIC128_RW && likely((pi & 15) =3D=3D 0)) { + atomic16_set(pv, val); return; } =20 @@ -1206,7 +1134,7 @@ static void store_atom_16(CPUArchState *env, uintptr_= t ra, } break; case -MO_64: - if (HAVE_al16) { + if (HAVE_ATOMIC128_RW) { uint64_t val_le; int s2 =3D pi & 15; int s1 =3D 16 - s2; @@ -1233,8 +1161,8 @@ static void store_atom_16(CPUArchState *env, uintptr_= t ra, } break; case MO_128: - if (HAVE_al16) { - store_atomic16(pv, val); + if (HAVE_ATOMIC128_RW) { + atomic16_set(pv, val); return; } break; --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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} while (0) +#else +# define tcg_debug_assert(X) \ + do { if (!(X)) { __builtin_unreachable(); } } while (0) +#endif + +#endif diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index cd6327b175..072c35f7f5 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -34,6 +34,7 @@ #include "tcg/tcg-mo.h" #include "tcg-target.h" #include "tcg/tcg-cond.h" +#include "tcg/debug-assert.h" =20 /* XXX: make safe guess about sizes */ #define MAX_OP_PER_INSTR 266 @@ -222,14 +223,6 @@ typedef uint64_t tcg_insn_unit; /* The port better have done this. */ #endif =20 - -#if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS -# define tcg_debug_assert(X) do { assert(X); } while (0) -#else -# define tcg_debug_assert(X) \ - do { if (!(X)) { __builtin_unreachable(); } } while (0) -#endif - typedef struct TCGRelocation TCGRelocation; struct TCGRelocation { QSIMPLEQ_ENTRY(TCGRelocation) next; diff --git a/MAINTAINERS b/MAINTAINERS index 1a32066231..1c93ab0ee5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -159,6 +159,7 @@ F: include/sysemu/tcg.h F: include/hw/core/tcg-cpu-ops.h F: host/include/*/host/cpuinfo.h F: util/cpuinfo-*.c +F: include/tcg/ =20 FPU emulation M: Aurelien Jarno --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886307; x=1687478307; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3dmtEq6kmVE3RGdrdH/eSfhix7HRQOKB/pXZ4u4czNE=; b=dxMp/su4auZGrrxiQBjq4afhP5rhz+Jao3vaoth+fd3PI9eQcjfG9m4Ug3yCYLw7Qc EKoQC/Q/oSIWDLMm8BlgSv/SM5RyV0n8sn2McfQwzkFg+xusYIout824De4/wEtyGuNt f/uvfMpmgbvgNpTtT+Vw0BLeiZTEYolc4SL01V7/En1PQx6nw5D8vyC884vGBLp5CPeL kgaGHSxMGJValIS9hHgFRLsMXL4HHgRrlxx1I6sQDHSOWgRPu+dJ+ewEDlV1J0ieddxM z0FoZ+7oNb/JyIlugY/GaB/xBQ/+olevL/+nJIIN/W99mJaeqeOg4taD/kvV0tnrpfay YHgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886307; x=1687478307; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3dmtEq6kmVE3RGdrdH/eSfhix7HRQOKB/pXZ4u4czNE=; b=hW9xuQa4UUNIOOmbgpLksTni7heLcwmjWBhzfvyms4tpG7TQKPV6A8Im5nk57npMVY Auq0WGRzrxyajA1weKefURbWfA6Os977eK7IM1iOablN8l521IKKe3jXYDmwN2UYtmIc eWTkSIvWQo75JKTMCIC4nj0EHw9eRKPL5Ry8RcMS1zhpPvrbozZ2Op3bzXhRl5663At0 gEtxkQHyXgcjYZu91Kx65ftQIiKuxuhcMBH0LApMaZop+P+polzEm6o2QSlvfmzHxdYS C94vcMW6SUoVLiQIOYargXL/Fddxx2YiY98Vk3bA4L/6JBadZTZtnfRvwHnV79NFqCRH esJg== X-Gm-Message-State: AC+VfDwVq7Z7K1B33utDRvjf+BB54HkzAGDFuShi/R1+v9dxtoiGaUwB iZ/MP0kgW23UY54hCHTE6nzulQuXqdP8VUuvorM= X-Google-Smtp-Source: ACHHUZ7ycotBLApiLL+wOf7czpkQrFmjVqximqsTWdw8mSiK7Y0bLsIMPBBTOXbccyVy9fE6w2dEJg== X-Received: by 2002:a05:6a00:2d13:b0:64c:b45f:fc86 with SMTP id fa19-20020a056a002d1300b0064cb45ffc86mr746573pfb.17.1684886307248; Tue, 23 May 2023 16:58:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 25/28] qemu/atomic128: Improve cmpxchg fallback for atomic16_set Date: Tue, 23 May 2023 16:58:01 -0700 Message-Id: <20230523235804.747803-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886858754100001 Use __sync_bool_compare_and_swap_16 to control the loop, rather than a separate comparison. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- host/include/generic/host/atomic128-ldst.h | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/host/include/generic/host/atomic128-ldst.h b/host/include/gene= ric/host/atomic128-ldst.h index 79d208b7a4..80fff0643a 100644 --- a/host/include/generic/host/atomic128-ldst.h +++ b/host/include/generic/host/atomic128-ldst.h @@ -58,11 +58,14 @@ atomic16_read_rw(Int128 *ptr) static inline void ATTRIBUTE_ATOMIC128_OPT atomic16_set(Int128 *ptr, Int128 val) { - Int128 old =3D *ptr, cmp; + __int128_t *ptr_align =3D __builtin_assume_aligned(ptr, 16); + __int128_t old; + Int128Alias new; + + new.s =3D val; do { - cmp =3D old; - old =3D atomic16_cmpxchg(ptr, cmp, val); - } while (int128_ne(old, cmp)); + old =3D *ptr_align; + } while (!__sync_bool_compare_and_swap_16(ptr_align, old, new.i)); } =20 #else --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684886862; cv=none; d=zohomail.com; s=zohoarc; b=FPLn8xHYhAF0RZaQ/ktC0XvJLm9WAX5KeDYhhC293npNxkEEoIvx1ghxyZY6eNZx7gskF0ng6ER+4WKwmo1Mr0Kj7CI2WKvtpXr+8IIG1VbmzlqvxHGQj8OdY5+tdhI4l3q6mpRGmoXG4wLcSGLl1h0Hv/VHThGlx2Wgh0XNjIg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684886862; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5xRZz/kuOTdd5TU904Y896iQ+sGtDMJKa0ny6/I3nUo=; b=DqvH3GsG82IBukGm1gIEo96e1ubfO2DyJ/XaMnm0nEJJy9srywnXvwf9Aiyy5+zIuQ06C0+Y09u1blhouS1QqaFXTLvaL2iG4wcXchOf61iZX8jEyD/sakzKspjg9P1t+5TfZse8P6Q+gDBTn3Cki0oi6+w1+IpdMQGCFeDK/5E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684886862856413.63731413320113; Tue, 23 May 2023 17:07:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1bu7-0004Ok-Mm; Tue, 23 May 2023 19:58:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1btl-0004J6-Fd for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:37 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1btc-0001lW-Pb for qemu-devel@nongnu.org; Tue, 23 May 2023 19:58:37 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-64d41d8bc63so123957b3a.0 for ; Tue, 23 May 2023 16:58:28 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- host/include/aarch64/host/atomic128-ldst.h | 53 ++++++++++++++++------ 1 file changed, 40 insertions(+), 13 deletions(-) diff --git a/host/include/aarch64/host/atomic128-ldst.h b/host/include/aarc= h64/host/atomic128-ldst.h index 4b1360de39..5aabd6b978 100644 --- a/host/include/aarch64/host/atomic128-ldst.h +++ b/host/include/aarch64/host/atomic128-ldst.h @@ -11,27 +11,48 @@ #ifndef AARCH64_ATOMIC128_LDST_H #define AARCH64_ATOMIC128_LDST_H =20 +#include "host/cpuinfo.h" +#include "tcg/debug-assert.h" + /* * Through gcc 10, aarch64 has no support for 128-bit atomics. * Through clang 16, without -march=3Darmv8.4-a, __atomic_load_16 * is incorrectly expanded to a read-write operation. + * + * Anyway, this method allows runtime detection of FEAT_LSE2. */ =20 -#define HAVE_ATOMIC128_RO 0 +#define HAVE_ATOMIC128_RO (cpuinfo & CPUINFO_LSE2) #define HAVE_ATOMIC128_RW 1 =20 -Int128 QEMU_ERROR("unsupported atomic") atomic16_read_ro(const Int128 *ptr= ); +static inline Int128 atomic16_read_ro(const Int128 *ptr) +{ + uint64_t l, h; + + tcg_debug_assert(HAVE_ATOMIC128_RO); + /* With FEAT_LSE2, 16-byte aligned LDP is atomic. */ + asm("ldp %[l], %[h], %[mem]" + : [l] "=3Dr"(l), [h] "=3Dr"(h) : [mem] "m"(*ptr)); + + return int128_make128(l, h); +} =20 static inline Int128 atomic16_read_rw(Int128 *ptr) { uint64_t l, h; uint32_t tmp; =20 - /* The load must be paired with the store to guarantee not tearing. */ - asm("0: ldxp %[l], %[h], %[mem]\n\t" - "stxp %w[tmp], %[l], %[h], %[mem]\n\t" - "cbnz %w[tmp], 0b" - : [mem] "+m"(*ptr), [tmp] "=3Dr"(tmp), [l] "=3Dr"(l), [h] "=3Dr"(h= )); + if (cpuinfo & CPUINFO_LSE2) { + /* With FEAT_LSE2, 16-byte aligned LDP is atomic. */ + asm("ldp %[l], %[h], %[mem]" + : [l] "=3Dr"(l), [h] "=3Dr"(h) : [mem] "m"(*ptr)); + } else { + /* The load must be paired with the store to guarantee not tearing= . */ + asm("0: ldxp %[l], %[h], %[mem]\n\t" + "stxp %w[tmp], %[l], %[h], %[mem]\n\t" + "cbnz %w[tmp], 0b" + : [mem] "+m"(*ptr), [tmp] "=3Dr"(tmp), [l] "=3Dr"(l), [h] "=3D= r"(h)); + } =20 return int128_make128(l, h); } @@ -41,12 +62,18 @@ static inline void atomic16_set(Int128 *ptr, Int128 val) uint64_t l =3D int128_getlo(val), h =3D int128_gethi(val); uint64_t t1, t2; =20 - /* Load into temporaries to acquire the exclusive access lock. */ - asm("0: ldxp %[t1], %[t2], %[mem]\n\t" - "stxp %w[t1], %[l], %[h], %[mem]\n\t" - "cbnz %w[t1], 0b" - : [mem] "+m"(*ptr), [t1] "=3D&r"(t1), [t2] "=3D&r"(t2) - : [l] "r"(l), [h] "r"(h)); + if (cpuinfo & CPUINFO_LSE2) { + /* With FEAT_LSE2, 16-byte aligned STP is atomic. */ + asm("stp %[l], %[h], %[mem]" + : [mem] "=3Dm"(*ptr) : [l] "r"(l), [h] "r"(h)); + } else { + /* Load into temporaries to acquire the exclusive access lock. */ + asm("0: ldxp %[t1], %[t2], %[mem]\n\t" + "stxp %w[t1], %[l], %[h], %[mem]\n\t" + "cbnz %w[t1], 0b" + : [mem] "+m"(*ptr), [t1] "=3D&r"(t1), [t2] "=3D&r"(t2) + : [l] "r"(l), [h] "r"(h)); + } } =20 #endif /* AARCH64_ATOMIC128_LDST_H */ --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886309; x=1687478309; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AhKJJweUGQGGXYuCAoB5iwT5c/CX9FC0MQLQONjnrYU=; b=aNOUorAGv6sHqA6YaonyfhWTkJNWbk2aTFj2gHzV5mQScW2xUyEqxWJjQqD6k/dDMW 0kX2T/AR4VtGflnCg8r9S/DvDWkzBtaW7dTonmyKLVxup1kyt5mKE5YTfKQoXElSBEYX 2dymhpTg/VE/lWeyK8QV91xAAgcLkMIPdspYzteizHN5PTwts82C6MocTGl6h/U2lHfX 5mCf706/AtB35ogxRDG3Tos+Xueu4IGjc0kfULbl7SUY90yFNOU1az/mRxnBCsUr/5f1 7tXN3S5ecplpZ4wAbN78YDheQnOQHnHgDsd+n6W59W8vU5KKaXhZul08OnR+jGK3QsAu 7RDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886309; x=1687478309; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AhKJJweUGQGGXYuCAoB5iwT5c/CX9FC0MQLQONjnrYU=; b=j4iyOGwlkWh5k+7uSlKXnZ+NlRANXQk3EH3mmB1Bbdwf1toMQfnvrW1chNDRlKnvap Wz/ohE4Aixrazjo/IuL14965XBsG4Jn5WUyRNi7tshZikThULnJ3r7jWLeadGERkGkr4 QF9WBxrr2bthg3HKo89B1Hh6SLOnktHA4uvGd9VQp1gGZWQdpjnyyhyKEc553qHJe5HS usEkGOZUkweMfUfX38DvKiw0Fl5qHBVa1+bjxUF64jvEn5SDEjUroZB+tIiMdJiHKkBA z2iLlFU/U3u/W3XubLI3TO8rsFUZlW+WDD6zjBoZhLp5D1fZ0aRK7vEgjqQBHBD3U/HC pWlQ== X-Gm-Message-State: AC+VfDyvhKNN1aOdIdh0a87E4mF30cC7bLplY0Qoyo6q9XrRs4Tlo7Aq T6JyShmKvWErGN1chb7gLrUy04W3+Ky6e+N+ziM= X-Google-Smtp-Source: ACHHUZ6oRkCBuKitWtr+YCRSGp9ysmPmLyTTT1bcWHxvfFiGGjF5uN9o16P7Y6dBPoCKqFqFuhFPzg== X-Received: by 2002:a05:6a00:1ad0:b0:64d:7314:6596 with SMTP id f16-20020a056a001ad000b0064d73146596mr872287pfv.27.1684886308748; Tue, 23 May 2023 16:58:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 27/28] tcg: Remove DEBUG_DISAS Date: Tue, 23 May 2023 16:58:03 -0700 Message-Id: <20230523235804.747803-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886589479100003 This had been set since the beginning, is never undefined, and it would seem to be harmful to debugging to do so. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 3 --- accel/tcg/cpu-exec.c | 2 -- accel/tcg/translate-all.c | 2 -- accel/tcg/translator.c | 2 -- target/sh4/translate.c | 2 -- target/sparc/translate.c | 2 -- tcg/tcg.c | 9 +-------- 7 files changed, 1 insertion(+), 21 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index ecded1f112..4d2b151986 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -27,9 +27,6 @@ #include "qemu/interval-tree.h" #include "qemu/clang-tsa.h" =20 -/* allow to see translation results - the slowdown should be negligible, s= o we leave it */ -#define DEBUG_DISAS - /* Page tracking code uses ram addresses in system mode, and virtual addresses in userspace mode. Define tb_page_addr_t to be an appropriate type. */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index bc0e1c3299..0e741960da 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -307,7 +307,6 @@ static void log_cpu_exec(target_ulong pc, CPUState *cpu, cpu->cpu_index, tb->tc.ptr, tb->cs_base, pc, tb->flags, tb->cflags, lookup_symbol(pc)); =20 -#if defined(DEBUG_DISAS) if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { @@ -323,7 +322,6 @@ static void log_cpu_exec(target_ulong pc, CPUState *cpu, qemu_log_unlock(logfile); } } -#endif /* DEBUG_DISAS */ } } =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 353849ca6d..c87648b99e 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -432,7 +432,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu, qatomic_set(&prof->search_out_len, prof->search_out_len + search_size); #endif =20 -#ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) && qemu_log_in_addr_range(pc)) { FILE *logfile =3D qemu_log_trylock(); @@ -505,7 +504,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu, qemu_log_unlock(logfile); } } -#endif =20 qatomic_set(&tcg_ctx->code_gen_ptr, (void *) ROUND_UP((uintptr_t)gen_code_buf + gen_code_size + search_size, diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 7bda43ff61..6120ef2a92 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -122,7 +122,6 @@ void translator_loop(CPUState *cpu, TranslationBlock *t= b, int *max_insns, tb->size =3D db->pc_next - db->pc_first; tb->icount =3D db->num_insns; =20 -#ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && qemu_log_in_addr_range(db->pc_first)) { FILE *logfile =3D qemu_log_trylock(); @@ -133,7 +132,6 @@ void translator_loop(CPUState *cpu, TranslationBlock *t= b, int *max_insns, qemu_log_unlock(logfile); } } -#endif } =20 static void *translator_access(CPUArchState *env, DisasContextBase *db, diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 0dedbb8210..d9accfa1e7 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -17,8 +17,6 @@ * License along with this library; if not, see . */ =20 -#define DEBUG_DISAS - #include "qemu/osdep.h" #include "cpu.h" #include "disas/disas.h" diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 414e014b11..9377798490 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -34,8 +34,6 @@ #include "asi.h" =20 =20 -#define DEBUG_DISAS - #define DYNAMIC_PC 1 /* dynamic pc value */ #define JUMP_PC 2 /* dynamic pc value which takes only two values according to jump_pc[T2] */ diff --git a/tcg/tcg.c b/tcg/tcg.c index 0b0fe9c7ad..bfe3d80fc2 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1451,7 +1451,6 @@ void tcg_prologue_init(TCGContext *s) (uintptr_t)s->code_buf, prologue_size); #endif =20 -#ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { @@ -1483,7 +1482,6 @@ void tcg_prologue_init(TCGContext *s) qemu_log_unlock(logfile); } } -#endif =20 #ifndef CONFIG_TCG_INTERPRETER /* @@ -5998,7 +5996,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= uint64_t pc_start) } #endif =20 -#ifdef DEBUG_DISAS if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP) && qemu_log_in_addr_range(pc_start))) { FILE *logfile =3D qemu_log_trylock(); @@ -6009,7 +6006,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= uint64_t pc_start) qemu_log_unlock(logfile); } } -#endif =20 #ifdef CONFIG_DEBUG_TCG /* Ensure all labels referenced have been emitted. */ @@ -6046,7 +6042,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= uint64_t pc_start) liveness_pass_1(s); =20 if (s->nb_indirects > 0) { -#ifdef DEBUG_DISAS if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND) && qemu_log_in_addr_range(pc_start))) { FILE *logfile =3D qemu_log_trylock(); @@ -6057,7 +6052,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= uint64_t pc_start) qemu_log_unlock(logfile); } } -#endif + /* Replace indirect temps with direct temps. */ if (liveness_pass_2(s)) { /* If changes were made, re-run liveness. */ @@ -6069,7 +6064,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= uint64_t pc_start) qatomic_set(&prof->la_time, prof->la_time + profile_getclock()); #endif =20 -#ifdef DEBUG_DISAS if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT) && qemu_log_in_addr_range(pc_start))) { FILE *logfile =3D qemu_log_trylock(); @@ -6080,7 +6074,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= uint64_t pc_start) qemu_log_unlock(logfile); } } -#endif =20 /* Initialize goto_tb jump offsets. */ tb->jmp_reset_offset[0] =3D TB_JMP_OFFSET_INVALID; --=20 2.34.1 From nobody Sat May 18 04:46:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684886858; cv=none; d=zohomail.com; s=zohoarc; b=nyOn0tO/5fYdI2qjtBR2MssNQUGhmbwp4YsL8ZijVXtUTAwCrNj7LlqlLePDMUss1xAqOqHzEj9a+cOERJ4T9cA+qK9biAAo/bV1NI20BYCB8nKvflMQqSX0MP7nDcq76X1PC+CefrZtmjWNTv0cf9QcjnAosidjxFcZUEQxSsU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684886858; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id p18-20020aa78612000000b0063b7c42a070sm6285041pfn.68.2023.05.23.16.58.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 16:58:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684886309; x=1687478309; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L4mMrlEHq00cb2PmywQti2UecytZbzZJsKcDPhsh4e0=; b=aTd3cqqmbuKPkJisJ7nATYUhtxQKQDXyqH9olGshhln1MybDRBww4DI9dANiE7qdZ/ ZhBb7B+v5WOlkgGS9VqYDkpyq1gS0gYhINkO1K0fhC3/Z7ZovXAd7N/B04ChlVXWZTv5 GaWX4yxDzEjWT46akjZPWlXxDiv1XlUZQwwUUtV/+OII756l6ZErb5gIkouQ1RdfmWRY 0RxBKv2WL5gwzfMQH/KNE0R5ZCXXOwfa+vLFjXdc0xantWImFHWmoP9zoSVX5x5jDFck fquAWHfJCcx8SCxLUYEGfZroB/6TejVlvjfsNWlvd8bYfpm0Qh8Fmxeip3Fb4+wSIUP4 g12w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684886309; x=1687478309; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L4mMrlEHq00cb2PmywQti2UecytZbzZJsKcDPhsh4e0=; b=M6AvOHN0+jOU9l1HgOhU9uM1TN4GL8ieegksWrvaJDlgrsZ/yiSBYWURo25erX9nuu S/5LcR1WL3P6DfJ4R1PxwX8+9WnMOxWY5rIBJ7WnTFswM9dNza366pnAaxvFgA5fNAso XWDMvpG+8wPLJdOeCN9seyMW/XfmXE84c9eerwfEWZJAl5jcObZTyJTVFxJiKSK2hl6Z eCHX5blp7yc3ldZAEZshXokLv/Ll296SPRLxfz0xe8UWRJhrhjZ0dnGqM8TFsIF8yXmN lvI5Tp0kGU+ZLQwUiK6ykT+jN16LeQ8b2/owzWIaZnUqIuLSjRqp8btp3TlWKi5kPafZ zdqg== X-Gm-Message-State: AC+VfDzJ2OOz7ZxZuROhn1euu0M2CIwv87IiHS8a5T2NbeklIhPIbzzC 8brlCQ0rgg1X6KvZK2yy5elfNYfEbhrpnuKVs6M= X-Google-Smtp-Source: ACHHUZ4ChEc85q0fUX+K3/+wD11wro7u2u7YJC50p2+EgCN8FV94DvsdRP2qXLhauj1+KAy2kb6cfg== X-Received: by 2002:a05:6a21:9985:b0:106:4197:b7ff with SMTP id ve5-20020a056a21998500b001064197b7ffmr16757035pzb.30.1684886309602; Tue, 23 May 2023 16:58:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 28/28] tcg: Remove USE_TCG_OPTIMIZATIONS Date: Tue, 23 May 2023 16:58:04 -0700 Message-Id: <20230523235804.747803-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523235804.747803-1-richard.henderson@linaro.org> References: <20230523235804.747803-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684886860816100007 This is always defined, and the optimization pass is essential to producing reasonable code. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tcg.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index bfe3d80fc2..ac30d484f5 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -22,9 +22,6 @@ * THE SOFTWARE. */ =20 -/* define it to use liveness analysis (better code) */ -#define USE_TCG_OPTIMIZATIONS - #include "qemu/osdep.h" =20 /* Define to jump the ELF file used to communicate with GDB. */ @@ -6028,9 +6025,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= uint64_t pc_start) qatomic_set(&prof->opt_time, prof->opt_time - profile_getclock()); #endif =20 -#ifdef USE_TCG_OPTIMIZATIONS tcg_optimize(s); -#endif =20 #ifdef CONFIG_PROFILER qatomic_set(&prof->opt_time, prof->opt_time + profile_getclock()); --=20 2.34.1