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Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index d4269dffcf..30372519dd 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2033,6 +2033,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, bool is_ld) { + TCGType addr_type =3D s->addr_type; TCGLabelQemuLdst *ldst =3D NULL; MemOp opc =3D get_memop(oi); MemOp a_bits; @@ -2085,17 +2086,18 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0)); =20 /* Load the (low part) TLB comparator into TMP2. */ - if (cmp_off =3D=3D 0 && TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { - uint32_t lxu =3D (TCG_TARGET_REG_BITS =3D=3D 32 || TARGET_LONG_BIT= S =3D=3D 32 + if (cmp_off =3D=3D 0 + && (TCG_TARGET_REG_BITS =3D=3D 64 || addr_type =3D=3D TCG_TYPE_I32= )) { + uint32_t lxu =3D (TCG_TARGET_REG_BITS =3D=3D 32 || addr_type =3D= =3D TCG_TYPE_I32 ? LWZUX : LDUX); tcg_out32(s, lxu | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2)); } else { tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2)); - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS =3D=3D 32 && addr_type !=3D TCG_TYPE_I32) { tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off + 4 * HOST_BIG_ENDIAN); } else { - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off= ); + tcg_out_ld(s, addr_type, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off); } } =20 @@ -2103,7 +2105,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, * Load the TLB addend for use on the fast path. * Do this asap to minimize any load use delay. */ - if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS =3D=3D 64 || addr_type =3D=3D TCG_TYPE_I32) { tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, offsetof(CPUTLBEntry, addend)); } @@ -2138,7 +2140,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, } =20 /* Mask the address for the requested alignment. */ - if (TARGET_LONG_BITS =3D=3D 32) { + if (addr_type =3D=3D TCG_TYPE_I32) { tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, (32 - a_bits) & 31, 31 - s->page_bits); } else if (a_bits =3D=3D 0) { @@ -2150,7 +2152,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, } } =20 - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS =3D=3D 32 && addr_type !=3D TCG_TYPE_I32) { /* Low part comparison into cr7. */ tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 0, 7, TCG_TYPE_I32); @@ -2170,8 +2172,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); } else { /* Full comparison into cr7. */ - tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, - 0, 7, TCG_TYPE_TL); + tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 0, 7, addr_t= ype); } =20 /* Load a pointer into the current opcode w/conditional branch-link. */ @@ -2198,7 +2199,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, h->base =3D guest_base ? TCG_GUEST_BASE_REG : 0; #endif =20 - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS =3D=3D 64 && addr_type =3D=3D TCG_TYPE_I32) { /* Zero-extend the guest address for use in the host address. */ tcg_out_ext32u(s, TCG_REG_R0, addrlo); h->index =3D TCG_REG_R0; --=20 2.34.1 From nobody Sat May 18 06:50:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851194; cv=none; d=zohomail.com; s=zohoarc; b=kmb4S6JCz8VRI4QOa5w142tttPaArwHl+zHw5lNsYdVvaylA46zXbmMaSNR1FoMhEbqZ9LZhj4+fcD6YyAtoGeX9XVg585U3bBAHsgk6VMPlgWAjNhJw5mo1ugIoXguXsnfhhJlGv09wJqKZTbxXVWUh674hh0UymRRyNdIomPE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851194; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0B6ZiccHfjA9+3V6I3lMmu3S/Ef9HuPrl6mcYOHXodE=; b=PksOpp/ZY+cuQCY5s38BE11hJM4iLZkrcd1uTVkC/PQeFzBk9XgAS1aVT7PksIeN7noq6M6ff6KJ+sul0Q6XBRYMFGVF2LcpR6K5ZtzoaUrRNcXg7zbQ05Y7Dn+TuFCB60vozT3jNpRSB803wTJ8o0iyqrVivoNfj90zVU/tvYE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684851194779274.744227041267; Tue, 23 May 2023 07:13:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SSi-0005He-FL; Tue, 23 May 2023 09:54:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSH-0004bY-TX for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:39 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SS7-0002zu-IM for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:36 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-64d577071a6so3557887b3a.1 for ; Tue, 23 May 2023 06:53:27 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850006; x=1687442006; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0B6ZiccHfjA9+3V6I3lMmu3S/Ef9HuPrl6mcYOHXodE=; b=x4HTLSoqRgazApQT252BV9W4VbPWh4fLVYMlkxXXuzWRsPUVxVsNhBOZsIDR/39wd/ lgAhhoAN8LLUn39XxhEI/wJi1FPhBoXR8FEjdChwYthZWt1huLzmk3Y/CUaO4tRAammU Iw8ijHkRWs4pm5sSSvgy3X9phoYG2ldNMD6edoAG4pBHfKxseNmeN2AzTJxAsZHgsMId RBxc7l7bEDdSIDQtbJ9VGW6669shAEQDV12QumQcY1zBtcaxEy/V5wDbOmywwY7M0WO4 KHlNHQZYjs+tWBC9Zoqx7tv1NZk3wfcwUMp1F1rHhJZZGGyasFK1WZCTIXyWGFQBsqf+ Hesw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850006; x=1687442006; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0B6ZiccHfjA9+3V6I3lMmu3S/Ef9HuPrl6mcYOHXodE=; b=So+joKc7LlCVCsUG7l3MjED7A75hVule6ZKzZXAj2ZoiTBZNeldHVoY1EIW4PCpZEr Xuz2T+9xhVW1J2OiZSc4jh8h8ZA0xBiF4eMbFKmRkG4caQuKOeWuy86cOIMzRqMxbZTD FzJdrYphmNHd4znNW4JOG544EjFK2lxdPXsj/GHTrZgzBueHxIpDIyEUmCPnqCk+IZJA zYqlnVr4T/zaqkFbM1fgWDGh28cvxWRLd+x3nrXa6rolGNNyjJUAm8Ubyoq35S+wKNkH 44XFIW9oQj+YVQSJBy+wbPm5rY4BvJA5m84RJ1xvrchRpZqrV9aykx8SgETJfV5EhhzO MMmQ== X-Gm-Message-State: AC+VfDyjFyPJd+DTMmpOhjlYBbkrQQbHX7yGc1I1NmcWTjBrv7xmdiCO Ykbx5IAMaQGmmEgKKlpdpAF8/XSDk4Wf1C7wGyw= X-Google-Smtp-Source: ACHHUZ5ya2ugQvs28eApBbrSuwzANS8OhNe/qisc9UPBAiUmbcqmdbscaSw/ZXnQgpx1Rtr0ltuIXQ== X-Received: by 2002:a05:6a20:a111:b0:10c:3535:162f with SMTP id q17-20020a056a20a11100b0010c3535162fmr4770325pzk.0.1684850005799; Tue, 23 May 2023 06:53:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 02/52] tcg/riscv: Remove TARGET_LONG_BITS, TCG_TYPE_TL Date: Tue, 23 May 2023 06:52:32 -0700 Message-Id: <20230523135322.678948-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851196536100001 Content-Type: text/plain; charset="utf-8" All uses replaced with TCGContext.addr_type. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index ff6334980f..45bd09cfc4 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -908,6 +908,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *= s, TCGReg *pbase, TCGReg addr_reg, MemOpIdx oi, bool is_ld) { + TCGType addr_type =3D s->addr_type; TCGLabelQemuLdst *ldst =3D NULL; MemOp opc =3D get_memop(oi); TCGAtomAlign aa; @@ -949,19 +950,19 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, TCGReg *pbase, addr_adj =3D addr_reg; if (a_mask < s_mask) { addr_adj =3D TCG_REG_TMP0; - tcg_out_opc_imm(s, TARGET_LONG_BITS =3D=3D 32 ? OPC_ADDIW : OPC_AD= DI, + tcg_out_opc_imm(s, addr_type =3D=3D TCG_TYPE_I32 ? OPC_ADDIW : OPC= _ADDI, addr_adj, addr_reg, s_mask - a_mask); } compare_mask =3D s->page_mask | a_mask; if (compare_mask =3D=3D sextreg(compare_mask, 0, 12)) { tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_adj, compare_mask); } else { - tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); + tcg_out_movi(s, addr_type, TCG_REG_TMP1, compare_mask); tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr_adj); } =20 /* Load the tlb comparator and the addend. */ - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, + tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, is_ld ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, @@ -973,7 +974,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *= s, TCGReg *pbase, =20 /* TLB Hit - translate address using addend. */ addr_adj =3D addr_reg; - if (TARGET_LONG_BITS =3D=3D 32) { + if (addr_type =3D=3D TCG_TYPE_I32) { addr_adj =3D TCG_REG_TMP0; tcg_out_ext32u(s, addr_adj, addr_reg); } @@ -995,7 +996,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *= s, TCGReg *pbase, } =20 TCGReg base =3D addr_reg; - if (TARGET_LONG_BITS =3D=3D 32) { + if (addr_type =3D=3D TCG_TYPE_I32) { tcg_out_ext32u(s, TCG_REG_TMP0, base); base =3D TCG_REG_TMP0; } --=20 2.34.1 From nobody Sat May 18 06:50:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684852890; cv=none; d=zohomail.com; s=zohoarc; b=ndoku33dgm66IAdLdU766uo3+WZ/qd0s/SdmsCzMJRqkbR72h6gh4by2f/X+grBPElu2z9lpc/oJks8TnmtgTGgDvsTFBUnzHCJvwtgJ///iT4d7lARJk+ydPyUj5tynYUji1ZAlFAxTtJMEEgppd+XNnQ7OLHudFCqsblZfq7k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684852890; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=x1u0vvNyx/nixXkB/+OG1xn3VbW+Qfvhi9OOeTFIibc=; b=P6nmLtw1EpHlXpppAaC9nOtw+OSMxCqeOCrYh9W4eD36HPPCjblCaJt5aRgThmMx8JV4E7rqcVViDit/alpPVeGh1XdTKj2lUmtjI/hGD0tzD8qWbwXtxOFGBAn2Lwwa1X0P84q8HK5hYELmpz82rLx78Si05oZvzh+1DkbHlm0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684852890714140.03030715108696; Tue, 23 May 2023 07:41:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SSE-0004Kl-00; Tue, 23 May 2023 09:53:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSC-00044n-6j for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:32 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SS7-0002zz-Qp for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:31 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-64d2a613ec4so3895245b3a.1 for ; Tue, 23 May 2023 06:53:27 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850006; x=1687442006; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=x1u0vvNyx/nixXkB/+OG1xn3VbW+Qfvhi9OOeTFIibc=; b=Xwj7FUcxgm6kTvSx3PKeNTZLy/5isLiwg3ZsMRgo8UpKPtoTEB2wrQEVD3G5hKJ32M E2kdNBmMsoQLBC5+91672w3sNX6X/vKUWQB2y/O3xUY7dO5qPaGvhLiuHdgaDTdDxaOI 5CFGy7+uPXFBIe8lZBrPOPVlNGIXI9ryroStiDwgGIncJbrfivJYff59sHjLZvztUQMR uXVzLH+ew2ZnAUdQXO2VWMNfaZLfUOgEiCAbEM8MR81g5IP/KdA5a7M8UME2pV+ujFXU fgXspuk25CHa3Pvhl1+tSweUFGJh8ek2K85umYBzRtwgQ1rNklkrqNTh19DKRnd8YTci +pgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850006; x=1687442006; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x1u0vvNyx/nixXkB/+OG1xn3VbW+Qfvhi9OOeTFIibc=; b=ZlFzSThD/q+3yZCpLwZgxCM3PmVNclJ5ryRNlQs/HtIiMnCeRUUKYz9aJu7J3LfvCg Acw0ARQKD0vNWiheerPozaTBt+dj8KMJ5byjh8pWcVq5nqRl6SLtM8lkQtnFrZXn3DIZ vXDMNHuhw1gb1DRAki0kFUkoc9GCvGMObZVl1VGzPudNss4X7yAWln/1Bc3UMVYaqQ3f mSxe+nsKWBLGxOlEh8bL/WOesiwNS0DK2Bsvq/TdV1CY96Pe/9ABfdfuCUW471WOzdIO K2QyPG3cI4TAmHiEVYdv83HHkYLMH/i8m1V60PSmK/WsQSlxz9l85ZtkW1kWQix8i7wH XLkw== X-Gm-Message-State: AC+VfDwgshVPfuN95xAGRW0s7TdIBeNHLSNpO0sJUGEh9+Yn9LisPKtC 8JKDiJNuwIvyQRSt38IAXwbiJ6NZ4assi6oTssA= X-Google-Smtp-Source: ACHHUZ5c4/JpOUaH5yTO2yQV0hg/CYhOkK/9rPoLJ8SuI605+SUHOa3PlAjJSu4Vnki3RIM4GuhJog== X-Received: by 2002:a05:6a00:2314:b0:63b:5c82:e209 with SMTP id h20-20020a056a00231400b0063b5c82e209mr17048468pfh.10.1684850006555; Tue, 23 May 2023 06:53:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 03/52] tcg/s390x: Remove TARGET_LONG_BITS, TCG_TYPE_TL Date: Tue, 23 May 2023 06:52:33 -0700 Message-Id: <20230523135322.678948-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684852895933100001 Content-Type: text/plain; charset="utf-8" All uses replaced with TCGContext.addr_type. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index dfaa34c264..c32801b829 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1732,6 +1732,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, TCGReg addr_reg, MemOpIdx oi, bool is_ld) { + TCGType addr_type =3D s->addr_type; TCGLabelQemuLdst *ldst =3D NULL; MemOp opc =3D get_memop(oi); unsigned a_mask; @@ -1773,7 +1774,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); } else { tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off); - tgen_andi(s, TCG_TYPE_TL, TCG_REG_R0, tlb_mask); + tgen_andi(s, addr_type, TCG_REG_R0, tlb_mask); } =20 if (is_ld) { @@ -1781,7 +1782,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, } else { ofs =3D offsetof(CPUTLBEntry, addr_write); } - if (TARGET_LONG_BITS =3D=3D 32) { + if (addr_type =3D=3D TCG_TYPE_I32) { tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); } else { tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); @@ -1794,7 +1795,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE, offsetof(CPUTLBEntry, addend)); =20 - if (TARGET_LONG_BITS =3D=3D 32) { + if (addr_type =3D=3D TCG_TYPE_I32) { tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg); h->base =3D TCG_REG_NONE; } else { @@ -1817,7 +1818,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, } =20 h->base =3D addr_reg; - if (TARGET_LONG_BITS =3D=3D 32) { + if (addr_type =3D=3D TCG_TYPE_I32) { tcg_out_ext32u(s, TCG_TMP0, addr_reg); h->base =3D TCG_TMP0; } --=20 2.34.1 From nobody Sat May 18 06:50:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684853111; cv=none; d=zohomail.com; s=zohoarc; b=L/hbMf5q+ZydJ7i/aU6wkE46t4XW2/wdn8TyEtipP1DRtCPH3kFoTrbw/Lu+5+oaxsoTptcfKca+X1GmT7TBB9w4qZPTg+WhC1hCJp30GbpB4HlPe+M9Lli193FEUoiwFZ2e/ZL3b7ZWk0vtyfNpWoXpGVk+fXImaopAWYbrs38= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684853111; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wZqbKGvvBLnxdV8hORtypSTdUMPJNxpFAqcst10iFXc=; b=lRoG2153Dcmkgqj8bteTzDetpBbRHEb6bENMMRmSZcQUveyeqnXle3+D0uY0B+IdE3rO6sopL8IscOvIFGwWmezs1QXFViuRiuM7p1yyXz8yH39Lb16N0eAgfiyEefVWyMqwgCqz3EHrKbvbQt6Wkyy3YKdvWcdedoLIzi10QC8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684853111524868.8057790793935; Tue, 23 May 2023 07:45:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SSK-0004ad-Fx; Tue, 23 May 2023 09:53:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSD-0004Ig-Ev for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:33 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SS9-00030F-GG for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:33 -0400 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-64d2467d640so6480913b3a.1 for ; Tue, 23 May 2023 06:53:28 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850007; x=1687442007; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wZqbKGvvBLnxdV8hORtypSTdUMPJNxpFAqcst10iFXc=; b=COHHOmsaIjZG39q6zg74Ktlio7u+mEC2PrH+PgR7ot9+JLiiDzjMv8q6SCfSSdTb5x 5YaSWiq5MBqUMHk4pr2iB7zz65lB65hvtEHl2gzgMw7zFk1sFPyrzUkVobpEtc5u77VK bYJ4foGJ4g9wWkuHzfgTJ6JYD/8wGXf5ro3uG7DPQzd0mXyu4EKrjosm1Wt4UmckdhO5 qSzR1Olht9HcUw1Fx5mhOtAfTenYaEuv8RyhdsdLAX9uOaAy5ah4BCflTa0YxO31sG7y EwFlwSpJJHWngcOKQQG54UtUB3G575VpWEZewZvE29WndwYIWL9CaeBxv4H7CnDhXR1p XgPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850007; x=1687442007; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wZqbKGvvBLnxdV8hORtypSTdUMPJNxpFAqcst10iFXc=; b=RtLzocZEWQYfF5uoklUmz1TmAmoUB+MwrIdb5fJbZu29HDw/2O397EE7zp53kHS2+J mgKbfPMvHU5YouWjbp6RTZMuqTa+X3xToGIz8QlJaOeL1my9KKEUElNJEj/aZWznpTT7 +hhHZFamhyn1jE+LT5/H4LC3Bxr5p9Tq1AYfHvfLkhj62i1jK6iHDWqdXXRbslpXm6j3 vtQYbeRnxcuynXrnH5kazrJjb4PY00tiVuXiJflcTn/sHVLGaZPCtP7e/Rd63rjYeepl 8bdC4P23mMtskUTZ2Ot5SzAqd/wfVprsOphRzMomHYo2aQwBN14zz5qZF2ohTaHpWGZn 44Nw== X-Gm-Message-State: AC+VfDyElhuYoISZuPAGGo4j5+7BM/m2Q7qupF7wuo/ilH/XqI+1H/9D TRpHkt/4CBWzAaL1e4+aPunf6/fO4gj5KT/I3yI= X-Google-Smtp-Source: ACHHUZ4hF8OuZRDSyRqz+GNENDqvO3WzaNe0TQ/l/FVcHx3mfPG41VvYFw7F5ZR2ngIJvfnJJLKTGw== X-Received: by 2002:a05:6a20:e68e:b0:104:41a0:c51a with SMTP id mz14-20020a056a20e68e00b0010441a0c51amr13121910pzb.38.1684850007323; Tue, 23 May 2023 06:53:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 04/52] tcg/sparc64: Remove TARGET_LONG_BITS, TCG_TYPE_TL Date: Tue, 23 May 2023 06:52:34 -0700 Message-Id: <20230523135322.678948-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684853111843100001 Content-Type: text/plain; charset="utf-8" All uses replaced with TCGContext.addr_type. Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index d2d0f604c2..48efd83817 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1027,6 +1027,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, TCGReg addr_reg, MemOpIdx oi, bool is_ld) { + TCGType addr_type =3D s->addr_type; TCGLabelQemuLdst *ldst =3D NULL; MemOp opc =3D get_memop(oi); MemOp s_bits =3D opc & MO_SIZE; @@ -1063,7 +1064,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T3, ARITH_ADD); =20 /* Load the tlb comparator and the addend. */ - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_T2, TCG_REG_T1, cmp_off); + tcg_out_ld(s, addr_type, TCG_REG_T2, TCG_REG_T1, cmp_off); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T1, TCG_REG_T1, add_off); h->base =3D TCG_REG_T1; =20 @@ -1084,7 +1085,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, ldst->label_ptr[0] =3D s->code_ptr; =20 /* bne,pn %[xi]cc, label0 */ - cc =3D TARGET_LONG_BITS =3D=3D 64 ? BPCC_XCC : BPCC_ICC; + cc =3D addr_type =3D=3D TCG_TYPE_I32 ? BPCC_ICC : BPCC_XCC; tcg_out_bpcc0(s, COND_NE, BPCC_PN | cc, 0); #else /* @@ -1110,7 +1111,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, #endif =20 /* If the guest address must be zero-extended, do in the delay slot. = */ - if (TARGET_LONG_BITS =3D=3D 32) { + if (addr_type =3D=3D TCG_TYPE_I32) { tcg_out_ext32u(s, TCG_REG_T2, addr_reg); h->index =3D TCG_REG_T2; } else { --=20 2.34.1 From nobody Sat May 18 06:50:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684853013; cv=none; d=zohomail.com; s=zohoarc; b=XEYxap2NjquHsa+pZu7wHy6xh+56Nt5AYfsY+h+3DpRieB2dZmS8cTqaHVF02ZHmwDOOl9n6VvwuEgeZ7L954utkRhdf0v5WHoirob+MJSZcDhSBKTzU7/DJSF5I5Fydp074dLtN8kHHNesXc3HBnHK+Lso/7/WGnfpFnv/82KA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684853013; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JleiEIiAEVnFwHzXeO5KaAmEINtpDRuqpeezDa9tVZU=; b=SL/n4LIw4oBiQyIM+80g3y9jtLEhyqnXmzCV0uTJ74FKAWW3lLJUq0/6LB0TYLvoGsHpCRAXklyb/E52AaZ9LaGv7qhiF+ysjmgMIi6QYEkSuH+fI+IKAUpusczHSUjS4ymyddGPRvjYTKb+LUM+VemAuLROWSy6OAKxb7noPng= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684853013290122.80722676184382; Tue, 23 May 2023 07:43:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SSF-0004Uc-EV; Tue, 23 May 2023 09:53:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSD-0004Jp-K4 for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:33 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SS9-00030S-Ge for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:33 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-64d44b198baso2524804b3a.0 for ; Tue, 23 May 2023 06:53:29 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850008; x=1687442008; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=JleiEIiAEVnFwHzXeO5KaAmEINtpDRuqpeezDa9tVZU=; b=aktuA5gFantLty1uJf/q4pcXr/jc+RddMoyHRq+0orF7N0BYUTyK/4BEkcGmVon1Rm nmHgCZGAVaL8uHtQCOCOFFVrjrzsJQ3gREiqSd1RHhr6kTlcroNghWYUcsGDL30+Z3kV nuzM1c6VxQv0n8DBqDZz90b3DQ7yLsEiy+9KiWjkmios2S/uo4NG4IHA4xLxXWLMz1dZ 4B94iS/wXjaL1cEaxDNgdxjc3S4wj+BWuNz29uQ6MMSvrPKrdcPHmGphEzPcOFysRp8h PHnO+fqLhc1y8e4bzdLC1F0UBrKwbBZn8dkmDBt00OpVDtlcPQNGH7Am+1aT++//C+w4 qIwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850008; x=1687442008; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JleiEIiAEVnFwHzXeO5KaAmEINtpDRuqpeezDa9tVZU=; b=FKFz2MOBQTFb5PKEigKCbUftLSgSusz0jLaLcT667H0fzEfNQZaKSyzEKFNqa7uuO4 wFe+H8O2WtKjJKi1tnqsK2JfiNsee3op9wI9O6mheHSza5TWqumzDJsqKHPCIyanXlvt T0sovgL7lqxktPozaRDszeka7kLVyTc43MEAlZu48uFLwWn91btyjqWxgwNw2mK7h2vk BGkzVl3I8Go9+mbSXnJqoxlU7GKVYzJQOBnx1MjFXOlosW47hGnGtAJ+BS/iHlKobhQ9 ou7HeeDugkx+WOYzVUZqoCpS3PIAdI5vo98LLI1oorGXaRF0J/v8/ah+72gfVkbmJol/ z9Aw== X-Gm-Message-State: AC+VfDw1/x+2HW6ZOD2kQODOPUkGw9QCgCROFHQehjCzVFYf5d2L7YTL xA8Rgi8/Nlnmg6JdkMqmoimqeNh3Qrtczd1Xh78= X-Google-Smtp-Source: ACHHUZ5IiNPqPIr87C8UM0aCXElsYcwrnyboOl22ySev0WEb0vFfG65YGXPD4fImVpm3WJyYmZzI3Q== X-Received: by 2002:a05:6a00:2e15:b0:645:834c:f521 with SMTP id fc21-20020a056a002e1500b00645834cf521mr22559640pfb.17.1684850008064; Tue, 23 May 2023 06:53:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 05/52] tcg: Move TCG_TYPE_TL from tcg.h to tcg-op.h Date: Tue, 23 May 2023 06:52:35 -0700 Message-Id: <20230523135322.678948-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684853014754100001 Content-Type: text/plain; charset="utf-8" Removes the only use of TARGET_LONG_BITS from tcg.h, which is to be target independent. Move the symbol to a define in tcg-op.h, which will continue to be target dependent. Rather than complicate matters for the use in tb_gen_code(), expand the definition there. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/tcg/tcg-op.h | 8 ++++++++ include/tcg/tcg.h | 7 ------- accel/tcg/translate-all.c | 2 +- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 35c5700183..844c666374 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -722,6 +722,14 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 ret, = TCGv_i64 lo, TCGv_i64 hi) #error must include QEMU headers #endif =20 +#if TARGET_LONG_BITS =3D=3D 32 +# define TCG_TYPE_TL TCG_TYPE_I32 +#elif TARGET_LONG_BITS =3D=3D 64 +# define TCG_TYPE_TL TCG_TYPE_I64 +#else +# error +#endif + #if TARGET_INSN_START_WORDS =3D=3D 1 static inline void tcg_gen_insn_start(target_ulong pc) { diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 072c35f7f5..0da17f1b4f 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -292,13 +292,6 @@ typedef enum TCGType { #else TCG_TYPE_PTR =3D TCG_TYPE_I64, #endif - - /* An alias for the size of the target "long", aka register. */ -#if TARGET_LONG_BITS =3D=3D 64 - TCG_TYPE_TL =3D TCG_TYPE_I64, -#else - TCG_TYPE_TL =3D TCG_TYPE_I32, -#endif } TCGType; =20 /** diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 353849ca6d..f6c8ad1a18 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -356,7 +356,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb_set_page_addr0(tb, phys_pc); tb_set_page_addr1(tb, -1); tcg_ctx->gen_tb =3D tb; - tcg_ctx->addr_type =3D TCG_TYPE_TL; + tcg_ctx->addr_type =3D TARGET_LONG_BITS =3D=3D 32 ? TCG_TYPE_I32 : TCG= _TYPE_I64; #ifdef CONFIG_SOFTMMU tcg_ctx->page_bits =3D TARGET_PAGE_BITS; tcg_ctx->page_mask =3D TARGET_PAGE_MASK; --=20 2.34.1 From nobody Sat May 18 06:50:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851238; cv=none; d=zohomail.com; s=zohoarc; b=b7wT99OvaA7dYGOEb1Tmas7j5NMuRnLPE3dq1Y5+2t5We+Ta5S2LA0YnmEMYOsLSYgOAHVxU4j4yE0q+zrGxwB/nqnE0eD4dvVIjhF/GI9QSQGrz7iegM1ii9X5qQcoIShtBl8cUaW9A02jcjmrI3zoxuAvBlMVVQ4UCK/deIws= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851238; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HxoP9990OHDYwNOE0anIjEZqeR9eEOPQW77YwWr1n2g=; b=OncU3YomriSTNdb+raSCDK3Y27pZ+IAiHL9JKp2yIHPAXaCDktsrCT5HHAtUnj+q1q8yfuVyw7j9MyIaqdqrN6nEzk3j4rixuXHUadYoiuKYe654R7B09/Yr4WoaP90rifqvJcMe5064UsQojqN8yFLu2T2qoPzvtXJVb5FoAfg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684851238063927.5146575055267; Tue, 23 May 2023 07:13:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SSy-000667-5x; Tue, 23 May 2023 09:54:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSE-0004Nt-7F for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:34 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSA-00030g-DI for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:33 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-64d2b42a8f9so4267584b3a.3 for ; Tue, 23 May 2023 06:53:29 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850009; x=1687442009; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=HxoP9990OHDYwNOE0anIjEZqeR9eEOPQW77YwWr1n2g=; b=CiVjx6Bvt1MQL6FvqAXZW3RFOJboT0fws4N9DOVUWfkU9urFNk4kFwnrFL4QQ90/i7 VcB/MFFMlvZM/mhzgNePOzKhs1YKHnT/+x73fqf5T84aVQWPUjCMS2bPdWVFblKZ85v3 7N765LYgw2Q5I5fgUX82tmoeDsa/YsR6NwmcCBcWXi3HDqndpk3mI/IRo0xqNnqcJ5r7 CFwLYDcnRSsddRdrI29PYvnEj+xRdLnK1ieC3f1PFoFDqxFfvywnEcyYWr0QrlFZJW7g k8lmKg3x732CLq75+bRl/uZc1WVpQ1tvpvSSD8WO47PlfXQkVArn8DIiTmhW0QGV3NCy cy8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850009; x=1687442009; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HxoP9990OHDYwNOE0anIjEZqeR9eEOPQW77YwWr1n2g=; b=TWJbQs2BeF6amGEiBR4RDGH9Vl9YGbluqe+gDZPHsWlcl0pZYkavPufJIeUG8hhbzQ MGNbTyKzi6Wr3qLwAaTMIzUA1CUlfp/7m4hT/QKlsSbieaagjO2w0ks8Fxl5SDRM8c3c z8LqByQx6pbnm8JzErGSPO90zHoDx99eHNuJKbWO0a/F161AiJ9UzRhtEc0MDKCPWFEO EMPTE8AwHGyqxsR+3GmpK/zZ9hYUBXdJlpxyxyjguB8uDGVX86m1A7f1Sip4huIQ5IPg LaKcuc+W8Os7tZMqGSQJtIJOoKUdln/o4BetDwmq9+rUCLBRoghYg1jQz+2mSFIzyg6D rb0Q== X-Gm-Message-State: AC+VfDxLgjXwgoQCdU23wzawp8P1dhhnjAMy4nj5l0BVaxCynsX0HPGx J/UY0fvonjuF9HZ8FS7NZ+WqdHnLV/ofxGcfFmY= X-Google-Smtp-Source: ACHHUZ4dV5GSDXk6dAffbHsu2/u2LW5up4/lds4tPq+2+yxY5Dr9UGw8b56Q6zH/qyI9oHrheb+OdA== X-Received: by 2002:a05:6a20:72a8:b0:10b:b166:8836 with SMTP id o40-20020a056a2072a800b0010bb1668836mr6772260pzk.47.1684850008864; Tue, 23 May 2023 06:53:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 06/52] tcg: Widen CPUTLBEntry comparators to 64-bits Date: Tue, 23 May 2023 06:52:36 -0700 Message-Id: <20230523135322.678948-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851238859100003 Content-Type: text/plain; charset="utf-8" This makes CPUTLBEntry agnostic to the address size of the guest. When 32-bit addresses are in effect, we can simply read the low 32 bits of the 64-bit field. Similarly when we need to update the field for setting TLB_NOTDIRTY. For TCG backends that could in theory be big-endian, but in practice are not (arm, loongarch, riscv), use QEMU_BUILD_BUG_ON to document and ensure this is not accidentally missed. For s390x, which is always big-endian, use HOST_BIG_ENDIAN anyway, to document the reason for the adjustment. For sparc64 and ppc64, always perform a 64-bit load, and rely on the following 32-bit comparison to ignore the high bits. Rearrange mips and ppc if ladders for clarity. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 37 +++++++++++--------------------- include/exec/cpu_ldst.h | 19 ++++++++++------ accel/tcg/cputlb.c | 8 +++++-- tcg/aarch64/tcg-target.c.inc | 1 + tcg/arm/tcg-target.c.inc | 1 + tcg/loongarch64/tcg-target.c.inc | 1 + tcg/mips/tcg-target.c.inc | 13 ++++++----- tcg/ppc/tcg-target.c.inc | 28 +++++++++++++----------- tcg/riscv/tcg-target.c.inc | 1 + tcg/s390x/tcg-target.c.inc | 1 + tcg/sparc64/tcg-target.c.inc | 8 +++++-- 11 files changed, 67 insertions(+), 51 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index a6e0cf1812..b757d37966 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -65,11 +65,7 @@ /* use a fully associative victim tlb of 8 entries */ #define CPU_VTLB_SIZE 8 =20 -#if HOST_LONG_BITS =3D=3D 32 && TARGET_LONG_BITS =3D=3D 32 -#define CPU_TLB_ENTRY_BITS 4 -#else #define CPU_TLB_ENTRY_BITS 5 -#endif =20 #define CPU_TLB_DYN_MIN_BITS 6 #define CPU_TLB_DYN_DEFAULT_BITS 8 @@ -95,33 +91,26 @@ # endif =20 /* Minimalized TLB entry for use by TCG fast path. */ -typedef struct CPUTLBEntry { - /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address - bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not - go directly to ram. - bit 3 : indicates that the entry is invalid - bit 2..0 : zero - */ - union { - struct { - target_ulong addr_read; - target_ulong addr_write; - target_ulong addr_code; - /* Addend to virtual address to get host address. IO accesses - use the corresponding iotlb value. */ - uintptr_t addend; - }; +typedef union CPUTLBEntry { + struct { + uint64_t addr_read; + uint64_t addr_write; + uint64_t addr_code; /* - * Padding to get a power of two size, as well as index - * access to addr_{read,write,code}. + * Addend to virtual address to get host address. IO accesses + * use the corresponding iotlb value. */ - target_ulong addr_idx[(1 << CPU_TLB_ENTRY_BITS) / TARGET_LONG_SIZE= ]; + uintptr_t addend; }; + /* + * Padding to get a power of two size, as well as index + * access to addr_{read,write,code}. + */ + uint64_t addr_idx[(1 << CPU_TLB_ENTRY_BITS) / sizeof(uint64_t)]; } CPUTLBEntry; =20 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) !=3D (1 << CPU_TLB_ENTRY_BITS)); =20 - #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ =20 #if !defined(CONFIG_USER_ONLY) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 5939688f69..a43b34e46b 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -334,18 +334,25 @@ static inline target_ulong tlb_read_idx(const CPUTLBE= ntry *entry, { /* Do not rearrange the CPUTLBEntry structure members. */ QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_read) !=3D - MMU_DATA_LOAD * TARGET_LONG_SIZE); + MMU_DATA_LOAD * sizeof(uint64_t)); QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_write) !=3D - MMU_DATA_STORE * TARGET_LONG_SIZE); + MMU_DATA_STORE * sizeof(uint64_t)); QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) !=3D - MMU_INST_FETCH * TARGET_LONG_SIZE); + MMU_INST_FETCH * sizeof(uint64_t)); =20 - const target_ulong *ptr =3D &entry->addr_idx[access_type]; -#if TCG_OVERSIZED_GUEST - return *ptr; +#if TARGET_LONG_BITS =3D=3D 32 + /* Use qatomic_read, in case of addr_write; only care about low bits. = */ + const uint32_t *ptr =3D (uint32_t *)&entry->addr_idx[access_type]; + ptr +=3D HOST_BIG_ENDIAN; + return qatomic_read(ptr); #else + const uint64_t *ptr =3D &entry->addr_idx[access_type]; +# if TCG_OVERSIZED_GUEST + return *ptr; +# else /* ofs might correspond to .addr_write, so use qatomic_read */ return qatomic_read(ptr); +# endif #endif } =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 90c72c9940..6beaeb0a81 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1000,11 +1000,15 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntr= y *tlb_entry, addr &=3D TARGET_PAGE_MASK; addr +=3D tlb_entry->addend; if ((addr - start) < length) { -#if TCG_OVERSIZED_GUEST +#if TARGET_LONG_BITS =3D=3D 32 + uint32_t *ptr_write =3D (uint32_t *)&tlb_entry->addr_write; + ptr_write +=3D HOST_BIG_ENDIAN; + qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY); +#elif TCG_OVERSIZED_GUEST tlb_entry->addr_write |=3D TLB_NOTDIRTY; #else qatomic_set(&tlb_entry->addr_write, - tlb_entry->addr_write | TLB_NOTDIRTY); + tlb_entry->addr_write | TLB_NOTDIRTY); #endif } } diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 84283665e7..39bb47baec 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1674,6 +1674,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, tcg_out_insn(s, 3502, ADD, 1, TCG_REG_X1, TCG_REG_X1, TCG_REG_X0); =20 /* Load the tlb comparator into X0, and the fast path addend into X1. = */ + QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); tcg_out_ld(s, addr_type, TCG_REG_X0, TCG_REG_X1, is_ld ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 20cc1cc477..64eb0cb5dc 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1430,6 +1430,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. * Load the tlb comparator into R2/R3 and the fast path addend into R1. */ + QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); if (cmp_off =3D=3D 0) { if (s->addr_type =3D=3D TCG_TYPE_I32) { tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 0bae922982..e89f3b848b 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -875,6 +875,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *= s, HostAddress *h, tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); =20 /* Load the tlb comparator and the addend. */ + QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, is_ld ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index ef146b193c..26ed2a4e9b 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1199,14 +1199,17 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3= . */ tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); =20 + if (TCG_TARGET_REG_BITS =3D=3D 32 || addr_type =3D=3D TCG_TYPE_I32) { + /* Load the (low half) tlb comparator. */ + tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, + cmp_off + HOST_BIG_ENDIAN * 4); + } else { + tcg_out_ld(s, TCG_TYPE_I64, TCG_TMP0, TCG_TMP3, cmp_off); + } + if (TCG_TARGET_REG_BITS =3D=3D 64 || addr_type =3D=3D TCG_TYPE_I32) { - /* Load the tlb comparator. */ - tcg_out_ld(s, addr_type, TCG_TMP0, TCG_TMP3, cmp_off); /* Load the tlb addend for the fast path. */ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); - } else { - /* Load the low half of the tlb comparator. */ - tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); } =20 /* diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 30372519dd..8add9afbbf 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2085,20 +2085,24 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, } tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0)); =20 - /* Load the (low part) TLB comparator into TMP2. */ - if (cmp_off =3D=3D 0 - && (TCG_TARGET_REG_BITS =3D=3D 64 || addr_type =3D=3D TCG_TYPE_I32= )) { - uint32_t lxu =3D (TCG_TARGET_REG_BITS =3D=3D 32 || addr_type =3D= =3D TCG_TYPE_I32 - ? LWZUX : LDUX); - tcg_out32(s, lxu | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2)); + /* + * Load the (low part) TLB comparator into TMP2. + * For 64-bit host, always load the entire 64-bit slot for simplicity. + * We will ignore the high bits with tcg_out_cmp(..., addr_type). + */ + if (TCG_TARGET_REG_BITS =3D=3D 64) { + if (cmp_off =3D=3D 0) { + tcg_out32(s, LDUX | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TM= P2)); + } else { + tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP= 2)); + tcg_out_ld(s, TCG_TYPE_I64, TCG_REG_TMP2, TCG_REG_TMP1, cmp_of= f); + } + } else if (cmp_off =3D=3D 0 && !HOST_BIG_ENDIAN) { + tcg_out32(s, LWZUX | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2)= ); } else { tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2)); - if (TCG_TARGET_REG_BITS =3D=3D 32 && addr_type !=3D TCG_TYPE_I32) { - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, - TCG_REG_TMP1, cmp_off + 4 * HOST_BIG_ENDIAN); - } else { - tcg_out_ld(s, addr_type, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off); - } + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1, + cmp_off + 4 * HOST_BIG_ENDIAN); } =20 /* diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 45bd09cfc4..1b5e3d3ec3 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -962,6 +962,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *= s, TCGReg *pbase, } =20 /* Load the tlb comparator and the addend. */ + QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, is_ld ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index c32801b829..319c697a3c 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1783,6 +1783,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, ofs =3D offsetof(CPUTLBEntry, addr_write); } if (addr_type =3D=3D TCG_TYPE_I32) { + ofs +=3D HOST_BIG_ENDIAN * 4; tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); } else { tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 48efd83817..6c60657c36 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1063,8 +1063,12 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContex= t *s, HostAddress *h, /* Add the tlb_table pointer, creating the CPUTLBEntry address into R2= . */ tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T3, ARITH_ADD); =20 - /* Load the tlb comparator and the addend. */ - tcg_out_ld(s, addr_type, TCG_REG_T2, TCG_REG_T1, cmp_off); + /* + * Load the tlb comparator and the addend. + * Always load the entire 64-bit comparator for simplicity. + * We will ignore the high bits via BPCC_ICC below. + */ + tcg_out_ld(s, TCG_TYPE_I64, TCG_REG_T2, TCG_REG_T1, cmp_off); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T1, TCG_REG_T1, add_off); h->base =3D TCG_REG_T1; =20 --=20 2.34.1 From nobody Sat May 18 06:50:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684854950; cv=none; d=zohomail.com; s=zohoarc; b=WvmTk7ZGlzjGsy2JCAXY9O6zW2XVVlClgVsUKnS4Bq+phVrDDa/lg5TodJ/T1hWFBxQcFgzP54hBDTzHaE2HA9exCYDkhP/pSge0fXLYN3+AV30RdkJ8dv4mJn6bZDBQX2YYnn2iRwmZzEVDpPd2dcBDBPwNVftAacpSCTfUFYI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684854950; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=++xGouEzAnDLCOE+hfQe+33jtp4dTZsPLh5EBleA5as=; b=Q/p1FHxtqZYjELKFsSwQfITbyL/H6BNCcPdh4Ur7vC0xzOH7awxDTzos0z7wcJNkMsnCcjBMbrNIPmDSm2LyTJNjUMvoTFnCBYdspwjKmY8W/fCZpVeumwvCGICAHT75AjtZwzBzQzaMp/W6fdaH4M1NTVjjC3tIvWtM3g5bdOU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684854950800431.5531899261596; Tue, 23 May 2023 08:15:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1STD-0006qz-Az; Tue, 23 May 2023 09:54:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSK-0004uI-NQ for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:41 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSA-0002zf-Up for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:38 -0400 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-64d2ca9ef0cso3750511b3a.1 for ; Tue, 23 May 2023 06:53:30 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850010; x=1687442010; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=++xGouEzAnDLCOE+hfQe+33jtp4dTZsPLh5EBleA5as=; b=NJSwZF1IQXP+5VK7pUoOmH+wfB9aZ4bGRKoOAysGt0SewV9dDQVVdssp092QPR1Fmb v9+J2PCRulGs99Krkd5JDS1OiEAHlil8n7P4Nc2dZLXgwuUZzWtci+pdQqHI6Yms4XM+ j+Y/nIcRsquQYdu8wZqdvFGf1fKEWdlffVHpmLUW7d4zP9l3jfzJ1I5dnLHkecsb7QXb evbDzjB1FZ06EjufkJ0vrgPqqaewMouWfGRBjiXux0AdTy4VsDVIMDiSOZaEFfqlJzou 9dNsqlEuNeoY9g1Tlb+j2at9LitLV0z7EoS9M3yVkMcUvfuS0XS11WBarTZ3DUOv7NiJ Ix0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850010; x=1687442010; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=++xGouEzAnDLCOE+hfQe+33jtp4dTZsPLh5EBleA5as=; b=M0yqLxAznPO6q1XBOoLMLKg92IJl8zFImRnoUVMPvEyWFKQBbcZYrIPa1xpRBX0txz zWJg5jl5pSYHoyjsstAshUVKYTQSA2SzD01xdf7KE+0UK071GJ6fE5Cc1uQ2ldglNNWD uJ5KV5eHM/ChGb6bubNBI/UU8kI1Or8hyaGvXovcPIX5pZbfBxND66JiEmwptsKEG9Yq cYiCK6wTN0SEAUj4EqpFhYViOAFPxAE7WSluP7LCa9CuBQZA2ckLyabTUhnAM5C/SQPv 5M88EsS2ZSH7sby0hgykob2AMWJDLTHP0BjzKN5bkeEDDGu+YlIt8TbE4gJroU3zk0RC +YgA== X-Gm-Message-State: AC+VfDwu+sUOQn6oeRk+Th0R+oqIYrpDdJa1q8o9cCKPOqTB/9PB9BMh uV10Xp3SfOVg6M5t+mcpxRm5ME2t3o6FT9YtP5Y= X-Google-Smtp-Source: ACHHUZ5YJqp2FFPmr9C+Rjk6/x3O/UKv3kd2aIx6xCK5UWR8I7i5dGMFLVeJ9NTh3pNDhmfR4JZK8g== X-Received: by 2002:a05:6a00:1689:b0:627:6328:79f1 with SMTP id k9-20020a056a00168900b00627632879f1mr20302375pfc.34.1684850010011; Tue, 23 May 2023 06:53:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 07/52] tcg: Add tlb_fast_offset to TCGContext Date: Tue, 23 May 2023 06:52:37 -0700 Message-Id: <20230523135322.678948-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684854951538100001 Content-Type: text/plain; charset="utf-8" Disconnect the layout of ArchCPU from TCG compilation. Pass the relative offset of 'env' and 'neg.tlb.f' as a parameter. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 39 +--------------------- include/exec/tlb-common.h | 56 ++++++++++++++++++++++++++++++++ include/tcg/tcg.h | 1 + accel/tcg/translate-all.c | 2 ++ tcg/tcg.c | 13 ++++++++ tcg/aarch64/tcg-target.c.inc | 7 ++-- tcg/arm/tcg-target.c.inc | 7 ++-- tcg/i386/tcg-target.c.inc | 9 ++--- tcg/loongarch64/tcg-target.c.inc | 7 ++-- tcg/mips/tcg-target.c.inc | 7 ++-- tcg/ppc/tcg-target.c.inc | 7 ++-- tcg/riscv/tcg-target.c.inc | 7 ++-- tcg/s390x/tcg-target.c.inc | 7 ++-- tcg/sparc64/tcg-target.c.inc | 7 ++-- 14 files changed, 110 insertions(+), 66 deletions(-) create mode 100644 include/exec/tlb-common.h diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index b757d37966..0d418a0384 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -61,12 +61,11 @@ #define NB_MMU_MODES 16 =20 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) +#include "exec/tlb-common.h" =20 /* use a fully associative victim tlb of 8 entries */ #define CPU_VTLB_SIZE 8 =20 -#define CPU_TLB_ENTRY_BITS 5 - #define CPU_TLB_DYN_MIN_BITS 6 #define CPU_TLB_DYN_DEFAULT_BITS 8 =20 @@ -90,27 +89,6 @@ # endif # endif =20 -/* Minimalized TLB entry for use by TCG fast path. */ -typedef union CPUTLBEntry { - struct { - uint64_t addr_read; - uint64_t addr_write; - uint64_t addr_code; - /* - * Addend to virtual address to get host address. IO accesses - * use the corresponding iotlb value. - */ - uintptr_t addend; - }; - /* - * Padding to get a power of two size, as well as index - * access to addr_{read,write,code}. - */ - uint64_t addr_idx[(1 << CPU_TLB_ENTRY_BITS) / sizeof(uint64_t)]; -} CPUTLBEntry; - -QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) !=3D (1 << CPU_TLB_ENTRY_BITS)); - #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ =20 #if !defined(CONFIG_USER_ONLY) @@ -184,17 +162,6 @@ typedef struct CPUTLBDesc { CPUTLBEntryFull *fulltlb; } CPUTLBDesc; =20 -/* - * Data elements that are per MMU mode, accessed by the fast path. - * The structure is aligned to aid loading the pair with one insn. - */ -typedef struct CPUTLBDescFast { - /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ - uintptr_t mask; - /* The array of tlb entries itself. */ - CPUTLBEntry *table; -} CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *)); - /* * Data elements that are shared between all MMU modes. */ @@ -230,10 +197,6 @@ typedef struct CPUTLB { CPUTLBDescFast f[NB_MMU_MODES]; } CPUTLB; =20 -/* This will be used by TCG backends to compute offsets. */ -#define TLB_MASK_TABLE_OFS(IDX) \ - ((int)offsetof(ArchCPU, neg.tlb.f[IDX]) - (int)offsetof(ArchCPU, env)) - #else =20 typedef struct CPUTLB { } CPUTLB; diff --git a/include/exec/tlb-common.h b/include/exec/tlb-common.h new file mode 100644 index 0000000000..dc5a5faa0b --- /dev/null +++ b/include/exec/tlb-common.h @@ -0,0 +1,56 @@ +/* + * Common definitions for the softmmu tlb + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#ifndef EXEC_TLB_COMMON_H +#define EXEC_TLB_COMMON_H 1 + +#define CPU_TLB_ENTRY_BITS 5 + +/* Minimalized TLB entry for use by TCG fast path. */ +typedef union CPUTLBEntry { + struct { + uint64_t addr_read; + uint64_t addr_write; + uint64_t addr_code; + /* + * Addend to virtual address to get host address. IO accesses + * use the corresponding iotlb value. + */ + uintptr_t addend; + }; + /* + * Padding to get a power of two size, as well as index + * access to addr_{read,write,code}. + */ + uint64_t addr_idx[(1 << CPU_TLB_ENTRY_BITS) / sizeof(uint64_t)]; +} CPUTLBEntry; + +QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) !=3D (1 << CPU_TLB_ENTRY_BITS)); + +/* + * Data elements that are per MMU mode, accessed by the fast path. + * The structure is aligned to aid loading the pair with one insn. + */ +typedef struct CPUTLBDescFast { + /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ + uintptr_t mask; + /* The array of tlb entries itself. */ + CPUTLBEntry *table; +} CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *)); + +#endif /* EXEC_TLB_COMMON_H */ diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 0da17f1b4f..54f260a66b 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -547,6 +547,7 @@ struct TCGContext { TCGType addr_type; /* TCG_TYPE_I32 or TCG_TYPE_I64 */ =20 #ifdef CONFIG_SOFTMMU + int tlb_fast_offset; int page_mask; uint8_t page_bits; uint8_t tlb_dyn_max_bits; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index f6c8ad1a18..be38d4aad8 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -361,6 +361,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->page_bits =3D TARGET_PAGE_BITS; tcg_ctx->page_mask =3D TARGET_PAGE_MASK; tcg_ctx->tlb_dyn_max_bits =3D CPU_TLB_DYN_MAX_BITS; + tcg_ctx->tlb_fast_offset =3D + (int)offsetof(ArchCPU, neg.tlb.f) - (int)offsetof(ArchCPU, env); #endif =20 tb_overflow: diff --git a/tcg/tcg.c b/tcg/tcg.c index 0b0fe9c7ad..35bbc03ede 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -44,6 +44,7 @@ #define NO_CPU_IO_DEFS =20 #include "exec/exec-all.h" +#include "exec/tlb-common.h" #include "tcg/tcg-op.h" =20 #if UINTPTR_MAX =3D=3D UINT32_MAX @@ -410,6 +411,13 @@ static uintptr_t G_GNUC_UNUSED get_jmp_target_addr(TCG= Context *s, int which) return (uintptr_t)tcg_splitwx_to_rx(&s->gen_tb->jmp_target_addr[which]= ); } =20 +#if defined(CONFIG_SOFTMMU) && !defined(CONFIG_TCG_INTERPRETER) +static int tlb_mask_table_ofs(TCGContext *s, int which) +{ + return s->tlb_fast_offset + which * sizeof(CPUTLBDescFast); +} +#endif + /* Signal overflow, starting over with fewer guest insns. */ static G_NORETURN void tcg_raise_tb_overflow(TCGContext *s) @@ -1526,6 +1534,11 @@ void tcg_func_start(TCGContext *s) =20 tcg_debug_assert(s->addr_type =3D=3D TCG_TYPE_I32 || s->addr_type =3D=3D TCG_TYPE_I64); + +#if defined(CONFIG_SOFTMMU) && !defined(CONFIG_TCG_INTERPRETER) + tcg_debug_assert(s->tlb_fast_offset < 0); + tcg_debug_assert(s->tlb_fast_offset >=3D MIN_TLB_MASK_TABLE_OFS); +#endif } =20 static TCGTemp *tcg_temp_alloc(TCGContext *s) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 39bb47baec..af4e9fdac7 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1620,6 +1620,9 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) return true; } =20 +/* We expect to use a 7-bit scaled negative offset from ENV. */ +#define MIN_TLB_MASK_TABLE_OFS -512 + /* * For softmmu, perform the TLB load and compare. * For useronly, perform any required alignment tests. @@ -1658,12 +1661,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, ? TCG_TYPE_I64 : TCG_TYPE_I32); =20 /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */ - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512); QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 8); tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0, - TLB_MASK_TABLE_OFS(mem_index), 1, 0); + tlb_mask_table_ofs(s, mem_index), 1, 0); =20 /* Extract the TLB index from the address into X0. */ tcg_out_insn(s, 3502S, AND_LSR, mask_type =3D=3D TCG_TYPE_I64, diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 64eb0cb5dc..83e286088f 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1374,6 +1374,9 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) return true; } =20 +/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ +#define MIN_TLB_MASK_TABLE_OFS -256 + static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, bool is_ld) @@ -1405,7 +1408,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, int mem_index =3D get_mmuidx(oi); int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write); - int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int fast_off =3D tlb_mask_table_ofs(s, mem_index); unsigned s_mask =3D (1 << (opc & MO_SIZE)) - 1; TCGReg t_addr; =20 @@ -1416,8 +1419,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, ldst->addrhi_reg =3D addrhi; =20 /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */ - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256); QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 4); tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index bfe9d98b7e..d955aa6a9c 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1858,6 +1858,8 @@ static inline int setup_guest_base_seg(void) #endif /* setup_guest_base_seg */ #endif /* !SOFTMMU */ =20 +#define MIN_TLB_MASK_TABLE_OFS INT_MIN + /* * For softmmu, perform the TLB load and compare. * For useronly, perform any required alignment tests. @@ -1892,6 +1894,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, unsigned mem_index =3D get_mmuidx(oi); unsigned s_bits =3D opc & MO_SIZE; unsigned s_mask =3D (1 << s_bits) - 1; + int fast_ofs =3D tlb_mask_table_ofs(s, mem_index); int tlb_mask; =20 ldst =3D new_ldst_label(s); @@ -1917,12 +1920,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, s->page_bits - CPU_TLB_ENTRY_BITS); =20 tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0, - TLB_MASK_TABLE_OFS(mem_index) + - offsetof(CPUTLBDescFast, mask)); + fast_ofs + offsetof(CPUTLBDescFast, mask)); =20 tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0, - TLB_MASK_TABLE_OFS(mem_index) + - offsetof(CPUTLBDescFast, table)); + fast_ofs + offsetof(CPUTLBDescFast, table)); =20 /* * If the required alignment is at least as large as the access, simply diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index e89f3b848b..baf5fc3819 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -834,6 +834,9 @@ bool tcg_target_has_memory_bswap(MemOp memop) return false; } =20 +/* We expect to use a 12-bit negative offset from ENV. */ +#define MIN_TLB_MASK_TABLE_OFS -(1 << 11) + /* * For softmmu, perform the TLB load and compare. * For useronly, perform any required alignment tests. @@ -855,7 +858,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *= s, HostAddress *h, #ifdef CONFIG_SOFTMMU unsigned s_bits =3D opc & MO_SIZE; int mem_index =3D get_mmuidx(oi); - int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); + int fast_ofs =3D tlb_mask_table_ofs(s, mem_index); int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); =20 @@ -864,8 +867,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *= s, HostAddress *h, ldst->oi =3D oi; ldst->addrlo_reg =3D addr_reg; =20 - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); =20 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 26ed2a4e9b..e2a78d0530 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1142,6 +1142,9 @@ bool tcg_target_has_memory_bswap(MemOp memop) return false; } =20 +/* We expect to use a 16-bit negative offset from ENV. */ +#define MIN_TLB_MASK_TABLE_OFS -32768 + /* * For softmmu, perform the TLB load and compare. * For useronly, perform any required alignment tests. @@ -1167,7 +1170,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, #ifdef CONFIG_SOFTMMU unsigned s_mask =3D (1 << s_bits) - 1; int mem_index =3D get_mmuidx(oi); - int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int fast_off =3D tlb_mask_table_ofs(s, mem_index); int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); int add_off =3D offsetof(CPUTLBEntry, addend); @@ -1181,8 +1184,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, ldst->addrhi_reg =3D addrhi; =20 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); =20 diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 8add9afbbf..073361a54b 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2023,6 +2023,9 @@ bool tcg_target_has_memory_bswap(MemOp memop) return true; } =20 +/* We expect to use a 16-bit negative offset from ENV. */ +#define MIN_TLB_MASK_TABLE_OFS -32768 + /* * For softmmu, perform the TLB load and compare. * For useronly, perform any required alignment tests. @@ -2058,7 +2061,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, int mem_index =3D get_mmuidx(oi); int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write); - int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int fast_off =3D tlb_mask_table_ofs(s, mem_index); int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); unsigned s_bits =3D opc & MO_SIZE; @@ -2070,8 +2073,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, ldst->addrhi_reg =3D addrhi; =20 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_AREG0, table_off); =20 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 1b5e3d3ec3..99e375d5b1 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -898,6 +898,9 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TC= GLabelQemuLdst *l) return true; } =20 +/* We expect to use a 12-bit negative offset from ENV. */ +#define MIN_TLB_MASK_TABLE_OFS -(1 << 11) + /* * For softmmu, perform the TLB load and compare. * For useronly, perform any required alignment tests. @@ -921,7 +924,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *= s, TCGReg *pbase, unsigned s_bits =3D opc & MO_SIZE; unsigned s_mask =3D (1u << s_bits) - 1; int mem_index =3D get_mmuidx(oi); - int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); + int fast_ofs =3D tlb_mask_table_ofs(s, mem_index); int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); int compare_mask; @@ -932,8 +935,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *= s, TCGReg *pbase, ldst->oi =3D oi; ldst->addrlo_reg =3D addr_reg; =20 - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); =20 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 319c697a3c..264a5628db 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1722,6 +1722,9 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) return true; } =20 +/* We're expecting to use a 20-bit negative offset on the tlb memory ops. = */ +#define MIN_TLB_MASK_TABLE_OFS -(1 << 19) + /* * For softmmu, perform the TLB load and compare. * For useronly, perform any required alignment tests. @@ -1744,7 +1747,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, unsigned s_bits =3D opc & MO_SIZE; unsigned s_mask =3D (1 << s_bits) - 1; int mem_index =3D get_mmuidx(oi); - int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int fast_off =3D tlb_mask_table_ofs(s, mem_index); int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); int ofs, a_off; @@ -1758,8 +1761,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, s->page_bits - CPU_TLB_ENTRY_BITS); =20 - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_off); tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_off); =20 diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 6c60657c36..ffcb879211 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1017,6 +1017,9 @@ bool tcg_target_has_memory_bswap(MemOp memop) return true; } =20 +/* We expect to use a 13-bit negative offset from ENV. */ +#define MIN_TLB_MASK_TABLE_OFS -(1 << 12) + /* * For softmmu, perform the TLB load and compare. * For useronly, perform any required alignment tests. @@ -1040,7 +1043,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, =20 #ifdef CONFIG_SOFTMMU int mem_index =3D get_mmuidx(oi); - int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int fast_off =3D tlb_mask_table_ofs(s, mem_index); int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) @@ -1050,8 +1053,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, int cc; =20 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12)); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T2, TCG_AREG0, mask_off); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T3, TCG_AREG0, table_off); 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Fixes: e77c89fb086a ("cputlb: Remove static tlb sizing") Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/aarch64/tcg-target.h | 1 - tcg/arm/tcg-target.h | 1 - tcg/i386/tcg-target.h | 1 - tcg/mips/tcg-target.h | 1 - tcg/ppc/tcg-target.h | 1 - tcg/riscv/tcg-target.h | 1 - tcg/s390x/tcg-target.h | 1 - tcg/sparc64/tcg-target.h | 1 - tcg/tci/tcg-target.h | 1 - 9 files changed, 9 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index d5f7614880..cea21234cd 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -16,7 +16,6 @@ #include "host/cpuinfo.h" =20 #define TCG_TARGET_INSN_UNIT_SIZE 4 -#define TCG_TARGET_TLB_DISPLACEMENT_BITS 24 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) =20 typedef enum { diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 65efc538f4..c649db72a6 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -31,7 +31,6 @@ extern int arm_arch; #define use_armv7_instructions (__ARM_ARCH >=3D 7 || arm_arch >=3D 7) =20 #define TCG_TARGET_INSN_UNIT_SIZE 4 -#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 #define MAX_CODE_GEN_BUFFER_SIZE UINT32_MAX =20 typedef enum { diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 0106946996..b0922922b3 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -28,7 +28,6 @@ #include "host/cpuinfo.h" =20 #define TCG_TARGET_INSN_UNIT_SIZE 1 -#define TCG_TARGET_TLB_DISPLACEMENT_BITS 31 =20 #ifdef __x86_64__ # define TCG_TARGET_REG_BITS 64 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 7277a117ef..e52cdf0e89 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -36,7 +36,6 @@ #endif =20 #define TCG_TARGET_INSN_UNIT_SIZE 4 -#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 #define TCG_TARGET_NB_REGS 32 =20 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 0914380bd7..d68a65a9bc 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -34,7 +34,6 @@ =20 #define TCG_TARGET_NB_REGS 64 #define TCG_TARGET_INSN_UNIT_SIZE 4 -#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 =20 typedef enum { TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 494c986b49..ffb3d9b5b4 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -35,7 +35,6 @@ #define TCG_TARGET_REG_BITS 64 =20 #define TCG_TARGET_INSN_UNIT_SIZE 4 -#define TCG_TARGET_TLB_DISPLACEMENT_BITS 20 #define TCG_TARGET_NB_REGS 32 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) =20 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 170007bea5..2bbeeae5cd 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -26,7 +26,6 @@ #define S390_TCG_TARGET_H =20 #define TCG_TARGET_INSN_UNIT_SIZE 2 -#define TCG_TARGET_TLB_DISPLACEMENT_BITS 19 =20 /* We have a +- 4GB range on the branches; leave some slop. */ #define MAX_CODE_GEN_BUFFER_SIZE (3 * GiB) diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index 31c5537379..d454278811 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -26,7 +26,6 @@ #define SPARC_TCG_TARGET_H =20 #define TCG_TARGET_INSN_UNIT_SIZE 4 -#define TCG_TARGET_TLB_DISPLACEMENT_BITS 32 #define TCG_TARGET_NB_REGS 32 #define MAX_CODE_GEN_BUFFER_SIZE (2 * GiB) =20 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 28dc6d5cfc..60a6ed65ce 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -42,7 +42,6 @@ =20 #define TCG_TARGET_INTERPRETER 1 #define TCG_TARGET_INSN_UNIT_SIZE 4 -#define TCG_TARGET_TLB_DISPLACEMENT_BITS 32 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) =20 #if UINTPTR_MAX =3D=3D UINT32_MAX --=20 2.34.1 From nobody Sat May 18 06:50:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850011; x=1687442011; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=pETdULDQ5wVmC1hpPClhoopHjiyEI8tGTGOipI84kxM=; b=q+mgntLrg1UWZclDE3LYT9aWqZk6AzgQZtPJNk9IaJ+8zKc9bK7knAyOjq1f4NWf83 biuhX5NLiw5r/u4MXiLWb1vNUw4clGTMMWkainDLsTkSxVN4dNwPlOTU96C735qn0oD1 de0Gs5vOpF3z1YsQWr/vpfHM/AnotXLK7TFG6l6NQEnuKGIXpgZ5huXC8WngIv22h+Cv LLCUGl6VHJYR/BUxD99AC+kG1ZQfdDQxgD5nSQO+3q1FDxXy83vjSnaW0RgYEpXM7pf3 yzBZWhqu7L465Re9nIVwKJoFkVBPhUMlcQPjC3QJFy0ttu0qey+8f2Ar5CGzA5+TRMiS bABg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850011; x=1687442011; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pETdULDQ5wVmC1hpPClhoopHjiyEI8tGTGOipI84kxM=; b=XKuY0WOqjQvBHaKqYNNKcE2dvIsrUwMfHEYSnDq3LsTIcRi6yVKcA9+tjNpAGCGcmn KAGlJIxwzxDEvn0EAR1nuK1EIYn+GP+q84AysFnCv6Ek+VE2HNiToQWvbYPrCGAT99zA H5bjINLgBHANZAjQlRM2NNT4IG4AF4xIrHIGgKmsJL3HJsCMnOvSLEHdui75Ym0m291B SNCGLLSKhIjCtKBUjXFh0nGDtj3kOAEa4yGLENNkHMgfQc8vAreQwv2mapQeHyb6sCtE LTFSzymL5Z375SipgYzYI/+f8rVHo0XBOTppVwF2DksNlmF1eLFeAOptL9MeQOIF/im3 tc9g== X-Gm-Message-State: AC+VfDyLMJSaCjrzxmPh3XO6YmqESxTN2FiLmYifzFvYOJTHrSKKmnnR Z04heRSHteZkZh3FwnLAlFi/D8UscGkJ19VbwOA= X-Google-Smtp-Source: ACHHUZ4dycvza3RtcsagkBaNNC7vF+aAgbvTynIPiPn7oYBSOiQdxgRg96LRltbRBaFEY7CdVJIVwA== X-Received: by 2002:a05:6a00:2e21:b0:627:e49a:871a with SMTP id fc33-20020a056a002e2100b00627e49a871amr18608389pfb.23.1684850011539; Tue, 23 May 2023 06:53:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 09/52] *: Add missing includes of qemu/error-report.h Date: Tue, 23 May 2023 06:52:39 -0700 Message-Id: <20230523135322.678948-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684850934187100001 Content-Type: text/plain; charset="utf-8" This had been pulled in from tcg/tcg.h, via exec/cpu_ldst.h, via exec/exec-all.h, but the include of tcg.h will be removed. Signed-off-by: Richard Henderson --- target/avr/helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/avr/helper.c b/target/avr/helper.c index 156dde4e92..2bad242a66 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -20,6 +20,7 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/error-report.h" #include "cpu.h" #include "hw/core/tcg-cpu-ops.h" #include "exec/exec-all.h" --=20 2.34.1 From nobody Sat May 18 06:50:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684853048; cv=none; d=zohomail.com; s=zohoarc; b=heBxIyFxJNKXAiNm6vMST9toy17oP3xflf5mCOm6Kcn2RJ/itc/wpDtpz307yJvmziAC/TwRoN+QBXj0W/DfT/LQmgF2hO7/6vfcK9f9/ssVckkdc175iB94rkhDnmdwYNzjNbBl8wkcxmFYVO6K59/tv3O2kK/L2CU7573+6YU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684853048; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FMynriKgHY7/a7Zeekt4jsXQMXu8INdJVu2wztuImV0=; b=KA9HJkl0jJp4u8Zju3GMIbzKzTTbrouyQfea2iL6niuSm74tL+Ztmsx5Gtc/EdOClO40i97umY4htIu+2wFPFYAa6J+tK4Y0IVla/BUnwB/8RRtLJcVC9RTOupXI04TdfGFL4XJV9pkhUYRvl3bD53YTOL1H20Xr+sx0ZgcUxtc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684853048375488.07337697956825; Tue, 23 May 2023 07:44:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SSv-0005wG-77; Tue, 23 May 2023 09:54:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSH-0004bX-So for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:39 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSD-00031u-PF for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:36 -0400 Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-64d2ca9ef0cso3750548b3a.1 for ; Tue, 23 May 2023 06:53:33 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850012; x=1687442012; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=FMynriKgHY7/a7Zeekt4jsXQMXu8INdJVu2wztuImV0=; b=nzLdzEiT2fInIGnjrcnAuX+RYtWr+1bokG/EpdUQyYK+NsGi+HPcbLgP79AutX5/pQ Uf7feEw/FiNvhcEMpWZ7emAAheSTWKgqDfrF0Rnh+c++5n2rg1mV91LmUwL0h3afUIkt BimW2RiSBChYoArovaGXsTDWaAAmFJjEK4CH2doB24ZAriZ55nebaBjt9ydlwGNRHhib oAKhLF5zEGkjQsFIIBaZragcdJk1VL0mdqfWNEu2PTV4wS6kE740iB6NMqMlwTBWj/kw rdedSqPBT78L6BLQdyRNxwHtkXCCIlGBpzUgDm/Zlfp2WhYDL+7u/eq7ej/FmrgXbHSo J8Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850012; x=1687442012; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FMynriKgHY7/a7Zeekt4jsXQMXu8INdJVu2wztuImV0=; b=cl+q9CiTrm5haFOSP7iyOB/BTenn40O+QLCDdmcJStZtomloVn4G8TLyG/YoyGvD6n 6h3yqfYP+FdCtdBQKqmnCC9L3KytGz9KIpCxxSNzSs5vxUHJHH7hIGOq1Em+OIfPfmMT vcu4gNT+PkcQMm/9zNVwfvpXDqjHx5UbPlVaVWb4TPfn9cJ2OVr+C5OBqNaFQBbd5NXe MblEgQHph73MkdMZx+YX9rGY+lLNzSBjV7cKA4plysKSzY7YVbh7iQt6bQZqjw3yAPu5 36KTOkhApGL6VUzd5pyp1D0ru/Mw5IufYnhLItSLfJqnk1eeiHEtVL+3yU60tsysn/bI 4wjw== X-Gm-Message-State: AC+VfDy8sRuD9+tQ1O2O6jiPyh2LJB0VEWcwsgdWir2mUuajbNecQ3tY siLju5iPrhdY3agHXt1q1tDbyJ3pu4xkYF+ti6E= X-Google-Smtp-Source: ACHHUZ6Quni6Xr2uS5VDzCrJZXGBAR6qBqXOGOMXP3DzIUFY0PMxFHhsh/PY4BPNBaKsGHDg2wJ6MA== X-Received: by 2002:a05:6a00:1798:b0:64d:22d:adb3 with SMTP id s24-20020a056a00179800b0064d022dadb3mr16641362pfg.1.1684850012466; Tue, 23 May 2023 06:53:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 10/52] *: Add missing includes of tcg/debug-assert.h Date: Tue, 23 May 2023 06:52:40 -0700 Message-Id: <20230523135322.678948-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684853049475100003 Content-Type: text/plain; charset="utf-8" This had been pulled in from tcg/tcg.h, via exec/cpu_ldst.h, via exec/exec-all.h, but the include of tcg.h will be removed. Signed-off-by: Richard Henderson --- target/avr/cpu.c | 1 + target/rx/cpu.c | 1 + target/rx/op_helper.c | 1 + target/tricore/cpu.c | 1 + 4 files changed, 4 insertions(+) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index a24c23c247..8f741f258c 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "cpu.h" #include "disas/dis-asm.h" +#include "tcg/debug-assert.h" =20 static void avr_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 67452e310c..157e57da0f 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "hw/loader.h" #include "fpu/softfloat.h" +#include "tcg/debug-assert.h" =20 static void rx_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c index acce650185..dc0092ca99 100644 --- a/target/rx/op_helper.c +++ b/target/rx/op_helper.c @@ -23,6 +23,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" +#include "tcg/debug-assert.h" =20 static inline G_NORETURN void raise_exception(CPURXState *env, int index, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index d0a9272961..7fa113fed2 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "qemu/error-report.h" +#include "tcg/debug-assert.h" =20 static inline void set_feature(CPUTriCoreState *env, int feature) { --=20 2.34.1 From nobody Sat May 18 06:50:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851201; cv=none; d=zohomail.com; s=zohoarc; b=GdIRJurhULFV7R2/ZX/Ncc3V9k3pgu4LbEnYCxSOWIwY5u7XUtqL+T/4xZDxkdVNrKIGR8qIjSL6mumq0JyZJfT6CD3P4G9Yv5AChzOJjPUYlFiZfGuy4d6OB8ailovZFx2PkAy8zEM7wuGXbGnexDIh59EZ/ycm5qFT611+QmY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851201; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fjia3Wxg3tvISCHmEv9hWQkEs32v9NCdixUCeRZrr9g=; b=DZGkTW8+2f+m1BT3Hz0HkBmEuhDCaghaeKNg6vUHy7vjf5z1Gy3fx38YcvyVuBTIkmFyVNHRJqD+MLWPmaptBHaE41XtSQz3oYrtU8wCzm4TebyO4kdrcsuY5SQPf5YD6lSv4WNnpU1rIt+1K1F39cdp1Vf2q702SkxuTZnf5Es= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684851201186363.8597744420455; Tue, 23 May 2023 07:13:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SSa-00058G-RB; Tue, 23 May 2023 09:53:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSK-0004uH-Mr for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:41 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSE-00032E-Di for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:37 -0400 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-64d426e63baso4407743b3a.0 for ; Tue, 23 May 2023 06:53:33 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850013; x=1687442013; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=fjia3Wxg3tvISCHmEv9hWQkEs32v9NCdixUCeRZrr9g=; b=D3Stj5FhKIT3w5YpkpoZ5z4Hi+aCiPolr+7VooIiXOy5Km+GT+iAtReUErBrvo2s44 e4BzcfLxd/sqyLQSrcTwbVLH9oMs7m9rw0lqMrubZ+aeJRrsVEFawwYbcPNj2Ze9buQ/ BIjFyJeEX6P7Y0U4eK343AshbBQjEUhMOZr5E4hM9rkk6zbwiO5npcMPgE4PiRsLp/a9 ylmqpdZjEu4A/4iHWWsijH5tkvjP5bRRjcqyU0XeVtaG/97NZliXpnxghPBr+yEPXUM+ qH5MMcHtGdPquuAHDB/ff1V0vO1s+/ckIcl3yGKsOuI8qwM3h96N9qjO9DvY2PCTab5O PNsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850013; x=1687442013; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fjia3Wxg3tvISCHmEv9hWQkEs32v9NCdixUCeRZrr9g=; b=DXVixYQ6YrpDBBIXaFZMIJ0Epuidx8+2Z3Zem52w78xNr+DzPkc5yWyFpTN7tE+s2w ZPOnHAcgy67jz5UNFxJjGNZDOuzHdLQN1SL0xL3PYCbNytPFDUoXlA9AHSwCOZ8P7VHJ PswfB3j5gXyZQwVegZ3YsOB5GKxh0BQEbqBuup16J+IwOC3bv+DGsjfrEfTTtCPmEiWI jo+5ckc/q6OxEtTKe2BBHDRw+9djTR2QyIRo+jOwo9CeFYieVrmtggxxnAIUT/ekm18U rHC5bgMsvuicRTEoFV9AkNtgL0PXf/+nRvgbhp6ehqWOSIVeS5rCzblrgynlZEeEw1YY hiXQ== X-Gm-Message-State: AC+VfDz1UUe9Oi0AzgpxLAwdg2MEskmWQS7SKxH8YtIK5m6rC0UCa7Lj iFOGQ6gN07yzluYC3gqXbB+l1tIld3SWV16ZXDs= X-Google-Smtp-Source: ACHHUZ4DicjP4xFNMSsXcoCilRywXxdQHFLqjCDFZC2PYKeTjDNlq+rTyXqHOO38HzR5rYKj1oRwsw== X-Received: by 2002:a05:6a00:1994:b0:647:3de:c0ff with SMTP id d20-20020a056a00199400b0064703dec0ffmr15050210pfl.30.1684850013182; Tue, 23 May 2023 06:53:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 11/52] *: Add missing includes of tcg/tcg.h Date: Tue, 23 May 2023 06:52:41 -0700 Message-Id: <20230523135322.678948-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851202642100001 Content-Type: text/plain; charset="utf-8" This had been pulled in from exec/cpu_ldst.h, via exec/exec-all.h, but the include of tcg.h will be removed. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/monitor.c | 1 + accel/tcg/tcg-accel-ops-mttcg.c | 2 +- accel/tcg/tcg-accel-ops-rr.c | 2 +- target/i386/helper.c | 3 +++ target/openrisc/sys_helper.c | 1 + 5 files changed, 7 insertions(+), 2 deletions(-) diff --git a/accel/tcg/monitor.c b/accel/tcg/monitor.c index 92fce580f1..f171bc6f5e 100644 --- a/accel/tcg/monitor.c +++ b/accel/tcg/monitor.c @@ -15,6 +15,7 @@ #include "sysemu/cpus.h" #include "sysemu/cpu-timers.h" #include "sysemu/tcg.h" +#include "tcg/tcg.h" #include "internal.h" =20 =20 diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttc= g.c index d50239e0e2..5d72c9b1bd 100644 --- a/accel/tcg/tcg-accel-ops-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -32,7 +32,7 @@ #include "qemu/guest-random.h" #include "exec/exec-all.h" #include "hw/boards.h" - +#include "tcg/tcg.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-mttcg.h" =20 diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index b6d10fa9a2..70b9b89073 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -32,7 +32,7 @@ #include "qemu/notify.h" #include "qemu/guest-random.h" #include "exec/exec-all.h" - +#include "tcg/tcg.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-rr.h" #include "tcg-accel-ops-icount.h" diff --git a/target/i386/helper.c b/target/i386/helper.c index 8857444819..682d10d98a 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -28,6 +28,9 @@ #include "monitor/monitor.h" #endif #include "qemu/log.h" +#ifdef CONFIG_TCG +#include "tcg/tcg.h" +#endif =20 void cpu_sync_avx_hflag(CPUX86State *env) { diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index ccdee3b8be..110f157601 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -26,6 +26,7 @@ #ifndef CONFIG_USER_ONLY #include "hw/boards.h" #endif +#include "tcg/tcg.h" =20 #define TO_SPR(group, number) (((group) << 11) + (number)) =20 --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684853514; cv=none; d=zohomail.com; s=zohoarc; b=TmleUi+gOLHdGWPcuGj3jqmIFPHBXCq3uwD3h0klGT73F1aTQcH+EbKapK4WJNSe8OtedtsZSNXOK+LnK9VI+lpp3njxGeHdMroevooVNrgHkI51ZU8PWNf0Nc+24rGlQDhJSwkBfNeQt/2OSkNUjvQOUwUS2jvcixCwmsEHj4c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684853514; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=M26CNL5kh945lDaXePkVkDlOFsIa+WmNokm9cWJMfCw=; b=K9lKjPUCDwqd+4LsS8LKP3pzpm+tjgujf5G9wagDJEXjdBoNA/HOpF0x8hXK22JZjKuhjyZAaIUK0lG99kweohLxR/TdOlbO3Btbm5a9Ar5SQOvtd48Bc9/BTjtoimemkGMLwQWNz7yO9C7FAe4Iza2i1KMhEa2/B2kuH7kLaRE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684853514533730.8886574483766; Tue, 23 May 2023 07:51:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SSu-0005ta-2T; Tue, 23 May 2023 09:54:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSK-0004uJ-OV for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:41 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSG-00032V-Dn for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:40 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-64d2981e3abso4341371b3a.1 for ; Tue, 23 May 2023 06:53:36 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850014; x=1687442014; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=M26CNL5kh945lDaXePkVkDlOFsIa+WmNokm9cWJMfCw=; b=zBY3ImLcf48eu7EkEk+xTL86N0w5GgoYtH/d7lHLGVKMuIdHEF9ymj8ChEXomO8XQh biqFwJ/hGT1azu4Hnv8JnTl8ra1mzEAwFBMwJOHqjLqhR8RcXYQ+8y1Pe6B/CvOPZb13 7oSrFJUxvjWUDCvDopqh81igd1jGNPPgnuj1uBHGkmFVKvi9Uj2zl3HKR9fyS5Tfw/8q JeDy83k+zuRlEkpsIlyU6y5VV6+b8nsXq2Sj9iuKxC4ms+116A04IERmLiteWP/DhUWH zXQ0mcI7j82IoH1uaEpz4Qi0P1vKArFxXP/1SgqCczYttnAtumuqD/zYI82T8HH5p0dv KtEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850014; x=1687442014; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M26CNL5kh945lDaXePkVkDlOFsIa+WmNokm9cWJMfCw=; b=cngWg6jJ5uXavaeVGzdVbj0cVW5tjr2E2gTbXFR+C24VXiMNSynJuQ+yzD5BFpzCr0 eBL+6Z83v2nsmTt1U+DQrqNwD9pvAcG/8wdjQpvhsLad6g+lr/JlwJOM7GRnMhyCYa0Y KpoBd00jhVYvyk7CwuxlQ+S3rkDG/0Sk3DhdjZ9BWLmVDanVE/+4dEOBdCjOnSuxE5H2 orrbL8B87alqATLwAir+kDblTE97BWOi0enZ1WxpyY14IQ6fq3Jfp3gZp445clHcl0nt ox8oRhp6Oa5uiBt9X3G8oQ02eMMeaWnwoHhdy6uKZ7UPU988+/ktEAvJARimhHA/Sn/Z yc0Q== X-Gm-Message-State: AC+VfDzHLDtaAg0/zbmaHkG2l+cnL79FOk8l3fdJ4b671YtcGtZJiQlt mUv8CCYxXGA1rjPS1HkLGNbCWoiBOU9WsgqCmT8= X-Google-Smtp-Source: ACHHUZ5lec2S7KuHzgwhiPj++MSZ7tGQ+ddv/iWxch/XEDAPoSm1zXT1xRNDsDCDjEIzZyh4N0GK9A== X-Received: by 2002:a05:6a21:9201:b0:ff:b564:c532 with SMTP id tl1-20020a056a21920100b000ffb564c532mr13591636pzb.43.1684850013982; Tue, 23 May 2023 06:53:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 12/52] tcg: Split out tcg-target-reg-bits.h Date: Tue, 23 May 2023 06:52:42 -0700 Message-Id: <20230523135322.678948-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684853515536100001 Content-Type: text/plain; charset="utf-8" Often, the only thing we need to know about the TCG host is the register size. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 12 +----------- tcg/aarch64/tcg-target-reg-bits.h | 12 ++++++++++++ tcg/arm/tcg-target-reg-bits.h | 12 ++++++++++++ tcg/i386/tcg-target-reg-bits.h | 16 ++++++++++++++++ tcg/i386/tcg-target.h | 2 -- tcg/loongarch64/tcg-target-reg-bits.h | 21 +++++++++++++++++++++ tcg/loongarch64/tcg-target.h | 11 ----------- tcg/mips/tcg-target-reg-bits.h | 18 ++++++++++++++++++ tcg/mips/tcg-target.h | 8 -------- tcg/ppc/tcg-target-reg-bits.h | 16 ++++++++++++++++ tcg/ppc/tcg-target.h | 5 ----- tcg/riscv/tcg-target-reg-bits.h | 19 +++++++++++++++++++ tcg/riscv/tcg-target.h | 9 --------- tcg/s390x/tcg-target-reg-bits.h | 17 +++++++++++++++++ tcg/sparc64/tcg-target-reg-bits.h | 12 ++++++++++++ tcg/tci/tcg-target-reg-bits.h | 18 ++++++++++++++++++ tcg/tci/tcg-target.h | 8 -------- tcg/s390x/tcg-target.c.inc | 5 ----- 18 files changed, 162 insertions(+), 59 deletions(-) create mode 100644 tcg/aarch64/tcg-target-reg-bits.h create mode 100644 tcg/arm/tcg-target-reg-bits.h create mode 100644 tcg/i386/tcg-target-reg-bits.h create mode 100644 tcg/loongarch64/tcg-target-reg-bits.h create mode 100644 tcg/mips/tcg-target-reg-bits.h create mode 100644 tcg/ppc/tcg-target-reg-bits.h create mode 100644 tcg/riscv/tcg-target-reg-bits.h create mode 100644 tcg/s390x/tcg-target-reg-bits.h create mode 100644 tcg/sparc64/tcg-target-reg-bits.h create mode 100644 tcg/tci/tcg-target-reg-bits.h diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 54f260a66b..5fe90cbb42 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -32,6 +32,7 @@ #include "qemu/plugin.h" #include "qemu/queue.h" #include "tcg/tcg-mo.h" +#include "tcg-target-reg-bits.h" #include "tcg-target.h" #include "tcg/tcg-cond.h" #include "tcg/debug-assert.h" @@ -44,17 +45,6 @@ #define CPU_TEMP_BUF_NLONGS 128 #define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) =20 -/* Default target word size to pointer size. */ -#ifndef TCG_TARGET_REG_BITS -# if UINTPTR_MAX =3D=3D UINT32_MAX -# define TCG_TARGET_REG_BITS 32 -# elif UINTPTR_MAX =3D=3D UINT64_MAX -# define TCG_TARGET_REG_BITS 64 -# else -# error Unknown pointer size for tcg target -# endif -#endif - #if TCG_TARGET_REG_BITS =3D=3D 32 typedef int32_t tcg_target_long; typedef uint32_t tcg_target_ulong; diff --git a/tcg/aarch64/tcg-target-reg-bits.h b/tcg/aarch64/tcg-target-reg= -bits.h new file mode 100644 index 0000000000..3b57a1aafb --- /dev/null +++ b/tcg/aarch64/tcg-target-reg-bits.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Define target-specific register size + * Copyright (c) 2023 Linaro + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +#define TCG_TARGET_REG_BITS 64 + +#endif diff --git a/tcg/arm/tcg-target-reg-bits.h b/tcg/arm/tcg-target-reg-bits.h new file mode 100644 index 0000000000..23b7730a8d --- /dev/null +++ b/tcg/arm/tcg-target-reg-bits.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific register size + * Copyright (c) 2023 Linaro + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +#define TCG_TARGET_REG_BITS 32 + +#endif diff --git a/tcg/i386/tcg-target-reg-bits.h b/tcg/i386/tcg-target-reg-bits.h new file mode 100644 index 0000000000..aa386050eb --- /dev/null +++ b/tcg/i386/tcg-target-reg-bits.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific register size + * Copyright (c) 2008 Fabrice Bellard + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +#ifdef __x86_64__ +# define TCG_TARGET_REG_BITS 64 +#else +# define TCG_TARGET_REG_BITS 32 +#endif + +#endif diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b0922922b3..bc0413ead1 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -30,11 +30,9 @@ #define TCG_TARGET_INSN_UNIT_SIZE 1 =20 #ifdef __x86_64__ -# define TCG_TARGET_REG_BITS 64 # define TCG_TARGET_NB_REGS 32 # define MAX_CODE_GEN_BUFFER_SIZE (2 * GiB) #else -# define TCG_TARGET_REG_BITS 32 # define TCG_TARGET_NB_REGS 24 # define MAX_CODE_GEN_BUFFER_SIZE UINT32_MAX #endif diff --git a/tcg/loongarch64/tcg-target-reg-bits.h b/tcg/loongarch64/tcg-ta= rget-reg-bits.h new file mode 100644 index 0000000000..51373ad70a --- /dev/null +++ b/tcg/loongarch64/tcg-target-reg-bits.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific register size + * Copyright (c) 2021 WANG Xuerui + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +/* + * Loongson removed the (incomplete) 32-bit support from kernel and toolch= ain + * for the initial upstreaming of this architecture, so don't bother and j= ust + * support the LP64* ABI for now. + */ +#if defined(__loongarch64) +# define TCG_TARGET_REG_BITS 64 +#else +# error unsupported LoongArch register size +#endif + +#endif diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index 482901ac15..26f1aab780 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -29,17 +29,6 @@ #ifndef LOONGARCH_TCG_TARGET_H #define LOONGARCH_TCG_TARGET_H =20 -/* - * Loongson removed the (incomplete) 32-bit support from kernel and toolch= ain - * for the initial upstreaming of this architecture, so don't bother and j= ust - * support the LP64* ABI for now. - */ -#if defined(__loongarch64) -# define TCG_TARGET_REG_BITS 64 -#else -# error unsupported LoongArch register size -#endif - #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_NB_REGS 32 =20 diff --git a/tcg/mips/tcg-target-reg-bits.h b/tcg/mips/tcg-target-reg-bits.h new file mode 100644 index 0000000000..56fe0a725e --- /dev/null +++ b/tcg/mips/tcg-target-reg-bits.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific register size + * Copyright (c) 2008-2009 Arnaud Patard + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +#if _MIPS_SIM =3D=3D _ABIO32 +# define TCG_TARGET_REG_BITS 32 +#elif _MIPS_SIM =3D=3D _ABIN32 || _MIPS_SIM =3D=3D _ABI64 +# define TCG_TARGET_REG_BITS 64 +#else +# error "Unknown ABI" +#endif + +#endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index e52cdf0e89..fe4414c697 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -27,14 +27,6 @@ #ifndef MIPS_TCG_TARGET_H #define MIPS_TCG_TARGET_H =20 -#if _MIPS_SIM =3D=3D _ABIO32 -# define TCG_TARGET_REG_BITS 32 -#elif _MIPS_SIM =3D=3D _ABIN32 || _MIPS_SIM =3D=3D _ABI64 -# define TCG_TARGET_REG_BITS 64 -#else -# error "Unknown ABI" -#endif - #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_NB_REGS 32 =20 diff --git a/tcg/ppc/tcg-target-reg-bits.h b/tcg/ppc/tcg-target-reg-bits.h new file mode 100644 index 0000000000..0efa80e7e0 --- /dev/null +++ b/tcg/ppc/tcg-target-reg-bits.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific register size + * Copyright (c) 2008 Fabrice Bellard + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +#ifdef _ARCH_PPC64 +# define TCG_TARGET_REG_BITS 64 +#else +# define TCG_TARGET_REG_BITS 32 +#endif + +#endif diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index d68a65a9bc..9497754174 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -25,11 +25,6 @@ #ifndef PPC_TCG_TARGET_H #define PPC_TCG_TARGET_H =20 -#ifdef _ARCH_PPC64 -# define TCG_TARGET_REG_BITS 64 -#else -# define TCG_TARGET_REG_BITS 32 -#endif #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) =20 #define TCG_TARGET_NB_REGS 64 diff --git a/tcg/riscv/tcg-target-reg-bits.h b/tcg/riscv/tcg-target-reg-bit= s.h new file mode 100644 index 0000000000..761ca0d774 --- /dev/null +++ b/tcg/riscv/tcg-target-reg-bits.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific register size + * Copyright (c) 2018 SiFive, Inc + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +/* + * We don't support oversize guests. + * Since we will only build tcg once, this in turn requires a 64-bit host. + */ +#if __riscv_xlen !=3D 64 +#error "unsupported code generation mode" +#endif +#define TCG_TARGET_REG_BITS 64 + +#endif diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index ffb3d9b5b4..d23353c28e 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -25,15 +25,6 @@ #ifndef RISCV_TCG_TARGET_H #define RISCV_TCG_TARGET_H =20 -/* - * We don't support oversize guests. - * Since we will only build tcg once, this in turn requires a 64-bit host. - */ -#if __riscv_xlen !=3D 64 -#error "unsupported code generation mode" -#endif -#define TCG_TARGET_REG_BITS 64 - #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_NB_REGS 32 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) diff --git a/tcg/s390x/tcg-target-reg-bits.h b/tcg/s390x/tcg-target-reg-bit= s.h new file mode 100644 index 0000000000..b01414e09d --- /dev/null +++ b/tcg/s390x/tcg-target-reg-bits.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific register size + * Copyright (c) 2009 Ulrich Hecht + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +/* We only support generating code for 64-bit mode. */ +#if UINTPTR_MAX =3D=3D UINT64_MAX +# define TCG_TARGET_REG_BITS 64 +#else +# error "unsupported code generation mode" +#endif + +#endif diff --git a/tcg/sparc64/tcg-target-reg-bits.h b/tcg/sparc64/tcg-target-reg= -bits.h new file mode 100644 index 0000000000..34a6711013 --- /dev/null +++ b/tcg/sparc64/tcg-target-reg-bits.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific register size + * Copyright (c) 2023 Linaro + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +#define TCG_TARGET_REG_BITS 64 + +#endif diff --git a/tcg/tci/tcg-target-reg-bits.h b/tcg/tci/tcg-target-reg-bits.h new file mode 100644 index 0000000000..dcb1a203f8 --- /dev/null +++ b/tcg/tci/tcg-target-reg-bits.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific register size + * Copyright (c) 2009, 2011 Stefan Weil + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +#if UINTPTR_MAX =3D=3D UINT32_MAX +# define TCG_TARGET_REG_BITS 32 +#elif UINTPTR_MAX =3D=3D UINT64_MAX +# define TCG_TARGET_REG_BITS 64 +#else +# error Unknown pointer size for tci target +#endif + +#endif diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 60a6ed65ce..37ee10c959 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -44,14 +44,6 @@ #define TCG_TARGET_INSN_UNIT_SIZE 4 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) =20 -#if UINTPTR_MAX =3D=3D UINT32_MAX -# define TCG_TARGET_REG_BITS 32 -#elif UINTPTR_MAX =3D=3D UINT64_MAX -# define TCG_TARGET_REG_BITS 64 -#else -# error Unknown pointer size for tci target -#endif - /* Optional instructions. */ =20 #define TCG_TARGET_HAS_bswap16_i32 1 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 264a5628db..6e168e69e5 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -24,11 +24,6 @@ * THE SOFTWARE. */ =20 -/* We only support generating code for 64-bit mode. */ -#if TCG_TARGET_REG_BITS !=3D 64 -#error "unsupported code generation mode" -#endif - #include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" #include "elf.h" --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684852668; cv=none; d=zohomail.com; s=zohoarc; b=F0eM275GPtfhX8oKemTTB6gKTNKwtP7btf8j46IeKZwz8nOE3szpJHxAtvS1wJj8fd7OFhaRIjq0Kd8WXsc3XBfWAYufLSxdrDl9OBMANjrW1yNvO4myB1N9icuA5Bejlf2zeA90JDyVpZr3QknxtOyDCipFQ1tEIZaIDgznpAk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684852668; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lLJ+OrJ6ZDoNmYA/4Pv3PzTB4pxZ5PUcgKGyl5lAA2g=; b=OpfHxNJvh1YT951ta144f/NHeUr2j9WT9+jJVhJlx/1OrwvL7ZrHVzJmkr6WiGrv5wYMwhh4koD5//pEIFS2uFzDhZNAqJOULRxNaE3oFc4jey1iTrkrbwUsCQd1TZZzZk1AkkUpxCPLHo2pGmEBgRbgn4tKQzA2qLhtnwWQXjE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684852668512127.28752682830691; Tue, 23 May 2023 07:37:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1ST2-0006Nx-M7; Tue, 23 May 2023 09:54:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSK-0004u8-Mi for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:41 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSG-00032f-5U for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:39 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-64d30ab1ef2so3629462b3a.2 for ; Tue, 23 May 2023 06:53:35 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850015; x=1687442015; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=lLJ+OrJ6ZDoNmYA/4Pv3PzTB4pxZ5PUcgKGyl5lAA2g=; b=GlIsUA+NU9ZEZb0DZUO1pCi/doCaxMSUFRG9+qdRouYauJ7B5AcHv+G9y0LZyyvvuz LlSBVJggCpYHih3N2HJjoN+wGfAGVVOpOCWaLqZpuJjzsh2EelnLPLtZ7QJlO7aGwk0m 4qoPAY+az/PITqoPqvEJLDBuo3vPeZLDZAma7rpXWZBGyTHaSa69OIZV9DMUa27ewaVo 9alFtEpxc8GfpM/DwLMpWUkLYo8EFQt4prvI+EpOvsaTyPo872AEVBTerhFDswZEyMbZ eJgRcZjrRbgM0pENu2/H+mwIY1f/Pfc4gIJuB94iVOJOaVQguja/sLnfV5zzbA4lVhKX F/pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850015; x=1687442015; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lLJ+OrJ6ZDoNmYA/4Pv3PzTB4pxZ5PUcgKGyl5lAA2g=; b=CnCeuGpBsB2PskmRQrNXvHpr9hFtMIvsXSfWWKEqA4ILUvPljaoIuMBCv6QFlzSYB3 Et2pubyzd4JnrHku0b+5DOnS2T3fz+D4jzg5qcEGFxtt0lLyI5OE5R+Qmywi+R8XlUtr cw3S+GMFL61pXw5+69a1j55Imr6vnCwvACCK2Uzl39iuiWf4DhlbfLHMlPwATexFjMZE yj7AkONnBWx0o6Qen+GUCi5aCk91ZfxE3tpTueRs+gYwcQKRo4Radf6KizZhN4/1RH2W myluyU126wSZTyX8t/o9N1G7Vf+wLpU9hVQlTqRoXF/56NmkqQ3dZOI8HlVC47vgoJOo UDtA== X-Gm-Message-State: AC+VfDxWM1FfvLVSf2sISuqIoMZX9YT7cibcTbWFrdEclLAnlWphgh5i SpRj96wkwKxPc0o2qjaXlcGiPzBaMpk0BhuB9TQ= X-Google-Smtp-Source: ACHHUZ5hqoENwVVEYeuWXw8jBRXuA6A6hpj656dTGTC0jxvhM1LL+HtJaOwcCCWJTwbMfMuiZ25wVQ== X-Received: by 2002:a05:6a21:329a:b0:10b:4f58:3fef with SMTP id yt26-20020a056a21329a00b0010b4f583fefmr8923085pzb.2.1684850014820; Tue, 23 May 2023 06:53:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 13/52] target/arm: Fix test of TCG_OVERSIZED_GUEST Date: Tue, 23 May 2023 06:52:43 -0700 Message-Id: <20230523135322.678948-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684852670474100007 Content-Type: text/plain; charset="utf-8" The symbol is always defined, even if to 0. We wanted to test for TCG_OVERSIZED_GUEST =3D=3D 0. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 69c05cd9da..b0d2a05403 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -418,6 +418,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t= old_val, uint64_t new_val, S1Translate *ptw, ARMMMUFaultInfo *fi) { +#ifdef TARGET_AARCH64 uint64_t cur_val; void *host =3D ptw->out_host; =20 @@ -473,7 +474,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t= old_val, * we know that TCG_OVERSIZED_GUEST is set, which means that we are * running in round-robin mode and could only race with dma i/o. */ -#ifndef TCG_OVERSIZED_GUEST +#if !TCG_OVERSIZED_GUEST # error "Unexpected configuration" #endif bool locked =3D qemu_mutex_iothread_locked(); @@ -497,6 +498,10 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_= t old_val, #endif =20 return cur_val; +#else + /* AArch32 does not have FEAT_HADFS. */ + g_assert_not_reached(); +#endif } =20 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684853516; cv=none; d=zohomail.com; s=zohoarc; b=QbHjVVHzD0+atnFcrqMrXmoBTjuHbgpzG4F3jNanIE5EulF3fdHNDmodW7T8ah1zsCRzhOWBnlefU44GQGXe/V3wrfCONAx0v5L6hNZVpz80QrSqTUBZAx8EKEr+M0AC2Du9GasdMWgnLU+sJ7KSndtL8r1snCwG+CCraUBrBYU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684853516; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qvUxh0n09hk8B0Pf+La9yLAbiGYU5Hxqjo6tGxJpF+o=; b=OyS5BTVpv3DmfIfRzz7gcsjk4AexzMdXhGxDiC1rp89h9WKRuzbsbVIVsw2dP6GGpXOkhbILD45JtYL46Frf5ywciHl4TKXqWdIH+k32YyYZn+G761IkzgBIZmYUhxWtjAYuN54vFCpWrdBOS5Uk2FU0XKGMF2Psj2vBUDsyAGo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684853515862198.9748553441243; Tue, 23 May 2023 07:51:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SSe-0005F4-ID; Tue, 23 May 2023 09:54:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSM-0004x2-7J for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:43 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSH-00032p-Ia for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:41 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-64d3fdcadb8so3010681b3a.3 for ; Tue, 23 May 2023 06:53:36 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850015; x=1687442015; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=qvUxh0n09hk8B0Pf+La9yLAbiGYU5Hxqjo6tGxJpF+o=; b=eEDZ0KMbLWjHP+x4ZzlQcrKYn2PLA66pcUNrSjnieIn/sxASK3zVwstgJ/RIUD+qWt LdvVKhRgmLYdA4Xim4wR9JPxEQ7E/ZY9SKQexItuVwxpSiLHpGD3A0KiV9kNTsZ8T+Q+ SCgTbjatqdKH6Sx7sZmdfEInBybkgUh/HOehJ27Tb4c7Exw8Ng8PeiE+gioZKniNYv0e qCxUHnL8nzNEG8xISaDwCRplFkh7gVxccF5zm/0cqmYFkOo6anzgZd9yzCa7is3tjNpP 2kFh5PKnRVNbtxtQdAMO+AI3EjwrXODLTzpHLCcP5V7fZcnuSwvg5bLc/Lp5IRqAcYni B1uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850015; x=1687442015; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qvUxh0n09hk8B0Pf+La9yLAbiGYU5Hxqjo6tGxJpF+o=; b=gs3JslvjWGyx/y2pNML4Eb1sHR7cGz6gh+lJ4KRfekJcTyVOCmV8o7PAGdyxi1YgkH 3B/ldQ1P3SNAqZJUOcfvoYJXhMH6bmhlCjNxFbXkPbiy4ooI1U5RFzgvcB5L+VyMV3BH e6w2mUKVjz7c/X4gJWNiLnYN3i6m2jxDq8DgYrR/bda1z9SyDhhx3z3MiIYQQAboJyCJ 0PBVfb4uhMr3FpwefFa8ptDKNARnrcppOVc/otlk6R5AOSG9XXYM+SfQ+eeQnxSt04k4 ckn0mZH6wdYeORIKvsnt7BajmPdg64wJNCuBtCyud4Den4NbXW/afRNQMTkOx9ImoMv/ cMMA== X-Gm-Message-State: AC+VfDxanJFlJozxf67p4U5+6R+rgCLOIuWF50cBhnjpcqufYN9HOq8w 7csA/bEVk2Dd0ieKbbaKiLlWN4yMmh/82LMt8R0= X-Google-Smtp-Source: ACHHUZ7UsxPCmC/u+LLXrq1gx3cMsSn1JVGpGsXEfTCMMzcou/GCbA5abBlHVrX20qH/Kdw1d9E5kg== X-Received: by 2002:a05:6a00:b8f:b0:64f:4586:83fc with SMTP id g15-20020a056a000b8f00b0064f458683fcmr2286481pfj.31.1684850015611; Tue, 23 May 2023 06:53:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 14/52] tcg: Split out tcg/oversized-guest.h Date: Tue, 23 May 2023 06:52:44 -0700 Message-Id: <20230523135322.678948-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684853517937100008 Content-Type: text/plain; charset="utf-8" Move a use of TARGET_LONG_BITS out of tcg/tcg.h. Include the new file only where required. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu_ldst.h | 3 +-- include/tcg/oversized-guest.h | 23 +++++++++++++++++++++++ include/tcg/tcg.h | 9 --------- accel/tcg/cputlb.c | 1 + accel/tcg/tcg-all.c | 1 + target/arm/ptw.c | 1 + target/riscv/cpu_helper.c | 1 + 7 files changed, 28 insertions(+), 11 deletions(-) create mode 100644 include/tcg/oversized-guest.h diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index a43b34e46b..896f305ff3 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -326,8 +326,7 @@ static inline void clear_helper_retaddr(void) =20 #else =20 -/* Needed for TCG_OVERSIZED_GUEST */ -#include "tcg/tcg.h" +#include "tcg/oversized-guest.h" =20 static inline target_ulong tlb_read_idx(const CPUTLBEntry *entry, MMUAccessType access_type) diff --git a/include/tcg/oversized-guest.h b/include/tcg/oversized-guest.h new file mode 100644 index 0000000000..641b9749ff --- /dev/null +++ b/include/tcg/oversized-guest.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define TCG_OVERSIZED_GUEST + * Copyright (c) 2008 Fabrice Bellard + */ + +#ifndef EXEC_TCG_OVERSIZED_GUEST_H +#define EXEC_TCG_OVERSIZED_GUEST_H + +#include "tcg-target-reg-bits.h" +#include "cpu-param.h" + +/* + * Oversized TCG guests make things like MTTCG hard + * as we can't use atomics for cputlb updates. + */ +#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS +#define TCG_OVERSIZED_GUEST 1 +#else +#define TCG_OVERSIZED_GUEST 0 +#endif + +#endif diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 5fe90cbb42..021fc903ad 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -59,15 +59,6 @@ typedef uint64_t tcg_target_ulong; #error unsupported #endif =20 -/* Oversized TCG guests make things like MTTCG hard - * as we can't use atomics for cputlb updates. - */ -#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS -#define TCG_OVERSIZED_GUEST 1 -#else -#define TCG_OVERSIZED_GUEST 0 -#endif - #if TCG_TARGET_NB_REGS <=3D 32 typedef uint32_t TCGRegSet; #elif TCG_TARGET_NB_REGS <=3D 64 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 6beaeb0a81..32a4817139 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -40,6 +40,7 @@ #include "qemu/plugin-memory.h" #endif #include "tcg/tcg-ldst.h" +#include "tcg/oversized-guest.h" #include "exec/helper-proto.h" =20 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index a831f8d7c3..02af6a2891 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -28,6 +28,7 @@ #include "exec/replay-core.h" #include "sysemu/cpu-timers.h" #include "tcg/tcg.h" +#include "tcg/oversized-guest.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/accel.h" diff --git a/target/arm/ptw.c b/target/arm/ptw.c index b0d2a05403..b2dc223525 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -14,6 +14,7 @@ #include "cpu.h" #include "internals.h" #include "idau.h" +#include "tcg/oversized-guest.h" =20 =20 typedef struct S1Translate { diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 57d04385f1..56381aaf26 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -31,6 +31,7 @@ #include "sysemu/cpu-timers.h" #include "cpu_bits.h" #include "debug.h" +#include "tcg/oversized-guest.h" =20 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) { --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850016; x=1687442016; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=W2MnbR8ivtG8F9lQRbQhTVo1lYYIJENM+G2/D5KOadw=; b=oaovV4kt5ni/IweCdJTfci5GktCTph6BIEj1So+X0uTrUihfUr16ugT0oiuwil8ZfU DkzBl6m/FgsJnOv5ZlSxtwolX7c86HGyKYHd9pDksGAHz+G68U3RrmYfdhOjf/AzT6oC LtV12xQQFEsr7FNgrffCieYXjSZDJXTExBOrLYES5bE1N4OWOt+Cjct7x7XDjUrtpuHi 8RriEyScn1jmzZTIlSsNBKI6aiSPD5tQyKrPcqOGWBRwH3CqIUsp66KKDTL8q/T/xNzX r6apXM+EdW4XUgQTisXY+X21li9GJcNFB85GhPLZkIr5Vjxa505IZbCc/Vrq2Iy+CsWe da/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850016; x=1687442016; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W2MnbR8ivtG8F9lQRbQhTVo1lYYIJENM+G2/D5KOadw=; b=StvTfjXlh7ga0KZB9vMGaRDv3buN4g3C4vyKRu2m6FISra/V8p1Bi0PRk7sbGB2vtb azeJm4Lshg8DegqfhIvEhw5+g5I2YVAiVFCa3M3TNI+ZPT+PaItl2RKO2TnAA7b1J5a7 7R1pIPIQJGp+51T2IxnYU7pjCeLIbR5/19QpJ6c0EuFe0M/4s2nqS3mKyq2YWKjXjXEU Sj6TXV0eJfz0a808eQ31RWYKU/ND7POGS3LKiStoQTKE1XalIge4ENumQPW6MZZketTK fPIkZVrE7d5ocJRd15fLjW5bXhZM7Vz1HOSEN/XXueGuZ3EtcRx3bDxoBuf9pWM+knYo Xyzg== X-Gm-Message-State: AC+VfDyKNLjs4g78Hq14g6aSgGKYG2QUPD3gf5OJIojdBwRUafjO4J0U ij1HbbLX2UwGcZUm1LSbUVyQl0krp7UZg52/V00= X-Google-Smtp-Source: ACHHUZ5hV0lMzqMw2vGYqdmRO1JTmpmyokdZbatnOevyPS5NZ/eg5q/V/JiQUbU3u716y0WOTF1RVw== X-Received: by 2002:a05:6a20:4292:b0:10b:c7f4:66ee with SMTP id o18-20020a056a20429200b0010bc7f466eemr7076839pzj.42.1684850016459; Tue, 23 May 2023 06:53:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 15/52] tcg: Move TCGv, dup_const_tl definitions to tcg-op.h Date: Tue, 23 May 2023 06:52:45 -0700 Message-Id: <20230523135322.678948-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684853641201100001 Content-Type: text/plain; charset="utf-8" These two items are the last uses of TARGET_LONG_BITS within tcg.h, and are more in common with the other "_tl" definitions within that file. Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 15 ++++++++++++++- include/tcg/tcg.h | 19 ------------------- target/mips/tcg/translate.h | 1 + 3 files changed, 15 insertions(+), 20 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 844c666374..b8f0599f3c 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -808,19 +808,23 @@ static inline void tcg_gen_plugin_cb_end(void) } =20 #if TARGET_LONG_BITS =3D=3D 32 +typedef TCGv_i32 TCGv; #define tcg_temp_new() tcg_temp_new_i32() #define tcg_global_mem_new tcg_global_mem_new_i32 #define tcg_temp_free tcg_temp_free_i32 #define tcgv_tl_temp tcgv_i32_temp #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 -#else +#elif TARGET_LONG_BITS =3D=3D 64 +typedef TCGv_i64 TCGv; #define tcg_temp_new() tcg_temp_new_i64() #define tcg_global_mem_new tcg_global_mem_new_i64 #define tcg_temp_free tcg_temp_free_i64 #define tcgv_tl_temp tcgv_i64_temp #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64 +#else +#error Unhandled TARGET_LONG_BITS value #endif =20 void tcg_gen_qemu_ld_i32_chk(TCGv_i32, TCGTemp *, TCGArg, MemOp, TCGType); @@ -1182,6 +1186,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGAr= g offset, TCGType t); #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i64 #define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec #define tcg_gen_dup_tl tcg_gen_dup_i64 +#define dup_const_tl dup_const #else #define tcg_gen_movi_tl tcg_gen_movi_i32 #define tcg_gen_mov_tl tcg_gen_mov_i32 @@ -1296,6 +1301,14 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGA= rg offset, TCGType t); #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i32 #define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec #define tcg_gen_dup_tl tcg_gen_dup_i32 + +#define dup_const_tl(VECE, C) \ + (__builtin_constant_p(VECE) \ + ? ( (VECE) =3D=3D MO_8 ? 0x01010101ul * (uint8_t)(C) \ + : (VECE) =3D=3D MO_16 ? 0x00010001ul * (uint16_t)(C) \ + : (VECE) =3D=3D MO_32 ? 0x00000001ul * (uint32_t)(C) \ + : (qemu_build_not_reached_always(), 0)) \ + : (target_long)dup_const(VECE, C)) #endif =20 #if UINTPTR_MAX =3D=3D UINT32_MAX diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 021fc903ad..9b2833b31d 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -357,13 +357,6 @@ typedef struct TCGv_i128_d *TCGv_i128; typedef struct TCGv_ptr_d *TCGv_ptr; typedef struct TCGv_vec_d *TCGv_vec; typedef TCGv_ptr TCGv_env; -#if TARGET_LONG_BITS =3D=3D 32 -#define TCGv TCGv_i32 -#elif TARGET_LONG_BITS =3D=3D 64 -#define TCGv TCGv_i64 -#else -#error Unhandled TARGET_LONG_BITS value -#endif =20 /* call flags */ /* Helper does not read globals (either directly or through an exception).= It @@ -1163,18 +1156,6 @@ uint64_t dup_const(unsigned vece, uint64_t c); : (qemu_build_not_reached_always(), 0)) \ : dup_const(VECE, C)) =20 -#if TARGET_LONG_BITS =3D=3D 64 -# define dup_const_tl dup_const -#else -# define dup_const_tl(VECE, C) \ - (__builtin_constant_p(VECE) \ - ? ( (VECE) =3D=3D MO_8 ? 0x01010101ul * (uint8_t)(C) \ - : (VECE) =3D=3D MO_16 ? 0x00010001ul * (uint16_t)(C) \ - : (VECE) =3D=3D MO_32 ? 0x00000001ul * (uint32_t)(C) \ - : (qemu_build_not_reached_always(), 0)) \ - : (target_long)dup_const(VECE, C)) -#endif - #ifdef CONFIG_DEBUG_TCG void tcg_assert_listed_vecop(TCGOpcode); #else diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 69f85841d2..fa8bf55209 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -10,6 +10,7 @@ =20 #include "qemu/log.h" #include "exec/translator.h" +#include "tcg/tcg-op.h" =20 #define MIPS_DEBUG_DISAS 0 =20 --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851225; cv=none; d=zohomail.com; s=zohoarc; b=kgq4+e6aQoVbw72HnRdNKiqVjPdUsMktbnX+YFb8ZfhqTPBN5N38WAzv/cXQ7wAq3Xpt20++ennd/IlzteWgdmYt1zbfKmMO9xhbGMRwZsucOOOi4RzzkXgxaVKW+PnOiDtzkCNiFhWMNdtfMAIVth7sS5zQ0gA4tfKlcVrL19k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851225; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fssj0MaV2qz7TtKeP0aTqm4OgrkaBD5PHGXLzCcbdIU=; b=Zxb+A7LLezZ5hYwCgKT+YfMxSBRPuBO2z4TW9qRk35i9bCHUzD4DS+qoheu9FOQemFU8YYFtEOVJj5/FeKmHDbo16m0F+YqVAds0IOH6CZ+dI+POLGI/yAHUr4OcubTupbry9IE2YbzFv3s56jVbjCmbEmKCoALRcT+IcyuuFzc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684851225367963.3584474857454; Tue, 23 May 2023 07:13:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1ST8-0006dU-C8; Tue, 23 May 2023 09:54:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSQ-0004zo-7f for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:47 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSK-0002zz-F2 for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:45 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-64d2a613ec4so3895396b3a.1 for ; Tue, 23 May 2023 06:53:38 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850018; x=1687442018; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=fssj0MaV2qz7TtKeP0aTqm4OgrkaBD5PHGXLzCcbdIU=; b=j59NNs7cgufXNIAR9RtHvqm5n0lP2oo7iE8uD+9ObLddIWuc28yuAxQ7RSzJkKETkN mJe2uLfjjr5b+nK+ZwphbWkmN5RmEOEKcO7quaGDWKCPM2Z1WAaqRLky9ktKnXKGjoBn hfhKumiamFkAf6sduF7gskxBXugX5JNhdk7upFt76XCEkFNtIo/X+0vvPvi4sGKJ4g+W uw0hCVx8IP1sQWezxAlE1Fcw1/ZoJp35XJhmnruUgPadU2ldlXxEIr9w4imUc6DxGYeO 5Bb1w2+GfZlqY7PG9eUJIaMfhOpDhr7IngzlWpw71S7pvYpb2dnsqRG+Yf3KFQdvG90K 9Qfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850018; x=1687442018; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fssj0MaV2qz7TtKeP0aTqm4OgrkaBD5PHGXLzCcbdIU=; b=C2ehBSCPR93vZK6/0SAIzjWHbbQJFyLgr3YSwK4Ls4rEniaPnphnu+sakCmAgvbA8a +neUg8Wh0kUM6yGjE8zDta9p8SjnECJcGSXFoJr7B7oOquayJnhfd/gaZjTTlR+7rZ0Q qqB2EhdjN2tegZX/ndu0n8IeIIjaJHo3cY+oZQcu23p/Mq5hlDntjpGSLrYZCn57A8zz /Vy7xrUKqwXpVhUuC4UwC6atu8Ob1tdkkYK50GLu6LvVLkHGAiHWYawT9f4sB3yfMbil NexxOy3JsjdWB1Bm/V5Bo7C2P3xZPCaxuYJIUktKZzpII0kwOzUEOr1EKDnSOndCGjsL tI/A== X-Gm-Message-State: AC+VfDwWftCWztWUur9kMhhLk8YVt9v1R8vuinvkmrE+wRL5NU9HLRMf fjLDpqukojGC8taCbDol2M3mnWC11p+bWMoM3XU= X-Google-Smtp-Source: ACHHUZ7NuViXC/6dfeo2GUDrSaUe+cCnHfkRIbZVbxMplYWpm+uvfAt+hvhiLW41eDhj1gVZbziUKg== X-Received: by 2002:a05:6a21:3711:b0:103:d538:5ea6 with SMTP id yl17-20020a056a21371100b00103d5385ea6mr7887742pzb.48.1684850017202; Tue, 23 May 2023 06:53:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 16/52] tcg: Split tcg/tcg-op-common.h from tcg/tcg-op.h Date: Tue, 23 May 2023 06:52:46 -0700 Message-Id: <20230523135322.678948-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851226731100001 Content-Type: text/plain; charset="utf-8" Create tcg/tcg-op-common.h, moving everything that does not concern TARGET_LONG_BITS or TCGv. Adjust tcg/*.c to use the new header instead of tcg-op.h, in preparation for compiling tcg/ only once. Signed-off-by: Richard Henderson --- include/tcg/tcg-op-common.h | 996 ++++++++++++++++++++++++++++++++++ include/tcg/tcg-op.h | 1004 +---------------------------------- tcg/optimize.c | 2 +- tcg/tcg-op-gvec.c | 2 +- tcg/tcg-op-ldst.c | 2 +- tcg/tcg-op-vec.c | 2 +- tcg/tcg-op.c | 2 +- tcg/tcg.c | 2 +- tcg/tci.c | 3 +- 9 files changed, 1007 insertions(+), 1008 deletions(-) create mode 100644 include/tcg/tcg-op-common.h diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h new file mode 100644 index 0000000000..04a9ca1fc6 --- /dev/null +++ b/include/tcg/tcg-op-common.h @@ -0,0 +1,996 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Target independent opcode generation functions. + * + * Copyright (c) 2008 Fabrice Bellard + */ + +#ifndef TCG_TCG_OP_COMMON_H +#define TCG_TCG_OP_COMMON_H + +#include "tcg/tcg.h" +#include "exec/helper-proto.h" +#include "exec/helper-gen.h" + +/* Basic output routines. Not for general consumption. */ + +void tcg_gen_op1(TCGOpcode, TCGArg); +void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg); +void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg); +void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg); +void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg); +void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg= ); + +void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg); +void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg); +void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGAr= g); + +static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1) +{ + tcg_gen_op1(opc, tcgv_i32_arg(a1)); +} + +static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1) +{ + tcg_gen_op1(opc, tcgv_i64_arg(a1)); +} + +static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1) +{ + tcg_gen_op1(opc, a1); +} + +static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2) +{ + tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2)); +} + +static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2) +{ + tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2)); +} + +static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2) +{ + tcg_gen_op2(opc, tcgv_i32_arg(a1), a2); +} + +static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2) +{ + tcg_gen_op2(opc, tcgv_i64_arg(a1), a2); +} + +static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2) +{ + tcg_gen_op2(opc, a1, a2); +} + +static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1, + TCGv_i32 a2, TCGv_i32 a3) +{ + tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3)); +} + +static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1, + TCGv_i64 a2, TCGv_i64 a3) +{ + tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3)); +} + +static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1, + TCGv_i32 a2, TCGArg a3) +{ + tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3); +} + +static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1, + TCGv_i64 a2, TCGArg a3) +{ + tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3); +} + +static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, + TCGv_ptr base, TCGArg offset) +{ + tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset); +} + +static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, + TCGv_ptr base, TCGArg offset) +{ + tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset); +} + +static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, + TCGv_i32 a3, TCGv_i32 a4) +{ + tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), tcgv_i32_arg(a4)); +} + +static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, + TCGv_i64 a3, TCGv_i64 a4) +{ + tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), tcgv_i64_arg(a4)); +} + +static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a= 2, + TCGv_i32 a3, TCGArg a4) +{ + tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), a4); +} + +static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a= 2, + TCGv_i64 a3, TCGArg a4) +{ + tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), a4); +} + +static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 = a2, + TCGArg a3, TCGArg a4) +{ + tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4); +} + +static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 = a2, + TCGArg a3, TCGArg a4) +{ + tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4); +} + +static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, + TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5) +{ + tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5)); +} + +static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, + TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5) +{ + tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5)); +} + +static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a= 2, + TCGv_i32 a3, TCGv_i32 a4, TCGArg a5) +{ + tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5); +} + +static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a= 2, + TCGv_i64 a3, TCGv_i64 a4, TCGArg a5) +{ + tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5); +} + +static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 = a2, + TCGv_i32 a3, TCGArg a4, TCGArg a5) +{ + tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), a4, a5); +} + +static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 = a2, + TCGv_i64 a3, TCGArg a4, TCGArg a5) +{ + tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), a4, a5); +} + +static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, + TCGv_i32 a3, TCGv_i32 a4, + TCGv_i32 a5, TCGv_i32 a6) +{ + tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), + tcgv_i32_arg(a6)); +} + +static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, + TCGv_i64 a3, TCGv_i64 a4, + TCGv_i64 a5, TCGv_i64 a6) +{ + tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), + tcgv_i64_arg(a6)); +} + +static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a= 2, + TCGv_i32 a3, TCGv_i32 a4, + TCGv_i32 a5, TCGArg a6) +{ + tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6); +} + +static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a= 2, + TCGv_i64 a3, TCGv_i64 a4, + TCGv_i64 a5, TCGArg a6) +{ + tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6); +} + +static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 = a2, + TCGv_i32 a3, TCGv_i32 a4, + TCGArg a5, TCGArg a6) +{ + tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6); +} + +static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 = a2, + TCGv_i64 a3, TCGv_i64 a4, + TCGArg a5, TCGArg a6) +{ + tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6); +} + + +/* Generic ops. */ + +static inline void gen_set_label(TCGLabel *l) +{ + l->present =3D 1; + tcg_gen_op1(INDEX_op_set_label, label_arg(l)); +} + +void tcg_gen_br(TCGLabel *l); +void tcg_gen_mb(TCGBar); + +/** + * tcg_gen_exit_tb() - output exit_tb TCG operation + * @tb: The TranslationBlock from which we are exiting + * @idx: Direct jump slot index, or exit request + * + * See tcg/README for more info about this TCG operation. + * See also tcg.h and the block comment above TB_EXIT_MASK. + * + * For a normal exit from the TB, back to the main loop, @tb should + * be NULL and @idx should be 0. Otherwise, @tb should be valid and + * @idx should be one of the TB_EXIT_ values. + */ +void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx); + +/** + * tcg_gen_goto_tb() - output goto_tb TCG operation + * @idx: Direct jump slot index (0 or 1) + * + * See tcg/README for more info about this TCG operation. + * + * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe wit= hin + * the pages this TB resides in because we don't take care of direct jumps= when + * address mapping changes, e.g. in tlb_flush(). In user mode, there's onl= y a + * static address translation, so the destination address is always valid,= TBs + * are always invalidated properly, and direct jumps are reset when mapping + * changes. + */ +void tcg_gen_goto_tb(unsigned idx); + +/** + * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if v= alid + * @addr: Guest address of the target TB + * + * If the TB is not valid, jump to the epilogue. + * + * This operation is optional. If the TCG backend does not implement goto_= ptr, + * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argume= nt. + */ +void tcg_gen_lookup_and_goto_ptr(void); + +static inline void tcg_gen_plugin_cb_start(unsigned from, unsigned type, + unsigned wr) +{ + tcg_gen_op3(INDEX_op_plugin_cb_start, from, type, wr); +} + +static inline void tcg_gen_plugin_cb_end(void) +{ + tcg_emit_op(INDEX_op_plugin_cb_end, 0); +} + +/* 32 bit ops */ + +void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg); +void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2); +void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); +void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); +void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2); +void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, + unsigned int ofs, unsigned int len); +void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, + unsigned int ofs, unsigned int len); +void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, + unsigned int ofs, unsigned int len); +void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, + unsigned int ofs, unsigned int len); +void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, + unsigned int ofs); +void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLab= el *); +void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLab= el *); +void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, + TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, + TCGv_i32 arg1, int32_t arg2); +void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, + TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2); +void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, + TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); +void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, + TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); +void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); +void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); +void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 = arg2); +void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags); +void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_abs_i32(TCGv_i32, TCGv_i32); + +/* Replicate a value of size @vece from @in to all the lanes in @out */ +void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in); + +static inline void tcg_gen_discard_i32(TCGv_i32 arg) +{ + tcg_gen_op1_i32(INDEX_op_discard, arg); +} + +static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) +{ + if (ret !=3D arg) { + tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); + } +} + +static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); +} + +static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); +} + +static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); +} + +static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); +} + +static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); +} + +static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); +} + +static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); +} + +static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); +} + +static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 a= rg2) +{ + tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); +} + +static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 a= rg2) +{ + tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); +} + +static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 a= rg2) +{ + tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); +} + +static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 ar= g2) +{ + tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); +} + +static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 a= rg2) +{ + tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); +} + +static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 a= rg2) +{ + tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); +} + +static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 a= rg2) +{ + tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); +} + +static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 a= rg2) +{ + tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); +} + +static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 a= rg2) +{ + tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); +} + +static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) +{ + if (TCG_TARGET_HAS_neg_i32) { + tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); + } else { + tcg_gen_subfi_i32(ret, 0, arg); + } +} + +static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) +{ + if (TCG_TARGET_HAS_not_i32) { + tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); + } else { + tcg_gen_xori_i32(ret, arg, -1); + } +} + +/* 64 bit ops */ + +void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg); +void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2); +void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); +void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); +void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2); +void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, + unsigned int ofs, unsigned int len); +void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, + unsigned int ofs, unsigned int len); +void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, + unsigned int ofs, unsigned int len); +void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, + unsigned int ofs, unsigned int len); +void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, + unsigned int ofs); +void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLab= el *); +void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLab= el *); +void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, + TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, + TCGv_i64 arg1, int64_t arg2); +void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, + TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2); +void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, + TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); +void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, + TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); +void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 a= rg2); +void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 a= rg2); +void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 = arg2); +void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); +void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); +void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_abs_i64(TCGv_i64, TCGv_i64); + +/* Replicate a value of size @vece from @in to all the lanes in @out */ +void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in); + +#if TCG_TARGET_REG_BITS =3D=3D 64 +static inline void tcg_gen_discard_i64(TCGv_i64 arg) +{ + tcg_gen_op1_i64(INDEX_op_discard, arg); +} + +static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) +{ + if (ret !=3D arg) { + tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); + } +} + +static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); +} + +static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); +} + +static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); +} + +static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); +} + +static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); +} + +static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); +} + +static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); +} + +static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); +} + +static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); +} + +static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); +} + +static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); +} + +static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 a= rg2) +{ + tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); +} + +static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 a= rg2) +{ + tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); +} + +static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 a= rg2) +{ + tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); +} + +static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 ar= g2) +{ + tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); +} + +static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 a= rg2) +{ + tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); +} + +static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 a= rg2) +{ + tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); +} + +static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 a= rg2) +{ + tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); +} + +static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 a= rg2) +{ + tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); +} + +static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 a= rg2) +{ + tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); +} +#else /* TCG_TARGET_REG_BITS =3D=3D 32 */ +void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset= ); +void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset= ); + +void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); + +void tcg_gen_discard_i64(TCGv_i64 arg); +void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); +void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); +void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); +void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); +void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +#endif /* TCG_TARGET_REG_BITS */ + +static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) +{ + if (TCG_TARGET_HAS_neg_i64) { + tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); + } else { + tcg_gen_subfi_i64(ret, 0, arg); + } +} + +/* Size changing operations. */ + +void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg); +void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg); +void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high); +void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg); +void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg); +void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg); +void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg); + +void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src); +void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg); +void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi); + +static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i6= 4 hi) +{ + tcg_gen_deposit_i64(ret, lo, hi, 32, 32); +} + +/* Local load/store bit ops */ + +void tcg_gen_qemu_ld_i32_chk(TCGv_i32, TCGTemp *, TCGArg, MemOp, TCGType); +void tcg_gen_qemu_st_i32_chk(TCGv_i32, TCGTemp *, TCGArg, MemOp, TCGType); +void tcg_gen_qemu_ld_i64_chk(TCGv_i64, TCGTemp *, TCGArg, MemOp, TCGType); +void tcg_gen_qemu_st_i64_chk(TCGv_i64, TCGTemp *, TCGArg, MemOp, TCGType); +void tcg_gen_qemu_ld_i128_chk(TCGv_i128, TCGTemp *, TCGArg, MemOp, TCGType= ); +void tcg_gen_qemu_st_i128_chk(TCGv_i128, TCGTemp *, TCGArg, MemOp, TCGType= ); + +/* Atomic ops */ + +void tcg_gen_atomic_cmpxchg_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, TCGv_i3= 2, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_cmpxchg_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, TCGv_i6= 4, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_cmpxchg_i128_chk(TCGv_i128, TCGTemp *, TCGv_i128, + TCGv_i128, TCGArg, MemOp, TCGType); + +void tcg_gen_nonatomic_cmpxchg_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, TCGv= _i32, + TCGArg, MemOp, TCGType); +void tcg_gen_nonatomic_cmpxchg_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, TCGv= _i64, + TCGArg, MemOp, TCGType); +void tcg_gen_nonatomic_cmpxchg_i128_chk(TCGv_i128, TCGTemp *, TCGv_i128, + TCGv_i128, TCGArg, MemOp, TCGType); + +void tcg_gen_atomic_xchg_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_xchg_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); + +void tcg_gen_atomic_fetch_add_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_add_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_and_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_and_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_or_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_or_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_xor_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_xor_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_smin_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_smin_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_umin_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_umin_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_smax_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_smax_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_umax_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_umax_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); + +void tcg_gen_atomic_add_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_add_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_and_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_and_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_or_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_or_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_xor_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_xor_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_smin_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_smin_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_umin_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_umin_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_smax_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_smax_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_umax_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_umax_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); + +/* Vector ops */ + +void tcg_gen_mov_vec(TCGv_vec, TCGv_vec); +void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32); +void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64); +void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_lon= g); +void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t); +void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a); +void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a); +void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a); +void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_umin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); + +void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); +void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); +void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); +void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); +void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); + +void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); +void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); +void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); +void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); + +void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); + +void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r, + TCGv_vec a, TCGv_vec b); + +void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a, + TCGv_vec b, TCGv_vec c); +void tcg_gen_cmpsel_vec(TCGCond cond, unsigned vece, TCGv_vec r, + TCGv_vec a, TCGv_vec b, TCGv_vec c, TCGv_vec d); + +void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); +void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); +void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); + +/* Host pointer ops */ + +#if UINTPTR_MAX =3D=3D UINT32_MAX +# define PTR i32 +# define NAT TCGv_i32 +#else +# define PTR i64 +# define NAT TCGv_i64 +#endif + +static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o) +{ + glue(tcg_gen_ld_,PTR)((NAT)r, a, o); +} + +static inline void tcg_gen_st_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o) +{ + glue(tcg_gen_st_, PTR)((NAT)r, a, o); +} + +static inline void tcg_gen_discard_ptr(TCGv_ptr a) +{ + glue(tcg_gen_discard_,PTR)((NAT)a); +} + +static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b) +{ + glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b); +} + +static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b) +{ + glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b); +} + +static inline void tcg_gen_mov_ptr(TCGv_ptr d, TCGv_ptr s) +{ + glue(tcg_gen_mov_,PTR)((NAT)d, (NAT)s); +} + +static inline void tcg_gen_movi_ptr(TCGv_ptr d, intptr_t s) +{ + glue(tcg_gen_movi_,PTR)((NAT)d, s); +} + +static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a, + intptr_t b, TCGLabel *label) +{ + glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label); +} + +static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a) +{ +#if UINTPTR_MAX =3D=3D UINT32_MAX + tcg_gen_mov_i32((NAT)r, a); +#else + tcg_gen_ext_i32_i64((NAT)r, a); +#endif +} + +static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a) +{ +#if UINTPTR_MAX =3D=3D UINT32_MAX + tcg_gen_extrl_i64_i32((NAT)r, a); +#else + tcg_gen_mov_i64((NAT)r, a); +#endif +} + +static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a) +{ +#if UINTPTR_MAX =3D=3D UINT32_MAX + tcg_gen_extu_i32_i64(r, (NAT)a); +#else + tcg_gen_mov_i64(r, (NAT)a); +#endif +} + +static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a) +{ +#if UINTPTR_MAX =3D=3D UINT32_MAX + tcg_gen_mov_i32(r, (NAT)a); +#else + tcg_gen_extrl_i64_i32(r, (NAT)a); +#endif +} + +#undef PTR +#undef NAT + +#endif /* TCG_TCG_OP_COMMON_H */ diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index b8f0599f3c..47f1dce816 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -1,722 +1,14 @@ +/* SPDX-License-Identifier: MIT */ /* - * Tiny Code Generator for QEMU + * Target dependent opcode generation functions. * * Copyright (c) 2008 Fabrice Bellard - * - * Permission is hereby granted, free of charge, to any person obtaining a= copy - * of this software and associated documentation files (the "Software"), t= o deal - * in the Software without restriction, including without limitation the r= ights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included= in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN - * THE SOFTWARE. */ =20 #ifndef TCG_TCG_OP_H #define TCG_TCG_OP_H =20 -#include "tcg/tcg.h" -#include "exec/helper-proto.h" -#include "exec/helper-gen.h" - -/* Basic output routines. Not for general consumption. */ - -void tcg_gen_op1(TCGOpcode, TCGArg); -void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg); -void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg); -void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg); -void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg); -void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg= ); - -void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg); -void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg); -void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGAr= g); - -static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1) -{ - tcg_gen_op1(opc, tcgv_i32_arg(a1)); -} - -static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1) -{ - tcg_gen_op1(opc, tcgv_i64_arg(a1)); -} - -static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1) -{ - tcg_gen_op1(opc, a1); -} - -static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2) -{ - tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2)); -} - -static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2) -{ - tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2)); -} - -static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2) -{ - tcg_gen_op2(opc, tcgv_i32_arg(a1), a2); -} - -static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2) -{ - tcg_gen_op2(opc, tcgv_i64_arg(a1), a2); -} - -static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2) -{ - tcg_gen_op2(opc, a1, a2); -} - -static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1, - TCGv_i32 a2, TCGv_i32 a3) -{ - tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3)); -} - -static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1, - TCGv_i64 a2, TCGv_i64 a3) -{ - tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3)); -} - -static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1, - TCGv_i32 a2, TCGArg a3) -{ - tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3); -} - -static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1, - TCGv_i64 a2, TCGArg a3) -{ - tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3); -} - -static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, - TCGv_ptr base, TCGArg offset) -{ - tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset); -} - -static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, - TCGv_ptr base, TCGArg offset) -{ - tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset); -} - -static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGv_i32 a4) -{ - tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4)); -} - -static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGv_i64 a4) -{ - tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4)); -} - -static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a= 2, - TCGv_i32 a3, TCGArg a4) -{ - tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), a4); -} - -static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a= 2, - TCGv_i64 a3, TCGArg a4) -{ - tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), a4); -} - -static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 = a2, - TCGArg a3, TCGArg a4) -{ - tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4); -} - -static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 = a2, - TCGArg a3, TCGArg a4) -{ - tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4); -} - -static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5) -{ - tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5)); -} - -static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5) -{ - tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5)); -} - -static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a= 2, - TCGv_i32 a3, TCGv_i32 a4, TCGArg a5) -{ - tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5); -} - -static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a= 2, - TCGv_i64 a3, TCGv_i64 a4, TCGArg a5) -{ - tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5); -} - -static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 = a2, - TCGv_i32 a3, TCGArg a4, TCGArg a5) -{ - tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), a4, a5); -} - -static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 = a2, - TCGv_i64 a3, TCGArg a4, TCGArg a5) -{ - tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), a4, a5); -} - -static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGv_i32 a4, - TCGv_i32 a5, TCGv_i32 a6) -{ - tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), - tcgv_i32_arg(a6)); -} - -static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGv_i64 a4, - TCGv_i64 a5, TCGv_i64 a6) -{ - tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), - tcgv_i64_arg(a6)); -} - -static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a= 2, - TCGv_i32 a3, TCGv_i32 a4, - TCGv_i32 a5, TCGArg a6) -{ - tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6); -} - -static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a= 2, - TCGv_i64 a3, TCGv_i64 a4, - TCGv_i64 a5, TCGArg a6) -{ - tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6); -} - -static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 = a2, - TCGv_i32 a3, TCGv_i32 a4, - TCGArg a5, TCGArg a6) -{ - tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6); -} - -static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 = a2, - TCGv_i64 a3, TCGv_i64 a4, - TCGArg a5, TCGArg a6) -{ - tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6); -} - - -/* Generic ops. */ - -static inline void gen_set_label(TCGLabel *l) -{ - l->present =3D 1; - tcg_gen_op1(INDEX_op_set_label, label_arg(l)); -} - -void tcg_gen_br(TCGLabel *l); -void tcg_gen_mb(TCGBar); - -/* Helper calls. */ - -/* 32 bit ops */ - -void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg); -void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2); -void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); -void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); -void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2); -void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, - unsigned int ofs, unsigned int len); -void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, - unsigned int ofs, unsigned int len); -void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, - unsigned int ofs, unsigned int len); -void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, - unsigned int ofs, unsigned int len); -void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, - unsigned int ofs); -void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLab= el *); -void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLab= el *); -void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, - TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, - TCGv_i32 arg1, int32_t arg2); -void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, - TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2); -void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, - TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); -void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, - TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); -void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); -void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 a= rg2); -void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 = arg2); -void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags); -void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_abs_i32(TCGv_i32, TCGv_i32); - -/* Replicate a value of size @vece from @in to all the lanes in @out */ -void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in); - -static inline void tcg_gen_discard_i32(TCGv_i32 arg) -{ - tcg_gen_op1_i32(INDEX_op_discard, arg); -} - -static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) -{ - if (ret !=3D arg) { - tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); - } -} - -static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); -} - -static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); -} - -static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); -} - -static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); -} - -static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); -} - -static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); -} - -static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); -} - -static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); -} - -static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 a= rg2) -{ - tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); -} - -static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 a= rg2) -{ - tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); -} - -static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 a= rg2) -{ - tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); -} - -static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 ar= g2) -{ - tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); -} - -static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 a= rg2) -{ - tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); -} - -static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 a= rg2) -{ - tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); -} - -static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 a= rg2) -{ - tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); -} - -static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 a= rg2) -{ - tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); -} - -static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 a= rg2) -{ - tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); -} - -static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) -{ - if (TCG_TARGET_HAS_neg_i32) { - tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); - } else { - tcg_gen_subfi_i32(ret, 0, arg); - } -} - -static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) -{ - if (TCG_TARGET_HAS_not_i32) { - tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); - } else { - tcg_gen_xori_i32(ret, arg, -1); - } -} - -/* 64 bit ops */ - -void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg); -void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2); -void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); -void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); -void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2); -void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, - unsigned int ofs, unsigned int len); -void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, - unsigned int ofs, unsigned int len); -void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, - unsigned int ofs, unsigned int len); -void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, - unsigned int ofs, unsigned int len); -void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, - unsigned int ofs); -void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLab= el *); -void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLab= el *); -void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, - TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, - TCGv_i64 arg1, int64_t arg2); -void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, - TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2); -void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, - TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); -void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, - TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); -void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 a= rg2); -void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 a= rg2); -void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 = arg2); -void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); -void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); -void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_abs_i64(TCGv_i64, TCGv_i64); - -/* Replicate a value of size @vece from @in to all the lanes in @out */ -void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in); - -#if TCG_TARGET_REG_BITS =3D=3D 64 -static inline void tcg_gen_discard_i64(TCGv_i64 arg) -{ - tcg_gen_op1_i64(INDEX_op_discard, arg); -} - -static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) -{ - if (ret !=3D arg) { - tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); - } -} - -static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); -} - -static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); -} - -static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); -} - -static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); -} - -static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); -} - -static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); -} - -static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); -} - -static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); -} - -static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); -} - -static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); -} - -static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); -} - -static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 a= rg2) -{ - tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); -} - -static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 a= rg2) -{ - tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); -} - -static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 a= rg2) -{ - tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); -} - -static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 ar= g2) -{ - tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); -} - -static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 a= rg2) -{ - tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); -} - -static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 a= rg2) -{ - tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); -} - -static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 a= rg2) -{ - tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); -} - -static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 a= rg2) -{ - tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); -} - -static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 a= rg2) -{ - tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); -} -#else /* TCG_TARGET_REG_BITS =3D=3D 32 */ -void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset= ); -void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset= ); - -void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); - -void tcg_gen_discard_i64(TCGv_i64 arg); -void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); -void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); -void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); -void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset= ); -void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -#endif /* TCG_TARGET_REG_BITS */ - -static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) -{ - if (TCG_TARGET_HAS_neg_i64) { - tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); - } else { - tcg_gen_subfi_i64(ret, 0, arg); - } -} - -/* Size changing operations. */ - -void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg); -void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg); -void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high); -void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg); -void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg); -void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg); -void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg); - -void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src); -void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg); -void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi); - -static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i6= 4 hi) -{ - tcg_gen_deposit_i64(ret, lo, hi, 32, 32); -} - -/* QEMU specific operations. */ +#include "tcg/tcg-op-common.h" =20 #ifndef TARGET_LONG_BITS #error must include QEMU headers @@ -756,57 +48,6 @@ static inline void tcg_gen_insn_start(target_ulong pc, = target_ulong a1, # error "Unhandled number of operands to insn_start" #endif =20 -/** - * tcg_gen_exit_tb() - output exit_tb TCG operation - * @tb: The TranslationBlock from which we are exiting - * @idx: Direct jump slot index, or exit request - * - * See tcg/README for more info about this TCG operation. - * See also tcg.h and the block comment above TB_EXIT_MASK. - * - * For a normal exit from the TB, back to the main loop, @tb should - * be NULL and @idx should be 0. Otherwise, @tb should be valid and - * @idx should be one of the TB_EXIT_ values. - */ -void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx); - -/** - * tcg_gen_goto_tb() - output goto_tb TCG operation - * @idx: Direct jump slot index (0 or 1) - * - * See tcg/README for more info about this TCG operation. - * - * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe wit= hin - * the pages this TB resides in because we don't take care of direct jumps= when - * address mapping changes, e.g. in tlb_flush(). In user mode, there's onl= y a - * static address translation, so the destination address is always valid,= TBs - * are always invalidated properly, and direct jumps are reset when mapping - * changes. - */ -void tcg_gen_goto_tb(unsigned idx); - -/** - * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if v= alid - * @addr: Guest address of the target TB - * - * If the TB is not valid, jump to the epilogue. - * - * This operation is optional. If the TCG backend does not implement goto_= ptr, - * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argume= nt. - */ -void tcg_gen_lookup_and_goto_ptr(void); - -static inline void tcg_gen_plugin_cb_start(unsigned from, unsigned type, - unsigned wr) -{ - tcg_gen_op3(INDEX_op_plugin_cb_start, from, type, wr); -} - -static inline void tcg_gen_plugin_cb_end(void) -{ - tcg_emit_op(INDEX_op_plugin_cb_end, 0); -} - #if TARGET_LONG_BITS =3D=3D 32 typedef TCGv_i32 TCGv; #define tcg_temp_new() tcg_temp_new_i32() @@ -827,13 +68,6 @@ typedef TCGv_i64 TCGv; #error Unhandled TARGET_LONG_BITS value #endif =20 -void tcg_gen_qemu_ld_i32_chk(TCGv_i32, TCGTemp *, TCGArg, MemOp, TCGType); -void tcg_gen_qemu_st_i32_chk(TCGv_i32, TCGTemp *, TCGArg, MemOp, TCGType); -void tcg_gen_qemu_ld_i64_chk(TCGv_i64, TCGTemp *, TCGArg, MemOp, TCGType); -void tcg_gen_qemu_st_i64_chk(TCGv_i64, TCGTemp *, TCGArg, MemOp, TCGType); -void tcg_gen_qemu_ld_i128_chk(TCGv_i128, TCGTemp *, TCGArg, MemOp, TCGType= ); -void tcg_gen_qemu_st_i128_chk(TCGv_i128, TCGTemp *, TCGArg, MemOp, TCGType= ); - static inline void tcg_gen_qemu_ld_i32(TCGv_i32 v, TCGv a, TCGArg i, MemOp m) { @@ -870,91 +104,6 @@ tcg_gen_qemu_st_i128(TCGv_i128 v, TCGv a, TCGArg i, Me= mOp m) tcg_gen_qemu_st_i128_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); } =20 -void tcg_gen_atomic_cmpxchg_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, TCGv_i3= 2, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_cmpxchg_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, TCGv_i6= 4, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_cmpxchg_i128_chk(TCGv_i128, TCGTemp *, TCGv_i128, - TCGv_i128, TCGArg, MemOp, TCGType); - -void tcg_gen_nonatomic_cmpxchg_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, TCGv= _i32, - TCGArg, MemOp, TCGType); -void tcg_gen_nonatomic_cmpxchg_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, TCGv= _i64, - TCGArg, MemOp, TCGType); -void tcg_gen_nonatomic_cmpxchg_i128_chk(TCGv_i128, TCGTemp *, TCGv_i128, - TCGv_i128, TCGArg, MemOp, TCGType); - -void tcg_gen_atomic_xchg_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_xchg_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); - -void tcg_gen_atomic_fetch_add_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_add_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_and_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_and_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_or_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_or_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_xor_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_xor_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_smin_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_smin_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_umin_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_umin_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_smax_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_smax_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_umax_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_umax_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); - -void tcg_gen_atomic_add_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_add_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_and_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_and_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_or_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_or_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_xor_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_xor_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_smin_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_smin_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_umin_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_umin_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_smax_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_smax_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_umax_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_umax_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); - #define DEF_ATOMIC2(N, S) \ static inline void N##_##S(TCGv_##S r, TCGv a, TCGv_##S v, \ TCGArg i, MemOp m) \ @@ -1013,63 +162,6 @@ DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64) #undef DEF_ATOMIC2 #undef DEF_ATOMIC3 =20 -void tcg_gen_mov_vec(TCGv_vec, TCGv_vec); -void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32); -void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64); -void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_lon= g); -void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t); -void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a); -void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a); -void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a); -void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_umin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); - -void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); -void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); -void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); -void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); -void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); - -void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); -void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); -void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); -void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); - -void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); -void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); -void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); -void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); -void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); - -void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r, - TCGv_vec a, TCGv_vec b); - -void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a, - TCGv_vec b, TCGv_vec c); -void tcg_gen_cmpsel_vec(TCGCond cond, unsigned vece, TCGv_vec r, - TCGv_vec a, TCGv_vec b, TCGv_vec c, TCGv_vec d); - -void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); -void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); -void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); - #if TARGET_LONG_BITS =3D=3D 64 #define tcg_gen_movi_tl tcg_gen_movi_i64 #define tcg_gen_mov_tl tcg_gen_mov_i64 @@ -1309,94 +401,6 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGAr= g offset, TCGType t); : (VECE) =3D=3D MO_32 ? 0x00000001ul * (uint32_t)(C) \ : (qemu_build_not_reached_always(), 0)) \ : (target_long)dup_const(VECE, C)) -#endif - -#if UINTPTR_MAX =3D=3D UINT32_MAX -# define PTR i32 -# define NAT TCGv_i32 -#else -# define PTR i64 -# define NAT TCGv_i64 -#endif - -static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o) -{ - glue(tcg_gen_ld_,PTR)((NAT)r, a, o); -} - -static inline void tcg_gen_st_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o) -{ - glue(tcg_gen_st_, PTR)((NAT)r, a, o); -} - -static inline void tcg_gen_discard_ptr(TCGv_ptr a) -{ - glue(tcg_gen_discard_,PTR)((NAT)a); -} - -static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b) -{ - glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b); -} - -static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b) -{ - glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b); -} - -static inline void tcg_gen_mov_ptr(TCGv_ptr d, TCGv_ptr s) -{ - glue(tcg_gen_mov_,PTR)((NAT)d, (NAT)s); -} - -static inline void tcg_gen_movi_ptr(TCGv_ptr d, intptr_t s) -{ - glue(tcg_gen_movi_,PTR)((NAT)d, s); -} - -static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a, - intptr_t b, TCGLabel *label) -{ - glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label); -} - -static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a) -{ -#if UINTPTR_MAX =3D=3D UINT32_MAX - tcg_gen_mov_i32((NAT)r, a); -#else - tcg_gen_ext_i32_i64((NAT)r, a); -#endif -} - -static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a) -{ -#if UINTPTR_MAX =3D=3D UINT32_MAX - tcg_gen_extrl_i64_i32((NAT)r, a); -#else - tcg_gen_mov_i64((NAT)r, a); -#endif -} - -static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a) -{ -#if UINTPTR_MAX =3D=3D UINT32_MAX - tcg_gen_extu_i32_i64(r, (NAT)a); -#else - tcg_gen_mov_i64(r, (NAT)a); -#endif -} - -static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a) -{ -#if UINTPTR_MAX =3D=3D UINT32_MAX - tcg_gen_mov_i32(r, (NAT)a); -#else - tcg_gen_extrl_i64_i32(r, (NAT)a); -#endif -} - -#undef PTR -#undef NAT =20 +#endif /* TARGET_LONG_BITS =3D=3D 64 */ #endif /* TCG_TCG_OP_H */ diff --git a/tcg/optimize.c b/tcg/optimize.c index bf975a3a6c..d2156367a3 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -25,7 +25,7 @@ =20 #include "qemu/osdep.h" #include "qemu/int128.h" -#include "tcg/tcg-op.h" +#include "tcg/tcg-op-common.h" #include "tcg-internal.h" =20 #define CASE_OP_32_64(x) \ diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index f51bcaa87b..7a9599e49e 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" -#include "tcg/tcg-op.h" +#include "tcg/tcg-op-common.h" #include "tcg/tcg-op-gvec.h" #include "tcg/tcg-gvec-desc.h" =20 diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index f4e508cb68..aae74f4341 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -26,7 +26,7 @@ #include "exec/exec-all.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" -#include "tcg/tcg-op.h" +#include "tcg/tcg-op-common.h" #include "tcg/tcg-mo.h" #include "exec/plugin-gen.h" #include "tcg-internal.h" diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index aeeb2435cb..35d67eeda0 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" -#include "tcg/tcg-op.h" +#include "tcg/tcg-op-common.h" #include "tcg/tcg-mo.h" #include "tcg-internal.h" =20 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index edbd1c61d7..8c1ad49c4e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -26,7 +26,7 @@ #include "exec/exec-all.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" -#include "tcg/tcg-op.h" +#include "tcg/tcg-op-common.h" #include "exec/plugin-gen.h" #include "tcg-internal.h" =20 diff --git a/tcg/tcg.c b/tcg/tcg.c index 35bbc03ede..32cd0e338d 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -45,7 +45,7 @@ =20 #include "exec/exec-all.h" #include "exec/tlb-common.h" -#include "tcg/tcg-op.h" +#include "tcg/tcg-op-common.h" =20 #if UINTPTR_MAX =3D=3D UINT32_MAX # define ELF_CLASS ELFCLASS32 diff --git a/tcg/tci.c b/tcg/tci.c index bab4397bc5..813572ff39 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -18,8 +18,7 @@ */ =20 #include "qemu/osdep.h" -#include "exec/cpu_ldst.h" -#include "tcg/tcg-op.h" +#include "tcg/tcg.h" #include "tcg/tcg-ldst.h" #include =20 --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850018; x=1687442018; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=WPQBaswIL5gnAeFH0J21sek4FINXtGXGMKXaBWTmSWg=; b=iecY4XBe8xGsyvF5KZfOu2H1chE4haPRyj0TjMwk4dduer4AKHPHa+nGHsO9IB8VSa 9P09LZJ4ZC4+Ds5vZewgYg19CDNZi3sZvZrB82tkq43G9eMudLg2m7hWPjCcB/6A9+HR oAvN6rhHmXyUAwhTmWpFM1Ov7WAzijzhkpZ0t+cCt13j9hzgD5VXYrMpKWD+jqB3tfp+ WPiqpkK+BQ803+3AHkiregeTLlLj5zacXWb7f75sNXhDyCqQqlWuKd3vJ1lNfKj1TXti 27kacT55Gz0Wtmzd0hiRAn69q0owhvaaDuBtCLpHFgpg38xql+meX77DtV8azGsHLHga f3eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850018; x=1687442018; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WPQBaswIL5gnAeFH0J21sek4FINXtGXGMKXaBWTmSWg=; b=D6kCd+LDrL6nxUH9ZN/6IwDIcfBUUJ2UCwWGY9RdAVn3NbYQgwpV/rO383U9IpCZQn xmyeJ66EsCPgjdbHVwRHxR4dXU/BBjtC7NdwUJLtRF4B0obH7IXd3Ezn8ypblBfYV8XY Y3u4g/PtYBE3i81RYnjnQBkFjPRZcuIDHpLW1zTkRwYn2VlB76WUKrWRl2Ahatz1fi5S UwyPo2cBl7c8UWKihh64XE3gmNzzJMZTlc3X2ed7VUWHs2IsbTgSnd2eNsPPNnnWzPkQ YA9tJvqd0dmln0xVMEgT8RStywjrAzIaYjthaqtSyPlYxoE3BePXiGfGH0m6QcE8vo9J /PQA== X-Gm-Message-State: AC+VfDwvVSMsTc7XEX+y0pRi87snA06xjQYuUqGDpb7VhIR9kLztjjgO p671UKwQolf0aB88r+fGv7Gu5p2c/11paL5PyWw= X-Google-Smtp-Source: ACHHUZ6tg0IQgSFe0zDpx6/eovL/7T4HQN18X2c/NKUeewGRnyQr7el3MCKr8+TO/oaPEyLxD4hsXw== X-Received: by 2002:a05:6a00:1487:b0:64f:3fc8:5d26 with SMTP id v7-20020a056a00148700b0064f3fc85d26mr3460352pfu.9.1684850018110; Tue, 23 May 2023 06:53:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 17/52] target/arm: Include helper-gen.h in translator.h Date: Tue, 23 May 2023 06:52:47 -0700 Message-Id: <20230523135322.678948-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684853478315100005 Content-Type: text/plain; charset="utf-8" This had been included via tcg-op-common.h via tcg-op.h, but that is going away. It is needed for inlines within translator.h, so we might as well do it there and not individually in each translator c file. Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 1 + target/arm/tcg/translate-a64.c | 2 -- target/arm/tcg/translate-sme.c | 1 - target/arm/tcg/translate-sve.c | 2 -- target/arm/tcg/translate.c | 2 -- 5 files changed, 1 insertion(+), 7 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index a9d1f4adc2..868a3abd0d 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -2,6 +2,7 @@ #define TARGET_ARM_TRANSLATE_H =20 #include "exec/translator.h" +#include "exec/helper-gen.h" #include "internals.h" =20 =20 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 741a608739..bc0cb98955 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -29,8 +29,6 @@ #include "qemu/host-utils.h" #include "semihosting/semihost.h" #include "exec/gen-icount.h" -#include "exec/helper-proto.h" -#include "exec/helper-gen.h" #include "exec/log.h" #include "cpregs.h" #include "translate-a64.h" diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index e3adba314e..b0812d9dd6 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -23,7 +23,6 @@ #include "tcg/tcg-op-gvec.h" #include "tcg/tcg-gvec-desc.h" #include "translate.h" -#include "exec/helper-gen.h" #include "translate-a64.h" #include "fpu/softfloat.h" =20 diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 92ab290106..106baf311f 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -27,8 +27,6 @@ #include "arm_ldst.h" #include "translate.h" #include "internals.h" -#include "exec/helper-proto.h" -#include "exec/helper-gen.h" #include "exec/log.h" #include "translate-a64.h" #include "fpu/softfloat.h" diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 7468476724..c89825ad6a 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -30,8 +30,6 @@ #include "qemu/bitops.h" #include "arm_ldst.h" #include "semihosting/semihost.h" -#include "exec/helper-proto.h" -#include "exec/helper-gen.h" #include "exec/log.h" #include "cpregs.h" =20 --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851238; cv=none; d=zohomail.com; s=zohoarc; b=gmQ761ZV11RN7N5edJurzYDvvANytEHZEW276f6JhyM6ip5UfXCCgFx4KlXeo1eYKuCNB76T/w2iFBQdweirudEHUeYE+xwKGT/9fRBbRVq9VHp5fz1qWD0T+C9rMyxhXhPcmllQFbGmYHenY0EQyUpTI3HCsRG3DQQ5Oj1wx6U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851238; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=byv7QZQSLFh7nyIZS76P7wjGuStySRLZzDv41rBbtmM=; b=lw3XdNiga1Zzheybu0ypzL/zrLhItORGA/huqVuBxa7FuuV9FwFdzsJ9sto+ArKtaL3f5vCFeN0HwqnzQ9+k/2M0vSB4H767nNg0y9Df/yfgjI1T/cnbkRF/o+CXosODVIFO44nixBBlXs4zq05tallHIhFU3Rsbirw1dbpxCq8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684851238230179.33181149932227; Tue, 23 May 2023 07:13:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1ST0-0006CC-20; Tue, 23 May 2023 09:54:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSN-0004xw-CN for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:45 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSK-00033Z-H9 for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:42 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-64d2e8a842cso3796494b3a.3 for ; Tue, 23 May 2023 06:53:40 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850019; x=1687442019; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=byv7QZQSLFh7nyIZS76P7wjGuStySRLZzDv41rBbtmM=; b=K57IpWc/RZ/KgPib/q1zfVCJZ7ZU9iPnZqbB0FMYkLL3w9vUKWRuDKyJw94n+ewC61 o+m6aEZ/fTjGxt2Dnn5Yzym5oVv2fXr4ZGUjygOulK9dcOlGLjo2gfo3PvlfahMRQYpC dAjteAaAVoB4AtZpsqkRU36/H0u4B5QKCI0Yx6LvbSwCZwzeqJ0zDcGhdNlkoCtAtP8f fZl0zz1eCs6AmzR0vGT3J83c255eVktxVMo/6SM2h3WvzEFU+1ebllCH6jh0n9m2VrOF 4JhAG0LoHKfEr5YfkDofoeYQ7GcyIRV1P4L0OpJ6EbSrCxFS34/N37uJZ/ys7fM125WP vHlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850019; x=1687442019; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=byv7QZQSLFh7nyIZS76P7wjGuStySRLZzDv41rBbtmM=; b=B5haMpyPTQEmadvlNoNGGKcBaZsALFH3haB0JReFiQMJtnVWpVqakq1jE2q6IrrBqW D4MCoXK490XJ2EFYHv6HQcpgLpSKT4bYF7jqs/auql8lqHw8ZqinPnaaFLhXTa59Z7I+ dyU8Yfgryipt+Z4e7hcmduXU8LBKpC5zcVOnm06TriqmctPmVxCisQYmvH9r1BfhM6g9 seWn39d63pafkwsK1iuaZJe7DHsvMHdcT3Cx938h3JYHCEy38+RDCTrPzM6drE1LSjBL ng5zmUv70XsgE5Kgfd4FcCJ8Iu/v6nNxy0ogppWasHDRwnJ+x1D5zCOfosT4eik8695B H8tA== X-Gm-Message-State: AC+VfDxFlDlbJpppL3GB6vJlSzrCb9Z8udnZhfxGYXwdNHBMBe9oSXaq f0qkpWI9LvXe9L2TqhyxV+nwBg8QbVO/p6eC35M= X-Google-Smtp-Source: ACHHUZ48TvdEzh4UYf/3DKg+teDXTS/hvx3s7IpOcourvdSlmaow8IzJvKtJO7iPev0/eWZZMShwEg== X-Received: by 2002:aa7:88c4:0:b0:64c:f4f9:de87 with SMTP id k4-20020aa788c4000000b0064cf4f9de87mr19587500pff.18.1684850019001; Tue, 23 May 2023 06:53:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 18/52] target/hexagon: Include helper-gen.h where needed Date: Tue, 23 May 2023 06:52:48 -0700 Message-Id: <20230523135322.678948-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851239002100005 Content-Type: text/plain; charset="utf-8" This had been included via tcg-op-common.h via tcg-op.h, but that is going away. In idef-parser.y, shuffle some tcg related includes into a more logical order. Signed-off-by: Richard Henderson --- target/hexagon/genptr.c | 1 + target/hexagon/translate.c | 1 + target/hexagon/idef-parser/idef-parser.y | 3 ++- 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index cb2aa28a19..2cb7061a69 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -20,6 +20,7 @@ #include "internal.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" +#include "exec/helper-gen.h" #include "insn.h" #include "opcodes.h" #include "translate.h" diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index b18f1a9051..f36442c6d5 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -20,6 +20,7 @@ #include "cpu.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" +#include "exec/helper-gen.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "internal.h" diff --git a/target/hexagon/idef-parser/idef-parser.y b/target/hexagon/idef= -parser/idef-parser.y index 5c983954ed..cd2612eb8c 100644 --- a/target/hexagon/idef-parser/idef-parser.y +++ b/target/hexagon/idef-parser/idef-parser.y @@ -843,13 +843,14 @@ int main(int argc, char **argv) fputs("#include \"qemu/log.h\"\n", output_file); fputs("#include \"cpu.h\"\n", output_file); fputs("#include \"internal.h\"\n", output_file); + fputs("#include \"tcg/tcg.h\"\n", output_file); fputs("#include \"tcg/tcg-op.h\"\n", output_file); + fputs("#include \"exec/helper-gen.h\"\n", output_file); fputs("#include \"insn.h\"\n", output_file); fputs("#include \"opcodes.h\"\n", output_file); fputs("#include \"translate.h\"\n", output_file); fputs("#define QEMU_GENERATE\n", output_file); fputs("#include \"genptr.h\"\n", output_file); - fputs("#include \"tcg/tcg.h\"\n", output_file); fputs("#include \"macros.h\"\n", output_file); fprintf(output_file, "#include \"%s\"\n", argv[ARG_INDEX_EMITTER_H]); =20 --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684854403; cv=none; d=zohomail.com; s=zohoarc; b=Mp05H0t/gfsh7dX90Ru8s7AM7W+XtSpBipB7lcpvzRQUXRcUpwxyTTRhHjtujJ4nr+9/mICSVL2HzQlCgk5czs5yHlUDWArbKtLM+XmgQcU5t3t+1Il1l+Jt5by5e9pC8nYFXbL5dFRY8A93mtKPj0KXJTPAjA/1liqvo2Ufsl0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684854403; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AcrCNc6GHVuEoru3kSHnYFGlGWejrWeSQLskEC2DiQ4=; b=IzQGdNaPKo9WODOq+u/9uvi63Jki/JY+3OzJlAGIzfh48sIxmCkUHQdfZyJs1VdQd09PSF9q5/1OM4+jy5+5K3p/OoMK20YsrlF2Buomqa+0GTxhN+9edPvSdDrOh2NX4ttybv+fhPJMuglFD5rressr8bd6weONJ0yLd113w6s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684854403831140.68440807549314; Tue, 23 May 2023 08:06:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1ST4-0006Rk-Gc; Tue, 23 May 2023 09:54:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSN-0004xx-JT for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:45 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSL-00033g-B4 for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:43 -0400 Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-64d30ab1ef2so3629540b3a.2 for ; Tue, 23 May 2023 06:53:40 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850020; x=1687442020; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=AcrCNc6GHVuEoru3kSHnYFGlGWejrWeSQLskEC2DiQ4=; b=JjWvy5SWQ9Hbp0Jn6RSz8Jh91K485QojHlGqMJ2JlQfR2BPMC4y2NFRjDrICnPhq2R yDe9/yuYWeVDVVc2jI7zdJdP7Te+flS1QnDWYNl0r8w6pB/qDRaCKX/N30YxBSwow1SM re2XlsnAKdgTCMC6IAA9ZYNPH7B9jD/J7QyTz46MB99eEXsqYTno3Bpdr2mim3OdQ7UQ Pyn2T+A/64HVoMAjrPI6f/nhEZYAaEcgq66aNTjAGBJ3quTH6irf1koz5eicS1EGJafL c57IC7fWFI1dcIfPHZCQi1yGls43diSReva2N0OVrAEWy6DhdzRVC5S8sdLya3+X8F/+ rBHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850020; x=1687442020; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AcrCNc6GHVuEoru3kSHnYFGlGWejrWeSQLskEC2DiQ4=; b=a4k36KuLCeR40UMCQV12GiYFFy3pKNO3v0Wb3bzqMhwDsXi2hsGDk8bS9zGhubePda /KvJiEmo9RP9tvr89Kcm7y5XdrOBxqdgnSQ+XAFX53Q19MEF+1vfoaFK+hFd2oDj07KW gk20M+YGIbJGoDgfiJp+QMCVF8Dv2E0zEei3vaPQszDJ58Di8AYEJFrX8nlP3IH0ZiL5 K/TN1L3asVNgk+mHVpWF0Y8rzRvsKcxjJ5c0hV/vLd4vnTrTVZk3/lI4bIJmUgE0+gjx YC0BQTjU1k1/MeKfN38L/+eJCS8NHwFJfZ+nUMDqECuc4SwSb+d0hXQmMSk7OpME/LZ1 iS8g== X-Gm-Message-State: AC+VfDxbUqrpDY9mqcA+xVqx5OyZkN/crG5Vf/zKcDMZHkrD5l2BbOpe AtdEpXVGwDMNMegpc3WAzjEubSP9nSTAkyBKDwo= X-Google-Smtp-Source: ACHHUZ4rKJN6kTVggyWkUxKh18TLMoL0hEqNIqo9f9AVhcrrSyPQxAKp+qDl03SGlHhtOoEYofutxw== X-Received: by 2002:a05:6a00:804:b0:647:d698:56d2 with SMTP id m4-20020a056a00080400b00647d69856d2mr19243743pfk.27.1684850019920; Tue, 23 May 2023 06:53:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 19/52] tcg: Remove outdated comments in helper-head.h Date: Tue, 23 May 2023 06:52:49 -0700 Message-Id: <20230523135322.678948-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684854404362100002 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- include/exec/helper-head.h | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index f863a6ef5d..a355ef8ebe 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -1,18 +1,6 @@ -/* Helper file for declaring TCG helper functions. - Used by other helper files. - - Targets should use DEF_HELPER_N and DEF_HELPER_FLAGS_N to declare helper - functions. Names should be specified without the helper_ prefix, and - the return and argument types specified. 3 basic types are understood - (i32, i64 and ptr). Additional aliases are provided for convenience and - to match the types used by the C helper implementation. - - The target helper.h should be included in all files that use/define - helper functions. THis will ensure that function prototypes are - consistent. In addition it should be included an extra two times for - helper.c, defining: - GEN_HELPER 1 to produce op generation functions (gen_helper_*) - GEN_HELPER 2 to do runtime registration helper functions. +/* + * Helper file for declaring TCG helper functions. + * Used by other helper files. */ =20 #ifndef EXEC_HELPER_HEAD_H --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684853644; cv=none; d=zohomail.com; s=zohoarc; b=lfiQ50NGaoMzaTrZ28PuYg1aSruSzH7xdipHQwKVuIGcDtVdPwMRqFTn9d5Iv1clIJozdgN4wZaC/bnZIjCdeZ+LH0yo4g9Rwa6R18DnfGvYgpiTLRrzlwjPL7VJWQsulV648IfQkO0bs6O59FsZFw6rgy4fsGz6YoYiZSqzfBM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684853644; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xd2AyLWHfL7nMXWfsFoMvsK6i0qMKcBbZmk4IdtvNsM=; b=kAxxT5bHAZ0lu/ymnaDJ5DTolOUTznThS5rrhg40FRExPisq8RPQALqNRg9Oy5h8tYZ8O/goC9xVc/cZ/N6LhAstYWmS/ntuvGJQGMPsuUH4OGhLlKJzDoPtWOB8rZQcJynDTe8NjlfrOvNCtw7mkYKp7GRtP46h4ucTq0LERVU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684853644809389.91670322990956; Tue, 23 May 2023 07:54:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1ST5-0006U8-Bc; Tue, 23 May 2023 09:54:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSO-0004zc-9n for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:45 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSM-000344-33 for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:43 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-64d57cd373fso2121930b3a.1 for ; Tue, 23 May 2023 06:53:41 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850021; x=1687442021; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=xd2AyLWHfL7nMXWfsFoMvsK6i0qMKcBbZmk4IdtvNsM=; b=N6EAj0dT8RVX36gl57F8SVJxaAvf92l6swqOEW+BwPfafKlxMnD+bDGsCET4mr57Js tDkf8SBXaZ4LxxVZpdgkgyt5GXN6zldRNLtiqawlEL+5QfRB7nm6h1SWccHmE+erpX+E hrE104bKspdSYUMQuWWXdX/iQXUhp52OPfDhNYR1MuNn168NmqODlUQURvBFcaC18ly5 WkVzcVv/svw4briMsr7vlPpluGm87CDW+arRkO2ZdaQ9KjBS6VxQnq9C5TGhzetBtN6r sR33cJ+wHWPV7kKO7QorC+55ViSjtGpp4Bzu6P+GUA4NmYfmPjvlTvNEGa8Bp1ntRUPy NVzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850021; x=1687442021; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xd2AyLWHfL7nMXWfsFoMvsK6i0qMKcBbZmk4IdtvNsM=; b=E7mrmtOVUC21jfPvvI3ezXh1D25oICKfMwyGl57At2IE/r513YGKAvdcLmqO6E9MJA T6BlTq8YdnqvwJy3GrN1NrqCtyb7fQ+Iwhty+BMN3bZBoehyrov9CVcu464ODo9qp6ts nOlro234LpNiJP1hC7qtYmapKlgMt9PrEgT4syYTqV6iKeokgFm/7oVrTq8X0ZGkf4xi 6YFUg7dciu5dg9qmSDH3c1gEuLhVCPmWagwdU38AozEsIPWWaoR6FoajV12/5zC9f97T BPMa9QPH22IgDPAFtub0ztK7eXVsR6nbKmJk/f1APJXoODW+gnVgR1qiz332/AW4aPnS QFbA== X-Gm-Message-State: AC+VfDxL5N6wxZaP0uWZZG9ZTvEdv33+7N0Zt7wP+u35PwGa5myhn5av ItdEmCH2xk978mdcGmoSadel2vpvVTZ5LMQ/uaI= X-Google-Smtp-Source: ACHHUZ4478cqdTYdD5lA3bBXD2dAsPHFEDZ95ImOVowZbMlMFgZpU3OBkxYmB7eaU7wqVcraX8+UBg== X-Received: by 2002:a05:6a20:938e:b0:10b:60c1:2999 with SMTP id x14-20020a056a20938e00b0010b60c12999mr8071407pzh.22.1684850020785; Tue, 23 May 2023 06:53:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 20/52] tcg: Move TCGHelperInfo and dependencies to tcg/helper-info.h Date: Tue, 23 May 2023 06:52:50 -0700 Message-Id: <20230523135322.678948-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684853645201100001 Content-Type: text/plain; charset="utf-8" This will be required outside of tcg-internal.h soon. Signed-off-by: Richard Henderson --- include/tcg/helper-info.h | 59 +++++++++++++++++++++++++++++++++++++++ tcg/tcg-internal.h | 47 +------------------------------ 2 files changed, 60 insertions(+), 46 deletions(-) create mode 100644 include/tcg/helper-info.h diff --git a/include/tcg/helper-info.h b/include/tcg/helper-info.h new file mode 100644 index 0000000000..f65f81c2e7 --- /dev/null +++ b/include/tcg/helper-info.h @@ -0,0 +1,59 @@ +/* + * TCG Helper Infomation Structure + * + * Copyright (c) 2023 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef TCG_HELPER_INFO_H +#define TCG_HELPER_INFO_H + +#ifdef CONFIG_TCG_INTERPRETER +#include +#endif + +/* + * Describe the calling convention of a given argument type. + */ +typedef enum { + TCG_CALL_RET_NORMAL, /* by registers */ + TCG_CALL_RET_BY_REF, /* for i128, by reference */ + TCG_CALL_RET_BY_VEC, /* for i128, by vector register */ +} TCGCallReturnKind; + +typedef enum { + TCG_CALL_ARG_NORMAL, /* by registers (continuing onto stack) */ + TCG_CALL_ARG_EVEN, /* like normal, but skipping odd slots */ + TCG_CALL_ARG_EXTEND, /* for i32, as a sign/zero-extended i64 */ + TCG_CALL_ARG_EXTEND_U, /* ... as a zero-extended i64 */ + TCG_CALL_ARG_EXTEND_S, /* ... as a sign-extended i64 */ + TCG_CALL_ARG_BY_REF, /* for i128, by reference, first */ + TCG_CALL_ARG_BY_REF_N, /* ... by reference, subsequent */ +} TCGCallArgumentKind; + +typedef struct TCGCallArgumentLoc { + TCGCallArgumentKind kind : 8; + unsigned arg_slot : 8; + unsigned ref_slot : 8; + unsigned arg_idx : 4; + unsigned tmp_subindex : 2; +} TCGCallArgumentLoc; + +typedef struct TCGHelperInfo { + void *func; + const char *name; +#ifdef CONFIG_TCG_INTERPRETER + ffi_cif *cif; +#endif + unsigned typemask : 32; + unsigned flags : 8; + unsigned nr_in : 8; + unsigned nr_out : 8; + TCGCallReturnKind out_kind : 8; + + /* Maximum physical arguments are constrained by TCG_TYPE_I128. */ + TCGCallArgumentLoc in[MAX_CALL_IARGS * (128 / TCG_TARGET_REG_BITS)]; +} TCGHelperInfo; + +#endif /* TCG_HELPER_INFO_H */ diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 67b698bd5c..fbe62b31b8 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -25,55 +25,10 @@ #ifndef TCG_INTERNAL_H #define TCG_INTERNAL_H =20 -#ifdef CONFIG_TCG_INTERPRETER -#include -#endif +#include "tcg/helper-info.h" =20 #define TCG_HIGHWATER 1024 =20 -/* - * Describe the calling convention of a given argument type. - */ -typedef enum { - TCG_CALL_RET_NORMAL, /* by registers */ - TCG_CALL_RET_BY_REF, /* for i128, by reference */ - TCG_CALL_RET_BY_VEC, /* for i128, by vector register */ -} TCGCallReturnKind; - -typedef enum { - TCG_CALL_ARG_NORMAL, /* by registers (continuing onto stack) */ - TCG_CALL_ARG_EVEN, /* like normal, but skipping odd slots */ - TCG_CALL_ARG_EXTEND, /* for i32, as a sign/zero-extended i64 */ - TCG_CALL_ARG_EXTEND_U, /* ... as a zero-extended i64 */ - TCG_CALL_ARG_EXTEND_S, /* ... as a sign-extended i64 */ - TCG_CALL_ARG_BY_REF, /* for i128, by reference, first */ - TCG_CALL_ARG_BY_REF_N, /* ... by reference, subsequent */ -} TCGCallArgumentKind; - -typedef struct TCGCallArgumentLoc { - TCGCallArgumentKind kind : 8; - unsigned arg_slot : 8; - unsigned ref_slot : 8; - unsigned arg_idx : 4; - unsigned tmp_subindex : 2; -} TCGCallArgumentLoc; - -typedef struct TCGHelperInfo { - void *func; - const char *name; -#ifdef CONFIG_TCG_INTERPRETER - ffi_cif *cif; -#endif - unsigned typemask : 32; - unsigned flags : 8; - unsigned nr_in : 8; - unsigned nr_out : 8; - TCGCallReturnKind out_kind : 8; - - /* Maximum physical arguments are constrained by TCG_TYPE_I128. */ - TCGCallArgumentLoc in[MAX_CALL_IARGS * (128 / TCG_TARGET_REG_BITS)]; -} TCGHelperInfo; - extern TCGContext tcg_init_ctx; extern TCGContext **tcg_ctxs; extern unsigned int tcg_cur_ctxs; --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684852683; cv=none; d=zohomail.com; s=zohoarc; b=PDYPeOWHfp3tnId5oBbjAll7dFgAXrahRVpJF1RUQO9QhRWvnPdPqvrAyk+ihe8cpxGrD9a1SoFPbY8CU3J1S4XuZj3BIR97Ai++oAJqUgyVL6fb7/cMIIFmYv9l+HjLUPzuwrOPc9xTxLul4I2eJ3te3e/AdW0Wo6FmOg9F7po= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684852683; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/zm/YdToozeI5DJd2JyJsPEf5LKODH81SXk0JPd/7sU=; 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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850022; x=1687442022; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=/zm/YdToozeI5DJd2JyJsPEf5LKODH81SXk0JPd/7sU=; b=ohKKxcSMhLa1pMv6YnugEC1A+OZPqdkA2Uq4mWnRvQKYt86lPVueblNGkpUbf2pe9r mMXtWSEGc4VwV5Rm4hrdFytqs184aq+1mJq9cUJu0X8YwFHAThBY87Zx3C1G5nk5pC1q pEGJRhjj2MwUnKHO6ZZA2YphamjIb5F4sLWGlYTxgapGQWwaUqDNuhgGVSC1Uf3ILgNL zRs9468PTQiEijpf4+z4uQSWQi0NfMZPdmYepLN39KD56uW4+5z7J5SAOQSHWHOV4C8b Nvb0r2DLTFJ3cUasGnrCArFOdkulqnupyuIw4KDpIi9b6ohwH0vliMutf1Xq5eskfCvJ +Drg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850022; x=1687442022; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/zm/YdToozeI5DJd2JyJsPEf5LKODH81SXk0JPd/7sU=; b=cDmibTLYd8Kf0ZG1fknW5U1Qq0CFuzXMchpk2zN05fiYI3bW+u8T5a7F5Untif5cMw laMpGbVLvvJy8mhRiBxcE74Mx9ukN/P0mBT+ZRWHApU5bQmrgMbnRtDUcBFA6yVwf6fd eFuhtpcWUR2no5hmdig33wtmC8g8s2kK2n8VvmMzigQF5HTxiC2mffSo7IOezt8I+1Ks G5mzwPBAH35nQby+3k2M9sGNHCfrPNaaQFqMX6Y9Z8UWq9AVCXUl4XeLUX+dDu7k4/2X jzgqRlE4Q37JrQb95JnMNo2SlA9wP/UdwdFB4f0RoD25yfxLlvZPMYD5a1m68zVI18kb xOew== X-Gm-Message-State: AC+VfDycTQwktUCiykKwGryQdAA0M0PUqtrx3qjh3e9K6lP7y+/RN5Ca dtuya8AKMLuMreW8PGOGJcs1r9vd0vIpfHnJpK0= X-Google-Smtp-Source: ACHHUZ70MHgtqrEOgIXRLYgvCaO0ifUNJnV0bCQ342e7Dg+oLC0t0FVx00L8/FDDzWCleM/OihlsqQ== X-Received: by 2002:a05:6a00:1896:b0:643:d40c:7db1 with SMTP id x22-20020a056a00189600b00643d40c7db1mr20922213pfh.3.1684850021492; Tue, 23 May 2023 06:53:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 21/52] tcg: Pass TCGHelperInfo to tcg_gen_callN Date: Tue, 23 May 2023 06:52:51 -0700 Message-Id: <20230523135322.678948-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684852683787100010 Content-Type: text/plain; charset="utf-8" In preparation for compiling tcg/ only once, eliminate the all_helpers array. Instantiate the info structs for the generic helpers in accel/tcg/, and the structs for the target-specific helpers in each translate.c. Since we don't see all of the info structs at startup, initialize at first use, using g_once_init_* to make sure we don't race while doing so. Signed-off-by: Richard Henderson --- include/exec/helper-gen.h | 65 ++++++++++++-------- include/exec/helper-tcg.h | 75 ----------------------- include/qemu/typedefs.h | 1 + include/tcg/helper-info.h | 9 ++- include/tcg/tcg.h | 2 +- accel/tcg/plugin-gen.c | 5 ++ accel/tcg/tcg-runtime.c | 4 ++ target/alpha/translate.c | 3 + target/arm/tcg/translate.c | 3 + target/avr/translate.c | 5 ++ target/cris/translate.c | 6 +- target/hexagon/translate.c | 4 ++ target/hppa/translate.c | 5 ++ target/i386/tcg/translate.c | 5 ++ target/loongarch/translate.c | 4 ++ target/m68k/translate.c | 3 + target/microblaze/translate.c | 4 ++ target/mips/tcg/translate.c | 5 ++ target/nios2/translate.c | 5 ++ target/openrisc/translate.c | 5 ++ target/ppc/translate.c | 4 ++ target/riscv/translate.c | 4 ++ target/rx/translate.c | 5 ++ target/s390x/tcg/translate.c | 4 ++ target/sh4/translate.c | 4 ++ target/sparc/translate.c | 3 + target/tricore/translate.c | 5 ++ target/xtensa/translate.c | 4 ++ tcg/tcg.c | 108 ++++++++++++--------------------- include/exec/helper-info.c.inc | 95 +++++++++++++++++++++++++++++ 30 files changed, 279 insertions(+), 175 deletions(-) delete mode 100644 include/exec/helper-tcg.h create mode 100644 include/exec/helper-info.c.inc diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h index 7b6ca975ef..5a7cdd2ee3 100644 --- a/include/exec/helper-gen.h +++ b/include/exec/helper-gen.h @@ -1,81 +1,95 @@ -/* Helper file for declaring TCG helper functions. - This one expands generation functions for tcg opcodes. */ +/* + * Helper file for declaring TCG helper functions. + * This one expands generation functions for tcg opcodes. + * Define HELPER_H for the header file to be expanded, + * and static inline to change from global file scope. + */ =20 #ifndef HELPER_GEN_H #define HELPER_GEN_H =20 +#include "tcg/tcg.h" +#include "tcg/helper-info.h" #include "exec/helper-head.h" =20 #define DEF_HELPER_FLAGS_0(name, flags, ret) \ +extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret)) \ { \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 0, NULL); \ + tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 0, NULL); \ } =20 #define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ +extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ dh_arg_decl(t1, 1)) \ { \ - TCGTemp *args[1] =3D { dh_arg(t1, 1) }; \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 1, args); \ + TCGTemp *args[1] =3D { dh_arg(t1, 1) }; \ + tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 1, args); \ } =20 #define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ +extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) \ { \ - TCGTemp *args[2] =3D { dh_arg(t1, 1), dh_arg(t2, 2) }; \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 2, args); \ + TCGTemp *args[2] =3D { dh_arg(t1, 1), dh_arg(t2, 2) }; \ + tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 2, args); \ } =20 #define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ +extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \ { \ - TCGTemp *args[3] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3) }; \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 3, args); \ + TCGTemp *args[3] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3) }; \ + tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 3, args); \ } =20 #define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ +extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), \ dh_arg_decl(t3, 3), dh_arg_decl(t4, 4)) \ { \ - TCGTemp *args[4] =3D { dh_arg(t1, 1), dh_arg(t2, 2), \ - dh_arg(t3, 3), dh_arg(t4, 4) }; \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 4, args); \ + TCGTemp *args[4] =3D { dh_arg(t1, 1), dh_arg(t2, 2), \ + dh_arg(t3, 3), dh_arg(t4, 4) }; \ + tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 4, args); \ } =20 #define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ +extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ dh_arg_decl(t4, 4), dh_arg_decl(t5, 5)) \ { \ - TCGTemp *args[5] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ - dh_arg(t4, 4), dh_arg(t5, 5) }; \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 5, args); \ + TCGTemp *args[5] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ + dh_arg(t4, 4), dh_arg(t5, 5) }; \ + tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 5, args); \ } =20 #define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ +extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6)) \ { \ - TCGTemp *args[6] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ - dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6) }; \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 6, args); \ + TCGTemp *args[6] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ + dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6) }; \ + tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 6, args); \ } =20 #define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7)\ +extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6), \ dh_arg_decl(t7, 7)) \ { \ - TCGTemp *args[7] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ - dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \ - dh_arg(t7, 7) }; \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 7, args); \ + TCGTemp *args[7] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ + dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \ + dh_arg(t7, 7) }; \ + tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 7, args); \ } =20 #include "helper.h" @@ -90,6 +104,5 @@ static inline void glue(gen_helper_, name)(dh_retvar_dec= l(ret) \ #undef DEF_HELPER_FLAGS_5 #undef DEF_HELPER_FLAGS_6 #undef DEF_HELPER_FLAGS_7 -#undef GEN_HELPER =20 #endif /* HELPER_GEN_H */ diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h deleted file mode 100644 index 3933258f1a..0000000000 --- a/include/exec/helper-tcg.h +++ /dev/null @@ -1,75 +0,0 @@ -/* Helper file for declaring TCG helper functions. - This one defines data structures private to tcg.c. */ - -#ifndef HELPER_TCG_H -#define HELPER_TCG_H - -#include "exec/helper-head.h" - -/* Need one more level of indirection before stringification - to get all the macros expanded first. */ -#define str(s) #s - -#define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ - .flags =3D FLAGS | dh_callflag(ret), \ - .typemask =3D dh_typemask(ret, 0) }, - -#define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ - .flags =3D FLAGS | dh_callflag(ret), \ - .typemask =3D dh_typemask(ret, 0) | dh_typemask(t1, 1) }, - -#define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ - .flags =3D FLAGS | dh_callflag(ret), \ - .typemask =3D dh_typemask(ret, 0) | dh_typemask(t1, 1) \ - | dh_typemask(t2, 2) }, - -#define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ - .flags =3D FLAGS | dh_callflag(ret), \ - .typemask =3D dh_typemask(ret, 0) | dh_typemask(t1, 1) \ - | dh_typemask(t2, 2) | dh_typemask(t3, 3) }, - -#define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ - .flags =3D FLAGS | dh_callflag(ret), \ - .typemask =3D dh_typemask(ret, 0) | dh_typemask(t1, 1) \ - | dh_typemask(t2, 2) | dh_typemask(t3, 3) | dh_typemask(t4, 4) }, - -#define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ - .flags =3D FLAGS | dh_callflag(ret), \ - .typemask =3D dh_typemask(ret, 0) | dh_typemask(t1, 1) \ - | dh_typemask(t2, 2) | dh_typemask(t3, 3) | dh_typemask(t4, 4) \ - | dh_typemask(t5, 5) }, - -#define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), \ - .flags =3D FLAGS | dh_callflag(ret), \ - .typemask =3D dh_typemask(ret, 0) | dh_typemask(t1, 1) \ - | dh_typemask(t2, 2) | dh_typemask(t3, 3) | dh_typemask(t4, 4) \ - | dh_typemask(t5, 5) | dh_typemask(t6, 6) }, - -#define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \ - { .func =3D HELPER(NAME), .name =3D str(NAME), .flags =3D FLAGS, \ - .typemask =3D dh_typemask(ret, 0) | dh_typemask(t1, 1) \ - | dh_typemask(t2, 2) | dh_typemask(t3, 3) | dh_typemask(t4, 4) \ - | dh_typemask(t5, 5) | dh_typemask(t6, 6) | dh_typemask(t7, 7) }, - -#include "helper.h" -#include "accel/tcg/tcg-runtime.h" -#include "accel/tcg/plugin-helpers.h" - -#undef str -#undef DEF_HELPER_FLAGS_0 -#undef DEF_HELPER_FLAGS_1 -#undef DEF_HELPER_FLAGS_2 -#undef DEF_HELPER_FLAGS_3 -#undef DEF_HELPER_FLAGS_4 -#undef DEF_HELPER_FLAGS_5 -#undef DEF_HELPER_FLAGS_6 -#undef DEF_HELPER_FLAGS_7 - -#endif /* HELPER_TCG_H */ diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 8e9ef252f5..8c1840bfc1 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -131,6 +131,7 @@ typedef struct ReservedRegion ReservedRegion; typedef struct SavedIOTLB SavedIOTLB; typedef struct SHPCDevice SHPCDevice; typedef struct SSIBus SSIBus; +typedef struct TCGHelperInfo TCGHelperInfo; typedef struct TranslationBlock TranslationBlock; typedef struct VirtIODevice VirtIODevice; typedef struct Visitor Visitor; diff --git a/include/tcg/helper-info.h b/include/tcg/helper-info.h index f65f81c2e7..4b6c9b43e8 100644 --- a/include/tcg/helper-info.h +++ b/include/tcg/helper-info.h @@ -40,12 +40,17 @@ typedef struct TCGCallArgumentLoc { unsigned tmp_subindex : 2; } TCGCallArgumentLoc; =20 -typedef struct TCGHelperInfo { +struct TCGHelperInfo { void *func; const char *name; + + /* Used with g_once_init_enter. */ #ifdef CONFIG_TCG_INTERPRETER ffi_cif *cif; +#else + uintptr_t init; #endif + unsigned typemask : 32; unsigned flags : 8; unsigned nr_in : 8; @@ -54,6 +59,6 @@ typedef struct TCGHelperInfo { =20 /* Maximum physical arguments are constrained by TCG_TYPE_I128. */ TCGCallArgumentLoc in[MAX_CALL_IARGS * (128 / TCG_TARGET_REG_BITS)]; -} TCGHelperInfo; +}; =20 #endif /* TCG_HELPER_INFO_H */ diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 9b2833b31d..34035dab81 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -937,7 +937,7 @@ typedef struct TCGTargetOpDef { =20 bool tcg_op_supported(TCGOpcode op); =20 -void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args); +void tcg_gen_callN(TCGHelperInfo *, TCGTemp *ret, int nargs, TCGTemp **arg= s); =20 TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs); void tcg_op_remove(TCGContext *s, TCGOp *op); diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 5b73a39ce5..40b34a0403 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -49,6 +49,11 @@ #include "exec/exec-all.h" #include "exec/plugin-gen.h" #include "exec/translator.h" +#include "exec/helper-proto.h" + +#define HELPER_H "accel/tcg/plugin-helpers.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H =20 #ifdef CONFIG_SOFTMMU # define CONFIG_SOFTMMU_GATE 1 diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index e4e030043f..14b59a36e5 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -31,6 +31,10 @@ #include "exec/log.h" #include "tcg/tcg.h" =20 +#define HELPER_H "accel/tcg/tcg-runtime.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + /* 32-bit helpers */ =20 int32_t HELPER(div_i32)(int32_t arg1, int32_t arg2) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index be8adb2526..545e5743c3 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -30,6 +30,9 @@ #include "exec/translator.h" #include "exec/log.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H =20 #undef ALPHA_DEBUG_DISAS #define CONFIG_SOFTFLOAT_INLINE diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index c89825ad6a..4d84850d74 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -33,6 +33,9 @@ #include "exec/log.h" #include "cpregs.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H =20 #define ENABLE_ARCH_4T arm_dc_feature(s, ARM_FEATURE_V4T) #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) diff --git a/target/avr/translate.c b/target/avr/translate.c index cd82f5d591..4fa40b568a 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -31,6 +31,11 @@ #include "exec/translator.h" #include "exec/gen-icount.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + + /* * Define if you want a BREAK instruction translated to a breakpoint * Active debugging connection is assumed diff --git a/target/cris/translate.c b/target/cris/translate.c index b2beb9964d..3c21826cc2 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -34,11 +34,13 @@ #include "exec/translator.h" #include "crisv32-decode.h" #include "qemu/qemu-print.h" - #include "exec/helper-gen.h" - #include "exec/log.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + =20 #define DISAS_CRIS 0 #if DISAS_CRIS diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index f36442c6d5..370dbbaa77 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -31,6 +31,10 @@ #include "genptr.h" #include "printinsn.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + #include "analyze_funcs_generated.c.inc" =20 typedef void (*AnalyzeInsn)(DisasContext *ctx); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 59e4688bfa..2c50fa72c3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -29,6 +29,11 @@ #include "exec/translator.h" #include "exec/log.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + + /* Since we have a distinction between register size and address size, we need to redefine all of these. */ =20 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 91c9c0c478..d509105505 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -34,6 +34,11 @@ =20 #include "exec/log.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + + #define PREFIX_REPZ 0x01 #define PREFIX_REPNZ 0x02 #define PREFIX_LOCK 0x04 diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index ae53f5ee9d..67140ada56 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -26,6 +26,10 @@ static TCGv cpu_lladdr, cpu_llval; =20 #include "exec/gen-icount.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + #define DISAS_STOP DISAS_TARGET_0 #define DISAS_EXIT DISAS_TARGET_1 #define DISAS_EXIT_UPDATE DISAS_TARGET_2 diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 44d852b106..90ca51fb9e 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -34,6 +34,9 @@ #include "exec/log.h" #include "fpu/softfloat.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H =20 //#define DEBUG_DISPATCH 1 =20 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index ee0d7b81ad..7a5d1066da 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -31,6 +31,10 @@ =20 #include "exec/log.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + #define EXTRACT_FIELD(src, start, end) \ (((src) >> start) & ((1 << (end - start + 1)) - 1)) =20 diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index a6ca2e5a3b..bff1859b86 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -37,6 +37,11 @@ #include "fpu_helper.h" #include "translate.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + + /* * Many sysemu-only helpers are not reachable for user-only. * Define stub generators here, so that we need not either sprinkle diff --git a/target/nios2/translate.c b/target/nios2/translate.c index a548e16ed5..28c1d700e1 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -35,6 +35,11 @@ #include "exec/gen-icount.h" #include "semihosting/semihost.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + + /* is_jmp field values */ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ =20 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 43ba0cc1ad..06e6eae952 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -35,6 +35,11 @@ =20 #include "exec/log.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + + /* is_jmp field values */ #define DISAS_EXIT DISAS_TARGET_0 /* force exit to main loop */ #define DISAS_JUMP DISAS_TARGET_1 /* exit via jmp_pc/jmp_pc_imm */ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 1720570b9b..3df42dba4e 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -41,6 +41,10 @@ #include "qemu/qemu-print.h" #include "qapi/error.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + #define CPU_SINGLE_STEP 0x1 #define CPU_BRANCH_STEP 0x2 =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 928da0d3f0..ed968162da 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -33,6 +33,10 @@ #include "instmap.h" #include "internals.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + /* global register indices */ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ diff --git a/target/rx/translate.c b/target/rx/translate.c index 70fad98e93..89dbec26f9 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -28,6 +28,11 @@ #include "exec/translator.h" #include "exec/log.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + + typedef struct DisasContext { DisasContextBase base; CPURXState *env; diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 3eb3708d55..60b17585a7 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -46,6 +46,10 @@ #include "exec/log.h" #include "qemu/atomic128.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + =20 /* Information that (most) every instruction needs to manipulate. */ typedef struct DisasContext DisasContext; diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 0dedbb8210..350f88a99f 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -31,6 +31,10 @@ #include "exec/log.h" #include "qemu/qemu-print.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + =20 typedef struct DisasContext { DisasContextBase base; diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 414e014b11..a3fed5e01b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -33,6 +33,9 @@ #include "exec/log.h" #include "asi.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H =20 #define DEBUG_DISAS =20 diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 2646cb3eb5..eee935bbaf 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -33,6 +33,11 @@ #include "exec/translator.h" #include "exec/log.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + + /* * TCG registers */ diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 728aeebebf..11bb8c079b 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -45,6 +45,10 @@ =20 #include "exec/log.h" =20 +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + =20 struct DisasContext { DisasContextBase base; diff --git a/tcg/tcg.c b/tcg/tcg.c index 32cd0e338d..7c5cc6c800 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -851,13 +851,6 @@ void tcg_pool_reset(TCGContext *s) s->pool_current =3D NULL; } =20 -#include "exec/helper-proto.h" - -static TCGHelperInfo all_helpers[] =3D { -#include "exec/helper-tcg.h" -}; -static GHashTable *helper_table; - /* * Create TCGHelperInfo structures for "tcg/tcg-ldst.h" functions, * akin to what "exec/helper-tcg.h" does with DEF_HELPER_FLAGS_N. @@ -967,57 +960,45 @@ static ffi_type *typecode_to_ffi(int argmask) g_assert_not_reached(); } =20 -static void init_ffi_layouts(void) +static ffi_cif *init_ffi_layout(TCGHelperInfo *info) { - /* g_direct_hash/equal for direct comparisons on uint32_t. */ - GHashTable *ffi_table =3D g_hash_table_new(NULL, NULL); + unsigned typemask =3D info->typemask; + struct { + ffi_cif cif; + ffi_type *args[]; + } *ca; + ffi_status status; + int nargs; =20 - for (int i =3D 0; i < ARRAY_SIZE(all_helpers); ++i) { - TCGHelperInfo *info =3D &all_helpers[i]; - unsigned typemask =3D info->typemask; - gpointer hash =3D (gpointer)(uintptr_t)typemask; - struct { - ffi_cif cif; - ffi_type *args[]; - } *ca; - ffi_status status; - int nargs; - ffi_cif *cif; + /* Ignoring the return type, find the last non-zero field. */ + nargs =3D 32 - clz32(typemask >> 3); + nargs =3D DIV_ROUND_UP(nargs, 3); + assert(nargs <=3D MAX_CALL_IARGS); =20 - cif =3D g_hash_table_lookup(ffi_table, hash); - if (cif) { - info->cif =3D cif; - continue; + ca =3D g_malloc0(sizeof(*ca) + nargs * sizeof(ffi_type *)); + ca->cif.rtype =3D typecode_to_ffi(typemask & 7); + ca->cif.nargs =3D nargs; + + if (nargs !=3D 0) { + ca->cif.arg_types =3D ca->args; + for (int j =3D 0; j < nargs; ++j) { + int typecode =3D extract32(typemask, (j + 1) * 3, 3); + ca->args[j] =3D typecode_to_ffi(typecode); } - - /* Ignoring the return type, find the last non-zero field. */ - nargs =3D 32 - clz32(typemask >> 3); - nargs =3D DIV_ROUND_UP(nargs, 3); - assert(nargs <=3D MAX_CALL_IARGS); - - ca =3D g_malloc0(sizeof(*ca) + nargs * sizeof(ffi_type *)); - ca->cif.rtype =3D typecode_to_ffi(typemask & 7); - ca->cif.nargs =3D nargs; - - if (nargs !=3D 0) { - ca->cif.arg_types =3D ca->args; - for (int j =3D 0; j < nargs; ++j) { - int typecode =3D extract32(typemask, (j + 1) * 3, 3); - ca->args[j] =3D typecode_to_ffi(typecode); - } - } - - status =3D ffi_prep_cif(&ca->cif, FFI_DEFAULT_ABI, nargs, - ca->cif.rtype, ca->cif.arg_types); - assert(status =3D=3D FFI_OK); - - cif =3D &ca->cif; - info->cif =3D cif; - g_hash_table_insert(ffi_table, hash, (gpointer)cif); } =20 - g_hash_table_destroy(ffi_table); + status =3D ffi_prep_cif(&ca->cif, FFI_DEFAULT_ABI, nargs, + ca->cif.rtype, ca->cif.arg_types); + assert(status =3D=3D FFI_OK); + + return &ca->cif; } + +#define HELPER_INFO_INIT(I) (&(I)->cif) +#define HELPER_INFO_INIT_VAL(I) init_ffi_layout(I) +#else +#define HELPER_INFO_INIT(I) (&(I)->init) +#define HELPER_INFO_INIT_VAL(I) 1 #endif /* CONFIG_TCG_INTERPRETER */ =20 static inline bool arg_slot_reg_p(unsigned arg_slot) @@ -1330,16 +1311,6 @@ static void tcg_context_init(unsigned max_cpus) args_ct +=3D n; } =20 - /* Register helpers. */ - /* Use g_direct_hash/equal for direct pointer comparisons on func. */ - helper_table =3D g_hash_table_new(NULL, NULL); - - for (i =3D 0; i < ARRAY_SIZE(all_helpers); ++i) { - init_call_layout(&all_helpers[i]); - g_hash_table_insert(helper_table, (gpointer)all_helpers[i].func, - (gpointer)&all_helpers[i]); - } - init_call_layout(&info_helper_ld32_mmu); init_call_layout(&info_helper_ld64_mmu); init_call_layout(&info_helper_ld128_mmu); @@ -1347,10 +1318,6 @@ static void tcg_context_init(unsigned max_cpus) init_call_layout(&info_helper_st64_mmu); init_call_layout(&info_helper_st128_mmu); =20 -#ifdef CONFIG_TCG_INTERPRETER - init_ffi_layouts(); -#endif - tcg_target_init(s); process_op_defs(s); =20 @@ -2146,15 +2113,18 @@ bool tcg_op_supported(TCGOpcode op) =20 static TCGOp *tcg_op_alloc(TCGOpcode opc, unsigned nargs); =20 -void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) +void tcg_gen_callN(TCGHelperInfo *info, TCGTemp *ret, int nargs, TCGTemp *= *args) { - const TCGHelperInfo *info; TCGv_i64 extend_free[MAX_CALL_IARGS]; int n_extend =3D 0; TCGOp *op; int i, n, pi =3D 0, total_args; =20 - info =3D g_hash_table_lookup(helper_table, (gpointer)func); + if (unlikely(g_once_init_enter(HELPER_INFO_INIT(info)))) { + init_call_layout(info); + g_once_init_leave(HELPER_INFO_INIT(info), HELPER_INFO_INIT_VAL(inf= o)); + } + total_args =3D info->nr_out + info->nr_in + 2; op =3D tcg_op_alloc(INDEX_op_call, total_args); =20 @@ -2221,7 +2191,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int narg= s, TCGTemp **args) g_assert_not_reached(); } } - op->args[pi++] =3D (uintptr_t)func; + op->args[pi++] =3D (uintptr_t)info->func; op->args[pi++] =3D (uintptr_t)info; tcg_debug_assert(pi =3D=3D total_args); =20 diff --git a/include/exec/helper-info.c.inc b/include/exec/helper-info.c.inc new file mode 100644 index 0000000000..5395e73c75 --- /dev/null +++ b/include/exec/helper-info.c.inc @@ -0,0 +1,95 @@ +/* + * Helper file for declaring TCG helper functions. + * This one expands info structures for tcg helpers. + * Define HELPER_H for the header file to be expanded. + */ + +#include "tcg/tcg.h" +#include "tcg/helper-info.h" +#include "exec/helper-head.h" + +/* + * Need one more level of indirection before stringification + * to get all the macros expanded first. + */ +#define str(s) #s + +#define DEF_HELPER_FLAGS_0(NAME, FLAGS, RET) \ + TCGHelperInfo glue(helper_info_, NAME) =3D { \ + .func =3D HELPER(NAME), .name =3D str(NAME), = \ + .flags =3D FLAGS | dh_callflag(RET), \ + .typemask =3D dh_typemask(RET, 0) \ + }; + +#define DEF_HELPER_FLAGS_1(NAME, FLAGS, RET, T1) \ + TCGHelperInfo glue(helper_info_, NAME) =3D { \ + .func =3D HELPER(NAME), .name =3D str(NAME), = \ + .flags =3D FLAGS | dh_callflag(RET), \ + .typemask =3D dh_typemask(RET, 0) | dh_typemask(T1, 1) \ + }; + +#define DEF_HELPER_FLAGS_2(NAME, FLAGS, RET, T1, T2) \ + TCGHelperInfo glue(helper_info_, NAME) =3D { \ + .func =3D HELPER(NAME), .name =3D str(NAME), = \ + .flags =3D FLAGS | dh_callflag(RET), \ + .typemask =3D dh_typemask(RET, 0) | dh_typemask(T1, 1) \ + | dh_typemask(T2, 2) \ + }; + +#define DEF_HELPER_FLAGS_3(NAME, FLAGS, RET, T1, T2, T3) \ + TCGHelperInfo glue(helper_info_, NAME) =3D { \ + .func =3D HELPER(NAME), .name =3D str(NAME), = \ + .flags =3D FLAGS | dh_callflag(RET), \ + .typemask =3D dh_typemask(RET, 0) | dh_typemask(T1, 1) \ + | dh_typemask(T2, 2) | dh_typemask(T3, 3) \ + }; + +#define DEF_HELPER_FLAGS_4(NAME, FLAGS, RET, T1, T2, T3, T4) \ + TCGHelperInfo glue(helper_info_, NAME) =3D { \ + .func =3D HELPER(NAME), .name =3D str(NAME), = \ + .flags =3D FLAGS | dh_callflag(RET), \ + .typemask =3D dh_typemask(RET, 0) | dh_typemask(T1, 1) \ + | dh_typemask(T2, 2) | dh_typemask(T3, 3) \ + | dh_typemask(T4, 4) \ + }; + +#define DEF_HELPER_FLAGS_5(NAME, FLAGS, RET, T1, T2, T3, T4, T5) \ + TCGHelperInfo glue(helper_info_, NAME) =3D { \ + .func =3D HELPER(NAME), .name =3D str(NAME), = \ + .flags =3D FLAGS | dh_callflag(RET), \ + .typemask =3D dh_typemask(RET, 0) | dh_typemask(T1, 1) \ + | dh_typemask(T2, 2) | dh_typemask(T3, 3) \ + | dh_typemask(T4, 4) | dh_typemask(T5, 5) \ + }; + +#define DEF_HELPER_FLAGS_6(NAME, FLAGS, RET, T1, T2, T3, T4, T5, T6) \ + TCGHelperInfo glue(helper_info_, NAME) =3D { \ + .func =3D HELPER(NAME), .name =3D str(NAME), = \ + .flags =3D FLAGS | dh_callflag(RET), \ + .typemask =3D dh_typemask(RET, 0) | dh_typemask(T1, 1) \ + | dh_typemask(T2, 2) | dh_typemask(T3, 3) \ + | dh_typemask(T4, 4) | dh_typemask(T5, 5) \ + | dh_typemask(T6, 6) \ + }; + +#define DEF_HELPER_FLAGS_7(NAME, FLAGS, RET, T1, T2, T3, T4, T5, T6, T7) \ + TCGHelperInfo glue(helper_info_, NAME) =3D { \ + .func =3D HELPER(NAME), .name =3D str(NAME), = \ + .flags =3D FLAGS | dh_callflag(RET), \ + .typemask =3D dh_typemask(RET, 0) | dh_typemask(T1, 1) \ + | dh_typemask(T2, 2) | dh_typemask(T3, 3) \ + | dh_typemask(T4, 4) | dh_typemask(T5, 5) \ + | dh_typemask(T6, 6) | dh_typemask(T7, 7) \ + }; + +#include HELPER_H + +#undef str +#undef DEF_HELPER_FLAGS_0 +#undef DEF_HELPER_FLAGS_1 +#undef DEF_HELPER_FLAGS_2 +#undef DEF_HELPER_FLAGS_3 +#undef DEF_HELPER_FLAGS_4 +#undef DEF_HELPER_FLAGS_5 +#undef DEF_HELPER_FLAGS_6 +#undef DEF_HELPER_FLAGS_7 --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684852816; cv=none; d=zohomail.com; s=zohoarc; b=Kvn94ZWB+7hsdcrPrnrTp8xChibpKPWZ17rxW6vDF09nF+osD2FyV4E28SMS3XFV8l3dAS8PHr2+HSerUQ81Z4r/6s+rSXUBNf27wCD64oqGMk4DELlpzdRunMGVNrtaXqg78oAVfHatDcBsjPe1smPl53229fvzYd9d40Be3sA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684852815; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850022; x=1687442022; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=f6ed1FqxBisHvzO2Ats72ofMAbjCaP6iPUvqaHHft5E=; b=oruelD3sU3wSANPCy3BUHVkx8CSpEfNcG2MAWyYYJt06dvNqLSv9sFO5rdN6wPgIgK txqQVv+m9Npnhq65XnQFwhONo3mnrIFJ4IqNdniKYdYVmjpJcMo3ALvNPZP3BQUY+JxC VjPcV3e3p97HIqRfOF6MQbIRyDZZQGDPsvxURnLJNw56aNe57ucxS89K1qKC8XqwqgJC YtlKzwu6/pkSNnYfS3Q2AQ7JQD4u2YpTknoJxXdWt+IJoDl8fksrn0ufNEkW1CBAeHCs yL3n3+dRL7z4J6Vmk5mbabES6IfX2R2uCv2mPPyvaAHSk1EVp4EyMtFhjyiOBeONaGEa b0Fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850022; x=1687442022; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f6ed1FqxBisHvzO2Ats72ofMAbjCaP6iPUvqaHHft5E=; b=htx4oaqtfAvgWVoTH2kUX6nBYCM/fExhT7frxoz9U0LY5yOe5lSMCNj8scnUn3jJYw jroesa11aJp3IoYUPmvzDCJ9Imiq7SL202pw6aQPoHbUJzxVm1gm5Je+f9RpGxYsS7FD YMiMJpefTp5Ewlrm+eldaR4YFTqF4Yf2E4372a8PUIfah+dtr0F28UowoeHhg9zpv9KI DdHNEsP0dpiLZVJrfpKG6i/hGJQd2GxjgZ9pWJtVYD5q3yFhnT/O6HROvIBzqOrSi7n0 zoJ6z7rl+g1gm+Qcr9ieGX29ZJ96+kl6KmaugnJCc2WV/bWaotdZXGa2UfvmCGJiYM9Z XsdQ== X-Gm-Message-State: AC+VfDwvmuJQCSllCJ2t0xHweRu0sODumT8i1KYd4TeRmwomkkHDRbki roIGwbcgO0RhmFmsuCbBN3IsPX3uW2d00GwkPhc= X-Google-Smtp-Source: ACHHUZ5snvS5JfNINxtUBvL+CTTq0nZpNnyP2wv437+SxtlLmPeqvF14BBdFulzIlCrAMPf4A8Ua4A== X-Received: by 2002:a05:6a20:3947:b0:10c:7916:f9f6 with SMTP id r7-20020a056a20394700b0010c7916f9f6mr2687163pzg.52.1684850022193; Tue, 23 May 2023 06:53:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 22/52] tcg: Move temp_idx and tcgv_i32_temp debug out of line Date: Tue, 23 May 2023 06:52:52 -0700 Message-Id: <20230523135322.678948-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684852818017100001 Content-Type: text/plain; charset="utf-8" Removes a multiplicty of calls to __assert_fail, saving up to 360kiB of .text space as measured on an x86_64 host. Old New Less %Change 9257272 8888680 368592 3.98% qemu-system-aarch64 6100968 5911832 189136 3.10% qemu-system-riscv64 5839112 5707032 132080 2.26% qemu-system-mips 4447608 4341752 105856 2.38% qemu-system-s390x Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 30 ++++++++++++++++-------------- tcg/tcg.c | 19 +++++++++++++++++++ 2 files changed, 35 insertions(+), 14 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 34035dab81..64c10a63f3 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -630,13 +630,6 @@ static inline void *tcg_splitwx_to_rw(const void *rx) } #endif =20 -static inline size_t temp_idx(TCGTemp *ts) -{ - ptrdiff_t n =3D ts - tcg_ctx->temps; - tcg_debug_assert(n >=3D 0 && n < tcg_ctx->nb_temps); - return n; -} - static inline TCGArg temp_arg(TCGTemp *ts) { return (uintptr_t)ts; @@ -647,16 +640,25 @@ static inline TCGTemp *arg_temp(TCGArg a) return (TCGTemp *)(uintptr_t)a; } =20 -/* Using the offset of a temporary, relative to TCGContext, rather than - its index means that we don't use 0. That leaves offset 0 free for - a NULL representation without having to leave index 0 unused. */ +#ifdef CONFIG_DEBUG_TCG +size_t temp_idx(TCGTemp *ts); +TCGTemp *tcgv_i32_temp(TCGv_i32 v); +#else +static inline size_t temp_idx(TCGTemp *ts) +{ + return ts - tcg_ctx->temps; +} + +/* + * Using the offset of a temporary, relative to TCGContext, rather than + * its index means that we don't use 0. That leaves offset 0 free for + * a NULL representation without having to leave index 0 unused. + */ static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) { - uintptr_t o =3D (uintptr_t)v; - TCGTemp *t =3D (void *)tcg_ctx + o; - tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) =3D=3D o); - return t; + return (void *)tcg_ctx + (uintptr_t)v; } +#endif =20 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) { diff --git a/tcg/tcg.c b/tcg/tcg.c index 7c5cc6c800..bd276f1d32 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1805,6 +1805,25 @@ TCGv_vec tcg_constant_vec_matching(TCGv_vec match, u= nsigned vece, int64_t val) return tcg_constant_vec(t->base_type, vece, val); } =20 +#ifdef CONFIG_DEBUG_TCG +size_t temp_idx(TCGTemp *ts) +{ + ptrdiff_t n =3D ts - tcg_ctx->temps; + assert(n >=3D 0 && n < tcg_ctx->nb_temps); + return n; +} + +TCGTemp *tcgv_i32_temp(TCGv_i32 v) +{ + uintptr_t o =3D (uintptr_t)v - offsetof(TCGContext, temps); + + assert(o < sizeof(TCGTemp) * tcg_ctx->nb_temps); + assert(o % sizeof(TCGTemp) =3D=3D 0); + + return (void *)tcg_ctx + (uintptr_t)v; +} +#endif /* CONFIG_DEBUG_TCG */ + /* Return true if OP may appear in the opcode stream. Test the runtime variable that controls each opcode. */ bool tcg_op_supported(TCGOpcode op) --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684852691; cv=none; d=zohomail.com; s=zohoarc; b=EBSsc5QIoRAST6iFBwCRSxrSttYgyzcW9c3l3skc8WDY4D7RyymkEcZhhedqvs5ytPQ5t1Hs8M+7WmiW1LbyV95mIK8jQOpD7C51AUg7MgWcmpBDqRZmmhoIDbSBTna4Polhgj3MzHoXbYNmHU8cQP+74DgZy1tluJf2HmAh954= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684852691; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zJjPyjOiX4+v5RoBR2XGJ8xMoz6bAllkVrtNZFBh3eA=; b=SuX2gpPXQeFZgvZIaMmNQ9T869zP+dNlXCSLyfV66VphJUAXvGXopb1YFjgqD2CDh1VDoyHFOwQ8S0YmAvm6NL+AF0r9GfIEk+BGJUYCuMsJK/Fz6KkvpOhx5VnajeeMjQQbCjlvWYQKEMIDaMnio2brI7X7czyPKPYo/fhLxM0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684852691321751.0546840741454; Tue, 23 May 2023 07:38:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1ST7-0006aw-Mp; Tue, 23 May 2023 09:54:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSQ-0004zp-DZ for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:47 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSO-00035U-AZ for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:46 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-64d3fbb8c1cso4743725b3a.3 for ; Tue, 23 May 2023 06:53:43 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850023; x=1687442023; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=zJjPyjOiX4+v5RoBR2XGJ8xMoz6bAllkVrtNZFBh3eA=; b=h0m9pJUROPYZJy5tSL7Je7rOeW+o+c41kRperxQmzPB1z/WbGE8XWv2/sQQje6cMw3 tjD/cnKaFMhIbaCVYZkeJTACp9KuO2DfOMmwoTD9RSswONh9IwOASU5mmjQ4qMCn5U++ RP0c+ECToZI9gVlMXLYVeLuPwRkmQTGbAZcBNl3+ITdiOSyJhb4MSsRfhiZkRKQdbEly A9nywtB37U5b4mB0tdrSgNTpPt02Dhshwp29+WTscu1E3eMtJjNDjvLHDCiCfwY4I4BE ZMFjFBIZCJr6KPERyNr2j7oZu9G18ngtzcrqevVVG7/ihlidhZ6mpyJZ3L+z4zaeGGtJ btLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850023; x=1687442023; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zJjPyjOiX4+v5RoBR2XGJ8xMoz6bAllkVrtNZFBh3eA=; b=G63aXNrMJxw71QOX3neQ1zvi3sn3oD12Zt6QJzBWLkyFrq6UEYWsE0yUl6iapPELft nmap4D/eOg8DzZAMeRsM+3m/oCP6W+vWhsCrj5Cg2iHO28vZ0gux3XeoFqQ2ee4vPLRw aU4aRuzIPMlYr0XZyp36jz1uVd9pD9GdBxWKiHKjyXbiBN9K70H9O0r0YguUXSXPgDrN 8G1ym85qZ+edxmNjf5gZHLSIve3z+44lwRlVDA3P+wSwkVASIybaMFdr41+pKHsJ8bQq Ln11aK93VfwT5BcNkLRZujkbtkO5atT0xuvQ3n//QF2WH6ARrl+o6M/VhiearT+JiX1k 2XoQ== X-Gm-Message-State: AC+VfDwAik2t2eqW305GX/AfhrZ2jSRED0Or/PzhJk1q4ejgPsgtD8Zr UlhN69kR0a63J8EgGf/+Aft99pS/QcbK73bUpT0= X-Google-Smtp-Source: ACHHUZ6p/2Yg6+5YQFLlZnPSf+VLbMUas45hkaoK8lujgfqcs+8tGzEWXLoBgm1NAK+EKxhgcaeMDQ== X-Received: by 2002:a05:6a00:2302:b0:64d:4188:ae86 with SMTP id h2-20020a056a00230200b0064d4188ae86mr16275667pfh.6.1684850022982; Tue, 23 May 2023 06:53:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 23/52] tcg: Split tcg_gen_callN Date: Tue, 23 May 2023 06:52:53 -0700 Message-Id: <20230523135322.678948-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684852691898100001 Content-Type: text/plain; charset="utf-8" Make tcg_gen_callN a static function. Create tcg_gen_call[0-7] functions for use by helper-gen.h.inc. Removes a multiplicty of calls to __stack_chk_fail, saving up to 143kiB of .text space as measured on an x86_64 host. Old New Less %Change 8888680 8741816 146864 1.65% qemu-system-aarch64 5911832 5856152 55680 0.94% qemu-system-riscv64 5816728 5767512 49216 0.85% qemu-system-mips64 6707832 6659144 48688 0.73% qemu-system-ppc64 Signed-off-by: Richard Henderson --- include/exec/helper-gen.h | 40 ++++++++++++++--------------- include/tcg/tcg.h | 14 +++++++++- tcg/tcg.c | 54 ++++++++++++++++++++++++++++++++++++++- 3 files changed, 86 insertions(+), 22 deletions(-) diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h index 5a7cdd2ee3..7c93ef70bc 100644 --- a/include/exec/helper-gen.h +++ b/include/exec/helper-gen.h @@ -16,7 +16,7 @@ extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret)) \ { \ - tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 0, NULL); \ + tcg_gen_call0(&glue(helper_info_, name), dh_retvar(ret)); \ } =20 #define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ @@ -24,8 +24,8 @@ extern TCGHelperInfo glue(helper_info_, name); = \ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ dh_arg_decl(t1, 1)) \ { \ - TCGTemp *args[1] =3D { dh_arg(t1, 1) }; \ - tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 1, args); \ + tcg_gen_call1(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1)); \ } =20 #define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ @@ -33,8 +33,8 @@ extern TCGHelperInfo glue(helper_info_, name); = \ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) \ { \ - TCGTemp *args[2] =3D { dh_arg(t1, 1), dh_arg(t2, 2) }; \ - tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 2, args); \ + tcg_gen_call2(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2)); \ } =20 #define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ @@ -42,8 +42,8 @@ extern TCGHelperInfo glue(helper_info_, name); = \ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \ { \ - TCGTemp *args[3] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3) }; \ - tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 3, args); \ + tcg_gen_call3(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3)); \ } =20 #define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ @@ -52,9 +52,9 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), \ dh_arg_decl(t3, 3), dh_arg_decl(t4, 4)) \ { \ - TCGTemp *args[4] =3D { dh_arg(t1, 1), dh_arg(t2, 2), \ - dh_arg(t3, 3), dh_arg(t4, 4) }; \ - tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 4, args); \ + tcg_gen_call4(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2), \ + dh_arg(t3, 3), dh_arg(t4, 4)); \ } =20 #define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ @@ -63,9 +63,9 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ dh_arg_decl(t4, 4), dh_arg_decl(t5, 5)) \ { \ - TCGTemp *args[5] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ - dh_arg(t4, 4), dh_arg(t5, 5) }; \ - tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 5, args); \ + tcg_gen_call5(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ + dh_arg(t4, 4), dh_arg(t5, 5)); \ } =20 #define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ @@ -74,9 +74,9 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl= (ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6)) \ { \ - TCGTemp *args[6] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ - dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6) }; \ - tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 6, args); \ + tcg_gen_call6(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ + dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6)); \ } =20 #define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7)\ @@ -86,10 +86,10 @@ static inline void glue(gen_helper_, name)(dh_retvar_de= cl(ret) \ dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6), \ dh_arg_decl(t7, 7)) \ { \ - TCGTemp *args[7] =3D { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ - dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \ - dh_arg(t7, 7) }; \ - tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 7, args); \ + tcg_gen_call7(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ + dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \ + dh_arg(t7, 7)); \ } =20 #include "helper.h" diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 64c10a63f3..7c1bbba673 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -939,7 +939,19 @@ typedef struct TCGTargetOpDef { =20 bool tcg_op_supported(TCGOpcode op); =20 -void tcg_gen_callN(TCGHelperInfo *, TCGTemp *ret, int nargs, TCGTemp **arg= s); +void tcg_gen_call0(TCGHelperInfo *, TCGTemp *ret); +void tcg_gen_call1(TCGHelperInfo *, TCGTemp *ret, TCGTemp *); +void tcg_gen_call2(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *); +void tcg_gen_call3(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, + TCGTemp *, TCGTemp *); +void tcg_gen_call4(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *, + TCGTemp *, TCGTemp *); +void tcg_gen_call5(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *, + TCGTemp *, TCGTemp *, TCGTemp *); +void tcg_gen_call6(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *, + TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *); +void tcg_gen_call7(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *, + TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *); =20 TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs); void tcg_op_remove(TCGContext *s, TCGOp *op); diff --git a/tcg/tcg.c b/tcg/tcg.c index bd276f1d32..57600f41ac 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2132,7 +2132,7 @@ bool tcg_op_supported(TCGOpcode op) =20 static TCGOp *tcg_op_alloc(TCGOpcode opc, unsigned nargs); =20 -void tcg_gen_callN(TCGHelperInfo *info, TCGTemp *ret, int nargs, TCGTemp *= *args) +static void tcg_gen_callN(TCGHelperInfo *info, TCGTemp *ret, TCGTemp **arg= s) { TCGv_i64 extend_free[MAX_CALL_IARGS]; int n_extend =3D 0; @@ -2222,6 +2222,58 @@ void tcg_gen_callN(TCGHelperInfo *info, TCGTemp *ret= , int nargs, TCGTemp **args) } } =20 +void tcg_gen_call0(TCGHelperInfo *info, TCGTemp *ret) +{ + tcg_gen_callN(info, ret, NULL); +} + +void tcg_gen_call1(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1) +{ + tcg_gen_callN(info, ret, &t1); +} + +void tcg_gen_call2(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, TCGTemp= *t2) +{ + TCGTemp *args[2] =3D { t1, t2 }; + tcg_gen_callN(info, ret, args); +} + +void tcg_gen_call3(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, + TCGTemp *t2, TCGTemp *t3) +{ + TCGTemp *args[3] =3D { t1, t2, t3 }; + tcg_gen_callN(info, ret, args); +} + +void tcg_gen_call4(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, + TCGTemp *t2, TCGTemp *t3, TCGTemp *t4) +{ + TCGTemp *args[4] =3D { t1, t2, t3, t4 }; + tcg_gen_callN(info, ret, args); +} + +void tcg_gen_call5(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, + TCGTemp *t2, TCGTemp *t3, TCGTemp *t4, TCGTemp *t5) +{ + TCGTemp *args[5] =3D { t1, t2, t3, t4, t5 }; + tcg_gen_callN(info, ret, args); +} + +void tcg_gen_call6(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, TCGTemp= *t2, + TCGTemp *t3, TCGTemp *t4, TCGTemp *t5, TCGTemp *t6) +{ + TCGTemp *args[6] =3D { t1, t2, t3, t4, t5, t6 }; + tcg_gen_callN(info, ret, args); +} + +void tcg_gen_call7(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, + TCGTemp *t2, TCGTemp *t3, TCGTemp *t4, + TCGTemp *t5, TCGTemp *t6, TCGTemp *t7) +{ + TCGTemp *args[7] =3D { t1, t2, t3, t4, t5, t6, t7 }; + tcg_gen_callN(info, ret, args); +} + static void tcg_reg_alloc_start(TCGContext *s) { int i, n; --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851336; cv=none; d=zohomail.com; s=zohoarc; b=cVW3reFSLokL85KOuLk1Nr+fu9d7x7mSEYsKegcJyU++tGzSXSkYiTUiZVA7pqMpnW2D8bJDDWJ6kInC8de4HCnwkIeTefOwoK3wI6lveibxOcsvAaqfVpriDBTC+xmc6YUGvJzhrYRcGiOduMmXHE786UZzAG2IMLfTpghOS0U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Use that in tcg-op-common.h. Reorg headers in target/arm to ensure that helper-gen.h is included before helper-info.c.inc. All other targets are already correct in this regard. Signed-off-by: Richard Henderson --- include/exec/helper-gen-common.h | 17 ++++++ include/exec/helper-gen.h | 101 ++----------------------------- include/tcg/tcg-op-common.h | 2 +- target/arm/tcg/translate.c | 8 +-- include/exec/helper-gen.h.inc | 101 +++++++++++++++++++++++++++++++ 5 files changed, 126 insertions(+), 103 deletions(-) create mode 100644 include/exec/helper-gen-common.h create mode 100644 include/exec/helper-gen.h.inc diff --git a/include/exec/helper-gen-common.h b/include/exec/helper-gen-com= mon.h new file mode 100644 index 0000000000..cb01ed49c5 --- /dev/null +++ b/include/exec/helper-gen-common.h @@ -0,0 +1,17 @@ +/* + * Helper file for declaring TCG helper functions. + * This one expands generation functions for tcg opcodes. + */ + +#ifndef HELPER_GEN_COMMON_H +#define HELPER_GEN_COMMON_H + +#define HELPER_H "accel/tcg/tcg-runtime.h" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +#define HELPER_H "accel/tcg/plugin-helpers.h" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +#endif /* HELPER_GEN_COMMON_H */ diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h index 7c93ef70bc..ca88e07182 100644 --- a/include/exec/helper-gen.h +++ b/include/exec/helper-gen.h @@ -1,108 +1,15 @@ /* * Helper file for declaring TCG helper functions. * This one expands generation functions for tcg opcodes. - * Define HELPER_H for the header file to be expanded, - * and static inline to change from global file scope. */ =20 #ifndef HELPER_GEN_H #define HELPER_GEN_H =20 -#include "tcg/tcg.h" -#include "tcg/helper-info.h" -#include "exec/helper-head.h" +#include "exec/helper-gen-common.h" =20 -#define DEF_HELPER_FLAGS_0(name, flags, ret) \ -extern TCGHelperInfo glue(helper_info_, name); \ -static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret)) \ -{ \ - tcg_gen_call0(&glue(helper_info_, name), dh_retvar(ret)); \ -} - -#define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ -extern TCGHelperInfo glue(helper_info_, name); \ -static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1)) \ -{ \ - tcg_gen_call1(&glue(helper_info_, name), dh_retvar(ret), \ - dh_arg(t1, 1)); \ -} - -#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ -extern TCGHelperInfo glue(helper_info_, name); \ -static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) \ -{ \ - tcg_gen_call2(&glue(helper_info_, name), dh_retvar(ret), \ - dh_arg(t1, 1), dh_arg(t2, 2)); \ -} - -#define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ -extern TCGHelperInfo glue(helper_info_, name); \ -static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \ -{ \ - tcg_gen_call3(&glue(helper_info_, name), dh_retvar(ret), \ - dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3)); \ -} - -#define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ -extern TCGHelperInfo glue(helper_info_, name); \ -static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), \ - dh_arg_decl(t3, 3), dh_arg_decl(t4, 4)) \ -{ \ - tcg_gen_call4(&glue(helper_info_, name), dh_retvar(ret), \ - dh_arg(t1, 1), dh_arg(t2, 2), \ - dh_arg(t3, 3), dh_arg(t4, 4)); \ -} - -#define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ -extern TCGHelperInfo glue(helper_info_, name); \ -static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ - dh_arg_decl(t4, 4), dh_arg_decl(t5, 5)) \ -{ \ - tcg_gen_call5(&glue(helper_info_, name), dh_retvar(ret), \ - dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ - dh_arg(t4, 4), dh_arg(t5, 5)); \ -} - -#define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ -extern TCGHelperInfo glue(helper_info_, name); \ -static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ - dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6)) \ -{ \ - tcg_gen_call6(&glue(helper_info_, name), dh_retvar(ret), \ - dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ - dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6)); \ -} - -#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7)\ -extern TCGHelperInfo glue(helper_info_, name); \ -static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ - dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6), \ - dh_arg_decl(t7, 7)) \ -{ \ - tcg_gen_call7(&glue(helper_info_, name), dh_retvar(ret), \ - dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ - dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \ - dh_arg(t7, 7)); \ -} - -#include "helper.h" -#include "accel/tcg/tcg-runtime.h" -#include "accel/tcg/plugin-helpers.h" - -#undef DEF_HELPER_FLAGS_0 -#undef DEF_HELPER_FLAGS_1 -#undef DEF_HELPER_FLAGS_2 -#undef DEF_HELPER_FLAGS_3 -#undef DEF_HELPER_FLAGS_4 -#undef DEF_HELPER_FLAGS_5 -#undef DEF_HELPER_FLAGS_6 -#undef DEF_HELPER_FLAGS_7 +#define HELPER_H "helper.h" +#include "exec/helper-gen.h.inc" +#undef HELPER_H =20 #endif /* HELPER_GEN_H */ diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 04a9ca1fc6..f6f05469c5 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -10,7 +10,7 @@ =20 #include "tcg/tcg.h" #include "exec/helper-proto.h" -#include "exec/helper-gen.h" +#include "exec/helper-gen-common.h" =20 /* Basic output routines. Not for general consumption. */ =20 diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 4d84850d74..ce50531dff 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -32,6 +32,9 @@ #include "semihosting/semihost.h" #include "exec/log.h" #include "cpregs.h" +#include "translate.h" +#include "translate-a32.h" +#include "exec/gen-icount.h" =20 #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" @@ -48,9 +51,6 @@ #define ENABLE_ARCH_7 arm_dc_feature(s, ARM_FEATURE_V7) #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8) =20 -#include "translate.h" -#include "translate-a32.h" - /* These are TCG temporaries used only by the legacy iwMMXt decoder */ static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; /* These are TCG globals which alias CPUARMState fields */ @@ -59,8 +59,6 @@ TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; TCGv_i64 cpu_exclusive_addr; TCGv_i64 cpu_exclusive_val; =20 -#include "exec/gen-icount.h" - static const char * const regnames[] =3D { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; diff --git a/include/exec/helper-gen.h.inc b/include/exec/helper-gen.h.inc new file mode 100644 index 0000000000..83bfa5b23f --- /dev/null +++ b/include/exec/helper-gen.h.inc @@ -0,0 +1,101 @@ +/* + * Helper file for declaring TCG helper functions. + * This one expands generation functions for tcg opcodes. + * Define HELPER_H for the header file to be expanded, + * and static inline to change from global file scope. + */ + +#include "tcg/tcg.h" +#include "tcg/helper-info.h" +#include "exec/helper-head.h" + +#define DEF_HELPER_FLAGS_0(name, flags, ret) \ +extern TCGHelperInfo glue(helper_info_, name); \ +static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret)) \ +{ \ + tcg_gen_call0(&glue(helper_info_, name), dh_retvar(ret)); \ +} + +#define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ +extern TCGHelperInfo glue(helper_info_, name); \ +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ + dh_arg_decl(t1, 1)) \ +{ \ + tcg_gen_call1(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1)); \ +} + +#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ +extern TCGHelperInfo glue(helper_info_, name); \ +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) \ +{ \ + tcg_gen_call2(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2)); \ +} + +#define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ +extern TCGHelperInfo glue(helper_info_, name); \ +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \ +{ \ + tcg_gen_call3(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3)); \ +} + +#define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ +extern TCGHelperInfo glue(helper_info_, name); \ +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), \ + dh_arg_decl(t3, 3), dh_arg_decl(t4, 4)) \ +{ \ + tcg_gen_call4(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2), \ + dh_arg(t3, 3), dh_arg(t4, 4)); \ +} + +#define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ +extern TCGHelperInfo glue(helper_info_, name); \ +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ + dh_arg_decl(t4, 4), dh_arg_decl(t5, 5)) \ +{ \ + tcg_gen_call5(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ + dh_arg(t4, 4), dh_arg(t5, 5)); \ +} + +#define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ +extern TCGHelperInfo glue(helper_info_, name); \ +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ + dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6)) \ +{ \ + tcg_gen_call6(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ + dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6)); \ +} + +#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7)\ +extern TCGHelperInfo glue(helper_info_, name); \ +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ + dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6), \ + dh_arg_decl(t7, 7)) \ +{ \ + tcg_gen_call7(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ + dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \ + dh_arg(t7, 7)); \ +} + +#include HELPER_H + +#undef DEF_HELPER_FLAGS_0 +#undef DEF_HELPER_FLAGS_1 +#undef DEF_HELPER_FLAGS_2 +#undef DEF_HELPER_FLAGS_3 +#undef DEF_HELPER_FLAGS_4 +#undef DEF_HELPER_FLAGS_5 +#undef DEF_HELPER_FLAGS_6 +#undef DEF_HELPER_FLAGS_7 --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850025; x=1687442025; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=2BRl6b+qsg5yVXN418PbRw7gzFMzDWkEFGMrhBcGxoc=; b=KOMLNagddM+1xY07UTayzUZ7Tv36RY264jM9o1zvhfm0CvhITn5L0fUwHAz26YKezy HFV7U3llAg0onUjHvQxS7hj13zrMMOG/7qGxiDSXj59PPJO9h0ZGfsusfgImzGY9+S61 IBM9xRVneKK61tFBWHamoG3mNObz8Z3lF6bf6mc+Q3AMovirOdDBZKHqFkP3sO43WXz6 RzRLlbuQS7jw1ft+fBiFWJU7fiAJbHngwHXthmX737lnpksGb+WKkPxhWWq7MPiLTFTO Ff33wLENx5Kcgne9LK2DAcbebCmUifjv5h1vOaq4dPe0wh9UM0Y6AFN+VPdQVuVgUVHZ G/wA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850025; x=1687442025; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2BRl6b+qsg5yVXN418PbRw7gzFMzDWkEFGMrhBcGxoc=; b=SzxbZH8vh1A7vaY6cVrSHmzbv6INYxhgYMGsQu10wBJHo5kVcy7XIEp/qx7LRV3IE8 flPs1lI5duy8qSETDqqErkKUFyoUtyBa0dKynE458fNJYIkdMNVqeff97WSrakwYTLqy D5n9TAJ8WDX3EBdWYpd7auHPw4FRolTKX/be1mL12rvfuCXfJkirQ7TfvEvWUW2Opxpm VeAICpawckU2qWQznsxSfElUXnb37oKacGRHWyo19spZSHmXMKD6ys9lK8O3N4THd4Zf Th47gHrPjY1ljUaI0762njOF2Gsqs6MB8GZYieEGcpMzuLC7j6koMqnfHG5hvVgIXfGo x0UA== X-Gm-Message-State: AC+VfDzH4GaeUbfGIkipfTlcyZVKcKJjUFx/IT0i3lNfkE91PpqFVFW6 c3qeeDKH8R15d8BF7gtCFjQ/rNtBPTg02+hEbvU= X-Google-Smtp-Source: ACHHUZ4q6NjaMNTmrcMdn6tGlOxkX78VlpqkVNnqzIXtFD5UQTqRaeuBtb2tVHKOm1ioar7l/fX8aw== X-Received: by 2002:a05:6a21:33a9:b0:10b:bf3d:bc5d with SMTP id yy41-20020a056a2133a900b0010bbf3dbc5dmr5923044pzb.47.1684850024619; Tue, 23 May 2023 06:53:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 25/52] tcg: Split helper-proto.h Date: Tue, 23 May 2023 06:52:55 -0700 Message-Id: <20230523135322.678948-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684852881554100001 Content-Type: text/plain; charset="utf-8" Create helper-proto-common.h without the target specific portion. Use that in tcg-op-common.h. Include helper-proto.h in target/arm and target/hexagon before helper-info.c.inc; all other targets are already correct in this regard. Signed-off-by: Richard Henderson --- include/exec/helper-proto-common.h | 17 +++++++ include/exec/helper-proto.h | 72 ++++-------------------------- include/tcg/tcg-op-common.h | 2 +- accel/tcg/cputlb.c | 3 +- accel/tcg/plugin-gen.c | 2 +- accel/tcg/tcg-runtime-gvec.c | 2 +- accel/tcg/tcg-runtime.c | 2 +- target/arm/tcg/translate.c | 1 + target/hexagon/translate.c | 1 + include/exec/helper-proto.h.inc | 67 +++++++++++++++++++++++++++ 10 files changed, 99 insertions(+), 70 deletions(-) create mode 100644 include/exec/helper-proto-common.h create mode 100644 include/exec/helper-proto.h.inc diff --git a/include/exec/helper-proto-common.h b/include/exec/helper-proto= -common.h new file mode 100644 index 0000000000..666778473e --- /dev/null +++ b/include/exec/helper-proto-common.h @@ -0,0 +1,17 @@ +/* + * Helper file for declaring TCG helper functions. + * This one expands prototypes for the helper functions. + */ + +#ifndef HELPER_PROTO_COMMON_H +#define HELPER_PROTO_COMMON_H + +#define HELPER_H "accel/tcg/tcg-runtime.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + +#define HELPER_H "accel/tcg/plugin-helpers.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + +#endif /* HELPER_PROTO_COMMON_H */ diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h index 7a3f04b58c..aac684dbbf 100644 --- a/include/exec/helper-proto.h +++ b/include/exec/helper-proto.h @@ -1,71 +1,15 @@ -/* Helper file for declaring TCG helper functions. - This one expands prototypes for the helper functions. */ +/* + * Helper file for declaring TCG helper functions. + * This one expands prototypes for the helper functions. + */ =20 #ifndef HELPER_PROTO_H #define HELPER_PROTO_H =20 -#include "exec/helper-head.h" +#include "exec/helper-proto-common.h" =20 -/* - * Work around an issue with --enable-lto, in which GCC's ipa-split pass - * decides to split out the noreturn code paths that raise an exception, - * taking the __builtin_return_address() along into the new function, - * where it no longer computes a value that returns to TCG generated code. - * Despite the name, the noinline attribute affects splitter, so this - * prevents the optimization in question. Given that helpers should not - * otherwise be called directly, this should have any other visible effect. - * - * See https://gitlab.com/qemu-project/qemu/-/issues/1454 - */ -#define DEF_HELPER_ATTR __attribute__((noinline)) - -#define DEF_HELPER_FLAGS_0(name, flags, ret) \ -dh_ctype(ret) HELPER(name) (void) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1)) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2)) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), \ - dh_ctype(t3)) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ - dh_ctype(t4)) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ - dh_ctype(t4), dh_ctype(t5)) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ - dh_ctype(t4), dh_ctype(t5), \ - dh_ctype(t6)) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ - dh_ctype(t4), dh_ctype(t5), dh_ctype(t6), \ - dh_ctype(t7)) DEF_HELPER_ATTR; - -#define IN_HELPER_PROTO - -#include "helper.h" -#include "accel/tcg/tcg-runtime.h" -#include "accel/tcg/plugin-helpers.h" - -#undef IN_HELPER_PROTO - -#undef DEF_HELPER_FLAGS_0 -#undef DEF_HELPER_FLAGS_1 -#undef DEF_HELPER_FLAGS_2 -#undef DEF_HELPER_FLAGS_3 -#undef DEF_HELPER_FLAGS_4 -#undef DEF_HELPER_FLAGS_5 -#undef DEF_HELPER_FLAGS_6 -#undef DEF_HELPER_FLAGS_7 -#undef DEF_HELPER_ATTR +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H =20 #endif /* HELPER_PROTO_H */ diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index f6f05469c5..be382bbf77 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -9,7 +9,7 @@ #define TCG_TCG_OP_COMMON_H =20 #include "tcg/tcg.h" -#include "exec/helper-proto.h" +#include "exec/helper-proto-common.h" #include "exec/helper-gen-common.h" =20 /* Basic output routines. Not for general consumption. */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 32a4817139..5e2ca47243 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -29,7 +29,7 @@ #include "tcg/tcg.h" #include "qemu/error-report.h" #include "exec/log.h" -#include "exec/helper-proto.h" +#include "exec/helper-proto-common.h" #include "qemu/atomic.h" #include "qemu/atomic128.h" #include "exec/translate-all.h" @@ -41,7 +41,6 @@ #endif #include "tcg/tcg-ldst.h" #include "tcg/oversized-guest.h" -#include "exec/helper-proto.h" =20 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 40b34a0403..3e528f191d 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -49,7 +49,7 @@ #include "exec/exec-all.h" #include "exec/plugin-gen.h" #include "exec/translator.h" -#include "exec/helper-proto.h" +#include "exec/helper-proto-common.h" =20 #define HELPER_H "accel/tcg/plugin-helpers.h" #include "exec/helper-info.c.inc" diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index 97399493d5..6c99f952ca 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qemu/host-utils.h" #include "cpu.h" -#include "exec/helper-proto.h" +#include "exec/helper-proto-common.h" #include "tcg/tcg-gvec-desc.h" =20 =20 diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index 14b59a36e5..9fa539ad3d 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -24,7 +24,7 @@ #include "qemu/osdep.h" #include "qemu/host-utils.h" #include "cpu.h" -#include "exec/helper-proto.h" +#include "exec/helper-proto-common.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "disas/disas.h" diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index ce50531dff..379f266256 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -35,6 +35,7 @@ #include "translate.h" #include "translate-a32.h" #include "exec/gen-icount.h" +#include "exec/helper-proto.h" =20 #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 370dbbaa77..eda384a9db 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -21,6 +21,7 @@ #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "exec/helper-gen.h" +#include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "internal.h" diff --git a/include/exec/helper-proto.h.inc b/include/exec/helper-proto.h.= inc new file mode 100644 index 0000000000..f6f0cfcacd --- /dev/null +++ b/include/exec/helper-proto.h.inc @@ -0,0 +1,67 @@ +/* + * Helper file for declaring TCG helper functions. + * This one expands prototypes for the helper functions. + * Define HELPER_H for the header file to be expanded. + */ + +#include "exec/helper-head.h" + +/* + * Work around an issue with --enable-lto, in which GCC's ipa-split pass + * decides to split out the noreturn code paths that raise an exception, + * taking the __builtin_return_address() along into the new function, + * where it no longer computes a value that returns to TCG generated code. + * Despite the name, the noinline attribute affects splitter, so this + * prevents the optimization in question. Given that helpers should not + * otherwise be called directly, this should have any other visible effect. + * + * See https://gitlab.com/qemu-project/qemu/-/issues/1454 + */ +#define DEF_HELPER_ATTR __attribute__((noinline)) + +#define DEF_HELPER_FLAGS_0(name, flags, ret) \ +dh_ctype(ret) HELPER(name) (void) DEF_HELPER_ATTR; + +#define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ +dh_ctype(ret) HELPER(name) (dh_ctype(t1)) DEF_HELPER_ATTR; + +#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ +dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2)) DEF_HELPER_ATTR; + +#define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ +dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), \ + dh_ctype(t3)) DEF_HELPER_ATTR; + +#define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ +dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ + dh_ctype(t4)) DEF_HELPER_ATTR; + +#define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ +dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ + dh_ctype(t4), dh_ctype(t5)) DEF_HELPER_ATTR; + +#define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ +dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ + dh_ctype(t4), dh_ctype(t5), \ + dh_ctype(t6)) DEF_HELPER_ATTR; + +#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7) \ +dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ + dh_ctype(t4), dh_ctype(t5), dh_ctype(t6), \ + dh_ctype(t7)) DEF_HELPER_ATTR; + +#define IN_HELPER_PROTO + +#include HELPER_H + +#undef IN_HELPER_PROTO + +#undef DEF_HELPER_FLAGS_0 +#undef DEF_HELPER_FLAGS_1 +#undef DEF_HELPER_FLAGS_2 +#undef DEF_HELPER_FLAGS_3 +#undef DEF_HELPER_FLAGS_4 +#undef DEF_HELPER_FLAGS_5 +#undef DEF_HELPER_FLAGS_6 +#undef DEF_HELPER_FLAGS_7 +#undef DEF_HELPER_ATTR --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851386; cv=none; d=zohomail.com; s=zohoarc; b=NUPsb8dhsPKjkdkpnXHM9PbB+CiJukR5f0RKJ5DzOpubscJOgkMGCR/zxRjLG/HKTW/GRehY7aV4a2PT6QhzjWAmRgt/xsPk3HAAUdFm2lO1SZ5aiBi1VwRJfhhyGjBL4TXLQ4EzTE+9FZdNUfutKbxXaA5PfDzafZjHkDvDeHo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851386; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wCcaXZX26ttTE2KUHjwkdjD/eesn8InDS8RkAO1/kaA=; b=ZWiQHJnw/LGtMx+yUC5ryVLQ8GENMZhaXDXfe7Ss6mrDwIarVwX/1/btZAl8ESgzQQjBEqeFv1mz4rWEr2Vc6T+VH24n2oWL/26l8Y+xWynNC5zsOxPYmWFMwxNnfUmsx8hzKDOrf8riW7Ca5A5mjntnF/svitocO5EqdE4slLE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684851386377503.152367482906; Tue, 23 May 2023 07:16:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1STY-0008W3-Jv; Tue, 23 May 2023 09:55:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSU-00054U-3x for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:52 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSR-00037f-TF for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:49 -0400 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-64d2a87b9daso3899477b3a.0 for ; Tue, 23 May 2023 06:53:47 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850026; x=1687442026; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wCcaXZX26ttTE2KUHjwkdjD/eesn8InDS8RkAO1/kaA=; b=qxp2U+PYVCQfLSFX2I/kK5ynr7NAOcpFSKCSZsmEbfC+0KAun9XrRh5Pf+5ggETmS4 MDsp3g5AFqqsordcbRfz8XTvkSVGn+4VtIQTi4qUiELe5f2VdWUyBQbKGpzEuTxPtYrG SuxyMRQ7R2eZ/ioDfqaQAJBJLL7arGsUkG1cZaToBm2UU0awQ3kUFDSfmioyjJS04Atu zrBrCRKHWXQOeEAom3Yrx5oWjqhg9Xupgsng9vJq/8aNkaQ84+3BF6sRtB4m1AUwdyJw wxgU0t2mtaLA2hbsPGoDRzXhlE/qWhWANM2fljgq+KeaAIOqlwMiTiG2k0X/OwV4/kxy NOvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850026; x=1687442026; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wCcaXZX26ttTE2KUHjwkdjD/eesn8InDS8RkAO1/kaA=; b=GplSMzAiZHzV5e2240IuGfgtFRBQ5C8y3VDjHM7TkO81ezU2yBFaSB8IMWy6vQiVls 34i18/QGRe/NXls5PwBsDhn2vizMZ3/tPHfdlquNYaNlz3ukRlVw4P8VO7WioLnschLo Yc2ltHBiWJUGIT/qryMvu6skMu2/zVg/+BygOGfDjaa10FfJfFh8aX+/3gdu6DzGnuFM WRndeIiBZkglAZ90gxuyC0qU7RpoMwsRZYTZf09Tgw09/FNKYM2w/57KKT9fmxnjdDx8 Sd365c9pzFbz5Wzfg2hvsJJRGUIgWyJcf/3a4huRzmF71+GNA9fCUWy2dYuePuNiQh7V nLSw== X-Gm-Message-State: AC+VfDxP0c5MjDIxkN+W02RA5NvD33yLdbRUYlEqPfkYFqJ6Wo8dSj3/ vd2ggpIViZebs/azaeZx1nbHoNL/ClShRNYq484= X-Google-Smtp-Source: ACHHUZ6gd33EKP5PM9HZgnRkAaJI5iTwcZ8L4vk0krVFRkiuOXNAq1WjZfYwzWU6N9ggUVRw18OzlQ== X-Received: by 2002:a05:6a00:1783:b0:644:d775:60bb with SMTP id s3-20020a056a00178300b00644d77560bbmr20508990pfg.20.1684850025407; Tue, 23 May 2023 06:53:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 26/52] tcg: Add insn_start_words to TCGContext Date: Tue, 23 May 2023 06:52:56 -0700 Message-Id: <20230523135322.678948-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851388577100007 Content-Type: text/plain; charset="utf-8" This will enable replacement of TARGET_INSN_START_WORDS in tcg.c. Split out "tcg/insn-start-words.h" and use it in target/. Signed-off-by: Richard Henderson --- include/tcg/insn-start-words.h | 17 +++++++++++++++++ include/tcg/tcg-op.h | 8 ++++---- include/tcg/tcg-opc.h | 6 +++--- include/tcg/tcg.h | 9 ++------- accel/tcg/perf.c | 8 ++++++-- accel/tcg/translate-all.c | 13 ++++++++----- target/i386/helper.c | 2 +- target/openrisc/sys_helper.c | 2 +- tcg/tcg.c | 16 +++++++++++----- 9 files changed, 53 insertions(+), 28 deletions(-) create mode 100644 include/tcg/insn-start-words.h diff --git a/include/tcg/insn-start-words.h b/include/tcg/insn-start-words.h new file mode 100644 index 0000000000..50c18bd326 --- /dev/null +++ b/include/tcg/insn-start-words.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define TARGET_INSN_START_WORDS + * Copyright (c) 2008 Fabrice Bellard + */ + +#ifndef TARGET_INSN_START_WORDS + +#include "cpu.h" + +#ifndef TARGET_INSN_START_EXTRA_WORDS +# define TARGET_INSN_START_WORDS 1 +#else +# define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) +#endif + +#endif /* TARGET_INSN_START_WORDS */ diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 47f1dce816..d63683c47b 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -22,20 +22,20 @@ # error #endif =20 -#if TARGET_INSN_START_WORDS =3D=3D 1 +#ifndef TARGET_INSN_START_EXTRA_WORDS static inline void tcg_gen_insn_start(target_ulong pc) { TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BIT= S); tcg_set_insn_start_param(op, 0, pc); } -#elif TARGET_INSN_START_WORDS =3D=3D 2 +#elif TARGET_INSN_START_EXTRA_WORDS =3D=3D 1 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) { TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, 2 * 64 / TCG_TARGET_REG= _BITS); tcg_set_insn_start_param(op, 0, pc); tcg_set_insn_start_param(op, 1, a1); } -#elif TARGET_INSN_START_WORDS =3D=3D 3 +#elif TARGET_INSN_START_EXTRA_WORDS =3D=3D 2 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, target_ulong a2) { @@ -45,7 +45,7 @@ static inline void tcg_gen_insn_start(target_ulong pc, ta= rget_ulong a1, tcg_set_insn_start_param(op, 2, a2); } #else -# error "Unhandled number of operands to insn_start" +#error Unhandled TARGET_INSN_START_EXTRA_WORDS value #endif =20 #if TARGET_LONG_BITS =3D=3D 32 diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 21594c1590..acfa5ba753 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -188,9 +188,9 @@ DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mu= lsh_i64)) =20 #define DATA64_ARGS (TCG_TARGET_REG_BITS =3D=3D 64 ? 1 : 2) =20 -/* QEMU specific */ -DEF(insn_start, 0, 0, DATA64_ARGS * TARGET_INSN_START_WORDS, - TCG_OPF_NOT_PRESENT) +/* There are tcg_ctx->insn_start_words here, not just one. */ +DEF(insn_start, 0, 0, DATA64_ARGS, TCG_OPF_NOT_PRESENT) + DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 7c1bbba673..813c733910 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -173,12 +173,6 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_v256 0 #endif =20 -#ifndef TARGET_INSN_START_EXTRA_WORDS -# define TARGET_INSN_START_WORDS 1 -#else -# define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) -#endif - typedef enum TCGOpcode { #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, #include "tcg/tcg-opc.h" @@ -526,6 +520,7 @@ struct TCGContext { uint8_t page_bits; uint8_t tlb_dyn_max_bits; #endif + uint8_t insn_start_words; =20 TCGRegSet reserved_regs; intptr_t current_frame_offset; @@ -597,7 +592,7 @@ struct TCGContext { TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; =20 uint16_t gen_insn_end_off[TCG_MAX_INSNS]; - uint64_t gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; + uint64_t *gen_insn_data; =20 /* Exit to translator on overflow. */ sigjmp_buf jmp_trans; diff --git a/accel/tcg/perf.c b/accel/tcg/perf.c index 65e35ea3b9..f5a1eda39f 100644 --- a/accel/tcg/perf.c +++ b/accel/tcg/perf.c @@ -311,7 +311,8 @@ void perf_report_code(uint64_t guest_pc, TranslationBlo= ck *tb, const void *start) { struct debuginfo_query *q; - size_t insn; + size_t insn, start_words; + uint64_t *gen_insn_data; =20 if (!perfmap && !jitdump) { return; @@ -325,9 +326,12 @@ void perf_report_code(uint64_t guest_pc, TranslationBl= ock *tb, debuginfo_lock(); =20 /* Query debuginfo for each guest instruction. */ + gen_insn_data =3D tcg_ctx->gen_insn_data; + start_words =3D tcg_ctx->insn_start_words; + for (insn =3D 0; insn < tb->icount; insn++) { /* FIXME: This replicates the restore_state_to_opc() logic. */ - q[insn].address =3D tcg_ctx->gen_insn_data[insn][0]; + q[insn].address =3D gen_insn_data[insn * start_words + 0]; if (tb_cflags(tb) & CF_PCREL) { q[insn].address |=3D (guest_pc & TARGET_PAGE_MASK); } else { diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index be38d4aad8..03ebe58099 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -64,6 +64,7 @@ #include "tb-context.h" #include "internal.h" #include "perf.h" +#include "tcg/insn-start-words.h" =20 /* Make sure all possible CPU event bits fit in tb->trace_vcpu_dstate */ QEMU_BUILD_BUG_ON(CPU_TRACE_DSTATE_MAX_EVENTS > @@ -132,19 +133,20 @@ static int64_t decode_sleb128(const uint8_t **pp) static int encode_search(TranslationBlock *tb, uint8_t *block) { uint8_t *highwater =3D tcg_ctx->code_gen_highwater; + uint64_t *insn_data =3D tcg_ctx->gen_insn_data; uint8_t *p =3D block; int i, j, n; =20 for (i =3D 0, n =3D tb->icount; i < n; ++i) { uint64_t prev; =20 - for (j =3D 0; j < TARGET_INSN_START_WORDS; ++j) { + for (j =3D 0; j < TARGET_INSN_START_WORDS; ++j, ++insn_data) { if (i =3D=3D 0) { prev =3D (!(tb_cflags(tb) & CF_PCREL) && j =3D=3D 0 ? tb->= pc : 0); } else { - prev =3D tcg_ctx->gen_insn_data[i - 1][j]; + prev =3D insn_data[-TARGET_INSN_START_WORDS]; } - p =3D encode_sleb128(p, tcg_ctx->gen_insn_data[i][j] - prev); + p =3D encode_sleb128(p, *insn_data - prev); } prev =3D (i =3D=3D 0 ? 0 : tcg_ctx->gen_insn_end_off[i - 1]); p =3D encode_sleb128(p, tcg_ctx->gen_insn_end_off[i] - prev); @@ -364,6 +366,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->tlb_fast_offset =3D (int)offsetof(ArchCPU, neg.tlb.f) - (int)offsetof(ArchCPU, env); #endif + tcg_ctx->insn_start_words =3D TARGET_INSN_START_WORDS; =20 tb_overflow: =20 @@ -458,7 +461,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, fprintf(logfile, "OUT: [size=3D%d]\n", gen_code_size); fprintf(logfile, " -- guest addr 0x%016" PRIx64 " + tb prologue\n", - tcg_ctx->gen_insn_data[insn][0]); + tcg_ctx->gen_insn_data[insn * TARGET_INSN_START_WORDS]= ); chunk_start =3D tcg_ctx->gen_insn_end_off[insn]; disas(logfile, tb->tc.ptr, chunk_start); =20 @@ -471,7 +474,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, size_t chunk_end =3D tcg_ctx->gen_insn_end_off[insn]; if (chunk_end > chunk_start) { fprintf(logfile, " -- guest addr 0x%016" PRIx64 "\n", - tcg_ctx->gen_insn_data[insn][0]); + tcg_ctx->gen_insn_data[insn * TARGET_INSN_STAR= T_WORDS]); disas(logfile, tb->tc.ptr + chunk_start, chunk_end - chunk_start); chunk_start =3D chunk_end; diff --git a/target/i386/helper.c b/target/i386/helper.c index 682d10d98a..36bf2107e7 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -29,7 +29,7 @@ #endif #include "qemu/log.h" #ifdef CONFIG_TCG -#include "tcg/tcg.h" +#include "tcg/insn-start-words.h" #endif =20 void cpu_sync_avx_hflag(CPUX86State *env) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 110f157601..782a5751b7 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -26,7 +26,7 @@ #ifndef CONFIG_USER_ONLY #include "hw/boards.h" #endif -#include "tcg/tcg.h" +#include "tcg/insn-start-words.h" =20 #define TO_SPR(group, number) (((group) << 11) + (number)) =20 diff --git a/tcg/tcg.c b/tcg/tcg.c index 57600f41ac..3888a22ba1 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1506,6 +1506,8 @@ void tcg_func_start(TCGContext *s) tcg_debug_assert(s->tlb_fast_offset < 0); tcg_debug_assert(s->tlb_fast_offset >=3D MIN_TLB_MASK_TABLE_OFS); #endif + + tcg_debug_assert(s->insn_start_words > 0); } =20 static TCGTemp *tcg_temp_alloc(TCGContext *s) @@ -2450,7 +2452,7 @@ static void tcg_dump_ops(TCGContext *s, FILE *f, bool= have_prefs) nb_oargs =3D 0; col +=3D ne_fprintf(f, "\n ----"); =20 - for (i =3D 0; i < TARGET_INSN_START_WORDS; ++i) { + for (i =3D 0, k =3D s->insn_start_words; i < k; ++i) { col +=3D ne_fprintf(f, " %016" PRIx64, tcg_get_insn_start_param(op, i)); } @@ -6029,7 +6031,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= uint64_t pc_start) #ifdef CONFIG_PROFILER TCGProfile *prof =3D &s->prof; #endif - int i, num_insns; + int i, start_words, num_insns; TCGOp *op; =20 #ifdef CONFIG_PROFILER @@ -6159,6 +6161,10 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb= , uint64_t pc_start) s->pool_labels =3D NULL; #endif =20 + start_words =3D s->insn_start_words; + s->gen_insn_data =3D + tcg_malloc(sizeof(uint64_t) * s->gen_tb->icount * start_words); + num_insns =3D -1; QTAILQ_FOREACH(op, &s->ops, link) { TCGOpcode opc =3D op->opc; @@ -6184,8 +6190,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= uint64_t pc_start) assert(s->gen_insn_end_off[num_insns] =3D=3D off); } num_insns++; - for (i =3D 0; i < TARGET_INSN_START_WORDS; ++i) { - s->gen_insn_data[num_insns][i] =3D + for (i =3D 0; i < start_words; ++i) { + s->gen_insn_data[num_insns * start_words + i] =3D tcg_get_insn_start_param(op, i); } break; @@ -6231,7 +6237,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= uint64_t pc_start) return -2; } } - tcg_debug_assert(num_insns >=3D 0); + tcg_debug_assert(num_insns + 1 =3D=3D s->gen_tb->icount); s->gen_insn_end_off[num_insns] =3D tcg_current_code_size(s); =20 /* Generate TB finalization at the end of block */ --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850026; x=1687442026; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=4h70UmOuZApqGwH8fl/aBGmj5U+73aMDvSoJL1qlazg=; b=DQKN1RmhsM1WfV3sb9RmlkUxVXfYbojqu1dvscpbTZbzz7nREbkM7i/8ahnlouwUqF PlvxwIAN6HgS3fyOREULmzlaZsP12JPsC7ZRKMhwYAEKrwSwmCiH8Ty8hihVKvYMAhDU iFusDgOQF9uQnCVs9uuCwcRvx1zPkrqCM3uleWN0qFmqV4OP/EXa0T1SUG0iRT653JIL CN8t0LdtIy+ZZoLf/zpDZKutkKaUXzYv38h2thiczlhMt+AowyGmhdC+vrXp+9xGkeRr pxxFW6O183wKDNE3nvQFtMGTegPv41UyKLONejg8YHtGUppJAOWB76pxTvGAyq8sloQT KOKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850026; x=1687442026; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4h70UmOuZApqGwH8fl/aBGmj5U+73aMDvSoJL1qlazg=; b=KEvSK6w3rw9WLSKMB1wuwMLSG1+EWWS11WiEwZ5+zVEuxSngBpXWE9mFcz6wCVkAi7 lhjMnv6+fF5HTfLocT+dqBpjRe1AODsV+mOkFjCwbl4lwcUsCKNzaxeBDs/zY4LpqzzX jHtyEA3k8ce7cSM38VCBQv5jjsi7sKGYgcu1U/DXbwtr1LWTJ2XG0NuYBCNkJLYDYVGj PL6XVG4f3dAwZT3F1Q9+6UmSW0NpcCGb/PDwcahSpLPJtmaHxIG/HZw+K4qJH600Vjv0 vXFi6htinI+ap2uziplMX8tyYSK0OOR6+OIcusD5mS3qVEBZJAgahvWVr9pad++R4+US 8YVA== X-Gm-Message-State: AC+VfDzTHM9ukrgpISnsW9rzslSQxQT2unuXXaAzPHbkiIkT2flkU2qH zJb6sXeajGoYgAboJooNyN8LY2rMRWYLgv37sx8= X-Google-Smtp-Source: ACHHUZ7K2MwO88dnYrW4hPovmBpKD9E9afT6WvzsJulTNx7HKJxobgo3Kwfpc3axC/6SaIx1JYxJ3Q== X-Received: by 2002:a05:6a00:a14:b0:647:2ce5:57c4 with SMTP id p20-20020a056a000a1400b006472ce557c4mr19913958pfh.5.1684850026152; Tue, 23 May 2023 06:53:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 27/52] tcg: Add guest_mo to TCGContext Date: Tue, 23 May 2023 06:52:57 -0700 Message-Id: <20230523135322.678948-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684852679698100003 Content-Type: text/plain; charset="utf-8" This replaces of TCG_GUEST_DEFAULT_MO in tcg-op-ldst.c. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 + accel/tcg/translate-all.c | 5 +++++ tcg/tcg-op-ldst.c | 4 +--- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 813c733910..9f607e2664 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -521,6 +521,7 @@ struct TCGContext { uint8_t tlb_dyn_max_bits; #endif uint8_t insn_start_words; + TCGBar guest_mo; =20 TCGRegSet reserved_regs; intptr_t current_frame_offset; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 03ebe58099..181f276b18 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -367,6 +367,11 @@ TranslationBlock *tb_gen_code(CPUState *cpu, (int)offsetof(ArchCPU, neg.tlb.f) - (int)offsetof(ArchCPU, env); #endif tcg_ctx->insn_start_words =3D TARGET_INSN_START_WORDS; +#ifdef TCG_GUEST_DEFAULT_MO + tcg_ctx->guest_mo =3D TCG_GUEST_DEFAULT_MO; +#else + tcg_ctx->guest_mo =3D TCG_MO_ALL; +#endif =20 tb_overflow: =20 diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index aae74f4341..55338ef0d7 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -104,9 +104,7 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 v, TCG= Temp *addr, MemOpIdx oi) =20 static void tcg_gen_req_mo(TCGBar type) { -#ifdef TCG_GUEST_DEFAULT_MO - type &=3D TCG_GUEST_DEFAULT_MO; -#endif + type &=3D tcg_ctx->guest_mo; type &=3D ~TCG_TARGET_DEFAULT_MO; if (type) { tcg_gen_mb(type | TCG_BAR_SC); --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851031; cv=none; d=zohomail.com; s=zohoarc; b=jhg1ZB3IMrzCE9N4y5OAGksoQzp9RCWVP/Gb7kGuInbldE5lA9BrXECZw66UMPdg3Z3sWt1XQxdxyfHrj84tojIaz8iuj5pimay6pS1qCYc1ec2GOL4vYwy04p1JuMzEDBlgf1dBbegbFofN2A8UEuCgUBLa6b6UX7S6d4mSKLk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851031; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Mi17CjRnKz4wPdo7CNg1kS18indd07wo46SSX6kjRvg=; b=gL3HfXEjExuqyAWAWNQoKkfL8j8ptbk4t+ldOexunAyBZOT8bMhqEp5vab669mlFvI2VWrfU7axMNvDGlbV7chkusq0vkpN8oqf9/ZDFhk1jrY/2x+huVQOI88JbcoRjKYT/Hgk5tWssdOxwG6PUApUMslaHZ2Jq9ex7c9w9iDY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684851031167753.0372915721302; Tue, 23 May 2023 07:10:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1ST8-0006eC-LH; Tue, 23 May 2023 09:54:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSV-00056D-FU for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:52 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSS-00037m-1v for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:51 -0400 Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-64d604cc0aaso2243932b3a.2 for ; Tue, 23 May 2023 06:53:47 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850027; x=1687442027; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Mi17CjRnKz4wPdo7CNg1kS18indd07wo46SSX6kjRvg=; b=XUmaNWEDS7d31gEkK6by98OdvVyfgFx0kORiLM1SCNcB4QeqT2IwLx3XsUp8Oia/zp S82pZjFkNerHkG8uVlIVApc17jyhHEELiNVYaN9EIYho4W0nLGZ2Md1KZgs6Ys/fkVyq 4BfiIPJfChtJkuqmL9SrFjitOwU7yTot1+0cz8HxNjrNZ9L5hQ1Lavmp+PSD4+4rK/T/ 2GDnGwGRuN7bBgz00CmfM+yX4NZg2x9pwnWuI2lh670YaoaZF6F0Zc9he3ERPKuCSHdO 81grwIfCCY5gJgLtMhJxpX5Sn4NrkVaTLG/y+eu69HGJANrHkyONHRYhjwP89Pb+Wreg AM4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850027; x=1687442027; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mi17CjRnKz4wPdo7CNg1kS18indd07wo46SSX6kjRvg=; b=W2GH7HgMtaI+MSUCsiVFW1V0XRmmIpnICHtPZt54J1IITqzgCxSZnQOeRf/XCimhY3 4Jf/PCIxiBdGAAiiSvqzt0QqCViqLPOyyZw0klpJABan8SxA3J2oZz4UJ9oTcH68CpkP kPp5NpXd+xbqF9GK7diSrejXjUSNK48kUwNFZhunQtu/DeA74Ha5fYAv3Z5sQRfBS2Eq vMxN/CD5ix/AVI1rZ8pPeniBoUQYEK1h3PDdmoD7ErnAXFHASinWV13/GsEp8unOtiCI VFjaqzNvI0FV5hWaLbW08fNWyWyT9n2jEhysDFV20rQXDH9dxOuMV4TmTQrhlzDin+Gp zv0A== X-Gm-Message-State: AC+VfDxhqvjdiN43bD+G6orsS7no1poM+oFpko9z/FL/cSq5mTKGnxi/ WvrNED+atqukLromtUz3fxxXGz27bqQf4kefI/U= X-Google-Smtp-Source: ACHHUZ7OLeDl0CgYeNhJuhtKlOpZ/FwTl/wdkNSINNC43wQ2Yni8tq4w3n8UYOTN4qpiB60ZSaOfSw== X-Received: by 2002:a05:6a20:8f14:b0:10b:27d0:70cc with SMTP id b20-20020a056a208f1400b0010b27d070ccmr10045239pzk.20.1684850026874; Tue, 23 May 2023 06:53:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 28/52] tcg: Move TLB_FLAGS_MASK check out of get_alignment_bits Date: Tue, 23 May 2023 06:52:58 -0700 Message-Id: <20230523135322.678948-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851031814100001 Content-Type: text/plain; charset="utf-8" The replacement isn't ideal, as the raw count of bits is not easily synced with exec/cpu-all.h, but it does remove from tcg.h the target dependency on TARGET_PAGE_BITS_MIN which is built into TLB_FLAGS_MASK. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 3 +++ include/tcg/tcg.h | 4 ---- tcg/tcg-op-ldst.c | 18 ++++++++++++++++-- 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 78d258af44..09bf4c0cc6 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -314,6 +314,9 @@ CPUArchState *cpu_copy(CPUArchState *env); * * Use TARGET_PAGE_BITS_MIN so that these bits are constant * when TARGET_PAGE_BITS_VARY is in effect. + * + * The count, if not the placement of these bits is known + * to tcg/tcg-op-ldst.c, check_max_alignment(). */ /* Zero if TLB entry is valid. */ #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 9f607e2664..635fa53fdb 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -305,10 +305,6 @@ static inline unsigned get_alignment_bits(MemOp memop) /* A specific alignment requirement. */ a =3D a >> MO_ASHIFT; } -#if defined(CONFIG_SOFTMMU) - /* The requested alignment cannot overlap the TLB flags. */ - tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) =3D=3D 0); -#endif return a; } =20 diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 55338ef0d7..02827b96cc 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -32,11 +32,23 @@ #include "tcg-internal.h" =20 =20 -static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st) +static void check_max_alignment(unsigned a_bits) +{ +#if defined(CONFIG_SOFTMMU) + /* + * The requested alignment cannot overlap the TLB flags. + * FIXME: Must keep the count up-to-date with "exec/cpu-all.h". + */ + tcg_debug_assert(a_bits + 6 <=3D tcg_ctx->page_bits); +#endif +} + +static MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st) { - /* Trigger the asserts within as early as possible. */ unsigned a_bits =3D get_alignment_bits(op); =20 + check_max_alignment(a_bits); + /* Prefer MO_ALIGN+MO_XX over MO_ALIGN_XX+MO_XX */ if (a_bits =3D=3D (op & MO_SIZE)) { op =3D (op & ~MO_AMASK) | MO_ALIGN; @@ -491,6 +503,7 @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCG= Temp *addr, TCGv_i64 ext_addr =3D NULL; TCGOpcode opc; =20 + check_max_alignment(get_alignment_bits(memop)); tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); =20 /* TODO: For now, force 32-bit hosts to use the helper. */ @@ -599,6 +612,7 @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCG= Temp *addr, TCGv_i64 ext_addr =3D NULL; TCGOpcode opc; =20 + check_max_alignment(get_alignment_bits(memop)); tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); =20 /* TODO: For now, force 32-bit hosts to use the helper. */ --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684854720; cv=none; d=zohomail.com; s=zohoarc; b=G47Qolvy1ntiALyUe3JvUjiOhTAhjcpNKd5ib/dXjTjyDYqc54pP9TiFfIxndpV6LNrR3mlzUl8ht+ItTHyFMU6LSu8HTRXb2p2y+DvwylAWI9xApxsrNmZqTbHPOZcIyMcSUZgVZpf+7201wuEbCIBBFwnyrRcPrKXzi/hB9GM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684854720; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xLxyYSdoAT/V2nwQqAf/ew1zY58jY8stWGFlvcTxHG4=; b=CzmXGXwAknI+FRlRiNUvzWx6Y+C2Rdn2uEQfR1SeAFzfc51kETnZ0J8HDWgjOIA7+12/Ymz9ykY7rLiYImGahRqzZrghbHVjBzuKxxIfQTR1PWXyrbQELVG2lYBPH6/Kkh0mfYswMej+DoWrNE+vh2cjpn6fcXL9H4iiQkJ9qVY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684854720632140.8808536750514; Tue, 23 May 2023 08:12:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1STs-0000BO-5k; Tue, 23 May 2023 09:55:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSX-00059I-UR for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:54 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SST-000384-Nf for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:53 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-64d247a023aso4101882b3a.2 for ; Tue, 23 May 2023 06:53:48 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850028; x=1687442028; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=xLxyYSdoAT/V2nwQqAf/ew1zY58jY8stWGFlvcTxHG4=; b=ivK4dYHxUPfueGTMrV7/Z/AGzZXxwr2BtzMPPoGzNbq9SK+xFADrkbKyJycLIeLJcu 80VeZ7uJyyke5f2r8Zbaw7vkUmfaHZG1/PijEfvGxh+HdOCjq2xnKN1co9QzfmzYDJ2r gBP+EaQ6ss9wod6zcmY0RFperyXDT3AmothHEVApSdL8JWh0IIuKA9NUmwYJYoY6/EMw ifYzJw+1HRkXrWqIxPd08xMgx2okWpd1QBmJAcdiRH23812ymx/P0G8azJOSv4fnJDdW jCoFtgcd9cIma5fFKFlGXzIGrs09Ojqh74uW6kG3kg6D5A5HpXMrWF72jx3o59GJe5vS +rXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850028; x=1687442028; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xLxyYSdoAT/V2nwQqAf/ew1zY58jY8stWGFlvcTxHG4=; b=M65myU5H29VoDffectSzmmQbckpff3+wdYf/5jcyktr4DVEzxU27a5I6ZkrM8gVETr yGxf+W49Cvo97P/0j3m8uhWXlY5vHiJ8dL0tMDaYiE2CXDmNJk+q0eZn//etyZE4m2QE mvQj509o+FAdZg4XG7xHmjlN6DNyfwg/R7Pdai485TXs0sEGGR5LKC7wyAPnoSLJyREt OCRNyIsj/pQqDVyZ+qPMI3HsWPk6H9HEs7M4YNlP/JqJHnSBASNgFCg7Kdr8kMi/qj5K CGxm0RBiZMLO5w94tCJeeQqi8tWvFifjWZGZCrJeGS3BA+feL/s13twEABHGrD9A2BhF 3NcA== X-Gm-Message-State: AC+VfDxOfM439S/YLfS+m9ocv9/21GglFnEL768G4UjDfBiwwki12YeT 0Bc0hi7mRyUEFvd1AZnic7hs6/oerxym+zp3CDw= X-Google-Smtp-Source: ACHHUZ7SzQwvDaCCEpffgfWvWYhuo5ki2O5Uhz6gWww5HRd2jiAy7Mn3caZw745Z8LQZ/d6eUJEk5Q== X-Received: by 2002:a05:6a00:1828:b0:643:98cb:ec1 with SMTP id y40-20020a056a00182800b0064398cb0ec1mr18802462pfa.0.1684850027762; Tue, 23 May 2023 06:53:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 29/52] tcg: Split tcg/tcg-op-gvec.h Date: Tue, 23 May 2023 06:52:59 -0700 Message-Id: <20230523135322.678948-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684854722313100001 Content-Type: text/plain; charset="utf-8" Create tcg/tcg-op-gvec-common.h, moving everything that does not concern TARGET_LONG_BITS. Adjust tcg-op-gvec.c to use the new header. Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec-common.h | 426 +++++++++++++++++++++++++++++ include/tcg/tcg-op-gvec.h | 444 +------------------------------ tcg/tcg-op-gvec.c | 2 +- 3 files changed, 437 insertions(+), 435 deletions(-) create mode 100644 include/tcg/tcg-op-gvec-common.h diff --git a/include/tcg/tcg-op-gvec-common.h b/include/tcg/tcg-op-gvec-com= mon.h new file mode 100644 index 0000000000..e2683d487f --- /dev/null +++ b/include/tcg/tcg-op-gvec-common.h @@ -0,0 +1,426 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Target independent generic vector operation expansion + * + * Copyright (c) 2018 Linaro + */ + +#ifndef TCG_TCG_OP_GVEC_COMMON_H +#define TCG_TCG_OP_GVEC_COMMON_H + +/* + * "Generic" vectors. All operands are given as offsets from ENV, + * and therefore cannot also be allocated via tcg_global_mem_new_*. + * OPRSZ is the byte size of the vector upon which the operation is perfor= med. + * MAXSZ is the byte size of the full vector; bytes beyond OPSZ are cleare= d. + * + * All sizes must be 8 or any multiple of 16. + * When OPRSZ is 8, the alignment may be 8, otherwise must be 16. + * Operands may completely, but not partially, overlap. + */ + +/* Expand a call to a gvec-style helper, with pointers to two vector + operands, and a descriptor (see tcg-gvec-desc.h). */ +typedef void gen_helper_gvec_2(TCGv_ptr, TCGv_ptr, TCGv_i32); +void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz, int32_t data, + gen_helper_gvec_2 *fn); + +/* Similarly, passing an extra data value. */ +typedef void gen_helper_gvec_2i(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32); +void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c, + uint32_t oprsz, uint32_t maxsz, int32_t data, + gen_helper_gvec_2i *fn); + +/* Similarly, passing an extra pointer (e.g. env or float_status). */ +typedef void gen_helper_gvec_2_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); +void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs, + TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz, + int32_t data, gen_helper_gvec_2_ptr *fn); + +/* Similarly, with three vector operands. */ +typedef void gen_helper_gvec_3(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); +void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz, int32_t data, + gen_helper_gvec_3 *fn); + +/* Similarly, with four vector operands. */ +typedef void gen_helper_gvec_4(TCGv_ptr, TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_i32); +void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t cofs, uint32_t oprsz, uint32_t maxsz, + int32_t data, gen_helper_gvec_4 *fn); + +/* Similarly, with five vector operands. */ +typedef void gen_helper_gvec_5(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_i32); +void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t cofs, uint32_t xofs, uint32_t oprsz, + uint32_t maxsz, int32_t data, gen_helper_gvec_5 *f= n); + +typedef void gen_helper_gvec_3_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_i32); +void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, + TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz, + int32_t data, gen_helper_gvec_3_ptr *fn); + +typedef void gen_helper_gvec_4_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_ptr, TCGv_i32); +void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t cofs, TCGv_ptr ptr, uint32_t oprsz, + uint32_t maxsz, int32_t data, + gen_helper_gvec_4_ptr *fn); + +typedef void gen_helper_gvec_5_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_ptr, TCGv_i32); +void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t cofs, uint32_t eofs, TCGv_ptr ptr, + uint32_t oprsz, uint32_t maxsz, int32_t data, + gen_helper_gvec_5_ptr *fn); + +/* Expand a gvec operation. Either inline or out-of-line depending on + the actual vector size and the operations supported by the host. */ +typedef struct { + /* Expand inline as a 64-bit or 32-bit integer. + Only one of these will be non-NULL. */ + void (*fni8)(TCGv_i64, TCGv_i64); + void (*fni4)(TCGv_i32, TCGv_i32); + /* Expand inline with a host vector type. */ + void (*fniv)(unsigned, TCGv_vec, TCGv_vec); + /* Expand out-of-line helper w/descriptor. */ + gen_helper_gvec_2 *fno; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; + /* The data argument to the out-of-line helper. */ + int32_t data; + /* The vector element size, if applicable. */ + uint8_t vece; + /* Prefer i64 to v64. */ + bool prefer_i64; + /* Load dest as a 2nd source operand. */ + bool load_dest; +} GVecGen2; + +typedef struct { + /* Expand inline as a 64-bit or 32-bit integer. + Only one of these will be non-NULL. */ + void (*fni8)(TCGv_i64, TCGv_i64, int64_t); + void (*fni4)(TCGv_i32, TCGv_i32, int32_t); + /* Expand inline with a host vector type. */ + void (*fniv)(unsigned, TCGv_vec, TCGv_vec, int64_t); + /* Expand out-of-line helper w/descriptor, data in descriptor. */ + gen_helper_gvec_2 *fno; + /* Expand out-of-line helper w/descriptor, data as argument. */ + gen_helper_gvec_2i *fnoi; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; + /* The vector element size, if applicable. */ + uint8_t vece; + /* Prefer i64 to v64. */ + bool prefer_i64; + /* Load dest as a 3rd source operand. */ + bool load_dest; +} GVecGen2i; + +typedef struct { + /* Expand inline as a 64-bit or 32-bit integer. + Only one of these will be non-NULL. */ + void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64); + void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32); + /* Expand inline with a host vector type. */ + void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec); + /* Expand out-of-line helper w/descriptor. */ + gen_helper_gvec_2i *fno; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; + /* The data argument to the out-of-line helper. */ + uint32_t data; + /* The vector element size, if applicable. */ + uint8_t vece; + /* Prefer i64 to v64. */ + bool prefer_i64; + /* Load scalar as 1st source operand. */ + bool scalar_first; +} GVecGen2s; + +typedef struct { + /* Expand inline as a 64-bit or 32-bit integer. + Only one of these will be non-NULL. */ + void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64); + void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32); + /* Expand inline with a host vector type. */ + void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec); + /* Expand out-of-line helper w/descriptor. */ + gen_helper_gvec_3 *fno; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; + /* The data argument to the out-of-line helper. */ + int32_t data; + /* The vector element size, if applicable. */ + uint8_t vece; + /* Prefer i64 to v64. */ + bool prefer_i64; + /* Load dest as a 3rd source operand. */ + bool load_dest; +} GVecGen3; + +typedef struct { + /* + * Expand inline as a 64-bit or 32-bit integer. Only one of these will= be + * non-NULL. + */ + void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, int64_t); + void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, int32_t); + /* Expand inline with a host vector type. */ + void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, int64_t); + /* Expand out-of-line helper w/descriptor, data in descriptor. */ + gen_helper_gvec_3 *fno; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; + /* The vector element size, if applicable. */ + uint8_t vece; + /* Prefer i64 to v64. */ + bool prefer_i64; + /* Load dest as a 3rd source operand. */ + bool load_dest; +} GVecGen3i; + +typedef struct { + /* Expand inline as a 64-bit or 32-bit integer. + Only one of these will be non-NULL. */ + void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64); + void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32); + /* Expand inline with a host vector type. */ + void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec); + /* Expand out-of-line helper w/descriptor. */ + gen_helper_gvec_4 *fno; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; + /* The data argument to the out-of-line helper. */ + int32_t data; + /* The vector element size, if applicable. */ + uint8_t vece; + /* Prefer i64 to v64. */ + bool prefer_i64; + /* Write aofs as a 2nd dest operand. */ + bool write_aofs; +} GVecGen4; + +typedef struct { + /* + * Expand inline as a 64-bit or 32-bit integer. Only one of these will= be + * non-NULL. + */ + void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64, int64_t); + void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32, int32_t); + /* Expand inline with a host vector type. */ + void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec, int64_t= ); + /* Expand out-of-line helper w/descriptor, data in descriptor. */ + gen_helper_gvec_4 *fno; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; + /* The vector element size, if applicable. */ + uint8_t vece; + /* Prefer i64 to v64. */ + bool prefer_i64; +} GVecGen4i; + +void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz, const GVecGen2 *); +void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, + uint32_t maxsz, int64_t c, const GVecGen2i *); +void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz, + uint32_t maxsz, TCGv_i64 c, const GVecGen2s *); +void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz, const GVecGen3 *); +void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz, int64_t c, + const GVecGen3i *); +void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t = cofs, + uint32_t oprsz, uint32_t maxsz, const GVecGen4 *); +void tcg_gen_gvec_4i(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t= cofs, + uint32_t oprsz, uint32_t maxsz, int64_t c, + const GVecGen4i *); + +/* Expand a specific vector operation. */ + +void tcg_gen_gvec_mov(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz); + +void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); + +void tcg_gen_gvec_addi(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t c, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t c, uint32_t oprsz, uint32_t maxsz); + +void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); + +/* Saturated arithmetic. */ +void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); + +/* Min/max. */ +void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); + +void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_nand(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_nor(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_eqv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); + +void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t c, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_xori(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t c, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t c, uint32_t oprsz, uint32_t maxsz); + +void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_andcs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); + +void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t s, uint32_t m); +void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t s, + uint32_t m, uint64_t imm); +void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s, + uint32_t m, TCGv_i32); +void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s, + uint32_t m, TCGv_i64); + +void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotri(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz); + +void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotrs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); + +/* + * Perform vector shift by vector element, modulo the element size. + * E.g. D[i] =3D A[i] << (B[i] % (8 << vece)). + */ +void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); + +void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, + uint32_t aofs, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); + +/* + * Perform vector bit select: d =3D (b & a) | (c & ~a). + */ +void tcg_gen_gvec_bitsel(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t cofs, + uint32_t oprsz, uint32_t maxsz); + +/* + * 64-bit vector operations. Use these when the register has been allocat= ed + * with tcg_global_mem_new_i64, and so we cannot also address it via point= er. + * OPRSZ =3D MAXSZ =3D 8. + */ + +void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 a); +void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 a); +void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 a); + +void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); +void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); +void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); + +void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); +void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); +void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); + +void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); +void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); +void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); +void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); +void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); +void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); +void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c); +void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c); + +/* 32-bit vector operations. */ +void tcg_gen_vec_add8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); +void tcg_gen_vec_add16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); + +void tcg_gen_vec_sub8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); +void tcg_gen_vec_sub16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); + +void tcg_gen_vec_shl8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); +void tcg_gen_vec_shl16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); +void tcg_gen_vec_shr8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); +void tcg_gen_vec_shr16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); +void tcg_gen_vec_sar8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); +void tcg_gen_vec_sar16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); + +#endif diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h index a8183bfeab..b0a81ad4bf 100644 --- a/include/tcg/tcg-op-gvec.h +++ b/include/tcg/tcg-op-gvec.h @@ -1,447 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * Generic vector operation expansion + * Target dependent generic vector operation expansion * * Copyright (c) 2018 Linaro - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . */ =20 #ifndef TCG_TCG_OP_GVEC_H #define TCG_TCG_OP_GVEC_H =20 -/* - * "Generic" vectors. All operands are given as offsets from ENV, - * and therefore cannot also be allocated via tcg_global_mem_new_*. - * OPRSZ is the byte size of the vector upon which the operation is perfor= med. - * MAXSZ is the byte size of the full vector; bytes beyond OPSZ are cleare= d. - * - * All sizes must be 8 or any multiple of 16. - * When OPRSZ is 8, the alignment may be 8, otherwise must be 16. - * Operands may completely, but not partially, overlap. - */ +#include "tcg/tcg-op-gvec-common.h" =20 -/* Expand a call to a gvec-style helper, with pointers to two vector - operands, and a descriptor (see tcg-gvec-desc.h). */ -typedef void gen_helper_gvec_2(TCGv_ptr, TCGv_ptr, TCGv_i32); -void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs, - uint32_t oprsz, uint32_t maxsz, int32_t data, - gen_helper_gvec_2 *fn); - -/* Similarly, passing an extra data value. */ -typedef void gen_helper_gvec_2i(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32); -void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c, - uint32_t oprsz, uint32_t maxsz, int32_t data, - gen_helper_gvec_2i *fn); - -/* Similarly, passing an extra pointer (e.g. env or float_status). */ -typedef void gen_helper_gvec_2_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); -void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs, - TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz, - int32_t data, gen_helper_gvec_2_ptr *fn); - -/* Similarly, with three vector operands. */ -typedef void gen_helper_gvec_3(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); -void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, - uint32_t oprsz, uint32_t maxsz, int32_t data, - gen_helper_gvec_3 *fn); - -/* Similarly, with four vector operands. */ -typedef void gen_helper_gvec_4(TCGv_ptr, TCGv_ptr, TCGv_ptr, - TCGv_ptr, TCGv_i32); -void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, - uint32_t cofs, uint32_t oprsz, uint32_t maxsz, - int32_t data, gen_helper_gvec_4 *fn); - -/* Similarly, with five vector operands. */ -typedef void gen_helper_gvec_5(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, - TCGv_ptr, TCGv_i32); -void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, - uint32_t cofs, uint32_t xofs, uint32_t oprsz, - uint32_t maxsz, int32_t data, gen_helper_gvec_5 *f= n); - -typedef void gen_helper_gvec_3_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, - TCGv_ptr, TCGv_i32); -void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, - TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz, - int32_t data, gen_helper_gvec_3_ptr *fn); - -typedef void gen_helper_gvec_4_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, - TCGv_ptr, TCGv_ptr, TCGv_i32); -void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, - uint32_t cofs, TCGv_ptr ptr, uint32_t oprsz, - uint32_t maxsz, int32_t data, - gen_helper_gvec_4_ptr *fn); - -typedef void gen_helper_gvec_5_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, - TCGv_ptr, TCGv_ptr, TCGv_i32); -void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, - uint32_t cofs, uint32_t eofs, TCGv_ptr ptr, - uint32_t oprsz, uint32_t maxsz, int32_t data, - gen_helper_gvec_5_ptr *fn); - -/* Expand a gvec operation. Either inline or out-of-line depending on - the actual vector size and the operations supported by the host. */ -typedef struct { - /* Expand inline as a 64-bit or 32-bit integer. - Only one of these will be non-NULL. */ - void (*fni8)(TCGv_i64, TCGv_i64); - void (*fni4)(TCGv_i32, TCGv_i32); - /* Expand inline with a host vector type. */ - void (*fniv)(unsigned, TCGv_vec, TCGv_vec); - /* Expand out-of-line helper w/descriptor. */ - gen_helper_gvec_2 *fno; - /* The optional opcodes, if any, utilized by .fniv. */ - const TCGOpcode *opt_opc; - /* The data argument to the out-of-line helper. */ - int32_t data; - /* The vector element size, if applicable. */ - uint8_t vece; - /* Prefer i64 to v64. */ - bool prefer_i64; - /* Load dest as a 2nd source operand. */ - bool load_dest; -} GVecGen2; - -typedef struct { - /* Expand inline as a 64-bit or 32-bit integer. - Only one of these will be non-NULL. */ - void (*fni8)(TCGv_i64, TCGv_i64, int64_t); - void (*fni4)(TCGv_i32, TCGv_i32, int32_t); - /* Expand inline with a host vector type. */ - void (*fniv)(unsigned, TCGv_vec, TCGv_vec, int64_t); - /* Expand out-of-line helper w/descriptor, data in descriptor. */ - gen_helper_gvec_2 *fno; - /* Expand out-of-line helper w/descriptor, data as argument. */ - gen_helper_gvec_2i *fnoi; - /* The optional opcodes, if any, utilized by .fniv. */ - const TCGOpcode *opt_opc; - /* The vector element size, if applicable. */ - uint8_t vece; - /* Prefer i64 to v64. */ - bool prefer_i64; - /* Load dest as a 3rd source operand. */ - bool load_dest; -} GVecGen2i; - -typedef struct { - /* Expand inline as a 64-bit or 32-bit integer. - Only one of these will be non-NULL. */ - void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64); - void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32); - /* Expand inline with a host vector type. */ - void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec); - /* Expand out-of-line helper w/descriptor. */ - gen_helper_gvec_2i *fno; - /* The optional opcodes, if any, utilized by .fniv. */ - const TCGOpcode *opt_opc; - /* The data argument to the out-of-line helper. */ - uint32_t data; - /* The vector element size, if applicable. */ - uint8_t vece; - /* Prefer i64 to v64. */ - bool prefer_i64; - /* Load scalar as 1st source operand. */ - bool scalar_first; -} GVecGen2s; - -typedef struct { - /* Expand inline as a 64-bit or 32-bit integer. - Only one of these will be non-NULL. */ - void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64); - void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32); - /* Expand inline with a host vector type. */ - void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec); - /* Expand out-of-line helper w/descriptor. */ - gen_helper_gvec_3 *fno; - /* The optional opcodes, if any, utilized by .fniv. */ - const TCGOpcode *opt_opc; - /* The data argument to the out-of-line helper. */ - int32_t data; - /* The vector element size, if applicable. */ - uint8_t vece; - /* Prefer i64 to v64. */ - bool prefer_i64; - /* Load dest as a 3rd source operand. */ - bool load_dest; -} GVecGen3; - -typedef struct { - /* - * Expand inline as a 64-bit or 32-bit integer. Only one of these will= be - * non-NULL. - */ - void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, int64_t); - void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, int32_t); - /* Expand inline with a host vector type. */ - void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, int64_t); - /* Expand out-of-line helper w/descriptor, data in descriptor. */ - gen_helper_gvec_3 *fno; - /* The optional opcodes, if any, utilized by .fniv. */ - const TCGOpcode *opt_opc; - /* The vector element size, if applicable. */ - uint8_t vece; - /* Prefer i64 to v64. */ - bool prefer_i64; - /* Load dest as a 3rd source operand. */ - bool load_dest; -} GVecGen3i; - -typedef struct { - /* Expand inline as a 64-bit or 32-bit integer. - Only one of these will be non-NULL. */ - void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64); - void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32); - /* Expand inline with a host vector type. */ - void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec); - /* Expand out-of-line helper w/descriptor. */ - gen_helper_gvec_4 *fno; - /* The optional opcodes, if any, utilized by .fniv. */ - const TCGOpcode *opt_opc; - /* The data argument to the out-of-line helper. */ - int32_t data; - /* The vector element size, if applicable. */ - uint8_t vece; - /* Prefer i64 to v64. */ - bool prefer_i64; - /* Write aofs as a 2nd dest operand. */ - bool write_aofs; -} GVecGen4; - -typedef struct { - /* - * Expand inline as a 64-bit or 32-bit integer. Only one of these will= be - * non-NULL. - */ - void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64, int64_t); - void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32, int32_t); - /* Expand inline with a host vector type. */ - void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec, int64_t= ); - /* Expand out-of-line helper w/descriptor, data in descriptor. */ - gen_helper_gvec_4 *fno; - /* The optional opcodes, if any, utilized by .fniv. */ - const TCGOpcode *opt_opc; - /* The vector element size, if applicable. */ - uint8_t vece; - /* Prefer i64 to v64. */ - bool prefer_i64; -} GVecGen4i; - -void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, - uint32_t oprsz, uint32_t maxsz, const GVecGen2 *); -void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, - uint32_t maxsz, int64_t c, const GVecGen2i *); -void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz, - uint32_t maxsz, TCGv_i64 c, const GVecGen2s *); -void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs, - uint32_t oprsz, uint32_t maxsz, const GVecGen3 *); -void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs, - uint32_t oprsz, uint32_t maxsz, int64_t c, - const GVecGen3i *); -void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t = cofs, - uint32_t oprsz, uint32_t maxsz, const GVecGen4 *); -void tcg_gen_gvec_4i(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t= cofs, - uint32_t oprsz, uint32_t maxsz, int64_t c, - const GVecGen4i *); - -/* Expand a specific vector operation. */ - -void tcg_gen_gvec_mov(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t oprsz, uint32_t maxsz); - -void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); - -void tcg_gen_gvec_addi(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t c, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t c, uint32_t oprsz, uint32_t maxsz); - -void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); - -/* Saturated arithmetic. */ -void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); - -/* Min/max. */ -void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); - -void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_nand(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_nor(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_eqv(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); - -void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t c, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_xori(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t c, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t c, uint32_t oprsz, uint32_t maxsz); - -void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_andcs(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); - -void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t s, uint32_t m); -void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t s, - uint32_t m, uint64_t imm); -void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s, - uint32_t m, TCGv_i32); -void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s, - uint32_t m, TCGv_i64); - -#if TARGET_LONG_BITS =3D=3D 64 -# define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i64 -#else -# define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i32 +#ifndef TARGET_LONG_BITS +#error must include QEMU headers #endif =20 -void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t shift, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t shift, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t shift, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t shift, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_rotri(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t shift, uint32_t oprsz, uint32_t maxsz); - -void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_rotrs(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); - -/* - * Perform vector shift by vector element, modulo the element size. - * E.g. D[i] =3D A[i] << (B[i] % (8 << vece)). - */ -void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); - -void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, - uint32_t aofs, uint32_t bofs, - uint32_t oprsz, uint32_t maxsz); - -/* - * Perform vector bit select: d =3D (b & a) | (c & ~a). - */ -void tcg_gen_gvec_bitsel(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t cofs, - uint32_t oprsz, uint32_t maxsz); - -/* - * 64-bit vector operations. Use these when the register has been allocat= ed - * with tcg_global_mem_new_i64, and so we cannot also address it via point= er. - * OPRSZ =3D MAXSZ =3D 8. - */ - -void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 a); -void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 a); -void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 a); - -void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); -void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); -void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); - -void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); -void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); -void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); - -void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); -void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); -void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); -void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); -void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); -void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); -void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c); -void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c); - -/* 32-bit vector operations. */ -void tcg_gen_vec_add8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); -void tcg_gen_vec_add16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); - -void tcg_gen_vec_sub8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); -void tcg_gen_vec_sub16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); - -void tcg_gen_vec_shl8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); -void tcg_gen_vec_shl16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); -void tcg_gen_vec_shr8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); -void tcg_gen_vec_shr16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); -void tcg_gen_vec_sar8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); -void tcg_gen_vec_sar16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); - #if TARGET_LONG_BITS =3D=3D 64 +#define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i64 #define tcg_gen_vec_add8_tl tcg_gen_vec_add8_i64 #define tcg_gen_vec_sub8_tl tcg_gen_vec_sub8_i64 #define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i64 @@ -454,8 +28,8 @@ void tcg_gen_vec_sar16i_i32(TCGv_i32 d, TCGv_i32 a, int3= 2_t); #define tcg_gen_vec_shl16i_tl tcg_gen_vec_shl16i_i64 #define tcg_gen_vec_shr16i_tl tcg_gen_vec_shr16i_i64 #define tcg_gen_vec_sar16i_tl tcg_gen_vec_sar16i_i64 - -#else +#elif TARGET_LONG_BITS =3D=3D 32 +#define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i32 #define tcg_gen_vec_add8_tl tcg_gen_vec_add8_i32 #define tcg_gen_vec_sub8_tl tcg_gen_vec_sub8_i32 #define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i32 @@ -468,6 +42,8 @@ void tcg_gen_vec_sar16i_i32(TCGv_i32 d, TCGv_i32 a, int3= 2_t); #define tcg_gen_vec_shl16i_tl tcg_gen_vec_shl16i_i32 #define tcg_gen_vec_shr16i_tl tcg_gen_vec_shr16i_i32 #define tcg_gen_vec_sar16i_tl tcg_gen_vec_sar16i_i32 +#else +# error #endif =20 #endif diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 7a9599e49e..95a588d6d2 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -21,7 +21,7 @@ #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" #include "tcg/tcg-op-common.h" -#include "tcg/tcg-op-gvec.h" +#include "tcg/tcg-op-gvec-common.h" #include "tcg/tcg-gvec-desc.h" =20 #define MAX_UNROLL 4 --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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The last time a use of this define was added to the source tree, as opposed to merely moved around, was 2008. There have been many cleanups since that time and this is no longer required for the build to succeed. Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 2 -- target/sparc/cpu.h | 2 -- accel/tcg/translate-all.c | 1 - tcg/tcg.c | 6 ------ 4 files changed, 11 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 0f9f2e1a0c..10c4ffa148 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1394,7 +1394,6 @@ void ppc_store_msr(CPUPPCState *env, target_ulong val= ue); void ppc_cpu_list(void); =20 /* Time-base and decrementer management */ -#ifndef NO_CPU_IO_DEFS uint64_t cpu_ppc_load_tbl(CPUPPCState *env); uint32_t cpu_ppc_load_tbu(CPUPPCState *env); void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value); @@ -1435,7 +1434,6 @@ int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *= tlb, hwaddr booke206_tlb_to_page_size(CPUPPCState *env, ppcmas_tlb_t *tlb); #endif -#endif =20 void ppc_store_fpscr(CPUPPCState *env, target_ulong val); void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit, diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index fb98843dad..3d090e8278 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -581,7 +581,6 @@ G_NORETURN void sparc_cpu_do_unaligned_access(CPUState = *cpu, vaddr addr, uintptr_t retaddr); G_NORETURN void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t); =20 -#ifndef NO_CPU_IO_DEFS /* cpu_init.c */ void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); void sparc_cpu_list(void); @@ -637,7 +636,6 @@ static inline int tlb_compare_context(const SparcTLBEnt= ry *tlb, return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK); } =20 -#endif #endif =20 /* cpu-exec.c */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 181f276b18..347768b979 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -19,7 +19,6 @@ =20 #include "qemu/osdep.h" =20 -#define NO_CPU_IO_DEFS #include "trace.h" #include "disas/disas.h" #include "exec/exec-all.h" diff --git a/tcg/tcg.c b/tcg/tcg.c index 3888a22ba1..a976e851d5 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -37,12 +37,6 @@ #include "qemu/cacheflush.h" #include "qemu/cacheinfo.h" #include "qemu/timer.h" - -/* Note: the long term plan is to reduce the dependencies on the QEMU - CPU definitions. Currently they are used for qemu_ld/st - instructions */ -#define NO_CPU_IO_DEFS - #include "exec/exec-all.h" #include "exec/tlb-common.h" #include "tcg/tcg-op-common.h" --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684853476; cv=none; d=zohomail.com; s=zohoarc; b=hh7QQQWXa6I6pBgeZPJ6mUf0G2FXvFyywl/l8mJX0K/YhzVW4PEZfa1BaX/R/B9xgFr/nbJvwvl6Ioho0u9GivoL4Sk2dj9Lu0LqxyOBxLQFXLcBvf8aDanrX6bqMq7PwGaoZlHjzqSOl1eBmd6fYkfNPlbkvK81jLh/azGDJ5o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684853476; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wDxG1Fumi/VCBapDyQzvtsqcUgkmKE+Qvv/KLvwRg5E=; b=U82gQlyVamU66R8VsY+aFpLsc6WbGD+kU41QLAGqonuNdNwKV3L82MhSDhcQlWM/yF1zmv8QlEOVwFzXl5OAy9hPDqKcRoAreL9W6XgJ8PAQvQgAdyVa1I7QFQkU8d3UD/rvrzQDh+Zmaiepl9MCjwjhBsEgPVkkM+QE9HT2SCM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684853476045949.4131689192662; Tue, 23 May 2023 07:51:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1STM-0007Ad-SP; Tue, 23 May 2023 09:54:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSV-00056F-VI for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:52 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSU-00034Z-9L for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:51 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-64d3fbb8c1cso4743854b3a.3 for ; Tue, 23 May 2023 06:53:49 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850029; x=1687442029; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wDxG1Fumi/VCBapDyQzvtsqcUgkmKE+Qvv/KLvwRg5E=; b=qylaO6wjLa6jrS/JoLX/9+IqF+DFMk/RzcFJyd6qnv/x3RqqBbhEhK5UeO33/vOR4t rl8zyo7bKL6nm4nSNC9Pva1M+GVpr5Khk9IswI+ZouP3rMAfQ3ULhKLgbNkNpeHzQ/Gt GoQlfTpxPpxfHdizQ5IHPWb699rbXrRGXRSVbSGUICLx38BFhrU3iqOgXc8jeCVDO4LA 7f3ZGL3jGW3dR22joqJnGlVbElex+gdEJ9Kp7CzDQdbeh67zv1scO2oJTcZGxPa97iQH SCF1BK37Qse30+5FdgaMWqXKezNDdAKOqEh68q0hdmNQQnV5tLQB/jwB2zNoQi3kW3qM vMmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850029; x=1687442029; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wDxG1Fumi/VCBapDyQzvtsqcUgkmKE+Qvv/KLvwRg5E=; b=TyN4txqapCrJjZKOmeWHoh+O82Sg5UWrJnJ8EtVQ8mjKNQnpTbwYoY19Zjb9x221fx Ks2U+OucYVMo5QB9NOtK9BFkvu6dUjuTVZ46hL1MTwdXcJSmJoGfjkjWxNdDw7J2RHRj sAKnw20K8Xg66aPGrMNGJoqP6pud2Ha4JtDVOf1IxMmCFb838mG+8a+6NhUTPxrkYqUl wGyfOaXbK5QtKmXRrEf45/bgIUCKe8hd02YRCGcKzwAlt5Jx5hCp24i4gv1peaUVr4PU 9AJoOfjLoR6Qqeajt9CVqOzrUWBPuubvQIDa92c1SF9wMogaWOwI7Uwyh7/asIY2a0Rr nQJQ== X-Gm-Message-State: AC+VfDzijzaxeZKb1vLPQFBizuBkTF7XgjWpqNCWAS8MyReTHzEulg5B wGXMzyVu8DXD65TllA9C2d+FCtdkCtj9SsLCLiE= X-Google-Smtp-Source: ACHHUZ6f0QBm6LjuwBSx7wCdRZNkN2rWWxXFuwZcUnMQtNoEiHe2lQpXabwSPAnGTGOeWNXpIVnblA== X-Received: by 2002:a05:6a00:1a46:b0:62a:d752:acc5 with SMTP id h6-20020a056a001a4600b0062ad752acc5mr21424417pfv.32.1684850029449; Tue, 23 May 2023 06:53:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 31/52] exec-all: Widen tb_page_addr_t for user-only Date: Tue, 23 May 2023 06:53:01 -0700 Message-Id: <20230523135322.678948-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684853477823100001 Content-Type: text/plain; charset="utf-8" This is a step toward making TranslationBlock agnostic to the address size of the guest. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index ecded1f112..8c8526d9f8 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -34,8 +34,8 @@ addresses in userspace mode. Define tb_page_addr_t to be an appropriate type. */ #if defined(CONFIG_USER_ONLY) -typedef abi_ulong tb_page_addr_t; -#define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx +typedef vaddr tb_page_addr_t; +#define TB_PAGE_ADDR_FMT "%" VADDR_PRIx #else typedef ram_addr_t tb_page_addr_t; #define TB_PAGE_ADDR_FMT RAM_ADDR_FMT --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851391; cv=none; d=zohomail.com; s=zohoarc; b=byFZhDYfZJpN3kDtiXMHa9SQhkr4/SqAuZaCyHhiTAqcXcZFOTzZ3rbT29EsuRJklg7RKiUGcdSKsoRD/zt0+m4oMBBibjFn1ulmLpPDUZlGy7iWMqzMXOWH4HnA3ARRNg4aoZ4iFqS/JEIJ2Cy1flfpQNyjHdlqXexHzons9Ig= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851391; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Eu9NQtb2FUQWFu9rVl+RtTj4i7Vm9wmVlC22z1EyvKw=; b=b8pn47PM26en8kq7O8eTjRnif0M7Qb9soUZAOwQzrXSsHwQhg29DMF4FgrFUDr/wViNH9NL8EQFWtpPc2CqqsNsc5flEyusBHU3fpiSeAWPyB1SLBYP46iyeKgmH2pV5xvofCaANCzkciMfl+pGQND2MHZaab8gYfl+Rb9OI2gk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684851391439403.2884145298642; Tue, 23 May 2023 07:16:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1STY-0008ST-B2; Tue, 23 May 2023 09:54:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSX-00057f-03 for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:54 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSV-00038b-DD for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:52 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-64d3e5e5980so4971099b3a.2 for ; Tue, 23 May 2023 06:53:51 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850030; x=1687442030; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Eu9NQtb2FUQWFu9rVl+RtTj4i7Vm9wmVlC22z1EyvKw=; b=E/wbr1Urw+1b0wYhdpsyx/a7B28ufV68QreggBfw9CTKCvrSGbaTy9GadpwxTiziAT tuwFgFh7Bi+BGQyiJp97KBmZ8hjglsbedBljdmH+NLmEvF0Rdz+a9Ld6oJNjHVgW62uL BibcwdonmPwiJnFztqvPeomjJym1LbFEcy74BXyFVHUuhva2QdW1KaDNV9Do0Y+zx80m ROMywTwWYEPtwxX1iqaTne6z8ILx0Gx/2zZmRUf/Dhk4yzSa8Z0yw3WYg9kY40G1HvzJ vVTyJxWcJlHLvJGk9xkPlsSIjRN5rvYfgesibMBDB9vZKYbpn8XeoX+eL4nA+vNkHLzh Abrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850030; x=1687442030; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Eu9NQtb2FUQWFu9rVl+RtTj4i7Vm9wmVlC22z1EyvKw=; b=c0naECXXRQVZeNRP1PmiskGW4hdWPixO+YKkSitZFzsfjWVst3roVuLExxqQaS7xIa UT87mtc6zZM3bf2aWNvrjS2axBVMONWmQyHND6JoGQJhn1t2hT/XF4i7Ir143OgImhLT cQYTctTJoErAQX6YcwX5ajamd+Zj2uBqfGe4jXkb/Jw2S6m9E5578vqMvMpxEZ0WLI1N uI670kUbMQkmnyBs/XroIO1AlUVhDsISUYIm+8JYpCzKE0qdrVoFatUahYhuw3Tx0/je 3H7jZyBI0Ole/pjSGqyMqiqS12+BjVrhLXdgGNRxAbBOvrSr90LXUl19MASvUvo+vk96 UEfA== X-Gm-Message-State: AC+VfDy4fAEqYdc19vYDgq0PrdKPc1V32NzkdRPaJPfbBUWOBAwjVAgA h8Kzfh3ORqDOSljzChp5GZ0DauTfiujANA+OKSM= X-Google-Smtp-Source: ACHHUZ4e7SizPq5LUd34k/B8B6T8qQ7M+zvXFA/kg2LpiN63Nf0Uu+c5/+5d4W8sDodHgeNL9F5PYA== X-Received: by 2002:a05:6a00:2d04:b0:64f:4812:8c7e with SMTP id fa4-20020a056a002d0400b0064f48128c7emr1527332pfb.19.1684850030153; Tue, 23 May 2023 06:53:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 32/52] exec-all: Widen TranslationBlock pc and cs_base to 64-bits Date: Tue, 23 May 2023 06:53:02 -0700 Message-Id: <20230523135322.678948-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851391872100001 Content-Type: text/plain; charset="utf-8" This makes TranslationBlock agnostic to the address size of the guest. Use vaddr for pc, since that's always a virtual address. Use uint64_t for cs_base, since usage varies between guests. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/exec-all.h | 4 ++-- accel/tcg/cpu-exec.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 8c8526d9f8..58ac1a91c2 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -519,7 +519,7 @@ struct TranslationBlock { * Unwind information is taken as offsets from the page, to be * deposited into the "current" PC. */ - target_ulong pc; + vaddr pc; =20 /* * Target-specific data associated with the TranslationBlock, e.g.: @@ -528,7 +528,7 @@ struct TranslationBlock { * s390x: instruction data for EXECUTE, * sparc: the next pc of the instruction queue (for delay slots). */ - target_ulong cs_base; + uint64_t cs_base; =20 uint32_t flags; /* flags defining in which context the code was genera= ted */ uint32_t cflags; /* compile flags */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index bc0e1c3299..9fe07c31fb 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -302,7 +302,7 @@ static void log_cpu_exec(target_ulong pc, CPUState *cpu, { if (qemu_log_in_addr_range(pc)) { qemu_log_mask(CPU_LOG_EXEC, - "Trace %d: %p [" TARGET_FMT_lx + "Trace %d: %p [%08" PRIx64 "/" TARGET_FMT_lx "/%08x/%08x] %s\n", cpu->cpu_index, tb->tc.ptr, tb->cs_base, pc, tb->flags, tb->cflags, lookup_symbol(pc)); --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851233; cv=none; d=zohomail.com; s=zohoarc; b=FNQla/B4VZbaP5cRItMF5/gzDegggtlmRAeWXzLhASpom2FUV8GcEnVLjHseaGPaukUGzG3CUIQgiwkR0t5XzfsTRHgJowc/d3GycnSNkvnRyjmVYSsGqxOL8w6bt5eUfpaGg2uRwNdWGwrg50n4CnACNYZ+L+HdelTeKXdAT84= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851233; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9LPVzQHA3yh4eIvBgA5mt6K1nxPIQ/WmRZegTc9VdCE=; b=cWoA2ahCk9sx9dsicSbT0dv4RQhB6Tf1wO98zF1fBYQ6XAV/z1TKoM6U++F8xznQRjPxqgWQ0ake4apFanbEvrmDMnDIPHuA08MnizUvclu1mtqopNrFVA5jLBaKyPHu2elvxxMJFUl9VC0bhpwNxZ6itqDh5/VDKZk6xt0xMoA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684851233022586.4892024185738; Tue, 23 May 2023 07:13:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SUL-0000bJ-Ew; Tue, 23 May 2023 09:55:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSX-00059H-RX for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:54 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSV-00032E-Rj for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:53 -0400 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-64d426e63baso4408125b3a.0 for ; Tue, 23 May 2023 06:53:51 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850031; x=1687442031; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=9LPVzQHA3yh4eIvBgA5mt6K1nxPIQ/WmRZegTc9VdCE=; b=xg1tsK02u9UXgGbGJIDI+/vLyuohWIMjYueZP8mInFEwNKKACDBYEviLcrALcAxXXB 3R5sJt7BSm375LsnnWaQ4fgE1EqYX8x95lsfhszVl+LsQUoQNCsbu/AZtFeZYYLNHpuB s6x2/VQNGpkdsiR0V6BeRRzVWjddkg8MiMYpIYocpx35xuPR1IRhj9rvG4A6oKf2h6Bv NcubDKbtWm/WdkAUeId7TcLsH9MFM2l0ejF/zrzNznkuLBag2UYQdp61EdYDH5MgWlW6 p4ZkgKmlstuHYvsTVCQ0/ELpMWtbJBSU3wQaz7fP1RNVJReg9kegFBwJEimFM5w/xzvG Tl5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850031; x=1687442031; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9LPVzQHA3yh4eIvBgA5mt6K1nxPIQ/WmRZegTc9VdCE=; b=WzsSDsIK1So10zCg38EXfip5WSko3x3xhQMyJS/y2DU0X/xSfM/oqSJZZx7QSQsGVW ZOs7KsJwn3PB3YCi5muX9Ro1f6QFJah5C318Erzzc1hA13q4uPVVqymZKkFzWozRAVpb jyxfYxU08gix9WkoS7Sf4pnzTbyohQTKLrR2QKtkEc+IqEVIIEtzKobkIuoWUcj/HUDJ pBgy3lK1bRHA1ZBOnP3cd+AC8YzhWZ9QnWIBP2ogk4QWLlLHIZUoJ3MtGzxQHWcPLiZY j7gPCt721FS1SU3tszSXITRrpg6kdQo6RSezmtUOz+QD4B1wh1p9G9nbvS4bvjAq75IO qEpQ== X-Gm-Message-State: AC+VfDw6VPOG7ZI2UoZIsaLNqKtz6NlgmXMnQLO3C9t4FV7ZafO3Kupt +AS/QU0QtLEZ+nKCG1Y7QezFQKQh0QwYvJO+zGE= X-Google-Smtp-Source: ACHHUZ79vbrHKAI6PiUEaMNcvDJoznlkNqiFYBqrW0yYm5BXyuGONF8dwTUEBjn05zpRLoSKuSIVYQ== X-Received: by 2002:a05:6a20:428a:b0:10b:cdb1:3563 with SMTP id o10-20020a056a20428a00b0010bcdb13563mr7046193pzj.46.1684850031004; Tue, 23 May 2023 06:53:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 33/52] tcg: Remove DEBUG_DISAS Date: Tue, 23 May 2023 06:53:03 -0700 Message-Id: <20230523135322.678948-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851234683100001 Content-Type: text/plain; charset="utf-8" This had been set since the beginning, is never undefined, and it would seem to be harmful to debugging to do so. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/exec-all.h | 3 --- accel/tcg/cpu-exec.c | 2 -- accel/tcg/translate-all.c | 2 -- accel/tcg/translator.c | 2 -- target/sh4/translate.c | 2 -- target/sparc/translate.c | 2 -- tcg/tcg.c | 9 +-------- 7 files changed, 1 insertion(+), 21 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 58ac1a91c2..a09d754624 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -27,9 +27,6 @@ #include "qemu/interval-tree.h" #include "qemu/clang-tsa.h" =20 -/* allow to see translation results - the slowdown should be negligible, s= o we leave it */ -#define DEBUG_DISAS - /* Page tracking code uses ram addresses in system mode, and virtual addresses in userspace mode. Define tb_page_addr_t to be an appropriate type. */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 9fe07c31fb..f1eae7b8e5 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -307,7 +307,6 @@ static void log_cpu_exec(target_ulong pc, CPUState *cpu, cpu->cpu_index, tb->tc.ptr, tb->cs_base, pc, tb->flags, tb->cflags, lookup_symbol(pc)); =20 -#if defined(DEBUG_DISAS) if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { @@ -323,7 +322,6 @@ static void log_cpu_exec(target_ulong pc, CPUState *cpu, qemu_log_unlock(logfile); } } -#endif /* DEBUG_DISAS */ } } =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 347768b979..dd19b3ca78 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -441,7 +441,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu, qatomic_set(&prof->search_out_len, prof->search_out_len + search_size); #endif =20 -#ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) && qemu_log_in_addr_range(pc)) { FILE *logfile =3D qemu_log_trylock(); @@ -514,7 +513,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu, qemu_log_unlock(logfile); } } -#endif =20 qatomic_set(&tcg_ctx->code_gen_ptr, (void *) ROUND_UP((uintptr_t)gen_code_buf + gen_code_size + search_size, diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 7bda43ff61..6120ef2a92 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -122,7 +122,6 @@ void translator_loop(CPUState *cpu, TranslationBlock *t= b, int *max_insns, tb->size =3D db->pc_next - db->pc_first; tb->icount =3D db->num_insns; =20 -#ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && qemu_log_in_addr_range(db->pc_first)) { FILE *logfile =3D qemu_log_trylock(); @@ -133,7 +132,6 @@ void translator_loop(CPUState *cpu, TranslationBlock *t= b, int *max_insns, qemu_log_unlock(logfile); } } -#endif } =20 static void *translator_access(CPUArchState *env, DisasContextBase *db, diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 350f88a99f..9d2c7a3337 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -17,8 +17,6 @@ * License along with this library; if not, see . */ =20 -#define DEBUG_DISAS - #include "qemu/osdep.h" #include "cpu.h" #include "disas/disas.h" diff --git a/target/sparc/translate.c b/target/sparc/translate.c index a3fed5e01b..ebaf376500 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -37,8 +37,6 @@ #include "exec/helper-info.c.inc" #undef HELPER_H =20 -#define DEBUG_DISAS - #define DYNAMIC_PC 1 /* dynamic pc value */ #define JUMP_PC 2 /* dynamic pc value which takes only two values according to jump_pc[T2] */ diff --git a/tcg/tcg.c b/tcg/tcg.c index a976e851d5..f7e61e736f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1420,7 +1420,6 @@ void tcg_prologue_init(TCGContext *s) (uintptr_t)s->code_buf, prologue_size); #endif =20 -#ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) { FILE *logfile =3D qemu_log_trylock(); if (logfile) { @@ -1452,7 +1451,6 @@ void tcg_prologue_init(TCGContext *s) qemu_log_unlock(logfile); } } -#endif =20 #ifndef CONFIG_TCG_INTERPRETER /* @@ -6048,7 +6046,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= uint64_t pc_start) } #endif =20 -#ifdef DEBUG_DISAS if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP) && qemu_log_in_addr_range(pc_start))) { FILE *logfile =3D qemu_log_trylock(); @@ -6059,7 +6056,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= uint64_t pc_start) qemu_log_unlock(logfile); } } -#endif =20 #ifdef CONFIG_DEBUG_TCG /* Ensure all labels referenced have been emitted. */ @@ -6096,7 +6092,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= uint64_t pc_start) liveness_pass_1(s); =20 if (s->nb_indirects > 0) { -#ifdef DEBUG_DISAS if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND) && qemu_log_in_addr_range(pc_start))) { FILE *logfile =3D qemu_log_trylock(); @@ -6107,7 +6102,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= uint64_t pc_start) qemu_log_unlock(logfile); } } -#endif + /* Replace indirect temps with direct temps. */ if (liveness_pass_2(s)) { /* If changes were made, re-run liveness. */ @@ -6119,7 +6114,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= uint64_t pc_start) qatomic_set(&prof->la_time, prof->la_time + profile_getclock()); #endif =20 -#ifdef DEBUG_DISAS if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT) && qemu_log_in_addr_range(pc_start))) { FILE *logfile =3D qemu_log_trylock(); @@ -6130,7 +6124,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= uint64_t pc_start) qemu_log_unlock(logfile); } } -#endif =20 /* Initialize goto_tb jump offsets. */ tb->jmp_reset_offset[0] =3D TB_JMP_OFFSET_INVALID; --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684852667; cv=none; d=zohomail.com; s=zohoarc; b=G8cPOGN4oE3ubU5VY/cnjMKy55uF4G7y0kMDJByJZLzxPrfsPbhDee4Us1LApjFYuzPGDQ/uJB8w9/tUSCxDXPklzZqb5EbiCrQY5cxEIxt6gSFuyYjvCAb5c3RhsJNa5SipZWjctoJumV0iYDDn3Y24xwuB3skkq6NZ8y2AJRo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684852667; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850032; x=1687442032; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=CqRHuePTegdze3NOBrjUysvcJxQSbD+uxpXc5nyVFn4=; b=fZzBcExymZpkAFcuLHX96MpONM1SL7FJD6VqVc++2TFKlpfVGsimotrkifNLq+4WkW hP1FoZT+8MObBHQmm9HhwERAmL9OR1b3KMv1DBse3MOhHSM5SzYv/iRFXL2o5yzZZX88 qLxSY3xzJ5gzqiYwxxQEJQHyPLXJRAM52oUCVH7Ka+9aAV9CdTVLsa7RNN9Wax4DtyZl VpJREIPIu1rXhZMy5El5Mmxt6s/mOuUkfYb7CwbHRosDhX6xIHFbszHSRqsDvgvoa8Cb E+AF3KY96Mr1f5JUUwBQunQkwGeHJj+fsTcUboR8W/lUMy3JbElF7TQvqcemmAVfXghy IaWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850032; x=1687442032; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CqRHuePTegdze3NOBrjUysvcJxQSbD+uxpXc5nyVFn4=; b=LNzbw159Q0dhGz+YnnVxTg+1GKQilmtOYzg0mh143JhmT0KIJ1Y7JOUwBlKdJLG2YL T9y5gJWO9wpcgxfsKqaBkA029YqzDYeQ1gjEOY9+orTnOcOLceCUjKwh5y9uY6LBHdDD ajU1mgpeSeGXbRNZBZunyaNloy6vN+z0YdAUSTxK1DjOfqF/3kY3Y+6zGkC+lbdTZWcX 7z+YiXXBoo1IPF3hb7vQbGJfY+OJPjqnf5v1jxlLIEBK8vb572kqPzPAL/8v40t8tue4 RlfJg8UNrN/5vHco4Yv2YTDFjvrgGEtCmhzp1U8Y6KDqBnLHw2K+z6e+VmoMkgv7hz7K vMYg== X-Gm-Message-State: AC+VfDyLcjOvvWQp4jv9M92Tc+GX6WS2j4fs0YEzmBCgA9pYOem9wVqJ TJ52xb0M8La+FGJrFseU6mDGjYPM4nEaY0/TNGI= X-Google-Smtp-Source: ACHHUZ4w4C32/1KZ/goYLbCIy7rkWbhaKGIs4370w6CCiGNUYqmdWjazbJ0wNZbVbRXo/+fxcpaUjg== X-Received: by 2002:a05:6a00:1a15:b0:63b:5c82:e21a with SMTP id g21-20020a056a001a1500b0063b5c82e21amr18012407pfv.1.1684850031790; Tue, 23 May 2023 06:53:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 34/52] tcg: Remove USE_TCG_OPTIMIZATIONS Date: Tue, 23 May 2023 06:53:04 -0700 Message-Id: <20230523135322.678948-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684852668485100001 Content-Type: text/plain; charset="utf-8" This is always defined, and the optimization pass is essential to producing reasonable code. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index f7e61e736f..7d0449f6a9 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -22,9 +22,6 @@ * THE SOFTWARE. */ =20 -/* define it to use liveness analysis (better code) */ -#define USE_TCG_OPTIMIZATIONS - #include "qemu/osdep.h" =20 /* Define to jump the ELF file used to communicate with GDB. */ @@ -6078,9 +6075,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb,= uint64_t pc_start) qatomic_set(&prof->opt_time, prof->opt_time - profile_getclock()); #endif =20 -#ifdef USE_TCG_OPTIMIZATIONS tcg_optimize(s); -#endif =20 #ifdef CONFIG_PROFILER qatomic_set(&prof->opt_time, prof->opt_time + profile_getclock()); --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851156; cv=none; d=zohomail.com; s=zohoarc; b=YMJqt9MMti18heRAT0DJL3OXox/X1A1bp5shVSV0BJgD9Vcc7x+BlirCTcDzcY1tj+FJibSWgDo/BcC7tCEDSTupLw73i8z50/c07ihWQGWxp+8YBV0IhVibjBvo0Eu6l4Jh+0OJribuh3ICTNNEaj2zTVdEniGwB4zuiPIYbt8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851156; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7vjuJuA4F+nXJBVYCTj3t799oWhCX0Jwt5+qkl4jK+w=; b=nrJ0rp9D/kTFeaFKGkmvfkYDudnv/ABnn+pW6vbn6YvyChOu+SueHCB1K5U6jNi+r32+c7Co08MVDGrHoiuJYGpF/KxtHJa00F8GbiMXYkn1IJmrizgL/daWgoUvHMrnWWbAnQFCBmegcFTXMbFxS+vr5n2NIPTOTNxiBEGjy+g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684851156100938.0717400968889; Tue, 23 May 2023 07:12:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1ST0-0006CD-AM; Tue, 23 May 2023 09:54:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSZ-0005A9-R8 for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:56 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSX-00032V-HI for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:55 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-64d2981e3abso4341676b3a.1 for ; Tue, 23 May 2023 06:53:53 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850033; x=1687442033; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7vjuJuA4F+nXJBVYCTj3t799oWhCX0Jwt5+qkl4jK+w=; b=lPsg+L0LFZnIvB+1DbIpDkMEqCTpOp821g7/ND5jt9imb6ZJZ0jJo/O8Vde7O8tKj+ m4V0ksjRadiqQFLK7RElWGVTeg/Sxim1G8bORcW4OCj+EzB2xq18hfBOs+tPtXVICYWy miZe3ZReLQV3WizN9yAX+s10bawlo2HgYNUIGCQVbuYUi3mNpLEHl4/lUvQKvBAr3T9f XugOn6gtWPlwRinMZds7H+MHeYS1Tk2YeymlJSY38JM2gV00gx73hhweYllhYFco4aMd 9baW+x5GoeuNpf04iyiKXRWMD1Rw8SKQQ5k9Da0UE1qd5hjEv1346mKcnzfkDPfMOxdm RZyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850033; x=1687442033; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7vjuJuA4F+nXJBVYCTj3t799oWhCX0Jwt5+qkl4jK+w=; b=XaPUUGQsfTTQtoBGuh0bmxxY72reBwBhF/3wqzSBCyq4IR5YDAiBMHenKwhLa4QaRj jsBRyplVSnoAh6zU+FAMLpkEOfl/AO+bweWJasWrkKwi0T+mRy8thP2q2c36H3wqa/6R g9/RlUZYuE5mrvCIFsCLf0CjTfuf0CNcTB4bM5tXgWAGuXbFLsPqvM2PCvZw5weB5LPB jGLIu7Wiv5Xxtc82HWyXx25nZ1OqGwNhZAq+RbluIL7V1x7lQ4A+BjIdWhe0/HJkayPG 4hJ67BvS1Ptk05xzd4m5frw/WSYpag+gldo+62bWzQqzfa8hoLaVbMJugV2UuDa0FNCg s1Rg== X-Gm-Message-State: AC+VfDwOD+JIj+iu04Bq0YmGtjkeHB13mh9ChkQy1eEqleyRG1lF+KBX 7mTv+VEEfgLjhAoXm+wZiAuE0khQcCL6FlX+LuM= X-Google-Smtp-Source: ACHHUZ69dsa0YdAKu8BeZN/1pHbJ7Nq33bxHdqja7NiFWB0YBdVr1JktAypxLh20xZ5knaqrkdVZJg== X-Received: by 2002:a05:6a00:248a:b0:64d:5b4b:8429 with SMTP id c10-20020a056a00248a00b0064d5b4b8429mr12323995pfv.18.1684850032528; Tue, 23 May 2023 06:53:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 35/52] tcg: Spit out exec/translation-block.h Date: Tue, 23 May 2023 06:53:05 -0700 Message-Id: <20230523135322.678948-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851158298100009 Content-Type: text/plain; charset="utf-8" This is all that is required by tcg/ from exec-all.h. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 135 +-------------------------- include/exec/translation-block.h | 152 +++++++++++++++++++++++++++++++ tcg/tcg-op-ldst.c | 2 +- 3 files changed, 154 insertions(+), 135 deletions(-) create mode 100644 include/exec/translation-block.h diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a09d754624..f01c7d57e8 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -24,20 +24,9 @@ #ifdef CONFIG_TCG #include "exec/cpu_ldst.h" #endif -#include "qemu/interval-tree.h" +#include "exec/translation-block.h" #include "qemu/clang-tsa.h" =20 -/* Page tracking code uses ram addresses in system mode, and virtual - addresses in userspace mode. Define tb_page_addr_t to be an appropriate - type. */ -#if defined(CONFIG_USER_ONLY) -typedef vaddr tb_page_addr_t; -#define TB_PAGE_ADDR_FMT "%" VADDR_PRIx -#else -typedef ram_addr_t tb_page_addr_t; -#define TB_PAGE_ADDR_FMT RAM_ADDR_FMT -#endif - /** * cpu_unwind_state_data: * @cpu: the cpu context @@ -478,8 +467,6 @@ int probe_access_full(CPUArchState *env, target_ulong a= ddr, int size, CPUTLBEntryFull **pfull, uintptr_t retaddr); #endif =20 -#define CODE_GEN_ALIGN 16 /* must be >=3D of the size of a icach= e line */ - /* Estimated block size for TB allocation. */ /* ??? The following is based on a 2015 survey of x86_64 host output. Better would seem to be some sort of dynamically sized TB array, @@ -490,126 +477,6 @@ int probe_access_full(CPUArchState *env, target_ulong= addr, int size, #define CODE_GEN_AVG_BLOCK_SIZE 150 #endif =20 -/* - * Translation Cache-related fields of a TB. - * This struct exists just for convenience; we keep track of TB's in a bin= ary - * search tree, and the only fields needed to compare TB's in the tree are - * @ptr and @size. - * Note: the address of search data can be obtained by adding @size to @pt= r. - */ -struct tb_tc { - const void *ptr; /* pointer to the translated code */ - size_t size; -}; - -struct TranslationBlock { - /* - * Guest PC corresponding to this block. This must be the true - * virtual address. Therefore e.g. x86 stores EIP + CS_BASE, and - * targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or - * privilege, must store those bits elsewhere. - * - * If CF_PCREL, the opcodes for the TranslationBlock are written - * such that the TB is associated only with the physical page and - * may be run in any virtual address context. In this case, PC - * must always be taken from ENV in a target-specific manner. - * Unwind information is taken as offsets from the page, to be - * deposited into the "current" PC. - */ - vaddr pc; - - /* - * Target-specific data associated with the TranslationBlock, e.g.: - * x86: the original user, the Code Segment virtual base, - * arm: an extension of tb->flags, - * s390x: instruction data for EXECUTE, - * sparc: the next pc of the instruction queue (for delay slots). - */ - uint64_t cs_base; - - uint32_t flags; /* flags defining in which context the code was genera= ted */ - uint32_t cflags; /* compile flags */ - -/* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */ -#define CF_COUNT_MASK 0x000001ff -#define CF_NO_GOTO_TB 0x00000200 /* Do not chain with goto_tb */ -#define CF_NO_GOTO_PTR 0x00000400 /* Do not chain with goto_ptr */ -#define CF_SINGLE_STEP 0x00000800 /* gdbstub single-step in effect */ -#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ -#define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ -#define CF_USE_ICOUNT 0x00020000 -#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock hel= d */ -#define CF_PARALLEL 0x00080000 /* Generate code for a parallel contex= t */ -#define CF_NOIRQ 0x00100000 /* Generate an uninterruptible TB */ -#define CF_PCREL 0x00200000 /* Opcodes in TB are PC-relative */ -#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ -#define CF_CLUSTER_SHIFT 24 - - /* Per-vCPU dynamic tracing state used to generate this TB */ - uint32_t trace_vcpu_dstate; - - /* - * Above fields used for comparing - */ - - /* size of target code for this block (1 <=3D size <=3D TARGET_PAGE_SI= ZE) */ - uint16_t size; - uint16_t icount; - - struct tb_tc tc; - - /* - * Track tb_page_addr_t intervals that intersect this TB. - * For user-only, the virtual addresses are always contiguous, - * and we use a unified interval tree. For system, we use a - * linked list headed in each PageDesc. Within the list, the lsb - * of the previous pointer tells the index of page_next[], and the - * list is protected by the PageDesc lock(s). - */ -#ifdef CONFIG_USER_ONLY - IntervalTreeNode itree; -#else - uintptr_t page_next[2]; - tb_page_addr_t page_addr[2]; -#endif - - /* jmp_lock placed here to fill a 4-byte hole. Its documentation is be= low */ - QemuSpin jmp_lock; - - /* The following data are used to directly call another TB from - * the code of this one. This can be done either by emitting direct or - * indirect native jump instructions. These jumps are reset so that th= e TB - * just continues its execution. The TB can be linked to another one by - * setting one of the jump targets (or patching the jump instruction).= Only - * two of such jumps are supported. - */ -#define TB_JMP_OFFSET_INVALID 0xffff /* indicates no jump generated */ - uint16_t jmp_reset_offset[2]; /* offset of original jump target */ - uint16_t jmp_insn_offset[2]; /* offset of direct jump insn */ - uintptr_t jmp_target_addr[2]; /* target address */ - - /* - * Each TB has a NULL-terminated list (jmp_list_head) of incoming jump= s. - * Each TB can have two outgoing jumps, and therefore can participate - * in two lists. The list entries are kept in jmp_list_next[2]. The le= ast - * significant bit (LSB) of the pointers in these lists is used to enc= ode - * which of the two list entries is to be used in the pointed TB. - * - * List traversals are protected by jmp_lock. The destination TB of ea= ch - * outgoing jump is kept in jmp_dest[] so that the appropriate jmp_lock - * can be acquired from any origin TB. - * - * jmp_dest[] are tagged pointers as well. The LSB is set when the TB = is - * being invalidated, so that no further outgoing jumps from it can be= set. - * - * jmp_lock also protects the CF_INVALID cflag; a jump must not be cha= ined - * to a destination TB that has CF_INVALID set. - */ - uintptr_t jmp_list_head; - uintptr_t jmp_list_next[2]; - uintptr_t jmp_dest[2]; -}; - /* Hide the qatomic_read to make code a little easier on the eyes */ static inline uint32_t tb_cflags(const TranslationBlock *tb) { diff --git a/include/exec/translation-block.h b/include/exec/translation-bl= ock.h new file mode 100644 index 0000000000..37aa979e20 --- /dev/null +++ b/include/exec/translation-block.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: LGPL-2.1-or-later */ +/* + * Definition of TranslationBlock. + * Copyright (c) 2003 Fabrice Bellard + */ + +#ifndef EXEC_TRANSLATION_BLOCK_H +#define EXEC_TRANSLATION_BLOCK_H + +#include "qemu/atomic.h" +#include "qemu/thread.h" +#include "qemu/interval-tree.h" +#include "exec/cpu-common.h" +#include "exec/target_page.h" + +/* + * Page tracking code uses ram addresses in system mode, and virtual + * addresses in userspace mode. Define tb_page_addr_t to be an + * appropriate type. + */ +#if defined(CONFIG_USER_ONLY) +typedef vaddr tb_page_addr_t; +#define TB_PAGE_ADDR_FMT "%" VADDR_PRIx +#else +typedef ram_addr_t tb_page_addr_t; +#define TB_PAGE_ADDR_FMT RAM_ADDR_FMT +#endif + +/* + * Translation Cache-related fields of a TB. + * This struct exists just for convenience; we keep track of TB's in a bin= ary + * search tree, and the only fields needed to compare TB's in the tree are + * @ptr and @size. + * Note: the address of search data can be obtained by adding @size to @pt= r. + */ +struct tb_tc { + const void *ptr; /* pointer to the translated code */ + size_t size; +}; + +struct TranslationBlock { + /* + * Guest PC corresponding to this block. This must be the true + * virtual address. Therefore e.g. x86 stores EIP + CS_BASE, and + * targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or + * privilege, must store those bits elsewhere. + * + * If CF_PCREL, the opcodes for the TranslationBlock are written + * such that the TB is associated only with the physical page and + * may be run in any virtual address context. In this case, PC + * must always be taken from ENV in a target-specific manner. + * Unwind information is taken as offsets from the page, to be + * deposited into the "current" PC. + */ + vaddr pc; + + /* + * Target-specific data associated with the TranslationBlock, e.g.: + * x86: the original user, the Code Segment virtual base, + * arm: an extension of tb->flags, + * s390x: instruction data for EXECUTE, + * sparc: the next pc of the instruction queue (for delay slots). + */ + uint64_t cs_base; + + uint32_t flags; /* flags defining in which context the code was genera= ted */ + uint32_t cflags; /* compile flags */ + +/* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */ +#define CF_COUNT_MASK 0x000001ff +#define CF_NO_GOTO_TB 0x00000200 /* Do not chain with goto_tb */ +#define CF_NO_GOTO_PTR 0x00000400 /* Do not chain with goto_ptr */ +#define CF_SINGLE_STEP 0x00000800 /* gdbstub single-step in effect */ +#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ +#define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ +#define CF_USE_ICOUNT 0x00020000 +#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock hel= d */ +#define CF_PARALLEL 0x00080000 /* Generate code for a parallel contex= t */ +#define CF_NOIRQ 0x00100000 /* Generate an uninterruptible TB */ +#define CF_PCREL 0x00200000 /* Opcodes in TB are PC-relative */ +#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ +#define CF_CLUSTER_SHIFT 24 + + /* Per-vCPU dynamic tracing state used to generate this TB */ + uint32_t trace_vcpu_dstate; + + /* + * Above fields used for comparing + */ + + /* size of target code for this block (1 <=3D size <=3D TARGET_PAGE_SI= ZE) */ + uint16_t size; + uint16_t icount; + + struct tb_tc tc; + + /* + * Track tb_page_addr_t intervals that intersect this TB. + * For user-only, the virtual addresses are always contiguous, + * and we use a unified interval tree. For system, we use a + * linked list headed in each PageDesc. Within the list, the lsb + * of the previous pointer tells the index of page_next[], and the + * list is protected by the PageDesc lock(s). + */ +#ifdef CONFIG_USER_ONLY + IntervalTreeNode itree; +#else + uintptr_t page_next[2]; + tb_page_addr_t page_addr[2]; +#endif + + /* jmp_lock placed here to fill a 4-byte hole. Its documentation is be= low */ + QemuSpin jmp_lock; + + /* The following data are used to directly call another TB from + * the code of this one. This can be done either by emitting direct or + * indirect native jump instructions. These jumps are reset so that th= e TB + * just continues its execution. The TB can be linked to another one by + * setting one of the jump targets (or patching the jump instruction).= Only + * two of such jumps are supported. + */ +#define TB_JMP_OFFSET_INVALID 0xffff /* indicates no jump generated */ + uint16_t jmp_reset_offset[2]; /* offset of original jump target */ + uint16_t jmp_insn_offset[2]; /* offset of direct jump insn */ + uintptr_t jmp_target_addr[2]; /* target address */ + + /* + * Each TB has a NULL-terminated list (jmp_list_head) of incoming jump= s. + * Each TB can have two outgoing jumps, and therefore can participate + * in two lists. The list entries are kept in jmp_list_next[2]. The le= ast + * significant bit (LSB) of the pointers in these lists is used to enc= ode + * which of the two list entries is to be used in the pointed TB. + * + * List traversals are protected by jmp_lock. The destination TB of ea= ch + * outgoing jump is kept in jmp_dest[] so that the appropriate jmp_lock + * can be acquired from any origin TB. + * + * jmp_dest[] are tagged pointers as well. The LSB is set when the TB = is + * being invalidated, so that no further outgoing jumps from it can be= set. + * + * jmp_lock also protects the CF_INVALID cflag; a jump must not be cha= ined + * to a destination TB that has CF_INVALID set. + */ + uintptr_t jmp_list_head; + uintptr_t jmp_list_next[2]; + uintptr_t jmp_dest[2]; +}; + +/* The alignment given to TranslationBlock during allocation. */ +#define CODE_GEN_ALIGN 16 + +#endif /* EXEC_TRANSLATION_BLOCK_H */ diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 02827b96cc..f32c0fda35 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -23,11 +23,11 @@ */ =20 #include "qemu/osdep.h" -#include "exec/exec-all.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" #include "tcg/tcg-op-common.h" #include "tcg/tcg-mo.h" +#include "exec/translation-block.h" #include "exec/plugin-gen.h" #include "tcg-internal.h" =20 --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851405; cv=none; d=zohomail.com; s=zohoarc; b=MjjzBJZTJYgf75IvSJqOkG+G0EzjR0xPlsZQQ0UTeCJJQGU2z8zDOI5hirBUHREtNbHDMhmq6UrtYCDxdBtL7y2NnLYHNt6ND/7QLa0IPbkYJZofaVdSi7Zo1Yz1HiVOXAtGzJ2rlnOq3YRkucOSZvbPfeWCgnBex4/hY/v1uwg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851405; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=g9Z7ehG7+swOH6zB5dODu6bYg//xIYbQwbOdJN6xAFw=; b=cWLcbzSWQfJU3NoeKXqotKqyjHbqbwor0hvwscFfJhVa7PegXimig6PsdE8lyIQ28iaDWTvnm5hSsHXNRZM71hU6maG2VAX/Rw6DyEao1E/VFml9T2kJeRbMVORSIDsO1U9QidkX5rDtonLpd+i4qWlZritfZ8+aInPhpQU5400= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684851405464299.7789492844048; Tue, 23 May 2023 07:16:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SUe-0000ne-O2; Tue, 23 May 2023 09:56:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSZ-0005AA-VV for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:56 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSY-00039l-Gn for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:55 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-64d24136685so3504749b3a.1 for ; Tue, 23 May 2023 06:53:54 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850033; x=1687442033; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=g9Z7ehG7+swOH6zB5dODu6bYg//xIYbQwbOdJN6xAFw=; b=VoLmy0zeNcxaB5k7SHGJIMvmSv3GNgwUNssLKkLX0oJ+fdREZgdWAV0q7/C80wqhsd +J8Zy4RaR1aln7Y01qOF7yMyN19G/5UHN3kk8fGpKIxJHDUlu2ixzWIdgRIoFrHaTUx2 QnXce6DkEMPAHhZclAPdMXzanrtXP3qLcz+vjmZOn/OjYLczb3DecAFDhwna+RRVlJmI npKhkQ5RnQoY1yB0AyElvkz++Jd4stSk+H4+hlmB1QfWIEomqPHNjHG30RHHoHrV3NlX LG7gn54gr4J/r4fs13VAHDEqVfU7bIE04of0sG4qS8l7XYwApMXnzX5nI4WpZTwwQ52x 8vug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850033; x=1687442033; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g9Z7ehG7+swOH6zB5dODu6bYg//xIYbQwbOdJN6xAFw=; b=RhIEoUC0xGBKoBTUaY/KAUtCi0DC8o0E67th/iXsdy3QUQkU0dmfuqOsrSbKDfHHLi a0sa86Azo4LvBWkSzhUKLTFoD8ahz9UAWAdqRCx9MdKdAORYauKI2TIbl0LqFUVdMGNx VXwKJXIV4ifzz7HkX59/RvMKbZ85w5BA5o5Rv6wT79TuqKw+lXMRmQfKsHGERmWzEmuR Bs3NNmX1Pb3M1quuO/QkRnmozcoNR4N3ldbhqqot2C9WBbKifBFE9J+MMmxwOUvUqXhN UAh6+OXafPzDLIlewzPczMWYDcvoA98s7baVamTop8Cfr4+B3jSMgRgRDRpRkIq1W3XJ S09g== X-Gm-Message-State: AC+VfDxkSnCEVG+C7M6YtG3l0MXXI0t5PT3P9LCXvJktpOtW/5tnrERo I6bSl0fow8N4bOeIXHf+6Iizi2fYAmTvIMueJ54= X-Google-Smtp-Source: ACHHUZ7OJoqdX1mY2SfA5jrlcIBHe2qiJrOrI4dZF5/fTiHjFrkZicRSccbo30gqObd5oE8XJyPniQ== X-Received: by 2002:a05:6a20:2454:b0:104:873:c3be with SMTP id t20-20020a056a20245400b001040873c3bemr12728349pzc.12.1684850033220; Tue, 23 May 2023 06:53:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 36/52] include/exec: Remove CODE_GEN_AVG_BLOCK_SIZE Date: Tue, 23 May 2023 06:53:06 -0700 Message-Id: <20230523135322.678948-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851406638100001 Content-Type: text/plain; charset="utf-8" The last use was removed with 2ac01d6dafab. Fixes: 2ac01d6dafab ("translate-all: use a binary search tree to track TBs = in TBContext") Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f01c7d57e8..698943d58f 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -467,16 +467,6 @@ int probe_access_full(CPUArchState *env, target_ulong = addr, int size, CPUTLBEntryFull **pfull, uintptr_t retaddr); #endif =20 -/* Estimated block size for TB allocation. */ -/* ??? The following is based on a 2015 survey of x86_64 host output. - Better would seem to be some sort of dynamically sized TB array, - adapting to the block sizes actually being produced. */ -#if defined(CONFIG_SOFTMMU) -#define CODE_GEN_AVG_BLOCK_SIZE 400 -#else -#define CODE_GEN_AVG_BLOCK_SIZE 150 -#endif - /* Hide the qatomic_read to make code a little easier on the eyes */ static inline uint32_t tb_cflags(const TranslationBlock *tb) { --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684853411; cv=none; d=zohomail.com; s=zohoarc; b=DT1D48XPY9G5tA6QH6/vh+Mats6zXQEDDJK62fexJvHMrZhvfVMUI56dMHBqByJKExWwkr7cxqYxamOnmIRimNQaWxW38RBosgzVLIAWMXNRN/JZmrH3NjqU4op5zyyYNWowWCjq+GUzXz/HKwQh3Kf6amXLYv9QQniBu2er3dU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684853411; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YHMznhDZOucZiZnqaYMteWVjZfl00HdpVCrzNF7XO3s=; b=EdJIHl8VPD/tUVKzFfakA2FkDXGAaJQ0JT/BEbv1E8YRtHTk3FFXp6IINV//znKKBiTMGqE0+NwKpYYI/IPwIZt53gKoFg25jOAyq5OMx2YTFT8Tj3K0QheeiMj2WtNoS6HzmdAO5nRa/enszSBRUSqHBJJ/9QHWToWxloUC8og= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684853411380244.9267486101944; Tue, 23 May 2023 07:50:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SUM-0000b8-Hg; Tue, 23 May 2023 09:55:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSa-0005AO-Q7 for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:58 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSY-00035U-TR for qemu-devel@nongnu.org; Tue, 23 May 2023 09:53:56 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-64d3fbb8c1cso4743978b3a.3 for ; Tue, 23 May 2023 06:53:54 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850034; x=1687442034; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=YHMznhDZOucZiZnqaYMteWVjZfl00HdpVCrzNF7XO3s=; b=dtFyH/gIehEeHyrlOeqtpR1mvBqucYh9TlLWarcvBzaxE3lln2ips1szipzoYwl3OQ KriTdgBU0VepTwo9l0mF1V1gqjtaFNLZeD3zVvJipXpHTeEs3p7RbUdylucJnne0ABTo E/dfeZ6hS4n4bqybM5b21x04ttho4STGQbcmjev9bvdPV8ZiS6uJ5agy9oI+kt4qLpgK 109GtVE0bDQGpXOo4lekMfT9RBZ6S8e7RlQb3GDcZTSKe59Pc9rFNGVOGQZp/CEKZ+OD dl1JaxSy3w7Tyy5gDQhe24z8zga6jrjP6uLxW+noc1lKoMHsu0bPksK4TidccR2GwioB 4aJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850034; x=1687442034; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YHMznhDZOucZiZnqaYMteWVjZfl00HdpVCrzNF7XO3s=; b=MP6+1WrRZyhWPS2PQVvXDEZo1sKkqa0zlGJfkhi90aHYAi/PI4zKy/r0S/jnUQt4Ki R/eUXK6h/FZvaOHenUBM43acb2hMQ30EOSybR0+Tl7acdJDtLFn1KA0rQ69tolgW1xFG K+IG+VzQv8UQndkLdp5DHzf0g8u2mrMxP+Z8MRs5mQM+Y7pAj2gR48dQDUt/+RUSfNv9 34aGeijKOHJ57LTEP3oxETyi5GnVrBEKKWmTEwlJK9gWUFLVcqQid+wlm5WVLjGYKqZM NvljQvFCaHx4dtNAuVC/PbXuPEDDNsaHcsK4xw6bk8tXNVInlQRyvk21X22znn4mAzyo B4OA== X-Gm-Message-State: AC+VfDxmgfL0AKtqPmpT6ZTdB8heZMvUEX+k9/QN+XqnEiKuJ0hhR60m dzD/lDvIVPxcOf9Y8PYg5QyrbfgsZfgNpf625hg= X-Google-Smtp-Source: ACHHUZ4rhit60VNBmxjHaMQ3iTC0l1o1BYEr2XmU9xIGErGX9U53T2qYJbqxGIOQzPSK85zhOrZDuQ== X-Received: by 2002:aa7:88c5:0:b0:64a:f8c9:a42c with SMTP id k5-20020aa788c5000000b0064af8c9a42cmr17937911pff.18.1684850034010; Tue, 23 May 2023 06:53:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 37/52] accel/tcg: Move most of gen-icount.h into translator.c Date: Tue, 23 May 2023 06:53:07 -0700 Message-Id: <20230523135322.678948-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684853411966100001 Content-Type: text/plain; charset="utf-8" The only usage of gen_tb_start and gen_tb_end are here. Move the static icount_start_insn variable into a local within translator_loop. Simplify the two subroutines by passing in the existing local cflags variable. Leave only the declaration of gen_io_start in gen-icount.h. Signed-off-by: Richard Henderson --- include/exec/gen-icount.h | 79 +------------------------------------ accel/tcg/translator.c | 83 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 82 insertions(+), 80 deletions(-) diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index f6de79a6b4..6006af4c06 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -1,83 +1,6 @@ #ifndef GEN_ICOUNT_H #define GEN_ICOUNT_H =20 -#include "exec/exec-all.h" - -/* Helpers for instruction counting code generation. */ - -static TCGOp *icount_start_insn; - -static inline void gen_io_start(void) -{ - tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, - offsetof(ArchCPU, parent_obj.can_do_io) - - offsetof(ArchCPU, env)); -} - -static inline void gen_tb_start(const TranslationBlock *tb) -{ - TCGv_i32 count =3D tcg_temp_new_i32(); - - tcg_gen_ld_i32(count, cpu_env, - offsetof(ArchCPU, neg.icount_decr.u32) - - offsetof(ArchCPU, env)); - - if (tb_cflags(tb) & CF_USE_ICOUNT) { - /* - * We emit a sub with a dummy immediate argument. Keep the insn in= dex - * of the sub so that we later (when we know the actual insn count) - * can update the argument with the actual insn count. - */ - tcg_gen_sub_i32(count, count, tcg_constant_i32(0)); - icount_start_insn =3D tcg_last_op(); - } - - /* - * Emit the check against icount_decr.u32 to see if we should exit - * unless we suppress the check with CF_NOIRQ. If we are using - * icount and have suppressed interruption the higher level code - * should have ensured we don't run more instructions than the - * budget. - */ - if (tb_cflags(tb) & CF_NOIRQ) { - tcg_ctx->exitreq_label =3D NULL; - } else { - tcg_ctx->exitreq_label =3D gen_new_label(); - tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, tcg_ctx->exitreq_label); - } - - if (tb_cflags(tb) & CF_USE_ICOUNT) { - tcg_gen_st16_i32(count, cpu_env, - offsetof(ArchCPU, neg.icount_decr.u16.low) - - offsetof(ArchCPU, env)); - /* - * cpu->can_do_io is cleared automatically here at the beginning of - * each translation block. The cost is minimal and only paid for - * -icount, plus it would be very easy to forget doing it in the - * translator. Doing it here means we don't need a gen_io_end() to - * go with gen_io_start(). - */ - tcg_gen_st_i32(tcg_constant_i32(0), cpu_env, - offsetof(ArchCPU, parent_obj.can_do_io) - - offsetof(ArchCPU, env)); - } -} - -static inline void gen_tb_end(const TranslationBlock *tb, int num_insns) -{ - if (tb_cflags(tb) & CF_USE_ICOUNT) { - /* - * Update the num_insn immediate parameter now that we know - * the actual insn count. - */ - tcg_set_insn_param(icount_start_insn, 2, - tcgv_i32_arg(tcg_constant_i32(num_insns))); - } - - if (tcg_ctx->exitreq_label) { - gen_set_label(tcg_ctx->exitreq_label); - tcg_gen_exit_tb(tb, TB_EXIT_REQUESTED); - } -} +void gen_io_start(void); =20 #endif diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 6120ef2a92..b0d0015c70 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -18,6 +18,84 @@ #include "exec/plugin-gen.h" #include "exec/replay-core.h" =20 + +void gen_io_start(void) +{ + tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, + offsetof(ArchCPU, parent_obj.can_do_io) - + offsetof(ArchCPU, env)); +} + +static TCGOp *gen_tb_start(uint32_t cflags) +{ + TCGv_i32 count =3D tcg_temp_new_i32(); + TCGOp *icount_start_insn =3D NULL; + + tcg_gen_ld_i32(count, cpu_env, + offsetof(ArchCPU, neg.icount_decr.u32) - + offsetof(ArchCPU, env)); + + if (cflags & CF_USE_ICOUNT) { + /* + * We emit a sub with a dummy immediate argument. Keep the insn in= dex + * of the sub so that we later (when we know the actual insn count) + * can update the argument with the actual insn count. + */ + tcg_gen_sub_i32(count, count, tcg_constant_i32(0)); + icount_start_insn =3D tcg_last_op(); + } + + /* + * Emit the check against icount_decr.u32 to see if we should exit + * unless we suppress the check with CF_NOIRQ. If we are using + * icount and have suppressed interruption the higher level code + * should have ensured we don't run more instructions than the + * budget. + */ + if (cflags & CF_NOIRQ) { + tcg_ctx->exitreq_label =3D NULL; + } else { + tcg_ctx->exitreq_label =3D gen_new_label(); + tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, tcg_ctx->exitreq_label); + } + + if (cflags & CF_USE_ICOUNT) { + tcg_gen_st16_i32(count, cpu_env, + offsetof(ArchCPU, neg.icount_decr.u16.low) - + offsetof(ArchCPU, env)); + /* + * cpu->can_do_io is cleared automatically here at the beginning of + * each translation block. The cost is minimal and only paid for + * -icount, plus it would be very easy to forget doing it in the + * translator. Doing it here means we don't need a gen_io_end() to + * go with gen_io_start(). + */ + tcg_gen_st_i32(tcg_constant_i32(0), cpu_env, + offsetof(ArchCPU, parent_obj.can_do_io) - + offsetof(ArchCPU, env)); + } + + return icount_start_insn; +} + +static void gen_tb_end(const TranslationBlock *tb, uint32_t cflags, + TCGOp *icount_start_insn, int num_insns) +{ + if (cflags & CF_USE_ICOUNT) { + /* + * Update the num_insn immediate parameter now that we know + * the actual insn count. + */ + tcg_set_insn_param(icount_start_insn, 2, + tcgv_i32_arg(tcg_constant_i32(num_insns))); + } + + if (tcg_ctx->exitreq_label) { + gen_set_label(tcg_ctx->exitreq_label); + tcg_gen_exit_tb(tb, TB_EXIT_REQUESTED); + } +} + bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest) { /* Suppress goto_tb if requested. */ @@ -34,6 +112,7 @@ void translator_loop(CPUState *cpu, TranslationBlock *tb= , int *max_insns, const TranslatorOps *ops, DisasContextBase *db) { uint32_t cflags =3D tb_cflags(tb); + TCGOp *icount_start_insn; bool plugin_enabled; =20 /* Initialize DisasContext */ @@ -55,7 +134,7 @@ void translator_loop(CPUState *cpu, TranslationBlock *tb= , int *max_insns, tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ =20 /* Start translating. */ - gen_tb_start(db->tb); + icount_start_insn =3D gen_tb_start(cflags); ops->tb_start(db, cpu); tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ =20 @@ -112,7 +191,7 @@ void translator_loop(CPUState *cpu, TranslationBlock *t= b, int *max_insns, =20 /* Emit code to exit the TB, as indicated by db->is_jmp. */ ops->tb_stop(db, cpu); - gen_tb_end(db->tb, db->num_insns); + gen_tb_end(tb, cflags, icount_start_insn, db->num_insns); =20 if (plugin_enabled) { plugin_gen_tb_end(cpu); --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851248; cv=none; d=zohomail.com; s=zohoarc; b=EiGEU2undmQS/OrId2yt7l2I5MV8F9lYsdMJkTLGjv4dMG7QQQGz/nKeyItUlZHLqwHIVDbaT5xh31mJMzj8hStnyVy+bOa5b3fXZrmD91l0JIiec+7Zndr7HKnxhDohklLn+yTB84BQ5Wx0cuJif9ksV9Da15uyw58g0LNKLWQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851248; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MA1LI1rMyXAOmoeuR5iGue00L90SxUPlcKIvdmIf31I=; b=FhCl9Y9DdMVdOUNQy4oVIi/8+igc5SrROrSNU4QGfzIui2fVrdk/kbbQTt/9lWcF8jHWQkMaWHVlUflkK/CtUhQQoy+tzyRGkYXHA24nIVn8pHzraseDOKZ5aQOHSuwVmXSiWrK/POYW0vBwUKGqWIiiRRZQa/UK6ql4aExfFlg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684851248253313.27520002034703; Tue, 23 May 2023 07:14:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SUj-0001Qe-Rj; Tue, 23 May 2023 09:56:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SSe-0005Hi-K9 for qemu-devel@nongnu.org; Tue, 23 May 2023 09:54:01 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SSa-00037f-76 for qemu-devel@nongnu.org; Tue, 23 May 2023 09:54:00 -0400 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-64d2a87b9daso3899625b3a.0 for ; Tue, 23 May 2023 06:53:55 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850035; x=1687442035; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=MA1LI1rMyXAOmoeuR5iGue00L90SxUPlcKIvdmIf31I=; b=L/t8BtjXm5ccVqaTYo1hGf8QZwCVZg5wIFlsc7vjj7QQAtYj+twt8avvkT5A1bECWT D204adzc3dV9VeFWHkCVjXoe/FNBa9vQnVO79c5QeNPKVRZxSwLxZOg2nabr66715H8p +QECtK9lHNqkM9LZaq3ZyFcUN6WGlFxZz7+vfSuCQB+vR1OhAvvp1oVhpgtFxphT980A yl9dHd47mTJ5/Z/kXkCUNOEKkdgS1IzqGnQGn2a9mGKzz0ml6WWdZiAbkmJZ8U99SqA0 gZSghzTCL9ieHdmVZO/Qo4INo9jqISYh20icM5jEgWXX6zfCaIRlcNZhH0jDfr/VuwmQ vjXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850035; x=1687442035; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MA1LI1rMyXAOmoeuR5iGue00L90SxUPlcKIvdmIf31I=; b=JHBnwpPz+cC+Ru+QGoBM/+PP3ikfI6SB1N/N2BWh0p9qdYJgQHHYLlC8Kf9qvvPKC6 iKgcuN5KNuV7nT4zgxqZw8m6J9y86GDrDMV5N4bKBYVd0tOBOuQXuyQ4sAH+jihb4eaH vKKl/mnmA8ES9zV7YasXWEm6kEtjlb1N32XoKTEF58mRP8tUTSog51jQXE2M57kDjtJ/ XO+WiBFF8euChA0KUWg6npPUz4Fulu0vEb6mtUkdoR4OZL6f44FvfDdZW2HHPEpGbgoV 3XmqN3t6/My9QVZhSUXBI3KtCB/ul6OEpkp2vNGpSTlOMwjChepdi25DYrypvHJmq968 /Czw== X-Gm-Message-State: AC+VfDwJoN09poLLFLHTAwg4yoKr1tu5sXnZ4bpfcr0x6xqLT89wPYf5 uFUPOr7bwVlJ+Hath7hE4NjTedk3DGMDn3T+r2Q= X-Google-Smtp-Source: ACHHUZ4lHVB/wswtOGdg/UvqgNnk3eQOxH+WBZXJt9bjTPnJE2xpgmp3OonR8nykVs7RKlrUpetFcg== X-Received: by 2002:a05:6a00:1389:b0:643:b27f:6c43 with SMTP id t9-20020a056a00138900b00643b27f6c43mr20957044pfg.27.1684850035102; Tue, 23 May 2023 06:53:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 38/52] accel/tcg: Introduce translator_io_start Date: Tue, 23 May 2023 06:53:08 -0700 Message-Id: <20230523135322.678948-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851249258100003 Content-Type: text/plain; charset="utf-8" New wrapper around gen_io_start which takes care of the USE_ICOUNT check, as well as marking the DisasContext to end the TB. Remove exec/gen-icount.h. Signed-off-by: Richard Henderson --- include/exec/gen-icount.h | 6 -- include/exec/translator.h | 10 +++ target/arm/cpregs.h | 4 +- accel/tcg/translator.c | 27 ++++++- target/alpha/translate.c | 15 +--- target/arm/tcg/translate-a64.c | 23 +++--- target/arm/tcg/translate-mve.c | 1 - target/arm/tcg/translate-neon.c | 1 - target/arm/tcg/translate-vfp.c | 4 +- target/arm/tcg/translate.c | 20 ++--- target/avr/translate.c | 1 - target/cris/translate.c | 2 - target/hppa/translate.c | 5 +- target/i386/tcg/translate.c | 52 +++---------- target/loongarch/translate.c | 2 - target/m68k/translate.c | 2 - target/microblaze/translate.c | 2 - target/mips/tcg/translate.c | 29 +++---- target/nios2/translate.c | 1 - target/openrisc/translate.c | 9 +-- target/ppc/translate.c | 13 +--- target/riscv/translate.c | 2 - target/rx/translate.c | 2 - target/s390x/tcg/translate.c | 6 +- target/sh4/translate.c | 2 - target/sparc/translate.c | 75 +++++-------------- target/tricore/translate.c | 2 - target/xtensa/translate.c | 27 ++----- MAINTAINERS | 1 - target/loongarch/insn_trans/trans_extra.c.inc | 4 +- .../insn_trans/trans_privileged.c.inc | 4 +- .../riscv/insn_trans/trans_privileged.c.inc | 8 +- target/riscv/insn_trans/trans_rvi.c.inc | 24 ++---- 33 files changed, 117 insertions(+), 269 deletions(-) delete mode 100644 include/exec/gen-icount.h diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h deleted file mode 100644 index 6006af4c06..0000000000 --- a/include/exec/gen-icount.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef GEN_ICOUNT_H -#define GEN_ICOUNT_H - -void gen_io_start(void); - -#endif diff --git a/include/exec/translator.h b/include/exec/translator.h index 797fef7515..c1a1203789 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -160,6 +160,16 @@ void translator_loop(CPUState *cpu, TranslationBlock *= tb, int *max_insns, */ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest); =20 +/** + * translator_io_start + * @db: Disassembly context + * + * If icount is enabled, set cpu->can_to_io, adjust db->is_jmp to + * DISAS_TOO_MANY if it is still DISAS_NEXT, and return true. + * Otherwise return false. + */ +bool translator_io_start(DisasContextBase *db); + /* * Translator Load Functions * diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index b04d344a9f..14785686f6 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -67,8 +67,8 @@ enum { ARM_CP_ALIAS =3D 1 << 8, /* * Flag: Register does I/O and therefore its accesses need to be marked - * with gen_io_start() and also end the TB. In particular, registers w= hich - * implement clocks or timers require this. + * with translator_io_start() and also end the TB. In particular, + * registers which implement clocks or timers require this. */ ARM_CP_IO =3D 1 << 9, /* diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index b0d0015c70..7a130e706e 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -12,20 +12,43 @@ #include "tcg/tcg.h" #include "tcg/tcg-op.h" #include "exec/exec-all.h" -#include "exec/gen-icount.h" #include "exec/log.h" #include "exec/translator.h" #include "exec/plugin-gen.h" #include "exec/replay-core.h" =20 =20 -void gen_io_start(void) +static void gen_io_start(void) { tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, offsetof(ArchCPU, parent_obj.can_do_io) - offsetof(ArchCPU, env)); } =20 +bool translator_io_start(DisasContextBase *db) +{ + uint32_t cflags =3D tb_cflags(db->tb); + + if (!(cflags & CF_USE_ICOUNT)) { + return false; + } + if (db->num_insns =3D=3D db->max_insns && (cflags & CF_LAST_IO)) { + /* Already started in translator_loop. */ + return true; + } + + gen_io_start(); + + /* + * Ensure that this instruction will be the last in the TB. + * The target may override this to something more forceful. + */ + if (db->is_jmp =3D=3D DISAS_NEXT) { + db->is_jmp =3D DISAS_TOO_MANY; + } + return true; +} + static TCGOp *gen_tb_start(uint32_t cflags) { TCGv_i32 count =3D tcg_temp_new_i32(); diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 545e5743c3..1f7dd078d8 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -96,8 +96,6 @@ static TCGv cpu_lock_value; static TCGv cpu_pal_ir[31]; #endif =20 -#include "exec/gen-icount.h" - void alpha_translate_init(void) { #define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUAlphaState, V) } @@ -1236,8 +1234,7 @@ static DisasJumpType gen_mfpr(DisasContext *ctx, TCGv= va, int regno) case 249: /* VMTIME */ helper =3D gen_helper_get_vmtime; do_helper: - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); + if (translator_io_start(&ctx->base)) { helper(va); return DISAS_PC_STALE; } else { @@ -1298,8 +1295,7 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv= vb, int regno) =20 case 251: /* ALARM */ - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); + if (translator_io_start(&ctx->base)) { ret =3D DISAS_PC_STALE; } gen_helper_set_alarm(cpu_env, vb); @@ -2335,13 +2331,10 @@ static DisasJumpType translate_one(DisasContext *ct= x, uint32_t insn) case 0xC000: /* RPCC */ va =3D dest_gpr(ctx, ra); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - gen_helper_load_pcc(va, cpu_env); + if (translator_io_start(&ctx->base)) { ret =3D DISAS_PC_STALE; - } else { - gen_helper_load_pcc(va, cpu_env); } + gen_helper_load_pcc(va, cpu_env); break; case 0xE000: /* RC */ diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index bc0cb98955..8d45dbf8fc 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -28,7 +28,6 @@ #include "internals.h" #include "qemu/host-utils.h" #include "semihosting/semihost.h" -#include "exec/gen-icount.h" #include "exec/log.h" #include "cpregs.h" #include "translate-a64.h" @@ -1552,9 +1551,7 @@ static bool trans_ERET(DisasContext *s, arg_ERET *a) tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUARMState, elr_el[s->current_el])); =20 - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&s->base); =20 gen_helper_exception_return(cpu_env, dst); /* Must exit loop to check un-masked IRQs */ @@ -1582,9 +1579,8 @@ static bool trans_ERETA(DisasContext *s, arg_reta *a) offsetof(CPUARMState, elr_el[s->current_el])); =20 dst =3D auth_branch_target(s, dst, cpu_X[31], !a->m); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + + translator_io_start(&s->base); =20 gen_helper_exception_return(cpu_env, dst); /* Must exit loop to check un-masked IRQs */ @@ -2044,6 +2040,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, uint32_t key =3D ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2); const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(s->cp_regs, key); + bool need_exit_tb =3D false; TCGv_ptr tcg_ri =3D NULL; TCGv_i64 tcg_rt; =20 @@ -2171,8 +2168,9 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, return; } =20 - if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO))= { - gen_io_start(); + if (ri->type & ARM_CP_IO) { + /* I/O operations must end the TB here (whether read or write) */ + need_exit_tb =3D translator_io_start(&s->base); } =20 tcg_rt =3D cpu_reg(s, rt); @@ -2202,10 +2200,6 @@ static void handle_sys(DisasContext *s, uint32_t ins= n, bool isread, } } =20 - if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO))= { - /* I/O operations must end the TB here (whether read or write) */ - s->base.is_jmp =3D DISAS_UPDATE_EXIT; - } if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* * A write to any coprocessor regiser that ends a TB @@ -2217,6 +2211,9 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ + need_exit_tb =3D true; + } + if (need_exit_tb) { s->base.is_jmp =3D DISAS_UPDATE_EXIT; } } diff --git a/target/arm/tcg/translate-mve.c b/target/arm/tcg/translate-mve.c index 31fb2110f1..2ad3c40975 100644 --- a/target/arm/tcg/translate-mve.c +++ b/target/arm/tcg/translate-mve.c @@ -21,7 +21,6 @@ #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "exec/exec-all.h" -#include "exec/gen-icount.h" #include "translate.h" #include "translate-a32.h" =20 diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neo= n.c index af8685a4ac..6fac577abd 100644 --- a/target/arm/tcg/translate-neon.c +++ b/target/arm/tcg/translate-neon.c @@ -24,7 +24,6 @@ #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "exec/exec-all.h" -#include "exec/gen-icount.h" #include "translate.h" #include "translate-a32.h" =20 diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index dd782aacf4..95ac8d9db3 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -24,7 +24,6 @@ #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "exec/exec-all.h" -#include "exec/gen-icount.h" #include "translate.h" #include "translate-a32.h" =20 @@ -117,9 +116,8 @@ static void gen_preserve_fp_state(DisasContext *s, bool= skip_context_update) * so we must mark it as an IO operation for icount (and cause * this to be the last insn in the TB). */ - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + if (translator_io_start(&s->base)) { s->base.is_jmp =3D DISAS_UPDATE_EXIT; - gen_io_start(); } gen_helper_v7m_preserve_fp_state(cpu_env); /* diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 379f266256..7caf6d802d 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -34,7 +34,6 @@ #include "cpregs.h" #include "translate.h" #include "translate-a32.h" -#include "exec/gen-icount.h" #include "exec/helper-proto.h" =20 #define HELPER_H "helper.h" @@ -2908,9 +2907,7 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCG= v_i32 cpsr) * appropriately depending on the new Thumb bit, so it must * be called after storing the new PC. */ - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&s->base); gen_helper_cpsr_write_eret(cpu_env, cpsr); /* Must exit loop to check un-masked IRQs */ s->base.is_jmp =3D DISAS_EXIT; @@ -4559,7 +4556,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, uint32_t key =3D ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc= 2); const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(s->cp_regs, key); TCGv_ptr tcg_ri =3D NULL; - bool need_exit_tb; + bool need_exit_tb =3D false; uint32_t syndrome; =20 /* @@ -4704,8 +4701,9 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, g_assert_not_reached(); } =20 - if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO))= { - gen_io_start(); + if (ri->type & ARM_CP_IO) { + /* I/O operations must end the TB here (whether read or write) */ + need_exit_tb =3D translator_io_start(&s->base); } =20 if (isread) { @@ -4787,10 +4785,6 @@ static void do_coproc_insn(DisasContext *s, int cpnu= m, int is64, } } =20 - /* I/O operations must end the TB here (whether read or write) */ - need_exit_tb =3D ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && - (ri->type & ARM_CP_IO)); - if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* * A write to any coprocessor register that ends a TB @@ -8047,9 +8041,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a= , int min_n) if (exc_return) { /* Restore CPSR from SPSR. */ tmp =3D load_cpu_field(spsr); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&s->base); gen_helper_cpsr_write_eret(cpu_env, tmp); /* Must exit loop to check un-masked IRQs */ s->base.is_jmp =3D DISAS_EXIT; diff --git a/target/avr/translate.c b/target/avr/translate.c index 4fa40b568a..ef2edd7415 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -29,7 +29,6 @@ #include "exec/helper-gen.h" #include "exec/log.h" #include "exec/translator.h" -#include "exec/gen-icount.h" =20 #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" diff --git a/target/cris/translate.c b/target/cris/translate.c index 3c21826cc2..1445cd8bb5 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -88,8 +88,6 @@ static TCGv env_btaken; static TCGv env_btarget; static TCGv env_pc; =20 -#include "exec/gen-icount.h" - /* This is the state at translation time. */ typedef struct DisasContext { DisasContextBase base; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 2c50fa72c3..d33813d173 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -364,8 +364,6 @@ static TCGv_reg cpu_psw_v; static TCGv_reg cpu_psw_cb; static TCGv_reg cpu_psw_cb_msb; =20 -#include "exec/gen-icount.h" - void hppa_translate_init(void) { #define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUHPPAState, V) } @@ -2090,8 +2088,7 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl = *a) /* FIXME: Respect PSW_S bit. */ nullify_over(ctx); tmp =3D dest_gpr(ctx, rt); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); + if (translator_io_start(&ctx->base)) { gen_helper_read_interval_timer(tmp); ctx->base.is_jmp =3D DISAS_IAQ_N_STALE; } else { diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index d509105505..5cf14311a6 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -78,8 +78,6 @@ static TCGv cpu_seg_base[6]; static TCGv_i64 cpu_bndl[4]; static TCGv_i64 cpu_bndu[4]; =20 -#include "exec/gen-icount.h" - typedef struct DisasContext { DisasContextBase base; =20 @@ -3933,10 +3931,7 @@ static bool disas_insn(DisasContext *s, CPUState *cp= u) !(s->cpuid_ext_features & CPUID_EXT_RDRAND)) { goto illegal_op; } - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - s->base.is_jmp =3D DISAS_TOO_MANY; - } + translator_io_start(&s->base); gen_helper_rdrand(s->T0, cpu_env); rm =3D (modrm & 7) | REX_B(s); gen_op_mov_reg_v(s, dflag, rm, s->T0); @@ -4974,10 +4969,7 @@ static bool disas_insn(DisasContext *s, CPUState *cp= u) SVM_IOIO_TYPE_MASK | SVM_IOIO_STR_MASK)) { break; } - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - s->base.is_jmp =3D DISAS_TOO_MANY; - } + translator_io_start(&s->base); if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { gen_repz_ins(s, ot); } else { @@ -4992,10 +4984,7 @@ static bool disas_insn(DisasContext *s, CPUState *cp= u) if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_STR_MASK)) { break; } - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - s->base.is_jmp =3D DISAS_TOO_MANY; - } + translator_io_start(&s->base); if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { gen_repz_outs(s, ot); } else { @@ -5014,10 +5003,7 @@ static bool disas_insn(DisasContext *s, CPUState *cp= u) if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_TYPE_MASK)) { break; } - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - s->base.is_jmp =3D DISAS_TOO_MANY; - } + translator_io_start(&s->base); gen_helper_in_func(ot, s->T1, s->tmp2_i32); gen_op_mov_reg_v(s, ot, R_EAX, s->T1); gen_bpt_io(s, s->tmp2_i32, ot); @@ -5030,10 +5016,7 @@ static bool disas_insn(DisasContext *s, CPUState *cp= u) if (!gen_check_io(s, ot, s->tmp2_i32, 0)) { break; } - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - s->base.is_jmp =3D DISAS_TOO_MANY; - } + translator_io_start(&s->base); gen_op_mov_v_reg(s, ot, s->T1, R_EAX); tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1); gen_helper_out_func(ot, s->tmp2_i32, s->tmp3_i32); @@ -5047,10 +5030,7 @@ static bool disas_insn(DisasContext *s, CPUState *cp= u) if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_TYPE_MASK)) { break; } - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - s->base.is_jmp =3D DISAS_TOO_MANY; - } + translator_io_start(&s->base); gen_helper_in_func(ot, s->T1, s->tmp2_i32); gen_op_mov_reg_v(s, ot, R_EAX, s->T1); gen_bpt_io(s, s->tmp2_i32, ot); @@ -5063,10 +5043,7 @@ static bool disas_insn(DisasContext *s, CPUState *cp= u) if (!gen_check_io(s, ot, s->tmp2_i32, 0)) { break; } - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - s->base.is_jmp =3D DISAS_TOO_MANY; - } + translator_io_start(&s->base); gen_op_mov_v_reg(s, ot, s->T1, R_EAX); tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1); gen_helper_out_func(ot, s->tmp2_i32, s->tmp3_i32); @@ -5674,10 +5651,7 @@ static bool disas_insn(DisasContext *s, CPUState *cp= u) case 0x131: /* rdtsc */ gen_update_cc_op(s); gen_update_eip_cur(s); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - s->base.is_jmp =3D DISAS_TOO_MANY; - } + translator_io_start(&s->base); gen_helper_rdtsc(cpu_env); break; case 0x133: /* rdpmc */ @@ -6133,10 +6107,7 @@ static bool disas_insn(DisasContext *s, CPUState *cp= u) } gen_update_cc_op(s); gen_update_eip_cur(s); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - s->base.is_jmp =3D DISAS_TOO_MANY; - } + translator_io_start(&s->base); gen_helper_rdtscp(cpu_env); break; =20 @@ -6490,10 +6461,7 @@ static bool disas_insn(DisasContext *s, CPUState *cp= u) } ot =3D (CODE64(s) ? MO_64 : MO_32); =20 - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - s->base.is_jmp =3D DISAS_TOO_MANY; - } + translator_io_start(&s->base); if (b & 2) { gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0 + reg); gen_op_mov_v_reg(s, ot, s->T0, rm); diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 67140ada56..1cf27a4611 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -24,8 +24,6 @@ TCGv cpu_gpr[32], cpu_pc; static TCGv cpu_lladdr, cpu_llval; =20 -#include "exec/gen-icount.h" - #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" #undef HELPER_H diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 90ca51fb9e..551ef9e52a 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -65,8 +65,6 @@ static TCGv NULL_QREG; /* Used to distinguish stores from bad addressing modes. */ static TCGv store_dummy; =20 -#include "exec/gen-icount.h" - void m68k_tcg_init(void) { char *p; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7a5d1066da..7e7f837c63 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -58,8 +58,6 @@ static TCGv_i32 cpu_iflags; static TCGv cpu_res_addr; static TCGv_i32 cpu_res_val; =20 -#include "exec/gen-icount.h" - /* This is the state at translation time. */ typedef struct DisasContext { DisasContextBase base; diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index bff1859b86..312ed66989 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1215,8 +1215,6 @@ static TCGv_i32 hflags; TCGv_i32 fpu_fcr0, fpu_fcr31; TCGv_i64 fpu_f64[32]; =20 -#include "exec/gen-icount.h" - static const char regnames_HI[][4] =3D { "HI0", "HI1", "HI2", "HI3", }; @@ -5670,9 +5668,8 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) switch (sel) { case CP0_REG09__COUNT: /* Mark as an IO operation because we read the time. */ - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); + gen_helper_mfc0_count(arg, cpu_env); /* * Break the TB to be able to take timer interrupts immediately @@ -6111,14 +6108,13 @@ cp0_unimplemented: static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) { const char *register_name =3D "invalid"; + bool icount; =20 if (sel !=3D 0) { check_insn(ctx, ISA_MIPS_R1); } =20 - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + icount =3D translator_io_start(&ctx->base); =20 switch (reg) { case CP0_REGISTER_00: @@ -6856,7 +6852,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) trace_mips_translate_c0("mtc0", register_name, reg, sel); =20 /* For simplicity assume that all writes can cause interrupts. */ - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + if (icount) { /* * DISAS_STOP isn't sufficient, we need to ensure we break out of * translated code to check for pending interrupts. @@ -7173,9 +7169,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) switch (sel) { case CP0_REG09__COUNT: /* Mark as an IO operation because we read the time. */ - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_mfc0_count(arg, cpu_env); /* * Break the TB to be able to take timer interrupts immediately @@ -7601,14 +7595,13 @@ cp0_unimplemented: static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) { const char *register_name =3D "invalid"; + bool icount; =20 if (sel !=3D 0) { check_insn(ctx, ISA_MIPS_R1); } =20 - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + icount =3D translator_io_start(&ctx->base); =20 switch (reg) { case CP0_REGISTER_00: @@ -8336,7 +8329,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) trace_mips_translate_c0("dmtc0", register_name, reg, sel); =20 /* For simplicity assume that all writes can cause interrupts. */ - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + if (icount) { /* * DISAS_STOP isn't sufficient, we need to ensure we break out of * translated code to check for pending interrupts. @@ -11147,9 +11140,7 @@ void gen_rdhwr(DisasContext *ctx, int rt, int rd, i= nt sel) gen_store_gpr(t0, rt); break; case 2: - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_rdhwr_cc(t0, cpu_env); gen_store_gpr(t0, rt); /* diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 28c1d700e1..a365ad8293 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -32,7 +32,6 @@ #include "exec/cpu_ldst.h" #include "exec/translator.h" #include "qemu/qemu-print.h" -#include "exec/gen-icount.h" #include "semihosting/semihost.h" =20 #define HELPER_H "helper.h" diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 06e6eae952..7760329e75 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -31,7 +31,6 @@ =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" -#include "exec/gen-icount.h" =20 #include "exec/log.h" =20 @@ -828,8 +827,7 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr= *a) =20 check_r0_write(dc, a->d); =20 - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); + if (translator_io_start(&dc->base)) { if (dc->delayed_branch) { tcg_gen_mov_tl(cpu_pc, jmp_pc); tcg_gen_discard_tl(jmp_pc); @@ -848,9 +846,8 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr= *a) { TCGv spr =3D tcg_temp_new(); =20 - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); + /* * For SR, we will need to exit the TB to recognize the new * exception state. For NPC, in theory this counts as a branch diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3df42dba4e..d02a781e29 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -80,8 +80,6 @@ static TCGv cpu_reserve_val2; static TCGv cpu_fpscr; static TCGv_i32 cpu_access_type; =20 -#include "exec/gen-icount.h" - void ppc_translate_init(void) { int i; @@ -300,16 +298,7 @@ static void gen_exception_nip(DisasContext *ctx, uint3= 2_t excp, =20 static void gen_icount_io_start(DisasContext *ctx) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - /* - * An I/O instruction must be last in the TB. - * Chain to the next TB, and let the code from gen_tb_start - * decide if we need to return to the main loop. - * Doing this first also allows this value to be overridden. - */ - ctx->base.is_jmp =3D DISAS_TOO_MANY; - } + translator_io_start(&ctx->base); } =20 #if !defined(CONFIG_USER_ONLY) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ed968162da..933b11c50d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -46,8 +46,6 @@ static TCGv load_val; static TCGv pm_mask; static TCGv pm_base; =20 -#include "exec/gen-icount.h" - /* * If an operation is being performed on less than TARGET_LONG_BITS, * it may require the inputs to be sign- or zero-extended; which will diff --git a/target/rx/translate.c b/target/rx/translate.c index 89dbec26f9..08cabbde61 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -73,8 +73,6 @@ static TCGv_i64 cpu_acc; =20 #define cpu_sp cpu_regs[0] =20 -#include "exec/gen-icount.h" - /* decoder helper */ static uint32_t decode_load_bytes(DisasContext *ctx, uint32_t insn, int i, int n) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 60b17585a7..7c549cd8d0 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -38,7 +38,6 @@ #include "qemu/log.h" #include "qemu/host-utils.h" #include "exec/cpu_ldst.h" -#include "exec/gen-icount.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" =20 @@ -6354,10 +6353,7 @@ static DisasJumpType translate_one(CPUS390XState *en= v, DisasContext *s) =20 /* input/output is the special case for icount mode */ if (unlikely(insn->flags & IF_IO)) { - icount =3D tb_cflags(s->base.tb) & CF_USE_ICOUNT; - if (icount) { - gen_io_start(); - } + icount =3D translator_io_start(&s->base); } } =20 diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 9d2c7a3337..efd889d9d3 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -75,8 +75,6 @@ static TCGv cpu_fregs[32]; /* internal register indexes */ static TCGv cpu_flags, cpu_delayed_pc, cpu_delayed_cond; =20 -#include "exec/gen-icount.h" - void sh4_translate_init(void) { int i; diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ebaf376500..bad2ec90a0 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -66,8 +66,6 @@ static TCGv cpu_wim; /* Floating point registers */ static TCGv_i64 cpu_fpr[TARGET_DPREGS]; =20 -#include "exec/gen-icount.h" - typedef struct DisasContext { DisasContextBase base; target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC = */ @@ -3217,16 +3215,12 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) r_const =3D tcg_constant_i32(dc->mem_idx); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, tick)); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); + if (translator_io_start(&dc->base)) { + dc->base.is_jmp =3D DISAS_EXIT; } gen_helper_tick_get_count(cpu_dst, cpu_env, r_tick= ptr, r_const); gen_store_gpr(dc, rd, cpu_dst); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - /* I/O operations in icount mode must end the = TB */ - dc->base.is_jmp =3D DISAS_EXIT; - } } break; case 0x5: /* V9 rdpc */ @@ -3269,16 +3263,12 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) r_const =3D tcg_constant_i32(dc->mem_idx); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, stick)); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); + if (translator_io_start(&dc->base)) { + dc->base.is_jmp =3D DISAS_EXIT; } gen_helper_tick_get_count(cpu_dst, cpu_env, r_tick= ptr, r_const); gen_store_gpr(dc, rd, cpu_dst); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - /* I/O operations in icount mode must end the = TB */ - dc->base.is_jmp =3D DISAS_EXIT; - } } break; case 0x19: /* System tick compare */ @@ -3399,15 +3389,11 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) r_const =3D tcg_constant_i32(dc->mem_idx); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, tick)); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); + if (translator_io_start(&dc->base)) { + dc->base.is_jmp =3D DISAS_EXIT; } gen_helper_tick_get_count(cpu_tmp0, cpu_env, r_tickptr, r_const); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - /* I/O operations in icount mode must end the = TB */ - dc->base.is_jmp =3D DISAS_EXIT; - } } break; case 5: // tba @@ -4212,10 +4198,7 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) r_tickptr =3D tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState,= tick)); - if (tb_cflags(dc->base.tb) & - CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_tick_set_limit(r_tickptr, cpu_tick_cmp= r); /* End TB to handle timer interrupt */ @@ -4235,10 +4218,7 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) r_tickptr =3D tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState,= stick)); - if (tb_cflags(dc->base.tb) & - CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_tick_set_count(r_tickptr, cpu_tmp0); /* End TB to handle timer interrupt */ @@ -4258,10 +4238,7 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) r_tickptr =3D tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState,= stick)); - if (tb_cflags(dc->base.tb) & - CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_tick_set_limit(r_tickptr, cpu_stick_cm= pr); /* End TB to handle timer interrupt */ @@ -4369,10 +4346,7 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) r_tickptr =3D tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState,= tick)); - if (tb_cflags(dc->base.tb) & - CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_tick_set_count(r_tickptr, cpu_tmp0); /* End TB to handle timer interrupt */ @@ -4384,14 +4358,10 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) break; case 6: // pstate save_state(dc); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT= ) { - gen_io_start(); - } - gen_helper_wrpstate(cpu_env, cpu_tmp0); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT= ) { - /* I/O ops in icount mode must end the= TB */ + if (translator_io_start(&dc->base)) { dc->base.is_jmp =3D DISAS_EXIT; } + gen_helper_wrpstate(cpu_env, cpu_tmp0); dc->npc =3D DYNAMIC_PC; break; case 7: // tl @@ -4401,14 +4371,10 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) dc->npc =3D DYNAMIC_PC; break; case 8: // pil - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT= ) { - gen_io_start(); - } - gen_helper_wrpil(cpu_env, cpu_tmp0); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT= ) { - /* I/O ops in icount mode must end the= TB */ + if (translator_io_start(&dc->base)) { dc->base.is_jmp =3D DISAS_EXIT; } + gen_helper_wrpil(cpu_env, cpu_tmp0); break; case 9: // cwp gen_helper_wrcwp(cpu_env, cpu_tmp0); @@ -4499,10 +4465,7 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) r_tickptr =3D tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState,= hstick)); - if (tb_cflags(dc->base.tb) & - CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_tick_set_limit(r_tickptr, cpu_hstick_c= mpr); /* End TB to handle timer interrupt */ @@ -5125,9 +5088,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) goto priv_insn; dc->npc =3D DYNAMIC_PC; dc->pc =3D DYNAMIC_PC; - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_done(cpu_env); goto jmp_insn; case 1: @@ -5135,9 +5096,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) goto priv_insn; dc->npc =3D DYNAMIC_PC; dc->pc =3D DYNAMIC_PC; - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_retry(cpu_env); goto jmp_insn; default: diff --git a/target/tricore/translate.c b/target/tricore/translate.c index eee935bbaf..8e4f99478c 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -55,8 +55,6 @@ static TCGv cpu_PSW_SV; static TCGv cpu_PSW_AV; static TCGv cpu_PSW_SAV; =20 -#include "exec/gen-icount.h" - static const char *regnames_a[] =3D { "a0" , "a1" , "a2" , "a3" , "a4" , "a5" , "a6" , "a7" , "a8" , "a9" , "sp" , "a11" , diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 11bb8c079b..b7386ff0f0 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -94,8 +94,6 @@ static TCGv_i32 cpu_exclusive_val; =20 static GHashTable *xtensa_regfile_table; =20 -#include "exec/gen-icount.h" - static char *sr_name[256]; static char *ur_name[256]; =20 @@ -577,9 +575,7 @@ static int gen_postprocess(DisasContext *dc, int slot) =20 #ifndef CONFIG_USER_ONLY if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) { - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_check_interrupts(cpu_env); } #endif @@ -2129,9 +2125,7 @@ static void translate_rsr_ccount(DisasContext *dc, co= nst OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_update_ccount(cpu_env); tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]); #endif @@ -2447,9 +2441,7 @@ static void translate_waiti(DisasContext *dc, const O= pcodeArg arg[], #ifndef CONFIG_USER_ONLY TCGv_i32 pc =3D tcg_constant_i32(dc->base.pc_next); =20 - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_waiti(cpu_env, pc, tcg_constant_i32(arg[0].imm)); #endif } @@ -2514,9 +2506,7 @@ static void translate_wsr_ccompare(DisasContext *dc, = const OpcodeArg arg[], uint32_t id =3D par[0] - CCOMPARE; =20 assert(id < dc->config->nccompare); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in); gen_helper_update_ccompare(cpu_env, tcg_constant_i32(id)); #endif @@ -2526,9 +2516,7 @@ static void translate_wsr_ccount(DisasContext *dc, co= nst OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_wsr_ccount(cpu_env, arg[0].in); #endif } @@ -2715,10 +2703,7 @@ static void translate_xsr_ccount(DisasContext *dc, c= onst OpcodeArg arg[], #ifndef CONFIG_USER_ONLY TCGv_i32 tmp =3D tcg_temp_new_i32(); =20 - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - + translator_io_start(&dc->base); gen_helper_update_ccount(cpu_env); tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); gen_helper_wsr_ccount(cpu_env, arg[0].in); diff --git a/MAINTAINERS b/MAINTAINERS index a1b99a31df..647288a86b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2861,7 +2861,6 @@ F: ui/cocoa.m Main loop M: Paolo Bonzini S: Maintained -F: include/exec/gen-icount.h F: include/qemu/main-loop.h F: include/sysemu/runstate.h F: include/sysemu/runstate-action.h diff --git a/target/loongarch/insn_trans/trans_extra.c.inc b/target/loongar= ch/insn_trans/trans_extra.c.inc index ad713cd61e..06f4de4515 100644 --- a/target/loongarch/insn_trans/trans_extra.c.inc +++ b/target/loongarch/insn_trans/trans_extra.c.inc @@ -39,9 +39,7 @@ static bool gen_rdtime(DisasContext *ctx, arg_rr *a, TCGv dst1 =3D gpr_dst(ctx, a->rd, EXT_NONE); TCGv dst2 =3D gpr_dst(ctx, a->rj, EXT_NONE); =20 - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_rdtime_d(dst1, cpu_env); if (word) { tcg_gen_sextract_tl(dst1, dst1, high ? 32 : 0, 32); diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/lo= ongarch/insn_trans/trans_privileged.c.inc index 5a04352b01..02bca7ca23 100644 --- a/target/loongarch/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/insn_trans/trans_privileged.c.inc @@ -185,9 +185,7 @@ static bool check_csr_flags(DisasContext *ctx, const CS= RInfo *csr, bool write) if ((csr->flags & CSRFL_READONLY) && write) { return false; } - if ((csr->flags & CSRFL_IO) && - (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT)) { - gen_io_start(); + if ((csr->flags & CSRFL_IO) && translator_io_start(&ctx->base)) { ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; } else if ((csr->flags & CSRFL_EXITTB) && write) { ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index 7c2837194c..528baa1652 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -77,9 +77,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) #ifndef CONFIG_USER_ONLY if (has_ext(ctx, RVS)) { decode_save_opc(ctx); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_sret(cpu_pc, cpu_env); exit_tb(ctx); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; @@ -96,9 +94,7 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY decode_save_opc(ctx); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_mret(cpu_pc, cpu_env); exit_tb(ctx); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index c70c495fc5..2031e9931e 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -813,9 +813,7 @@ static bool do_csrr(DisasContext *ctx, int rd, int rc) TCGv dest =3D dest_gpr(ctx, rd); TCGv_i32 csr =3D tcg_constant_i32(rc); =20 - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_csrr(dest, cpu_env, csr); gen_set_gpr(ctx, rd, dest); return do_csr_post(ctx); @@ -825,9 +823,7 @@ static bool do_csrw(DisasContext *ctx, int rc, TCGv src) { TCGv_i32 csr =3D tcg_constant_i32(rc); =20 - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_csrw(cpu_env, csr, src); return do_csr_post(ctx); } @@ -837,9 +833,7 @@ static bool do_csrrw(DisasContext *ctx, int rd, int rc,= TCGv src, TCGv mask) TCGv dest =3D dest_gpr(ctx, rd); TCGv_i32 csr =3D tcg_constant_i32(rc); =20 - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_csrrw(dest, cpu_env, csr, src, mask); gen_set_gpr(ctx, rd, dest); return do_csr_post(ctx); @@ -851,9 +845,7 @@ static bool do_csrr_i128(DisasContext *ctx, int rd, int= rc) TCGv desth =3D dest_gprh(ctx, rd); TCGv_i32 csr =3D tcg_constant_i32(rc); =20 - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_csrr_i128(destl, cpu_env, csr); tcg_gen_ld_tl(desth, cpu_env, offsetof(CPURISCVState, retxh)); gen_set_gpr128(ctx, rd, destl, desth); @@ -864,9 +856,7 @@ static bool do_csrw_i128(DisasContext *ctx, int rc, TCG= v srcl, TCGv srch) { TCGv_i32 csr =3D tcg_constant_i32(rc); =20 - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_csrw_i128(cpu_env, csr, srcl, srch); return do_csr_post(ctx); } @@ -878,9 +868,7 @@ static bool do_csrrw_i128(DisasContext *ctx, int rd, in= t rc, TCGv desth =3D dest_gprh(ctx, rd); TCGv_i32 csr =3D tcg_constant_i32(rc); =20 - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_csrrw_i128(destl, cpu_env, csr, srcl, srch, maskl, maskh); tcg_gen_ld_tl(desth, cpu_env, offsetof(CPURISCVState, retxh)); gen_set_gpr128(ctx, rd, destl, desth); --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850036; x=1687442036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=v5+X8dtE6LfSMMjI2gnNlBbQTFJOMR9qw0ZxeW19zPE=; b=GXFj6UcZMGR+KV/DlZBqEsMGxJSTa8FyC0Q7WbHOl6WoIYDP/0RCJw5XiOCpeuxyMa PKZGjGFVVn7Eg4Fky+VbsTCecjPxX2hbHo/ZZj65X6y3f2skqsrBSpTMnOjR3FuR8W+g VCtaEhvZiE2h0xvZqQgov5tUlCuu1ixZ6jua+eIXvuYbuZJJQNdImdoEvXlTSp/EiOg4 PLgfFFODjNjLnDgSeLiou7U6/g9SpWqLfYzxcl3L0srXvPmKt1rY4WfjZg8zS8Ahu94f 15OIqDSM388d5HoY0NGFVSenYjptnTUgzyMMi3AP/txKSjUaa2NpjCxFPpcpAsfnVKjo NtkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850036; x=1687442036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v5+X8dtE6LfSMMjI2gnNlBbQTFJOMR9qw0ZxeW19zPE=; b=f5QfqZEVuWhp43RYpnhLWrCLRHMNKrGjtnAvAnte+W0egDBKtUHseyK10U9Yybli4j JO7IV5KS8lpaF1bnub3EYI9CLahvQKsgSEPc9OOToHpBZdywMjF0+RakrUXamsKFHhev gi09a0Dd3cNJjZJ2eSljQHEhYf44p4HiapWnazdZ8aKUvyC88WC/H+gZwHsfOWTUZuVd Izwrhmkkw35zFADta5JF/1dakWB5F/CKnS3iBB0t8Hh68Kd1VFo/RFLKKBLhat3cfrCu HkNLVCirXUnU+oMp5/+NszEzWXQAZcV8wrItuiqrER9GjHkjw/gK3N2huMJn/bqkFdVP eDPg== X-Gm-Message-State: AC+VfDzJ4Xih893yOaC76mx53BDW9FyLTaSQPmYf88Q0qfqL5JL6HL4O 6QbH2UAMP4yDpjR9OD97KzFKuH0nhuab6nOSi08= X-Google-Smtp-Source: ACHHUZ7up5OrB2k2f71H/sWNQfczo3LuNteiaghh6GGR1JXofE/8Dejlw278yWR8EvKoC9WvrJeZtg== X-Received: by 2002:a05:6a00:2282:b0:63f:18ae:1d5f with SMTP id f2-20020a056a00228200b0063f18ae1d5fmr20543890pfe.29.1684850035887; Tue, 23 May 2023 06:53:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 39/52] accel/tcg: Move translator_fake_ldb out of line Date: Tue, 23 May 2023 06:53:09 -0700 Message-Id: <20230523135322.678948-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684853515956100003 Content-Type: text/plain; charset="utf-8" This is used by exactly one host in extraordinary circumstances. This means that translator.h need not include plugin-gen.h; translator.c already includes plugin-gen.h. Signed-off-by: Richard Henderson --- include/exec/translator.h | 8 +------- accel/tcg/translator.c | 5 +++++ 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index c1a1203789..228002a623 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -22,7 +22,6 @@ #include "qemu/bswap.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" -#include "exec/plugin-gen.h" #include "exec/translate-all.h" #include "tcg/tcg.h" =20 @@ -229,12 +228,7 @@ translator_ldq_swap(CPUArchState *env, DisasContextBas= e *db, * re-synthesised for s390x "ex"). It ensures we update other areas of * the translator with details of the executed instruction. */ - -static inline void translator_fake_ldb(uint8_t insn8, abi_ptr pc) -{ - plugin_insn_append(pc, &insn8, sizeof(insn8)); -} - +void translator_fake_ldb(uint8_t insn8, abi_ptr pc); =20 /* * Return whether addr is on the same page as where disassembly started. diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 7a130e706e..60a613c99d 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -345,3 +345,8 @@ uint64_t translator_ldq(CPUArchState *env, DisasContext= Base *db, abi_ptr pc) plugin_insn_append(pc, &plug, sizeof(ret)); return ret; } + +void translator_fake_ldb(uint8_t insn8, abi_ptr pc) +{ + plugin_insn_append(pc, &insn8, sizeof(insn8)); +} --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851237; cv=none; d=zohomail.com; s=zohoarc; b=DCaEM9LyR6+lejoUFEg0sHnBqU+grRDqLA8UrOYT2HLQyf6r3Gh+YiXkPRok2NE8TyMwoY9rmFoNjiGadnK6nUdvGVE8fY88onJmxMiTY1OMgqhHBHRQsW26d4fvfJn37RC8fsRMnVVh5Y7hB4yVYQX+RQSp+dH6ToVjMCdPfnk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851237; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yWrZGJGhJkGS/jT+aD3SdArCyOPdyMfFotilTaL2dRI=; b=ehEe+SU57XGAjMIBftbjrnS6n2yr72GnoBL98ixxHMWvxnxIVe7lrakrSrHyK7Ns6rWwMyakTP2RtvOmsl9KmDZ/6OY9X6AKx1SWi/BY0h4rQ8ytXitmqZcXaXUnCnkeLa7dcM8xTkJpj3oUYaiAmmumTbQ88Idw3TzWUc4ra+c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684851237960532.2330796718801; Tue, 23 May 2023 07:13:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SVf-0003GY-2R; Tue, 23 May 2023 09:57:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SVY-00036f-P4 for qemu-devel@nongnu.org; Tue, 23 May 2023 09:57:02 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SVW-0004BN-N6 for qemu-devel@nongnu.org; Tue, 23 May 2023 09:57:00 -0400 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-64f47448aeaso363641b3a.0 for ; Tue, 23 May 2023 06:56:58 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id v11-20020a62a50b000000b0063799398eaesm5805790pfm.51.2023.05.23.06.56.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:56:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850217; x=1687442217; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=yWrZGJGhJkGS/jT+aD3SdArCyOPdyMfFotilTaL2dRI=; b=LJBXY/2O+DxopgPZNK/s+cO/KW1lufkO6rmnj9ULvao5Gtbg6FMcC7iEoxpkP/ZlM1 TdP0kNR3MKcFil6j6UmEnQlb8rS9ge+tLWO62ZmF05Ed08x3inAoKW2yz3cXde2H529B B8l4Y1joEe8nMWGqweyy/vWYibyU2WJp4BlR2WA7jQx9G1FFC2IQi9jcuP9QVofGHchr wS0v0+ADVx7jGVtJ3JwjbS3GaoEd/RDfGLm7hf362xfk4vIrgYAXDjjZI+nVoP5BCaV1 sQpilPpsv4rlSSbvqX+iCstNz45O/5L8q+BQa/E3xtSeRFiayn32H9/f4BpdTJe9hJ9Z C98w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850217; x=1687442217; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yWrZGJGhJkGS/jT+aD3SdArCyOPdyMfFotilTaL2dRI=; b=TJnarG0mumr0tez4OWMdOzIkg+8XQJ6kXdNixcR/VeSVRGwCbReWMYP3tKhYNYu/g5 8F4o6wKOLA3k5YgLYSgBx7ghy58eIg6U5REKxz1cNqfg4AuMKy0sfOBf8tjKDC6/PqLa 93AEdM+O5D2+IJFz/A38mXVrSEOzgIuFHCdWlgC1MxI5+spOqEbFvQgbl3TL0KKSI6uc OJ2o+Yp5azMb/J4J1vxEAeKAke2WNbya/2/j3wzYABYtBBPqWlqJx1FNtdjfrAtEfo2O HhyRREZsEnOrOvivxeJOX7P1BGO8/UFtH+nGOo0U5WMsnF8UNQmhmx38jYsbXyGbB0Q3 4kMg== X-Gm-Message-State: AC+VfDwYuYXwvIZy6UW/BrwoeAqiE+hN8mDE0RdaVDwYiQ18XQZGrQ1c bzUtd75C4gX1txzR7unV77AmhfKhK89aBm4leHg= X-Google-Smtp-Source: ACHHUZ5XYT9lHmQzZUwwnZ5Ar3ny+ytkrq9vSPE46BQukudVFoQb/OmKCb4DqlZ6W467kmjqbh3HpA== X-Received: by 2002:a05:6a00:1a15:b0:638:7e00:3737 with SMTP id g21-20020a056a001a1500b006387e003737mr16186906pfv.23.1684850217091; Tue, 23 May 2023 06:56:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 40/52] target/arm: Tidy helpers for translation Date: Tue, 23 May 2023 06:53:10 -0700 Message-Id: <20230523135322.678948-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851238736100001 Content-Type: text/plain; charset="utf-8" Move most includes from *translate*.c to translate.h, ensuring that we get the ordering correct. Ensure cpu.h is first. Use disas/disas.h instead of exec/log.h. Drop otherwise unused includes. Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 3 +++ target/arm/tcg/translate-a64.c | 17 +++++------------ target/arm/tcg/translate-m-nocp.c | 2 -- target/arm/tcg/translate-mve.c | 3 --- target/arm/tcg/translate-neon.c | 3 --- target/arm/tcg/translate-sme.c | 6 ------ target/arm/tcg/translate-sve.c | 9 --------- target/arm/tcg/translate-vfp.c | 3 --- target/arm/tcg/translate.c | 17 +++++------------ 9 files changed, 13 insertions(+), 50 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 868a3abd0d..5b53b6215d 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -1,6 +1,9 @@ #ifndef TARGET_ARM_TRANSLATE_H #define TARGET_ARM_TRANSLATE_H =20 +#include "cpu.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" #include "exec/translator.h" #include "exec/helper-gen.h" #include "internals.h" diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 8d45dbf8fc..d9800337cf 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -18,20 +18,13 @@ */ #include "qemu/osdep.h" =20 -#include "cpu.h" -#include "exec/exec-all.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "qemu/log.h" -#include "arm_ldst.h" #include "translate.h" -#include "internals.h" -#include "qemu/host-utils.h" -#include "semihosting/semihost.h" -#include "exec/log.h" -#include "cpregs.h" #include "translate-a64.h" -#include "qemu/atomic128.h" +#include "qemu/log.h" +#include "disas/disas.h" +#include "arm_ldst.h" +#include "semihosting/semihost.h" +#include "cpregs.h" =20 static TCGv_i64 cpu_X[32]; static TCGv_i64 cpu_pc; diff --git a/target/arm/tcg/translate-m-nocp.c b/target/arm/tcg/translate-m= -nocp.c index 9a89aab785..33f6478bb9 100644 --- a/target/arm/tcg/translate-m-nocp.c +++ b/target/arm/tcg/translate-m-nocp.c @@ -18,8 +18,6 @@ */ =20 #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" #include "translate.h" #include "translate-a32.h" =20 diff --git a/target/arm/tcg/translate-mve.c b/target/arm/tcg/translate-mve.c index 2ad3c40975..bbc7b3f4ce 100644 --- a/target/arm/tcg/translate-mve.c +++ b/target/arm/tcg/translate-mve.c @@ -18,9 +18,6 @@ */ =20 #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "exec/exec-all.h" #include "translate.h" #include "translate-a32.h" =20 diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neo= n.c index 6fac577abd..03913de047 100644 --- a/target/arm/tcg/translate-neon.c +++ b/target/arm/tcg/translate-neon.c @@ -21,9 +21,6 @@ */ =20 #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "exec/exec-all.h" #include "translate.h" #include "translate-a32.h" =20 diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index b0812d9dd6..d0054e3f77 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -18,14 +18,8 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "tcg/tcg-gvec-desc.h" #include "translate.h" #include "translate-a64.h" -#include "fpu/softfloat.h" - =20 /* * Include the generated decoder. diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 106baf311f..d9d5810dde 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -18,16 +18,7 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" -#include "exec/exec-all.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "tcg/tcg-gvec-desc.h" -#include "qemu/log.h" -#include "arm_ldst.h" #include "translate.h" -#include "internals.h" -#include "exec/log.h" #include "translate-a64.h" #include "fpu/softfloat.h" =20 diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index 95ac8d9db3..359b1e3e96 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -21,9 +21,6 @@ */ =20 #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "exec/exec-all.h" #include "translate.h" #include "translate-a32.h" =20 diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 7caf6d802d..a68d3c7f6d 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -20,20 +20,13 @@ */ #include "qemu/osdep.h" =20 -#include "cpu.h" -#include "internals.h" -#include "disas/disas.h" -#include "exec/exec-all.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "qemu/log.h" -#include "qemu/bitops.h" -#include "arm_ldst.h" -#include "semihosting/semihost.h" -#include "exec/log.h" -#include "cpregs.h" #include "translate.h" #include "translate-a32.h" +#include "qemu/log.h" +#include "disas/disas.h" +#include "arm_ldst.h" +#include "semihosting/semihost.h" +#include "cpregs.h" #include "exec/helper-proto.h" =20 #define HELPER_H "helper.h" --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id v11-20020a62a50b000000b0063799398eaesm5805790pfm.51.2023.05.23.06.56.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:56:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850218; x=1687442218; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=jIBJg2lmoN4SFecYrI5sb6VaAgGxZyVvAyGpaJ4I0ws=; b=o2yABc5bQOXdy8Kx1nSLrZCHG+6VludoGRQFpCX1KoUcG/sjdbUhMFBn3gdGESZYjT mX8YWbaG+m3/2Bi1KHMMOrWKGakrXEhLeEoK2knjAci799+vpCQqjw5t2yLS1sQBq+sI 1VmyHpXlVMxT8yhmD/kXNTMwLgoPzHwyazQ/ADqI2ldnrmLVVvyZI587242dsTMNOU1O dOXTdrq0Vn2k0imk8jyKCTl3U0QjnL/cZLjg9vsyaQGmfoYkAgwe5G7sGVnxbMmKTQlK tnC20JOyROX4KFtYxU3GeWK2H6B30OYO9DLVBw3IQarg8CsAVcKgJf4T2vIJyyxcEane QkUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850218; x=1687442218; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jIBJg2lmoN4SFecYrI5sb6VaAgGxZyVvAyGpaJ4I0ws=; b=Gdu96RDvrXlj8Vfk0xvdBL//34FCCMGm10GN35oxo973upXDKMeXmvOQ/2ep+f6+Nc BUODAIPOTGTHmBSfNYOTFQ2q2XL6qJYj/y/ZPJiOjXskMAQOqmNS9cMD+7m3c1MRyqdp jRah/GpbAR1uw5tTGhTEIPDBrGw1q0aHswxzXSbNYAAIARXTYgzs5zYX8dY4XK/uqaUk lh+e7QHQjCn1tq+FzjQAOKH5uSg8ajwx0d+/11x9VCzpxgLluCSZH2rt7U2yKUdO+2Og 8lGxiyGx6+WohoEcqaDwAMybTaev+T1m3tYO61Hsy+YKFuhmvObF1wrAhGLrdJMZVW3u pboQ== X-Gm-Message-State: AC+VfDz8TO3A7IZClfyy6LN52Kp1ukFC0gXYcynK/NTVAll0DgrXh5Ji ha7HBdaunrD1wZjNgYuIxSguvGWDA/9f+pRJfAM= X-Google-Smtp-Source: ACHHUZ5plF4ERR373wIaL4fLb8jg7e04iBwdWgt5D/TWDarWXZJQXWiDcWxlRz4PLpThe+vEgKB97g== X-Received: by 2002:a05:6a00:1486:b0:645:d02d:9a83 with SMTP id v6-20020a056a00148600b00645d02d9a83mr20047104pfu.17.1684850217886; Tue, 23 May 2023 06:56:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 41/52] target/mips: Tidy helpers for translation Date: Tue, 23 May 2023 06:53:11 -0700 Message-Id: <20230523135322.678948-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684852693216100005 Content-Type: text/plain; charset="utf-8" Move most includes from *translate*.c to translate.h, ensuring that we get the ordering correct. Ensure cpu.h is first. Use disas/disas.h instead of exec/log.h. Drop otherwise unused includes. Signed-off-by: Richard Henderson --- target/mips/tcg/translate.h | 6 ++++-- target/mips/tcg/msa_translate.c | 3 --- target/mips/tcg/mxu_translate.c | 2 -- target/mips/tcg/octeon_translate.c | 4 +--- target/mips/tcg/rel6_translate.c | 2 -- target/mips/tcg/translate.c | 18 ++++++------------ target/mips/tcg/translate_addr_const.c | 1 - target/mips/tcg/tx79_translate.c | 4 +--- target/mips/tcg/vr54xx_translate.c | 3 --- 9 files changed, 12 insertions(+), 31 deletions(-) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index fa8bf55209..3b0498a47a 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -8,9 +8,11 @@ #ifndef TARGET_MIPS_TRANSLATE_H #define TARGET_MIPS_TRANSLATE_H =20 -#include "qemu/log.h" -#include "exec/translator.h" +#include "cpu.h" #include "tcg/tcg-op.h" +#include "exec/translator.h" +#include "exec/helper-gen.h" +#include "qemu/log.h" =20 #define MIPS_DEBUG_DISAS 0 =20 diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 220cd3b048..b5b66fb38a 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -11,11 +11,8 @@ * SPDX-License-Identifier: LGPL-2.1-or-later */ #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "exec/helper-gen.h" #include "translate.h" #include "fpu_helper.h" -#include "internal.h" =20 static int elm_n(DisasContext *ctx, int x); static int elm_df(DisasContext *ctx, int x); diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translat= e.c index be038b5f07..39348b3a91 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -16,8 +16,6 @@ */ =20 #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "exec/helper-gen.h" #include "translate.h" =20 /* diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_tr= anslate.c index 103c304d10..e25c4cbaa0 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -7,10 +7,8 @@ */ =20 #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "exec/helper-gen.h" #include "translate.h" +#include "tcg/tcg-op-gvec.h" =20 /* Include the auto-generated decoder. */ #include "decode-octeon.c.inc" diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_transl= ate.c index d631851258..59f237ba3b 100644 --- a/target/mips/tcg/rel6_translate.c +++ b/target/mips/tcg/rel6_translate.c @@ -9,8 +9,6 @@ */ =20 #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "exec/helper-gen.h" #include "translate.h" =20 /* Include the auto-generated decoders. */ diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 312ed66989..f3da05ba3b 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -23,19 +23,13 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" -#include "internal.h" -#include "tcg/tcg-op.h" -#include "exec/translator.h" -#include "exec/helper-proto.h" -#include "exec/helper-gen.h" -#include "semihosting/semihost.h" - -#include "trace.h" -#include "exec/log.h" -#include "qemu/qemu-print.h" -#include "fpu_helper.h" #include "translate.h" +#include "internal.h" +#include "exec/helper-proto.h" +#include "semihosting/semihost.h" +#include "trace.h" +#include "disas/disas.h" +#include "fpu_helper.h" =20 #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" diff --git a/target/mips/tcg/translate_addr_const.c b/target/mips/tcg/trans= late_addr_const.c index a510da406c..6f4b39f715 100644 --- a/target/mips/tcg/translate_addr_const.c +++ b/target/mips/tcg/translate_addr_const.c @@ -11,7 +11,6 @@ * SPDX-License-Identifier: LGPL-2.1-or-later */ #include "qemu/osdep.h" -#include "tcg/tcg-op.h" #include "translate.h" =20 bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa) diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_transl= ate.c index 3a45a1bfea..dd6fb8a7bd 100644 --- a/target/mips/tcg/tx79_translate.c +++ b/target/mips/tcg/tx79_translate.c @@ -8,10 +8,8 @@ */ =20 #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "exec/helper-gen.h" #include "translate.h" +#include "tcg/tcg-op-gvec.h" =20 /* Include the auto-generated decoder. */ #include "decode-tx79.c.inc" diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_tr= anslate.c index 804672f84c..2c1f6cc527 100644 --- a/target/mips/tcg/vr54xx_translate.c +++ b/target/mips/tcg/vr54xx_translate.c @@ -10,10 +10,7 @@ */ =20 #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "exec/helper-gen.h" #include "translate.h" -#include "internal.h" =20 /* Include the auto-generated decoder. */ #include "decode-vr54xx.c.inc" --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id v11-20020a62a50b000000b0063799398eaesm5805790pfm.51.2023.05.23.06.56.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:56:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850218; x=1687442218; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=gIw13ktYRKuHjGYgqanTyY2L+IU7oi03A0ph96rfnSk=; b=DnPhdf1D+iWjK1y0vhfVlKethFneI8pvrIrE3xCjHnNmtJJTzH8v1bLdbsEe4LdbIG uX4YnHm/TtTRHL6t9kEMCmVWuQO74Qjjqz3nPzE6viuKPq0tEsVEa6wr9CLj/y7zYFLD lPXtyDi2FOhsSr58iSLgbEDBSv1kOIHZSrvZKrsSCAWyt7anRPCfqrBYBxQe42C0zUa9 ZmjwdBLMVwXGaKeqo0E1RelvznZ5lSYaohlLocvoPJyhlb4xjWN0MG1Er0FwhylSWXPm 0KxSO7QV/vjRXWcNwjSpBdVotW6DgVoRjvaKLl4y6TTTKhdBB11rvZIAAGYNN7J/mjAz vmXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850218; x=1687442218; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gIw13ktYRKuHjGYgqanTyY2L+IU7oi03A0ph96rfnSk=; b=TtQTnd+tmVb1LpALCFzlSGICAUJ3lfIuQgDkHPa+lDgMMGHucI/uwAMjibH1EYbHO7 8mmiP8vd7aHnnO2Q6TgJeVoCe1xfP5ADuDG6/PFmmiybaw7EjtQBhF+TADkVPxt3ODXQ Xf5uRuX8vpiHrnWBtQeUuF44R2aQ7kAMFW7hOyLyrRdvc7WSllY+9y1D1ZydGakcHb4d IphoirRtfNJJbo+7H4HKIjBI7n9VTFy82ObJrZ8NaEb1+i4ya3b6LISBQzheV8mW3boB e2E1RV/hctTsgjXHNlyMij7oA/RG6SdhlJX/dvH/hcXhOilxdVgxQ8GCtH80LgfDHJ/M fDfQ== X-Gm-Message-State: AC+VfDwlEweAyNOqmrxRG6Do7Y2hJtLmwpsCL0uD7OCkqF6Uv5yNfl4j A9KSDUGB2AA4MbgeKdsT1+xzAVYNTqeypQcpYn4= X-Google-Smtp-Source: ACHHUZ72oTMtrWEs7fHZKMvjMEw9tFgAphAo/Nf/J9+BAYGQZ9+7V3RBG6/kyiHGsFqw1LqsaUy9ig== X-Received: by 2002:a05:6a00:1788:b0:636:e52f:631e with SMTP id s8-20020a056a00178800b00636e52f631emr19960416pfg.1.1684850218746; Tue, 23 May 2023 06:56:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 42/52] *: Add missing includes of exec/translation-block.h Date: Tue, 23 May 2023 06:53:12 -0700 Message-Id: <20230523135322.678948-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851383730100001 Content-Type: text/plain; charset="utf-8" This had been pulled in via exec/exec-all.h, via exec/translator.h, but the include of exec-all.h will be removed. Signed-off-by: Richard Henderson --- target/hexagon/translate.c | 1 + target/loongarch/translate.c | 3 +-- target/mips/tcg/translate.c | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index eda384a9db..16cdfcc2bd 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -22,6 +22,7 @@ #include "tcg/tcg-op-gvec.h" #include "exec/helper-gen.h" #include "exec/helper-proto.h" +#include "exec/translation-block.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "internal.h" diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 1cf27a4611..3146a2d4ac 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -9,11 +9,10 @@ #include "cpu.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" - +#include "exec/translation-block.h" #include "exec/translator.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" - #include "exec/log.h" #include "qemu/qemu-print.h" #include "fpu/softfloat.h" diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index f3da05ba3b..74af91e4f5 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -26,6 +26,7 @@ #include "translate.h" #include "internal.h" #include "exec/helper-proto.h" +#include "exec/translation-block.h" #include "semihosting/semihost.h" #include "trace.h" #include "disas/disas.h" --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851437; cv=none; d=zohomail.com; s=zohoarc; b=O+Lhg1GHuyJC3fvNumG4IaAfhhfB3nSeagPBQqV1nu8P4CThXWnlQ/Vr1Ymunw6Kasw5tv7JIfoIvGrBoMlYF9XX8bLkwDkK4/ue7aaVqAj2AW9smpgn0URjTEqRNHu9uKU+rV6IlYy7nsCZ7yiStV/F5R+1P9pU392sfbtyEek= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851437; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5OmjOrE/P0VU5UgUG9OCCxhc4dLq9WZZ40K8T/sgGq8=; b=Q7lntT7sIG8ifu7gKUC7nXQWHkZ4/hO2DjOt1YDNK3FMhq3C1sCmCcZpsV333Ywkm9R1qtQZavnTkVa+NHNoya/VngX6MxU08L6PzAcV3iYU2bOjfsFXpBOIUbdV0/G35966Yf7tbHb7C4/dBw7o7ZyIks048EQzlqQEeilU3ZM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684851437262893.1887242626094; Tue, 23 May 2023 07:17:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SVe-0003FP-AY; Tue, 23 May 2023 09:57:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SVb-0003Ap-IM for qemu-devel@nongnu.org; Tue, 23 May 2023 09:57:03 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SVY-0004C2-Q9 for qemu-devel@nongnu.org; Tue, 23 May 2023 09:57:03 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-64d3fbb8c1cso4747716b3a.3 for ; Tue, 23 May 2023 06:57:00 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id v11-20020a62a50b000000b0063799398eaesm5805790pfm.51.2023.05.23.06.56.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:56:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850219; x=1687442219; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=5OmjOrE/P0VU5UgUG9OCCxhc4dLq9WZZ40K8T/sgGq8=; b=ncImANGMt9TB30AnijYfbmCyyodwfC3hQwqkzYfOHjyF2327TEBgBlwB9Gtutgf8i5 afZ3saKly3Xq+USoyASyEN2k3zNbPJb1B4StRNqdw/FKGZRqfZHF4fHX5uFFvhorclBt AfxJkH+aL//g5BkxF9thr7Onfi+5KnI2eV9R85QuGnZOUpFalB5UgOT2G41yXXAhF5WP 3NrXDnaOVZjp6Z5I2LGJ1Mnz3RRt8ljwIRyb2Cj2g8Ga4Fw2KjZHjJKXt1e3RjncHb7C 3lsz0oQ4hfC1phJklVTLpeLSs2RwbWZWtQnD7XxOmlXelSIAnImmwqqn1OCDlIu5ciIG r3xQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850219; x=1687442219; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5OmjOrE/P0VU5UgUG9OCCxhc4dLq9WZZ40K8T/sgGq8=; b=V5ocvLHwTXZkexsBAfbCVi3XSQUIdaKoiH3PXa0iG4cOQ61hriFlM03AUYERe/NpYB pKOP/nkPCf6twhtbZCt31fNScpLaaR+vZAZsX7YVmWEA7XJTFuVZtXK/lFQp0/HvmJZ1 qiKRJnG7j3LzdO3ZojtPXLRQ5Iz7bUHkZlAIH6Ttx0CGuKbwBrtdsXP7GE3c3ZxL7sNy XzOeooAZv1EL5W63LyYl6dq8+G5me3OoJimaHjKe3EVNM3Vi41B38fxYBJ6C87aQGXs4 8GApR9a4cjOVLbThHGtvExz5pDe0MHojViwTjVwzlsqMvFXeU5IdxHFAmtQhsm6xtTKS 4otA== X-Gm-Message-State: AC+VfDwZM5LpUAagaNaG1Ix2DYwHyDMWJ5a4DHHUl0q4Hb2OLExc3V/9 NaXdXvZ+fZsO9xBCzNhn0E3w1QHop2O55ncCpEs= X-Google-Smtp-Source: ACHHUZ7pmu0Zp1G8oZwwabO6GAweM3SV5KN3TGn0qA+nhmh4L1Z97HF0/61whLETzIS8RykSbz32Eg== X-Received: by 2002:a05:6a00:14c4:b0:643:9cc0:a3be with SMTP id w4-20020a056a0014c400b006439cc0a3bemr17506050pfu.5.1684850219394; Tue, 23 May 2023 06:56:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 43/52] *: Add missing includes of exec/exec-all.h Date: Tue, 23 May 2023 06:53:13 -0700 Message-Id: <20230523135322.678948-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851438980100005 Content-Type: text/plain; charset="utf-8" This had been pulled in via exec/translator.h, but the include of exec-all.h will be removed. Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 5b53b6215d..4d88197715 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -4,6 +4,7 @@ #include "cpu.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" +#include "exec/exec-all.h" #include "exec/translator.h" #include "exec/helper-gen.h" #include "internals.h" --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851386; cv=none; d=zohomail.com; s=zohoarc; b=V5RitzZAeytgxIasTEIiMRnvi55pBZb+MWnd4LflmAiPgTz+OcKHDdTayCsBdfFCGJaAuCU97lggvyIlZETob0zvCXai7Hmhj2bDm6ECmpl63MxlAKHK8PHzsLS8YvrdHPPsGJBZApgWFM4C85Ir4BB+YZ7H6xYj4zdquJzXGmM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851386; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yAI6VIgzMZpgJduQw+zbfBfSRhC2iaxfwnzVojWouK0=; b=UIUuKnIXz3UXGdmZ6yOFLEw/bjbzSqra/D6+h1Eap+0vZMAqkQQAk0HaqHX/M1x70Y1MkDIsJzV09BeDjYq2e+5HoBaY+XyTxOf4XO1vRZOibVb0kj/3RM3IV/pBVnqg0yaY3msovO9WcoqvOpKmdlZ8dBWyl8TskQHvPVTAPsw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684851386258242.4989311381554; Tue, 23 May 2023 07:16:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SVs-0003lI-6J; Tue, 23 May 2023 09:57:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SVl-0003UE-Ip for qemu-devel@nongnu.org; Tue, 23 May 2023 09:57:13 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SVa-0004CF-0h for qemu-devel@nongnu.org; Tue, 23 May 2023 09:57:12 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-64d41763796so2907226b3a.2 for ; Tue, 23 May 2023 06:57:01 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id v11-20020a62a50b000000b0063799398eaesm5805790pfm.51.2023.05.23.06.56.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:56:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850220; x=1687442220; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=yAI6VIgzMZpgJduQw+zbfBfSRhC2iaxfwnzVojWouK0=; b=X3NDGYHP/J5DtEHxOb5/zazcfj6L/Cmdjw0d7wiaB0y6t69KHI9wJJaTVPi2Ux+BLI zS1kY6EzUGQVjOIHXEMugHifwTsoObcIKDgFr1ZSD3OaNaj3g19oomRpBfwRXMZCivhv 4ckxZVouExW/3B1Vpgz2OKZ9gIBbPckObq+efq4RPFF5OB2epCuTgv+fMKEm+7U4Xzgm pGiFesDNz8wYF0F36t0KSUsRBTwSjtVH3lXjrXRRqKriAUYBABE59Bxh4/tGmwBUA6ob ZYcEZwOqT/gsp+qFIJ98OReHlawHmSsnxfKgaCExu0EKAl9i7GE2OrHXyoEz6WQ2NpFk 77bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850220; x=1687442220; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yAI6VIgzMZpgJduQw+zbfBfSRhC2iaxfwnzVojWouK0=; b=OYPHMbTNEB8JVAPsU+TM4K5MaMaIgQq3rVGrkYjwvu7xh93H90aBYfKn+zSKOc29G4 72gVj8UvkN8InE3srOexCN2HDRx+BvbKhJOVzmk2/EQ7WexlU+6WBIhE8ignzY1DRlg5 /07etFNq9+SdFxH6h9GkQFFLV/3YCbw7x9+qNnFLNplFgmL3+0iFDZVaPviuqq08xJ20 18W8+aQPzggpNvg0a8YHiBDppKjvEHdbRfXXi6jbJIwvqE6r56RQCQNPYrQeUNVTZpE8 rvLNu5EPgLEhGvzuDx166l5kEDViR47F9507Vfpc3k+yI3atRv6Lw9T3ZUbiXzUYdIGD 2Abg== X-Gm-Message-State: AC+VfDwThJLeYVlShhrIhUCr5wMTBs9wgbR0pOBdtLJ2ylvt2qTyB+Tj JKCLJT75iS/0jyoTjWqTA2e/5MuKJtQiWlRJrvA= X-Google-Smtp-Source: ACHHUZ6W87dJebLSJ+EjHbyPHe3wZL2eQfGIELTAfHZ7/NPoFFd73NnVvKZ9HihMQIsK9GN2Zjz/Tw== X-Received: by 2002:a05:6a00:1783:b0:644:d775:60bb with SMTP id s3-20020a056a00178300b00644d77560bbmr20520014pfg.20.1684850220053; Tue, 23 May 2023 06:57:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 44/52] accel/tcg: Tidy includes for translator.[ch] Date: Tue, 23 May 2023 06:53:14 -0700 Message-Id: <20230523135322.678948-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851387727100001 Content-Type: text/plain; charset="utf-8" Reduce the header to only bswap.h and cpu_ldst.h. Move exec/translate-all.h to translator.c. Reduce tcg.h and tcg-op.h to tcg-op-common.h. Remove otherwise unused headers. Signed-off-by: Richard Henderson --- include/exec/translator.h | 6 +----- accel/tcg/translator.c | 8 +++----- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index 228002a623..224ae14aa7 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -18,12 +18,8 @@ * member in your target-specific DisasContext. */ =20 - #include "qemu/bswap.h" -#include "exec/exec-all.h" -#include "exec/cpu_ldst.h" -#include "exec/translate-all.h" -#include "tcg/tcg.h" +#include "exec/cpu_ldst.h" /* for abi_ptr */ =20 /** * gen_intermediate_code diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 60a613c99d..fda4e7f637 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -8,15 +8,13 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" #include "qemu/error-report.h" -#include "tcg/tcg.h" -#include "tcg/tcg-op.h" #include "exec/exec-all.h" -#include "exec/log.h" #include "exec/translator.h" +#include "exec/translate-all.h" #include "exec/plugin-gen.h" -#include "exec/replay-core.h" - +#include "tcg/tcg-op-common.h" =20 static void gen_io_start(void) { --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851153; cv=none; d=zohomail.com; s=zohoarc; b=iinMuWPbeVeM45sAtdJLKUoLey+KfEBeWrROUCeiKuAE/vWLSHM8mZxHvZ0UM/XLU1bc+RE14H9tRyPHCshDirH57DJ32nwCuQZeXqHUY0m8yz80Ptf6UTO3tcG4ROoXHWVjTIkei8tLFiW9QuV27vTUUiSoqP3iMAfO5NjGkmg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851153; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=h+RdJQ/zC7YSHEg4bhdr641ZyzAbD7cM7kABj3n3kOQ=; b=Fr6g+U5jcTipiJCWgZiSaF7RhZnJ1azKwMjg2ZjbMySXDtAKaNTQ9nqZKi2XqicctNSs6KuQUolosIB2iR1nJcLf8D8AXcWPrXeMHWZXHM3IrUn61lqumhh28rSYJwH4l1x9H0JA3MP7kgPf+JKL99vBz59KeuEdTSR6L8TjSAY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684851153932704.8215157664098; Tue, 23 May 2023 07:12:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SVi-0003Ol-Qn; Tue, 23 May 2023 09:57:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SVc-0003Bl-6P for qemu-devel@nongnu.org; Tue, 23 May 2023 09:57:04 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SVa-0004CR-55 for qemu-devel@nongnu.org; Tue, 23 May 2023 09:57:03 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-64d3491609fso3279236b3a.3 for ; Tue, 23 May 2023 06:57:01 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id v11-20020a62a50b000000b0063799398eaesm5805790pfm.51.2023.05.23.06.57.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:57:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850221; x=1687442221; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=h+RdJQ/zC7YSHEg4bhdr641ZyzAbD7cM7kABj3n3kOQ=; b=Koj1bKC7RgazYhoHG5o2b7zoai4YsVwVUNawjwmzzuUR7AXTo4Mh2KgUTiY0jDX81o dxbYuZZB2oTECfJBUmP0uZKNXEjlPmU6+Vc8LzTJanZ76VCWF2I3jMZO4OULCyj5S6Km oxQ2uKQ4Ag372wJpoSqbca8gDuO5BZbzTCoaMMSDRKMBGkQzQ+iEUDgHJa8wZNgRKuM2 OqrnMzuv6d1TfVt1XcdtG03EYIwAst+8cRUBwppGD4cV5mgvtb/089JoYPNPBl68URNN zRdVyflsguS5ouoIzMBWE2oMt/Ca/zPFVTYLxr+29RvT2oOFTVqqxVtgP89+kMfOg4so VNzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850221; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851155991100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/region.c | 2 ++ tcg/tcg-common.c | 2 ++ tcg/tcg-op-gvec.c | 2 ++ tcg/tcg-op-ldst.c | 2 ++ tcg/tcg-op-vec.c | 2 ++ tcg/tcg-op.c | 2 ++ tcg/tcg.c | 2 ++ 7 files changed, 14 insertions(+) diff --git a/tcg/region.c b/tcg/region.c index bef4c4756f..34ac124081 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -22,6 +22,8 @@ * THE SOFTWARE. */ =20 +#define IN_TCG + #include "qemu/osdep.h" #include "qemu/units.h" #include "qemu/madvise.h" diff --git a/tcg/tcg-common.c b/tcg/tcg-common.c index 35e7616ae9..678ab482f7 100644 --- a/tcg/tcg-common.c +++ b/tcg/tcg-common.c @@ -22,6 +22,8 @@ * THE SOFTWARE. */ =20 +#define IN_TCG + #include "qemu/osdep.h" #include "tcg/tcg.h" =20 diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 95a588d6d2..0ecde731f4 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -17,6 +17,8 @@ * License along with this library; if not, see . */ =20 +#define IN_TCG + #include "qemu/osdep.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index f32c0fda35..dc8dcd8b4f 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -22,6 +22,8 @@ * THE SOFTWARE. */ =20 +#define IN_TCG + #include "qemu/osdep.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 35d67eeda0..6c70178e9e 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -17,6 +17,8 @@ * License along with this library; if not, see . */ =20 +#define IN_TCG + #include "qemu/osdep.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 8c1ad49c4e..16ff61c65d 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -22,6 +22,8 @@ * THE SOFTWARE. */ =20 +#define IN_TCG + #include "qemu/osdep.h" #include "exec/exec-all.h" #include "tcg/tcg.h" diff --git a/tcg/tcg.c b/tcg/tcg.c index 7d0449f6a9..38321d6d54 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -22,6 +22,8 @@ * THE SOFTWARE. */ =20 +#define IN_TCG + #include "qemu/osdep.h" =20 /* Define to jump the ELF file used to communicate with GDB. */ --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id v11-20020a62a50b000000b0063799398eaesm5805790pfm.51.2023.05.23.06.57.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:57:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850222; x=1687442222; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=OVmsUx5trCwxWekmTd1RE9Nb9Hhxj1t4Uos0U6OmJ/w=; b=rd5dBAFJ+i2tym6Xr9t6sA6gQH6AkVzfIwKiViNeTK3GxHP+cuudVqCIJtFkPE5dk9 IH6sINRdT716LrbMqWDZLAFsuYVOBxzsfBNjQfW5j0qmU5ox3H8gX56goPYWxX8dvch8 IDC70dckXsrInY/tyEAQyT2OTRUnb3D8W41VDV62TrMZqgWUuJ5f/2FSEhsrU7+4xeEh EOtubzR+ZT+uSJcaZV+f69+wP2A5L+qJG3VHdYehpP8gd68VoMkKxFB0z3WW9DqPzNfL telci+jAWDkGD9KBzcxWN9gv2I4szKDKFWDGtmzKNPQ3VdRq/t1nkvdtJhgi6JKHas1f eWGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850222; x=1687442222; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OVmsUx5trCwxWekmTd1RE9Nb9Hhxj1t4Uos0U6OmJ/w=; b=BCglddv7qEBJ/NlAtSHX1VBqHtIxpSADTi/xCyP5RsAXb03GmyKyzTDBBHYbxlAh3+ Jkq1GkZNqtc94cLLEIyl1wjTpblgVypgQ1rziQTuTWFqTFObM2OvdrW99kLS8/wb6X3/ V7vrF58WEHCNwByRY/3zxzsUHz1Y7BTRQ+fw7Jk26RnWgErgt1Lm4raCWgznerXD0Jfn TLbV6IBAVw+rv3y4jBb4mBubZTCOsVPDgGT9lSotjg2LSLHNgV69hiycHc6XvhTnoJqr vMVCANs/PyHlBfdLnPghHhbLlOkkjwpApFZP34s8HQoI3N0NEZkcGQzPruQMJoEF6kpW dn6g== X-Gm-Message-State: AC+VfDzjrWsbMFWcqsREwvHMqr7mQJGCKbTxzhE125yYYYbj8GoDN6SX OpSIQAg/E6A1bfG4IKFXPA87U56r7yUmI/bDy1I= X-Google-Smtp-Source: ACHHUZ6Lk7AA4CX+4qGfDvAsyvGgYFpyKNzHGDsDPm1UBcpY00KpYN71I2u1azIZchKHIA696jPq5Q== X-Received: by 2002:a05:6a00:1307:b0:64b:256:204c with SMTP id j7-20020a056a00130700b0064b0256204cmr18298429pfu.20.1684850221464; Tue, 23 May 2023 06:57:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 46/52] tcg: Fix PAGE/PROT confusion Date: Tue, 23 May 2023 06:53:16 -0700 Message-Id: <20230523135322.678948-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684850943383100003 Content-Type: text/plain; charset="utf-8" The bug was hidden because they happen to have the same values. Signed-off-by: Richard Henderson --- tcg/region.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/tcg/region.c b/tcg/region.c index 34ac124081..184e684b04 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -507,6 +507,14 @@ static int alloc_code_gen_buffer(size_t tb_size, int s= plitwx, Error **errp) return PROT_READ | PROT_WRITE; } #elif defined(_WIN32) +/* + * Local source-level compatibility with Unix. + * Used by tcg_region_init below. + */ +#define PROT_READ 1 +#define PROT_WRITE 2 +#define PROT_EXEC 4 + static int alloc_code_gen_buffer(size_t size, int splitwx, Error **errp) { void *buf; @@ -527,7 +535,7 @@ static int alloc_code_gen_buffer(size_t size, int split= wx, Error **errp) region.start_aligned =3D buf; region.total_size =3D size; =20 - return PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return PROT_READ | PROT_WRITE | PROT_EXEC; } #else static int alloc_code_gen_buffer_anon(size_t size, int prot, @@ -796,10 +804,10 @@ void tcg_region_init(size_t tb_size, int splitwx, uns= igned max_cpus) * buffer -- let that one use hugepages throughout. * Work with the page protections set up with the initial mapping. */ - need_prot =3D PAGE_READ | PAGE_WRITE; + need_prot =3D PROT_READ | PROT_WRITE; #ifndef CONFIG_TCG_INTERPRETER if (tcg_splitwx_diff =3D=3D 0) { - need_prot |=3D PAGE_EXEC; + need_prot |=3D PROT_EXEC; } #endif for (size_t i =3D 0, n =3D region.n; i < n; i++) { @@ -809,9 +817,9 @@ void tcg_region_init(size_t tb_size, int splitwx, unsig= ned max_cpus) if (have_prot !=3D need_prot) { int rc; =20 - if (need_prot =3D=3D (PAGE_READ | PAGE_WRITE | PAGE_EXEC)) { + if (need_prot =3D=3D (PROT_READ | PROT_WRITE | PROT_EXEC)) { rc =3D qemu_mprotect_rwx(start, end - start); - } else if (need_prot =3D=3D (PAGE_READ | PAGE_WRITE)) { + } else if (need_prot =3D=3D (PROT_READ | PROT_WRITE)) { rc =3D qemu_mprotect_rw(start, end - start); } else { g_assert_not_reached(); --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851286; cv=none; d=zohomail.com; s=zohoarc; b=TV0ZZo0gOLfpe+t2IkbtubvIfuHoUbNphnu0As/f6Fv7zaqZE5RTqQ7LoueFn4saS1PGPGefruLLyOftvw+/kGn/LYYx7uP06pRZcrOJtY0qQ+PUjWBwPvgM+WN5Q4WTnZmqKyxdjI0Ds24MT3FsEq6HExoyllk9Bh+0wate1S8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851286; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Br8zXaVAOKNlB9xv5g9cPNHLqbtW8oBpWMoxXID7zwE=; b=b8ukU4KmtQPYTNiZa98BHBNp/S2sPnXFd/GY6yxkIFkGLq0no4R/R0VDlvvKurmSiQjkHci9R/Eu3LFRC/uC00E/5jHLUTIEGqZsC8dm/xIy0rbzjWK84/8LWOvflFP6XBh7ZBRDvapHnur7NORHiWfcjpib1ugJRMNGjgfiy7I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684851286694436.8149045913717; Tue, 23 May 2023 07:14:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SVk-0003SH-Id; Tue, 23 May 2023 09:57:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SVh-0003MD-Fj for qemu-devel@nongnu.org; Tue, 23 May 2023 09:57:09 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SVb-0004Cw-HE for qemu-devel@nongnu.org; Tue, 23 May 2023 09:57:08 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-64d30ab1f89so3420625b3a.3 for ; Tue, 23 May 2023 06:57:03 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id v11-20020a62a50b000000b0063799398eaesm5805790pfm.51.2023.05.23.06.57.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:57:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850222; x=1687442222; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Br8zXaVAOKNlB9xv5g9cPNHLqbtW8oBpWMoxXID7zwE=; b=g81ezXOtth/xC8Z5cSOn/XNLj4zwn1LRG01CPvz1r7dICqD/FTDpXrB5buaTnKW/qa Uz81t2kIGV21gpS9BnzRAbtCM56FbnvcGhjNx3k9qlRnAzZEUkISK4SKg4u7FUCnMber sPk83NdFVfjongPY2YZXz76RV+awfelEd7cAfTNbFaFl9FwZ08C+YEL5app25d6Shj/5 Dk/eUoPHoucin4v/mnnoe0ym20iWxyYv1/65WOTUZ2DrQ6cpdNYp2+u/FTCSubvwfVg7 2yHxs6tyucwRA5oZHEldu9w5QEjWiOUX5iAfI5cDGq8l67FM1XhDvpJ7u//8YuhZQsVu oZ5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850222; x=1687442222; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Br8zXaVAOKNlB9xv5g9cPNHLqbtW8oBpWMoxXID7zwE=; b=gcaZmOEBN2MYFLn5DpQCgOwNPc6aXgMrreK7kN+YuvGqtXi9ZP/hSgWa9dpHv3x0ox rGJ3a/YlHFj/H6M/kkMUTue9QXezQKYayqF72/mn35tR3i9LpUJ65sbDnnaH/BfXcAzE 7t9XUr48LFpdTsJMbItiQxhiaX4oGnGtjRdGJno2itRDkW0zBX8MERcuBMd2sAywySgx prAxbqBrYeF0WTF/fae4fcvHbw2i1fathhvOauPQQyowoC1YUs3wqMHLVgphL78Szh3d cA06sAQaKfi/jGPZ/h8eeocpDkag0ig5iGtHyd/cRgWb+YicyNxjP+v40AZJE0emQXXv Yi6g== X-Gm-Message-State: AC+VfDynAVyFKJfX1/i/nEverUjWM5HX0GRWNDACpVlcWgOfPf7i3+KH e/cP8cWcf/+Xww2aWw4pWaBBDd8+K3YlRoVf2Q8= X-Google-Smtp-Source: ACHHUZ74Aozjn4YeX0V77wxD30Va322y51mhQsFJF1YvQ8YlDqj2jpU6z2joLqgj38LDAHbFhj2Gsg== X-Received: by 2002:a05:6a00:2da8:b0:64b:20cd:6d52 with SMTP id fb40-20020a056a002da800b0064b20cd6d52mr18728001pfb.14.1684850222187; Tue, 23 May 2023 06:57:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 47/52] tcg: Move env defines out of NEED_CPU_H in helper-head.h Date: Tue, 23 May 2023 06:53:17 -0700 Message-Id: <20230523135322.678948-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851287431100003 Content-Type: text/plain; charset="utf-8" Since the change to CPUArchState, we have a common typedef that can always be used. Signed-off-by: Richard Henderson --- include/exec/helper-head.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index a355ef8ebe..28ceab0a46 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -22,6 +22,7 @@ #define dh_alias_f64 i64 #define dh_alias_ptr ptr #define dh_alias_cptr ptr +#define dh_alias_env ptr #define dh_alias_void void #define dh_alias_noreturn noreturn #define dh_alias(t) glue(dh_alias_, t) @@ -37,6 +38,7 @@ #define dh_ctype_f64 float64 #define dh_ctype_ptr void * #define dh_ctype_cptr const void * +#define dh_ctype_env CPUArchState * #define dh_ctype_void void #define dh_ctype_noreturn G_NORETURN void #define dh_ctype(t) dh_ctype_##t @@ -52,9 +54,6 @@ # endif # endif # define dh_ctype_tl target_ulong -# define dh_alias_env ptr -# define dh_ctype_env CPUArchState * -# define dh_typecode_env dh_typecode_ptr #endif =20 /* We can't use glue() here because it falls foul of C preprocessor @@ -96,6 +95,7 @@ #define dh_typecode_f32 dh_typecode_i32 #define dh_typecode_f64 dh_typecode_i64 #define dh_typecode_cptr dh_typecode_ptr +#define dh_typecode_env dh_typecode_ptr #define dh_typecode(t) dh_typecode_##t =20 #define dh_callflag_i32 0 --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851332; cv=none; d=zohomail.com; s=zohoarc; b=KKDVR9clsMh1NvjyNJKSdQONqZHfJFwoNx5UZfRledZYs5M4B0OiROYp+2ZHNXQJEBTi03OpG1rIDOg46CyusxkdoampqbyjmZUSEIr4KW+Vgt192EpB9V1FVLZZUQHOg26M/JJeol4g1j/4Ps7mh2uwQ2eUCB/e55tzPU3eTOg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851332; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HKdjWZZDyCzXoRyD/E9HH3fJ0gjM+XwFZKOPdo6BjpI=; b=Z8mzAAfiGsHRTu5fVl8csGH2J4eip87KoVS8Pxpn6U6Y+GOvJxW2FnHiTe0p6SA4upnR4a18s6r2YxKhWuaT1eeXK6kv3IrNButC+9XK4P0bYH2HXlCtIX7owwRnnNqo1h4PD25j6BHEG4g3w95KOfOMUIUeMHRPLy2Ky0cNI00= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16848513322671017.8680534505983; Tue, 23 May 2023 07:15:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SVl-0003UD-RB; Tue, 23 May 2023 09:57:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SVf-0003I9-PU for qemu-devel@nongnu.org; Tue, 23 May 2023 09:57:07 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SVd-0004DC-8C for qemu-devel@nongnu.org; Tue, 23 May 2023 09:57:07 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-64d341bdedcso3312969b3a.3 for ; Tue, 23 May 2023 06:57:03 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id v11-20020a62a50b000000b0063799398eaesm5805790pfm.51.2023.05.23.06.57.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:57:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850223; x=1687442223; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=HKdjWZZDyCzXoRyD/E9HH3fJ0gjM+XwFZKOPdo6BjpI=; b=WkRLK51883e7bpZO/iYsoVq5BCzR3k7C+jg6D5BDuDoJDXOAZH287tRVXOBM5QH/g5 cagbifNN3OlwCvrHoBOmZmjzsaTvQtsuEAUraq4kn2I7/FrhGo6Dvif94Gkh1xXyy+48 bIhEcyJhKFyEFB91Qk6T5OwDsakHJr7lYt+S9l2UQmrHyJe3A2UqjDzN/uwuIy76pp0/ XhZGm9d8FOUzpKf4TJAZfXcI2NKxS3sUmmOub1bspkkGycHZJQmbRrGphUdKNMBg15Qz 1os8MqPS58yQ2vbxQatfy2iUoMRC3w1Alu0Z1Kc47uQRNX1vwtjKCFv3XCDyqcYnk7Fq VJEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850223; x=1687442223; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HKdjWZZDyCzXoRyD/E9HH3fJ0gjM+XwFZKOPdo6BjpI=; b=ZuihwQb8LayMCHQ6wnOKgd6lewRv7s074BFGVN5tIxgBnRALOI1MaSCOn4RMMA8FL2 6hGCqlvjfYdRXD6YSxxGJOePRMJLGccTGBxtK0rGXie7bmI9UyICjL5161vsrgZgvfE4 /k8D+wyD2ZuBFFufAA/IwIpC9s3JYEYAEH7h311Bdpx0aQKqJZaXtLG/9SeTtxvY6EoD c+fnEicWw9ZKxlz/LVnQ+SlL9pxdF3/w0S/CpFHpenhIZcDUTLW3EIs/BOG6If3qf6x1 a9CJHCYv4m+iuoObcmguEJ13egYU7XxEa03rn9Z2nGDFsBruN2RnLAVT6alqMcK77IkN ogiQ== X-Gm-Message-State: AC+VfDxZSUmDGCrgZGvMp4nqiR7LrlzIFFSjkVkbi7T3mgtcRhamyYvb AziYO05Fqoka8wiYBhM9Vrj3HEgqMjTEL5qMN6s= X-Google-Smtp-Source: ACHHUZ5y86anIC+mrp4VO4A1bp5+q925y2mz0EoDyqpjKbHdwuv3zoDF07d0CYcCxKlVzhzNed7urQ== X-Received: by 2002:a05:6a21:7891:b0:103:b0f9:7110 with SMTP id bf17-20020a056a21789100b00103b0f97110mr18064168pzc.11.1684850222872; Tue, 23 May 2023 06:57:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 48/52] tcg: Remove target-specific headers from tcg.[ch] Date: Tue, 23 May 2023 06:53:18 -0700 Message-Id: <20230523135322.678948-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851333406100001 Content-Type: text/plain; charset="utf-8" This finally paves the way for tcg/ to be built once per mode. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 - accel/tcg/plugin-gen.c | 1 + tcg/region.c | 2 +- tcg/tcg-op.c | 2 +- tcg/tcg.c | 2 +- 5 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 635fa53fdb..a498f31967 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -25,7 +25,6 @@ #ifndef TCG_H #define TCG_H =20 -#include "cpu.h" #include "exec/memop.h" #include "exec/memopidx.h" #include "qemu/bitops.h" diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 3e528f191d..5c13615112 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -43,6 +43,7 @@ * CPU's index into a TCG temp, since the first callback did it already. */ #include "qemu/osdep.h" +#include "cpu.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" #include "tcg/tcg-op.h" diff --git a/tcg/region.c b/tcg/region.c index 184e684b04..cf4568bb8f 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -32,8 +32,8 @@ #include "qemu/cacheinfo.h" #include "qemu/qtree.h" #include "qapi/error.h" -#include "exec/exec-all.h" #include "tcg/tcg.h" +#include "exec/translation-block.h" #include "tcg-internal.h" =20 =20 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 16ff61c65d..ba12bf053e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -25,10 +25,10 @@ #define IN_TCG =20 #include "qemu/osdep.h" -#include "exec/exec-all.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" #include "tcg/tcg-op-common.h" +#include "exec/translation-block.h" #include "exec/plugin-gen.h" #include "tcg-internal.h" =20 diff --git a/tcg/tcg.c b/tcg/tcg.c index 38321d6d54..06085f4c99 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -36,7 +36,7 @@ #include "qemu/cacheflush.h" #include "qemu/cacheinfo.h" #include "qemu/timer.h" -#include "exec/exec-all.h" +#include "exec/translation-block.h" #include "exec/tlb-common.h" #include "tcg/tcg-op-common.h" =20 --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684853706; cv=none; d=zohomail.com; s=zohoarc; b=D5mPw3gRGHV4rECy9Jry2vwowI/nUWm2+ijEb5eIXeGLLKQ0XpEvpMhdvATbXCsfZDoo9YeF5xvWhW2eQ8AOD32D+DFNw1LYmeToIJWe/47bgAJkBvRfwDcdkavl4Hh/QunWRiTSu8KrO48094sDGece9cbwSGR77XrEiU6KOJk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684853706; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5T+y6XKoovlI/5PgO4ohU9QwOLRgrcATNcdajUNZQbc=; b=VnAyBx6GQpAtDu+H2eSg7eOy4ISfaNEHH8l01OX/Wt1EDMdkYa4x0YxwoT/rwxdYgUUFmmiLA/xrGbaD1ablzxSVaxceYhag6StyAhvpC6Z1dkQY1Pb4WNdVhh0Wm7VZ7ogfXHb0GT5pHpOzq4sOPR/Nwq/wv5JzA8iZgLKVPBU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684853706222629.7155907485011; Tue, 23 May 2023 07:55:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SVm-0003UW-25; Tue, 23 May 2023 09:57:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SVf-0003HO-Db for qemu-devel@nongnu.org; Tue, 23 May 2023 09:57:07 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SVd-0004DN-1n for qemu-devel@nongnu.org; Tue, 23 May 2023 09:57:07 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-64d426e63baso4412074b3a.0 for ; Tue, 23 May 2023 06:57:04 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id v11-20020a62a50b000000b0063799398eaesm5805790pfm.51.2023.05.23.06.57.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:57:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850223; x=1687442223; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=5T+y6XKoovlI/5PgO4ohU9QwOLRgrcATNcdajUNZQbc=; b=ZFAldy4+tFBfVjc/8kmEkv5YJDcD3GBrtyg3gkEED1tEfFqlyHHj4hGhTxVhmFfHhj tT4uYed1gwQH2o0V6vaIpKJoDe6RE1qf5cJJRMAz7sBBOPkU9Ca3eQXlNPXSSHZFu2jv HwEQs0B00gIMAE9wBceoajBvv9YCOR0ougnIEA0k8bwTYcoRlI9EHNii61y9UaqNhJ7D hslnTi3MlL5CzdCuK9Cy82hU5GYqBxXsTebXfUd+bCteuYQQyRyP/ZyOq0OZf+T6hCMN s4OvVALYV21QTJNLQac47n/30q1q4STbZuuVX9o5VYRpqe2Gxl3OpyVRjjjXD9EQtEy5 1wCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850223; x=1687442223; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5T+y6XKoovlI/5PgO4ohU9QwOLRgrcATNcdajUNZQbc=; b=bvVHsKP/FhRPoD5A8fBBJs/Z7V8HdT9WlCSvmJNULO3S7kXMI23JBmax41hI8KofUF 0RI3ME1p86jJN+OSafqULsq5QAKfxLR89xswzksYd2dPDEPk3uZUmJ4RROLVdyfVX47F sQKBv/WG5/XrS1L4x7G1ykjuhHAhMTQYc4G0YYux4hUiawwfXthuO/nGFx2ztMKU9emM 6WE9yDbxsGVGCtq8JnAOn1EAKcwyHb6pudJzx+teeOl26Y2qYPISd+T+OM2pAj/IIG/F B3SNwZ3vqpaLunWG/vTEx+btopJfmUa6Ubr7WsVkhVUzF6pSEHmOgIT4eWIJu78Mx19r 3uHA== X-Gm-Message-State: AC+VfDzGlV923b0qQB+U/o3dVzL6dnFA/wcjd4BDiZPGD3LC+aAYXJCF Z5CbykdTHrsraB/JCxezhMt/+YbwE/5ej+8pB9A= X-Google-Smtp-Source: ACHHUZ7NvL60hANmfPQ4YxSiuDHpMI3ba0EZ5Y3xrJNgZLaBByrGBuTkFKiXaLhM2JMZ4gy+jSkRgw== X-Received: by 2002:a05:6a00:2d26:b0:63f:2f00:c6d with SMTP id fa38-20020a056a002d2600b0063f2f000c6dmr20201600pfb.2.1684850223702; Tue, 23 May 2023 06:57:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 49/52] plugins: Move plugin_insn_append to translator.c Date: Tue, 23 May 2023 06:53:19 -0700 Message-Id: <20230523135322.678948-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684853706774100001 Content-Type: text/plain; charset="utf-8" This function is only used in translator.c, and uses a target-specific typedef, abi_ptr. Signed-off-by: Richard Henderson --- include/exec/plugin-gen.h | 22 ---------------------- accel/tcg/translator.c | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 22 deletions(-) diff --git a/include/exec/plugin-gen.h b/include/exec/plugin-gen.h index 3af0168e65..e9a976f815 100644 --- a/include/exec/plugin-gen.h +++ b/include/exec/plugin-gen.h @@ -29,25 +29,6 @@ void plugin_gen_insn_end(void); void plugin_gen_disable_mem_helpers(void); void plugin_gen_empty_mem_callback(TCGv_i64 addr, uint32_t info); =20 -static inline void plugin_insn_append(abi_ptr pc, const void *from, size_t= size) -{ - struct qemu_plugin_insn *insn =3D tcg_ctx->plugin_insn; - abi_ptr off; - - if (insn =3D=3D NULL) { - return; - } - off =3D pc - insn->vaddr; - if (off < insn->data->len) { - g_byte_array_set_size(insn->data, off); - } else if (off > insn->data->len) { - /* we have an unexpected gap */ - g_assert_not_reached(); - } - - insn->data =3D g_byte_array_append(insn->data, from, size); -} - #else /* !CONFIG_PLUGIN */ =20 static inline bool @@ -72,9 +53,6 @@ static inline void plugin_gen_disable_mem_helpers(void) static inline void plugin_gen_empty_mem_callback(TCGv_i64 addr, uint32_t i= nfo) { } =20 -static inline void plugin_insn_append(abi_ptr pc, const void *from, size_t= size) -{ } - #endif /* CONFIG_PLUGIN */ =20 #endif /* QEMU_PLUGIN_GEN_H */ diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index fda4e7f637..918a455e73 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -285,6 +285,27 @@ static void *translator_access(CPUArchState *env, Disa= sContextBase *db, return host + (pc - base); } =20 +static void plugin_insn_append(abi_ptr pc, const void *from, size_t size) +{ +#ifdef CONFIG_PLUGIN + struct qemu_plugin_insn *insn =3D tcg_ctx->plugin_insn; + abi_ptr off; + + if (insn =3D=3D NULL) { + return; + } + off =3D pc - insn->vaddr; + if (off < insn->data->len) { + g_byte_array_set_size(insn->data, off); + } else if (off > insn->data->len) { + /* we have an unexpected gap */ + g_assert_not_reached(); + } + + insn->data =3D g_byte_array_append(insn->data, from, size); +#endif +} + uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, abi_ptr p= c) { uint8_t ret; --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851088; cv=none; d=zohomail.com; s=zohoarc; b=BnUwa0rOOatNub2WW3Fi8NDKFeNsNvMHsGBoX1MPqB8YgB84GBPj0FcSdJ1DBCUoH8drH0+kJ28LHeiqqrFfia3inFcyQZF6DiH/Xk/jvOUW+vHO6uGU/BdWUn3QBB0QTforwB01o6GxeCgqyjhoDdFz4HgCVPWPdazxFl8R3j8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851088; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bVDQIGY4qsUIGLjKLkOyu6DlKk1Y53Q32bQuvC8FPMo=; b=Qy054dhlM5xDqZ+YgdMvoQe7gt8xQnToUH0uEchsKAuKyhvpIKrgfEHKujTPMyt1Cp9UhDI2la6V8qtMDq2jWPGQwtZ47L0nRWaS9MqOZw4ONB5hWz4idj9GcNP1B6XFklZETp5bbKaluyTLanRAtf4E9A7FKuAzHDKqECb24oE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168485108897025.33831531440535; Tue, 23 May 2023 07:11:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SVj-0003Pd-0Q; Tue, 23 May 2023 09:57:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SVg-0003Jo-KE for qemu-devel@nongnu.org; Tue, 23 May 2023 09:57:08 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SVd-0004DW-Sg for qemu-devel@nongnu.org; Tue, 23 May 2023 09:57:08 -0400 Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-64d3578c25bso5247265b3a.3 for ; Tue, 23 May 2023 06:57:05 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id v11-20020a62a50b000000b0063799398eaesm5805790pfm.51.2023.05.23.06.57.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:57:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850224; x=1687442224; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=bVDQIGY4qsUIGLjKLkOyu6DlKk1Y53Q32bQuvC8FPMo=; b=Gfo5Mq9oqnvG3omtXeOo5euI8B5NPnOUzxpGpygWe7r8NYdvEYLwdzI4c8j5OwcNQF +spGaXgamHb8qNGjGnjCWqXqubCOPtmdidP9EmSxIl2UCiXCiJViio/SxqO//Sq3Lvpu GQvrsFvEpkmbL4ufW37cp/1HkBvxmJG5jqAELDP2OdVNnYbhnFYrwOUcUywEKl9LxKM9 HRQWK79sogW7aPbxBXT1wen7d1Ldvz/pDUvsEvA4Q/68kmsKzf2w2Yk7JoRwOMyotHsO BblOIy1NlH8INx1smasl9PyqBIUPR7kNSyGJXghiwo+M+EL8Pj7gFDYYrojUnLx+grEF MDoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850224; x=1687442224; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bVDQIGY4qsUIGLjKLkOyu6DlKk1Y53Q32bQuvC8FPMo=; b=WGlHmBBMU4TMWFmMeRRwxJdtuSmzpTVgUu1vHp5vSuNEwDz4pxycaFTO8c7l0DKf9F 2JrAKRLwM3beWEIIr8924YSrQ9Dp+shA5GsgyYEXIQwAyIxnGfcNBxUf7pemEye4r7rs 7wDhoPOOwA3Coin1pJ1sVGEIe3RDg3BGIU+48Y4tD0G5hj5wI+CYMsvcG5AFEjFeR+VV XmOSkT7CQFIerILoSY3b8LizQG3Xt2HSRtU4w0twzF7xqJoNEARm+sv6mQBHs7/xjkej ctFazD0zUHaYIneH+KGNLdolzHkQHz28oOHJTCLKYDXqVTVE4/2sKXs2gk0ZfcxekqGR hY9w== X-Gm-Message-State: AC+VfDxtRcQlvjHA3MlzVccA4rpmjNIBug8/3ZpZPHvuAXmwSneVUWTz 6DRWKc70d6CBv5+Ngvoz0RG1rN/rRL+S0LGKgCQ= X-Google-Smtp-Source: ACHHUZ4sIK5mu79TEUIm0/Rs+5bjmIY/0nwW2hyc53AKQsE+skH5Gu/tRgVNLdPGcvDC3g4trzxc+g== X-Received: by 2002:a05:6a00:9a7:b0:64c:9972:f74b with SMTP id u39-20020a056a0009a700b0064c9972f74bmr18915049pfg.12.1684850224642; Tue, 23 May 2023 06:57:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 50/52] plugins: Drop unused headers from exec/plugin-gen.h Date: Tue, 23 May 2023 06:53:20 -0700 Message-Id: <20230523135322.678948-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851089715100003 Content-Type: text/plain; charset="utf-8" Two headers are not required for the rest of the contents of plugin-gen.h. Signed-off-by: Richard Henderson --- include/exec/plugin-gen.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/exec/plugin-gen.h b/include/exec/plugin-gen.h index e9a976f815..52828781bc 100644 --- a/include/exec/plugin-gen.h +++ b/include/exec/plugin-gen.h @@ -12,8 +12,6 @@ #ifndef QEMU_PLUGIN_GEN_H #define QEMU_PLUGIN_GEN_H =20 -#include "exec/cpu_ldst.h" -#include "qemu/plugin.h" #include "tcg/tcg.h" =20 struct DisasContextBase; --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851384; cv=none; d=zohomail.com; s=zohoarc; b=Qsw465LP7JrxfRm/6KJZomPPz2W0gbwsNn2Vq+vvlbSp7uvzQXzvwbS3NoShIyQb+pWeqBuJGtCGy5qpDTsICbMbNbtoVcHtIgfWPZI1kxlgpOVUgS5dnR1sxYOEtrGCHX2JTsrAnEfhhMtqgtyfVnsi+S+pDkqTJlYzy6jkmmA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851384; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PRmXJMFN3rYya2LUNfLtjvM1yMLdoZFGjXY4lJtw1jE=; b=J1SEevyIHjwBNWNbp6zwOVfvzdL7WCXoVyHOHzxBenHBnfWAwnZMLvXgXs5W3VY3qCDFReQZ6yjzM4yx484fIXTzLMtqw1BFEnbWhp5EgH0cHaDpxhskN5P+hvHeSlcjTrPrxZmwA0fqUMwQ+2zMmgJ3ns614pFczxHPIy16o2Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684851384036475.8275741833985; Tue, 23 May 2023 07:16:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SVp-0003bM-1b; Tue, 23 May 2023 09:57:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SVm-0003WQ-Jd for qemu-devel@nongnu.org; Tue, 23 May 2023 09:57:14 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SVe-0004BV-Pz for qemu-devel@nongnu.org; Tue, 23 May 2023 09:57:14 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-64d1e96c082so4215138b3a.1 for ; Tue, 23 May 2023 06:57:06 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id v11-20020a62a50b000000b0063799398eaesm5805790pfm.51.2023.05.23.06.57.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:57:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850226; x=1687442226; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=PRmXJMFN3rYya2LUNfLtjvM1yMLdoZFGjXY4lJtw1jE=; b=fhbY9Gl2HgEsCvEI3gzEY+YcjLrGDqywmivCg2PzNxrTjXFmUd7jQX3TTY6eCZ5Ezx aKR+nrXzyRVfTFRGopPCq03uEVXbtPoxXEwF/dGxR7LUwrCYyQTFyLRJd8qlvm4uA1dr 9rSkpG1iDMzgi4DtLNFUJ6GUR4E92kzjyeNb2DwAeFXb4Du8RE4PLrdvGkcUXar79Oyj AWf0FeOJLSO/slUhVagKOMD+y/PEr0qyLiKOWKxyIBucGe6XQtSyPrdf0hhNxpNJbCLl HDH+cK3KV0zKXKnta6LoNGDl1DnTLqJo2vGaE3tclzwWwutZps7MKRvlO1aSxSCxYcdx 9wMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850226; x=1687442226; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PRmXJMFN3rYya2LUNfLtjvM1yMLdoZFGjXY4lJtw1jE=; b=kpCS18qM/pQ6r7rcJ8XYjIhtybqDJ1QDTjTVrFjOOaws2SvUpnhGge2aLLeOkZAG07 X8dlU3HjE5wTpXr0QeW9xQeRBYHfJhoCkXA16lA/isOAl1l29VooOQIH5z3F6TJr1/pQ zzhVKuChxeLYW3S1tX31mp/PGXxy45e9sdRxJQgjFYoGWt4F/6wDlseERvPac+K8nDC7 UoWdamLEzEmbwD8pKSmDvLqtMCDaGQLDkJq4Ty1G000sCD9/58DezSTX/unHV0NStYSj fKPD9YykBpCaIgl41Szw0erhxzw3lPZyaVrpzyaylh+3+ltjOcMSERfkqLyCZ+FP3RVe LVKg== X-Gm-Message-State: AC+VfDy90S4RJMgwf8j1CE4UP89ESn5nQBvyNu9Ngf1qFZXBCGb7zjSw nRcv1FSJYPlRtGkCoJeITV+5X9yrXV+/h3z5LUY= X-Google-Smtp-Source: ACHHUZ7lz1XDLUCrO0UT2wOyhzOzxizVXVuMrUjZteMwh8eIqomT6WDzEYRsZlLhbSrPU52ReH3Syw== X-Received: by 2002:a05:6a00:188e:b0:64d:3227:b800 with SMTP id x14-20020a056a00188e00b0064d3227b800mr19126746pfh.16.1684850225438; Tue, 23 May 2023 06:57:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 51/52] exec/poison: Do not poison CONFIG_SOFTMMU Date: Tue, 23 May 2023 06:53:21 -0700 Message-Id: <20230523135322.678948-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851384568100005 Content-Type: text/plain; charset="utf-8" If CONFIG_USER_ONLY is ok generically, so is CONFIG_SOFTMMU, because they are exactly opposite. Signed-off-by: Richard Henderson --- include/exec/poison.h | 1 - scripts/make-config-poison.sh | 5 +++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/exec/poison.h b/include/exec/poison.h index 256736e11a..e94ee8dfef 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -85,7 +85,6 @@ #pragma GCC poison CONFIG_HVF #pragma GCC poison CONFIG_LINUX_USER #pragma GCC poison CONFIG_KVM -#pragma GCC poison CONFIG_SOFTMMU #pragma GCC poison CONFIG_WHPX #pragma GCC poison CONFIG_XEN =20 diff --git a/scripts/make-config-poison.sh b/scripts/make-config-poison.sh index 1892854261..2b36907e23 100755 --- a/scripts/make-config-poison.sh +++ b/scripts/make-config-poison.sh @@ -4,11 +4,12 @@ if test $# =3D 0; then exit 0 fi =20 -# Create list of config switches that should be poisoned in common code... -# but filter out CONFIG_TCG and CONFIG_USER_ONLY which are special. +# Create list of config switches that should be poisoned in common code, +# but filter out several which are handled manually. exec sed -n \ -e' /CONFIG_TCG/d' \ -e '/CONFIG_USER_ONLY/d' \ + -e '/CONFIG_SOFTMMU/d' \ -e '/^#define / {' \ -e 's///' \ -e 's/ .*//' \ --=20 2.34.1 From nobody Sat May 18 06:50:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1684851122; cv=none; d=zohomail.com; s=zohoarc; b=FL6jL1hqZ31q5wYkzpD7lRo+lfxGuJbU60lXIEEfVd3Yz1d9p8AcHPlcnjpd78QYtH329u6K94zE/Jf5hX+ArOyIleQfKr/j5p3InKsgc6yXvGu6DdelRanj/nevpfVJGX9G7CdF1R2YFA3My7nBdzWKAsXZXO2zFZGg/kNuXg0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684851122; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nI2w8QPEk+92crMZ+axm4/ERglLN4PhhZ5orQ1/925g=; b=LW5MV0QBQganrIBzF7rSoc5M9Q7yzGR/hIMEAj3Hw/u0bPs4arfQotn3aDlwQQuRJRT+ztHzXRn+qdcn4XBqREZpId6tnpp+jMKNmw6f41vpMqUp9+G4RKpIIjiiJ0CZlEOTJd+RSqbLOEymYbhpj5gcHSTbuVIi6jji3nUzCHE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684851122226342.9690762655358; Tue, 23 May 2023 07:12:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q1SVm-0003VJ-A6; Tue, 23 May 2023 09:57:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q1SVi-0003O5-Dp for qemu-devel@nongnu.org; Tue, 23 May 2023 09:57:10 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q1SVg-0004E8-JU for qemu-devel@nongnu.org; Tue, 23 May 2023 09:57:10 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-64d44b198baso2527851b3a.0 for ; Tue, 23 May 2023 06:57:08 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id v11-20020a62a50b000000b0063799398eaesm5805790pfm.51.2023.05.23.06.57.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:57:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684850227; x=1687442227; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=nI2w8QPEk+92crMZ+axm4/ERglLN4PhhZ5orQ1/925g=; b=n+oI1x49R+cr4UbKa9yA+wahQcPCTjr1AU9phksY2VT9JISvKojbmuS1t60OV99Am6 yPxIzx+xcLzehh/WdtX3wJCb0CP+Op6+on0aKK3cJPCZ8d8QdURnQNMM8/2k8+vfRV4A PGg3Th+ezTYfEYkSj0QwN11C6mXeSWdWtR62j4g4B81yqc6QWfNr9bpM6wREQ0PrhCGD hBYWj97bjJH6zknsEApKg6vLI73EmK9jgoWY2+0b45xEq2Ny/jDDgIcsuGz4zgYNH+D0 YU2UywxdLJp4oNr6hDBF379vghLScSzuUQHDPEJW79dQlqI4J/4jgt3HE+8A1NU6JEHo 3wmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684850227; x=1687442227; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nI2w8QPEk+92crMZ+axm4/ERglLN4PhhZ5orQ1/925g=; b=d1JEoi2Y7FV83dvm6suJJqLSA1Ryj9O7ItcImgEa7Duokv0Xrh2YP8GUl9VBYwfFro wVRqnedG5bE/xnb1SKpNGkwKF9KsPqticJsm9cSGM7NEB8wppI5Yku6mHvJwnK8NJBYF 6wSVfFz5+aD2lBpv36txlWTB8/UYj/gaV9/6/InR5YI9us3YXDoDhN/y0OiyTKEGFYi5 pde0OkPWwP4jhdvHylaavOHGfoRaMKHG9ICCd1I1dIXhwWLtKJPPEHGxZCv7m5faGlTG +6QoMYJrtNV34vUjhNxOSYsMjG9UKj5QnECjbvC+2jMLEzLo+HopObZ8czvY3rQx1Nn4 ZxLg== X-Gm-Message-State: AC+VfDyIcP0d8HR2uuDOQPI7JwMDbeEVqyH9tCekDagSDo2EJxd5EKck IwOr/nw03MPV+ji1UEI42z7o5KV2W2puNMNUHKQ= X-Google-Smtp-Source: ACHHUZ4seqKdKG93f6idSOVuVFZdQh3tAS71RKcUorBD6gjXUG6nGtj1RItxKQhQnxQMVOgVOQNXAQ== X-Received: by 2002:a05:6a00:13a7:b0:63d:6744:8cae with SMTP id t39-20020a056a0013a700b0063d67448caemr17906298pfg.2.1684850227229; Tue, 23 May 2023 06:57:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 52/52] tcg: Build once for system and once for user-only Date: Tue, 23 May 2023 06:53:22 -0700 Message-Id: <20230523135322.678948-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1684851124133100002 Content-Type: text/plain; charset="utf-8" Create two static libraries for use by each execution mode. Signed-off-by: Richard Henderson --- tcg/meson.build | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/tcg/meson.build b/tcg/meson.build index bdc185a485..565c60bc96 100644 --- a/tcg/meson.build +++ b/tcg/meson.build @@ -1,3 +1,7 @@ +if not get_option('tcg').allowed() + subdir_done() +endif + tcg_ss =3D ss.source_set() =20 tcg_ss.add(files( @@ -14,8 +18,28 @@ tcg_ss.add(files( if get_option('tcg_interpreter') libffi =3D dependency('libffi', version: '>=3D3.0', required: true, method: 'pkg-config') - specific_ss.add(libffi) - specific_ss.add(files('tci.c')) + tcg_ss.add(libffi) + tcg_ss.add(files('tci.c')) endif =20 -specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss) +tcg_ss =3D tcg_ss.apply(config_host, strict: false) + +libtcg_user =3D static_library('tcg_user', + tcg_ss.sources() + genh, + name_suffix: 'fa', + c_args: '-DCONFIG_USER_ONLY', + build_by_default: have_user) + +tcg_user =3D declare_dependency(link_with: libtcg_user, + dependencies: tcg_ss.dependencies()) +user_ss.add(tcg_user) + +libtcg_softmmu =3D static_library('tcg_softmmu', + tcg_ss.sources() + genh, + name_suffix: 'fa', + c_args: '-DCONFIG_SOFTMMU', + build_by_default: have_system) + +tcg_softmmu =3D declare_dependency(link_with: libtcg_softmmu, + dependencies: tcg_ss.dependencies()) +softmmu_ss.add(tcg_softmmu) --=20 2.34.1