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charset="utf-8" Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Daniel Henrique Barboza --- hw/riscv/riscv_hart.c | 21 +++++++++++++++++++++ include/hw/riscv/riscv_hart.h | 4 ++++ target/riscv/cpu.c | 14 ++++++++++++++ target/riscv/cpu.h | 7 +++++++ target/riscv/cpu_bits.h | 12 ++++++++++++ target/riscv/cpu_helper.c | 24 ++++++++++++++++++++++++ 6 files changed, 82 insertions(+) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 613ea2aaa0..eac18f8c29 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -33,6 +33,12 @@ static Property riscv_harts_props[] =3D { DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec, DEFAULT_RSTVEC), + DEFINE_PROP_ARRAY("rnmi-interrupt-vector", RISCVHartArrayState, + num_rnmi_irqvec, rnmi_irqvec, qdev_prop_uint64, + uint64_t), + DEFINE_PROP_ARRAY("rnmi-exception-vector", RISCVHartArrayState, + num_rnmi_excpvec, rnmi_excpvec, qdev_prop_uint64, + uint64_t), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -47,6 +53,21 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, i= nt idx, { object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_typ= e); qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); + + if (s->harts[idx].cfg.ext_smrnmi) { + if (s->rnmi_irqvec) { + qdev_prop_set_uint64(DEVICE(&s->harts[idx]), + "rnmi-interrupt-vector", + s->rnmi_irqvec[idx]); + } + + if (s->rnmi_excpvec) { + qdev_prop_set_uint64(DEVICE(&s->harts[idx]), + "rnmi-exception-vector", + s->rnmi_excpvec[idx]); + } + } + s->harts[idx].env.mhartid =3D s->hartid_base + idx; qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp); diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index bbc21cdc9a..99c0ac5009 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -38,6 +38,10 @@ struct RISCVHartArrayState { uint32_t hartid_base; char *cpu_type; uint64_t resetvec; + uint32_t num_rnmi_irqvec; + uint64_t *rnmi_irqvec; + uint32_t num_rnmi_excpvec; + uint64_t *rnmi_excpvec; RISCVCPU *harts; }; =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index db0875fb43..39b74569b1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -119,6 +119,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), + ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), @@ -1404,6 +1405,12 @@ static void riscv_cpu_set_irq(void *opaque, int irq,= int level) g_assert_not_reached(); } } + +static void riscv_cpu_set_nmi(void *opaque, int irq, int level) +{ + RISCVCPU *cpu =3D RISCV_CPU(opaque); + riscv_cpu_set_rnmi(cpu, irq, level); +} #endif /* CONFIG_USER_ONLY */ =20 static void riscv_cpu_init(Object *obj) @@ -1420,6 +1427,8 @@ static void riscv_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); + qdev_init_gpio_in_named(DEVICE(cpu), riscv_cpu_set_nmi, + "riscv.cpu.rnmi", RNMI_MAX); #endif /* CONFIG_USER_ONLY */ } =20 @@ -1600,6 +1609,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), + DEFINE_PROP_BOOL("x-smrnmi", RISCVCPU, cfg.ext_smrnmi, false), =20 DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), @@ -1644,6 +1654,10 @@ static Property riscv_cpu_properties[] =3D { =20 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), + DEFINE_PROP_UINT64("rnmi-interrupt-vector", RISCVCPU, env.rnmi_irqvec, + DEFAULT_RNMI_IRQVEC), + DEFINE_PROP_UINT64("rnmi-exception-vector", RISCVCPU, env.rnmi_excpvec, + DEFAULT_RNMI_EXCPVEC), =20 /* * write_misa() is marked as experimental for now so mark diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de7e43126a..6c14b93cb5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -366,6 +366,11 @@ struct CPUArchState { uint64_t kvm_timer_compare; uint64_t kvm_timer_state; uint64_t kvm_timer_frequency; + + /* RNMI */ + target_ulong rnmip; + uint64_t rnmi_irqvec; + uint64_t rnmi_excpvec; }; =20 /* @@ -436,6 +441,7 @@ struct RISCVCPUConfig { bool ext_smaia; bool ext_ssaia; bool ext_sscofpmf; + bool ext_smrnmi; bool rvv_ta_all_1s; bool rvv_ma_all_1s; =20 @@ -562,6 +568,7 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, uint64_t value); +void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), void *arg); diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 59f0ffd9e1..7cb43b88f3 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -659,6 +659,12 @@ typedef enum { /* Default Reset Vector adress */ #define DEFAULT_RSTVEC 0x1000 =20 +/* Default RNMI Interrupt Vector address */ +#define DEFAULT_RNMI_IRQVEC 0x0 + +/* Default RNMI Exception Vector address */ +#define DEFAULT_RNMI_EXCPVEC 0x0 + /* Exception causes */ typedef enum RISCVException { RISCV_EXCP_NONE =3D -1, /* sentinel value */ @@ -705,6 +711,9 @@ typedef enum RISCVException { #define IRQ_LOCAL_MAX 16 #define IRQ_LOCAL_GUEST_MAX (TARGET_LONG_BITS - 1) =20 +/* RNMI causes */ +#define RNMI_MAX 16 + /* mip masks */ #define MIP_USIP (1 << IRQ_U_SOFT) #define MIP_SSIP (1 << IRQ_S_SOFT) @@ -896,6 +905,9 @@ typedef enum RISCVException { #define MHPMEVENT_IDX_MASK 0xFFFFF #define MHPMEVENT_SSCOF_RESVD 16 =20 +/* RISC-V-specific interrupt pending bits. */ +#define CPU_INTERRUPT_RNMI CPU_INTERRUPT_TGT_EXT_0 + /* JVT CSR bits */ #define JVT_MODE 0x3F #define JVT_BASE (~0x3F) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 57d04385f1..cc7898f103 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -635,6 +635,30 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint= 64_t mask, return old; } =20 +void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level) +{ + CPURISCVState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + bool locked =3D false; + + if (!qemu_mutex_iothread_locked()) { + locked =3D true; + qemu_mutex_lock_iothread(); + } + + if (level) { + env->rnmip |=3D 1 << irq; + cpu_interrupt(cs, CPU_INTERRUPT_RNMI); + } else { + env->rnmip &=3D ~(1 << irq); + cpu_reset_interrupt(cs, CPU_INTERRUPT_RNMI); + } + + if (locked) { + qemu_mutex_unlock_iothread(); + } +} + void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), void *arg) { --=20 2.31.1 From nobody Sat May 18 20:37:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1684761124; cv=none; d=zohomail.com; s=zohoarc; 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Date: Mon, 22 May 2023 06:11:21 -0700 Message-Id: <20230522131123.3498539-3-tommy.wu@sifive.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230522131123.3498539-1-tommy.wu@sifive.com> References: <20230522131123.3498539-1-tommy.wu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=tommy.wu@sifive.com; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1684761125973100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 5 +++ target/riscv/cpu.h | 4 ++ target/riscv/cpu_bits.h | 11 ++++++ target/riscv/csr.c | 82 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 102 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 39b74569b1..1b645c5485 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -810,6 +810,11 @@ static void riscv_cpu_reset_hold(Object *obj) riscv_trigger_init(env); } =20 + if (cpu->cfg.ext_smrnmi) { + env->rnmip =3D 0; + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, false); + } + if (kvm_enabled()) { kvm_riscv_reset_vcpu(cpu); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6c14b93cb5..f44fd95f16 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -368,6 +368,10 @@ struct CPUArchState { uint64_t kvm_timer_frequency; =20 /* RNMI */ + target_ulong mnscratch; + target_ulong mnepc; + target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */ + target_ulong mnstatus; target_ulong rnmip; uint64_t rnmi_irqvec; uint64_t rnmi_excpvec; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7cb43b88f3..d7bd4538ab 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -355,6 +355,12 @@ #define CSR_PMPADDR14 0x3be #define CSR_PMPADDR15 0x3bf =20 +/* RNMI */ +#define CSR_MNSCRATCH 0x740 +#define CSR_MNEPC 0x741 +#define CSR_MNCAUSE 0x742 +#define CSR_MNSTATUS 0x744 + /* Debug/Trace Registers (shared with Debug Mode) */ #define CSR_TSELECT 0x7a0 #define CSR_TDATA1 0x7a1 @@ -624,6 +630,11 @@ typedef enum { #define SATP64_ASID 0x0FFFF00000000000ULL #define SATP64_PPN 0x00000FFFFFFFFFFFULL =20 +/* RNMI mnstatus CSR mask */ +#define MNSTATUS_NMIE 0x00000008 +#define MNSTATUS_MNPV 0x00000080 +#define MNSTATUS_MNPP 0x00001800 + /* VM modes (satp.mode) privileged ISA 1.10 */ #define VM_1_10_MBARE 0 #define VM_1_10_SV32 1 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4451bd1263..a1d39fc116 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -536,6 +536,18 @@ static RISCVException debug(CPURISCVState *env, int cs= rno) =20 return RISCV_EXCP_ILLEGAL_INST; } + +static RISCVException rnmi(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + if (cpu->cfg.ext_smrnmi) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} + #endif =20 static RISCVException seed(CPURISCVState *env, int csrno) @@ -2336,6 +2348,66 @@ static RISCVException rmw_miph(CPURISCVState *env, i= nt csrno, return ret; } =20 +static int read_mnscratch(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mnscratch; + return RISCV_EXCP_NONE; +} + +static int write_mnscratch(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnscratch =3D val; + return RISCV_EXCP_NONE; +} + +static int read_mnepc(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mnepc; + return RISCV_EXCP_NONE; +} + +static int write_mnepc(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnepc =3D val; + return RISCV_EXCP_NONE; +} + +static int read_mncause(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mncause; + return RISCV_EXCP_NONE; +} + +static int write_mncause(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mncause =3D val; + return RISCV_EXCP_NONE; +} + +static int read_mnstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mnstatus; + return RISCV_EXCP_NONE; +} + +static int write_mnstatus(CPURISCVState *env, int csrno, target_ulong val) +{ + target_ulong mask =3D (MNSTATUS_NMIE | MNSTATUS_MNPP); + + if (riscv_has_ext(env, RVH)) { + /* Flush tlb on mnstatus fields that affect VM. */ + if ((val ^ env->mnstatus) & MNSTATUS_MNPV) { + tlb_flush(env_cpu(env)); + } + + mask |=3D MNSTATUS_MNPV; + } + + /* mnstatus.mnie can only be cleared by hardware. */ + env->mnstatus =3D (env->mnstatus & MNSTATUS_NMIE) | (val & mask); + return RISCV_EXCP_NONE; +} + /* Supervisor Trap Setup */ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, Int128 *val) @@ -4204,6 +4276,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { write_sstateen_1_3, .min_priv_ver =3D PRIV_VERSION_1_12_0 }, =20 + /* RNMI */ + [CSR_MNSCRATCH] =3D { "mnscratch", rnmi, read_mnscratch, write_mnscrat= ch, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MNEPC] =3D { "mnepc", rnmi, read_mnepc, write_mnepc, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MNCAUSE] =3D { "mncause", rnmi, read_mncause, write_mncause, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MNSTATUS] =3D { "mnstatus", rnmi, read_mnstatus, write_mnstatu= s, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus, NULL, read_sstatus_i128 = }, --=20 2.31.1 From nobody Sat May 18 20:37:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 22 May 2023 06:11:33 -0700 (PDT) From: Tommy Wu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, Tommy Wu Subject: [PATCH v3 3/4] target/riscv: Handle Smrnmi interrupt and exception. Date: Mon, 22 May 2023 06:11:22 -0700 Message-Id: <20230522131123.3498539-4-tommy.wu@sifive.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230522131123.3498539-1-tommy.wu@sifive.com> References: <20230522131123.3498539-1-tommy.wu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=tommy.wu@sifive.com; helo=mail-ot1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1684761123230100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- target/riscv/cpu_helper.c | 60 +++++++++++++++++++++++++++++++++++---- 1 file changed, 55 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index cc7898f103..7bdea0d2ca 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -405,6 +405,19 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *= env) { int virq; uint64_t irqs, pending, mie, hsie, vsie; + RISCVCPU *cpu =3D env_archcpu(env); + + /* Priority: RNMI > Other interrupt. */ + if (cpu->cfg.ext_smrnmi) { + /* If mnstatus.NMIE =3D=3D 0, all interrupts are disabled. */ + if (!get_field(env->mnstatus, MNSTATUS_NMIE)) { + return RISCV_EXCP_NONE; + } + + if (env->rnmip) { + return ctz64(env->rnmip); /* since non-zero */ + } + } =20 /* Determine interrupt enable state of all privilege modes */ if (env->virt_enabled) { @@ -451,7 +464,9 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *e= nv) =20 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { - if (interrupt_request & CPU_INTERRUPT_HARD) { + uint32_t mask =3D CPU_INTERRUPT_HARD | CPU_INTERRUPT_RNMI; + + if (interrupt_request & mask) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; int interruptno =3D riscv_cpu_local_irq_pending(env); @@ -1613,6 +1628,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) CPURISCVState *env =3D &cpu->env; bool write_gva =3D false; uint64_t s; + int mode; =20 /* * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide @@ -1625,6 +1641,22 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong tinst =3D 0; target_ulong htval =3D 0; target_ulong mtval2 =3D 0; + bool nmi_execp =3D false; + + if (cpu->cfg.ext_smrnmi) { + if (env->rnmip && async) { + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, fals= e); + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPV, + env->virt_enabled); + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPP, + env->priv); + env->mncause =3D cause | ((target_ulong)1U << (TARGET_LONG_BIT= S - 1)); + env->mnepc =3D env->pc; + env->pc =3D env->rnmi_irqvec; + riscv_cpu_set_mode(env, PRV_M); + goto handled; + } + } =20 if (cause =3D=3D RISCV_EXCP_SEMIHOST) { do_common_semihosting(cs); @@ -1711,8 +1743,20 @@ void riscv_cpu_do_interrupt(CPUState *cs) __func__, env->mhartid, async, cause, env->pc, tval, riscv_cpu_get_trap_name(cause, async)); =20 - if (env->priv <=3D PRV_S && - cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { + mode =3D env->priv <=3D PRV_S && + cause < TARGET_LONG_BITS && ((deleg >> cause) & 1) ? PRV_S : PRV_M; + + /* + * If the hart encounters an exception while executing in M-mode, + * with the mnstatus.NMIE bit clear, the program counter is set to + * the RNMI exception trap handler address. + */ + nmi_execp =3D cpu->cfg.ext_smrnmi && + !get_field(env->mnstatus, MNSTATUS_NMIE) && + !async && + mode =3D=3D PRV_M; + + if (mode =3D=3D PRV_S) { /* handle the trap in S-mode */ if (riscv_has_ext(env, RVH)) { uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; @@ -1787,8 +1831,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mtval =3D tval; env->mtval2 =3D mtval2; env->mtinst =3D tinst; - env->pc =3D (env->mtvec >> 2 << 2) + - ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); + if (cpu->cfg.ext_smrnmi && nmi_execp) { + env->pc =3D env->rnmi_excpvec; + } else { + env->pc =3D (env->mtvec >> 2 << 2) + + ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : = 0); + } riscv_cpu_set_mode(env, PRV_M); } =20 @@ -1801,6 +1849,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) =20 env->two_stage_lookup =3D false; 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Mon, 22 May 2023 06:11:35 -0700 (PDT) From: Tommy Wu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org, Tommy Wu Subject: [PATCH v3 4/4] target/riscv: Add Smrnmi mnret instruction. Date: Mon, 22 May 2023 06:11:23 -0700 Message-Id: <20230522131123.3498539-5-tommy.wu@sifive.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230522131123.3498539-1-tommy.wu@sifive.com> References: <20230522131123.3498539-1-tommy.wu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=tommy.wu@sifive.com; helo=mail-ot1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1684761148177100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Frank Chang Signed-off-by: Tommy Wu --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 3 ++ .../riscv/insn_trans/trans_privileged.c.inc | 12 +++++ target/riscv/op_helper.c | 51 +++++++++++++++++++ 4 files changed, 67 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 98e97810fd..00f1032086 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -112,6 +112,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(sret, tl, env) DEF_HELPER_1(mret, tl, env) +DEF_HELPER_1(mnret, tl, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(tlb_flush, void, env) DEF_HELPER_1(tlb_flush_all, void, env) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 73d5d1b045..e0698f9dfb 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -111,6 +111,9 @@ wfi 0001000 00101 00000 000 00000 1110011 sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm =20 +# *** NMI *** +mnret 0111000 00010 00000 000 00000 1110011 + # *** RV32I Base Instruction Set *** lui .................... ..... 0110111 @u auipc .................... ..... 0010111 @u diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index 7c2837194c..0c1c2db5c6 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -108,6 +108,18 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a) #endif } =20 +static bool trans_mnret(DisasContext *ctx, arg_mnret *a) +{ +#ifndef CONFIG_USER_ONLY + gen_helper_mnret(cpu_pc, cpu_env); + tcg_gen_exit_tb(NULL, 0); /* no chaining */ + ctx->base.is_jmp =3D DISAS_NORETURN; + return true; +#else + return false; +#endif +} + static bool trans_wfi(DisasContext *ctx, arg_wfi *a) { #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index f563dc3981..2de3f102b5 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -359,6 +359,57 @@ target_ulong helper_mret(CPURISCVState *env) return retpc; } =20 +target_ulong helper_mnret(CPURISCVState *env) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + if (!cpu->cfg.ext_smrnmi) { + /* RNMI feature is not presented. */ + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + if (!(env->priv >=3D PRV_M)) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + /* Get return PC from mnepc CSR. */ + target_ulong retpc =3D env->mnepc; + if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) { + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); + } + + /* Get previous privilege level from mnstatus CSR. */ + target_ulong prev_priv =3D get_field(env->mnstatus, MNSTATUS_MNPP); + + if (cpu->cfg.pmp && + !pmp_get_num_rules(env) && (prev_priv !=3D PRV_M)) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + riscv_cpu_set_mode(env, prev_priv); + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, true); + + target_ulong prev_virt =3D get_field(env->mnstatus, MNSTATUS_MNPV); + + /* + * If MNRET changes the privilege mode to a mode + * less privileged than M, it also sets mstatus.MPRV to 0. + */ + if (prev_priv < PRV_M) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_MPRV, false); + } + + if (riscv_has_ext(env, RVH)) { + if (prev_virt) { + riscv_cpu_swap_hypervisor_regs(env); + } + + riscv_cpu_set_virt_enabled(env, prev_virt); + } + + return retpc; +} + void helper_wfi(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); --=20 2.31.1