From nobody Sat May 18 10:07:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1684331955; cv=none; d=zohomail.com; s=zohoarc; b=JRW+oaBU8bhbQmT6v/aIbJjOJGANmPTPLqzmcALfzFGq3Ofto5pbE50I5Rcrerf+NwU43dBO7gHn/iEEnn8yUn1BN3n6IXOOJBDzTEl8Qsi+ceJ2OuzdwQnda8GnOENoAVCY8B/oa+iNPZlRInGosiFK8Ig3NEwucZmrh3GA5KU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684331955; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0/REJdOy6wXsH3mtIDXTGps7VFdkDX4BIyrwNm0mndU=; b=lTfaJIvaHAVRsXaZQMgNc+kLBDJ/MfJparvT+y5HSsI+doAsrB2LS1p4hiYWWtQB7epodnQfL7Wt3sbJZtCev0UOQGL8eELwCAG7HU2AUpV7hLbc6lsG1IiMy/Nv0TcR5gQrCJyIpoZtcsKwrl/D5OtXanfFV9IKNFiS0csCBFQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684331955723105.47856094424583; Wed, 17 May 2023 06:59:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzHen-0000x5-0n; Wed, 17 May 2023 09:57:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzHek-0000wg-TU for qemu-devel@nongnu.org; Wed, 17 May 2023 09:57:30 -0400 Received: from mail-oi1-x235.google.com ([2607:f8b0:4864:20::235]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pzHei-0000UB-Ma for qemu-devel@nongnu.org; Wed, 17 May 2023 09:57:30 -0400 Received: by mail-oi1-x235.google.com with SMTP id 5614622812f47-3941c3ba226so558911b6e.0 for ; Wed, 17 May 2023 06:57:28 -0700 (PDT) Received: from grind.. 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[189.46.207.53]) by smtp.gmail.com with ESMTPSA id j21-20020a544815000000b00383d9700294sm9409562oij.40.2023.05.17.06.57.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 06:57:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1684331847; x=1686923847; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0/REJdOy6wXsH3mtIDXTGps7VFdkDX4BIyrwNm0mndU=; b=GNxPOLSCBpYmSC1jnYicd+yKlWg/bOxCwS3rJrbruocnHujrB+Ufkdc+Ql8KaZl01E 40myg8kdnaRrd64iTE41sKUMMN9lGJ8eZTC1cs23tGj+LgZbfSnLtpgQms8pGbohUo6Q Fv/YkkWjqXyM2euUXFB8s7hOWm6x6yGGm7bnTun4nrT0G7fCIExwP537q/asjZgjiioa AhB7l13eENIVC/eTduaVn+o2EcPggbH7UtmlhUUFi2/Tx8wwMMEE1z1odeZYBZLen/nJ dac6u7ATTkfuSsF14769yscPKNSJaiAsHH1NwUYhWRQVRt+vgTxVge+xtX7k+YEZoEG4 SUvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684331847; x=1686923847; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0/REJdOy6wXsH3mtIDXTGps7VFdkDX4BIyrwNm0mndU=; b=cqofPFb+MoXyHP61zlyBU5A54nzvoKz7zx3K6/ngrn0MIy4vmN6MCKLsLkhGDl0SrO by+hjpF38LWKsUpwGQHBnycTQtXLp2vYOSWzjU3aTmOzIHYv1iB80Mm1CYdnVOe3d6JS GczmqVLNnvNC9HKkEaxihzavUj/g9G6hSsRp99xGkkcvcMJks9zk6qzXzPxWuMJezyRv +sYA5SB+E4+RyasutIEHCV+Ag0pPQiM2+LHDE3S/ByivVVcErJ7zwfR201lvKT0AydhD pAwsdOHbd74twznXEqnJFZpqSpRMU1DgVb7kVrP53I+YMYzIIZhWzWlWRBV8NHuqsGSO xw9g== X-Gm-Message-State: AC+VfDyMSTi610BsxtsCJcfLVePvD+Eau7aY/x1XyoplTfzJpfScPiuI /UibvZS1cwCPuvmUqepPiIL4nT7OgyeirD/4c8g= X-Google-Smtp-Source: ACHHUZ6MtgtoV5z9OXhkDo8wMsGY9JZM3wam0fMR/sliK3N7iP9pCuE5jixm7IfllCbuGzisKFhqzA== X-Received: by 2002:a05:6808:140b:b0:396:4890:adc9 with SMTP id w11-20020a056808140b00b003964890adc9mr780432oiv.6.1684331847293; Wed, 17 May 2023 06:57:27 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v9 01/11] target/riscv/cpu.c: add riscv_cpu_validate_v() Date: Wed, 17 May 2023 10:57:04 -0300 Message-Id: <20230517135714.211809-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230517135714.211809-1-dbarboza@ventanamicro.com> References: <20230517135714.211809-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1684331956747100001 Content-Type: text/plain; charset="utf-8" The RVV verification will error out if fails and it's being done at the end of riscv_cpu_validate_set_extensions(), after we've already set some extensions that are dependent on RVV. Let's put it in its own function and do it earlier. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 89 +++++++++++++++++++++++++--------------------- 1 file changed, 48 insertions(+), 41 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index db0875fb43..4e6de82afa 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -834,6 +834,46 @@ static void riscv_cpu_disas_set_info(CPUState *s, disa= ssemble_info *info) } } =20 +static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, + Error **errp) +{ + int vext_version =3D VEXT_VERSION_1_00_0; + + if (!is_power_of_2(cfg->vlen)) { + error_setg(errp, "Vector extension VLEN must be power of 2"); + return; + } + if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { + error_setg(errp, + "Vector extension implementation only supports VLEN " + "in the range [128, %d]", RV_VLEN_MAX); + return; + } + if (!is_power_of_2(cfg->elen)) { + error_setg(errp, "Vector extension ELEN must be power of 2"); + return; + } + if (cfg->elen > 64 || cfg->elen < 8) { + error_setg(errp, + "Vector extension implementation only supports ELEN " + "in the range [8, 64]"); + return; + } + if (cfg->vext_spec) { + if (!g_strcmp0(cfg->vext_spec, "v1.0")) { + vext_version =3D VEXT_VERSION_1_00_0; + } else { + error_setg(errp, "Unsupported vector spec version '%s'", + cfg->vext_spec); + return; + } + } else { + qemu_log("vector version is not specified, " + "use the default value v1.0\n"); + } + set_vext_version(env, vext_version); +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -841,6 +881,7 @@ static void riscv_cpu_disas_set_info(CPUState *s, disas= semble_info *info) static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; + Error *local_err =3D NULL; =20 /* Do some ISA extension error checking */ if (riscv_has_ext(env, RVG) && @@ -909,8 +950,14 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU= *cpu, Error **errp) return; } =20 - /* The V vector extension depends on the Zve64d extension */ if (riscv_has_ext(env, RVV)) { + riscv_cpu_validate_v(env, &cpu->cfg, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + + /* The V vector extension depends on the Zve64d extension */ cpu->cfg.ext_zve64d =3D true; } =20 @@ -1045,46 +1092,6 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) cpu->cfg.ext_zksed =3D true; cpu->cfg.ext_zksh =3D true; } - - if (riscv_has_ext(env, RVV)) { - int vext_version =3D VEXT_VERSION_1_00_0; - if (!is_power_of_2(cpu->cfg.vlen)) { - error_setg(errp, - "Vector extension VLEN must be power of 2"); - return; - } - if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { - error_setg(errp, - "Vector extension implementation only supports VLEN= " - "in the range [128, %d]", RV_VLEN_MAX); - return; - } - if (!is_power_of_2(cpu->cfg.elen)) { - error_setg(errp, - "Vector extension ELEN must be power of 2"); - return; - } - if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { - error_setg(errp, - "Vector extension implementation only supports ELEN= " - "in the range [8, 64]"); - return; - } - if (cpu->cfg.vext_spec) { - if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { - vext_version =3D VEXT_VERSION_1_00_0; - } else { - error_setg(errp, - "Unsupported vector spec version '%s'", - cpu->cfg.vext_spec); - return; - } - } else { - qemu_log("vector version is not specified, " - "use the default value v1.0\n"); - } - set_vext_version(env, vext_version); - } } =20 #ifndef CONFIG_USER_ONLY --=20 2.40.1 From nobody Sat May 18 10:07:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1684331870; cv=none; d=zohomail.com; s=zohoarc; b=MYBxBbXeMg/Q+C21UgNyVKLEwL+NHC284gCiFiuB1n8Bk3ayt6QG3rYA0P8Ka/IVb2Z9+YPah2WGT418INdsIqHeGvSst5crE2TEzkhkz4TraQYlsntQMIoIDN0N0WmD3qwQJJKPrJk/uRKLFH+1jnvP9qY2kYJzo+hL9VLYltg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[189.46.207.53]) by smtp.gmail.com with ESMTPSA id j21-20020a544815000000b00383d9700294sm9409562oij.40.2023.05.17.06.57.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 06:57:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1684331850; x=1686923850; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GAiO4x83ijNy4ajX2j8DN3y60DdS3AGTCOKSTObnjs0=; b=hhRoaTUM3UJU6ZJrmIxH4b17wQkbI8Ib7Cycglor159Mh59+vcCMOR2BL+9iMaOp++ o0+SqAdXqArkLZ3VyzDIMWILdD4QIsiE7qrQpMbPo3PEWqZqR3wdKXoAQv69Mut483R9 gBc1XexY1O3qPERMVVeeVa9lQGu7eHF2QOi6r/HZQ0eeNSGz8vl6nJIATViSMDJgz/nm JoKLUr2lzn9AC19KzhfEHPoRq11iBtQCJmzQ2o0WIAEQQkhJ6AROJ/fqLXah8xo1NZms +vu/HbIvfo+8i5YB1Br/kaVsw7eqIne9Q325mhvTYPvJeyfxDducx3yXJlA1MzCLbEke Tb8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684331850; x=1686923850; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GAiO4x83ijNy4ajX2j8DN3y60DdS3AGTCOKSTObnjs0=; b=SL+qoshoHKP3T4IJeSdYbGu7zHLy37S5OZJKfOE3Ku30IzI5OC1uOp1Hz1H1o39N2l gHyeWoURMXjDARFc8Qs2A8DFFxolvZOebT/0/Jw/HyHdOPMCBhZpZd/0I7AzKOxrRiY1 5GUjvRgSQVNftFJdXPgEDwf58c6e4F4Py77uMqbzEEyeUhUAB73Y5JR80NJa2UDoe6a7 wn3QCX452cCiLKlMjmEzalQMVv60varBYgmKCqOoOSTDyzHsQtgQan5ajpVvdUvMwSU4 vts/EBS3Iezmo2/BBGlJa80pBKo0k5BwIn/0J4EBi51+KkhJtNrLkeYj4X/4yBBzXs5L sVTA== X-Gm-Message-State: AC+VfDwqacKiJ8TF6slGChwOnVia6+324KS79KulAa4zT3sFz54AMsVQ UUEoTBRXR0SEt6bBwTcLqyufjsSOEezFGjy+PNQ= X-Google-Smtp-Source: ACHHUZ4kQNdIb3rX9W60cuvgg58VHjZMxo41rbn/zTSJyWVCXByQSxe1kHvW6q3CxjF6E6xBJ8CJWA== X-Received: by 2002:a05:6808:1415:b0:395:f484:78bb with SMTP id w21-20020a056808141500b00395f48478bbmr8235519oiv.13.1684331849935; Wed, 17 May 2023 06:57:29 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v9 02/11] target/riscv/cpu.c: remove set_vext_version() Date: Wed, 17 May 2023 10:57:05 -0300 Message-Id: <20230517135714.211809-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230517135714.211809-1-dbarboza@ventanamicro.com> References: <20230517135714.211809-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1684331872351100001 Content-Type: text/plain; charset="utf-8" This setter is doing nothing else but setting env->vext_ver. Assign the value directly. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4e6de82afa..bb7522bb3e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -252,11 +252,6 @@ static void set_priv_version(CPURISCVState *env, int p= riv_ver) env->priv_ver =3D priv_ver; } =20 -static void set_vext_version(CPURISCVState *env, int vext_ver) -{ - env->vext_ver =3D vext_ver; -} - #ifndef CONFIG_USER_ONLY static uint8_t satp_mode_from_str(const char *satp_mode_str) { @@ -871,7 +866,7 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RI= SCVCPUConfig *cfg, qemu_log("vector version is not specified, " "use the default value v1.0\n"); } - set_vext_version(env, vext_version); + env->vext_ver =3D vext_version; } =20 /* --=20 2.40.1 From nobody Sat May 18 10:07:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1684331979; cv=none; d=zohomail.com; s=zohoarc; b=JtavViHpl+aGxL+1BiP100JZ/pGIbw6V6j/fR8aQMeiuDXSAONOV+3bQ0HncDms7OESc4ZSwOmojK0Oaddtpp8oAmbVW4vbJqQFjhKq3B+OTh3MAZptNlR7NTb+cwfDpfiKahv3ajaw7GLmzFDTONZjBmRtyMg91riHVJtrL8jU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684331979; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=P29BBl7ZaC0EgtGQcMzwXQB97vtm4udpd6UulJvMR8w=; b=f4CaxBSJ/W3ZGKMUWJRwLGqHsKvDZef5xiydJXfX79AWHZky2g+EAGbQR1TjXk3nZRpt1xco4g1NSD7KqTeV+uIdCKiZpr8nX45U1N55sCRLEq1i+IqMJVS9WdS7Lchj47wMWLcNpVlVXOdr3IFJ6pnyCa0x/HvnKD5s/MeQ/Tg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684331978990838.0021895094948; Wed, 17 May 2023 06:59:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzHf0-00011v-QQ; Wed, 17 May 2023 09:57:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzHev-0000zt-87 for qemu-devel@nongnu.org; Wed, 17 May 2023 09:57:44 -0400 Received: from mail-oi1-x22e.google.com ([2607:f8b0:4864:20::22e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pzHeo-0000V9-Co for qemu-devel@nongnu.org; Wed, 17 May 2023 09:57:39 -0400 Received: by mail-oi1-x22e.google.com with SMTP id 5614622812f47-3942cd86697so485355b6e.0 for ; Wed, 17 May 2023 06:57:34 -0700 (PDT) Received: from grind.. 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[189.46.207.53]) by smtp.gmail.com with ESMTPSA id j21-20020a544815000000b00383d9700294sm9409562oij.40.2023.05.17.06.57.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 06:57:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1684331852; x=1686923852; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P29BBl7ZaC0EgtGQcMzwXQB97vtm4udpd6UulJvMR8w=; b=OLWKNPnmFE3+ibviK8y2JT0gDoAxVg3kyWbb4BlL7s9CogmUDg/Qd6exXdYjCxMn9P rpjsjj1H88ekHYj8PzEjRWccj9lTg4bQgbVOERvohcDcpKS49rJj+EGA3xm6p8EB3PuD Y+yHJ5ZVA6Iss9p94lxBR07vL6+zfx1UFyn6DB1ihxKlnnd0A3+zfA+c6HzM1+q1UKHD iIl0eFuJrupXcA/OljZyiavaHELU/PdacR28NzaCbDOhJJCzODntcmWpVxH8aqz5qOJI kzPdY2cJSc/2/iPnh0VE3BP3o1axfcmR6DXl67rlvIrYaKgCjSEE3Qd2qIRKES0Xq9hG ZrjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684331852; x=1686923852; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P29BBl7ZaC0EgtGQcMzwXQB97vtm4udpd6UulJvMR8w=; b=EounDKavcX9mOozLp9hluq7HuZKn76peksg610KzxMhBAol18rdlqeyYli/0rwTHjF hcsYP5ZxDm+VlQ+m4umh1mQiEvpMDcR7CXHgUUGskhMLGKX+Ghmm+hTqb9HQvyZhoDqo B2vrNMw+yXLn46HC8ftxcbZTocgXU9nVnRYzDtN1pdpDabkEMShzCwjafBA4FMFcO0IH iaS6fRiamAv1hAtcaham4jWbOfseG1CIvvqCOzfiMeznErRWSZcnKGdlHyJNgc6tm6P0 ypQ7I2V6ACCKY+2GNy9FScoM1sEkepnYRV9PhHE4kMZor97fFjiMeEVJIcCk0GLF3XIe ckHw== X-Gm-Message-State: AC+VfDxu2dMgw7lnzznxXeafa1JZVnOnYmCk0wJjqvzxHQpYhENPDOdW lCb3A69a7Z6KzA0GYB6WzM+g7rQ8ObOhGOKWqJ8= X-Google-Smtp-Source: ACHHUZ53PRY7RyedgA3G7s2KUgoLHAg3e4OwGR7OMXTRdvtF/Gz9jqBU9RYi0EeRgSeVJZcnWy0BaQ== X-Received: by 2002:aca:dfc6:0:b0:395:eb6c:6334 with SMTP id w189-20020acadfc6000000b00395eb6c6334mr6761748oig.32.1684331852658; Wed, 17 May 2023 06:57:32 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v9 03/11] target/riscv/cpu.c: remove set_priv_version() Date: Wed, 17 May 2023 10:57:06 -0300 Message-Id: <20230517135714.211809-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230517135714.211809-1-dbarboza@ventanamicro.com> References: <20230517135714.211809-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1684331980235100001 Content-Type: text/plain; charset="utf-8" The setter is doing nothing special. Just set env->priv_ver directly. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 29 ++++++++++++----------------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bb7522bb3e..8ba86d54b2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -247,11 +247,6 @@ static void set_misa(CPURISCVState *env, RISCVMXL mxl,= uint32_t ext) env->misa_ext_mask =3D env->misa_ext =3D ext; } =20 -static void set_priv_version(CPURISCVState *env, int priv_ver) -{ - env->priv_ver =3D priv_ver; -} - #ifndef CONFIG_USER_ONLY static uint8_t satp_mode_from_str(const char *satp_mode_str) { @@ -350,7 +345,7 @@ static void riscv_any_cpu_init(Object *obj) VM_1_10_SV32 : VM_1_10_SV57); #endif =20 - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver =3D PRIV_VERSION_1_12_0; } =20 #if defined(TARGET_RISCV64) @@ -361,7 +356,7 @@ static void rv64_base_cpu_init(Object *obj) set_misa(env, MXL_RV64, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver =3D PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -371,7 +366,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); #endif @@ -383,7 +378,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -396,7 +391,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_11_0); + env->priv_ver =3D PRIV_VERSION_1_11_0; =20 cpu->cfg.ext_zfh =3D true; cpu->cfg.mmu =3D true; @@ -467,7 +462,7 @@ static void rv128_base_cpu_init(Object *obj) set_misa(env, MXL_RV128, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver =3D PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -480,7 +475,7 @@ static void rv32_base_cpu_init(Object *obj) set_misa(env, MXL_RV32, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver =3D PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif @@ -490,7 +485,7 @@ static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif @@ -502,7 +497,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -515,7 +510,7 @@ static void rv32_ibex_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_11_0); + env->priv_ver =3D PRIV_VERSION_1_11_0; cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -529,7 +524,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -1211,7 +1206,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) } =20 if (priv_version >=3D PRIV_VERSION_1_10_0) { - set_priv_version(env, priv_version); + env->priv_ver =3D priv_version; } =20 riscv_cpu_validate_misa_priv(env, &local_err); --=20 2.40.1 From nobody Sat May 18 10:07:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1684331895; cv=none; d=zohomail.com; s=zohoarc; b=WDtMtIhVgQ1+IiSkvF5VKmXXPLdSi9OFSpKS10TI0nDYcOQQWCDbKwuhej7q3WKAda4IojbM5HLD5k263ict3x4MFpgXyusR7WxPG/ASfmUYY+mj4ZA/6he/magw5UCvYPh52cy/o1QMDPk8kiokfj5Gpd3C5Y8+Rp+NZDy60vc= ARC-Message-Signature: i=1; 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[189.46.207.53]) by smtp.gmail.com with ESMTPSA id j21-20020a544815000000b00383d9700294sm9409562oij.40.2023.05.17.06.57.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 06:57:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1684331855; x=1686923855; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+AzVR8nq7ycPyzgqq+Qc5hSUqVlyii/kLSoYn9cWTds=; b=EgWqCL4Lfz2L0xemboHv33FDhXox7Fo4l7TM2wNLBQBXRqqcwDo2RhDfXBW1ZBSfEy WURm6bL+njYEsl1AWCtjmk1oftHZsY7LxR6LJcDv5x6vOg/tFK5XyR+Jx357dzp5d9ME R0XQzZdAkVhExVenTORFn5KAfJcCknQxMdHYVdlw0oNmDb8p9Y4NbJpyMf+OPNryxOwc F3zyRtdXeQ2HefIEai+snKABRqNSJFnp7Da2Xnmdhw/6PNc3thZgeNMj3vCeMErqGlNl LVspRQOq78rYqCcUgJ1FX/MLahPdBGV4Cd3hKC44xl10P1eHve1pOzZdvH6VwzO8TPzf xAyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684331855; x=1686923855; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+AzVR8nq7ycPyzgqq+Qc5hSUqVlyii/kLSoYn9cWTds=; b=DxOJ8j1+kb1FZ0gDboV52WYLrNDLKB/eH8+JB4qL703pTiA0KHCw0zV6E/C+gtwA2Q Nj5CE9+gsIYObiAvDkPqfhBopXmoeYMPKpTw9ZCFpGRALP1SQ70FpJvVS0A6LjgheZqT BmT5TXbWCajSHnVIKAGvBnvRLtHmaOp5MNxr3HAXXnHeQZr8JYUpcXowX+abFq3nqsrX Xg1+aJAc78Jttvr8r1K4UXnaB6EztPtt3muJlSdYNvFGThAw9pC6VbEcGI2l/ShluAzw BG2F+1aTnbwW1W0Rbf9VVwJxjDciM2SyLm2xF8waDzKxcHEDqEXTTGCtMDE6g/DwLb2F jNDQ== X-Gm-Message-State: AC+VfDwgCeWlQpCP6+pajYe/aFVc0CIf6FW0FGprKVmtP1KBkeyDnaYs fueYCXzWxnULckSxUTDRy+bySVyf+BPl9tlHs+E= X-Google-Smtp-Source: ACHHUZ4tCaHFD48fbUulD1Hqj74bXE2DkUclmKn5t77AwcpwUQ/VhwX4hOCqFrEEVSNo6txv5WzSdQ== X-Received: by 2002:a05:6808:4cf:b0:38d:ec3f:3118 with SMTP id a15-20020a05680804cf00b0038dec3f3118mr12894072oie.28.1684331855661; Wed, 17 May 2023 06:57:35 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Richard Henderson Subject: [PATCH v9 04/11] target/riscv: add PRIV_VERSION_LATEST Date: Wed, 17 May 2023 10:57:07 -0300 Message-Id: <20230517135714.211809-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230517135714.211809-1-dbarboza@ventanamicro.com> References: <20230517135714.211809-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1684331896414100001 Content-Type: text/plain; charset="utf-8" All these generic CPUs are using the latest priv available, at this moment PRIV_VERSION_1_12_0: - riscv_any_cpu_init() - rv32_base_cpu_init() - rv64_base_cpu_init() - rv128_base_cpu_init() Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll make it easier to update everything at once when a new priv version is available. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 8 ++++---- target/riscv/cpu.h | 2 ++ 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8ba86d54b2..b1a6675d1e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -345,7 +345,7 @@ static void riscv_any_cpu_init(Object *obj) VM_1_10_SV32 : VM_1_10_SV57); #endif =20 - env->priv_ver =3D PRIV_VERSION_1_12_0; + env->priv_ver =3D PRIV_VERSION_LATEST; } =20 #if defined(TARGET_RISCV64) @@ -356,7 +356,7 @@ static void rv64_base_cpu_init(Object *obj) set_misa(env, MXL_RV64, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_1_12_0; + env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -462,7 +462,7 @@ static void rv128_base_cpu_init(Object *obj) set_misa(env, MXL_RV128, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_1_12_0; + env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -475,7 +475,7 @@ static void rv32_base_cpu_init(Object *obj) set_misa(env, MXL_RV32, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_1_12_0; + env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de7e43126a..15423585d0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -61,6 +61,8 @@ enum { PRIV_VERSION_1_10_0 =3D 0, PRIV_VERSION_1_11_0, PRIV_VERSION_1_12_0, + + PRIV_VERSION_LATEST =3D PRIV_VERSION_1_12_0, }; =20 #define VEXT_VERSION_1_00_0 0x00010000 --=20 2.40.1 From nobody Sat May 18 10:07:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1684331944; cv=none; d=zohomail.com; s=zohoarc; b=IS9mYj1tz1nmXGGVNpcj/ohj66zsLy98jOj5muIfBvPZ6J2NFdqa5j4qVTrAGGJTHX4/mylL4zirhywKZhg2pnhFzaWw+H3OZVniW0OwsvIIlHN8KSGp6g1Foi9l1pxMYUs0BSsMiSxelL5FcJifEWpqIxsbLVRu35SCZzN8amQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684331944; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lMnHi4+vBadWo5A/+JSdVRCwH4evlrvC8EDyRoJWt8w=; b=EEfLBj8s/2KPPnjXh1hDamPKMfoprrDjxHGxIEaf/fE9MEmFXw+kRAbt8wVbXl2G+VoSfJlMLE4kLlJx7tpFt83Kmwzr8cShvXhw/y/96MSy50J3ibmL8JMh8GI05lKXt2HopsnVjOKeoAmTjEBmnbg+1+HnJLpWkRfIMQGdMiE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684331944273801.4628688489074; Wed, 17 May 2023 06:59:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzHf0-00011s-JX; Wed, 17 May 2023 09:57:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzHex-00010A-UI for qemu-devel@nongnu.org; Wed, 17 May 2023 09:57:44 -0400 Received: from mail-oi1-x234.google.com ([2607:f8b0:4864:20::234]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pzHeu-0000Vs-WD for qemu-devel@nongnu.org; Wed, 17 May 2023 09:57:42 -0400 Received: by mail-oi1-x234.google.com with SMTP id 5614622812f47-39462726590so558188b6e.1 for ; Wed, 17 May 2023 06:57:39 -0700 (PDT) Received: from grind.. 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[189.46.207.53]) by smtp.gmail.com with ESMTPSA id j21-20020a544815000000b00383d9700294sm9409562oij.40.2023.05.17.06.57.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 06:57:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1684331858; x=1686923858; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lMnHi4+vBadWo5A/+JSdVRCwH4evlrvC8EDyRoJWt8w=; b=U6eGMimFWubwOYLpY+g8ed4b3KBrpiARCBDOk1K9E9IIG5TXN9zMo0E8DFHgnU6HBh mzaeqrCUN0aQm2Qd/1314MhwYIViu3McaUDH2tjq6Nl3NLz6shRdbPLaSKcZfqwmPBOu LPNpTUhJxsAC8XM5ePUdQQlBT5uzKvf0EBYpWm3Q9eROl8NYtP8jD8XOpv9U9OxDEmNo NFjJsBAa1GQWQvb1rRyBEpDrioiqJ1RrGgbwbPJPULD5LnqVbVy+/WQEGCwT8FwIg70D 1RJavR0R7nBdiWtxpyht9uwIXI318sSA5gaGsSaxeeRCNh5Nd1Ci7wUJmTJnYjQKXVnd 8gvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684331858; x=1686923858; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lMnHi4+vBadWo5A/+JSdVRCwH4evlrvC8EDyRoJWt8w=; b=JQTnabLNPaQLw4072iDKFx4CAdGVmi9iMokFGPluTN+Ez5GJkWpPYoX/7l9sJjQrVI UUBfMBoQF0oqR9lfMqTvmxabMOn+uRn4vxcFtcJXpce9MlBYsig0rhnB6NGvKgKB71O/ YVL+Q8ZT2tsZ2tz7FHVFr/BTH5RjVXTPPet2b7JWqs1DYwfD0SCuRkNRVf0XeFNTopxK kyxxBLXo4hn37XspttButYd+TNBH9fY8l+XqoHmTwLQ15HS9T3XlsKWA7NdQ53onXy5S n/nuo30tIYA0R81TkcsxhgyKFQdH1dRllmaMjyC6BIWWUZLI1UVDcisBbCcELkKI4R8t MrvQ== X-Gm-Message-State: AC+VfDzPFM7eQnc7O9oprxtYu2hbNuA57pzc83T6OAmfCG6VdE5NJzE0 wxBJo0o8oN85jFc7ilzDzvHlRtrcrZckkkbchUI= X-Google-Smtp-Source: ACHHUZ6djNEcGi3N30clc+0qAmQBbYGCMYzC7VPT0Pil6RAv3PjOX6urU7IXqrtzJ/2Pycv4J/V8Mw== X-Received: by 2002:a54:4018:0:b0:389:4a00:51b5 with SMTP id x24-20020a544018000000b003894a0051b5mr15267418oie.8.1684331858335; Wed, 17 May 2023 06:57:38 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v9 05/11] target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version Date: Wed, 17 May 2023 10:57:08 -0300 Message-Id: <20230517135714.211809-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230517135714.211809-1-dbarboza@ventanamicro.com> References: <20230517135714.211809-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1684331945470100003 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Using implicitly enabled extensions such as Zca/Zcf/Zcd instead of their super extensions can simplify the extension related check. However, they may have higher priv version than their super extensions. So we should mask them in the isa_string based on priv version to make them invisible to user if the specified priv version is lower than their minimal priv version. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b1a6675d1e..88195945e5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1758,7 +1758,8 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char = **isa_str, int i; =20 for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { + if (cpu->env.priv_ver >=3D isa_edata_arr[i].min_version && + isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { new =3D g_strconcat(old, "_", isa_edata_arr[i].name, NULL); g_free(old); old =3D new; --=20 2.40.1 From nobody Sat May 18 10:07:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1684331951; cv=none; d=zohomail.com; s=zohoarc; b=HZPdWimgmXuvtvas6NJvLt0hzEl53GGoMkCC1bziIjHiNiE0Ro+nx4+R0q3LcoQ0J5rKP+y7oqbOk6Pf21IrOCXJzLlYSYXI3BR+QSoybRMQOQydECBk/cQfCWgNKhmczg1BPR1gTLZ/ARQd9OidMdTJPqe+x1gy7yBX2pqCb2g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684331951; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6LhYeXpWQRvlfMmKe9Vt//iFu9+3u6HPN95qmw4lUp4=; b=a30Ks9c0fXS/+1+FkMF5834iqhePtPtShwdT8EuytqP1KhZW4h4msXUC3plkI+1U535vBZTNw0ttEyHObSWfSG0tYS8BRc4svhagY+5FcOhEyxbN3lQLotwoJ+FD+DTdHnmkp66O0NrpsX+ROyVyoMFuDRcqOJsGGLcz0E8Dpag= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684331951729944.3484795521113; Wed, 17 May 2023 06:59:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzHf2-00012C-2Y; Wed, 17 May 2023 09:57:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzHez-00011E-JJ for qemu-devel@nongnu.org; Wed, 17 May 2023 09:57:45 -0400 Received: from mail-oi1-x229.google.com ([2607:f8b0:4864:20::229]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pzHex-0000WL-NE for qemu-devel@nongnu.org; Wed, 17 May 2023 09:57:45 -0400 Received: by mail-oi1-x229.google.com with SMTP id 5614622812f47-395a957a310so354504b6e.0 for ; Wed, 17 May 2023 06:57:41 -0700 (PDT) Received: from grind.. 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[189.46.207.53]) by smtp.gmail.com with ESMTPSA id j21-20020a544815000000b00383d9700294sm9409562oij.40.2023.05.17.06.57.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 06:57:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1684331861; x=1686923861; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6LhYeXpWQRvlfMmKe9Vt//iFu9+3u6HPN95qmw4lUp4=; b=o2vKkUHdbzpw7WO05rzAYldLz+ilaIQ8dZRuNIzAaP2MYZp1XsnHEtw4mFbvEjCupv HwC+S4qxs8zP/L8eBpxJlvWYf75U3aKBmjIrIpkUAooFqzk+kuM12eyGUFYMhXpW9cR0 AeqHzC4kKx4g2mWt7UVYz4lTnW7pbgjpUYeGtEyUOSg88fR8rd9dTC0FYv1vS8xAqVdK kR9+zwZxn1ozKhZiFchJEQofPVkz8zysNnzmteramsiotrhX5z2Zdoo1Rd2EhGoPjGVh 7hfkfDtCTHTOyRkXQIt69NDTrmWDS8BnNopId8knsYkCBU7DE/49Ad3JZG6MmILLohRF YX6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684331861; x=1686923861; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6LhYeXpWQRvlfMmKe9Vt//iFu9+3u6HPN95qmw4lUp4=; b=T6t3dcG1exN7YvylfgvrWgtxckclNCNamybBoCm67yjFCL3sUOAOEU1PCLkFwD90Bw /buqBNLIvaVGjgWOfmTRKBB0a03wLqtzqXkcIPcORndLWO3FlnqCSQ5ewMdJYIgKdktb Vu/MFkWHYUomkH0mDMWhpeD072Zbs3AbdWHH9Ul+Uc+28Gi2qBJXBuyqQBkmQXxApfQn L7mtsLRkkBWtljx4Wuj9gmKyxVrtEYBHg6KNAE6O73wf00ZQWbFx6YpXBFG1ZTx2sFDv oTC6xJMMcKYJFpWdvfT7tq/vjKeema5DqxMJOz5TgDxN6QVtbaXDwWIOGxWszRYe9fLX p2ZA== X-Gm-Message-State: AC+VfDwrHAKECQ0+MUf/I0iYY2RlQYx7xuMm8Gou8SYEbjD5gJcQ6NEv eazEyBvsfKe9PAyodaU/hfBFmTIWXMQOYBICmLU= X-Google-Smtp-Source: ACHHUZ5kcNuDhwJdy6c885z9y4Pj/XTu9nHs6g4dJwClICSXl8oZxIOs8mO/jxfRuGhPwoNzSpXZpQ== X-Received: by 2002:a05:6808:103:b0:390:84bc:529c with SMTP id b3-20020a056808010300b0039084bc529cmr13698975oie.28.1684331860767; Wed, 17 May 2023 06:57:40 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: [PATCH v9 06/11] target/riscv: Update check for Zca/Zcf/Zcd Date: Wed, 17 May 2023 10:57:09 -0300 Message-Id: <20230517135714.211809-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230517135714.211809-1-dbarboza@ventanamicro.com> References: <20230517135714.211809-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1684331953508100003 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Even though Zca/Zcf/Zcd can be included by C/F/D, however, their priv version is higher than the priv version of C/F/D. So if we use check for them instead of check for C/F/D totally, it will trigger new problem when we try to disable the extensions based on the configured priv version. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvd.c.inc | 12 +++++++----- target/riscv/insn_trans/trans_rvf.c.inc | 14 ++++++++------ target/riscv/insn_trans/trans_rvi.c.inc | 5 +++-- target/riscv/translate.c | 5 +++-- 4 files changed, 21 insertions(+), 15 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 2c51e01c40..6bdb55ef43 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -31,9 +31,11 @@ } \ } while (0) =20 -#define REQUIRE_ZCD(ctx) do { \ - if (!ctx->cfg_ptr->ext_zcd) { \ - return false; \ +#define REQUIRE_ZCD_OR_DC(ctx) do { \ + if (!ctx->cfg_ptr->ext_zcd) { \ + if (!has_ext(ctx, RVD) || !has_ext(ctx, RVC)) { \ + return false; \ + } \ } \ } while (0) =20 @@ -67,13 +69,13 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) =20 static bool trans_c_fld(DisasContext *ctx, arg_fld *a) { - REQUIRE_ZCD(ctx); + REQUIRE_ZCD_OR_DC(ctx); return trans_fld(ctx, a); } =20 static bool trans_c_fsd(DisasContext *ctx, arg_fsd *a) { - REQUIRE_ZCD(ctx); + REQUIRE_ZCD_OR_DC(ctx); return trans_fsd(ctx, a); } =20 diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index b2de4fcf3f..c47138575a 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -30,10 +30,12 @@ } \ } while (0) =20 -#define REQUIRE_ZCF(ctx) do { \ - if (!ctx->cfg_ptr->ext_zcf) { \ - return false; \ - } \ +#define REQUIRE_ZCF_OR_FC(ctx) do { \ + if (!ctx->cfg_ptr->ext_zcf) { \ + if (!has_ext(ctx, RVF) || !has_ext(ctx, RVC)) { \ + return false; \ + } \ + } \ } while (0) =20 static bool trans_flw(DisasContext *ctx, arg_flw *a) @@ -69,13 +71,13 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) =20 static bool trans_c_flw(DisasContext *ctx, arg_flw *a) { - REQUIRE_ZCF(ctx); + REQUIRE_ZCF_OR_FC(ctx); return trans_flw(ctx, a); } =20 static bool trans_c_fsw(DisasContext *ctx, arg_fsw *a) { - REQUIRE_ZCF(ctx); + REQUIRE_ZCF_OR_FC(ctx); return trans_fsw(ctx, a); } =20 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index c70c495fc5..e33f63bea1 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -56,7 +56,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2); =20 gen_set_pc(ctx, cpu_pc); - if (!ctx->cfg_ptr->ext_zca) { + if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) { TCGv t0 =3D tcg_temp_new(); =20 misaligned =3D gen_new_label(); @@ -169,7 +169,8 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCG= Cond cond) =20 gen_set_label(l); /* branch taken */ =20 - if (!ctx->cfg_ptr->ext_zca && ((ctx->base.pc_next + a->imm) & 0x3)) { + if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca && + ((ctx->base.pc_next + a->imm) & 0x3)) { /* misaligned */ gen_exception_inst_addr_mis(ctx); } else { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 928da0d3f0..a889454137 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -549,7 +549,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_u= long imm) =20 /* check misaligned: */ next_pc =3D ctx->base.pc_next + imm; - if (!ctx->cfg_ptr->ext_zca) { + if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) { if ((next_pc & 0x3) !=3D 0) { gen_exception_inst_addr_mis(ctx); return; @@ -1123,7 +1123,8 @@ static void decode_opc(CPURISCVState *env, DisasConte= xt *ctx, uint16_t opcode) * The Zca extension is added as way to refer to instructions in t= he C * extension that do not include the floating-point loads and stor= es */ - if (ctx->cfg_ptr->ext_zca && decode_insn16(ctx, opcode)) { + if ((has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zca) && + decode_insn16(ctx, opcode)) { return; } } else { --=20 2.40.1 From nobody Sat May 18 10:07:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1684331973; cv=none; d=zohomail.com; s=zohoarc; b=Xej1WxkyVgn2JTsM/KlSWpmvZjlQudR2Adf94wAFl/+PK6S0ZufCKCGH9vNDTJsIOQdmfrhVJm487AC9XW3n1xBMEz7C/jsKArA70v72EQUGidTUaSq2hQunMb1dv4bgnF1E7GvDyQ3zWLClBiSPfR8XbRY2ellcErB6CiChduI= ARC-Message-Signature: i=1; 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[189.46.207.53]) by smtp.gmail.com with ESMTPSA id j21-20020a544815000000b00383d9700294sm9409562oij.40.2023.05.17.06.57.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 06:57:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1684331863; x=1686923863; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fkNpNmR66GejSLq+xvI9J7aeh+Cy9r79mU2H1FdTjDQ=; b=KWGV8Jw9mngiLjZdK6uMxoEE4i/z3c+vkEqRN2JC8YyzGm8kg/hJ2Y/OqLv9qfviIy eBxtXsmOo/4aN0/e4h70QlK9qV6Vf9nnK3A0Shb8HDBbT6J/c4Uv/vZtuvufbG2GlXPZ 16OT1deJHRApeDkbgWJdoggVv79bsbCM/tQUntFJiMNjnVuJJXFG948uJPjVFmGQapTa 4SaCG/qqaF7lnKjSmyYaFwkMFslr+O4WTLnvn4K3wA1eukxwOTUtS0Djv/MopfUXdYvY bIr0Loei3Dpzmz4Jus3VsS174szSHcLGQLHTfZJ9Up3lHCy016cru0B3SvCxwZulMpuK XDSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684331863; x=1686923863; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fkNpNmR66GejSLq+xvI9J7aeh+Cy9r79mU2H1FdTjDQ=; b=aafixClV7o6x6W9E/dluwxXtxwenC9Pr5t+copehMfVXeNSi9MwGpj4XvtlrONqadI yl/9L4RhRZmkYpXbmwYHJm8vl8WMd9CbcpOMPGb8NL5FJkWUiwAOKFa63bOdo2TihIZx /Luqrq6xjEv055Rg0NL0rEIpvkxt7Q4WB8xBZtKl5D6APQR6yeyJ7Z+wDL7sHuP+4NAk H/Cb+Hdye0YGZjvKjaks50vPyxKRXzkkaZ1n152dw1qgVLcUL5tXsxklSpaDZD1h54cH j9QTmXKXTKt/UvGx0xn1ThKw7uBAe7ozbAuXjdCG+jTvcnrpH1GmBkvH//nMMXX+UCMA rDKw== X-Gm-Message-State: AC+VfDzu9an3Ys9IRjedfaeK5f91z+zhk3yfFxyZpfkViQ2CM345r/Iq VfnEpmc6EFSjO4wKHtFTnYBxjBUR4uQwomDXoiw= X-Google-Smtp-Source: ACHHUZ45O5dvHIHbSj6wNKR3uol5n5y2gS5JLhisSu3YZSb01eyD7uiLCH1Ck95s65EDS3wJaRv5fQ== X-Received: by 2002:a05:6808:2002:b0:396:25be:bb79 with SMTP id q2-20020a056808200200b0039625bebb79mr4057718oiw.11.1684331863477; Wed, 17 May 2023 06:57:43 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v9 07/11] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers Date: Wed, 17 May 2023 10:57:10 -0300 Message-Id: <20230517135714.211809-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230517135714.211809-1-dbarboza@ventanamicro.com> References: <20230517135714.211809-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1684331975840100003 Content-Type: text/plain; charset="utf-8" We're doing env->priv_spec validation and assignment at the start of riscv_cpu_realize(), which is fine, but then we're doing a force disable on extensions that aren't compatible with the priv version. This second step is being done too early. The disabled extensions might be re-enabled again in riscv_cpu_validate_set_extensions() by accident. A better place to put this code is at the end of riscv_cpu_validate_set_extensions() after all the validations are completed. Add a new helper, riscv_cpu_disable_priv_spec_isa_exts(), to disable the extesions after the validation is done. While we're at it, create a riscv_cpu_validate_priv_spec() helper to host all env->priv_spec related validation to unclog riscv_cpu_realize a bit. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 91 ++++++++++++++++++++++++++++------------------ 1 file changed, 56 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 88195945e5..58a38bc62f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -864,6 +864,52 @@ static void riscv_cpu_validate_v(CPURISCVState *env, R= ISCVCPUConfig *cfg, env->vext_ver =3D vext_version; } =20 +static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env =3D &cpu->env; + int priv_version =3D -1; + + if (cpu->cfg.priv_spec) { + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { + priv_version =3D PRIV_VERSION_1_12_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { + priv_version =3D PRIV_VERSION_1_11_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { + priv_version =3D PRIV_VERSION_1_10_0; + } else { + error_setg(errp, + "Unsupported privilege spec version '%s'", + cpu->cfg.priv_spec); + return; + } + + env->priv_ver =3D priv_version; + } +} + +static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) +{ + CPURISCVState *env =3D &cpu->env; + int i; + + /* Force disable extensions if priv spec version does not match */ + for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { + if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && + (env->priv_ver < isa_edata_arr[i].min_version)) { + isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); +#ifndef CONFIG_USER_ONLY + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx + " because privilege spec version does not match", + isa_edata_arr[i].name, env->mhartid); +#else + warn_report("disabling %s extension because " + "privilege spec version does not match", + isa_edata_arr[i].name); +#endif + } + } +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -1082,6 +1128,12 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) cpu->cfg.ext_zksed =3D true; cpu->cfg.ext_zksh =3D true; } + + /* + * Disable isa extensions based on priv spec after we + * validated and set everything we need. + */ + riscv_cpu_disable_priv_spec_isa_exts(cpu); } =20 #ifndef CONFIG_USER_ONLY @@ -1181,7 +1233,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); CPUClass *cc =3D CPU_CLASS(mcc); - int i, priv_version =3D -1; Error *local_err =3D NULL; =20 cpu_exec_realizefn(cs, &local_err); @@ -1190,23 +1241,10 @@ static void riscv_cpu_realize(DeviceState *dev, Err= or **errp) return; } =20 - if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { - priv_version =3D PRIV_VERSION_1_12_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { - priv_version =3D PRIV_VERSION_1_11_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { - priv_version =3D PRIV_VERSION_1_10_0; - } else { - error_setg(errp, - "Unsupported privilege spec version '%s'", - cpu->cfg.priv_spec); - return; - } - } - - if (priv_version >=3D PRIV_VERSION_1_10_0) { - env->priv_ver =3D priv_version; + riscv_cpu_validate_priv_spec(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; } =20 riscv_cpu_validate_misa_priv(env, &local_err); @@ -1215,23 +1253,6 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) return; } =20 - /* Force disable extensions if priv spec version does not match */ - for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && - (env->priv_ver < isa_edata_arr[i].min_version)) { - isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); -#ifndef CONFIG_USER_ONLY - warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx - " because privilege spec version does not match", - isa_edata_arr[i].name, env->mhartid); -#else - warn_report("disabling %s extension because " - "privilege spec version does not match", - isa_edata_arr[i].name); -#endif - } - } - if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available --=20 2.40.1 From nobody Sat May 18 10:07:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[189.46.207.53]) by smtp.gmail.com with ESMTPSA id j21-20020a544815000000b00383d9700294sm9409562oij.40.2023.05.17.06.57.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 06:57:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1684331866; x=1686923866; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vtUwD5uLnT/SSQASOF4X8pyHibJ8G3gdoTuEx0wIxyE=; b=oYxt3NN/HTSHQU+YbD2F4D1Dhl2tF+IQvAGBZr1Ck2CT6RoTA+OD279BlfyN5wVSmV tco3HUZSBDfJShhh894sQzxUn/dW14tUhqGNMnx/4xAfIPNysSTkjxpYw6gJ7r77dAhc DilmAkUSCpeHOlfAfrgi6IdNXkY1RPwirDWPnIQco5ikzoFR4nq1vLh+xotFKq8Y7Eb7 i1/u9A3RQJx8EOWqoXV3rVy1Zd77SeHkUBaYwYoPCyTbquH9HGOdBwcjBt2/JsL0hn1V KA6xNHP7UgF0eIVaPK/ujZEVMx6unH76MlCLqQ5GLt8K3aRiJEOzANMRKypHT6Ty8ePl mRYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684331866; x=1686923866; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vtUwD5uLnT/SSQASOF4X8pyHibJ8G3gdoTuEx0wIxyE=; b=KJ8UVba4aDCz/w1qKu24AfiS86aWJwYTUaqORH9scJqNu3NbGgTKii+3utmDR31Ybk CMr0NFqXxd0WOsDRx00Z+vVLbR5Qh8KHlULVL33q2teiXBppmzhswoB9Q2CCrmqHOvXL JQMy2Dj2yICNjLCK/oolpeALts3iVmWmqSxZMbUy3suRgxCeuqWHdvLXrss2IuD/lG7Q MY96o0YFfbacJ5dUBKFh2R/qyDgzGfgXPvdVqD0zZXD2nxsJq9xs50X6cakqHThvJyP6 J6QiFvV+DsRbNU3bghKn8Ugwg1PNgx8ad4a6EtPbW6wrPEvwrNufE87wcXyQQG5lHCoJ bcag== X-Gm-Message-State: AC+VfDwS1hBjoyeQMOHZmvJmWVvCJEINH6ufnS+wWd9cV3PKtYVj/UEL 8oVjAQHDZfsZvKLlLA8URvZBt1t7cIDO11LLst8= X-Google-Smtp-Source: ACHHUZ5VoKqNqbHLkmJzis+0h2tFNXiVOPwVAosw55x2UAFX2sezXCTaI5J2RvRPgLLT8/im9I4jEA== X-Received: by 2002:aca:f02:0:b0:394:2478:4966 with SMTP id 2-20020aca0f02000000b0039424784966mr12342306oip.10.1684331866066; Wed, 17 May 2023 06:57:46 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v9 08/11] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() Date: Wed, 17 May 2023 10:57:11 -0300 Message-Id: <20230517135714.211809-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230517135714.211809-1-dbarboza@ventanamicro.com> References: <20230517135714.211809-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1684331924318100003 Content-Type: text/plain; charset="utf-8" Let's remove more code that is open coded in riscv_cpu_realize() and put it into a helper. Let's also add an error message instead of just asserting out if env->misa_mxl_max !=3D env->misa_mlx. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 50 ++++++++++++++++++++++++++++++---------------- 1 file changed, 33 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 58a38bc62f..32240a0b10 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -910,6 +910,33 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCV= CPU *cpu) } } =20 +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); + CPUClass *cc =3D CPU_CLASS(mcc); + CPURISCVState *env =3D &cpu->env; + + /* Validate that MISA_MXL is set properly. */ + switch (env->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + case MXL_RV128: + cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; + break; +#endif + case MXL_RV32: + cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; + break; + default: + g_assert_not_reached(); + } + + if (env->misa_mxl_max !=3D env->misa_mxl) { + error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); + return; + } +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -1232,7 +1259,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) RISCVCPU *cpu =3D RISCV_CPU(dev); CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); - CPUClass *cc =3D CPU_CLASS(mcc); Error *local_err =3D NULL; =20 cpu_exec_realizefn(cs, &local_err); @@ -1241,6 +1267,12 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) return; } =20 + riscv_cpu_validate_misa_mxl(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + riscv_cpu_validate_priv_spec(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); @@ -1269,22 +1301,6 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) } #endif /* CONFIG_USER_ONLY */ =20 - /* Validate that MISA_MXL is set properly. */ - switch (env->misa_mxl_max) { -#ifdef TARGET_RISCV64 - case MXL_RV64: - case MXL_RV128: - cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; - break; -#endif - case MXL_RV32: - cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; - break; - default: - g_assert_not_reached(); - } - assert(env->misa_mxl_max =3D=3D env->misa_mxl); - riscv_cpu_validate_set_extensions(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.40.1 From nobody Sat May 18 10:07:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1684331901; cv=none; d=zohomail.com; s=zohoarc; b=CisoGQvrHP8/JOTrJQ4a8n/upSPdL/X49dFgs5zMPmo9fXgHSUINcQ3kVWtw9TGP9uln4+5B6NBwdSUQyhph3COOJi4ImFVXnDLmC4nbXqi/4Y6J1UoLsfjRqv3wZ8wJgopxehd52Dk46GXEP2GwpK/9rx9djfzxKqflM8ZLH/M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684331901; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lWt2ZMWA6z+B9QZASmH5IEOuVSLKg4cj3mZuVfKgT9E=; b=JdZdFvXN+L2gGGNGvrhAJ1JpyRifdSNI2CrY77ZUr4kMJm/IlpyHxNbmoztOftyu0FekY9qtv1oxFWe+SmpsDcZWLFrT+PhG1gCpTd1qdD+1Q1IPVas8vLwt4RfnVxwQJLIxMpFt79tNZQ15QpuHQEII4ow0JqE8Qz3uQ5HxxiQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684331901950272.9799530287893; Wed, 17 May 2023 06:58:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzHfC-0001M7-Na; Wed, 17 May 2023 09:57:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzHf6-0001GL-9p for qemu-devel@nongnu.org; Wed, 17 May 2023 09:57:53 -0400 Received: from mail-oi1-x234.google.com ([2607:f8b0:4864:20::234]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pzHf3-0000U8-Gw for qemu-devel@nongnu.org; Wed, 17 May 2023 09:57:51 -0400 Received: by mail-oi1-x234.google.com with SMTP id 5614622812f47-3941c3ba226so559129b6e.0 for ; Wed, 17 May 2023 06:57:49 -0700 (PDT) Received: from grind.. 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[189.46.207.53]) by smtp.gmail.com with ESMTPSA id j21-20020a544815000000b00383d9700294sm9409562oij.40.2023.05.17.06.57.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 06:57:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1684331868; x=1686923868; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lWt2ZMWA6z+B9QZASmH5IEOuVSLKg4cj3mZuVfKgT9E=; b=MGZdnd2ukuvB8MVF+0VU1dWqIfJVCIb5vmKGBBlIVHP5NHBef1riz2/1hyDbA/8fBb Dt5Cw+6KSd8LkAEwhFPPpxoumIUWpgjZPynbsmXjTrEH+vv+ap13OJPm+Dc+iSVRV41D yCj4hcpPFsSgJtBuwm/ZKUCHF6EZc5xZMtZXOZyzoaQIcvc7CL03KA//fBrQhC9ghAkC 9441ph/bq3oUnPTf3LEaeGNqx9xB7pWJbgWaL8wfOH2OqF9fBbaxLHHiUg3TSTCHO6R2 agolp4wqZ3L/22TUkIc64p0I/pPKb0P7/SybYACu8j7rTN9m/xQwJA8sNvuMWxZuMOeN wrzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684331868; x=1686923868; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lWt2ZMWA6z+B9QZASmH5IEOuVSLKg4cj3mZuVfKgT9E=; b=ib6nLRew24VbFt9khQbw7JLZpzJc637tP0/Vw5eIPiM8wRZw4ADsHdx7oKKU74oeAQ f6xGLZyuciBloTfzoIQPEA9WBagWO+QRNTP7fOqilvgNDasM3gITsecV2+2eVGDx2Cfj Tg66GDtBoUxLPn+WyRIW7lRLhybIDqC8o7VGtpCCjlsPwNP7VDETJzb0VE0vl3pSgaEz W385UwWbhNWJKRB0gofA4B18HR9jEJF5KNnKV4Ksxh7vzdUBE321S8RxM+Flz3A8RDob NMbBCT1/o75sdEI1tDQkRqUMlatrBQbgXf6e9lgmlDXdKHfwqdFkBpg9VgAItKxnsw4N cepQ== X-Gm-Message-State: AC+VfDz0wTATaX8ZIDAxSvjYnIl+c5Sf05hWYYye5r6c5RQYMsNFhfm9 eVazQf/BUgR4RxnkGE+oCDEiDmhJ8lMdoIvO75o= X-Google-Smtp-Source: ACHHUZ7eNlt0D86+8IoLPOpOBufgbJ0HEmranlwJPP3dLmHCQ4r9T2y/kF1WcVs3IEOwOwopX0yrhQ== X-Received: by 2002:a05:6808:10d1:b0:396:cd:82b1 with SMTP id s17-20020a05680810d100b0039600cd82b1mr8464034ois.2.1684331868646; Wed, 17 May 2023 06:57:48 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v9 09/11] target/riscv/cpu.c: validate extensions before riscv_timer_init() Date: Wed, 17 May 2023 10:57:12 -0300 Message-Id: <20230517135714.211809-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230517135714.211809-1-dbarboza@ventanamicro.com> References: <20230517135714.211809-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1684331903998100001 Content-Type: text/plain; charset="utf-8" There is no need to init timers if we're not even sure that our extensions are valid. Execute riscv_cpu_validate_set_extensions() before riscv_timer_init(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 32240a0b10..9e33fa4301 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1294,13 +1294,6 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) return; } =20 - -#ifndef CONFIG_USER_ONLY - if (cpu->cfg.ext_sstc) { - riscv_timer_init(cpu); - } -#endif /* CONFIG_USER_ONLY */ - riscv_cpu_validate_set_extensions(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); @@ -1308,6 +1301,10 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) } =20 #ifndef CONFIG_USER_ONLY + if (cpu->cfg.ext_sstc) { + riscv_timer_init(cpu); + } + if (cpu->cfg.pmu_num) { if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpm= f) { cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, --=20 2.40.1 From nobody Sat May 18 10:07:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1684331897; cv=none; d=zohomail.com; s=zohoarc; b=Hn5so28XiFcXJZZwnuJAkntSJB0YKSI7Xx67T4Dxhoidr5Z2qjLjmOCifdysGdZGZqxMbuY2WwiDsJjG0IgMqWwsaryym12j9+emuhffAishSztywm8ykLsMy7sPdMYSQtcJ7N3wGtq86tknuk6yXOa5YWnrcKQCNcIZUxE1GK0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1684331897; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kfSAPgxiMzr1wrf+V+jfCJowiPVIcHPmXy6mTve0Hgw=; b=ZtfatCtcBqditK26L4K34BV/0cHqIb178nT6/wOz/w2ODGGHR4sqvWaxTfPJvyUOjHOFI5QgBGLd2EETjeIuMkOqtfpL2WhIawuAc+iXCZ1NbF+2eCGcBCK+aioleAS+52JXtlv3cLqzdJAbQU3hM2jFjs7RC/Fkmh0HCXsnF2w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1684331897439724.1101541216594; Wed, 17 May 2023 06:58:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pzHfM-0001rJ-3m; Wed, 17 May 2023 09:58:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pzHfK-0001eH-4T for qemu-devel@nongnu.org; Wed, 17 May 2023 09:58:06 -0400 Received: from mail-ot1-x32d.google.com ([2607:f8b0:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pzHf6-0000Zn-O2 for qemu-devel@nongnu.org; Wed, 17 May 2023 09:58:05 -0400 Received: by mail-ot1-x32d.google.com with SMTP id 46e09a7af769-6ab13810da6so344828a34.2 for ; Wed, 17 May 2023 06:57:52 -0700 (PDT) Received: from grind.. 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[189.46.207.53]) by smtp.gmail.com with ESMTPSA id j21-20020a544815000000b00383d9700294sm9409562oij.40.2023.05.17.06.57.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 06:57:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1684331871; x=1686923871; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kfSAPgxiMzr1wrf+V+jfCJowiPVIcHPmXy6mTve0Hgw=; b=eLirNB4mNDQQrvIO/RU2ENvMWRjIgkYqkRyl0UEQwSeSi6/Rw9ZfHuJJSoK4Ns1MhN AZ8FNCS279kj8EkB0+UT4BOEb6CUxJq3jtE8vGHDuQoEEiKhomsHp6QQx4FHreuhHIlU XZRvYyMlPL69Oq75O0JSA2byyI5kA9pveTDoPsEVaSimkdXLOKkEmMSc93PJKJk1fswi e2VeEiLdpVVO5MuThHJrUmi8wRChQC1KsaIHaq0/8HnzUjl02znCdDfE+5+liY8D115t Vrq+jmLl5mCJMW2VdYWprmrueja+SscwNV5hL0Y3Bi8fUv/d6dq0bKKYKVJi4qTGh1pt ecJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684331871; x=1686923871; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kfSAPgxiMzr1wrf+V+jfCJowiPVIcHPmXy6mTve0Hgw=; b=aTU1Yputf15K+C0/7XlGxvxP+UAt+ITmCMlOBf1l4JdWQBj1Y78mEfOy8s9h3E6b6i zm1sn6WnujwJ4xs6vNoTT7f0NkjT18g5bozZQlrJZpns8JEg5F4ZqwZ5DY+NiHtj7Gl/ 7oYiKOKpcj41yaYNSoM8K4tHdIzyILCtcIZ9Te8jltLR3hypvhuKTWSUcnaPzhXUlIZe 5K0ML9BIrftTsUXP/q3duMY4DhcBq1zN2b7jcqqjgl408D1iQOfkSbx4Ts/zEwnjLAXq OVOgxTLTXTTbHYKwHwBQ7Lkp0W50Ai3paJWumWqoCQd+jdIuTpkEPxO0v7nQTpJjRKvz xTLg== X-Gm-Message-State: AC+VfDz8+y368xOifdDL0WMu48NFN54DXo/0D5yMjqSOGa7pITEQGVCn uZTzW40rvtJ6Ed/767TTc+GXyzHLRVfbexsCxZ0= X-Google-Smtp-Source: ACHHUZ49VZ571ZP+FW+02cRgJus9xHVmFLQbiP0sqOXUV2kMSRwlgsEAkX9tNnTuVqLsnYP4yAvEWw== X-Received: by 2002:a05:6808:6185:b0:38e:3904:2db9 with SMTP id dn5-20020a056808618500b0038e39042db9mr13732956oib.46.1684331871388; Wed, 17 May 2023 06:57:51 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v9 10/11] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() Date: Wed, 17 May 2023 10:57:13 -0300 Message-Id: <20230517135714.211809-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230517135714.211809-1-dbarboza@ventanamicro.com> References: <20230517135714.211809-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32d; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1684331899139100005 Content-Type: text/plain; charset="utf-8" We have 4 config settings being done in riscv_cpu_init(): ext_ifencei, ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu" device, which happens to be the parent device of every RISC-V cpu. The result is that these 4 configs are being set every time, and every other CPU should always account for them. CPUs such as sifive_e need to disable settings that aren't enabled simply because the parent class happens to be enabling it. Moving all configurations from the parent class to each CPU will centralize the config of each CPU into its own init(), which is clearer than having to account to whatever happens to be set in the parent device. These settings are also being set in register_cpu_props() when no 'misa_ext' is set, so for these CPUs we don't need changes. Named CPUs will receive all cfgs that the parent were setting into their init(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 59 ++++++++++++++++++++++++++++++++++++---------- 1 file changed, 47 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9e33fa4301..52f91ff8cf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -332,7 +332,8 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) =20 static void riscv_any_cpu_init(Object *obj) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; #if defined(TARGET_RISCV32) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #elif defined(TARGET_RISCV64) @@ -346,6 +347,12 @@ static void riscv_any_cpu_init(Object *obj) #endif =20 env->priv_ver =3D PRIV_VERSION_LATEST; + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; } =20 #if defined(TARGET_RISCV64) @@ -364,12 +371,19 @@ static void rv64_base_cpu_init(Object *obj) =20 static void rv64_sifive_u_cpu_init(Object *obj) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv64_sifive_e_cpu_init(Object *obj) @@ -379,10 +393,14 @@ static void rv64_sifive_e_cpu_init(Object *obj) =20 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; - cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv64_thead_c906_cpu_init(Object *obj) @@ -410,6 +428,9 @@ static void rv64_thead_c906_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_SV39); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.pmp =3D true; } =20 static void rv64_veyron_v1_cpu_init(Object *obj) @@ -483,12 +504,19 @@ static void rv32_base_cpu_init(Object *obj) =20 static void rv32_sifive_u_cpu_init(Object *obj) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv32_sifive_e_cpu_init(Object *obj) @@ -498,10 +526,14 @@ static void rv32_sifive_e_cpu_init(Object *obj) =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; - cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv32_ibex_cpu_init(Object *obj) @@ -511,11 +543,15 @@ static void rv32_ibex_cpu_init(Object *obj) =20 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_11_0; - cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif cpu->cfg.epmp =3D true; + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv32_imafcu_nommu_cpu_init(Object *obj) @@ -525,10 +561,14 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; - cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.pmp =3D true; } #endif =20 @@ -1441,11 +1481,6 @@ static void riscv_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - cpu->cfg.ext_ifencei =3D true; - cpu->cfg.ext_icsr =3D true; - cpu->cfg.mmu =3D true; - cpu->cfg.pmp =3D true; - cpu_set_cpustate_pointers(cpu); =20 #ifndef CONFIG_USER_ONLY --=20 2.40.1 From nobody Sat May 18 10:07:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1684331910; cv=none; d=zohomail.com; s=zohoarc; b=brjZame8j7Z63UBG0kTdhq5YMjA3YvF4Fj8PAH0aVl8GSQcH4WKruzSwhSE5wOlWtQX1hu6h76EYkI6w/HWq/iMh44VgKaMqqm1FPEoVofBvKVsnsPjJsfBsDBQzY7+m8W5vU4hf38fzEXDTWlT4Z5xPVICZ6sNJawPlBMw0E0U= ARC-Message-Signature: i=1; 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[189.46.207.53]) by smtp.gmail.com with ESMTPSA id j21-20020a544815000000b00383d9700294sm9409562oij.40.2023.05.17.06.57.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 06:57:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1684331874; x=1686923874; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=t6Xyw8ijFq4Yvxjt3imbOP1FVRYfmako65iN6rlGhO4=; b=JnBVs262jhbK61QKgT77Y3OEcbXd2XgtDCAXBmF2yXCXBJhW9d6qUZ3jcn/vV4c7UJ 3rBaDVrPfsqD5yTfDewIbGjTCrYdK/fVSP7BucoZQQ/Dwk9eGZzUx+8GapF7hX9I+VWr fNYxoqdQh0X9LJThf3dM0j5QQ3XralGnlkw8uap39UxPjD47vo+E14znGqpVNK/zhECB TwqlBU8N+k0+w9DnYM8ays1socHpX/9el7eMJgrLZkrPNvL2rJQEgUT76wX9tj7CAwAV /7WaNHo43tL2AHhnnBkS6Xyd9Hz7iHvelNbeJBdK2B/LH0cE/5MqHOn898WZIOqxzibD rP6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684331874; x=1686923874; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t6Xyw8ijFq4Yvxjt3imbOP1FVRYfmako65iN6rlGhO4=; b=bnnBo+/ynayuaXmkx/OrBh1Q77otsQPNuQPwy6xqpxHU+2+2Tm9dna5QW7cqkV47a3 hPKR0CGqk9q7Ko+CJVFpCMiz3B8xyKFjcp1Ubz7aIX+q2UfEsQ+aZt0pG7dLJSMN9UFX LrgNdFEl1oRBxz1lR79DyObxcuY7G9smQD+y9VQpuDeJiRS5YCm4b708E+rW8qTDmTpV qbj2gE3dfVYHh9loyIdMfMEfVLKSUCRcxsDEiZ7Pq/A7n3SSqNxGC88Yo0BTzIPvLjTV enin1as2HttsDCY90w+ZL96quiQS2+fb8Lnz49XVNK4HlSXbGnpaPDDPmoeAs838XrfH b0oQ== X-Gm-Message-State: AC+VfDwd/KfRAKONB6oyWST45KlloYOD5C4wwuCwcZqKpt2x1wJCicl1 TtouT4qvqW5oCPDDbTfnOEipaNDOemW7KXkJcJE= X-Google-Smtp-Source: ACHHUZ5xXHciR7vE4lD0NlGxgWFwO0AwGcWejtQdURrUY8LKEL7uNWb0Q8ipl9assQe4ABhHy9gU3w== X-Received: by 2002:a05:6808:2091:b0:395:ddd0:2a5f with SMTP id s17-20020a056808209100b00395ddd02a5fmr8315511oiw.4.1684331874022; Wed, 17 May 2023 06:57:54 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v9 11/11] target/riscv: rework write_misa() Date: Wed, 17 May 2023 10:57:14 -0300 Message-Id: <20230517135714.211809-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230517135714.211809-1-dbarboza@ventanamicro.com> References: <20230517135714.211809-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1684331911882100003 Content-Type: text/plain; charset="utf-8" write_misa() must use as much common logic as possible. We want to open code just the bits that are exclusive to the CSR write operation and TCG internals. Our validation is done with riscv_cpu_validate_set_extensions(), but we need a small tweak first. When enabling RVG we're doing: env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; env->misa_ext_mask =3D env->misa_ext; This works fine for realize() time but this can potentially overwrite env->misa_ext_mask if we reutilize the function for write_misa(). Instead of doing misa_ext_mask =3D misa_ext, sum up the RVG extensions in misa_ext_mask as well. This won't change realize() time behavior (misa_ext_mask will be =3D=3D misa_ext) and will ensure that write_misa() won't change misa_ext_mask by accident. After that, rewrite write_misa() to work as follows: - mask the write using misa_ext_mask to avoid enabling unsupported extensions; - suppress RVC if the next insn isn't aligned; - disable RVG if any of RVG dependencies are being disabled by the user; - assign env->misa_ext and run riscv_cpu_validate_set_extensions(). On error, rollback env->misa_ext to its original value, logging a GUEST_ERROR to inform the user about the failed write; - handle RVF and MSTATUS_FS and continue as usual. Let's keep write_misa() as experimental for now until this logic gains enough mileage. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 4 ++-- target/riscv/cpu.h | 1 + target/riscv/csr.c | 51 ++++++++++++++++++++++------------------------ 3 files changed, 27 insertions(+), 29 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 52f91ff8cf..6d4748bf24 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -981,7 +981,7 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, = Error **errp) * Check consistency between chosen extensions while setting * cpu->cfg accordingly. */ -static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; @@ -997,7 +997,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) cpu->cfg.ext_ifencei =3D true; =20 env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; - env->misa_ext_mask =3D env->misa_ext; + env->misa_ext_mask |=3D RVI | RVM | RVA | RVF | RVD; } =20 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 15423585d0..1f39edc687 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -548,6 +548,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); =20 #define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4451bd1263..cf7da4f87f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1387,39 +1387,18 @@ static RISCVException read_misa(CPURISCVState *env,= int csrno, static RISCVException write_misa(CPURISCVState *env, int csrno, target_ulong val) { + RISCVCPU *cpu =3D env_archcpu(env); + uint32_t orig_misa_ext =3D env->misa_ext; + Error *local_err =3D NULL; + if (!riscv_cpu_cfg(env)->misa_w) { /* drop write to misa */ return RISCV_EXCP_NONE; } =20 - /* 'I' or 'E' must be present */ - if (!(val & (RVI | RVE))) { - /* It is not, drop write to misa */ - return RISCV_EXCP_NONE; - } - - /* 'E' excludes all other extensions */ - if (val & RVE) { - /* - * when we support 'E' we can do "val =3D RVE;" however - * for now we just drop writes if 'E' is present. - */ - return RISCV_EXCP_NONE; - } - - /* - * misa.MXL writes are not supported by QEMU. - * Drop writes to those bits. - */ - /* Mask extensions that are not supported by this hart */ val &=3D env->misa_ext_mask; =20 - /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ - if ((val & RVD) && !(val & RVF)) { - val &=3D ~RVD; - } - /* * Suppress 'C' if next instruction is not aligned * TODO: this should check next_pc @@ -1428,18 +1407,36 @@ static RISCVException write_misa(CPURISCVState *env= , int csrno, val &=3D ~RVC; } =20 + /* Disable RVG if any of its dependencies are disabled */ + if (!(val & RVI && val & RVM && val & RVA && + val & RVF && val & RVD)) { + val &=3D ~RVG; + } + /* If nothing changed, do nothing. */ if (val =3D=3D env->misa_ext) { return RISCV_EXCP_NONE; } =20 - if (!(val & RVF)) { + env->misa_ext =3D val; + riscv_cpu_validate_set_extensions(cpu, &local_err); + if (local_err !=3D NULL) { + /* Rollback on validation error */ + qemu_log_mask(LOG_GUEST_ERROR, "Unable to write MISA ext value " + "0x%x, keeping existing MISA ext 0x%x\n", + env->misa_ext, orig_misa_ext); + + env->misa_ext =3D orig_misa_ext; + + return RISCV_EXCP_NONE; + } + + if (!(env->misa_ext & RVF)) { env->mstatus &=3D ~MSTATUS_FS; } =20 /* flush translation cache */ tb_flush(env_cpu(env)); - env->misa_ext =3D val; env->xl =3D riscv_cpu_mxl(env); return RISCV_EXCP_NONE; } --=20 2.40.1