From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792327; cv=none; d=zohomail.com; s=zohoarc; b=JheORVaB+9tL0HZf5BuhcnpyWefEAFH1Y7/5j+g1Ks8gLrNo24Zz5ZsF+MD1Q4uLicj+qISOVE3N173dBVgH7l7zmj/fBJmV+i21YHFVL/hNeYhF5nE9oO6J17soi2uEzkWDZtdQ0MBbMqgxS+U7eH7pLAx9iKvYcQ0d/Z63Bws= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792327; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fbkyE6bJfLhheM4qb7LWlvv0iU1hoxBxThnKXs5khSU=; b=TMoTQTV65dNEf/jDq35ejB9+eqteamodeGP8e2qDhK2z/5TrlHDWtxqeRWERE6TT/0u2VJj5r3zgo27fICC/JeSHB8LhIHKoRSSpcCiwU2/Fzn6UZCnm04EYe4u+I8srVU7aKlZWKGRdQs0wB7ZjvXGsthxcOwsoHd1kwi5Xhw0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168379232694790.99505306766264; Thu, 11 May 2023 01:05:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1IM-0006IS-KX; Thu, 11 May 2023 04:05:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1IG-0006I1-DJ for qemu-devel@nongnu.org; Thu, 11 May 2023 04:04:56 -0400 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IE-0000w4-Px for qemu-devel@nongnu.org; Thu, 11 May 2023 04:04:56 -0400 Received: by mail-ed1-x52b.google.com with SMTP id 4fb4d7f45d1cf-50bd875398dso12512099a12.1 for ; Thu, 11 May 2023 01:04:54 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.04.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:04:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792293; x=1686384293; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fbkyE6bJfLhheM4qb7LWlvv0iU1hoxBxThnKXs5khSU=; b=YV2ibgjTOw6ff3Hm3Nvv5s7UdNuPXInTZ1QTgAd8z69+cAX+cdWkTeCRRQj9uA4X+V hQ+krIkjT0XnbSFThNv71/OStOFUTc7lN9O/TZN5hM9wikCXfaahSKHOabhCoI6iOnZA zUfyUwQz9ryCi9G//ZQMrin0NVmCkGiE0y02fk/2gfCgLF/71IjYJfBim0Yv5mY1j65P dcwy2q/CRpv2Xhof7VFcbdebHUl98EL7hLnwFfONbtpktWspCYp9uV5Yfh+jhuy1ScUY Y3nh3aHcllB7ZjFItoY1fY6V3m/JtiQ+L4XrbDhS0rQ2fEhowacs/FR8s02Ht2NEftWu 0V9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792293; x=1686384293; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fbkyE6bJfLhheM4qb7LWlvv0iU1hoxBxThnKXs5khSU=; b=XwyuIwLYFAoglAAl/MJnfVg6FKeroNEvvqyz4Tfpx3QQ7/fCZNmUx3BYnSoA+ZMeDi qwaJ3yV+d1drpBxghrH6XVuCn0s4BGqSHpgMkC16LyZAqSND3W0bSfL3vutpxyDQbg6q DWt74WRcuk/tu49MxKb7iYla/97mH7tze+OjP9jPGTaAh5txs92iWpYCDhnUl05YVlpN fO94ttC66aKLLXN7Tzm5gHSu22AQiDQZLHPobi9+UqR+rW9yRp3bNYfdXMFY5hyk/y7d zTrRtjMTZjJunHSk4PnHvjdL4lARAPyF5uuhUf2JSS+cMS3LVmY2F7QEhorhLHTwChBF MAyg== X-Gm-Message-State: AC+VfDysD2UyGKA+TYbPh/PRiZvb/MeYX4HJ3pW5ili3KmAkqOpRtxf/ AgEMs5UEGqFE3l3Q7KMkA4BFScWii6pNRGlaI3Pz8Q== X-Google-Smtp-Source: ACHHUZ5aDYj08c6JWmFpr7XWeS0hbAtRcrccxXQ/sXkwiDHrcdiKAwSvysbfNBfhGB3PP3QWFlV8Rw== X-Received: by 2002:a05:6402:2d0:b0:50d:91c8:9e16 with SMTP id b16-20020a05640202d000b0050d91c89e16mr12441760edx.12.1683792293422; Thu, 11 May 2023 01:04:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 01/53] target/m68k: Fix gen_load_fp for OS_LONG Date: Thu, 11 May 2023 09:03:58 +0100 Message-Id: <20230511080450.860923-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792328257100001 Case was accidentally dropped in b7a94da9550b. Tested-by: Laurent Vivier Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/m68k/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 744eb3748b..44d852b106 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -959,6 +959,7 @@ static void gen_load_fp(DisasContext *s, int opsize, TC= Gv addr, TCGv_ptr fp, switch (opsize) { case OS_BYTE: case OS_WORD: + case OS_LONG: tcg_gen_qemu_ld_tl(tmp, addr, index, opsize | MO_SIGN | MO_TE); gen_helper_exts32(cpu_env, fp, tmp); break; --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792408; cv=none; d=zohomail.com; s=zohoarc; b=jeZBVrX18hlEpuVfXNpWaegGzMYr92stwW2Cw/2fL26RL5qjzOscIvyB44HQvtUr1F/7jpkLpod137POEI+cYSG4yHGDn97MRaQlWjoomv8XcrKzEng9sUZEpbyYN+nKXonS9bKjiikmvSsI7qWOzg/N/CxykZ+4EF5RLb6hMKg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792408; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/cqb6SMgF1kpXdbzqQmLZE9A6UROEDFcMPbJJOQUicI=; b=avWvs0SEhmDJpkR3RUO/NGTjOKrIAcJSHG+p29PGmzCbOU+UrnRmeDvKyVOwJPgVsAB6yNSjWEQ5wzyIHBTzs/WpMaZtv9hoI8HRdJQrt2ygwDxgwfhu1rdWIbBrEtvo12WLMSIkEgs7MeDN51j19vLyHtxkMC1JpUJtI+TcTsg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792408316443.7283033198911; Thu, 11 May 2023 01:06:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Ij-0006R3-7Y; Thu, 11 May 2023 04:05:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1IJ-0006IP-MX for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:00 -0400 Received: from mail-ed1-x532.google.com ([2a00:1450:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IG-0000wG-Ic for qemu-devel@nongnu.org; Thu, 11 May 2023 04:04:57 -0400 Received: by mail-ed1-x532.google.com with SMTP id 4fb4d7f45d1cf-50bcae898b2so14640593a12.0 for ; Thu, 11 May 2023 01:04:56 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.04.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:04:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792294; x=1686384294; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/cqb6SMgF1kpXdbzqQmLZE9A6UROEDFcMPbJJOQUicI=; b=Xs02Be5cmIK9kX9TFgLLekEfry3HIJctMtTxyqZGQzdcLH8nu2vMtCxHaEumu1zALa x5kQ98Tsvz9CT5u6klgt8UrYdfLltC7GSVFECc0BDklP1IOq2/vyJQOw2XCsWumACQ4L bIVf56cAEgwHYl8tAnEecERvwD9UE4v6zyh+Syj2WX+3m5THJnGr3AhrI2ZeNA3xwfCt 4UzhDRGxyE/NGXbiORcH8Ve7wseMgqdV//9Aw+UbMex0OfzVxtAn4N/J33fVA0NcfF9L zmNsCbJjf117CCzeIV85blFUHltEnU5TlC2bh97uTt2vDqawkNDVIRj00HiNpm8zkpBZ QuCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792294; x=1686384294; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/cqb6SMgF1kpXdbzqQmLZE9A6UROEDFcMPbJJOQUicI=; b=OsExUxxA85LS4aQmbQxG7xUT/RNDC17RW8/SWWJULuruUe55PvtJLpEc192NlrxGkB wZyPXGZdBJLhbGRRRX8hIa+muaLmfldAOtxW/BNCmifyaKBjhEoamXfVWCMuSfiOPkub vYASpG+KkWp34LgzMa5bari7cdyspfQjQjSm/nSuCQa/AqxNW+hDRKz3qhbuTlDANqqF FDP+k1TH0eSgVTKa13wRDwY61fm5Or/LKewvEYLL4ZqPi9cIEb5whSj+fBsKzbaUp+RB g17FH+2BntARWAkj27vGxvXznCqmTwYcb5daXmisHrrQesZIRSCR1HX3IHMnuC74WuGc dBBg== X-Gm-Message-State: AC+VfDyIr4lti4xCDxfL8/jKAtNyv+4nWeOozj/piRiQEc9zCIg8+2vX RtAlUSHW2/A+fp4sbExJ7bpqJjS55wWGU+U3qoh4qg== X-Google-Smtp-Source: ACHHUZ5YDMP07NB8B96BMMQ2A3Lol1WEtKSwEtVV9ZY307tqXrgnMuFwaXY1Wp0pWbB6mugwYvldEQ== X-Received: by 2002:aa7:d982:0:b0:509:f221:cee2 with SMTP id u2-20020aa7d982000000b00509f221cee2mr17314994eds.32.1683792294188; Thu, 11 May 2023 01:04:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 02/53] accel/tcg: Fix atomic_mmu_lookup for reads Date: Thu, 11 May 2023 09:03:59 +0100 Message-Id: <20230511080450.860923-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792408881100001 A copy-paste bug had us looking at the victim cache for writes. Cc: qemu-stable@nongnu.org Reported-by: Peter Maydell Signed-off-by: Richard Henderson Fixes: 08dff435e2 ("tcg: Probe the proper permissions for atomic ops") Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Message-Id: <20230505204049.352469-1-richard.henderson@linaro.org> --- accel/tcg/cputlb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 3117886af1..0b8a5f93d2 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1835,7 +1835,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, } else /* if (prot & PAGE_READ) */ { tlb_addr =3D tlbe->addr_read; if (!tlb_hit(tlb_addr, addr)) { - if (!VICTIM_TLB_HIT(addr_write, addr)) { + if (!VICTIM_TLB_HIT(addr_read, addr)) { tlb_fill(env_cpu(env), addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); index =3D tlb_index(env, mmu_idx, addr); --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792504; cv=none; d=zohomail.com; s=zohoarc; b=B8xHrbnpn9hjiiSXxum+5i6YJ8NA/nxYkc2BPcrbafE0ASI4ok061SHUTf0bCtyMoVcO4Xmd0KIyKzuMoMf7bdP8YKyvmBuVVJKd6FAApwUDdh6Uc9UI2wT/dPEcSXf9bXUxl0327J5/zOgRegHllcxed0qXr5hsRp9xIAONBz0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792504; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MH/FislB+PZ3yaaoaYyH7lf008m95iYymuHXns73bX4=; b=gOLrhmOeGoH1raLvwveGwddqh2noas7g7H9rbi3054MGAiV1N3bMkThWrhvlPR/LFnCo+5a4D6o3pI+49JuYRVtlwZPeH54PnVJZf9PgXTQ9MQ8xtfU08Ht3wRwFxTAIrKKbKcJh20hUofvbV51mImkwzZkEoBkQgIKLqdTZyqc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792504454457.2415463204103; Thu, 11 May 2023 01:08:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Ip-0006my-53; Thu, 11 May 2023 04:05:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1IJ-0006IQ-NK for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:00 -0400 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IG-0000wL-AV for qemu-devel@nongnu.org; Thu, 11 May 2023 04:04:57 -0400 Received: by mail-ed1-x536.google.com with SMTP id 4fb4d7f45d1cf-50be17a1eceso15586002a12.2 for ; Thu, 11 May 2023 01:04:55 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.04.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:04:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792295; x=1686384295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MH/FislB+PZ3yaaoaYyH7lf008m95iYymuHXns73bX4=; b=fKcyQA9IYtRkZmn4RVg9tSwIu/WWSWT29IZu7aemDdLROh4kCag9DxAZ6WMkWqxPAt UuGK7NDsXNiMUv9VCVfot10usJql6oTE78FQOLvRGBkIgimZlz5HAeRryXUUZuRjdD6d Q295U7aj3a0auZECR/KC5jpl3LD3cM6Y9FQU//MCKyd+9iuUnHo2cYjBMyLoJhiMCbNN PFDce1tbIsMyPdUXtIUzeaBbloJjVm+hstbvbTTRw7cE12BtxXCxW1y8381AyTQWNKsv c9BIcxxTDzx2RCJiZYC/bkrxHESjXa3CXKIa1W44JGFGkrG3Rj7WcV1f+9/0zc5HQEll g+MQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792295; x=1686384295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MH/FislB+PZ3yaaoaYyH7lf008m95iYymuHXns73bX4=; b=YbyHZ7Vzd2+ZM5mIHp2thskWZ/WQ7l/FkCMD0cf3MvtiK3FdVkMokX+kHOl/US4qrC 09LfyCKQutngnUHWyngI63cLNee/7+iOb9LsREbKOhaS66dmsp8dPqKGOwLX9GG0o/pC nRDCAhNgRCjFKC1zm104M2/N12bp3HcRFvTWUAFBJdVZTrBSbkgCMFg0vsdJmQlKZd+E vWWkamzHe0VDdHajdFdUUagPRNmTytkHtnV0SSFg+z3aqBCfCkFKV0WCc8nLS2tc27g8 svSxWJNJz1+D5JHsyymqM0dYB5O9UvGroYGNeylVLJfHEHp8OUYw0FOW66Z54jmbfE/L 1Kyw== X-Gm-Message-State: AC+VfDyoZSlzdDjCiZM2Ssh0zUJ3rRJnxdHrMn0UrvG6zL7hzwaMkvQS yTnKufcGv2U+TN4XzI9mrT0XLDYthUiwx0enMRjFbA== X-Google-Smtp-Source: ACHHUZ453/H57Sv4m5XVIWFG2v4ERkAcfl2ANjH5HKMWAl8jXNvEvPMw86LKGRbL6VysKVm/RaGkWw== X-Received: by 2002:aa7:c3d8:0:b0:50b:d75d:5dca with SMTP id l24-20020aa7c3d8000000b0050bd75d5dcamr15828641edr.42.1683792294870; Thu, 11 May 2023 01:04:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 03/53] disas: Fix tabs and braces in disas.c Date: Thu, 11 May 2023 09:04:00 +0100 Message-Id: <20230511080450.860923-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792505406100001 Content-Type: text/plain; charset="utf-8" Fix these before moving the file, for checkpatch.pl. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20230510170812.663149-1-richard.henderson@linaro.org> --- disas.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/disas.c b/disas.c index b087c12c47..d46f638a72 100644 --- a/disas.c +++ b/disas.c @@ -226,11 +226,12 @@ void target_disas(FILE *out, CPUState *cpu, target_ul= ong code, } =20 for (pc =3D code; size > 0; pc +=3D count, size -=3D count) { - fprintf(out, "0x" TARGET_FMT_lx ": ", pc); - count =3D s.info.print_insn(pc, &s.info); - fprintf(out, "\n"); - if (count < 0) - break; + fprintf(out, "0x" TARGET_FMT_lx ": ", pc); + count =3D s.info.print_insn(pc, &s.info); + fprintf(out, "\n"); + if (count < 0) { + break; + } if (size < count) { fprintf(out, "Disassembler disagrees with translator over instructi= on " --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792411; cv=none; d=zohomail.com; s=zohoarc; b=anVOVrjTdhKL6YrLBVyTNYy2n00jnjwDIAgHS/5apG2IChPoJZivP70sTSEaeqxoQrFJAV2C6O6w+NSwqFyXvvHXHHviBwgK6cFzJVnlbi9EJZCW5j1SU1mt+lW5csnVxMbXQFW1zLdGTlRrfD5Y/bXNN+0bVXnzkr4rfRy7zdg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792411; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=slYlxvey8vS8jO03oI+FfzvDLZXCxhNVbpSrio4xGh4=; b=l5Iqrfz8rkvDF6jIuh1BEdGS5cJ4UWyd/xdvR/mQaSqYosaeCkpzxd+bORgTv23V5G+hu74LVDs3BiNWahfNSiT7NB6eL+a5Ox593VE2MUVtnqnw0nm8ZiYLvJcH2i1T43AL5TzNSyCvcFR6zvGLoTRtCWSg0+xJ1Aw/7eM5apE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792411260640.0799796707233; Thu, 11 May 2023 01:06:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1IS-0006KE-Cq; Thu, 11 May 2023 04:05:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1IJ-0006IR-NC for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:00 -0400 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IG-0000wT-WD for qemu-devel@nongnu.org; Thu, 11 May 2023 04:04:58 -0400 Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-50bc4b88998so14604008a12.3 for ; Thu, 11 May 2023 01:04:56 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.04.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:04:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792295; x=1686384295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=slYlxvey8vS8jO03oI+FfzvDLZXCxhNVbpSrio4xGh4=; b=fW01KRHVdU+Ht00iycElVt0trwMiBnNYNnnKWpZKeAWH5aEEBDmipNZpX/LqGNJLMS X+eMKZopdEKJbHojZm9ctnK97B4Q2qCY5/cEg5+I/pZclZ+vtLiKy+869xpqfmZSyY+b KT8g1+XDks44XsrlTZL0PyiejD+Bck/6PPnV0bMFraLKZsyjQC9BlhqRKiglowOqisHT 8eVzj0RKtceNtAFUnlgA5cVE+sw0t3434VAYE3TNMXTcTGgKrZrmEW3Fx4g+tgol7Pvo Wt7UDbNjnVJ4ED6RNiQzs4NOIM09KYvBxPW7uLpZ0cwS9YbHlCkPe073LDZ/Slr3zdC9 AASw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792295; x=1686384295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=slYlxvey8vS8jO03oI+FfzvDLZXCxhNVbpSrio4xGh4=; b=BjO0jAMgLbVVHeOdeFjdFgytCF8mp7Fh3MoE5YZs558ps+QnNyilj4Ui5ZE9wxUDuu jDdzxxpp9Cpc/pCHfrq+T8KTPnfWMF1qjpsC4Qz4nCYTGnhUm9LMF8nqYI4sX7xPBaBJ eYe8SrPYLokYJtjbkHFpd6l3EA3VVoFLPa8U0w3cX8jIvvAZK+Qhi/XCp+QkaMG2fW18 4fjn5+yZxwVXPgfs+qtLIDHAx7iItGWYzyiVQxaOZQkBgmkh781MOyjl3cFgTRQRClfD YC8EKfMWrthzQooR9ifQNvZL+3x15/kB08CwYtLlJlSZs2bdrAyejCh+YIHRxUK8g4ps t/dA== X-Gm-Message-State: AC+VfDwbBlXIVmH9QHsGiDgDlrf6ZAybb+fuHrM4Z0PHBUhdR7LHlPpy npgAkWVjZF1dQk1Wct++r+i0VioOzgqcZajEDx4tgg== X-Google-Smtp-Source: ACHHUZ5vAdjwmtKz9WJ3ov9GJ/E1nj33VuWuIVzMGk9TYtxJh1s6RKstaQJejq58M9Rq1B+Tm79+xg== X-Received: by 2002:aa7:d8cb:0:b0:50b:d76a:7904 with SMTP id k11-20020aa7d8cb000000b0050bd76a7904mr14764431eds.28.1683792295577; Thu, 11 May 2023 01:04:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Thomas Huth Subject: [PULL 04/53] disas: Move disas.c to disas/ Date: Thu, 11 May 2023 09:04:01 +0100 Message-Id: <20230511080450.860923-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792412874100004 Content-Type: text/plain; charset="utf-8" Reviewed-by: Thomas Huth Signed-off-by: Richard Henderson Message-Id: <20230503072331.1747057-80-richard.henderson@linaro.org> --- meson.build | 3 --- disas.c =3D> disas/disas.c | 0 disas/meson.build | 4 +++- 3 files changed, 3 insertions(+), 4 deletions(-) rename disas.c =3D> disas/disas.c (100%) diff --git a/meson.build b/meson.build index 5c7af6f3bc..d3cf48960b 100644 --- a/meson.build +++ b/meson.build @@ -3153,9 +3153,6 @@ specific_ss.add(files('cpu.c')) =20 subdir('softmmu') =20 -common_ss.add(capstone) -specific_ss.add(files('disas.c'), capstone) - # Work around a gcc bug/misfeature wherein constant propagation looks # through an alias: # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D99696 diff --git a/disas.c b/disas/disas.c similarity index 100% rename from disas.c rename to disas/disas.c diff --git a/disas/meson.build b/disas/meson.build index c865bdd882..cbf6315f25 100644 --- a/disas/meson.build +++ b/disas/meson.build @@ -10,4 +10,6 @@ common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files('r= iscv.c')) common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c')) common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c')) common_ss.add(when: 'CONFIG_XTENSA_DIS', if_true: files('xtensa.c')) -common_ss.add(when: capstone, if_true: files('capstone.c')) +common_ss.add(when: capstone, if_true: [files('capstone.c'), capstone]) + +specific_ss.add(files('disas.c'), capstone) --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792334; cv=none; d=zohomail.com; s=zohoarc; b=iEe93xHtpj9s/GE+TmJe2pYO1IbWKCFdw+YTPuzEH3DaxBm/T0Cp5GxZeG85kwvcoiyQtXpDVsa5aeugyJTht/miHpTbp0EVywP433uIW1U6TKE7wIsHS4J7LOeue+k2hgYL4bShqSJUgE83QaxxngIvrJd6eILs5FrYUIhcSik= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792334; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6Az8WcHOgmzjU41IoVy9JVQ9yyean8ToXLY6lPiG6LY=; b=VHKIDvOeE4T7gDTooZbs7TVLi7MLwXfS7HlqNJ4u8z4IaIXyKGHiSj2LB4DvLmFwPpVjzxjqR7EUoCGaXJZtks9UA4RZdEa0lBnup9IFA+bx7fQhseyLYcsShyK4ANGJ3hcEgDF1E+mjWOHCN2gI3QFkKe27QX9Ixgy+deWk/L8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792334355924.2188332517086; Thu, 11 May 2023 01:05:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1IW-0006MQ-9j; Thu, 11 May 2023 04:05:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1IL-0006Ia-GG for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:02 -0400 Received: from mail-ed1-x535.google.com ([2a00:1450:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1II-0000wh-DU for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:00 -0400 Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-50bc37e1525so15593154a12.1 for ; Thu, 11 May 2023 01:04:57 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.04.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:04:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792296; x=1686384296; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6Az8WcHOgmzjU41IoVy9JVQ9yyean8ToXLY6lPiG6LY=; b=amhE8Hvl1VNR34giNIwRiF9Y1Si2yRdqKIub7q58k8IrXDN8z4YFco2xbGgkJv7166 ZScsZRvBOn2fZmkwpxw1JqluP6/rmXe0jV8QEjPoiQEh7E9QnMg9qCKS3CqfBsqaDTMi JZYJN1ohd16wGY+FLoMUNWwjIF5gGU6DA7/PoKrIM1KFHqwol9F4tczP6ebYFa1QNOuL EbZiNoSK+mwdW0JtfGYwlC7LCLyp2q/hljrNluIaP2cJZTrKpA+EMRNGSu33fEUbOVnL eBVHOZf42gDWeqPhW0o3q60uFXRz91xiw3hLmt2swxX8/A8PMgQs5bBE5HCjXFhWe+0a ibZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792296; x=1686384296; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6Az8WcHOgmzjU41IoVy9JVQ9yyean8ToXLY6lPiG6LY=; b=WpuAFKL1mUGQghmoYfpdOi23iucVH3xOHNbNND4MNzatSCfNQbNOhGygV3Qn+OuaPL 2q+XZY/7PntJI38Fxn5qct416arxT+iw6agRUTGGpFrEKe+ticc5sqrmIH7NUpiOXHc+ 9JyP7C5Jezm23Sq7DH33Kv8rAyjhdBHk/1WmG40unY7cuFAkfK2ECa0DDfCVJpcKqm5U G6SMFXPpyGw3rxp27r8wZ8024lbT+gfEwh31ui2di0E4TvepJKGsnz1siy2HUm421LkU 1nXYL9479KrpuE2hHUBov1dfGbkwpWlSFeQ+TwjAwiOpFEZGp0Bjx/alWxNgcNbvs7NG T7Iw== X-Gm-Message-State: AC+VfDzInLv7fNBopa2JfGNROGTDScz7YvcVud1wi6z2uALGrWRafItb +JmxP3ml14BjdF+hYpbHipjlBZwV4Tm09TeGdVkUhA== X-Google-Smtp-Source: ACHHUZ7W/JTehh5Y86dYOao06jwi2spM9ZLu4/8BJmhdgV5P3K93puq+Dk9F8NCH0besdlgQ9kt4mw== X-Received: by 2002:aa7:cc8b:0:b0:50b:d2f2:43f with SMTP id p11-20020aa7cc8b000000b0050bd2f2043fmr14403490edt.35.1683792296054; Thu, 11 May 2023 01:04:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Thomas Huth Subject: [PULL 05/53] disas: Remove target_ulong from the interface Date: Thu, 11 May 2023 09:04:02 +0100 Message-Id: <20230511080450.860923-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792334686100001 Content-Type: text/plain; charset="utf-8" Use uint64_t for the pc, and size_t for the size. Reviewed-by: Thomas Huth Signed-off-by: Richard Henderson Message-Id: <20230503072331.1747057-81-richard.henderson@linaro.org> --- include/disas/disas.h | 17 ++++++----------- bsd-user/elfload.c | 5 +++-- disas/disas.c | 19 +++++++++---------- linux-user/elfload.c | 5 +++-- 4 files changed, 21 insertions(+), 25 deletions(-) diff --git a/include/disas/disas.h b/include/disas/disas.h index d363e95ede..6c394e0b09 100644 --- a/include/disas/disas.h +++ b/include/disas/disas.h @@ -7,28 +7,23 @@ #include "cpu.h" =20 /* Disassemble this for me please... (debugging). */ -void disas(FILE *out, const void *code, unsigned long size); -void target_disas(FILE *out, CPUState *cpu, target_ulong code, - target_ulong size); +void disas(FILE *out, const void *code, size_t size); +void target_disas(FILE *out, CPUState *cpu, uint64_t code, size_t size); =20 -void monitor_disas(Monitor *mon, CPUState *cpu, - target_ulong pc, int nb_insn, int is_physical); +void monitor_disas(Monitor *mon, CPUState *cpu, uint64_t pc, + int nb_insn, bool is_physical); =20 char *plugin_disas(CPUState *cpu, uint64_t addr, size_t size); =20 /* Look up symbol for debugging purpose. Returns "" if unknown. */ -const char *lookup_symbol(target_ulong orig_addr); +const char *lookup_symbol(uint64_t orig_addr); #endif =20 struct syminfo; struct elf32_sym; struct elf64_sym; =20 -#if defined(CONFIG_USER_ONLY) -typedef const char *(*lookup_symbol_t)(struct syminfo *s, target_ulong ori= g_addr); -#else -typedef const char *(*lookup_symbol_t)(struct syminfo *s, hwaddr orig_addr= ); -#endif +typedef const char *(*lookup_symbol_t)(struct syminfo *s, uint64_t orig_ad= dr); =20 struct syminfo { lookup_symbol_t lookup_symbol; diff --git a/bsd-user/elfload.c b/bsd-user/elfload.c index fbcdc94b96..2e76f0d3b5 100644 --- a/bsd-user/elfload.c +++ b/bsd-user/elfload.c @@ -352,9 +352,10 @@ static abi_ulong load_elf_interp(struct elfhdr *interp= _elf_ex, =20 static int symfind(const void *s0, const void *s1) { - target_ulong addr =3D *(target_ulong *)s0; + __typeof(sym->st_value) addr =3D *(uint64_t *)s0; struct elf_sym *sym =3D (struct elf_sym *)s1; int result =3D 0; + if (addr < sym->st_value) { result =3D -1; } else if (addr >=3D sym->st_value + sym->st_size) { @@ -363,7 +364,7 @@ static int symfind(const void *s0, const void *s1) return result; } =20 -static const char *lookup_symbolxx(struct syminfo *s, target_ulong orig_ad= dr) +static const char *lookup_symbolxx(struct syminfo *s, uint64_t orig_addr) { #if ELF_CLASS =3D=3D ELFCLASS32 struct elf_sym *syms =3D s->disas_symtab.elf32; diff --git a/disas/disas.c b/disas/disas.c index d46f638a72..aac7cf3b03 100644 --- a/disas/disas.c +++ b/disas/disas.c @@ -204,10 +204,9 @@ static void initialize_debug_host(CPUDebug *s) } =20 /* Disassemble this for me please... (debugging). */ -void target_disas(FILE *out, CPUState *cpu, target_ulong code, - target_ulong size) +void target_disas(FILE *out, CPUState *cpu, uint64_t code, size_t size) { - target_ulong pc; + uint64_t pc; int count; CPUDebug s; =20 @@ -226,7 +225,7 @@ void target_disas(FILE *out, CPUState *cpu, target_ulon= g code, } =20 for (pc =3D code; size > 0; pc +=3D count, size -=3D count) { - fprintf(out, "0x" TARGET_FMT_lx ": ", pc); + fprintf(out, "0x%08" PRIx64 ": ", pc); count =3D s.info.print_insn(pc, &s.info); fprintf(out, "\n"); if (count < 0) { @@ -293,7 +292,7 @@ char *plugin_disas(CPUState *cpu, uint64_t addr, size_t= size) } =20 /* Disassemble this for me please... (debugging). */ -void disas(FILE *out, const void *code, unsigned long size) +void disas(FILE *out, const void *code, size_t size) { uintptr_t pc; int count; @@ -325,7 +324,7 @@ void disas(FILE *out, const void *code, unsigned long s= ize) } =20 /* Look up symbol for debugging purpose. Returns "" if unknown. */ -const char *lookup_symbol(target_ulong orig_addr) +const char *lookup_symbol(uint64_t orig_addr) { const char *symbol =3D ""; struct syminfo *s; @@ -357,8 +356,8 @@ physical_read_memory(bfd_vma memaddr, bfd_byte *myaddr,= int length, } =20 /* Disassembler for the monitor. */ -void monitor_disas(Monitor *mon, CPUState *cpu, - target_ulong pc, int nb_insn, int is_physical) +void monitor_disas(Monitor *mon, CPUState *cpu, uint64_t pc, + int nb_insn, bool is_physical) { int count, i; CPUDebug s; @@ -379,13 +378,13 @@ void monitor_disas(Monitor *mon, CPUState *cpu, } =20 if (!s.info.print_insn) { - monitor_printf(mon, "0x" TARGET_FMT_lx + monitor_printf(mon, "0x%08" PRIx64 ": Asm output not supported on this arch\n", pc); return; } =20 for (i =3D 0; i < nb_insn; i++) { - g_string_append_printf(ds, "0x" TARGET_FMT_lx ": ", pc); + g_string_append_printf(ds, "0x%08" PRIx64 ": ", pc); count =3D s.info.print_insn(pc, &s.info); g_string_append_c(ds, '\n'); if (count < 0) { diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 703f7434a0..80085b8a30 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -3327,9 +3327,10 @@ static void load_elf_interp(const char *filename, st= ruct image_info *info, =20 static int symfind(const void *s0, const void *s1) { - target_ulong addr =3D *(target_ulong *)s0; struct elf_sym *sym =3D (struct elf_sym *)s1; + __typeof(sym->st_value) addr =3D *(uint64_t *)s0; int result =3D 0; + if (addr < sym->st_value) { result =3D -1; } else if (addr >=3D sym->st_value + sym->st_size) { @@ -3338,7 +3339,7 @@ static int symfind(const void *s0, const void *s1) return result; } =20 -static const char *lookup_symbolxx(struct syminfo *s, target_ulong orig_ad= dr) +static const char *lookup_symbolxx(struct syminfo *s, uint64_t orig_addr) { #if ELF_CLASS =3D=3D ELFCLASS32 struct elf_sym *syms =3D s->disas_symtab.elf32; --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792765; cv=none; d=zohomail.com; s=zohoarc; b=ZniooecHI0OFIvMX7sIHfpIpLBCjrpk/rjQT7QWjmwDe/g818OxeovwwaflFMBJs4iqQApLjnUv5GKJ/s7OewYFCwcdACLbGtuOUL7lVLBXLD63n+iqN9irnv2CILoV3ZOy48R2i+7oX5Ylc5h0s5DzZ6s1fSeieaTeY7STDSG8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792765; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Hh23CcAHzAZeDiuALc/R+n3TikDVtA9YTdeEDvFpi4s=; b=gbVLlyp8LTPVKA4hDIrQ2jDw5EQwXqcOHkuX9kqlXFyfjaiIcEyp3DUe4CKcyGnBUrY2mq9qE0M7fN7bZPprE923DyxlIUeHm9JlkBPmE1b4Z0fzJTmImRaro9VrEpAjBVlhlg1XmvptaFiwouOq2vXvxGJlnGjyDpoQuqZFRo0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792765643585.434576236926; Thu, 11 May 2023 01:12:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Ib-0006PN-S5; Thu, 11 May 2023 04:05:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1IN-0006JK-FP for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:05 -0400 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IJ-0000wq-DC for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:02 -0400 Received: by mail-ed1-x529.google.com with SMTP id 4fb4d7f45d1cf-50bc570b4a3so15012100a12.1 for ; Thu, 11 May 2023 01:04:57 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.04.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:04:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792296; x=1686384296; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hh23CcAHzAZeDiuALc/R+n3TikDVtA9YTdeEDvFpi4s=; b=vTQiQjPa8bAWeHlq/2NR/ODtEJKOse7ozhLthoGsTlMrsiiQ/eq23npixi3X+0LfAh PyFlpQ5dlaVk+RkpvpEY4Puc+bwf2NSm0sFiS0U5mRM2oYKfWH9eCgHJOiExkVs1A2ir Gfk1yAizLqoHJo66eTbkyblFEcdWp73iTjY6RWvHab/oGz27Rj8EcKDl//xVwe6Fy73T CK5dk6ZlxriR05f+FUFlaC4Dx6CBTslgaXCU9j8o2bflJDDY8M5sXgF5zvJBhUp7oRNb RWgJ9KuXI0ljKZWiFn7w3s7OchHpq7NruFii9ixxtDMFw/Iq8l2TOTutOCB751wKkCZe uNUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792296; x=1686384296; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hh23CcAHzAZeDiuALc/R+n3TikDVtA9YTdeEDvFpi4s=; b=AMMHRVruhHqAwpUC0JMaE6K1k3pnWVTFgdkPs79F3WvdfgSM+nGBXaCzukzT7Jitt6 1o6L96IIt36ttTs3an7kl5osjYnszkGA2KJgfZYUdAQj5mxxYGSbF4A5Lhyplbt7dHqP vekzmm+KiYz5OzC4lIBhgXUgy1PSwNYEI8QwJYYpyw3l7bx4Lspzpt1BdJN9OPPZWD/H 18DGTQ/B31HhALZn47y1JJita8VXI9T+5305LY7NR+Ij8dJKXla/BpYLe2OrhTkmv8S6 2HE0qZIdwuLyfch47zrapwy/ksiit54U6Ek6dKplkT9gZAyjByJMk60BoagQm6XMGzxB 7CwQ== X-Gm-Message-State: AC+VfDz/8ASgnvBYfsKfMRC5Fj3d74SrOv0PvRZ5DTZLqbtnUFnC2q2Q mS3raKQDqo+3zr5i2ljUlEl6JGwFIieP5iS2bXpuLA== X-Google-Smtp-Source: ACHHUZ7BT6k9AiQ5FELFUeJaALLPktB876FT1z226U0B9XJgAcRaJdkrocwU2Rfi1pXm10zfqfTejg== X-Received: by 2002:aa7:d1d0:0:b0:50b:d731:9fa8 with SMTP id g16-20020aa7d1d0000000b0050bd7319fa8mr15455132edp.28.1683792296600; Thu, 11 May 2023 01:04:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Thomas Huth Subject: [PULL 06/53] disas: Remove target-specific headers Date: Thu, 11 May 2023 09:04:03 +0100 Message-Id: <20230511080450.860923-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792766219100005 Content-Type: text/plain; charset="utf-8" Reviewed-by: Thomas Huth Signed-off-by: Richard Henderson Message-Id: <20230503072331.1747057-83-richard.henderson@linaro.org> --- include/disas/disas.h | 6 ------ disas/disas.c | 3 ++- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/include/disas/disas.h b/include/disas/disas.h index 6c394e0b09..176775eff7 100644 --- a/include/disas/disas.h +++ b/include/disas/disas.h @@ -1,11 +1,6 @@ #ifndef QEMU_DISAS_H #define QEMU_DISAS_H =20 -#include "exec/hwaddr.h" - -#ifdef NEED_CPU_H -#include "cpu.h" - /* Disassemble this for me please... (debugging). */ void disas(FILE *out, const void *code, size_t size); void target_disas(FILE *out, CPUState *cpu, uint64_t code, size_t size); @@ -17,7 +12,6 @@ char *plugin_disas(CPUState *cpu, uint64_t addr, size_t s= ize); =20 /* Look up symbol for debugging purpose. Returns "" if unknown. */ const char *lookup_symbol(uint64_t orig_addr); -#endif =20 struct syminfo; struct elf32_sym; diff --git a/disas/disas.c b/disas/disas.c index aac7cf3b03..a06954254b 100644 --- a/disas/disas.c +++ b/disas/disas.c @@ -3,9 +3,10 @@ #include "disas/dis-asm.h" #include "elf.h" #include "qemu/qemu-print.h" - #include "disas/disas.h" #include "disas/capstone.h" +#include "hw/core/cpu.h" +#include "exec/memory.h" =20 typedef struct CPUDebug { struct disassemble_info info; --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792345; cv=none; d=zohomail.com; s=zohoarc; b=bszz3fLnjJg+NyH0ZzcwNI9P4KBNT1l0w6lBWvk7trevOCE5c9GDkyERUqfvcWed01toHNs7/qYS2xQ0T7GK+b3w54QIpsXFekvZeRua9mcYoCkmT2dui6q45OVXb0qINIlEV7KdT6d1LyDCXkeE1rHv6LRMOQyB+spM3Vl9lt4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792345; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/w4TC2x/MHMk9Ao0+lVZ7OcQUDEv1JV3QxIfXizq1io=; b=QHV/cbwMjDbjETa+ByklBSASQvvhcazoAVNoT5sKHp9b60D4hubBnyiRcChC7lWYE6SB8AgpVfZFxhAYECMPyRQMX7xJ1ezDG/xnQ1l8A+S1e3Tu/84pdk7xIFUVXoN55mi1Y/+iFm+j0WdEqEow91YMJEi+QbhTImA7EJfr6qs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792345263322.7192243341933; Thu, 11 May 2023 01:05:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1IY-0006NK-H1; Thu, 11 May 2023 04:05:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1IN-0006JL-Fb for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:05 -0400 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IJ-0000x2-Ef for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:02 -0400 Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-50db7ec8188so4836969a12.2 for ; Thu, 11 May 2023 01:04:58 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.04.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:04:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792297; x=1686384297; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/w4TC2x/MHMk9Ao0+lVZ7OcQUDEv1JV3QxIfXizq1io=; b=H5NxAMfIQgano+lRowYSclNtkepUAuhDcFP9aIEXIXg1wSgQSZ57Snv2CKQSQNHEuI 062du9IaSqH6fmix8WrtSCYrqZUpNKoakNY6Zz5aN75EsiTgU1mayJoSnn31xzoBW2Cp W5QNcBx6O/VgTQ9hEoDa08TX8Vf3wRtgrCbObl+MzRyy/zsODw9l/Q2JA9ktq2Fb4BeP +XENOf186SCHMvkU07k+43EhnzBEn9fxK0APuG1gheEBVkaOlAmU0R13WnyMIadFqqVR duFo823yoInEqZhGky/4VAz6O9ZJAvrSVYscsHqNu4KBUOtvVDIIUsBDs0y9BKhXhTYx xKtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792297; x=1686384297; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/w4TC2x/MHMk9Ao0+lVZ7OcQUDEv1JV3QxIfXizq1io=; b=T7u/asaNGRLnbk2P0Xeg0IRa8ZTJ+l6YLE+9QAhxrhkjVekQ/1kMCvwY+dj4Jpa0Ra M92Ad+7KCOTnz8oF7EblUV8GZbb0OAfJRbXGC6qmm5PgYZ2soX0XPwpaUC/bPTeBxcVG GUkBnXP9JyLAjHh8SkkuYaRVNC1VjoHSD0g/lobuPhuWq4dq+XlWrWB6KHHKwyPjOnXh ZMpO63R0haiLQ5QT2EYo4p9oD+zqwjq0/xpxU8HbaU9n0g6FoY9JleJank/3HisnG6AA J+OI4OevckZS4ANSsPRUe2l4j9d1P8TGkeuTMIvxyZq2bFK4XfNs81EXjzWR2bOF0pOF qVMw== X-Gm-Message-State: AC+VfDy4zcyIZWAcrZiBfge09FLDOPqLheg96pj6yiDdqhSXr6/ZerhQ nnVcgLJRl/+b9CAsOQ55pJkHqgrcnNfnmaOYQeB8QQ== X-Google-Smtp-Source: ACHHUZ6/2dkPrSSYhe3uCPO//b3ZuYI2KnOMse6jU2syoIssviBSidw6BMRUItxCLc+iUNdyOngoRg== X-Received: by 2002:a17:907:a49:b0:96a:30b5:cfac with SMTP id be9-20020a1709070a4900b0096a30b5cfacmr3623521ejc.28.1683792297352; Thu, 11 May 2023 01:04:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Thomas Huth Subject: [PULL 07/53] disas: Move softmmu specific code to separate file Date: Thu, 11 May 2023 09:04:04 +0100 Message-Id: <20230511080450.860923-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_PDS_OTHER_BAD_TLD=0.01, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792346429100001 Content-Type: text/plain; charset="utf-8" From: Thomas Huth We'd like to move disas.c into the common code source set, where CONFIG_USER_ONLY is not available anymore. So we have to move the related code into a separate file instead. Signed-off-by: Thomas Huth Message-Id: <20230508133745.109463-2-thuth@redhat.com> [rth: Type change done in a separate patch] Signed-off-by: Richard Henderson --- disas/disas-internal.h | 21 ++++++++++++ disas/disas-mon.c | 65 ++++++++++++++++++++++++++++++++++++ disas/disas.c | 76 ++++-------------------------------------- disas/meson.build | 1 + 4 files changed, 93 insertions(+), 70 deletions(-) create mode 100644 disas/disas-internal.h create mode 100644 disas/disas-mon.c diff --git a/disas/disas-internal.h b/disas/disas-internal.h new file mode 100644 index 0000000000..84a01f126f --- /dev/null +++ b/disas/disas-internal.h @@ -0,0 +1,21 @@ +/* + * Definitions used internally in the disassembly code + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef DISAS_INTERNAL_H +#define DISAS_INTERNAL_H + +#include "disas/dis-asm.h" + +typedef struct CPUDebug { + struct disassemble_info info; + CPUState *cpu; +} CPUDebug; + +void disas_initialize_debug_target(CPUDebug *s, CPUState *cpu); +int disas_gstring_printf(FILE *stream, const char *fmt, ...) + G_GNUC_PRINTF(2, 3); + +#endif diff --git a/disas/disas-mon.c b/disas/disas-mon.c new file mode 100644 index 0000000000..48ac492c6c --- /dev/null +++ b/disas/disas-mon.c @@ -0,0 +1,65 @@ +/* + * Functions related to disassembly from the monitor + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "disas-internal.h" +#include "disas/disas.h" +#include "exec/memory.h" +#include "hw/core/cpu.h" +#include "monitor/monitor.h" + +static int +physical_read_memory(bfd_vma memaddr, bfd_byte *myaddr, int length, + struct disassemble_info *info) +{ + CPUDebug *s =3D container_of(info, CPUDebug, info); + MemTxResult res; + + res =3D address_space_read(s->cpu->as, memaddr, MEMTXATTRS_UNSPECIFIED, + myaddr, length); + return res =3D=3D MEMTX_OK ? 0 : EIO; +} + +/* Disassembler for the monitor. */ +void monitor_disas(Monitor *mon, CPUState *cpu, uint64_t pc, + int nb_insn, bool is_physical) +{ + int count, i; + CPUDebug s; + g_autoptr(GString) ds =3D g_string_new(""); + + disas_initialize_debug_target(&s, cpu); + s.info.fprintf_func =3D disas_gstring_printf; + s.info.stream =3D (FILE *)ds; /* abuse this slot */ + + if (is_physical) { + s.info.read_memory_func =3D physical_read_memory; + } + s.info.buffer_vma =3D pc; + + if (s.info.cap_arch >=3D 0 && cap_disas_monitor(&s.info, pc, nb_insn))= { + monitor_puts(mon, ds->str); + return; + } + + if (!s.info.print_insn) { + monitor_printf(mon, "0x%08" PRIx64 + ": Asm output not supported on this arch\n", pc); + return; + } + + for (i =3D 0; i < nb_insn; i++) { + g_string_append_printf(ds, "0x%08" PRIx64 ": ", pc); + count =3D s.info.print_insn(pc, &s.info); + g_string_append_c(ds, '\n'); + if (count < 0) { + break; + } + pc +=3D count; + } + + monitor_puts(mon, ds->str); +} diff --git a/disas/disas.c b/disas/disas.c index a06954254b..45614af02d 100644 --- a/disas/disas.c +++ b/disas/disas.c @@ -1,6 +1,6 @@ /* General "disassemble this chunk" code. Used for debugging. */ #include "qemu/osdep.h" -#include "disas/dis-asm.h" +#include "disas/disas-internal.h" #include "elf.h" #include "qemu/qemu-print.h" #include "disas/disas.h" @@ -8,11 +8,6 @@ #include "hw/core/cpu.h" #include "exec/memory.h" =20 -typedef struct CPUDebug { - struct disassemble_info info; - CPUState *cpu; -} CPUDebug; - /* Filled in by elfload.c. Simplistic, but will do for now. */ struct syminfo *syminfos =3D NULL; =20 @@ -120,7 +115,7 @@ static void initialize_debug(CPUDebug *s) s->info.symbol_at_address_func =3D symbol_at_address; } =20 -static void initialize_debug_target(CPUDebug *s, CPUState *cpu) +void disas_initialize_debug_target(CPUDebug *s, CPUState *cpu) { initialize_debug(s); =20 @@ -211,7 +206,7 @@ void target_disas(FILE *out, CPUState *cpu, uint64_t co= de, size_t size) int count; CPUDebug s; =20 - initialize_debug_target(&s, cpu); + disas_initialize_debug_target(&s, cpu); s.info.fprintf_func =3D fprintf; s.info.stream =3D out; s.info.buffer_vma =3D code; @@ -242,8 +237,7 @@ void target_disas(FILE *out, CPUState *cpu, uint64_t co= de, size_t size) } } =20 -static int G_GNUC_PRINTF(2, 3) -gstring_printf(FILE *stream, const char *fmt, ...) +int disas_gstring_printf(FILE *stream, const char *fmt, ...) { /* We abuse the FILE parameter to pass a GString. */ GString *s =3D (GString *)stream; @@ -273,8 +267,8 @@ char *plugin_disas(CPUState *cpu, uint64_t addr, size_t= size) CPUDebug s; GString *ds =3D g_string_new(NULL); =20 - initialize_debug_target(&s, cpu); - s.info.fprintf_func =3D gstring_printf; + disas_initialize_debug_target(&s, cpu); + s.info.fprintf_func =3D disas_gstring_printf; s.info.stream =3D (FILE *)ds; /* abuse this slot */ s.info.buffer_vma =3D addr; s.info.buffer_length =3D size; @@ -339,61 +333,3 @@ const char *lookup_symbol(uint64_t orig_addr) =20 return symbol; } - -#if !defined(CONFIG_USER_ONLY) - -#include "monitor/monitor.h" - -static int -physical_read_memory(bfd_vma memaddr, bfd_byte *myaddr, int length, - struct disassemble_info *info) -{ - CPUDebug *s =3D container_of(info, CPUDebug, info); - MemTxResult res; - - res =3D address_space_read(s->cpu->as, memaddr, MEMTXATTRS_UNSPECIFIED, - myaddr, length); - return res =3D=3D MEMTX_OK ? 0 : EIO; -} - -/* Disassembler for the monitor. */ -void monitor_disas(Monitor *mon, CPUState *cpu, uint64_t pc, - int nb_insn, bool is_physical) -{ - int count, i; - CPUDebug s; - g_autoptr(GString) ds =3D g_string_new(""); - - initialize_debug_target(&s, cpu); - s.info.fprintf_func =3D gstring_printf; - s.info.stream =3D (FILE *)ds; /* abuse this slot */ - - if (is_physical) { - s.info.read_memory_func =3D physical_read_memory; - } - s.info.buffer_vma =3D pc; - - if (s.info.cap_arch >=3D 0 && cap_disas_monitor(&s.info, pc, nb_insn))= { - monitor_puts(mon, ds->str); - return; - } - - if (!s.info.print_insn) { - monitor_printf(mon, "0x%08" PRIx64 - ": Asm output not supported on this arch\n", pc); - return; - } - - for (i =3D 0; i < nb_insn; i++) { - g_string_append_printf(ds, "0x%08" PRIx64 ": ", pc); - count =3D s.info.print_insn(pc, &s.info); - g_string_append_c(ds, '\n'); - if (count < 0) { - break; - } - pc +=3D count; - } - - monitor_puts(mon, ds->str); -} -#endif diff --git a/disas/meson.build b/disas/meson.build index cbf6315f25..f40230c58f 100644 --- a/disas/meson.build +++ b/disas/meson.build @@ -12,4 +12,5 @@ common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('s= parc.c')) common_ss.add(when: 'CONFIG_XTENSA_DIS', if_true: files('xtensa.c')) common_ss.add(when: capstone, if_true: [files('capstone.c'), capstone]) =20 +softmmu_ss.add(files('disas-mon.c')) specific_ss.add(files('disas.c'), capstone) --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792692; cv=none; d=zohomail.com; s=zohoarc; b=CzW8DPocg2imH9sjgL5DGGH1bgjGX1u2vkOAW5F+lIzyGixqE8xoA1F3sKYlNRwMCrCb6WXFT+nshXXw5qdIOxgf/n6o5te8ZhNbBDrXX8WkAGEqGZwZoPAI8ya3x15MkXWk0uWj+8x/hQSx66IkVkvDhcv2zerHU3qbuR0srNQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792692; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=I/9c63Radhgc81C1RKjpHc6zkE/Zkh0JPyRZzb2Zqao=; b=VrGUKIRnyPULsG8C4XLXVy7YnKnDKm0j9QjGaIz4nrJH1/5Cj2Rp1MZ6nw1hEI23ikC1mfri4rqH9BdzXGRerE2TRO4OODBAUWpVn3fEfAkxeQUN4MffO5ZZQM6Qn5TKm2p3eXQK6Pgk5Z1fEnAlZUdOQTI8XhV/hcIRRK3DZac= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168379269223492.73960105356286; Thu, 11 May 2023 01:11:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Ia-0006Oi-Ku; Thu, 11 May 2023 04:05:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1IV-0006Ke-4u for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:12 -0400 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IK-0000x5-1j for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:08 -0400 Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-50bcb4a81ceso14613170a12.2 for ; Thu, 11 May 2023 01:04:59 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.04.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:04:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792298; x=1686384298; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=I/9c63Radhgc81C1RKjpHc6zkE/Zkh0JPyRZzb2Zqao=; b=g1BwYUTGIhvh9p+PL7x55z/Y8A0wXqfW1tG34hFXhn8PGSLQ1HnKpS7tT3da3jdRnD aJEVUjKTs1HlSVaaVwipq0eUQL+lXLj3JeLJ18ZQuGkc+32/1gDiY7oOLFweyxBPTmJ/ WPRe9pR+4rMJb6UxbNUMjazUYTNll7+/G7qXxTfL19xnt6brk8P1h8LAguQVqbKQm/AS u3mfDneNjvji6Pzb5K5MSaSdqSrWTXgqRgN/qFz9wcyBzPEmccYewXcbLi8PsauLb6Pf eoE8HWJxytYkPXlvlc/a5Qa5RfCIrfaZzTWKJj9O0r+68oRdcaK0CopESosAhXWPdQJd 5YUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792298; x=1686384298; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I/9c63Radhgc81C1RKjpHc6zkE/Zkh0JPyRZzb2Zqao=; b=G+MPpQg7vvdJCjTcWbbTvcZfGByE07Rcax3S9IkmBv0xeIWJ0fKtnLNGcVa19Yvuxr 9G3kCfuI6FIfxPyUD+w3ZksZiU5hgY++GvOkU2XwczBlnS+YzZUlWetlMywCJ9t1RtKY MqCwRv8jlRUQDwUfpTzFm9BPZsdXUqA9ib6/Uq28ZOVHmfm8KAOiLQPACRYkuEe5ZTYf zYk8k4UUVIrg7T7ypRB8IVbmX5H6eVLou9SrIUu8h4PezIVOl27qxI5jzlCS/7AWLAZc NQ8WWUpOqOx4Kkj8LbBVQMM4xuHLHENfiIpbiN1e+Epz+mHc5/r4pmEP7UU2yeDxvN0I Xd3A== X-Gm-Message-State: AC+VfDx+VLzBe6HAOKcUsXT9QTsmNvv+FOlRQw5wvzHXHnDXM+GTT1hW plxsIbsy119F3Xvwwj4wycSALam6PrTNj9oYJ7RH5A== X-Google-Smtp-Source: ACHHUZ6PiHNpNXH7OFDH+aDPQVW1OqBtJg1LbvgQDqljyKlurOxOVcke1j+GLDpTNlhNPHOjQwl7uw== X-Received: by 2002:aa7:d88f:0:b0:50b:c1e3:6f02 with SMTP id u15-20020aa7d88f000000b0050bc1e36f02mr16981690edq.21.1683792297923; Thu, 11 May 2023 01:04:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Thomas Huth Subject: [PULL 08/53] disas: Move disas.c into the target-independent source set Date: Thu, 11 May 2023 09:04:05 +0100 Message-Id: <20230511080450.860923-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792694141100003 Content-Type: text/plain; charset="utf-8" From: Thomas Huth By using target_words_bigendian() instead of an ifdef, we can build this code once. Signed-off-by: Thomas Huth Message-Id: <20230508133745.109463-3-thuth@redhat.com> [rth: Type change done in a separate patch] Signed-off-by: Richard Henderson --- disas/disas.c | 10 +++++----- disas/meson.build | 3 ++- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/disas/disas.c b/disas/disas.c index 45614af02d..f405f4762a 100644 --- a/disas/disas.c +++ b/disas/disas.c @@ -122,11 +122,11 @@ void disas_initialize_debug_target(CPUDebug *s, CPUSt= ate *cpu) s->cpu =3D cpu; s->info.read_memory_func =3D target_read_memory; s->info.print_address_func =3D print_address; -#if TARGET_BIG_ENDIAN - s->info.endian =3D BFD_ENDIAN_BIG; -#else - s->info.endian =3D BFD_ENDIAN_LITTLE; -#endif + if (target_words_bigendian()) { + s->info.endian =3D BFD_ENDIAN_BIG; + } else { + s->info.endian =3D BFD_ENDIAN_LITTLE; + } =20 CPUClass *cc =3D CPU_GET_CLASS(cpu); if (cc->disas_set_info) { diff --git a/disas/meson.build b/disas/meson.build index f40230c58f..832727e4b3 100644 --- a/disas/meson.build +++ b/disas/meson.build @@ -11,6 +11,7 @@ common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4= .c')) common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c')) common_ss.add(when: 'CONFIG_XTENSA_DIS', if_true: files('xtensa.c')) common_ss.add(when: capstone, if_true: [files('capstone.c'), capstone]) +common_ss.add(files('disas.c')) =20 softmmu_ss.add(files('disas-mon.c')) -specific_ss.add(files('disas.c'), capstone) +specific_ss.add(capstone) --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792398; cv=none; d=zohomail.com; s=zohoarc; b=iYxUSHSjoewt029Db7RnV4c8woCSsiaggSlq8E11XIc75Kbv0AYeRW4zFpTMrq34OzgV7OANP66yIIb6DUhoeYh3EE6LsHVEw1VG336uvrqiJxVRZDuF2aq4rGxUWBsczqe9BXyQIowkPz6WEjy1qTF2N4m81HdizutsM5F3984= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792398; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tU8RR/cxPbafbDJqUPQJIVzs1TdjNS5NeQ3A/dTuICk=; b=CdCecvopxBI4jgDo+9HZ112aEjHb7A0bZq4YohfptxTdgBYx1IcSVtqQvP/Eepgh6N2M+ocFW5+1aG0SBkd0gUveAn8FW9ERAFzp9N+Zcx8l+9D6IDLlDpfNPrr9rBhOlhKNjbWF06/ICpJ6IgJKD4rgKjHCufyfeE/66zO91E8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792398369998.7008944000734; Thu, 11 May 2023 01:06:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Ik-0006Yr-CJ; Thu, 11 May 2023 04:05:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1IZ-0006OI-Sa for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:16 -0400 Received: from mail-ed1-x52c.google.com ([2a00:1450:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IK-0000xA-99 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:15 -0400 Received: by mail-ed1-x52c.google.com with SMTP id 4fb4d7f45d1cf-50bc4ba28cbso14720769a12.0 for ; Thu, 11 May 2023 01:04:59 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.04.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:04:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792299; x=1686384299; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tU8RR/cxPbafbDJqUPQJIVzs1TdjNS5NeQ3A/dTuICk=; b=PquY7GI9KvtfwrQAaZkqZCLIkJabdgmB+W0RQarOew5opojwT2dngfTA82oAZMCY3y 4VgWuCJUKJe73Hw2WEMthuRQtPorNuh2OcrVO03ekGorSgaLvWw5P4cexJWWBKqE8Vdg XOJ2lhudWv8t5YyTVGuSFnNPHeEqmjgrPLiDIH5zpq11mV+HZltAQf01ruyEhPtCLiZp 3/X6NAwOYJ9m+MZahWdNESnd5dJB9zo6+kg7n2YbsJNQsWomr8gbKHlGJ/svFi3obmm7 X0j+8eJ4uvcflYseUDIysJGvU+zywYxgdV0Wgf7TpAYwGwv/kQyDqPdlZGvttiapyBYy tQEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792299; x=1686384299; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tU8RR/cxPbafbDJqUPQJIVzs1TdjNS5NeQ3A/dTuICk=; b=UWPCpHllzmKVWPEOlb6uv/vToP6CfqGeYs3WxzhvgBjXSrZE0errFqqt7jPq4naMuf O7XEiB4C13iuXGuAKPSnBMZkfDc58GH4noygq9A5a8GeUjOmwfsXRs82QOy3F/3stQZU LmmNyymoER/Ri5q08o+uZiKt2R+CXpHv+YoYOYU6v+g6JuTUF9+2gj9QhTqEh9mrLoTB RM1jpO4krX2Sx0MZwmV2UBnwBmd/l2qM0ZTclSfRbco+N2SIY4U+HJTLQELhSF6Jjxax /70Hvqr2JYmCV08kI7gHsDRnA2L8thwNeJQJAKjzQy9ofUXMgCOLubulJz+aFYlTQR55 Xjcw== X-Gm-Message-State: AC+VfDzYJbWYRd2zo5L+49l8y+2136WsJbOCEpMs7iYZiss2F06Zbb5g 3dP5Kcb24ZU/xM3ZiaB4A0nAXaMdl6nQ8617CxsDjQ== X-Google-Smtp-Source: ACHHUZ7J8sv6pjiMDcnAxVtrllPL99KE/DXGbunnY+uuXIM6xPAYUpP3jniYx+gvxP+achpraW9hrA== X-Received: by 2002:a17:906:4793:b0:94e:d84e:d4d0 with SMTP id cw19-20020a170906479300b0094ed84ed4d0mr19573404ejc.18.1683792298688; Thu, 11 May 2023 01:04:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Jamie Iles , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 09/53] cpu: expose qemu_cpu_list_lock for lock-guard use Date: Thu, 11 May 2023 09:04:06 +0100 Message-Id: <20230511080450.860923-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792398848100011 From: Jamie Iles Expose qemu_cpu_list_lock globally so that we can use WITH_QEMU_LOCK_GUARD and QEMU_LOCK_GUARD to simplify a few code paths now and in future. Signed-off-by: Jamie Iles Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20230427020925.51003-2-quic_jiles@quicinc.com> Signed-off-by: Richard Henderson --- include/exec/cpu-common.h | 1 + cpus-common.c | 2 +- linux-user/elfload.c | 13 +++++++------ migration/dirtyrate.c | 26 +++++++++++++------------- trace/control-target.c | 9 ++++----- 5 files changed, 26 insertions(+), 25 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 1be4a3117e..e5a55ede5f 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -32,6 +32,7 @@ extern intptr_t qemu_host_page_mask; #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_si= ze()) =20 /* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */ +extern QemuMutex qemu_cpu_list_lock; void qemu_init_cpu_list(void); void cpu_list_lock(void); void cpu_list_unlock(void); diff --git a/cpus-common.c b/cpus-common.c index a53716deb4..45c745ecf6 100644 --- a/cpus-common.c +++ b/cpus-common.c @@ -25,7 +25,7 @@ #include "qemu/lockable.h" #include "trace/trace-root.h" =20 -static QemuMutex qemu_cpu_list_lock; +QemuMutex qemu_cpu_list_lock; static QemuCond exclusive_cond; static QemuCond exclusive_resume; static QemuCond qemu_work_cond; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 80085b8a30..418ad92598 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -17,6 +17,7 @@ #include "qemu/guest-random.h" #include "qemu/units.h" #include "qemu/selfmap.h" +#include "qemu/lockable.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "target_signal.h" @@ -4238,14 +4239,14 @@ static int fill_note_info(struct elf_note_info *inf= o, info->notes_size +=3D note_size(&info->notes[i]); =20 /* read and fill status of all threads */ - cpu_list_lock(); - CPU_FOREACH(cpu) { - if (cpu =3D=3D thread_cpu) { - continue; + WITH_QEMU_LOCK_GUARD(&qemu_cpu_list_lock) { + CPU_FOREACH(cpu) { + if (cpu =3D=3D thread_cpu) { + continue; + } + fill_thread_info(info, cpu->env_ptr); } - fill_thread_info(info, cpu->env_ptr); } - cpu_list_unlock(); =20 return (0); } diff --git a/migration/dirtyrate.c b/migration/dirtyrate.c index 180ba38c7a..388337a332 100644 --- a/migration/dirtyrate.c +++ b/migration/dirtyrate.c @@ -150,25 +150,25 @@ int64_t vcpu_calculate_dirtyrate(int64_t calc_time_ms, retry: init_time_ms =3D qemu_clock_get_ms(QEMU_CLOCK_REALTIME); =20 - cpu_list_lock(); - gen_id =3D cpu_list_generation_id_get(); - records =3D vcpu_dirty_stat_alloc(stat); - vcpu_dirty_stat_collect(stat, records, true); - cpu_list_unlock(); + WITH_QEMU_LOCK_GUARD(&qemu_cpu_list_lock) { + gen_id =3D cpu_list_generation_id_get(); + records =3D vcpu_dirty_stat_alloc(stat); + vcpu_dirty_stat_collect(stat, records, true); + } =20 duration =3D dirty_stat_wait(calc_time_ms, init_time_ms); =20 global_dirty_log_sync(flag, one_shot); =20 - cpu_list_lock(); - if (gen_id !=3D cpu_list_generation_id_get()) { - g_free(records); - g_free(stat->rates); - cpu_list_unlock(); - goto retry; + WITH_QEMU_LOCK_GUARD(&qemu_cpu_list_lock) { + if (gen_id !=3D cpu_list_generation_id_get()) { + g_free(records); + g_free(stat->rates); + cpu_list_unlock(); + goto retry; + } + vcpu_dirty_stat_collect(stat, records, false); } - vcpu_dirty_stat_collect(stat, records, false); - cpu_list_unlock(); =20 for (i =3D 0; i < stat->nvcpu; i++) { dirtyrate =3D do_calculate_dirtyrate(records[i], duration); diff --git a/trace/control-target.c b/trace/control-target.c index 232c97a4a1..c0c1e2310a 100644 --- a/trace/control-target.c +++ b/trace/control-target.c @@ -8,6 +8,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/lockable.h" #include "cpu.h" #include "trace/trace-root.h" #include "trace/control.h" @@ -116,11 +117,9 @@ static bool adding_first_cpu1(void) =20 static bool adding_first_cpu(void) { - bool res; - cpu_list_lock(); - res =3D adding_first_cpu1(); - cpu_list_unlock(); - return res; + QEMU_LOCK_GUARD(&qemu_cpu_list_lock); + + return adding_first_cpu1(); } =20 void trace_init_vcpu(CPUState *vcpu) --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792987; cv=none; d=zohomail.com; s=zohoarc; b=jyUlVEWZiNUiWNYUf8gjRlHGrvh6QB9ttFDG0wxRTF2kjWjmMv91xoCpFPkyxs3lc6DdxG3uSuRyRWqGoYfTTUdo9GKTV01zVKhrutrvaiD5lmV8upvKJG/RCWhLbWaLwcqCdRJZNOK/9uTSKt+aYSc1iMTKbSgO57WgQAiTVvw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792987; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6hyQISceXBTNv4jbNz8lrHn9gEvFfSgtE9qQIEmFUjw=; b=V2/lq5j7OiazCJpQ3hN+UGp1EKACzGmYI435yXSvd/Tti1jHRxPDOVXY8VsZ5PW+ZePOQ7NL85/aO2SlDHwxrHuVKZwO/EtY0+k07IqLDyDndBLtCWIDNDgSQoB5bX0UyKocUOzHrbS8kPoWU/nOtZuRbqk7g9NdtNSP1AX35DQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792987046699.7272482803044; Thu, 11 May 2023 01:16:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Ic-0006Pd-Qh; Thu, 11 May 2023 04:05:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1IN-0006JN-HH for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:05 -0400 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IK-0000xZ-N5 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:02 -0400 Received: by mail-ed1-x52f.google.com with SMTP id 4fb4d7f45d1cf-50bc3088b7aso15607527a12.3 for ; Thu, 11 May 2023 01:05:00 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.04.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:04:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792299; x=1686384299; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6hyQISceXBTNv4jbNz8lrHn9gEvFfSgtE9qQIEmFUjw=; b=RRNAyJGaIQBp3zD24OeFGwldIYE4juIJo5o/Jq7LDYVSFNw9w2V+Xr7GnGAmB9uBIV FVHZF4FDdoRKyg6LEl7IJw71I1XqcQaY9zZm7FXK9ZHzHzqelM9y1Uxb6wpVDxJN/p2C eG6eSINA4b26RYHlNsWecA7zKBtvhk4c13IiKj7fpn9S5ATKvwFbjZ6xAb+DI5NoarAS PEBcF/MVSHmuDq9JAVniciZl8Yu1zvqWG8r4tZkLj735LmvGRmFi0w5TZlGxp+mjvy8k z5XrdHk3PmdmPYw2Z+rXv51vgMf9He3sb+DK15WTvhTuUkuTJDPZ3qVdaPat+KeKWwOv 1fvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792299; x=1686384299; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6hyQISceXBTNv4jbNz8lrHn9gEvFfSgtE9qQIEmFUjw=; b=PBQHkEfuS9+OtnRfFOf9wakbsyz3nnO7scmWd+nybHkJRNxOhzx+MxpERtkTKpldSE O2fP4GvfXTUhnqhcGYJXOE23r6OULwXKiq0b3lpIiW3CGry08C3RnV48G9Gqbkkd1/vO D0KQNGjUCN8tgFzqXrC5bLD80naPorHISgeYkvs7cXq0jveDJ+xtwKwRhx6L+/pnfUqj jNGHdgq8+DrCd/8Den4wi55rmRZqG0aOX4H1CeOnSRhlvxTwx9iXpUAclQCs/0A3A613 VNNqdAMnrLIepxiuZ/y+3X+35HKo0M6O1L2HKT+I+7QOBcbGusqoKJxDu+PanPLYlYnm eSVg== X-Gm-Message-State: AC+VfDxqVV4sQsF1nlfdrvxMfe1/omvnf6PebgOcnSgPwV2gKW31enY9 VgHnnk/g3Uu1Kl9dj3vVRTkgZ54JMAynNXCt0hCy6w== X-Google-Smtp-Source: ACHHUZ7SJ3KmkBl5lSMMpUgJMjlzQ/5B8t05kpXZpuuTGZPybDkMUAYUwINAStVAL74R6tIbe/Juog== X-Received: by 2002:aa7:c84c:0:b0:50b:fb49:39c9 with SMTP id g12-20020aa7c84c000000b0050bfb4939c9mr14983412edt.34.1683792299238; Thu, 11 May 2023 01:04:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Jamie Iles , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PULL 10/53] accel/tcg/tcg-accel-ops-rr: ensure fairness with icount Date: Thu, 11 May 2023 09:04:07 +0100 Message-Id: <20230511080450.860923-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792987406100001 From: Jamie Iles The round-robin scheduler will iterate over the CPU list with an assigned budget until the next timer expiry and may exit early because of a TB exit. This is fine under normal operation but with icount enabled and SMP it is possible for a CPU to be starved of run time and the system live-locks. For example, booting a riscv64 platform with '-icount shift=3D0,align=3Doff,sleep=3Don -smp 2' we observe a livelock once the ker= nel has timers enabled and starts performing TLB shootdowns. In this case we have CPU 0 in M-mode with interrupts disabled sending an IPI to CPU 1. As we enter the TCG loop, we assign the icount budget to next timer interrupt to CPU 0 and begin executing where the guest is sat in a busy loop exhausting all of the budget before we try to execute CPU 1 which is the target of the IPI but CPU 1 is left with no budget with which to execute and the process repeats. We try here to add some fairness by splitting the budget across all of the CPUs on the thread fairly before entering each one. The CPU count is cached on CPU list generation ID to avoid iterating the list on each loop iteration. With this change it is possible to boot an SMP rv64 guest with icount enabled and no hangs. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Peter Maydell Signed-off-by: Jamie Iles Reviewed-by: Richard Henderson Message-Id: <20230427020925.51003-3-quic_jiles@quicinc.com> Signed-off-by: Richard Henderson --- accel/tcg/tcg-accel-ops-icount.h | 3 ++- accel/tcg/tcg-accel-ops-icount.c | 21 ++++++++++++++---- accel/tcg/tcg-accel-ops-rr.c | 37 +++++++++++++++++++++++++++++++- replay/replay.c | 3 +-- 4 files changed, 56 insertions(+), 8 deletions(-) diff --git a/accel/tcg/tcg-accel-ops-icount.h b/accel/tcg/tcg-accel-ops-ico= unt.h index 1b6fd9c607..16a301b6dc 100644 --- a/accel/tcg/tcg-accel-ops-icount.h +++ b/accel/tcg/tcg-accel-ops-icount.h @@ -11,7 +11,8 @@ #define TCG_ACCEL_OPS_ICOUNT_H =20 void icount_handle_deadline(void); -void icount_prepare_for_run(CPUState *cpu); +void icount_prepare_for_run(CPUState *cpu, int64_t cpu_budget); +int64_t icount_percpu_budget(int cpu_count); void icount_process_data(CPUState *cpu); =20 void icount_handle_interrupt(CPUState *cpu, int mask); diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-ico= unt.c index 84cc7421be..3d2cfbbc97 100644 --- a/accel/tcg/tcg-accel-ops-icount.c +++ b/accel/tcg/tcg-accel-ops-icount.c @@ -89,7 +89,20 @@ void icount_handle_deadline(void) } } =20 -void icount_prepare_for_run(CPUState *cpu) +/* Distribute the budget evenly across all CPUs */ +int64_t icount_percpu_budget(int cpu_count) +{ + int64_t limit =3D icount_get_limit(); + int64_t timeslice =3D limit / cpu_count; + + if (timeslice =3D=3D 0) { + timeslice =3D limit; + } + + return timeslice; +} + +void icount_prepare_for_run(CPUState *cpu, int64_t cpu_budget) { int insns_left; =20 @@ -101,13 +114,13 @@ void icount_prepare_for_run(CPUState *cpu) g_assert(cpu_neg(cpu)->icount_decr.u16.low =3D=3D 0); g_assert(cpu->icount_extra =3D=3D 0); =20 - cpu->icount_budget =3D icount_get_limit(); + replay_mutex_lock(); + + cpu->icount_budget =3D MIN(icount_get_limit(), cpu_budget); insns_left =3D MIN(0xffff, cpu->icount_budget); cpu_neg(cpu)->icount_decr.u16.low =3D insns_left; cpu->icount_extra =3D cpu->icount_budget - insns_left; =20 - replay_mutex_lock(); - if (cpu->icount_budget =3D=3D 0) { /* * We're called without the iothread lock, so must take it while diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index 290833a37f..5788efa5ff 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -24,6 +24,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/lockable.h" #include "sysemu/tcg.h" #include "sysemu/replay.h" #include "sysemu/cpu-timers.h" @@ -139,6 +140,33 @@ static void rr_force_rcu(Notifier *notify, void *data) rr_kick_next_cpu(); } =20 +/* + * Calculate the number of CPUs that we will process in a single iteration= of + * the main CPU thread loop so that we can fairly distribute the instructi= on + * count across CPUs. + * + * The CPU count is cached based on the CPU list generation ID to avoid + * iterating the list every time. + */ +static int rr_cpu_count(void) +{ + static unsigned int last_gen_id =3D ~0; + static int cpu_count; + CPUState *cpu; + + QEMU_LOCK_GUARD(&qemu_cpu_list_lock); + + if (cpu_list_generation_id_get() !=3D last_gen_id) { + cpu_count =3D 0; + CPU_FOREACH(cpu) { + ++cpu_count; + } + last_gen_id =3D cpu_list_generation_id_get(); + } + + return cpu_count; +} + /* * In the single-threaded case each vCPU is simulated in turn. If * there is more than a single vCPU we create a simple timer to kick @@ -185,11 +213,16 @@ static void *rr_cpu_thread_fn(void *arg) cpu->exit_request =3D 1; =20 while (1) { + /* Only used for icount_enabled() */ + int64_t cpu_budget =3D 0; + qemu_mutex_unlock_iothread(); replay_mutex_lock(); qemu_mutex_lock_iothread(); =20 if (icount_enabled()) { + int cpu_count =3D rr_cpu_count(); + /* Account partial waits to QEMU_CLOCK_VIRTUAL. */ icount_account_warp_timer(); /* @@ -197,6 +230,8 @@ static void *rr_cpu_thread_fn(void *arg) * waking up the I/O thread and waiting for completion. */ icount_handle_deadline(); + + cpu_budget =3D icount_percpu_budget(cpu_count); } =20 replay_mutex_unlock(); @@ -218,7 +253,7 @@ static void *rr_cpu_thread_fn(void *arg) =20 qemu_mutex_unlock_iothread(); if (icount_enabled()) { - icount_prepare_for_run(cpu); + icount_prepare_for_run(cpu, cpu_budget); } r =3D tcg_cpus_exec(cpu); if (icount_enabled()) { diff --git a/replay/replay.c b/replay/replay.c index c39156c522..0f7d766efe 100644 --- a/replay/replay.c +++ b/replay/replay.c @@ -74,7 +74,7 @@ uint64_t replay_get_current_icount(void) int replay_get_instructions(void) { int res =3D 0; - replay_mutex_lock(); + g_assert(replay_mutex_locked()); if (replay_next_event_is(EVENT_INSTRUCTION)) { res =3D replay_state.instruction_count; if (replay_break_icount !=3D -1LL) { @@ -85,7 +85,6 @@ int replay_get_instructions(void) } } } - replay_mutex_unlock(); return res; } =20 --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792745; cv=none; d=zohomail.com; s=zohoarc; b=L5zhgs/FoPteHAg3UeNLVrq5oxADi2jgoNn0D0lkKvnjb8jaqVx8I6d4mokaZJUxhJZcikZHBT41BpE4BarG1uFlmHwBzsmiNoS51gBMeyL/BrmMXmuPtbWaVcQmnjg21JgVbIwcvUcQCyTUNIjfwJzx23kexdKxPg3cvygA8IM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792745; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UZG5AIZYUQmNYurPolHdCLcsLkjWJ1LdiIgbXm/REew=; b=JaSDYzfljycTypKKWh/jRki59LntqvquPHQj//Nns/kaZitpW5Ntgu2r3S50pg0r4cQ1unkhEbm8g/f9n1Fur/2YQEum2iSJw8t45ydRMtt/y6z/Us0FOF6Yx/YxspQ5rx+yilsr66gD/xcuYM/LmOHxOv8IHdX1hVemVjDJwKA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792745162229.57725963807673; Thu, 11 May 2023 01:12:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1IY-0006NN-IA; Thu, 11 May 2023 04:05:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1IO-0006JU-IM for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:05 -0400 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IL-0000xe-Jp for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:04 -0400 Received: by mail-ed1-x52f.google.com with SMTP id 4fb4d7f45d1cf-50bc4bc2880so12843451a12.2 for ; Thu, 11 May 2023 01:05:01 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.04.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:04:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792300; x=1686384300; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UZG5AIZYUQmNYurPolHdCLcsLkjWJ1LdiIgbXm/REew=; b=Cla3Y1jmbL5bCkS+4CZVpqLyGe4KtM0zBYJwpoOmkQRz32JDd8gKbwGBZe8dTl7MKx n2h1Ast2HTbkcatBxwSSpKHog3Mhv2lkOkm9ptTQdArv8n3z+be720UtpFEsB9MdiQGP AVu8AYoW0LRK98kECFG8uYy0g94bCqItjEVL75zqf3m0g+UXbByJd5xV+foMP9yu8qyp GLTZ8mjqWl+RdsJh3/1cch/q32/JpePoJDWEpYXTz4mvTJT/t+e/wTfP6DQ90b10tFzP 6PTFmWwZbFxnj2R8h5gRg8kgviN0r6wZUwdhV0NRq4SIoNBBGCaN4HW/zitHqvMtGOZA 4DAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792300; x=1686384300; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UZG5AIZYUQmNYurPolHdCLcsLkjWJ1LdiIgbXm/REew=; b=glyuJERVi7bmoouOlQSWieNyF3abQx3Gtn/Adq+Zmv82qsxCzgCFRL2TvTx75P6FI7 Th7X46GUcGd9Kam64f2SNpQVx+N4pegrs5tdV3Su0liTWRlPYSeHKpfaf3qx3Q95Ncex 84kV2qVGpRYIbC8wurj34YhvcUE1TVLpTaiC3k5jbu3kpdHPkCNfKo8G61nWcj7t46Gy 3HUbSnndJEuGR7pJHkkrj35PKMnRBWlVMnpJxNK2Ma0W5dBMfUW+gmyIrDQaNg5yFEVh UVkv/z7Migk+Zys0mu3rpUwOG0jd90doQSWPNb8oMLjtTBAwMhG/7qRX3/VdQufB+hIi 3t0g== X-Gm-Message-State: AC+VfDx/IZhJTGrHx6JjpY89P9NAolqSDXvHtXjIqsZoH3ma4k88o3ao ccdtxGzLz49fU1auBkihRu8OGUqeOOfYHY89I244cg== X-Google-Smtp-Source: ACHHUZ7cdXac1FeWv+Ce12jSVrye/kJ1mBfHR7mYIHMBqpVYvWNfjmpxM1T9jtMKx99G7A9ce+2+9Q== X-Received: by 2002:a50:ed0b:0:b0:50b:cae1:d4b2 with SMTP id j11-20020a50ed0b000000b0050bcae1d4b2mr15205799eds.38.1683792299920; Thu, 11 May 2023 01:04:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 11/53] tcg/i386: Introduce prepare_host_addr Date: Thu, 11 May 2023 09:04:08 +0100 Message-Id: <20230511080450.860923-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792746451100001 Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 346 ++++++++++++++++---------------------- 1 file changed, 145 insertions(+), 201 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index aae698121a..5d702b69ac 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1802,135 +1802,6 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_B= SWAP) + 1] =3D { [MO_BEUQ] =3D helper_be_stq_mmu, }; =20 -/* Perform the TLB load and compare. - - Inputs: - ADDRLO and ADDRHI contain the low and high part of the address. - - MEM_INDEX and S_BITS are the memory context and log2 size of the load. - - WHICH is the offset into the CPUTLBEntry structure of the slot to read. - This should be offsetof addr_read or addr_write. - - Outputs: - LABEL_PTRS is filled with 1 (32-bit addresses) or 2 (64-bit addresses) - positions of the displacements of forward jumps to the TLB miss case. - - Second argument register is loaded with the low part of the address. - In the TLB hit case, it has been adjusted as indicated by the TLB - and so is a host address. In the TLB miss case, it continues to - hold a guest address. - - First argument register is clobbered. */ - -static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg a= ddrhi, - int mem_index, MemOp opc, - tcg_insn_unit **label_ptr, int which) -{ - TCGType ttype =3D TCG_TYPE_I32; - TCGType tlbtype =3D TCG_TYPE_I32; - int trexw =3D 0, hrexw =3D 0, tlbrexw =3D 0; - unsigned a_bits =3D get_alignment_bits(opc); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_mask =3D (1 << a_bits) - 1; - unsigned s_mask =3D (1 << s_bits) - 1; - target_ulong tlb_mask; - - if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (TARGET_LONG_BITS =3D=3D 64) { - ttype =3D TCG_TYPE_I64; - trexw =3D P_REXW; - } - if (TCG_TYPE_PTR =3D=3D TCG_TYPE_I64) { - hrexw =3D P_REXW; - if (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32) { - tlbtype =3D TCG_TYPE_I64; - tlbrexw =3D P_REXW; - } - } - } - - tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo); - tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - - tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0, - TLB_MASK_TABLE_OFS(mem_index) + - offsetof(CPUTLBDescFast, mask)); - - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0, - TLB_MASK_TABLE_OFS(mem_index) + - offsetof(CPUTLBDescFast, table)); - - /* If the required alignment is at least as large as the access, simply - copy the address and mask. For lesser alignments, check that we do= n't - cross pages for the complete access. */ - if (a_bits >=3D s_bits) { - tcg_out_mov(s, ttype, TCG_REG_L1, addrlo); - } else { - tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1, - addrlo, s_mask - a_mask); - } - tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; - tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0); - - /* cmp 0(TCG_REG_L0), TCG_REG_L1 */ - tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, - TCG_REG_L1, TCG_REG_L0, which); - - /* Prepare for both the fast path add of the tlb addend, and the slow - path function argument setup. */ - tcg_out_mov(s, ttype, TCG_REG_L1, addrlo); - - /* jne slow_path */ - tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); - label_ptr[0] =3D s->code_ptr; - s->code_ptr +=3D 4; - - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - /* cmp 4(TCG_REG_L0), addrhi */ - tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, TCG_REG_L0, which + = 4); - - /* jne slow_path */ - tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); - label_ptr[1] =3D s->code_ptr; - s->code_ptr +=3D 4; - } - - /* TLB Hit. */ - - /* add addend(TCG_REG_L0), TCG_REG_L1 */ - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L1, TCG_REG_L0, - offsetof(CPUTLBEntry, addend)); -} - -/* - * Record the context of a call to the out of line helper code for the slo= w path - * for a load or store, so that we can later generate the correct helper c= ode - */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, - TCGType type, MemOpIdx oi, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addrhi, - tcg_insn_unit *raddr, - tcg_insn_unit **label_ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D type; - label->datalo_reg =3D datalo; - label->datahi_reg =3D datahi; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr[0]; - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - label->label_ptr[1] =3D label_ptr[1]; - } -} - /* * Generate code for the slow path for a load at the end of block */ @@ -2061,27 +1932,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) return true; } #else - -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrl= o, - TCGReg addrhi, unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *label; - - tcg_out_testi(s, addrlo, a_mask); - /* jne slow_path */ - tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); - - label =3D new_ldst_label(s); - label->is_ld =3D is_ld; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; - label->raddr =3D tcg_splitwx_to_rx(s->code_ptr + 4); - label->label_ptr[0] =3D s->code_ptr; - - s->code_ptr +=3D 4; -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { /* resolve label address */ @@ -2159,6 +2009,135 @@ static inline int setup_guest_base_seg(void) #endif /* setup_guest_base_seg */ #endif /* SOFTMMU */ =20 +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, bool is_ld) +{ + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned a_mask =3D (1 << a_bits) - 1; + +#ifdef CONFIG_SOFTMMU + int cmp_ofs =3D is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write); + TCGType ttype =3D TCG_TYPE_I32; + TCGType tlbtype =3D TCG_TYPE_I32; + int trexw =3D 0, hrexw =3D 0, tlbrexw =3D 0; + unsigned mem_index =3D get_mmuidx(oi); + unsigned s_bits =3D opc & MO_SIZE; + unsigned s_mask =3D (1 << s_bits) - 1; + target_ulong tlb_mask; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + if (TCG_TARGET_REG_BITS =3D=3D 64) { + if (TARGET_LONG_BITS =3D=3D 64) { + ttype =3D TCG_TYPE_I64; + trexw =3D P_REXW; + } + if (TCG_TYPE_PTR =3D=3D TCG_TYPE_I64) { + hrexw =3D P_REXW; + if (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32) { + tlbtype =3D TCG_TYPE_I64; + tlbrexw =3D P_REXW; + } + } + } + + tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo); + tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + + tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0, + TLB_MASK_TABLE_OFS(mem_index) + + offsetof(CPUTLBDescFast, mask)); + + tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0, + TLB_MASK_TABLE_OFS(mem_index) + + offsetof(CPUTLBDescFast, table)); + + /* + * If the required alignment is at least as large as the access, simply + * copy the address and mask. For lesser alignments, check that we do= n't + * cross pages for the complete access. + */ + if (a_bits >=3D s_bits) { + tcg_out_mov(s, ttype, TCG_REG_L1, addrlo); + } else { + tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1, + addrlo, s_mask - a_mask); + } + tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; + tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0); + + /* cmp 0(TCG_REG_L0), TCG_REG_L1 */ + tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, + TCG_REG_L1, TCG_REG_L0, cmp_ofs); + + /* + * Prepare for both the fast path add of the tlb addend, and the slow + * path function argument setup. + */ + *h =3D (HostAddress) { + .base =3D TCG_REG_L1, + .index =3D -1 + }; + tcg_out_mov(s, ttype, h->base, addrlo); + + /* jne slow_path */ + tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); + ldst->label_ptr[0] =3D s->code_ptr; + s->code_ptr +=3D 4; + + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + /* cmp 4(TCG_REG_L0), addrhi */ + tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, TCG_REG_L0, cmp_ofs = + 4); + + /* jne slow_path */ + tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); + ldst->label_ptr[1] =3D s->code_ptr; + s->code_ptr +=3D 4; + } + + /* TLB Hit. */ + + /* add addend(TCG_REG_L0), TCG_REG_L1 */ + tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, h->base, TCG_REG_L0, + offsetof(CPUTLBEntry, addend)); +#else + if (a_bits) { + ldst =3D new_ldst_label(s); + + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + tcg_out_testi(s, addrlo, a_mask); + /* jne slow_path */ + tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); + ldst->label_ptr[0] =3D s->code_ptr; + s->code_ptr +=3D 4; + } + + *h =3D x86_guest_base; + h->base =3D addrlo; +#endif + + return ldst; +} + static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, HostAddress h, TCGType type, MemOp memo= p) { @@ -2258,35 +2237,18 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[2]; + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, true); + tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, get_memop(oi)); =20 - tcg_out_tlb_load(s, addrlo, addrhi, get_mmuidx(oi), opc, - label_ptr, offsetof(CPUTLBEntry, addr_read)); - - /* TLB Hit. */ - h.base =3D TCG_REG_L1; - h.index =3D -1; - h.ofs =3D 0; - h.seg =3D 0; - tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, opc); - - /* Record the current context of a load into ldst label */ - add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - - h =3D x86_guest_base; - h.base =3D addrlo; - tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, opc); -#endif } =20 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, @@ -2345,36 +2307,18 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[2]; + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, false); + tcg_out_qemu_st_direct(s, datalo, datahi, h, get_memop(oi)); =20 - tcg_out_tlb_load(s, addrlo, addrhi, get_mmuidx(oi), opc, - label_ptr, offsetof(CPUTLBEntry, addr_write)); - - /* TLB Hit. */ - h.base =3D TCG_REG_L1; - h.index =3D -1; - h.ofs =3D 0; - h.seg =3D 0; - tcg_out_qemu_st_direct(s, datalo, datahi, h, opc); - - /* Record the current context of a store into ldst label */ - add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - - h =3D x86_guest_base; - h.base =3D addrlo; - - tcg_out_qemu_st_direct(s, datalo, datahi, h, opc); -#endif } =20 static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683793041; cv=none; d=zohomail.com; s=zohoarc; b=GI7wM4Q2/NOhJmYKp1eX1MBJPzLoxx9IzZFoF/RNL8cbJguo+9tueOJyrFDulyceZtPkIFGt3cRiMRZSD6h2dvzHetzobptlZmqK7Zn6CL3UYruyK5u9XPH02m+w++BVQByFLgyor3m0mmG3/Jw8jQbEO5lAj2yS21SMAvC7f4M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683793041; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=f+t7z0FUWlRAicpheOk0qlu8uMDwmd02otcOLGaJHHo=; b=iZgNbniwe8pfZbrKg15GiSHhxlX3LtIrB7eoosdyNf5+IjChhnflPZwDws1fX4Ap3nPplsDybUtMGIOj1svxfRKhcqsLXS7cQ7ZkJTxUTRWIZhn9Lw83MeM+O0gAYoGqtcHVPLRl8eINI07SZ8sOU/jO8PVbU5W9LMjoex8cJH0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683793041222678.3221893758549; Thu, 11 May 2023 01:17:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Id-0006QK-Fk; Thu, 11 May 2023 04:05:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1IO-0006JV-Vs for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:05 -0400 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IN-0000xo-7j for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:04 -0400 Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-50b383222f7so12306458a12.3 for ; Thu, 11 May 2023 01:05:02 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792300; x=1686384300; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f+t7z0FUWlRAicpheOk0qlu8uMDwmd02otcOLGaJHHo=; b=jeqC4jRk0QcrBRdjHPZkwrbUJWqkXxwkBfrjklNpfMmAdfFFYBU2JqUPfGvHeSMTQI BxLAhGtTyCNsTqlkqBrk/CDv9kBFzbCxqjmOg5ezpm559ytSPj8a0Uh515KihZDfHwIT p+dKAzGyIX3wWj1eBcdRQH0YxTbx5x5JY/2r77lbP8j2bRBJwKiuL7DIbnFfJecxwxMs DNVRlQcPmg7NU9T8QoOsKBT/9OjawYEKB/aO7SAk9+MBvLVE4uBfWV+8veeuCmQtrGNl AtNK6M6I5Up/e220Wk8bP2szB1+EWJSBQcHSTpj74nUi7tGE/6WXK9iJhBBEyj6d0Jfc nJeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792300; x=1686384300; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f+t7z0FUWlRAicpheOk0qlu8uMDwmd02otcOLGaJHHo=; b=Gjb6xE4Wpd7L/NUGKwIpjCz1YVQaE9vEXc2xsQCAPTTsfXL1bigpLK0R59LTki9NQb /EyZXjF1DcfqIscqZC6PA3aUp1NEDqOKB+mrARKCPJTEWKi3UM0nhLHPXPkeO9bLBvIc NX3I/Gz+Y7PRiL84T1CXnaRu+4VQ3BTE7S6yxFpmktBB779G2rpYCzRkJ/Hmuhh5WYiW tj9spCghTHuPdIaT02ZHAqloiRcxXcZllhB5da2TA9ajv8DmokqDSHBXgjsaGriYvSmz XqK8BBaIzi4uO0LA4ewiQbtqHVzhCFrPehRM9GDsInDxBiq3VkVPe8rkRPcxeyAb10y9 Pzzg== X-Gm-Message-State: AC+VfDyrzcivnmGQmyHhsJi741T7SIILvH3OO6KiTh39ZjwuQbeMzv2E 9F7Ivy4CuHikh/xnYazHm26v8qD3tlxzfRhF/kjVRQ== X-Google-Smtp-Source: ACHHUZ7faasROsRwZT461AzdNbHj/G51kZOKts4GRprjnZ+ei/W2hd++3HovVW8uKCplU2iwMFlECQ== X-Received: by 2002:aa7:ca46:0:b0:50d:8991:d1b9 with SMTP id j6-20020aa7ca46000000b0050d8991d1b9mr15099009edt.8.1683792300489; Thu, 11 May 2023 01:05:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 12/53] tcg/i386: Use indexed addressing for softmmu fast path Date: Thu, 11 May 2023 09:04:09 +0100 Message-Id: <20230511080450.860923-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683793042398100003 Since tcg_out_{ld,st}_helper_args, the slow path no longer requires the address argument to be set up by the tlb load sequence. Use a plain load for the addend and indexed addressing with the original input address register. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 5d702b69ac..18b0e7997d 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1837,7 +1837,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) tcg_out_sti(s, TCG_TYPE_PTR, (uintptr_t)l->raddr, TCG_REG_ESP, ofs= ); } else { tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); - /* The second argument is already loaded with addrlo. */ + tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], + l->addrlo_reg); tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], oi); tcg_out_movi(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[3], (uintptr_t)l->raddr); @@ -1910,7 +1911,8 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, ofs); } else { tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); - /* The second argument is already loaded with addrlo. */ + tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], + l->addrlo_reg); tcg_out_mov(s, (s_bits =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), tcg_target_call_iarg_regs[2], l->datalo_reg); tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], oi); @@ -2085,16 +2087,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContex= t *s, HostAddress *h, tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, TCG_REG_L1, TCG_REG_L0, cmp_ofs); =20 - /* - * Prepare for both the fast path add of the tlb addend, and the slow - * path function argument setup. - */ - *h =3D (HostAddress) { - .base =3D TCG_REG_L1, - .index =3D -1 - }; - tcg_out_mov(s, ttype, h->base, addrlo); - /* jne slow_path */ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); ldst->label_ptr[0] =3D s->code_ptr; @@ -2111,10 +2103,13 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, } =20 /* TLB Hit. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0, + offsetof(CPUTLBEntry, addend)); =20 - /* add addend(TCG_REG_L0), TCG_REG_L1 */ - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, h->base, TCG_REG_L0, - offsetof(CPUTLBEntry, addend)); + *h =3D (HostAddress) { + .base =3D addrlo, + .index =3D TCG_REG_L0, + }; #else if (a_bits) { ldst =3D new_ldst_label(s); --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792395; cv=none; d=zohomail.com; s=zohoarc; b=HLYmmgnJkUDVOy/bTmX2xrTT/ZSQM9F/kTjbOYcqjsAFcZ7yS1bXxqUXIRIU6URDy7DnzdNNfEsP/marJzT6w3mXOzcXEsQsHCCgymzHCwtFaA9gBFeYkIeK9UGjkuwYhd4Ydg/wHZux/m5aNlqmAKvGKYKoXYhxqusazA96gHk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792395; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DpoVkMirxHpSMfRoJifq8tc63ZR881tHQ0V7ao3Bhh8=; b=gx4i8b3Pn0CkQTSsk4snLuT4Ch6KtTTl83rlo04IJnickQH8AvIj+YioRTOx6zWYR+UlhAKQ6ywrLZdlvvaoydIuqULeJpJ7qerThSsQsbHcgmSTzFcGq5hHhGnnLZ7hgZDBOeb7EiB2ZCZtsNfZYChf/O8fXnNXf7nccDKodMw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792395450958.7058035976944; Thu, 11 May 2023 01:06:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Ia-0006ON-CE; Thu, 11 May 2023 04:05:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1IP-0006K7-EY for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:07 -0400 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IN-0000yE-4P for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:05 -0400 Received: by mail-ed1-x52b.google.com with SMTP id 4fb4d7f45d1cf-50b37f3e664so14602572a12.1 for ; Thu, 11 May 2023 01:05:02 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792301; x=1686384301; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DpoVkMirxHpSMfRoJifq8tc63ZR881tHQ0V7ao3Bhh8=; b=z7Y4APJu0ZeTTnX4F5K0oncMnBGcwn6oMecOXKP5v1B17mXgHS80znV9QgTeAj24PO wp0SAEGbzx6FKHhaQLvoI/7dCZK8yIEdNGULe1Ny2+CFVNgEJS/dn/VkrCtUYvwN9Xnw 1c2er67bzw/qYE8ozgmJVLPQ8j9UvjLLB856Nah6QRrn3JlPhL8mnJhIYDVrevosGATB L0imb3wx1okv5nhpqBF3bvI4RY0DQM4+9xU5W9MHVfnDFacJZWeY9WV8DHPHYPXTsky0 +ywhWuNFOp6bMkcxRcqmlbRfYTNm9CXqw5ilAYWkA6b9/NhbGQLWdnOcUq1JQVbr/hpj Uhmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792301; x=1686384301; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DpoVkMirxHpSMfRoJifq8tc63ZR881tHQ0V7ao3Bhh8=; b=iagco9L6f2UPWo7+SvYSLhO7ckh0g3Q7TP2IWMLC31kRMaZ+4ptSCxbq3lcK88PucJ JMLVIiQFN3aK3XC9wQ6y/00ZYvtiakNnFe7ddbP6raNmZowT8iZbh06tuvsCZDfrkV6v XaTPvDBknIapdgF9M+vyNPSDYNkSXPhEz68NCBZxLXFSGWWSOelw2o92vVmKM6pyWy5X Y5G1Yqgq+hHIEvgWwtXBHYL5MCXIeQe9i1sVR4HsLI2FXonbIQnmbYfE/8dFb6auzSeI W7raGvdsiW22wlWTtdCA6/PeVK37PeXQftneBOO5sUREjMqrP08ATM1QqZeHeoxXtW8e OMIQ== X-Gm-Message-State: AC+VfDxR+wABzwEdmAXnD3sZoWSz8/oYKsGR1ZXDKbmyC9NvEN6zF/cr mVaWVlj9vJZsOrDmFFJGvlVefGKoVpWU2y33jbhuAg== X-Google-Smtp-Source: ACHHUZ59YlFSYG3I1oC8o2N0KnqNfmq9AB6Hwc+mVt5aTdzHqlDCgU1Pc7bxeD1uXUrTlCJekQK3qQ== X-Received: by 2002:aa7:d59a:0:b0:50b:5dbe:e0f6 with SMTP id r26-20020aa7d59a000000b0050b5dbee0f6mr16896633edq.25.1683792301074; Thu, 11 May 2023 01:05:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 13/53] tcg/aarch64: Introduce prepare_host_addr Date: Thu, 11 May 2023 09:04:10 +0100 Message-Id: <20230511080450.860923-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792396715100005 Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 313 +++++++++++++++-------------------- 1 file changed, 133 insertions(+), 180 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index d8d464e4a0..202b90c001 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1667,113 +1667,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) tcg_out_goto(s, lb->raddr); return true; } - -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, - TCGType ext, TCGReg data_reg, TCGReg addr_= reg, - tcg_insn_unit *raddr, tcg_insn_unit *label= _ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D ext; - label->datalo_reg =3D data_reg; - label->addrlo_reg =3D addr_reg; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr; -} - -/* We expect to use a 7-bit scaled negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512); - -/* These offsets are built into the LDP below. */ -QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); -QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 8); - -/* Load and compare a TLB entry, emitting the conditional jump to the - slow path for the failure case, which will be patched later when finali= zing - the slow path. Generated code returns the host addend in X1, - clobbers X0,X2,X3,TMP. */ -static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc, - tcg_insn_unit **label_ptr, int mem_index, - bool is_read) -{ - unsigned a_bits =3D get_alignment_bits(opc); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_mask =3D (1u << a_bits) - 1; - unsigned s_mask =3D (1u << s_bits) - 1; - TCGReg x3; - TCGType mask_type; - uint64_t compare_mask; - - mask_type =3D (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32 - ? TCG_TYPE_I64 : TCG_TYPE_I32); - - /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */ - tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0, - TLB_MASK_TABLE_OFS(mem_index), 1, 0); - - /* Extract the TLB index from the address into X0. */ - tcg_out_insn(s, 3502S, AND_LSR, mask_type =3D=3D TCG_TYPE_I64, - TCG_REG_X0, TCG_REG_X0, addr_reg, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - - /* Add the tlb_table pointer, creating the CPUTLBEntry address into X1= . */ - tcg_out_insn(s, 3502, ADD, 1, TCG_REG_X1, TCG_REG_X1, TCG_REG_X0); - - /* Load the tlb comparator into X0, and the fast path addend into X1. = */ - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_X0, TCG_REG_X1, is_read - ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, TCG_REG_X1, - offsetof(CPUTLBEntry, addend)); - - /* For aligned accesses, we check the first byte and include the align= ment - bits within the address. For unaligned access, we check that we do= n't - cross pages using the address of the last byte of the access. */ - if (a_bits >=3D s_bits) { - x3 =3D addr_reg; - } else { - tcg_out_insn(s, 3401, ADDI, TARGET_LONG_BITS =3D=3D 64, - TCG_REG_X3, addr_reg, s_mask - a_mask); - x3 =3D TCG_REG_X3; - } - compare_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; - - /* Store the page mask part of the address into X3. */ - tcg_out_logicali(s, I3404_ANDI, TARGET_LONG_BITS =3D=3D 64, - TCG_REG_X3, x3, compare_mask); - - /* Perform the address comparison. */ - tcg_out_cmp(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X0, TCG_REG_X3, 0); - - /* If not equal, we jump to the slow path. */ - *label_ptr =3D s->code_ptr; - tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); -} - #else -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_= reg, - unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->addrlo_reg =3D addr_reg; - - /* tst addr, #mask */ - tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask); - - label->label_ptr[0] =3D s->code_ptr; - - /* b.ne slow_path */ - tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); - - label->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { if (!reloc_pc19(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -1801,6 +1695,125 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) } #endif /* CONFIG_SOFTMMU */ =20 +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addr_reg, MemOpIdx oi, + bool is_ld) +{ + TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned a_mask =3D (1u << a_bits) - 1; + +#ifdef CONFIG_SOFTMMU + unsigned s_bits =3D opc & MO_SIZE; + unsigned s_mask =3D (1u << s_bits) - 1; + unsigned mem_index =3D get_mmuidx(oi); + TCGReg x3; + TCGType mask_type; + uint64_t compare_mask; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + mask_type =3D (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32 + ? TCG_TYPE_I64 : TCG_TYPE_I32); + + /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */ + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512); + QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); + QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 8); + tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0, + TLB_MASK_TABLE_OFS(mem_index), 1, 0); + + /* Extract the TLB index from the address into X0. */ + tcg_out_insn(s, 3502S, AND_LSR, mask_type =3D=3D TCG_TYPE_I64, + TCG_REG_X0, TCG_REG_X0, addr_reg, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + + /* Add the tlb_table pointer, creating the CPUTLBEntry address into X1= . */ + tcg_out_insn(s, 3502, ADD, 1, TCG_REG_X1, TCG_REG_X1, TCG_REG_X0); + + /* Load the tlb comparator into X0, and the fast path addend into X1. = */ + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_X0, TCG_REG_X1, + is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, TCG_REG_X1, + offsetof(CPUTLBEntry, addend)); + + /* + * For aligned accesses, we check the first byte and include the align= ment + * bits within the address. For unaligned access, we check that we do= n't + * cross pages using the address of the last byte of the access. + */ + if (a_bits >=3D s_bits) { + x3 =3D addr_reg; + } else { + tcg_out_insn(s, 3401, ADDI, TARGET_LONG_BITS =3D=3D 64, + TCG_REG_X3, addr_reg, s_mask - a_mask); + x3 =3D TCG_REG_X3; + } + compare_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; + + /* Store the page mask part of the address into X3. */ + tcg_out_logicali(s, I3404_ANDI, TARGET_LONG_BITS =3D=3D 64, + TCG_REG_X3, x3, compare_mask); + + /* Perform the address comparison. */ + tcg_out_cmp(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X0, TCG_REG_X3, 0); + + /* If not equal, we jump to the slow path. */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); + + *h =3D (HostAddress){ + .base =3D TCG_REG_X1, + .index =3D addr_reg, + .index_ext =3D addr_type + }; +#else + if (a_mask) { + ldst =3D new_ldst_label(s); + + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + /* tst addr, #mask */ + tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask); + + /* b.ne slow_path */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); + } + + if (USE_GUEST_BASE) { + *h =3D (HostAddress){ + .base =3D TCG_REG_GUEST_BASE, + .index =3D addr_reg, + .index_ext =3D addr_type + }; + } else { + *h =3D (HostAddress){ + .base =3D addr_reg, + .index =3D TCG_REG_XZR, + .index_ext =3D TCG_TYPE_I64 + }; + } +#endif + + return ldst; +} + static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext, TCGReg data_r, HostAddress h) { @@ -1857,93 +1870,33 @@ static void tcg_out_qemu_st_direct(TCGContext *s, M= emOp memop, static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp memop =3D get_memop(oi); - TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; + TCGLabelQemuLdst *ldst; HostAddress h; =20 - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, true); + tcg_out_qemu_ld_direct(s, get_memop(oi), data_type, data_reg, h); =20 -#ifdef CONFIG_SOFTMMU - tcg_insn_unit *label_ptr; - - tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 1); - - h =3D (HostAddress){ - .base =3D TCG_REG_X1, - .index =3D addr_reg, - .index_ext =3D addr_type - }; - tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, h); - - add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ - unsigned a_bits =3D get_alignment_bits(memop); - if (a_bits) { - tcg_out_test_alignment(s, true, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - if (USE_GUEST_BASE) { - h =3D (HostAddress){ - .base =3D TCG_REG_GUEST_BASE, - .index =3D addr_reg, - .index_ext =3D addr_type - }; - } else { - h =3D (HostAddress){ - .base =3D addr_reg, - .index =3D TCG_REG_XZR, - .index_ext =3D TCG_TYPE_I64 - }; - } - tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, h); -#endif /* CONFIG_SOFTMMU */ } =20 static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp memop =3D get_memop(oi); - TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; + TCGLabelQemuLdst *ldst; HostAddress h; =20 - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, false); + tcg_out_qemu_st_direct(s, get_memop(oi), data_reg, h); =20 -#ifdef CONFIG_SOFTMMU - tcg_insn_unit *label_ptr; - - tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 0); - - h =3D (HostAddress){ - .base =3D TCG_REG_X1, - .index =3D addr_reg, - .index_ext =3D addr_type - }; - tcg_out_qemu_st_direct(s, memop, data_reg, h); - - add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ - unsigned a_bits =3D get_alignment_bits(memop); - if (a_bits) { - tcg_out_test_alignment(s, false, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - if (USE_GUEST_BASE) { - h =3D (HostAddress){ - .base =3D TCG_REG_GUEST_BASE, - .index =3D addr_reg, - .index_ext =3D addr_type - }; - } else { - h =3D (HostAddress){ - .base =3D addr_reg, - .index =3D TCG_REG_XZR, - .index_ext =3D TCG_TYPE_I64 - }; - } - tcg_out_qemu_st_direct(s, memop, data_reg, h); -#endif /* CONFIG_SOFTMMU */ } =20 static const tcg_insn_unit *tb_ret_addr; --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683793047; cv=none; d=zohomail.com; s=zohoarc; b=bo0P+d5uTvcfmGIA0hWc/U1xIhZiub79naIetvtLn0xwRIt6oL8I2Bd+o03PKLLqWfjrQWpC7NXeGbc/EKkIYCCOkPdpcfG3e/p/uCiNHo3hBctF8t0nxmji3+YE+6w83KVzFMxbNkWJEPElcckWKEZpx3/5I3owAHPGpjOXpL4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683793047; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=H0V7HhHtKM9k4p+hSzl/W/n+0SiKFZ7BnhitgUZAQrs=; b=N1Y0zmubFiOqnUIwY8OzjgDmFJlHW8oEMt19CXeBH0dTe2AdNtCKxS4qjeEN1K5o2RsIyMWT+X1gCl6FaF4C/lrT+SBPKs5facKEF8cLqwC3Dwf6f3Uh1c8IQrGUfGUdZr6WBSuFT+EOlNxahVBXoh/81NiwrS/mslCOOKxijtQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683793047112991.6220231009661; Thu, 11 May 2023 01:17:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Id-0006Pk-39; Thu, 11 May 2023 04:05:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1IS-0006Kb-N5 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:12 -0400 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IN-0000yJ-I5 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:06 -0400 Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-965e93f915aso1362002866b.2 for ; Thu, 11 May 2023 01:05:03 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792301; x=1686384301; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H0V7HhHtKM9k4p+hSzl/W/n+0SiKFZ7BnhitgUZAQrs=; b=y/pM4T5j8BRq29yg2Vd30dIrO6sXyeZa+tBNfD7MhXgzJWDxcXUzmOq8+kK3WuEVP+ eZcu+YpmZrGSqy4gdSaS2dhkxBT4O0FdKL5Ktn1/DH75dBN0Iz61OH1cvHGQ6aaetTBn mdnqonzjpKIDiAUb8FZaL+eu3GdaY6jiXcevibwAsxYZ8wZOArLjAkxWOeg/MQMpBk6n ToDjyXfQtH5qtNpqdyo5FsAHJmg2F/6/gzOmck7Xfqvaxm/yyarBz2owFruTm+6Dc7T+ xxS5x3+YYIC5ODCBTXmyyl2P+rrvdXkpLGWDBtlp9rRhb1SIXnA4g0SLK/cs5l3UD4b6 ABXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792301; x=1686384301; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H0V7HhHtKM9k4p+hSzl/W/n+0SiKFZ7BnhitgUZAQrs=; b=Se8gzHpBv4SqepWUP4bcwodgL2mtRi/p687roiwq6HgKIkHt5gCqviTWpwEABaB2Zq /mKTosYv2o6OCnThUmICFoB35yBozJS+tFvgOtCXqq1tZBzKNzBa4p2iawe8wc2E8fJ0 uCiPe6hYUvm7s5/ywqYcm99UtbCFSzNfZeLcofikwJnQm+S/1GVJz61Zc9qimCQVzWed wp6odML41dKv0NIjO5/ITG+N2+6tq12vS0ZYiR8tYqRYPcpzKlwTUFhde4osnmH5L4ei UEHpvNIpBh8MJ79sXMEOrPOvz/H8wk+aniIdkc+qkQdDcfsJ3/UrNeAl3fLKBHOY4VXI AZig== X-Gm-Message-State: AC+VfDzaLc7DFLwieeyMOmBJ41hzHM3/PSRsFbmUw4XCoPBbnhf2HFhX PqSzzoUo803aouSgII+QyzxEYZXCNv2GSVwSXcUF0g== X-Google-Smtp-Source: ACHHUZ5tNkJUkzeDjS0tDmR1FMPFFGG8ZXhnk8Vw3UaxeY4UnIlvWX19IjrfF1F5/yjL/giE0DJVLA== X-Received: by 2002:a17:907:84a:b0:94e:bc04:c6f6 with SMTP id ww10-20020a170907084a00b0094ebc04c6f6mr17378955ejb.9.1683792301587; Thu, 11 May 2023 01:05:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 14/53] tcg/arm: Introduce prepare_host_addr Date: Thu, 11 May 2023 09:04:11 +0100 Message-Id: <20230511080450.860923-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683793047749100001 Merge tcg_out_tlb_load, add_qemu_ldst_label, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 351 ++++++++++++++++++--------------------- 1 file changed, 159 insertions(+), 192 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index b6b4ffc546..c744512778 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1434,125 +1434,6 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGR= eg argreg, } } =20 -#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS) - -/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256); - -/* These offsets are built into the LDRD below. */ -QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); -QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 4); - -/* Load and compare a TLB entry, leaving the flags set. Returns the regis= ter - containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */ - -static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, - MemOp opc, int mem_index, bool is_load) -{ - int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); - unsigned s_mask =3D (1 << (opc & MO_SIZE)) - 1; - unsigned a_mask =3D (1 << get_alignment_bits(opc)) - 1; - TCGReg t_addr; - - /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */ - tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); - - /* Extract the tlb index from the address into R0. */ - tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo, - SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)); - - /* - * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. - * Load the tlb comparator into R2/R3 and the fast path addend into R1. - */ - if (cmp_off =3D=3D 0) { - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); - } else { - tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); - } - } else { - tcg_out_dat_reg(s, COND_AL, ARITH_ADD, - TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); - } else { - tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); - } - } - - /* Load the tlb addend. */ - tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, - offsetof(CPUTLBEntry, addend)); - - /* - * Check alignment, check comparators. - * Do this in 2-4 insns. Use MOVW for v7, if possible, - * to reduce the number of sequential conditional instructions. - * Almost all guests have at least 4k pages, which means that we need - * to clear at least 9 bits even for an 8-byte memory, which means it - * isn't worth checking for an immediate operand for BIC. - * - * For unaligned accesses, test the page of the last unit of alignment. - * This leaves the least significant alignment bits unchanged, and of - * course must be zero. - */ - t_addr =3D addrlo; - if (a_mask < s_mask) { - t_addr =3D TCG_REG_R0; - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, - addrlo, s_mask - a_mask); - } - if (use_armv7_instructions && TARGET_PAGE_BITS <=3D 16) { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(TARGET_PAGE_MASK | a_mas= k)); - tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, - t_addr, TCG_REG_TMP, 0); - tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP,= 0); - } else { - if (a_mask) { - tcg_debug_assert(a_mask <=3D 0xff); - tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); - } - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, - SHIFT_IMM_LSR(TARGET_PAGE_BITS)); - tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, - 0, TCG_REG_R2, TCG_REG_TMP, - SHIFT_IMM_LSL(TARGET_PAGE_BITS)); - } - - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0); - } - - return TCG_REG_R1; -} - -/* Record the context of a call to the out of line helper code for the slow - path for a load or store, so that we can later generate the correct - helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, - MemOpIdx oi, TCGType type, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addrhi, - tcg_insn_unit *raddr, - tcg_insn_unit *label_ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D type; - label->datalo_reg =3D datalo; - label->datahi_reg =3D datahi; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr; -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGReg argreg; @@ -1636,29 +1517,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) return true; } #else - -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrl= o, - TCGReg addrhi, unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; - - /* We are expecting a_bits to max out at 7, and can easily support 8. = */ - tcg_debug_assert(a_mask <=3D 0xff); - /* tst addr, #mask */ - tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); - - /* blne slow_path */ - label->label_ptr[0] =3D s->code_ptr; - tcg_out_bl_imm(s, COND_NE, 0); - - label->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { if (!reloc_pc24(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -1703,6 +1561,134 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) } #endif /* SOFTMMU */ =20 +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, bool is_ld) +{ + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + MemOp a_bits =3D get_alignment_bits(opc); + unsigned a_mask =3D (1 << a_bits) - 1; + +#ifdef CONFIG_SOFTMMU + int mem_index =3D get_mmuidx(oi); + int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write); + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + unsigned s_mask =3D (1 << (opc & MO_SIZE)) - 1; + TCGReg t_addr; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */ + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256); + QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); + QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 4); + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); + + /* Extract the tlb index from the address into R0. */ + tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo, + SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)); + + /* + * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. + * Load the tlb comparator into R2/R3 and the fast path addend into R1. + */ + if (cmp_off =3D=3D 0) { + if (TARGET_LONG_BITS =3D=3D 64) { + tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); + } else { + tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); + } + } else { + tcg_out_dat_reg(s, COND_AL, ARITH_ADD, + TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); + if (TARGET_LONG_BITS =3D=3D 64) { + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); + } else { + tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); + } + } + + /* Load the tlb addend. */ + tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, + offsetof(CPUTLBEntry, addend)); + + /* + * Check alignment, check comparators. + * Do this in 2-4 insns. Use MOVW for v7, if possible, + * to reduce the number of sequential conditional instructions. + * Almost all guests have at least 4k pages, which means that we need + * to clear at least 9 bits even for an 8-byte memory, which means it + * isn't worth checking for an immediate operand for BIC. + * + * For unaligned accesses, test the page of the last unit of alignment. + * This leaves the least significant alignment bits unchanged, and of + * course must be zero. + */ + t_addr =3D addrlo; + if (a_mask < s_mask) { + t_addr =3D TCG_REG_R0; + tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, + addrlo, s_mask - a_mask); + } + if (use_armv7_instructions && TARGET_PAGE_BITS <=3D 16) { + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(TARGET_PAGE_MASK | a_mas= k)); + tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, + t_addr, TCG_REG_TMP, 0); + tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP,= 0); + } else { + if (a_mask) { + tcg_debug_assert(a_mask <=3D 0xff); + tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); + } + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, + SHIFT_IMM_LSR(TARGET_PAGE_BITS)); + tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, + 0, TCG_REG_R2, TCG_REG_TMP, + SHIFT_IMM_LSL(TARGET_PAGE_BITS)); + } + + if (TARGET_LONG_BITS =3D=3D 64) { + tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0); + } + + *h =3D (HostAddress){ + .cond =3D COND_AL, + .base =3D addrlo, + .index =3D TCG_REG_R1, + .index_scratch =3D true, + }; +#else + if (a_mask) { + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + /* We are expecting a_bits to max out at 7 */ + tcg_debug_assert(a_mask <=3D 0xff); + /* tst addr, #mask */ + tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); + } + + *h =3D (HostAddress){ + .cond =3D COND_AL, + .base =3D addrlo, + .index =3D guest_base ? TCG_REG_GUEST_BASE : -1, + .index_scratch =3D false, + }; +#endif + + return ldst; +} + static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, TCGReg datahi, HostAddress h) { @@ -1799,37 +1785,28 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - h.cond =3D COND_AL; - h.base =3D addrlo; - h.index_scratch =3D true; - h.index =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 1= ); + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, true); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; =20 - /* - * This a conditional BL only to load a pointer within this opcode into - * LR for the slow path. We will not be using the value for a tail ca= ll. - */ - tcg_insn_unit *label_ptr =3D s->code_ptr; - tcg_out_bl_imm(s, COND_NE, 0); + /* + * This a conditional BL only to load a pointer within this + * opcode into LR for the slow path. We will not be using + * the value for a tail call. + */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_bl_imm(s, COND_NE, 0); =20 - tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); - - add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); + tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); + } else { + tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); } - - h.cond =3D COND_AL; - h.base =3D addrlo; - h.index =3D guest_base ? TCG_REG_GUEST_BASE : -1; - h.index_scratch =3D false; - tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); -#endif } =20 static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, @@ -1891,35 +1868,25 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - h.cond =3D COND_EQ; - h.base =3D addrlo; - h.index_scratch =3D true; - h.index =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 0= ); - tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, false); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; =20 - /* The conditional call must come last, as we're going to return here.= */ - tcg_insn_unit *label_ptr =3D s->code_ptr; - tcg_out_bl_imm(s, COND_NE, 0); - - add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - - h.cond =3D COND_AL; - if (a_bits) { - tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); h.cond =3D COND_EQ; - } + tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); =20 - h.base =3D addrlo; - h.index =3D guest_base ? TCG_REG_GUEST_BASE : -1; - h.index_scratch =3D false; - tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); -#endif + /* The conditional call is last, as we're going to return here. */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_bl_imm(s, COND_NE, 0); + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); + } else { + tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); + } } =20 static void tcg_out_epilogue(TCGContext *s); --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792831; cv=none; d=zohomail.com; s=zohoarc; b=N05ic/f+SfGoDQrTmFj8NsRz0SMm9wailif/qRKHOYfLjKcDV5eN6H/HwmOn/Fo4tv4CuZRNWNsbyLmqzAfL1FONsA+dGPWZaAD8zy/2rsxeJM/d8deuqNDgEc2Q19pjkStlfgZM6FHv4SboRYyj3MoJEPndgdjv7rwoYVox/mk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792831; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Lh4IgNBqqCeCY4GRiOSSQP+mNam0FJ6oAg9ySjC0hgE=; b=Cj53PflNX25DZGU8k9F1/jo7vyLsrEKQE9gm35WVD3UvK2rgqqKePg1fPjCQG26tOAIfzdcK0PoefJJ80JckEeF8o3a55btL3niBnkhim8xxNApZpbLI91Ui2l9dKRR1yfv8FQ6CcqxgizFOllJQjbgCO907StYtJyw1sG/8R2c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792831765107.24272250479873; Thu, 11 May 2023 01:13:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Ic-0006PS-Cw; Thu, 11 May 2023 04:05:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1IW-0006Mk-C8 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:12 -0400 Received: from mail-ed1-x530.google.com ([2a00:1450:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IN-0000yR-QI for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:11 -0400 Received: by mail-ed1-x530.google.com with SMTP id 4fb4d7f45d1cf-50bc0117683so14700257a12.1 for ; Thu, 11 May 2023 01:05:03 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792302; x=1686384302; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Lh4IgNBqqCeCY4GRiOSSQP+mNam0FJ6oAg9ySjC0hgE=; b=iSaKdB+glbAV2lDI/5/ZCgiegTZr1UdxD0+k5i0jWr4ReqWjkx4rC7Zdt4x2lY+2GC 1h1MjwMTlna1ecPV4WV5qsBXav90328PGmtdbo9xb2c0EjByGFjtUJfbIPOX3UYkily3 O8/+e0uc/Mo54GoyTjKBH88CTsVSmCV+2Hjo0xDJJYomQN2O8WP7+18lQk1x30uLZyeQ z8MTUFAPpIYfoc03uIY7zS9bXviarqzmE+bqNR9Ljgc05JWyyuu97bOeiKMKF9h5/GHJ S1mdYHznEVDyr5UuQvfMzUqJXB6nLgxntqC0r/yU5nkHO/SyCrYFjUMW+TN3uv04SX22 Lz1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792302; x=1686384302; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lh4IgNBqqCeCY4GRiOSSQP+mNam0FJ6oAg9ySjC0hgE=; b=HyM840pXCwTK0Ad/zfQ10iWVHeQXotpd4Ph9HbkWdxjO9Z/OVGufvoRzPPNc0hHkIr 6eSQ/DBFh//xZ6rsLa44I+zNAOTGqxgbR3rrIHjGmJGr7f+40BhEv8dgWkh3siPLac1O zrVbtdV6lypKFehPsMMVCKVxPrk81WLQCx/rM3TiqGYEroTN5MA14WfyPRpzJQrgR+iz 7Z8kdG0d0N3sIWAQKvlyRBKC9KN/cHMGN4gFsRMdSSlAIfxkJx0n+h4bff9sAf9vOGrT KE/tv+C0vytEDZNSrNlP0I5fbpRSPSTl1zViW7Unoj1SEDfLA2pYln24qqxq+gByUSg3 rx0A== X-Gm-Message-State: AC+VfDwV79G+5VXY4evb+uQ3NWkX4he8ngu2ZySJJ/vI6iBFGZPFII9k agxsoLuRdziEAbdK+KSEMVs+YqgtzlXXC2l3egpF0A== X-Google-Smtp-Source: ACHHUZ5SD+59kQsxjxjJkaMGXkUYt6V/gPmdhdFAW/LuTpR01cbqJ9zKic7cLVzrlwx8Kgl224teFw== X-Received: by 2002:a05:6402:14d3:b0:508:4120:202a with SMTP id f19-20020a05640214d300b005084120202amr17887269edx.10.1683792302279; Thu, 11 May 2023 01:05:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 15/53] tcg/loongarch64: Introduce prepare_host_addr Date: Thu, 11 May 2023 09:04:12 +0100 Message-Id: <20230511080450.860923-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792832845100005 Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, tcg_out_zext_addr_if_32_bit, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 255 +++++++++++++------------------ 1 file changed, 105 insertions(+), 150 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 6a87a5e5a3..2f2c34b930 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -818,81 +818,12 @@ static void * const qemu_st_helpers[4] =3D { [MO_64] =3D helper_le_stq_mmu, }; =20 -/* We expect to use a 12-bit negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); - static bool tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) { tcg_out_opc_b(s, 0); return reloc_br_sd10k16(s->code_ptr - 1, target); } =20 -/* - * Emits common code for TLB addend lookup, that eventually loads the - * addend in TCG_REG_TMP2. - */ -static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, MemOpIdx oi, - tcg_insn_unit **label_ptr, bool is_load) -{ - MemOp opc =3D get_memop(oi); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_bits =3D get_alignment_bits(opc); - tcg_target_long compare_mask; - int mem_index =3D get_mmuidx(oi); - int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); - int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); - int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); - - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); - - tcg_out_opc_srli_d(s, TCG_REG_TMP2, addrl, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); - tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); - - /* Load the tlb comparator and the addend. */ - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, - is_load ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, - offsetof(CPUTLBEntry, addend)); - - /* We don't support unaligned accesses. */ - if (a_bits < s_bits) { - a_bits =3D s_bits; - } - /* Clear the non-page, non-alignment bits from the address. */ - compare_mask =3D (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - = 1); - tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); - tcg_out_opc_and(s, TCG_REG_TMP1, TCG_REG_TMP1, addrl); - - /* Compare masked address with the TLB entry. */ - label_ptr[0] =3D s->code_ptr; - tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0); - - /* TLB Hit - addend in TCG_REG_TMP2, ready for use. */ -} - -static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, - TCGType type, - TCGReg datalo, TCGReg addrlo, - void *raddr, tcg_insn_unit **label_ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D type; - label->datalo_reg =3D datalo; - label->datahi_reg =3D 0; /* unused */ - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D 0; /* unused */ - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr[0]; -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { MemOpIdx oi =3D l->oi; @@ -941,33 +872,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, T= CGLabelQemuLdst *l) return tcg_out_goto(s, l->raddr); } #else - -/* - * Alignment helpers for user-mode emulation - */ - -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_= reg, - unsigned a_bits) -{ - TCGLabelQemuLdst *l =3D new_ldst_label(s); - - l->is_ld =3D is_ld; - l->addrlo_reg =3D addr_reg; - - /* - * Without micro-architecture details, we don't know which of bstrpick= or - * andi is faster, so use bstrpick as it's not constrained by imm field - * width. (Not to say alignments >=3D 2^12 are going to happen any time - * soon, though) - */ - tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1); - - l->label_ptr[0] =3D s->code_ptr; - tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0); - - l->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { /* resolve label address */ @@ -997,27 +901,102 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) =20 #endif /* CONFIG_SOFTMMU */ =20 -/* - * `ext32u` the address register into the temp register given, - * if target is 32-bit, no-op otherwise. - * - * Returns the address register ready for use with TLB addend. - */ -static TCGReg tcg_out_zext_addr_if_32_bit(TCGContext *s, - TCGReg addr, TCGReg tmp) -{ - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, tmp, addr); - return tmp; - } - return addr; -} - typedef struct { TCGReg base; TCGReg index; } HostAddress; =20 +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addr_reg, MemOpIdx oi, + bool is_ld) +{ + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + +#ifdef CONFIG_SOFTMMU + unsigned s_bits =3D opc & MO_SIZE; + int mem_index =3D get_mmuidx(oi); + int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); + int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); + tcg_target_long compare_mask; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); + + tcg_out_opc_srli_d(s, TCG_REG_TMP2, addr_reg, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); + tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); + + /* Load the tlb comparator and the addend. */ + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, + is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, + offsetof(CPUTLBEntry, addend)); + + /* We don't support unaligned accesses. */ + if (a_bits < s_bits) { + a_bits =3D s_bits; + } + /* Clear the non-page, non-alignment bits from the address. */ + compare_mask =3D (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - = 1); + tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); + tcg_out_opc_and(s, TCG_REG_TMP1, TCG_REG_TMP1, addr_reg); + + /* Compare masked address with the TLB entry. */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0); + + h->index =3D TCG_REG_TMP2; +#else + if (a_bits) { + ldst =3D new_ldst_label(s); + + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + /* + * Without micro-architecture details, we don't know which of + * bstrpick or andi is faster, so use bstrpick as it's not + * constrained by imm field width. Not to say alignments >=3D 2^12 + * are going to happen any time soon. + */ + tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1); + + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0); + } + + h->index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; +#endif + + if (TARGET_LONG_BITS =3D=3D 32) { + h->base =3D TCG_REG_TMP0; + tcg_out_ext32u(s, h->base, addr_reg); + } else { + h->base =3D addr_reg; + } + + return ldst; +} + static void tcg_out_qemu_ld_indexed(TCGContext *s, MemOp opc, TCGType type, TCGReg rd, HostAddress h) { @@ -1057,29 +1036,17 @@ static void tcg_out_qemu_ld_indexed(TCGContext *s, = MemOp opc, TCGType type, static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - tcg_insn_unit *label_ptr[1]; + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, true); + tcg_out_qemu_ld_indexed(s, get_memop(oi), data_type, data_reg, h); =20 - tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1); - h.index =3D TCG_REG_TMP2; -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, true, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - h.index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; -#endif - - h.base =3D tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0); - tcg_out_qemu_ld_indexed(s, opc, data_type, data_reg, h); - -#ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#endif } =20 static void tcg_out_qemu_st_indexed(TCGContext *s, MemOp opc, @@ -1109,29 +1076,17 @@ static void tcg_out_qemu_st_indexed(TCGContext *s, = MemOp opc, static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - tcg_insn_unit *label_ptr[1]; + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, false); + tcg_out_qemu_st_indexed(s, get_memop(oi), data_reg, h); =20 - tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0); - h.index =3D TCG_REG_TMP2; -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, false, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - h.index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; -#endif - - h.base =3D tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0); - tcg_out_qemu_st_indexed(s, opc, data_reg, h); - -#ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#endif } =20 /* --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792709; cv=none; d=zohomail.com; s=zohoarc; b=ZGY3UvXI9hg7N6qdlCnStnIllDDcSx1yJO6n4KSW1tgglHP3C9j7E8jsbZEfiAVnCbv0k7jw2G7xv/9R2i/74W2BfW6sE3ym3+SZHl3gZ2+TXCRlihRslXZ5gdFKDIcegzxFFhI1DbuFNOegBVFLxGbFUciSUzPiWJ7IaSxacOs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792709; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tFsAKR1F4unb+CV5xdOAnujvyBvYhp+S9YqQqo+ZzEU=; b=armdn6NGTM+xZdihl0jQRvJDwVgP9yIWXvCkWOp83GvpG69I26Ykv8YqBInsNh/HAYzyFSSHpa/Z1BZRP/pzskvDVpa1ZVTd0lVhrD53+J77egBKvTVXVZnGC1egfumJOj4LeM/Pkxmlbfd7jL/liMkkJwuTkLCBUPJ2pQrdsxw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792709904483.4901489085993; Thu, 11 May 2023 01:11:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Iu-00076h-Df; Thu, 11 May 2023 04:05:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1IS-0006Kc-Nw for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:11 -0400 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IO-0000x2-4C for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:07 -0400 Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-50db7ec8188so4837105a12.2 for ; Thu, 11 May 2023 01:05:03 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792303; x=1686384303; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tFsAKR1F4unb+CV5xdOAnujvyBvYhp+S9YqQqo+ZzEU=; b=mrS7vwiZDWJgidTwmu/joIQm5DcCcdFwifdhqNiWt1SrRfgcoFtmAYa0M+v4C9lBFV 6PB6i5A+ND7H/zjU/1I2tgI6aco04WskihoAGCNjOzkWIEBT+iPZXxZcH2jGGIdKLyMB J3Zsunt85QobCc12Ti5G9jklQ3UEDD6pP4pkzkekiNegbQJSn3N4lGtR70BX764uBn5w FBNkEjGC9GbWkEP/q1BVAWZz4GgebkXxX9n5RJO2KpC06x1f19ngG/lDj7/4cj+ByZYr Jmzm1MzIFD/k4UsNpbaHSapwGwukOaefs22SBLHDCKXTG3o5xVs76nu2u6HFy8jRO7PG dpug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792303; x=1686384303; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tFsAKR1F4unb+CV5xdOAnujvyBvYhp+S9YqQqo+ZzEU=; b=F+oCwhKyBH3DC+uTDh8oFqTwxArLEpuQrXKK8bvfrocYqewJD2mHJIfhbEDwPAu6yW 2/Bdc4J4jQaLHEAzk83ez4ehbWWVtS6rgugwlzkDuIoq51EsrBprCPovsDjhaxbaapq5 aymVZ0S3DPgBZUrYkzbIB20qhiq2mZMjlV56PwalYNZHlMIhDGf7XR2+nfhgFYsoQlSa E8n+g7/lJZ/bgOr9YdXZ5E3sr3wiItkHcR2u2YsfhWNvbL73OzV1JKHMeq6Z1vFuQyZe Bqa+P5iSITbSX3ps9/ah2sOhb0JonTEWdfSX5L+nvK1HOsKPWLjyqwQgXrC9x6nhiR7G NfyQ== X-Gm-Message-State: AC+VfDx9+LiWHpJ27eGc+QCra4b+F///xvstdOVbfK33f8AeiLPnx3dh jOvr/NDTi81slEP7n1NXI88iKiHeXAUARBXMIz3gig== X-Google-Smtp-Source: ACHHUZ4ynPIW/xQzSaVd59sr3kQZLUZdSz/XloaaSd2bNz1AYXN671X5mRMeRFosgGcYXWXroiPXqw== X-Received: by 2002:a17:907:3e1d:b0:94e:dd30:54b5 with SMTP id hp29-20020a1709073e1d00b0094edd3054b5mr20961374ejc.6.1683792302816; Thu, 11 May 2023 01:05:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 16/53] tcg/mips: Introduce prepare_host_addr Date: Thu, 11 May 2023 09:04:13 +0100 Message-Id: <20230511080450.860923-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792711345100002 Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 404 ++++++++++++++++---------------------- 1 file changed, 172 insertions(+), 232 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index ef8350e9cd..94708e6ea7 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1181,120 +1181,6 @@ static int tcg_out_call_iarg_reg2(TCGContext *s, in= t i, TCGReg al, TCGReg ah) return i; } =20 -/* We expect to use a 16-bit negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); - -/* - * Perform the tlb comparison operation. - * The complete host address is placed in BASE. - * Clobbers TMP0, TMP1, TMP2, TMP3. - */ -static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, - TCGReg addrh, MemOpIdx oi, - tcg_insn_unit *label_ptr[2], bool is_load) -{ - MemOp opc =3D get_memop(oi); - unsigned a_bits =3D get_alignment_bits(opc); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_mask =3D (1 << a_bits) - 1; - unsigned s_mask =3D (1 << s_bits) - 1; - int mem_index =3D get_mmuidx(oi); - int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); - int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); - int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); - int add_off =3D offsetof(CPUTLBEntry, addend); - int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - target_ulong tlb_mask; - - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); - - /* Extract the TLB index from the address into TMP3. */ - tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); - - /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3= . */ - tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); - - /* Load the (low-half) tlb comparator. */ - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); - } else { - tcg_out_ldst(s, (TARGET_LONG_BITS =3D=3D 64 ? OPC_LD - : TCG_TARGET_REG_BITS =3D=3D 64 ? OPC_LWU : OPC_L= W), - TCG_TMP0, TCG_TMP3, cmp_off); - } - - /* Zero extend a 32-bit guest address for a 64-bit host. */ - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addrl); - addrl =3D base; - } - - /* - * Mask the page bits, keeping the alignment bits to compare against. - * For unaligned accesses, compare against the end of the access to - * verify that it does not cross a page boundary. - */ - tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; - tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, tlb_mask); - if (a_mask >=3D s_mask) { - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); - } else { - tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP2, addrl, s_mask - a_mask); - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); - } - - if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { - /* Load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); - } - - label_ptr[0] =3D s->code_ptr; - tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); - - /* Load and test the high half tlb comparator. */ - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - /* delay slot */ - tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); - - /* Load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); - - label_ptr[1] =3D s->code_ptr; - tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0); - } - - /* delay slot */ - tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl); -} - -static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, - TCGType ext, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addrhi, - void *raddr, tcg_insn_unit *label_ptr[2]) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D ext; - label->datalo_reg =3D datalo; - label->datahi_reg =3D datahi; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr[0]; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - label->label_ptr[1] =3D label_ptr[1]; - } -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { const tcg_insn_unit *tgt_rx =3D tcg_splitwx_to_rx(s->code_ptr); @@ -1403,32 +1289,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) } =20 #else - -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrl= o, - TCGReg addrhi, unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *l =3D new_ldst_label(s); - - l->is_ld =3D is_ld; - l->addrlo_reg =3D addrlo; - l->addrhi_reg =3D addrhi; - - /* We are expecting a_bits to max out at 7, much lower than ANDI. */ - tcg_debug_assert(a_bits < 16); - tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask); - - l->label_ptr[0] =3D s->code_ptr; - if (use_mips32r6_instructions) { - tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); - } else { - tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); - tcg_out_nop(s); - } - - l->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { void *target; @@ -1478,6 +1338,154 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) } #endif /* SOFTMMU */ =20 +typedef struct { + TCGReg base; + MemOp align; +} HostAddress; + +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, bool is_ld) +{ + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned s_bits =3D opc & MO_SIZE; + unsigned a_mask =3D (1 << a_bits) - 1; + TCGReg base; + +#ifdef CONFIG_SOFTMMU + unsigned s_mask =3D (1 << s_bits) - 1; + int mem_index =3D get_mmuidx(oi); + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); + int add_off =3D offsetof(CPUTLBEntry, addend); + int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write); + target_ulong tlb_mask; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + base =3D TCG_REG_A0; + + /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); + + /* Extract the TLB index from the address into TMP3. */ + tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrlo, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); + + /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3= . */ + tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); + + /* Load the (low-half) tlb comparator. */ + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); + } else { + tcg_out_ldst(s, (TARGET_LONG_BITS =3D=3D 64 ? OPC_LD + : TCG_TARGET_REG_BITS =3D=3D 64 ? OPC_LWU : OPC_L= W), + TCG_TMP0, TCG_TMP3, cmp_off); + } + + /* Zero extend a 32-bit guest address for a 64-bit host. */ + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, base, addrlo); + addrlo =3D base; + } + + /* + * Mask the page bits, keeping the alignment bits to compare against. + * For unaligned accesses, compare against the end of the access to + * verify that it does not cross a page boundary. + */ + tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; + tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, tlb_mask); + if (a_mask >=3D s_mask) { + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo); + } else { + tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP2, addrlo, s_mask - a_mask); + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); + } + + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + /* Load the tlb addend for the fast path. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); + } + + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); + + /* Load and test the high half tlb comparator. */ + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + /* delay slot */ + tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); + + /* Load the tlb addend for the fast path. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); + + ldst->label_ptr[1] =3D s->code_ptr; + tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0); + } + + /* delay slot */ + tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrlo); +#else + if (a_mask && (use_mips32r6_instructions || a_bits !=3D s_bits)) { + ldst =3D new_ldst_label(s); + + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + /* We are expecting a_bits to max out at 7, much lower than ANDI. = */ + tcg_debug_assert(a_bits < 16); + tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask); + + ldst->label_ptr[0] =3D s->code_ptr; + if (use_mips32r6_instructions) { + tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); + } else { + tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); + tcg_out_nop(s); + } + } + + base =3D addrlo; + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_A0, base); + base =3D TCG_REG_A0; + } + if (guest_base) { + if (guest_base =3D=3D (int16_t)guest_base) { + tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); + } else { + tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, + TCG_GUEST_BASE_REG); + } + base =3D TCG_REG_A0; + } +#endif + + h->base =3D base; + h->align =3D a_bits; + return ldst; +} + static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, TCGReg base, MemOp opc, TCGType type) { @@ -1707,57 +1715,23 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); - unsigned a_bits =3D get_alignment_bits(opc); - unsigned s_bits =3D opc & MO_SIZE; - TCGReg base; + TCGLabelQemuLdst *ldst; + HostAddress h; =20 - /* - * R6 removes the left/right instructions but requires the - * system to support misaligned memory accesses. - */ -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[2]; + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, true); =20 - base =3D TCG_REG_A0; - tcg_out_tlb_load(s, base, addrlo, addrhi, oi, label_ptr, 1); - if (use_mips32r6_instructions || a_bits >=3D s_bits) { - tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type); + if (use_mips32r6_instructions || h.align >=3D (opc & MO_SIZE)) { + tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); } else { - tcg_out_qemu_ld_unalign(s, datalo, datahi, base, opc, data_type); + tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type); } - add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#else - base =3D addrlo; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_A0, base); - base =3D TCG_REG_A0; + + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - if (guest_base) { - if (guest_base =3D=3D (int16_t)guest_base) { - tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); - } else { - tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, - TCG_GUEST_BASE_REG); - } - base =3D TCG_REG_A0; - } - if (use_mips32r6_instructions) { - if (a_bits) { - tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); - } - tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type); - } else { - if (a_bits && a_bits !=3D s_bits) { - tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); - } - if (a_bits >=3D s_bits) { - tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type= ); - } else { - tcg_out_qemu_ld_unalign(s, datalo, datahi, base, opc, data_typ= e); - } - } -#endif } =20 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, @@ -1899,57 +1873,23 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); - unsigned a_bits =3D get_alignment_bits(opc); - unsigned s_bits =3D opc & MO_SIZE; - TCGReg base; + TCGLabelQemuLdst *ldst; + HostAddress h; =20 - /* - * R6 removes the left/right instructions but requires the - * system to support misaligned memory accesses. - */ -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[2]; + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, false); =20 - base =3D TCG_REG_A0; - tcg_out_tlb_load(s, base, addrlo, addrhi, oi, label_ptr, 0); - if (use_mips32r6_instructions || a_bits >=3D s_bits) { - tcg_out_qemu_st_direct(s, datalo, datahi, base, opc); + if (use_mips32r6_instructions || h.align >=3D (opc & MO_SIZE)) { + tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); } else { - tcg_out_qemu_st_unalign(s, datalo, datahi, base, opc); + tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); } - add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#else - base =3D addrlo; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_A0, base); - base =3D TCG_REG_A0; + + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - if (guest_base) { - if (guest_base =3D=3D (int16_t)guest_base) { - tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); - } else { - tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, - TCG_GUEST_BASE_REG); - } - base =3D TCG_REG_A0; - } - if (use_mips32r6_instructions) { - if (a_bits) { - tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); - } - tcg_out_qemu_st_direct(s, datalo, datahi, base, opc); - } else { - if (a_bits && a_bits !=3D s_bits) { - tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); - } - if (a_bits >=3D s_bits) { - tcg_out_qemu_st_direct(s, datalo, datahi, base, opc); - } else { - tcg_out_qemu_st_unalign(s, datalo, datahi, base, opc); - } - } -#endif } =20 static void tcg_out_mb(TCGContext *s, TCGArg a0) --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792382; cv=none; d=zohomail.com; s=zohoarc; b=YoukNHz0HIntP/LiV2PpGbfmo1wlmXpCeczkdBmTvlBO976PowAcJZ7TNWRDsdlHLfFEHiH7Gp2aENEdDhGmcs5Jma9De/1mo3tpJ4reJYQe5ij8t0U7ejCBrP16wbvU9W61+jpXccXc+FRcNDCJg8Dc1xZA+dLIB7e7H1cGQC8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792382; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4G/Epwo7Q+ZNo/cIUdCaZ2PtYugLXplOtsNze4CSSQI=; b=E66qxtTmame1W90TfZrJevRe64TkWWdmBxybciovXyH+4++9Jert7eiUbwS+d+HHf4gooh6d33KXGwLtdcfif5HnfnhSoed7Qz1+eUfpgCGU04QJyECCCDYPCoUlJfKNfrmGXCpVZjXNy/HHkgwoR4fUmWO8Xn7ko0XjQJUtjSg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792382428716.6593785825597; Thu, 11 May 2023 01:06:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Iq-0006sZ-1s; Thu, 11 May 2023 04:05:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Ih-0006RL-D0 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:25 -0400 Received: from mail-ed1-x52c.google.com ([2a00:1450:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IS-0000z1-3S for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:23 -0400 Received: by mail-ed1-x52c.google.com with SMTP id 4fb4d7f45d1cf-50b383222f7so12306532a12.3 for ; Thu, 11 May 2023 01:05:04 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792304; x=1686384304; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4G/Epwo7Q+ZNo/cIUdCaZ2PtYugLXplOtsNze4CSSQI=; b=lrP0iRAKIiH4IJ2aX3RM/gEa5f/+yfrVTkYpk17GhHF74apxgladSnrQzkHXrRAJKo JUjZFeL039dGq9USoAKMknj70xcfjleZWDEC8IBPh4KD/mJwG48UngH1QynFr9Ctfqzt 7ieizOhznX7V/AMrGLlrJp+k6p9apcfVTesfN6L3WgHT2sm4GgfJStQE9bjs7L7IIvQG 9OMPL/aocuHRe8NJpkJSsJ+103ZGP/vJMGUmP5xacVCwJiJ5Q6XtMZbRpxmVXKhFCL2C 3zTPF3UAHLFex55gzyatCBHsu2grnhdxf12k4jnc7+3/znAAI+VhMZxvkAUK62FK64Mz /G6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792304; x=1686384304; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4G/Epwo7Q+ZNo/cIUdCaZ2PtYugLXplOtsNze4CSSQI=; b=hkxWTmc3xKjbAVCs0BgFoDKVIxcu2EIZGB9mbXh/LYGVrGjuMDcT0XQ2op8o0QEyBi 7qivPLR1gW738nSODErHhDMi89CDy/XIi/7uIFzInOd10HHAAR+GXe58qHBTk3Miw54/ MP6YT+PY7G+AVeigc1U0uQz9haBp0srX2sm/YhP4VrqY2VQyrlRrgg6M9kPZQtPX9gn4 F8SnTZahSYYDUG3N2WqTwLN+00Bif7dPKl/3lf/ZhiVSW6bBdckfmbiG6evt5tcMbd2u re5rbQL1CRcDy4hP1hkWzN6gJnQQx9fiLYxVwdb1NT/kaDlz6DdYE6EpNBBHfbHV3UiA ydpg== X-Gm-Message-State: AC+VfDwTQY+JVDqB0vNfn/292xKPA1hEs5/0Bd4XTQcnrdTTvNV+j5Ds dBVV1za0z9Vj3qfv0pF160i20m/KcJK+96eBLMVTxA== X-Google-Smtp-Source: ACHHUZ7GJ1KbEYyOAVuHrc+PZCLAdDOkYfDjBut7nnd414BXVFto6mR4Es3t5fVUOFztQqwMa5Q8Cg== X-Received: by 2002:aa7:cd76:0:b0:50b:c5b0:4de6 with SMTP id ca22-20020aa7cd76000000b0050bc5b04de6mr15254108edb.9.1683792303453; Thu, 11 May 2023 01:05:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 17/53] tcg/ppc: Introduce prepare_host_addr Date: Thu, 11 May 2023 09:04:14 +0100 Message-Id: <20230511080450.860923-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792382741100001 Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 381 ++++++++++++++++++--------------------- 1 file changed, 172 insertions(+), 209 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index cd473deb36..0469e299a0 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2003,140 +2003,6 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_B= SWAP) + 1] =3D { [MO_BEUQ] =3D helper_be_stq_mmu, }; =20 -/* We expect to use a 16-bit negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); - -/* Perform the TLB load and compare. Places the result of the comparison - in CR7, loads the addend of the TLB into R3, and returns the register - containing the guest address (zero-extended into R4). Clobbers R0 and = R2. */ - -static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc, - TCGReg addrlo, TCGReg addrhi, - int mem_index, bool is_read) -{ - int cmp_off - =3D (is_read - ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); - int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); - int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_bits =3D get_alignment_bits(opc); - - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off); - - /* Extract the page index, shifted into place for tlb index. */ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_shri32(s, TCG_REG_TMP1, addrlo, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - } else { - tcg_out_shri64(s, TCG_REG_TMP1, addrlo, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - } - tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1)); - - /* Load the TLB comparator. */ - if (cmp_off =3D=3D 0 && TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { - uint32_t lxu =3D (TCG_TARGET_REG_BITS =3D=3D 32 || TARGET_LONG_BIT= S =3D=3D 32 - ? LWZUX : LDUX); - tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4)); - } else { - tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4)); - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off = + 4); - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off); - } else { - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off); - } - } - - /* Load the TLB addend for use on the fast path. Do this asap - to minimize any load use delay. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, - offsetof(CPUTLBEntry, addend)); - - /* Clear the non-page, non-alignment bits from the address */ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - /* We don't support unaligned accesses on 32-bits. - * Preserve the bottom bits and thus trigger a comparison - * failure on unaligned accesses. - */ - if (a_bits < s_bits) { - a_bits =3D s_bits; - } - tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0, - (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); - } else { - TCGReg t =3D addrlo; - - /* If the access is unaligned, we need to make sure we fail if we - * cross a page boundary. The trick is to add the access size-1 - * to the address before masking the low bits. That will make the - * address overflow to the next page if we cross a page boundary, - * which will then force a mismatch of the TLB compare. - */ - if (a_bits < s_bits) { - unsigned a_mask =3D (1 << a_bits) - 1; - unsigned s_mask =3D (1 << s_bits) - 1; - tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask)); - t =3D TCG_REG_R0; - } - - /* Mask the address for the requested alignment. */ - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, - (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); - /* Zero-extend the address for use in the final address. */ - tcg_out_ext32u(s, TCG_REG_R4, addrlo); - addrlo =3D TCG_REG_R4; - } else if (a_bits =3D=3D 0) { - tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS= ); - } else { - tcg_out_rld(s, RLDICL, TCG_REG_R0, t, - 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits); - tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BIT= S, 0); - } - } - - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, - 0, 7, TCG_TYPE_I32); - tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32= ); - tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); - } else { - tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, - 0, 7, TCG_TYPE_TL); - } - - return addrlo; -} - -/* Record the context of a call to the out of line helper code for the slow - path for a load or store, so that we can later generate the correct - helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, - TCGType type, MemOpIdx oi, - TCGReg datalo_reg, TCGReg datahi_reg, - TCGReg addrlo_reg, TCGReg addrhi_reg, - tcg_insn_unit *raddr, tcg_insn_unit *lptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->type =3D type; - label->oi =3D oi; - label->datalo_reg =3D datalo_reg; - label->datahi_reg =3D datahi_reg; - label->addrlo_reg =3D addrlo_reg; - label->addrhi_reg =3D addrhi_reg; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D lptr; -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { MemOpIdx oi =3D lb->oi; @@ -2225,27 +2091,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) return true; } #else - -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrl= o, - TCGReg addrhi, unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; - - /* We are expecting a_bits to max out at 7, much lower than ANDI. */ - tcg_debug_assert(a_bits < 16); - tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, a_mask)); - - label->label_ptr[0] =3D s->code_ptr; - tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK); - - label->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { if (!reloc_pc14(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -2294,37 +2139,171 @@ typedef struct { TCGReg index; } HostAddress; =20 +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, bool is_ld) +{ + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + +#ifdef CONFIG_SOFTMMU + int mem_index =3D get_mmuidx(oi); + int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write); + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); + unsigned s_bits =3D opc & MO_SIZE; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off); + + /* Extract the page index, shifted into place for tlb index. */ + if (TCG_TARGET_REG_BITS =3D=3D 32) { + tcg_out_shri32(s, TCG_REG_TMP1, addrlo, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + } else { + tcg_out_shri64(s, TCG_REG_TMP1, addrlo, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + } + tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1)); + + /* Load the TLB comparator. */ + if (cmp_off =3D=3D 0 && TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + uint32_t lxu =3D (TCG_TARGET_REG_BITS =3D=3D 32 || TARGET_LONG_BIT= S =3D=3D 32 + ? LWZUX : LDUX); + tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4)); + } else { + tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4)); + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off = + 4); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off); + } else { + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off); + } + } + + /* + * Load the TLB addend for use on the fast path. + * Do this asap to minimize any load use delay. + */ + h->base =3D TCG_REG_R3; + tcg_out_ld(s, TCG_TYPE_PTR, h->base, TCG_REG_R3, + offsetof(CPUTLBEntry, addend)); + + /* Clear the non-page, non-alignment bits from the address */ + if (TCG_TARGET_REG_BITS =3D=3D 32) { + /* + * We don't support unaligned accesses on 32-bits. + * Preserve the bottom bits and thus trigger a comparison + * failure on unaligned accesses. + */ + if (a_bits < s_bits) { + a_bits =3D s_bits; + } + tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0, + (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); + } else { + TCGReg t =3D addrlo; + + /* + * If the access is unaligned, we need to make sure we fail if we + * cross a page boundary. The trick is to add the access size-1 + * to the address before masking the low bits. That will make the + * address overflow to the next page if we cross a page boundary, + * which will then force a mismatch of the TLB compare. + */ + if (a_bits < s_bits) { + unsigned a_mask =3D (1 << a_bits) - 1; + unsigned s_mask =3D (1 << s_bits) - 1; + tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask)); + t =3D TCG_REG_R0; + } + + /* Mask the address for the requested alignment. */ + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, + (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); + /* Zero-extend the address for use in the final address. */ + tcg_out_ext32u(s, TCG_REG_R4, addrlo); + addrlo =3D TCG_REG_R4; + } else if (a_bits =3D=3D 0) { + tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS= ); + } else { + tcg_out_rld(s, RLDICL, TCG_REG_R0, t, + 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits); + tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BIT= S, 0); + } + } + h->index =3D addrlo; + + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, + 0, 7, TCG_TYPE_I32); + tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32= ); + tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); + } else { + tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, + 0, 7, TCG_TYPE_TL); + } + + /* Load a pointer into the current opcode w/conditional branch-link. */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); +#else + if (a_bits) { + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + /* We are expecting a_bits to max out at 7, much lower than ANDI. = */ + tcg_debug_assert(a_bits < 16); + tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, (1 << a_bits) - 1)); + + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK); + } + + h->base =3D guest_base ? TCG_GUEST_BASE_REG : 0; + h->index =3D addrlo; + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); + h->index =3D TCG_REG_TMP1; + } +#endif + + return ldst; +} + static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - tcg_insn_unit *label_ptr; + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, true); =20 - h.index =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), t= rue); - h.base =3D TCG_REG_R3; - - /* Load a pointer into the current opcode w/conditional branch-link. */ - label_ptr =3D s->code_ptr; - tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); -#else /* !CONFIG_SOFTMMU */ - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); - } - h.base =3D guest_base ? TCG_GUEST_BASE_REG : 0; - h.index =3D addrlo; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); - h.index =3D TCG_REG_TMP1; - } -#endif - - if (TCG_TARGET_REG_BITS =3D=3D 32 && s_bits =3D=3D MO_64) { + if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { if (opc & MO_BSWAP) { tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); @@ -2357,10 +2336,12 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, } } =20 -#ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#endif + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); + } } =20 static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, @@ -2368,32 +2349,12 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - tcg_insn_unit *label_ptr; + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, false); =20 - h.index =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), f= alse); - h.base =3D TCG_REG_R3; - - /* Load a pointer into the current opcode w/conditional branch-link. */ - label_ptr =3D s->code_ptr; - tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); -#else /* !CONFIG_SOFTMMU */ - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); - } - h.base =3D guest_base ? TCG_GUEST_BASE_REG : 0; - h.index =3D addrlo; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); - h.index =3D TCG_REG_TMP1; - } -#endif - - if (TCG_TARGET_REG_BITS =3D=3D 32 && s_bits =3D=3D MO_64) { + if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { if (opc & MO_BSWAP) { tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); @@ -2418,10 +2379,12 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, } } =20 -#ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#endif + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); + } } =20 static void tcg_out_nop_fill(tcg_insn_unit *p, int count) --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683793034; cv=none; d=zohomail.com; s=zohoarc; b=S0HPG23qBCLPvHijHezwpeO0SmdK+8nNimt/yL7OmpSVEYUVHeSp1zqIu8jSjF8VDsHUGZ8nWYsQGuvLVzwRvRTjAwn4rmuLrXjIl5i+xOyiV6/xCwyKt2CMorwDMhqOJzazU53AJC4hOAVGt07t4VyP4Daw+vuYrqO+LoFg9C8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683793034; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XkF3/2eIXQLlh8f3HilwSMrgKtksr8bPayrf2imDWgY=; b=j8CCpHqiC1pKIxGUyI3NJKVtQ08ELSrMkMldY77y2rRvMjozq73vY3UJqevH8cI9ExnASY4z/O2RovVg9jRLcN26nER14+E2kXUm2ZFGH4wcZvG4NsYyN+MAS/6KuiVnPuZU0edFNPBqd5A/3HqbkUhhg95GGd4wiT1UbKhs9bM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683793034984493.76290481758167; Thu, 11 May 2023 01:17:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Im-0006fo-LH; Thu, 11 May 2023 04:05:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1IW-0006MO-5k for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:12 -0400 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IR-0000z8-My for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:11 -0400 Received: by mail-ed1-x52a.google.com with SMTP id 4fb4d7f45d1cf-50bc070c557so15618268a12.0 for ; Thu, 11 May 2023 01:05:05 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792304; x=1686384304; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XkF3/2eIXQLlh8f3HilwSMrgKtksr8bPayrf2imDWgY=; b=vHwVn8WGY5dYD12DYMAVV0zdz9cEiN8elAUfina8b6tHP4wspcFGzeDg5sqSiY299d 5FMFBehF2c11XCuXaph+wKbjnva30d8QGQf4cNuzhRTRi0N9RSQ7oH1Xl9ur0Cyjk4wO dj2eItx63geQEpn1Qid0wclWj6fEBaqjL8u+Y1vNzVNcVGEp5u12uukR1nwykTMm1Tqs 6icjU2KAXRAd460pUElbtNj68XxVscRUdurXDTmeYRt7+HpD0GybTm7j4gLeohVeh5B7 nI2AFTpvErB3WNHjdW/iPyJxFM2qw+rwEFmRvTLpdwsNdw0v0UWhehmIe2vYGv8WZb9K PVkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792304; x=1686384304; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XkF3/2eIXQLlh8f3HilwSMrgKtksr8bPayrf2imDWgY=; b=KokTBXWIFg1hQpQZbWM0pn7O2/bVOBn9sc8zpG+SAcXUwUVasmTQB3ZQOWggoRiUMC Xsz2knf0P8PhcRGD8wsdJl8Y3bHlykVV0FOIjImgJy/LlYpC3L6N789JZRXa0oMaEpT/ sa/dj59r9yKnEDqt0poGgAUSxAKiZVvHsqH7+XAMR4oW9oN8/mHhSeTL899I6YlQDT8i n9PSjNx3nPKM0cQtHWUXi1srh9GzoLEMBgcfFEEqwDnQtj/7pBUOOelZ+riXzZoZfONK FxX22Ip+gQd0k86BktgYvx3T6578LbUBkN/Zj+LsYdv0uyDOiqp2D5fcEESBNhLrYmyH k1XA== X-Gm-Message-State: AC+VfDyNr+fMGZru6oL7jD8uA5VfHMq6pQclNhSgzLv8N12Xy5J7j07k KKza6qN80tFTkN8waEJ6XCBQkcHhuxBJh8xo4PibbQ== X-Google-Smtp-Source: ACHHUZ5s4qJ1ANsxIQJburDFSO2g5KFY0dklOjkXBc3qIm5e7qtGal6vH9uC34w9S/EGwqHm3PBoiw== X-Received: by 2002:a17:907:72cc:b0:969:9118:a98f with SMTP id du12-20020a17090772cc00b009699118a98fmr11009565ejc.10.1683792304121; Thu, 11 May 2023 01:05:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 18/53] tcg/riscv: Introduce prepare_host_addr Date: Thu, 11 May 2023 09:04:15 +0100 Message-Id: <20230511080450.860923-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683793036018100005 Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns TCGReg and TCGLabelQemuLdst. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 253 +++++++++++++++++-------------------- 1 file changed, 114 insertions(+), 139 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index a4cf60ca75..2b2d313fe2 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -899,10 +899,6 @@ static void * const qemu_st_helpers[MO_SIZE + 1] =3D { #endif }; =20 -/* We expect to use a 12-bit negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); - static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) { tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); @@ -910,76 +906,6 @@ static void tcg_out_goto(TCGContext *s, const tcg_insn= _unit *target) tcg_debug_assert(ok); } =20 -static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, MemOpIdx oi, - tcg_insn_unit **label_ptr, bool is_load) -{ - MemOp opc =3D get_memop(oi); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_bits =3D get_alignment_bits(opc); - tcg_target_long compare_mask; - int mem_index =3D get_mmuidx(oi); - int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); - int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); - int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); - TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; - - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs); - - tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); - - /* Load the tlb comparator and the addend. */ - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, - is_load ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, - offsetof(CPUTLBEntry, addend)); - - /* We don't support unaligned accesses. */ - if (a_bits < s_bits) { - a_bits =3D s_bits; - } - /* Clear the non-page, non-alignment bits from the address. */ - compare_mask =3D (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - = 1); - if (compare_mask =3D=3D sextreg(compare_mask, 0, 12)) { - tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr, compare_mask); - } else { - tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); - tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr); - } - - /* Compare masked address with the TLB entry. */ - label_ptr[0] =3D s->code_ptr; - tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); - - /* TLB Hit - translate address using addend. */ - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_TMP0, addr); - addr =3D TCG_REG_TMP0; - } - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addr); - return TCG_REG_TMP0; -} - -static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, - TCGType data_type, TCGReg data_reg, - TCGReg addr_reg, void *raddr, - tcg_insn_unit **label_ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D data_type; - label->datalo_reg =3D data_reg; - label->addrlo_reg =3D addr_reg; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr[0]; -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { MemOpIdx oi =3D l->oi; @@ -1037,26 +963,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) return true; } #else - -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_= reg, - unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *l =3D new_ldst_label(s); - - l->is_ld =3D is_ld; - l->addrlo_reg =3D addr_reg; - - /* We are expecting a_bits to max out at 7, so we can always use andi.= */ - tcg_debug_assert(a_bits < 12); - tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask); - - l->label_ptr[0] =3D s->code_ptr; - tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0); - - l->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { /* resolve label address */ @@ -1083,9 +989,108 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) { return tcg_out_fail_alignment(s, l); } - #endif /* CONFIG_SOFTMMU */ =20 +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, + TCGReg addr_reg, MemOpIdx oi, + bool is_ld) +{ + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned a_mask =3D (1u << a_bits) - 1; + +#ifdef CONFIG_SOFTMMU + unsigned s_bits =3D opc & MO_SIZE; + int mem_index =3D get_mmuidx(oi); + int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); + int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); + TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; + tcg_target_long compare_mask; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs); + + tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr_reg, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); + + /* Load the tlb comparator and the addend. */ + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, + is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, + offsetof(CPUTLBEntry, addend)); + + /* We don't support unaligned accesses. */ + if (a_bits < s_bits) { + a_bits =3D s_bits; + } + /* Clear the non-page, non-alignment bits from the address. */ + compare_mask =3D (tcg_target_long)TARGET_PAGE_MASK | a_mask; + if (compare_mask =3D=3D sextreg(compare_mask, 0, 12)) { + tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, compare_mask); + } else { + tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); + tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr_reg); + } + + /* Compare masked address with the TLB entry. */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); + + /* TLB Hit - translate address using addend. */ + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg); + addr_reg =3D TCG_REG_TMP0; + } + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addr_reg); + *pbase =3D TCG_REG_TMP0; +#else + if (a_mask) { + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + /* We are expecting a_bits max 7, so we can always use andi. */ + tcg_debug_assert(a_bits < 12); + tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask); + + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0); + } + + TCGReg base =3D addr_reg; + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_ext32u(s, TCG_REG_TMP0, base); + base =3D TCG_REG_TMP0; + } + if (guest_base !=3D 0) { + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base= ); + base =3D TCG_REG_TMP0; + } + *pbase =3D base; +#endif + + return ldst; +} + static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val, TCGReg base, MemOp opc, TCGType type) { @@ -1125,32 +1130,17 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg val, static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; TCGReg base; =20 -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[1]; + ldst =3D prepare_host_addr(s, &base, addr_reg, oi, true); + tcg_out_qemu_ld_direct(s, data_reg, base, get_memop(oi), data_type); =20 - base =3D tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1); - tcg_out_qemu_ld_direct(s, data_reg, base, opc, data_type); - add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, true, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - base =3D addr_reg; - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_TMP0, base); - base =3D TCG_REG_TMP0; - } - if (guest_base !=3D 0) { - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base= ); - base =3D TCG_REG_TMP0; - } - tcg_out_qemu_ld_direct(s, data_reg, base, opc, data_type); -#endif } =20 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg val, @@ -1180,32 +1170,17 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg val, static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; TCGReg base; =20 -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[1]; + ldst =3D prepare_host_addr(s, &base, addr_reg, oi, false); + tcg_out_qemu_st_direct(s, data_reg, base, get_memop(oi)); =20 - base =3D tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0); - tcg_out_qemu_st_direct(s, data_reg, base, opc); - add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, false, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - base =3D addr_reg; - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_TMP0, base); - base =3D TCG_REG_TMP0; - } - if (guest_base !=3D 0) { - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base= ); - base =3D TCG_REG_TMP0; - } - tcg_out_qemu_st_direct(s, data_reg, base, opc); -#endif } =20 static const tcg_insn_unit *tb_ret_addr; --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792337; cv=none; d=zohomail.com; s=zohoarc; b=X+3bgF20sypA6ImHCLTgKxZv58ZBM/SwMA+cJ9qlN8LRLzz6lJNpE3WNAZVnGoDaSeYqQIzRDbtUwNJD0HW5ncHWFsYmyenN+S85XKQeuBG+dAqQ6+8Tl27zhZHVAMPmxnDfhonsHj2lzRx19aQgNs0fr+1cJlP8Ln+uerLXDzg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792337; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WJGLF3VMQwBAdiymHix5Qpi+BVax8590pOJ0fBYfNEw=; b=jC5//+gu9NKNMr1klzfN4jS2W1jpX+oC5elWcRKqsCdTbrpKTVb4pUJ07JjHj4RHUgQHh95EaKl4i/a1DKA5HiLmAGqpCJcNZV92IBHR28P1fTdD3xM7KSpKRoTzFh01KflCVLaQIffJ8MpXiV8qpXgfBvy1YHOvHiehLCVoF0o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792337011497.45899531227053; Thu, 11 May 2023 01:05:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Il-0006cO-3A; Thu, 11 May 2023 04:05:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Id-0006QJ-EH for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:19 -0400 Received: from mail-ed1-x530.google.com ([2a00:1450:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IT-0000zN-G3 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:19 -0400 Received: by mail-ed1-x530.google.com with SMTP id 4fb4d7f45d1cf-50bc25f0c7dso15004192a12.3 for ; Thu, 11 May 2023 01:05:05 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792305; x=1686384305; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WJGLF3VMQwBAdiymHix5Qpi+BVax8590pOJ0fBYfNEw=; b=hufyC5TH3jxN8xVZCk3mD3fCqbHX6dwk8UHvIRFwYnWphzo0bU/F6f1Y+oIGCH4lpE 5SLuR2kVKyGUwkpHnZwh05IW2QJmMUsAcyE4NCmS7hy1cdDUyPeePV+61kbZB1W6NgGL fioQnKPQMIsPEWsheRkAif+QvkDrsB2eK1Cwuq12EtHyC1GUireXbiq6Cb05WTRDxQAT FoF5t7NxnCKTTVFHGe7GXR7T1xQvhGDVtjeD4WVtLzDM/NfXFc8B+/mW1H5kzaU5YxDb aJrlI2/exCelNielcqLwMYRwcxDsEuQzOjyEBjmDsXBb/+UhSLMxJ8d28pjbFJp1dZhB D4Ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792305; x=1686384305; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WJGLF3VMQwBAdiymHix5Qpi+BVax8590pOJ0fBYfNEw=; b=bb+bZxOcyvky9LUV9UL87uzWPXzbNjz8ug+a2hKXibz11YKwMBLsxOxrh/nbIZYHxg wVc2mSf/I8qHzQvhZhMOFx9M6KZ+LBS3gKHX7RQSQfjBSvblzfayRcWs/jRwK/KwkR51 xnYve0A7xoJQCjPwCZBgT/3mmAzCDdfQyk8Op8k1b7kI+T3FtdZGh0TnAzWLkgecVH7h uaRhXQCrR0CPtakqb9eBhA38Wrr1OE4uPYr/pyTgj4tp0zCInfzEnKglIRDDDb1HrnvC O25v/m3t2kgTrXKfM5SUmpBDKyPDR6PrhIF8tz01zLUPEMQ0+u7PLTxaZfNFwhzKMAAU Mbxw== X-Gm-Message-State: AC+VfDwPUA6PWxfkWtbJzadzP3+6KxZtKOUl0IJ2YnpLn+a1fdqz+hQJ H+OopuM85kW8tHqfowDibdAZ+rbSHe+jSsZB5hkRKg== X-Google-Smtp-Source: ACHHUZ6eQeCxuEuRHRAw9titEvpYLLvtqAenZwSzcO28461NukdbYSMgsKfau1mmfygWkCRhj9kDsg== X-Received: by 2002:a05:6402:606:b0:506:8dba:bd71 with SMTP id n6-20020a056402060600b005068dbabd71mr17170798edv.27.1683792304863; Thu, 11 May 2023 01:05:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 19/53] tcg/s390x: Introduce prepare_host_addr Date: Thu, 11 May 2023 09:04:16 +0100 Message-Id: <20230511080450.860923-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792338367100007 Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, tcg_prepare_user_ldst, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 263 ++++++++++++++++--------------------- 1 file changed, 113 insertions(+), 150 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index da7ee5b085..c3157d22be 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1718,78 +1718,6 @@ static void tcg_out_qemu_st_direct(TCGContext *s, Me= mOp opc, TCGReg data, } =20 #if defined(CONFIG_SOFTMMU) -/* We're expecting to use a 20-bit negative offset on the tlb memory ops. = */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); - -/* Load and compare a TLB entry, leaving the flags set. Loads the TLB - addend into R2. Returns a register with the santitized guest address. = */ -static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc, - int mem_index, bool is_ld) -{ - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_bits =3D get_alignment_bits(opc); - unsigned s_mask =3D (1 << s_bits) - 1; - unsigned a_mask =3D (1 << a_bits) - 1; - int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); - int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); - int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); - int ofs, a_off; - uint64_t tlb_mask; - - tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - tcg_out_insn(s, RXY, NG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, mask_off= ); - tcg_out_insn(s, RXY, AG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, table_of= f); - - /* For aligned accesses, we check the first byte and include the align= ment - bits within the address. For unaligned access, we check that we do= n't - cross pages using the address of the last byte of the access. */ - a_off =3D (a_bits >=3D s_bits ? 0 : s_mask - a_mask); - tlb_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; - if (a_off =3D=3D 0) { - tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask); - } else { - tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off); - tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask); - } - - if (is_ld) { - ofs =3D offsetof(CPUTLBEntry, addr_read); - } else { - ofs =3D offsetof(CPUTLBEntry, addr_write); - } - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_insn(s, RX, C, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs); - } else { - tcg_out_insn(s, RXY, CG, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs= ); - } - - tcg_out_insn(s, RXY, LG, TCG_REG_R2, TCG_REG_R2, TCG_REG_NONE, - offsetof(CPUTLBEntry, addend)); - - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_R3, addr_reg); - return TCG_REG_R3; - } - return addr_reg; -} - -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, - TCGType type, TCGReg data, TCGReg addr, - tcg_insn_unit *raddr, tcg_insn_unit *label= _ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D type; - label->datalo_reg =3D data; - label->addrlo_reg =3D addr; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr; -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGReg addr_reg =3D lb->addrlo_reg; @@ -1842,26 +1770,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) return true; } #else -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, - TCGReg addrlo, unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *l =3D new_ldst_label(s); - - l->is_ld =3D is_ld; - l->addrlo_reg =3D addrlo; - - /* We are expecting a_bits to max out at 7, much lower than TMLL. */ - tcg_debug_assert(a_bits < 16); - tcg_out_insn(s, RI, TMLL, addrlo, a_mask); - - tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */ - l->label_ptr[0] =3D s->code_ptr; - s->code_ptr +=3D 1; - - l->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { if (!patch_reloc(l->label_ptr[0], R_390_PC16DBL, @@ -1888,91 +1796,146 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *= s, TCGLabelQemuLdst *l) { return tcg_out_fail_alignment(s, l); } +#endif /* CONFIG_SOFTMMU */ =20 -static HostAddress tcg_prepare_user_ldst(TCGContext *s, TCGReg addr_reg) +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addr_reg, MemOpIdx oi, + bool is_ld) { - TCGReg index; - int disp; + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned a_mask =3D (1u << a_bits) - 1; =20 +#ifdef CONFIG_SOFTMMU + unsigned s_bits =3D opc & MO_SIZE; + unsigned s_mask =3D (1 << s_bits) - 1; + int mem_index =3D get_mmuidx(oi); + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); + int ofs, a_off; + uint64_t tlb_mask; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); + tcg_out_insn(s, RXY, NG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, mask_off= ); + tcg_out_insn(s, RXY, AG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, table_of= f); + + /* + * For aligned accesses, we check the first byte and include the align= ment + * bits within the address. For unaligned access, we check that we do= n't + * cross pages using the address of the last byte of the access. + */ + a_off =3D (a_bits >=3D s_bits ? 0 : s_mask - a_mask); + tlb_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; + if (a_off =3D=3D 0) { + tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask); + } else { + tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off); + tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask); + } + + if (is_ld) { + ofs =3D offsetof(CPUTLBEntry, addr_read); + } else { + ofs =3D offsetof(CPUTLBEntry, addr_write); + } + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_insn(s, RX, C, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs); + } else { + tcg_out_insn(s, RXY, CG, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs= ); + } + + tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); + ldst->label_ptr[0] =3D s->code_ptr++; + + h->index =3D TCG_REG_R2; + tcg_out_insn(s, RXY, LG, h->index, TCG_REG_R2, TCG_REG_NONE, + offsetof(CPUTLBEntry, addend)); + + h->base =3D addr_reg; + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_ext32u(s, TCG_REG_R3, addr_reg); + h->base =3D TCG_REG_R3; + } + h->disp =3D 0; +#else + if (a_mask) { + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + /* We are expecting a_bits to max out at 7, much lower than TMLL. = */ + tcg_debug_assert(a_bits < 16); + tcg_out_insn(s, RI, TMLL, addr_reg, a_mask); + + tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */ + ldst->label_ptr[0] =3D s->code_ptr++; + } + + h->base =3D addr_reg; if (TARGET_LONG_BITS =3D=3D 32) { tcg_out_ext32u(s, TCG_TMP0, addr_reg); - addr_reg =3D TCG_TMP0; + h->base =3D TCG_TMP0; } if (guest_base < 0x80000) { - index =3D TCG_REG_NONE; - disp =3D guest_base; + h->index =3D TCG_REG_NONE; + h->disp =3D guest_base; } else { - index =3D TCG_GUEST_BASE_REG; - disp =3D 0; + h->index =3D TCG_GUEST_BASE_REG; + h->disp =3D 0; } - return (HostAddress){ .base =3D addr_reg, .index =3D index, .disp =3D = disp }; +#endif + + return ldst; } -#endif /* CONFIG_SOFTMMU */ =20 static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - unsigned mem_index =3D get_mmuidx(oi); - tcg_insn_unit *label_ptr; + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, true); + tcg_out_qemu_ld_direct(s, get_memop(oi), data_reg, h); =20 - h.base =3D tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1); - h.index =3D TCG_REG_R2; - h.disp =3D 0; - - tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); - label_ptr =3D s->code_ptr; - s->code_ptr +=3D 1; - - tcg_out_qemu_ld_direct(s, opc, data_reg, h); - - add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - - if (a_bits) { - tcg_out_test_alignment(s, true, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - h =3D tcg_prepare_user_ldst(s, addr_reg); - tcg_out_qemu_ld_direct(s, opc, data_reg, h); -#endif } =20 static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - unsigned mem_index =3D get_mmuidx(oi); - tcg_insn_unit *label_ptr; + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, false); + tcg_out_qemu_st_direct(s, get_memop(oi), data_reg, h); =20 - h.base =3D tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0); - h.index =3D TCG_REG_R2; - h.disp =3D 0; - - tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); - label_ptr =3D s->code_ptr; - s->code_ptr +=3D 1; - - tcg_out_qemu_st_direct(s, opc, data_reg, h); - - add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - - if (a_bits) { - tcg_out_test_alignment(s, false, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - h =3D tcg_prepare_user_ldst(s, addr_reg); - tcg_out_qemu_st_direct(s, opc, data_reg, h); -#endif } =20 static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792831; cv=none; d=zohomail.com; s=zohoarc; b=mnyTVT91jMXKeAH0yVvIi8STEuVylenL1kxD6bgcHw2pnI3HrAqt/sSAh7np5eMOd3PIaA3JJr54ssBTyzb/ZJvngkm4KBqKb9sukPiA2ZLvadcP+Ie5AzGchzTzljtoOWhXprb13W+qvVIbSc+EqhVCtCk7hBgcV2Ngn0du1mg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792831; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VszhHwNY+TEImXBrF+yFJeC2jVP2XDNODgOkO3kVRw0=; b=nJSbrbv5i1XovxMfiKvduZPiBhGOkvTmZx/PHUlvFWwuvSHSF4oYgGNwJcBNIqkts597vBdZPCtvrJ/cCUf0Ktftm5R+pOkBSQ3oTZJ8E3AkyWy0fUPNA8hz/xFSAldElxjHCkMB0pu5P31cWXALcQwdLoOGrJ5aveeUZ5kBlSQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168379283174857.2070575002781; Thu, 11 May 2023 01:13:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Ix-0007EV-GS; Thu, 11 May 2023 04:05:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Id-0006Pw-73 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:19 -0400 Received: from mail-ej1-x62a.google.com ([2a00:1450:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IT-0000za-GE for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:18 -0400 Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-956ff2399b1so1555122566b.3 for ; Thu, 11 May 2023 01:05:06 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792305; x=1686384305; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VszhHwNY+TEImXBrF+yFJeC2jVP2XDNODgOkO3kVRw0=; b=Vs7IRTC4RMN6uC1WVgpvHSDhF5hX6cjRT1NnpA5JkmD/L4BnIueV9N2b62C5DNRiAt 4TOu2OexOOrdCs2Q7EJDXq5cPrcbQFAqhEmoYEcuoGCvBxsCxbcX4qpQ1IcSTDW9h6Lv HP3n5WBb2fYowaa2UeM8GY9CXGLstca6TayWjprBiI/A2zN6GphbZfZhiRLXoFcMZRed p9DYJZUt+SQL5lDyEjuS2F0p6DQ/QcKe/xVa78YqW6cuiWs5YhO+CDjGFl3qhpXhxGja s7xWUbkE23nhaRQrpIo3ItpQ/JPdo7qwGEqXPSJ5YNg3AuTlZ6J6F4qTEFvaJ8OYe7DM 8LlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792305; x=1686384305; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VszhHwNY+TEImXBrF+yFJeC2jVP2XDNODgOkO3kVRw0=; b=LTHvzw7CB1S+VHqjNolCoxg8SDJA3UHKEjcK7tKJ83R5ILwGewBhKdTxYv46uc1Ng2 pokedeqaiQ2Mi5WgjrT8bAcYaiflkm9ZAGZjpTBx5BK1puLl5t3kgHxeO+6coVtVerc5 6rdms/6Ia1ypLnXZsTTlD44jmZ49kjaHfHgYWKw9O5K4Z0Ttm75r270/YES8HdrxbAsI FLS25lpjmpL4VS97zHzMnsZXi2LiLGEtTYDnLI+nP1ndarBmmyQqRhDza2bQZEo3RvcM Fb/wL8aoPAoEhYBfCBwOJQyX3G68Y1Dw/5TLXaj+e43UzvKzuwDUXu5fSarFoqUHxjW/ uNOw== X-Gm-Message-State: AC+VfDw5X/N6ifSr0rDRKVZRFTqe/efBdBYiPIE1omj+OU10/A/NunGt jt0TPhoEtQuJb2C+Nnh0RpBwNqxOsbfvn9rIuNR22Q== X-Google-Smtp-Source: ACHHUZ7fWmZ+QwCe22RaDiyyKZS3f+eVQTWTWthZFZgMXiEUYp0hbP/QOXf4SO5zizVe4XjT5zGPgg== X-Received: by 2002:a17:907:70e:b0:965:6199:cf60 with SMTP id xb14-20020a170907070e00b009656199cf60mr18117930ejb.42.1683792305359; Thu, 11 May 2023 01:05:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 20/53] tcg: Add routines for calling slow-path helpers Date: Thu, 11 May 2023 09:04:17 +0100 Message-Id: <20230511080450.860923-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792832412100003 Add tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. These and their subroutines use the existing knowledge of the host function call abi to load the function call arguments and return results. These will be used to simplify the backends in turn. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/tcg.c | 475 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 471 insertions(+), 4 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 057423c121..88fe01f59f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -181,6 +181,22 @@ static bool tcg_target_const_match(int64_t val, TCGTyp= e type, int ct); static int tcg_out_ldst_finalize(TCGContext *s); #endif =20 +typedef struct TCGLdstHelperParam { + TCGReg (*ra_gen)(TCGContext *s, const TCGLabelQemuLdst *l, int arg_reg= ); + unsigned ntmp; + int tmp[3]; +} TCGLdstHelperParam; + +static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *= l, + const TCGLdstHelperParam *p) + __attribute__((unused)); +static void tcg_out_ld_helper_ret(TCGContext *s, const TCGLabelQemuLdst *l, + bool load_sign, const TCGLdstHelperParam= *p) + __attribute__((unused)); +static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *= l, + const TCGLdstHelperParam *p) + __attribute__((unused)); + TCGContext tcg_init_ctx; __thread TCGContext *tcg_ctx; =20 @@ -366,8 +382,17 @@ void tcg_raise_tb_overflow(TCGContext *s) siglongjmp(s->jmp_trans, -2); } =20 +/* + * Used by tcg_out_movext{1,2} to hold the arguments for tcg_out_movext. + * By the time we arrive at tcg_out_movext1, @dst is always a TCGReg. + * + * However, tcg_out_helper_load_slots reuses this field to hold an + * argument slot number (which may designate a argument register or an + * argument stack slot), converting to TCGReg once all arguments that + * are destined for the stack are processed. + */ typedef struct TCGMovExtend { - TCGReg dst; + unsigned dst; TCGReg src; TCGType dst_type; TCGType src_type; @@ -459,9 +484,8 @@ static void tcg_out_movext1(TCGContext *s, const TCGMov= Extend *i) * between the sources and destinations. */ =20 -static void __attribute__((unused)) -tcg_out_movext2(TCGContext *s, const TCGMovExtend *i1, - const TCGMovExtend *i2, int scratch) +static void tcg_out_movext2(TCGContext *s, const TCGMovExtend *i1, + const TCGMovExtend *i2, int scratch) { TCGReg src1 =3D i1->src; TCGReg src2 =3D i2->src; @@ -715,6 +739,58 @@ static TCGHelperInfo all_helpers[] =3D { }; static GHashTable *helper_table; =20 +/* + * Create TCGHelperInfo structures for "tcg/tcg-ldst.h" functions, + * akin to what "exec/helper-tcg.h" does with DEF_HELPER_FLAGS_N. + * We only use these for layout in tcg_out_ld_helper_ret and + * tcg_out_st_helper_args, and share them between several of + * the helpers, with the end result that it's easier to build manually. + */ + +#if TCG_TARGET_REG_BITS =3D=3D 32 +# define dh_typecode_ttl dh_typecode_i32 +#else +# define dh_typecode_ttl dh_typecode_i64 +#endif + +static TCGHelperInfo info_helper_ld32_mmu =3D { + .flags =3D TCG_CALL_NO_WG, + .typemask =3D dh_typemask(ttl, 0) /* return tcg_target_ulong */ + | dh_typemask(env, 1) + | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i32, 3) /* unsigned oi */ + | dh_typemask(ptr, 4) /* uintptr_t ra */ +}; + +static TCGHelperInfo info_helper_ld64_mmu =3D { + .flags =3D TCG_CALL_NO_WG, + .typemask =3D dh_typemask(i64, 0) /* return uint64_t */ + | dh_typemask(env, 1) + | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i32, 3) /* unsigned oi */ + | dh_typemask(ptr, 4) /* uintptr_t ra */ +}; + +static TCGHelperInfo info_helper_st32_mmu =3D { + .flags =3D TCG_CALL_NO_WG, + .typemask =3D dh_typemask(void, 0) + | dh_typemask(env, 1) + | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i32, 3) /* uint32_t data */ + | dh_typemask(i32, 4) /* unsigned oi */ + | dh_typemask(ptr, 5) /* uintptr_t ra */ +}; + +static TCGHelperInfo info_helper_st64_mmu =3D { + .flags =3D TCG_CALL_NO_WG, + .typemask =3D dh_typemask(void, 0) + | dh_typemask(env, 1) + | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i64, 3) /* uint64_t data */ + | dh_typemask(i32, 4) /* unsigned oi */ + | dh_typemask(ptr, 5) /* uintptr_t ra */ +}; + #ifdef CONFIG_TCG_INTERPRETER static ffi_type *typecode_to_ffi(int argmask) { @@ -1126,6 +1202,11 @@ static void tcg_context_init(unsigned max_cpus) (gpointer)&all_helpers[i]); } =20 + init_call_layout(&info_helper_ld32_mmu); + init_call_layout(&info_helper_ld64_mmu); + init_call_layout(&info_helper_st32_mmu); + init_call_layout(&info_helper_st64_mmu); + #ifdef CONFIG_TCG_INTERPRETER init_ffi_layouts(); #endif @@ -5011,6 +5092,392 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp= *op) } } =20 +/* + * Similarly for qemu_ld/st slow path helpers. + * We must re-implement tcg_gen_callN and tcg_reg_alloc_call simultaneousl= y, + * using only the provided backend tcg_out_* functions. + */ + +static int tcg_out_helper_stk_ofs(TCGType type, unsigned slot) +{ + int ofs =3D arg_slot_stk_ofs(slot); + + /* + * Each stack slot is TCG_TARGET_LONG_BITS. If the host does not + * require extension to uint64_t, adjust the address for uint32_t. + */ + if (HOST_BIG_ENDIAN && + TCG_TARGET_REG_BITS =3D=3D 64 && + type =3D=3D TCG_TYPE_I32) { + ofs +=3D 4; + } + return ofs; +} + +static void tcg_out_helper_load_regs(TCGContext *s, + unsigned nmov, TCGMovExtend *mov, + unsigned ntmp, const int *tmp) +{ + switch (nmov) { + default: + /* The backend must have provided enough temps for the worst case.= */ + tcg_debug_assert(ntmp + 1 >=3D nmov); + + for (unsigned i =3D nmov - 1; i >=3D 2; --i) { + TCGReg dst =3D mov[i].dst; + + for (unsigned j =3D 0; j < i; ++j) { + if (dst =3D=3D mov[j].src) { + /* + * Conflict. + * Copy the source to a temporary, recurse for the + * remaining moves, perform the extension from our + * scratch on the way out. + */ + TCGReg scratch =3D tmp[--ntmp]; + tcg_out_mov(s, mov[i].src_type, scratch, mov[i].src); + mov[i].src =3D scratch; + + tcg_out_helper_load_regs(s, i, mov, ntmp, tmp); + tcg_out_movext1(s, &mov[i]); + return; + } + } + + /* No conflicts: perform this move and continue. */ + tcg_out_movext1(s, &mov[i]); + } + /* fall through for the final two moves */ + + case 2: + tcg_out_movext2(s, mov, mov + 1, ntmp ? tmp[0] : -1); + return; + case 1: + tcg_out_movext1(s, mov); + return; + case 0: + g_assert_not_reached(); + } +} + +static void tcg_out_helper_load_slots(TCGContext *s, + unsigned nmov, TCGMovExtend *mov, + const TCGLdstHelperParam *parm) +{ + unsigned i; + + /* + * Start from the end, storing to the stack first. + * This frees those registers, so we need not consider overlap. + */ + for (i =3D nmov; i-- > 0; ) { + unsigned slot =3D mov[i].dst; + + if (arg_slot_reg_p(slot)) { + goto found_reg; + } + + TCGReg src =3D mov[i].src; + TCGType dst_type =3D mov[i].dst_type; + MemOp dst_mo =3D dst_type =3D=3D TCG_TYPE_I32 ? MO_32 : MO_64; + + /* The argument is going onto the stack; extend into scratch. */ + if ((mov[i].src_ext & MO_SIZE) !=3D dst_mo) { + tcg_debug_assert(parm->ntmp !=3D 0); + mov[i].dst =3D src =3D parm->tmp[0]; + tcg_out_movext1(s, &mov[i]); + } + + tcg_out_st(s, dst_type, src, TCG_REG_CALL_STACK, + tcg_out_helper_stk_ofs(dst_type, slot)); + } + return; + + found_reg: + /* + * The remaining arguments are in registers. + * Convert slot numbers to argument registers. + */ + nmov =3D i + 1; + for (i =3D 0; i < nmov; ++i) { + mov[i].dst =3D tcg_target_call_iarg_regs[mov[i].dst]; + } + tcg_out_helper_load_regs(s, nmov, mov, parm->ntmp, parm->tmp); +} + +static void tcg_out_helper_load_imm(TCGContext *s, unsigned slot, + TCGType type, tcg_target_long imm, + const TCGLdstHelperParam *parm) +{ + if (arg_slot_reg_p(slot)) { + tcg_out_movi(s, type, tcg_target_call_iarg_regs[slot], imm); + } else { + int ofs =3D tcg_out_helper_stk_ofs(type, slot); + if (!tcg_out_sti(s, type, imm, TCG_REG_CALL_STACK, ofs)) { + tcg_debug_assert(parm->ntmp !=3D 0); + tcg_out_movi(s, type, parm->tmp[0], imm); + tcg_out_st(s, type, parm->tmp[0], TCG_REG_CALL_STACK, ofs); + } + } +} + +static void tcg_out_helper_load_common_args(TCGContext *s, + const TCGLabelQemuLdst *ldst, + const TCGLdstHelperParam *parm, + const TCGHelperInfo *info, + unsigned next_arg) +{ + TCGMovExtend ptr_mov =3D { + .dst_type =3D TCG_TYPE_PTR, + .src_type =3D TCG_TYPE_PTR, + .src_ext =3D sizeof(void *) =3D=3D 4 ? MO_32 : MO_64 + }; + const TCGCallArgumentLoc *loc =3D &info->in[0]; + TCGType type; + unsigned slot; + tcg_target_ulong imm; + + /* + * Handle env, which is always first. + */ + ptr_mov.dst =3D loc->arg_slot; + ptr_mov.src =3D TCG_AREG0; + tcg_out_helper_load_slots(s, 1, &ptr_mov, parm); + + /* + * Handle oi. + */ + imm =3D ldst->oi; + loc =3D &info->in[next_arg]; + type =3D TCG_TYPE_I32; + switch (loc->kind) { + case TCG_CALL_ARG_NORMAL: + break; + case TCG_CALL_ARG_EXTEND_U: + case TCG_CALL_ARG_EXTEND_S: + /* No extension required for MemOpIdx. */ + tcg_debug_assert(imm <=3D INT32_MAX); + type =3D TCG_TYPE_REG; + break; + default: + g_assert_not_reached(); + } + tcg_out_helper_load_imm(s, loc->arg_slot, type, imm, parm); + next_arg++; + + /* + * Handle ra. + */ + loc =3D &info->in[next_arg]; + slot =3D loc->arg_slot; + if (parm->ra_gen) { + int arg_reg =3D -1; + TCGReg ra_reg; + + if (arg_slot_reg_p(slot)) { + arg_reg =3D tcg_target_call_iarg_regs[slot]; + } + ra_reg =3D parm->ra_gen(s, ldst, arg_reg); + + ptr_mov.dst =3D slot; + ptr_mov.src =3D ra_reg; + tcg_out_helper_load_slots(s, 1, &ptr_mov, parm); + } else { + imm =3D (uintptr_t)ldst->raddr; + tcg_out_helper_load_imm(s, slot, TCG_TYPE_PTR, imm, parm); + } +} + +static unsigned tcg_out_helper_add_mov(TCGMovExtend *mov, + const TCGCallArgumentLoc *loc, + TCGType dst_type, TCGType src_type, + TCGReg lo, TCGReg hi) +{ + if (dst_type <=3D TCG_TYPE_REG) { + MemOp src_ext; + + switch (loc->kind) { + case TCG_CALL_ARG_NORMAL: + src_ext =3D src_type =3D=3D TCG_TYPE_I32 ? MO_32 : MO_64; + break; + case TCG_CALL_ARG_EXTEND_U: + dst_type =3D TCG_TYPE_REG; + src_ext =3D MO_UL; + break; + case TCG_CALL_ARG_EXTEND_S: + dst_type =3D TCG_TYPE_REG; + src_ext =3D MO_SL; + break; + default: + g_assert_not_reached(); + } + + mov[0].dst =3D loc->arg_slot; + mov[0].dst_type =3D dst_type; + mov[0].src =3D lo; + mov[0].src_type =3D src_type; + mov[0].src_ext =3D src_ext; + return 1; + } + + assert(TCG_TARGET_REG_BITS =3D=3D 32); + + mov[0].dst =3D loc[HOST_BIG_ENDIAN].arg_slot; + mov[0].src =3D lo; + mov[0].dst_type =3D TCG_TYPE_I32; + mov[0].src_type =3D TCG_TYPE_I32; + mov[0].src_ext =3D MO_32; + + mov[1].dst =3D loc[!HOST_BIG_ENDIAN].arg_slot; + mov[1].src =3D hi; + mov[1].dst_type =3D TCG_TYPE_I32; + mov[1].src_type =3D TCG_TYPE_I32; + mov[1].src_ext =3D MO_32; + + return 2; +} + +static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *= ldst, + const TCGLdstHelperParam *parm) +{ + const TCGHelperInfo *info; + const TCGCallArgumentLoc *loc; + TCGMovExtend mov[2]; + unsigned next_arg, nmov; + MemOp mop =3D get_memop(ldst->oi); + + switch (mop & MO_SIZE) { + case MO_8: + case MO_16: + case MO_32: + info =3D &info_helper_ld32_mmu; + break; + case MO_64: + info =3D &info_helper_ld64_mmu; + break; + default: + g_assert_not_reached(); + } + + /* Defer env argument. */ + next_arg =3D 1; + + loc =3D &info->in[next_arg]; + nmov =3D tcg_out_helper_add_mov(mov, loc, TCG_TYPE_TL, TCG_TYPE_TL, + ldst->addrlo_reg, ldst->addrhi_reg); + next_arg +=3D nmov; + + tcg_out_helper_load_slots(s, nmov, mov, parm); + + /* No special attention for 32 and 64-bit return values. */ + tcg_debug_assert(info->out_kind =3D=3D TCG_CALL_RET_NORMAL); + + tcg_out_helper_load_common_args(s, ldst, parm, info, next_arg); +} + +static void tcg_out_ld_helper_ret(TCGContext *s, const TCGLabelQemuLdst *l= dst, + bool load_sign, + const TCGLdstHelperParam *parm) +{ + TCGMovExtend mov[2]; + + if (ldst->type <=3D TCG_TYPE_REG) { + MemOp mop =3D get_memop(ldst->oi); + + mov[0].dst =3D ldst->datalo_reg; + mov[0].src =3D tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, 0); + mov[0].dst_type =3D ldst->type; + mov[0].src_type =3D TCG_TYPE_REG; + + /* + * If load_sign, then we allowed the helper to perform the + * appropriate sign extension to tcg_target_ulong, and all + * we need now is a plain move. + * + * If they do not, then we expect the relevant extension + * instruction to be no more expensive than a move, and + * we thus save the icache etc by only using one of two + * helper functions. + */ + if (load_sign || !(mop & MO_SIGN)) { + if (TCG_TARGET_REG_BITS =3D=3D 32 || ldst->type =3D=3D TCG_TYP= E_I32) { + mov[0].src_ext =3D MO_32; + } else { + mov[0].src_ext =3D MO_64; + } + } else { + mov[0].src_ext =3D mop & MO_SSIZE; + } + tcg_out_movext1(s, mov); + } else { + assert(TCG_TARGET_REG_BITS =3D=3D 32); + + mov[0].dst =3D ldst->datalo_reg; + mov[0].src =3D + tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, HOST_BIG_ENDIAN); + mov[0].dst_type =3D TCG_TYPE_I32; + mov[0].src_type =3D TCG_TYPE_I32; + mov[0].src_ext =3D MO_32; + + mov[1].dst =3D ldst->datahi_reg; + mov[1].src =3D + tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, !HOST_BIG_ENDIAN= ); + mov[1].dst_type =3D TCG_TYPE_REG; + mov[1].src_type =3D TCG_TYPE_REG; + mov[1].src_ext =3D MO_32; + + tcg_out_movext2(s, mov, mov + 1, parm->ntmp ? parm->tmp[0] : -1); + } +} + +static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *= ldst, + const TCGLdstHelperParam *parm) +{ + const TCGHelperInfo *info; + const TCGCallArgumentLoc *loc; + TCGMovExtend mov[4]; + TCGType data_type; + unsigned next_arg, nmov, n; + MemOp mop =3D get_memop(ldst->oi); + + switch (mop & MO_SIZE) { + case MO_8: + case MO_16: + case MO_32: + info =3D &info_helper_st32_mmu; + data_type =3D TCG_TYPE_I32; + break; + case MO_64: + info =3D &info_helper_st64_mmu; + data_type =3D TCG_TYPE_I64; + break; + default: + g_assert_not_reached(); + } + + /* Defer env argument. */ + next_arg =3D 1; + nmov =3D 0; + + /* Handle addr argument. */ + loc =3D &info->in[next_arg]; + n =3D tcg_out_helper_add_mov(mov, loc, TCG_TYPE_TL, TCG_TYPE_TL, + ldst->addrlo_reg, ldst->addrhi_reg); + next_arg +=3D n; + nmov +=3D n; + + /* Handle data argument. */ + loc =3D &info->in[next_arg]; + n =3D tcg_out_helper_add_mov(mov + nmov, loc, data_type, ldst->type, + ldst->datalo_reg, ldst->datahi_reg); + next_arg +=3D n; + nmov +=3D n; + tcg_debug_assert(nmov <=3D ARRAY_SIZE(mov)); + + tcg_out_helper_load_slots(s, nmov, mov, parm); + tcg_out_helper_load_common_args(s, ldst, parm, info, next_arg); +} + #ifdef CONFIG_PROFILER =20 /* avoid copy/paste errors */ --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792741; cv=none; d=zohomail.com; s=zohoarc; b=RHMghhVLz3CdYiN1Otvq28rwhfSnMRPJ8gLRXuDUTNQY33RAJGa+q6WfopjN7rZCRrCj0RykWAog1pzZIDcYnq7ZNpWeTR/7tPwk8ICWIyFhP+S+w9xJ54I0eCh/1g2o/R2kbhhmdCpYgJaGqtk7scAXpiuvl6uTmAjXNg7a19A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792741; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=S8RtnewBREelRk2wvCU4YAc0w9WRx08DJdvjsASE20Q=; b=YJJvg1XcFUdRkByKPcd3xwkp6Zz+UpyOj46wva5FcwlMeDt1ppBoewmr+DAGvOTSoHSex2Ypku1BUcNvQHbEtWYMMznPCR5/1OnSGxfdr6qJ39rng1SKc9Pval4Leee0+q7tJzI89XkT2+a0xtMaLxHHR7RFFI61N8nAc1EXR+w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792741307487.03254873701553; Thu, 11 May 2023 01:12:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Ie-0006Qg-2l; Thu, 11 May 2023 04:05:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1IY-0006NJ-EG for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:14 -0400 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IS-0000zg-DD for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:14 -0400 Received: by mail-ed1-x52a.google.com with SMTP id 4fb4d7f45d1cf-50bd2d7ba74so76559232a12.1 for ; Thu, 11 May 2023 01:05:06 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792306; x=1686384306; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=S8RtnewBREelRk2wvCU4YAc0w9WRx08DJdvjsASE20Q=; b=tpygpO37QElwBX5gE0YQ4dJsGUEFXic8/ywVaCVjCeIxhz3yso5Zva+gOx/+xYZZG7 Ld877EN1hqA+lW4XsazmgZhqnLJWeeBmFZpQr9E/nESMNXZaGNbINbcX/Ywv4SBZjIqE n02v+cgnEvHwWPkH566/+Nz84QIfyxqgL2Rmovk4KrI5EB43G9bG3/xQ5E6Lv1vMsJpd j16WkaKfZgRVFgJIYQhw16+B2hyxgq/fHravnG4r/ANqhb7SlS2XGHm5VRdTRIbkhWSY jGY2c0Ul+IotM4vIqS7btJRNA7V3+1iagRv2UwQycJMNJmVINjyx821JrHFjtJwjmie4 GoxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792306; x=1686384306; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S8RtnewBREelRk2wvCU4YAc0w9WRx08DJdvjsASE20Q=; b=J02aHkmTv/vVJV71CeTyhUQOjNqrMegcKGmGbSdFL0S9Q8qc2gwbPKF/1nZnYDXQxK 4TTsIR+eR0XLByHIaph3f+hEfPpjlaDsTk3ssm/uu4FydwbmDrV6TN3/2+yyp0wxOddt LXr/G79OA46KmPnoXvrS46jkJZXcwZhNyTNmKomNVd7t7vpbcuA+NZADfGqyuE+Zrjvc F4vNrdNjHW8vijG17P98GRpePH8QUaF7X191cPDZmwpLiPTJ8X4ikc5UZM8tl8t6Hsa5 sN3am3p8/7KEj39bZUUc1sG7wP3Ct6tBXjQ+L8IB4UWbjQ0XTT1ynN68tzejeTZ44g26 grUw== X-Gm-Message-State: AC+VfDx/bdqDdHWv1WQoZQoDBvExil8bk2xAe1cit6fQybBlnlmGDE7b 2pz+UJPSOgkKwHWFWnfcsfhH/V+9Qg23h43rnjOm+g== X-Google-Smtp-Source: ACHHUZ4OUeS0tEQ/LJVJQXdYgW9Do7nj9AJCJzmlcKCFvCCbRugX4D9NytbDxKMLYr9POIiMZi0V2A== X-Received: by 2002:a05:6402:510d:b0:506:94db:f4fb with SMTP id m13-20020a056402510d00b0050694dbf4fbmr15228541edd.20.1683792305975; Thu, 11 May 2023 01:05:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 21/53] tcg/i386: Convert tcg_out_qemu_ld_slow_path Date: Thu, 11 May 2023 09:04:18 +0100 Message-Id: <20230511080450.860923-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792743367100003 Use tcg_out_ld_helper_args and tcg_out_ld_helper_ret. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 71 +++++++++++++++------------------------ 1 file changed, 28 insertions(+), 43 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 18b0e7997d..3508b9cc6c 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1802,13 +1802,37 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_B= SWAP) + 1] =3D { [MO_BEUQ] =3D helper_be_stq_mmu, }; =20 +/* + * Because i686 has no register parameters and because x86_64 has xchg + * to handle addr/data register overlap, we have placed all input arguments + * before we need might need a scratch reg. + * + * Even then, a scratch is only needed for l->raddr. Rather than expose + * a general-purpose scratch when we don't actually know it's available, + * use the ra_gen hook to load into RAX if needed. + */ +#if TCG_TARGET_REG_BITS =3D=3D 64 +static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int ar= g) +{ + if (arg < 0) { + arg =3D TCG_REG_RAX; + } + tcg_out_movi(s, TCG_TYPE_PTR, arg, (uintptr_t)l->raddr); + return arg; +} +static const TCGLdstHelperParam ldst_helper_param =3D { + .ra_gen =3D ldst_ra_gen +}; +#else +static const TCGLdstHelperParam ldst_helper_param =3D { }; +#endif + /* * Generate code for the slow path for a load at the end of block */ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(l->oi); tcg_insn_unit **label_ptr =3D &l->label_ptr[0]; =20 /* resolve label address */ @@ -1817,49 +1841,10 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); } =20 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - int ofs =3D 0; - - tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); - ofs +=3D 4; - - tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - } - - tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs); - ofs +=3D 4; - - tcg_out_sti(s, TCG_TYPE_PTR, (uintptr_t)l->raddr, TCG_REG_ESP, ofs= ); - } else { - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); - tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], - l->addrlo_reg); - tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], oi); - tcg_out_movi(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[3], - (uintptr_t)l->raddr); - } - + tcg_out_ld_helper_args(s, l, &ldst_helper_param); tcg_out_branch(s, 1, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param); =20 - if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { - TCGMovExtend ext[2] =3D { - { .dst =3D l->datalo_reg, .dst_type =3D TCG_TYPE_I32, - .src =3D TCG_REG_EAX, .src_type =3D TCG_TYPE_I32, .src_ext = =3D MO_UL }, - { .dst =3D l->datahi_reg, .dst_type =3D TCG_TYPE_I32, - .src =3D TCG_REG_EDX, .src_type =3D TCG_TYPE_I32, .src_ext = =3D MO_UL }, - }; - tcg_out_movext2(s, &ext[0], &ext[1], -1); - } else { - tcg_out_movext(s, l->type, l->datalo_reg, - TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_EAX); - } - - /* Jump to the code corresponding to next IR of qemu_st */ tcg_out_jmp(s, l->raddr); return true; } --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792954; cv=none; d=zohomail.com; s=zohoarc; b=Seb4ZlIdaCVqo0dzonHBH3tQ2CPEDrGbZC9wybsWUhJJE4GAXMBLScq4c2Z9DSrOxOEzs0OlUIFnYtfRWcxNyiRcOaZkfp4zP2rH9yDnYiLW/3TtRbFbiJDnOMC/UzaybQ29kbwjad/cEGTay9kTp5qrxKPuguz0fNmnVE5b9+k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792954; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gGX1OvBPBJZ0dJTeWQA17dDEsVv5029y7NlB8JCmIAo=; b=OFQdqBMiM3Omu8Hc6OmrDu8tt2ZEt6JS6UlUF9j0mrbl4OzAQwlbZZCYahPFGtonad63Q3R7Bn0prvE6XYWHm+D7b8aVKwbll3cyLLBAoKKysKTsAgeN1GtibERTUBs5eK3E7mniOgeDhsFWsW1G5pkZ7PX0f8IB6X4xPLzr1YY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792954981776.9595397233709; Thu, 11 May 2023 01:15:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Is-00071s-7S; Thu, 11 May 2023 04:05:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Ib-0006PC-6s for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:17 -0400 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IT-0000zl-GB for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:16 -0400 Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-9659c5b14d8so1353011866b.3 for ; Thu, 11 May 2023 01:05:07 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792307; x=1686384307; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gGX1OvBPBJZ0dJTeWQA17dDEsVv5029y7NlB8JCmIAo=; b=sI/IRxR2ODrHpeebLZ6menmGfU2l1SS02AUjebBvw3+X8dHVSWTbS7l/ipjq/FDntp NtCEsmWNBifgPtEVxnWcEHvEwKII2ZG8GLvSLWAJ36TxdgPJCUuPS4tygpqk4HkoZWf1 4kpQdNNfG0o5+urs7vOZVzaaVnV/AODcznOBVcOaaMTQkFXwEDeqvvWtA0Hdv+epgQQm P8ehXY9aAr4ERNT5Pt1dUZ2eoQRZklLV5kpzPBSvu0QuHCjHI34+LJyL/wG+Dy8c7D8Y 0dDDMLunA7jys8JB10Ve64JJpYLR9eTzgFUY98LG2oOQgCSLAv/psAxJlg/ZoSEorTwc w4xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792307; x=1686384307; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gGX1OvBPBJZ0dJTeWQA17dDEsVv5029y7NlB8JCmIAo=; b=f0wj/WBf++ws0gRtVOvIbpgx3gu6GvLuo+dDi4Mv3FXRxuN8RY4ClkQ9Bsm1FWaW74 IgSpjTwDMNKiTBq2SYUj8MQhYeixmCXzICVGzJGWW9JS/8giWDWwAyqn6nQTg/lfn2/b Fkyu6wCuKBwPc75p96v0bc7Tb5FnDIdL7XaPsuYlBhmNph3DlUlIcTFmVcdA+X2K4lw4 dqOdHnzPioBHTtU1DNE6nXjSfpc5cyEzJr3Z8LtZPjIa/B02ZCKX3XQTfb9NACM6nNCu 2jcANlwpOw23EcXnHVDs/lMQS41CPVfXQSxgr8dGFpNYYUwtfsFolVt1cxvJ+ZHRTmTf 14lQ== X-Gm-Message-State: AC+VfDxFMdYya3NYU1MaohbGLMro67jrwDFS19REoubEUKt+c/NyS4m2 7U3LDwNJyf+lFiqX7pd3lU4Vz/eckH5jYbW6e/RCWw== X-Google-Smtp-Source: ACHHUZ5okSQXBFMGGqTFGsyMf/0pl+AEGe8HFVsxT/lZWKRoi64X7kF0BDyNZU5e4bPhRanrtCSPAw== X-Received: by 2002:a17:907:96a1:b0:966:a691:678d with SMTP id hd33-20020a17090796a100b00966a691678dmr13271605ejc.51.1683792306637; Thu, 11 May 2023 01:05:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 22/53] tcg/i386: Convert tcg_out_qemu_st_slow_path Date: Thu, 11 May 2023 09:04:19 +0100 Message-Id: <20230511080450.860923-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792955379100001 Use tcg_out_st_helper_args. This eliminates the use of a tail call to the store helper. This may or may not be an improvement, depending on the call/return branch prediction of the host microarchitecture. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 57 +++------------------------------------ 1 file changed, 4 insertions(+), 53 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 3508b9cc6c..a01bfad773 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1854,11 +1854,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) */ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; + MemOp opc =3D get_memop(l->oi); tcg_insn_unit **label_ptr =3D &l->label_ptr[0]; - TCGReg retaddr; =20 /* resolve label address */ tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); @@ -1866,56 +1863,10 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); } =20 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - int ofs =3D 0; + tcg_out_st_helper_args(s, l, &ldst_helper_param); + tcg_out_branch(s, 1, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 - tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); - ofs +=3D 4; - - tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - } - - tcg_out_st(s, TCG_TYPE_I32, l->datalo_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - - if (s_bits =3D=3D MO_64) { - tcg_out_st(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - } - - tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs); - ofs +=3D 4; - - retaddr =3D TCG_REG_EAX; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, ofs); - } else { - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); - tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], - l->addrlo_reg); - tcg_out_mov(s, (s_bits =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - tcg_target_call_iarg_regs[2], l->datalo_reg); - tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], oi); - - if (ARRAY_SIZE(tcg_target_call_iarg_regs) > 4) { - retaddr =3D tcg_target_call_iarg_regs[4]; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - } else { - retaddr =3D TCG_REG_RAX; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, - TCG_TARGET_CALL_STACK_OFFSET); - } - } - - /* "Tail call" to the helper, with the return address back inline. */ - tcg_out_push(s, retaddr); - tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_jmp(s, l->raddr); return true; } #else --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792397; cv=none; d=zohomail.com; s=zohoarc; b=WsgtdRHqiznutaRlC++ItaoIpTb6m+626MGHjM8fCAMaJbBDzjXkJIEl2Nt9ddOyrcGVyfhBi0IsvUiC9PFS/9A1et5ZJujt4Cuf1DJvyFsMufw0gBUrPKn8+h33OtHmEBpDc9VwEZaLJkLStcSHBVeqGtKUrqn/TaWIW+k3UVg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792397; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DNyOVYVbB6rri70d92kOlQalXLO+2p9TbN15kXr6tJA=; b=bemm2wGLF+cvr27gPBga6ej+8oqrYzSptt+A36icSY6h8B2G888d2DQLyWOv0/v4ze8XM5ieUPtequLRK8mlljbq05Yh0JPFzBA62MNBmPHlJNVlp+8XrUlVvx2TWp9jsg46C4CA3UNEyF57pYQfy2yw23oc5WCAZCpTPV1Ttd4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792397029679.0639445042607; Thu, 11 May 2023 01:06:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1JC-0007O6-Iy; Thu, 11 May 2023 04:05:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Il-0006eZ-CQ for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:27 -0400 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IS-0000zo-MR for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:27 -0400 Received: by mail-ed1-x529.google.com with SMTP id 4fb4d7f45d1cf-50bc1612940so15018016a12.2 for ; Thu, 11 May 2023 01:05:08 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792307; x=1686384307; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DNyOVYVbB6rri70d92kOlQalXLO+2p9TbN15kXr6tJA=; b=xHahpTdtWuXdysS3gElUpUmTw+jL081oZopLuFV+XcDKAzkAlTb6PpbDwp2RZQlRTE XMI9KTO86GRenDTLi02VuTYkAS+d6xDD+GR5GCyii+I6dJ+Uo4giHbWfi2LMP0zyHCv0 NSl0yqEhb9Ke4BPskK5ZpAt/w19ErJwyba+dRUmtcZndTkCm8U9wGKezKMnYekXhimUG qh0/iAM5SSuZvt346VF9J9Lr9s8/r/V/DZU+b7thjShxlsaPh0eFGozYQ7y3jwk4VHRg lYHKthWai/f5QbvVOtfi2aDp2EJ0KswmH2Nyct/V87gGxGewsJnKQIrelRUl7v5pke/g lA6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792307; x=1686384307; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DNyOVYVbB6rri70d92kOlQalXLO+2p9TbN15kXr6tJA=; b=PdZ2+MwuSCqhh6yzFo+Rulbhs7WkTFfbYrg7L1qya9VfSm/AvxIsdaujHYTBz29p+3 VSEpNy9YJ2VWFvakdq6b7fqWxN7u9A1jTDCzOv01MXr74dgMQinDiBkChVDgU5KKxf8W gq0fKBwR+1RQpAJvWtV8ye1BPuB1ERNe0wpa3EEP4y2UDBo61wV/4O5Q/eBZBTwo5iUK qvnuCNrDLvZJN1646/4cetvLtqovEXmhS1YXi9yv2xdPyutgwDRNaP2ogWs32zJyPoPU JO8dNxGYz7UU4xeVHt5Oc9fRq9ck7kqea8bqwjLhh/RKcv7lagjrUHnHtljInuTK2OKt LsPw== X-Gm-Message-State: AC+VfDywfyVmU6/8Jrz+Ssn02HDjSd8Hq518naLmQ0IwSz7HhYgVudYz avssUj0H7S4tHW6Z7Zot6l3WzvbhBRmqF70+8fdX1Q== X-Google-Smtp-Source: ACHHUZ5jxo5rfOMK5ZCFKEz98tChUI6jB69XOI4XQzmdAt9+oIUcqk0XMktsRb9VYB5WPs0kT2UR/g== X-Received: by 2002:a05:6402:10d7:b0:50d:bb87:2473 with SMTP id p23-20020a05640210d700b0050dbb872473mr6569472edu.1.1683792307242; Thu, 11 May 2023 01:05:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 23/53] tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path Date: Thu, 11 May 2023 09:04:20 +0100 Message-Id: <20230511080450.860923-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792398825100010 Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 40 +++++++++++++++--------------------- 1 file changed, 16 insertions(+), 24 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 202b90c001..62dd22d73c 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1580,13 +1580,6 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext,= TCGReg d, } } =20 -static void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target) -{ - ptrdiff_t offset =3D tcg_pcrel_diff(s, target); - tcg_debug_assert(offset =3D=3D sextract64(offset, 0, 21)); - tcg_out_insn(s, 3406, ADR, rd, offset); -} - typedef struct { TCGReg base; TCGReg index; @@ -1627,47 +1620,46 @@ static void * const qemu_st_helpers[MO_SIZE + 1] = =3D { #endif }; =20 +static const TCGLdstHelperParam ldst_helper_param =3D { + .ntmp =3D 1, .tmp =3D { TCG_REG_TMP } +}; + static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc19(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); - tcg_out_mov(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X1, lb->addrlo_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, oi); - tcg_out_adr(s, TCG_REG_X3, lb->raddr); + tcg_out_ld_helper_args(s, lb, &ldst_helper_param); tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); - - tcg_out_movext(s, lb->type, lb->datalo_reg, - TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_X0); + tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); tcg_out_goto(s, lb->raddr); return true; } =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); - MemOp size =3D opc & MO_SIZE; + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc19(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); - tcg_out_mov(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X1, lb->addrlo_reg); - tcg_out_mov(s, size =3D=3D MO_64, TCG_REG_X2, lb->datalo_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, oi); - tcg_out_adr(s, TCG_REG_X4, lb->raddr); + tcg_out_st_helper_args(s, lb, &ldst_helper_param); tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE]); tcg_out_goto(s, lb->raddr); return true; } #else +static void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target) +{ + ptrdiff_t offset =3D tcg_pcrel_diff(s, target); + tcg_debug_assert(offset =3D=3D sextract64(offset, 0, 21)); + tcg_out_insn(s, 3406, ADR, rd, offset); +} + static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { if (!reloc_pc19(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792942; cv=none; d=zohomail.com; s=zohoarc; b=NVWyGLY6ym7tnDYBn30wPyGRlQShdk/wSad3vrRQwtSzcFDMNm/VZLpW0MBhpTrkbGsJiqO27qTv4M9hMbHIaVMUVYMUEv/xF+Ynyu6a0DS6jgf5juUOKJ4X0QA9RJRlH4gvhQh/aM+CNm3CdrGy49EI+uKc5FEn4v7tKrVUD+s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792942; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UUj3/kyGKwpEpcvTwoB3ZHHrWxCfgrZwSxh+YB+l6ZQ=; b=ZJSnr09JDQPvs1PtNSpqRVutog7ZOWmAFIfDZyomGvIrSPdNn9dxhtahzegN2dCiDpfGFLq5/+01ghB2hXfHWc7evLf1I07+vVujfPwrm4O5A+//E0g68/33IOFFWX1YnbdnEeD4fBI3eyC/DteJ2yPseHycf4z3WpAhlE++9Vk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792942198626.891754129156; Thu, 11 May 2023 01:15:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Iu-00075S-DD; Thu, 11 May 2023 04:05:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Ij-0006Yp-O4 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:26 -0400 Received: from mail-ed1-x532.google.com ([2a00:1450:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IS-0000wG-MF for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:24 -0400 Received: by mail-ed1-x532.google.com with SMTP id 4fb4d7f45d1cf-50bcae898b2so14640989a12.0 for ; Thu, 11 May 2023 01:05:08 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792307; x=1686384307; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UUj3/kyGKwpEpcvTwoB3ZHHrWxCfgrZwSxh+YB+l6ZQ=; b=KHJ4T9M4xmhthrcy/ayLTlCpHcvYDMkIMO0CqvWz3so6441r+nRYhSDF87u66j5q4l 40SdaE1tws+7bEP1A46MI2vZT1wwk6SslwXULnBUV3TLtAgaAq/jGkLL9/1QVTI2amHh tU1ljwVhDK5R69aYeP6xxNLeRgR128zEx4r5LMGJp25NGdRpHRlTprOjn8YGhjYJm8T4 U1qNKPM3/JAREaEQZUM6n+0++blpC7yJQqyEZbS7Wpekk0kyQg3jxGbVOMA71F8gOTBN dLAMwmejQhDEX99Ld6iZBxv2uVom4zL7mFG7HakhSW5Mk2Ejb82H+L8Moq4hfHpRpf4S NWHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792307; x=1686384307; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UUj3/kyGKwpEpcvTwoB3ZHHrWxCfgrZwSxh+YB+l6ZQ=; b=QmWw6eupQ/FO3FPl27ZevFqRKqu0Q8txtazfoPqDMzPJePxxXiZvEUn9crNpmsxeqa ns5fA0fUaHX/WK2oddBdpHfutzoDtfuiKjS/ZtaPS87IV/IeoHj/0COBLrg7he1sylkY MRQCMoKv6tQgrGWFY4cWJZG8XyYD8Cer2XeIH/ymV/DmR9iU33mYevGHw6Gv5tJvO/Dl xZitrQHd3+9K/AyZQ47Z1IU2nyIS9X3DN+R7zsoBs59yIztFkpoaGhps++u4flv+yull 66AkeiTbYHk7dzl/vGNfM40faGYYfrK3wzmvymwjZwC/BBVFJo21QAFys8JUQBnM3ilu v8vA== X-Gm-Message-State: AC+VfDzBASOI2aQBWe3aAT8Ee8h97/ENbpWrktf4n1TSwMvJKCEUyeDJ 3cP7yfVU1Rv5Aup+BD0MnY1LSkrfmTH13MPkIZUEkg== X-Google-Smtp-Source: ACHHUZ4gR/sfRj69WsAkhlJme0R7UFtccBcqHXCioeNXQPAxxJ1Xq3gWgtI6KaqlHy9WL76f6zBZGw== X-Received: by 2002:aa7:d88f:0:b0:50b:c1e3:6f02 with SMTP id u15-20020aa7d88f000000b0050bc1e36f02mr16982018edq.21.1683792307732; Thu, 11 May 2023 01:05:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 24/53] tcg/arm: Convert tcg_out_qemu_{ld,st}_slow_path Date: Thu, 11 May 2023 09:04:21 +0100 Message-Id: <20230511080450.860923-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792943285100001 Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. This allows our local tcg_out_arg_* infrastructure to be removed. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 140 +++++---------------------------------- 1 file changed, 18 insertions(+), 122 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index c744512778..df514e56fc 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -690,8 +690,8 @@ tcg_out_ldrd_rwb(TCGContext *s, ARMCond cond, TCGReg rt= , TCGReg rn, TCGReg rm) tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 1); } =20 -static void tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, int imm8) +static void __attribute__((unused)) +tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); } @@ -969,28 +969,16 @@ static void tcg_out_ext8u(TCGContext *s, TCGReg rd, T= CGReg rn) tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff); } =20 -static void __attribute__((unused)) -tcg_out_ext8u_cond(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) -{ - tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff); -} - static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) { /* sxth */ tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn); } =20 -static void tcg_out_ext16u_cond(TCGContext *s, ARMCond cond, - TCGReg rd, TCGReg rn) -{ - /* uxth */ - tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn); -} - static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) { - tcg_out_ext16u_cond(s, COND_AL, rd, rn); + /* uxth */ + tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | (rd << 12) | rn); } =20 static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) @@ -1382,92 +1370,29 @@ static void * const qemu_st_helpers[MO_SIZE + 1] = =3D { #endif }; =20 -/* Helper routines for marshalling helper function arguments into - * the correct registers and stack. - * argreg is where we want to put this argument, arg is the argument itsel= f. - * Return value is the updated argreg ready for the next call. - * Note that argreg 0..3 is real registers, 4+ on stack. - * - * We provide routines for arguments which are: immediate, 32 bit - * value in register, 16 and 8 bit values in register (which must be zero - * extended before use) and 64 bit value in a lo:hi register pair. - */ -#define DEFINE_TCG_OUT_ARG(NAME, ARGTYPE, MOV_ARG, EXT_ARG) = \ -static TCGReg NAME(TCGContext *s, TCGReg argreg, ARGTYPE arg) = \ -{ = \ - if (argreg < 4) { = \ - MOV_ARG(s, COND_AL, argreg, arg); = \ - } else { = \ - int ofs =3D (argreg - 4) * 4; = \ - EXT_ARG; = \ - tcg_debug_assert(ofs + 4 <=3D TCG_STATIC_CALL_ARGS_SIZE); = \ - tcg_out_st32_12(s, COND_AL, arg, TCG_REG_CALL_STACK, ofs); = \ - } = \ - return argreg + 1; = \ -} - -DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32, uint32_t, tcg_out_movi32, - (tcg_out_movi32(s, COND_AL, TCG_REG_TMP, arg), arg =3D TCG_REG_TMP)) -DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8, TCGReg, tcg_out_ext8u_cond, - (tcg_out_ext8u_cond(s, COND_AL, TCG_REG_TMP, arg), arg =3D TCG_REG_TMP= )) -DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16, TCGReg, tcg_out_ext16u_cond, - (tcg_out_ext16u_cond(s, COND_AL, TCG_REG_TMP, arg), arg =3D TCG_REG_TM= P)) -DEFINE_TCG_OUT_ARG(tcg_out_arg_reg32, TCGReg, tcg_out_mov_reg, ) - -static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg, - TCGReg arglo, TCGReg arghi) +static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int ar= g) { - /* 64 bit arguments must go in even/odd register pairs - * and in 8-aligned stack slots. - */ - if (argreg & 1) { - argreg++; - } - if (argreg >=3D 4 && (arglo & 1) =3D=3D 0 && arghi =3D=3D arglo + 1) { - tcg_out_strd_8(s, COND_AL, arglo, - TCG_REG_CALL_STACK, (argreg - 4) * 4); - return argreg + 2; - } else { - argreg =3D tcg_out_arg_reg32(s, argreg, arglo); - argreg =3D tcg_out_arg_reg32(s, argreg, arghi); - return argreg; - } + /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */ + return TCG_REG_R14; } =20 +static const TCGLdstHelperParam ldst_helper_param =3D { + .ra_gen =3D ldst_ra_gen, + .ntmp =3D 1, + .tmp =3D { TCG_REG_TMP }, +}; + static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGReg argreg; - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - argreg =3D tcg_out_arg_reg32(s, TCG_REG_R0, TCG_AREG0); - if (TARGET_LONG_BITS =3D=3D 64) { - argreg =3D tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi= _reg); - } else { - argreg =3D tcg_out_arg_reg32(s, argreg, lb->addrlo_reg); - } - argreg =3D tcg_out_arg_imm32(s, argreg, oi); - argreg =3D tcg_out_arg_reg32(s, argreg, TCG_REG_R14); - - /* Use the canonical unsigned helpers and minimize icache usage. */ + tcg_out_ld_helper_args(s, lb, &ldst_helper_param); tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); - - if ((opc & MO_SIZE) =3D=3D MO_64) { - TCGMovExtend ext[2] =3D { - { .dst =3D lb->datalo_reg, .dst_type =3D TCG_TYPE_I32, - .src =3D TCG_REG_R0, .src_type =3D TCG_TYPE_I32, .src_ext = =3D MO_UL }, - { .dst =3D lb->datahi_reg, .dst_type =3D TCG_TYPE_I32, - .src =3D TCG_REG_R1, .src_type =3D TCG_TYPE_I32, .src_ext = =3D MO_UL }, - }; - tcg_out_movext2(s, &ext[0], &ext[1], TCG_REG_TMP); - } else { - tcg_out_movext(s, TCG_TYPE_I32, lb->datalo_reg, - TCG_TYPE_I32, opc & MO_SSIZE, TCG_REG_R0); - } + tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); =20 tcg_out_goto(s, COND_AL, lb->raddr); return true; @@ -1475,42 +1400,13 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGReg argreg, datalo, datahi; - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - argreg =3D TCG_REG_R0; - argreg =3D tcg_out_arg_reg32(s, argreg, TCG_AREG0); - if (TARGET_LONG_BITS =3D=3D 64) { - argreg =3D tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi= _reg); - } else { - argreg =3D tcg_out_arg_reg32(s, argreg, lb->addrlo_reg); - } - - datalo =3D lb->datalo_reg; - datahi =3D lb->datahi_reg; - switch (opc & MO_SIZE) { - case MO_8: - argreg =3D tcg_out_arg_reg8(s, argreg, datalo); - break; - case MO_16: - argreg =3D tcg_out_arg_reg16(s, argreg, datalo); - break; - case MO_32: - default: - argreg =3D tcg_out_arg_reg32(s, argreg, datalo); - break; - case MO_64: - argreg =3D tcg_out_arg_reg64(s, argreg, datalo, datahi); - break; - } - - argreg =3D tcg_out_arg_imm32(s, argreg, oi); - argreg =3D tcg_out_arg_reg32(s, argreg, TCG_REG_R14); + tcg_out_st_helper_args(s, lb, &ldst_helper_param); =20 /* Tail-call to the helper, which will return to the fast path. */ tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792709; cv=none; d=zohomail.com; s=zohoarc; b=RiY+h+tmUBW6Isu8/NQN25aUH32ZedBMmORugC/38+9PdEiYAO85lTNSo8A+M1uEDifo4p4TW2FMmv5laiUH7IpKkSBGy7Ks1bZ58pjs5C93d0z8mYasIDAYOoTMP/z5Y3vafkGczNb32UqH+8FJHPteckJCKEssSHxfIyyLfR0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792709; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QD1cfplkf+/IZwEsl1xHBR+T6wK07Cr9vNJTvgqMw3Y=; b=YhAmaZ2dZ2x1gBq6noWxf46InOq4Q099qvzDHyZGFeer/EM4bqjmw5NKriOmqLhDjzVFquHEkeyJqtx8KEMSlBfHoBg8QUocM3Qb95J8he1ZyAiyoI70ZBMbNWs4ZVS+lDnkDjnb8LSNfLe3+Ij1clQED1gd9q3o/a/ihbEdqGQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792709869436.1340429775596; Thu, 11 May 2023 01:11:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Ip-0006mv-4Y; Thu, 11 May 2023 04:05:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Ib-0006PK-LX for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:17 -0400 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IU-0000wF-Dg for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:17 -0400 Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-50bcb4a81ceso14613456a12.2 for ; Thu, 11 May 2023 01:05:08 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792308; x=1686384308; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QD1cfplkf+/IZwEsl1xHBR+T6wK07Cr9vNJTvgqMw3Y=; b=Bq3V9m833qx+cQJhZXR00GsloJe1rd9yiq3Wo4i5lbs0J/GP8kUC5x5Hu9yTL5c070 IW+cYCXR/IIwmaycSL+C16xsNv2eDFxTX454T05kVyiuXTouinGbqBhW/mdvlPz5oZVG TdUw8AmU0as08J0Tc4cfWoj+hua99g2YleXuUuHHUnFJTWHBxi1WzT2iZrjp/4akJk+O B8R7cR/XrmXlFrNqIW8eVTUYXaAW1ToG1Lo6bmiPt2C3lxx4ojR6NE6a3kCyRwDut5EV QnGKxpog7DuLd+7GABV/6ZKUxYj9rre+aLtUp4YKwK3FZqu/4IPDWWoUJBA8TLWHShQF RIvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792308; x=1686384308; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QD1cfplkf+/IZwEsl1xHBR+T6wK07Cr9vNJTvgqMw3Y=; b=ZeOATaQ/vEDEU3LDk4+e4/XYwkC8VjXj08ikFVVpqcmrIuYr9lXFBC67ENLm5Sz21X hL49xlgz2h/0sHxLbnsroaRk1dIvawl+9fh0slfn+0lUBrPcRAAnnTeu6mew78Iwohf4 G76KDCVwjn28AtZUlyen7634KeZ+fhM7hHAbui80vS3Ekh9fNauGxMHpi+gNtKv/+PHh vpjF2+2E84sffN3bjr5MbW18QtBI6Yev2mxBxCeK09U5zTAiIKCrShI3C7PIHfRELfF/ yrkQrQPp9toy3JnBfzYWJ5uRddn67urpqBPFszkeYxFztiYvTXFmLxAn1RGm6Z5wKJvR UfQw== X-Gm-Message-State: AC+VfDxBGPaxrDrVMEPPr0G6QiR++oqlmb31maDd0FD2Px7+2WjEXb3y vfkS5fKl5HDfPQ664aqfl8wFYSne6JonYm1GPocl9A== X-Google-Smtp-Source: ACHHUZ4K+r1OoH/qhu8rfjqXw9d7NaCOp0TY626YM/y6y+39UVpCCC7VKq2vUh8sBCyo8TdaOA1xxg== X-Received: by 2002:a05:6402:517b:b0:4fa:b302:84d4 with SMTP id d27-20020a056402517b00b004fab30284d4mr16746120ede.13.1683792308238; Thu, 11 May 2023 01:05:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 25/53] tcg/loongarch64: Convert tcg_out_qemu_{ld,st}_slow_path Date: Thu, 11 May 2023 09:04:22 +0100 Message-Id: <20230511080450.860923-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792711305100001 Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 37 ++++++++++---------------------- 1 file changed, 11 insertions(+), 26 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 2f2c34b930..60d2c904dd 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -824,51 +824,36 @@ static bool tcg_out_goto(TCGContext *s, const tcg_ins= n_unit *target) return reloc_br_sd10k16(s->code_ptr - 1, target); } =20 +static const TCGLdstHelperParam ldst_helper_param =3D { + .ntmp =3D 1, .tmp =3D { TCG_REG_TMP0 } +}; + static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - MemOp size =3D opc & MO_SIZE; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - /* call load helper */ - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A1, l->addrlo_reg); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A2, oi); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, (tcg_target_long)l->raddr); - - tcg_out_call_int(s, qemu_ld_helpers[size], false); - - tcg_out_movext(s, l->type, l->datalo_reg, - TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_A0); + tcg_out_ld_helper_args(s, l, &ldst_helper_param); + tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE], false); + tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param); return tcg_out_goto(s, l->raddr); } =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - MemOp size =3D opc & MO_SIZE; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - /* call store helper */ - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A1, l->addrlo_reg); - tcg_out_movext(s, size =3D=3D MO_64 ? TCG_TYPE_I32 : TCG_TYPE_I32, TCG= _REG_A2, - l->type, size, l->datalo_reg); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, oi); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A4, (tcg_target_long)l->raddr); - - tcg_out_call_int(s, qemu_st_helpers[size], false); - + tcg_out_st_helper_args(s, l, &ldst_helper_param); + tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); return tcg_out_goto(s, l->raddr); } #else --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683793033; cv=none; d=zohomail.com; s=zohoarc; b=I2mjfSHAAAZOpdbrmADyxpeXISWDfM8+97Oi4sMWdZXnY1A2qQxjKeTLixNQHv6a1b9xi+sF+IOlwaqcDFJHVKoYJMb2mJmkim6xgydgXLIB65qis0p+WKRmiUOph4uNA+E3zFV37XbhaBrRkVeqfmkhAwgCXYIlRH5VXpGjrt4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683793033; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dlah/sNKnEYoy9ZbUN1QDNt4gOhBndvkbi67wtgjUoM=; b=MMb8TVO2HBRHAoE3BMijM2oEmbMOMUdLIK4R0uYQim+weQW6LLS0x/pRG0qTy9ot8xxQiOFENIDgHKVa71H/RH+3VjGInqpsCmj10Ub2te1sNV/GP7AygBamHLr7WntRscrfJRemaL4CJXKDXWlW2vDM6wq8kVPYPUIKcUFTiGQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16837930337411004.4464855187342; Thu, 11 May 2023 01:17:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Ir-0006ws-1l; Thu, 11 May 2023 04:05:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Ig-0006RI-Es for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:24 -0400 Received: from mail-ed1-x52c.google.com ([2a00:1450:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IV-00010K-TK for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:22 -0400 Received: by mail-ed1-x52c.google.com with SMTP id 4fb4d7f45d1cf-50b9ef67f35so14689758a12.2 for ; Thu, 11 May 2023 01:05:09 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792309; x=1686384309; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dlah/sNKnEYoy9ZbUN1QDNt4gOhBndvkbi67wtgjUoM=; b=ayr4DsMW/ZiSqDJIifas65IMGnBlxAplPm1QxdTmIpNSF4PJN26EnWH/i3U7t+ej7S tAjkO56yqYGO3MWLIj6OYLlEbxnon1Spl6FokpSrsQv0xjbxZmfb6WaNGg63zxw7OWn9 EX47eMJpHLkAeQQ1IB4qnOvHEWpS/gDwnfp9Rm25826IJfqauGfNlWRB2l3fGNsfL7BK N5OleHYCDct5mKPSN7oBr+1DDuAeulFNOjtu3yVOduZFigy48afluAqRYe6K4fElKg8M DGJ61OPWa/1eljc3Q4tldtA/3RSo5l/EjArL5ouW4uJSxnaTD9fb08WBVRVtXtVLuvGB 7ITA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792309; x=1686384309; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dlah/sNKnEYoy9ZbUN1QDNt4gOhBndvkbi67wtgjUoM=; b=Gx3XeHnEumc9CbuOCKo5WTuta9p+/ZN+lX2QsgcnQpZRyaJ6QvIuhk0tx5lkdbn2Aj M2IkRnlsxEYrV4pw6SDie2TIXqEszPMjrnOr6DeCExzdM9D7aWoDWdJ16RoaYW62oWbU GP6SlgJgRFhlwhT6XF9wjpeBLu+8BfHUaxNancovETL29DtO4cdhEMZ18DExabJwNY7i 0KXKxdJEqCxoPZJeCtvYL244T+312ahasj8xj2qckgDV4TbQkyDUJ452ZNdlEuHe+S3u msnDATeBCGjMvH3fRojq6oDzoZJ6VUXA1j5FYsLpsmvC3QQ8RjsmvzP0Z8RmG5OyYoX8 T0/w== X-Gm-Message-State: AC+VfDxR8ImE5lUzQi8VLagauCURudXd5e8tdDtaxN4X4B6i+ehJ5TkO ZTpiJ2zYjM/23zo4nKyLb5FYOyAaVtE6ce6MptWR2A== X-Google-Smtp-Source: ACHHUZ754LCrXWBpW0fSnoWgE5nHHIfNBRgQC17IcO4qXyhqyLV4l2EteTM/gr8hS+S7N+IeAX3n6Q== X-Received: by 2002:aa7:d7d4:0:b0:50b:dcf6:8e6d with SMTP id e20-20020aa7d7d4000000b0050bdcf68e6dmr16667065eds.18.1683792308800; Thu, 11 May 2023 01:05:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 26/53] tcg/mips: Convert tcg_out_qemu_{ld,st}_slow_path Date: Thu, 11 May 2023 09:04:23 +0100 Message-Id: <20230511080450.860923-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683793035846100003 Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. This allows our local tcg_out_arg_* infrastructure to be removed. We are no longer filling the call or return branch delay slots, nor are we tail-calling for the store, but this seems a small price to pay. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 154 ++++++-------------------------------- 1 file changed, 22 insertions(+), 132 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 94708e6ea7..022960d79a 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1115,79 +1115,15 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_B= SWAP) + 1] =3D { [MO_BEUQ] =3D helper_be_stq_mmu, }; =20 -/* Helper routines for marshalling helper function arguments into - * the correct registers and stack. - * I is where we want to put this argument, and is updated and returned - * for the next call. ARG is the argument itself. - * - * We provide routines for arguments which are: immediate, 32 bit - * value in register, 16 and 8 bit values in register (which must be zero - * extended before use) and 64 bit value in a lo:hi register pair. - */ - -static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg) -{ - if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { - tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg); - } else { - /* For N32 and N64, the initial offset is different. But there - we also have 8 argument register so we don't run out here. */ - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); - tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i); - } - return i + 1; -} - -static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg) -{ - TCGReg tmp =3D TCG_TMP0; - if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { - tmp =3D tcg_target_call_iarg_regs[i]; - } - tcg_out_ext8u(s, tmp, arg); - return tcg_out_call_iarg_reg(s, i, tmp); -} - -static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg) -{ - TCGReg tmp =3D TCG_TMP0; - if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { - tmp =3D tcg_target_call_iarg_regs[i]; - } - tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff); - return tcg_out_call_iarg_reg(s, i, tmp); -} - -static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg) -{ - TCGReg tmp =3D TCG_TMP0; - if (arg =3D=3D 0) { - tmp =3D TCG_REG_ZERO; - } else { - if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { - tmp =3D tcg_target_call_iarg_regs[i]; - } - tcg_out_movi(s, TCG_TYPE_REG, tmp, arg); - } - return tcg_out_call_iarg_reg(s, i, tmp); -} - -static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg = ah) -{ - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); - i =3D (i + 1) & ~1; - i =3D tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al)); - i =3D tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah)); - return i; -} +/* We have four temps, we might as well expose three of them. */ +static const TCGLdstHelperParam ldst_helper_param =3D { + .ntmp =3D 3, .tmp =3D { TCG_TMP0, TCG_TMP1, TCG_TMP2 } +}; =20 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { const tcg_insn_unit *tgt_rx =3D tcg_splitwx_to_rx(s->code_ptr); - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - TCGReg v0; - int i; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_pc16(l->label_ptr[0], tgt_rx) @@ -1196,29 +1132,13 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) return false; } =20 - i =3D 1; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - i =3D tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); - } else { - i =3D tcg_out_call_iarg_reg(s, i, l->addrlo_reg); - } - i =3D tcg_out_call_iarg_imm(s, i, oi); - i =3D tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr); + tcg_out_ld_helper_args(s, l, &ldst_helper_param); + tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], fals= e); /* delay slot */ - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); + tcg_out_nop(s); =20 - v0 =3D l->datalo_reg; - if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { - /* We eliminated V0 from the possible output registers, so it - cannot be clobbered here. So we must move V1 first. */ - if (MIPS_BE) { - tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1); - v0 =3D l->datahi_reg; - } else { - tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1); - } - } + tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); =20 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { @@ -1226,22 +1146,14 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) } =20 /* delay slot */ - if (TCG_TARGET_REG_BITS =3D=3D 64 && l->type =3D=3D TCG_TYPE_I32) { - /* we always sign-extend 32-bit loads */ - tcg_out_ext32s(s, v0, TCG_REG_V0); - } else { - tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO); - } + tcg_out_nop(s); return true; } =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { const tcg_insn_unit *tgt_rx =3D tcg_splitwx_to_rx(s->code_ptr); - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; - int i; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_pc16(l->label_ptr[0], tgt_rx) @@ -1250,41 +1162,19 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) return false; } =20 - i =3D 1; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - i =3D tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); - } else { - i =3D tcg_out_call_iarg_reg(s, i, l->addrlo_reg); - } - switch (s_bits) { - case MO_8: - i =3D tcg_out_call_iarg_reg8(s, i, l->datalo_reg); - break; - case MO_16: - i =3D tcg_out_call_iarg_reg16(s, i, l->datalo_reg); - break; - case MO_32: - i =3D tcg_out_call_iarg_reg(s, i, l->datalo_reg); - break; - case MO_64: - if (TCG_TARGET_REG_BITS =3D=3D 32) { - i =3D tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_re= g); - } else { - i =3D tcg_out_call_iarg_reg(s, i, l->datalo_reg); - } - break; - default: - g_assert_not_reached(); - } - i =3D tcg_out_call_iarg_imm(s, i, oi); + tcg_out_st_helper_args(s, l, &ldst_helper_param); =20 - /* Tail call to the store helper. Thus force the return address - computation to take place in the return address register. */ - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr); - i =3D tcg_out_call_iarg_reg(s, i, TCG_REG_RA); - tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true); + tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], false= ); /* delay slot */ - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); + tcg_out_nop(s); + + tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); + if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { + return false; + } + + /* delay slot */ + tcg_out_nop(s); return true; } =20 --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792845; cv=none; d=zohomail.com; s=zohoarc; b=ijMdrOaJczW8GNQs74lAK5g1DBclZM+Ms83S819d1Nv0SuV1QOf9q2Vp8hsdy4QAGdGa79dVCUrXR624+yWGXNRRX5he3o690E3qcNeXLTeIimcr52BaSy1GWuAxACrXNzAQuYdqEPjWpGlHEXkaa0POGZYXTTkDZxBBBTAxhnA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792845; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4MyRgw/PtcZChVqlCdO0y70qQ7cwt0IlfzjPvvDgR9k=; b=BXNU/cCrlY/2DIFv6v8WRATmvdMe8MG7WC0ZTVxZlLyYpez48DooAWtNUeAk2WEP6xbav+u0f6bHJmI2rbOPWyzCRDsdj+mhToMzqc2SihuM3yvLGysf4u22vZVBasJj1YxiM7w+BO2FaIucIa68Qdwn0ICM0ns8rXqdoC22SZg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792845157248.40567776504417; Thu, 11 May 2023 01:14:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Io-0006jX-Iz; Thu, 11 May 2023 04:05:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Ie-0006RC-QV for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:24 -0400 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IV-0000wT-5U for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:20 -0400 Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-50bc4b88998so14604437a12.3 for ; Thu, 11 May 2023 01:05:09 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792309; x=1686384309; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4MyRgw/PtcZChVqlCdO0y70qQ7cwt0IlfzjPvvDgR9k=; b=YdC/nHrInwaBfiwsyuCCO+ZmhAk5cOKOpSlkmbBgEGemBIrgS9OqW04LHKqgACkh2Y DxlY4QwrwzujSROi3DQ+sgWAKqqvZ3g3u0w/ImtOiROlP14tm81rU3qx98cwEOXxDeGi KRpPAJlg4Uh9sUBSOOEACFlDs+xAwJSyRegaCx2i4HRycAxGWfzGHgANskHSEQamV9m6 Uv+hSYJJVhUoraxwDDSPHkEZwbV7tFxA5q28pZPvMTfKKarJzHcGBJm6o+3SyDgJ68wj yi3jfF6HOxwsuH1E5+cn+DQojdpMr1CfOX7lp0hOtXB3sclqNtjAHFokXBnBDAZwPDIz CTtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792309; x=1686384309; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4MyRgw/PtcZChVqlCdO0y70qQ7cwt0IlfzjPvvDgR9k=; b=U7CX6Qhig8F2MjqQim1Dv8x8aVTV4H1PWb27jZyYSpgs0YY0vSiduiwDKPC8m/u69T UyIzfz+aNeLn5XiljLCxEsHADyWzOb6esbzZxh5D4fk8uNWgOG/gRPgmuiLkG13KOGKu ygmQ5+neYTRBLqFCl2ZaUAlbChkOGtytK8QafHBq6xAMyr/JioSrWd8UZrWq1dew7rKu xVBk8FUueRvkfgtWg1LzCeCN1HUQCvcOSRGbqq5uceWhpOpM0REGb3Uq6fht3toaiW8I tyJaO3FWrmr2yGVvRHSZHxNTCslr9b3aIfKCWXKIwripnMcwuK8yS/929jAfGZNtkvfg zCbw== X-Gm-Message-State: AC+VfDxmcA+HfIWFZy5UkpzPFzWAhF4Ux/ek5Xyvo1z4LE8VX/vgJHmZ p8r2CPxB+/hbOw0+yEhjw3GcGIM0mBiE5a9Hp4oSbA== X-Google-Smtp-Source: ACHHUZ7VQb1pRAAbaESK5vJAEkug2QXxnJEaFvzY9eOsHH8Q8+cT3PyyWx8KXap5N2p34Tr0WIN/ng== X-Received: by 2002:aa7:c546:0:b0:50b:d4e8:3173 with SMTP id s6-20020aa7c546000000b0050bd4e83173mr16616614edr.8.1683792309340; Thu, 11 May 2023 01:05:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Daniel Henrique Barboza Subject: [PULL 27/53] tcg/ppc: Convert tcg_out_qemu_{ld,st}_slow_path Date: Thu, 11 May 2023 09:04:24 +0100 Message-Id: <20230511080450.860923-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792846859100001 Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 88 ++++++++++++---------------------------- 1 file changed, 26 insertions(+), 62 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 0469e299a0..4c479fdece 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2003,44 +2003,38 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_B= SWAP) + 1] =3D { [MO_BEUQ] =3D helper_be_stq_mmu, }; =20 +static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int ar= g) +{ + if (arg < 0) { + arg =3D TCG_REG_TMP1; + } + tcg_out32(s, MFSPR | RT(arg) | LR); + return arg; +} + +/* + * For the purposes of ppc32 sorting 4 input registers into 4 argument + * registers, there is an outside chance we would require 3 temps. + * Because of constraints, no inputs are in r3, and env will not be + * placed into r3 until after the sorting is done, and is thus free. + */ +static const TCGLdstHelperParam ldst_helper_param =3D { + .ra_gen =3D ldst_ra_gen, + .ntmp =3D 3, + .tmp =3D { TCG_REG_TMP1, TCG_REG_R0, TCG_REG_R3 } +}; + static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); - TCGReg hi, lo, arg =3D TCG_REG_R3; + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); - - lo =3D lb->addrlo_reg; - hi =3D lb->addrhi_reg; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - arg |=3D (TCG_TARGET_CALL_ARG_I64 =3D=3D TCG_CALL_ARG_EVEN); - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - } else { - /* If the address needed to be zero-extended, we'll have already - placed it in R4. The only remaining case is 64-bit guest. */ - tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); - } - - tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); - tcg_out32(s, MFSPR | RT(arg) | LR); - + tcg_out_ld_helper_args(s, lb, &ldst_helper_param); tcg_out_call_int(s, LK, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); - - lo =3D lb->datalo_reg; - hi =3D lb->datahi_reg; - if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { - tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4); - tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3); - } else { - tcg_out_movext(s, lb->type, lo, - TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_R3); - } + tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); =20 tcg_out_b(s, 0, lb->raddr); return true; @@ -2048,43 +2042,13 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; - TCGReg hi, lo, arg =3D TCG_REG_R3; + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); - - lo =3D lb->addrlo_reg; - hi =3D lb->addrhi_reg; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - arg |=3D (TCG_TARGET_CALL_ARG_I64 =3D=3D TCG_CALL_ARG_EVEN); - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - } else { - /* If the address needed to be zero-extended, we'll have already - placed it in R4. The only remaining case is 64-bit guest. */ - tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); - } - - lo =3D lb->datalo_reg; - hi =3D lb->datahi_reg; - if (TCG_TARGET_REG_BITS =3D=3D 32 && s_bits =3D=3D MO_64) { - arg |=3D (TCG_TARGET_CALL_ARG_I64 =3D=3D TCG_CALL_ARG_EVEN); - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - } else { - tcg_out_movext(s, s_bits =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I3= 2, - arg++, lb->type, s_bits, lo); - } - - tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); - tcg_out32(s, MFSPR | RT(arg) | LR); - + tcg_out_st_helper_args(s, lb, &ldst_helper_param); tcg_out_call_int(s, LK, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 tcg_out_b(s, 0, lb->raddr); --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792410; cv=none; d=zohomail.com; s=zohoarc; b=MPnwn+TqtfKSL77vd9WDYEMt1yZ0V014nv9lC/hnIAwqict6ihXv202TvC0QLKKyL4tNsYL3Gn7T6LFUWBPnQ7APbpiiY4VPf5snSlMbHvwzE/vhzSfoYYFYwwXPFzO80O/ihniXxlqPn7iflhecFXsXXANTKlgiOgOs+dxUE7c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792410; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Y/Z9z3KxUvkNWrhd72QB2/LSG455kaOK5ErkxE1hIbM=; b=CclNScNN3kntIoNL62o/dj+5ZSoYH4kaXCuhd04dNJqmplH+XlLINtcrSqto4WWNDm4IPDzjDR5w/9G9jmeFXiyo+L6QbEcwpPBlDjWaJ/n7wb59eGitd3I1MmMeokwtoH/NNiuZ+D8BVG5KNP4AtwHhjCogNTwxoAX/HaapKXw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792410908461.3804928697846; Thu, 11 May 2023 01:06:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1J8-0007Hq-7n; Thu, 11 May 2023 04:05:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Ie-0006Qz-Hv for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:24 -0400 Received: from mail-ed1-x530.google.com ([2a00:1450:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IV-00010Q-52 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:20 -0400 Received: by mail-ed1-x530.google.com with SMTP id 4fb4d7f45d1cf-50b9ef67f35so14689783a12.2 for ; Thu, 11 May 2023 01:05:10 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792310; x=1686384310; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y/Z9z3KxUvkNWrhd72QB2/LSG455kaOK5ErkxE1hIbM=; b=pA8BB7dbSKcNeQ15eOmUwQYTg0FQuh9X6mST9bfxMv4rQ6i3230NU7IOmvRVHeiLCs iFDqQzbjXZNl1SxDKtAvAFw7zj35U56oGDxk7kXerzvj+i+aA4ffiJMBrBKbJ1DRWry4 oDyufdTMP0aPRI1B5OSoJKgVLTOKh75EfL6/pQbsPDzxeL16lTNL772ix9gTfOunjxWb smynthsmlMH2YCyBMoszWc6z2kJR15lA9gDAVCDQ/lXtcB+CcydKeQHDRt1BqKMSkjWA X9UiU7YQRma9hHfMeBq2Vl40M0Kqfx/+Grpavl6ZosBPbgeGmcUsiYXcWhwFPJ5mg2BU H6kA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792310; x=1686384310; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y/Z9z3KxUvkNWrhd72QB2/LSG455kaOK5ErkxE1hIbM=; b=PcaxkO1kDPuHxsZ8BbR8mlPAziQMEqJqTRj7xYNbzhPCm+FOfMPa3ad/hDRnuT9uGl ayaaMjgmaj7uAcu5wWnhAxK7PoNPPkPwTbUKWua/CSCz8KnCFys+R66e2/jzlxvSEQJH qKy7DkCNTLPfmBJVx3zqujyHdZkFH3sNBbxfYmEZb9SJR0JCZubbJo5JiqOJzb3rpAe2 Bud0x9oBKB+6Gkvtfix0a5dDF6xVqLn+12NWyX1Rzuf575qweqZI0MTASfB7O1mZsPCj CKlcEJoL+kAyT+JbngIz3Z2NzEgqCGLH8e5ojl6e9iCskr/2eaoGRxtrv9zEhv02FTLS t13g== X-Gm-Message-State: AC+VfDx5WvjYoRJOIDTv4k0VHxsLvlmVTAEy/2xJ1rUBCKd+XtadQ6+3 AsXG5GobMuOcUqxQQWECPCmjs+KQy2ijJYbHTM2Icg== X-Google-Smtp-Source: ACHHUZ7ESaBsNnST5bUud/Sk9h/Uw7cj9q3Cd5DZ48+lQC4CL3qf7zO7DpPiomSmk9pJOIt6H279lQ== X-Received: by 2002:a05:6402:1a48:b0:50c:d5d:c960 with SMTP id bf8-20020a0564021a4800b0050c0d5dc960mr16519972edb.38.1683792309879; Thu, 11 May 2023 01:05:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Daniel Henrique Barboza Subject: [PULL 28/53] tcg/riscv: Convert tcg_out_qemu_{ld,st}_slow_path Date: Thu, 11 May 2023 09:04:25 +0100 Message-Id: <20230511080450.860923-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792412827100003 Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 37 ++++++++++--------------------------- 1 file changed, 10 insertions(+), 27 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 2b2d313fe2..c22d1e35ac 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -906,14 +906,14 @@ static void tcg_out_goto(TCGContext *s, const tcg_ins= n_unit *target) tcg_debug_assert(ok); } =20 +/* We have three temps, we might as well expose them. */ +static const TCGLdstHelperParam ldst_helper_param =3D { + .ntmp =3D 3, .tmp =3D { TCG_REG_TMP0, TCG_REG_TMP1, TCG_REG_TMP2 } +}; + static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - TCGReg a0 =3D tcg_target_call_iarg_regs[0]; - TCGReg a1 =3D tcg_target_call_iarg_regs[1]; - TCGReg a2 =3D tcg_target_call_iarg_regs[2]; - TCGReg a3 =3D tcg_target_call_iarg_regs[3]; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -921,13 +921,9 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, T= CGLabelQemuLdst *l) } =20 /* call load helper */ - tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); - tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); - tcg_out_movi(s, TCG_TYPE_PTR, a2, oi); - tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr); - + tcg_out_ld_helper_args(s, l, &ldst_helper_param); tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); - tcg_out_mov(s, (opc & MO_SIZE) =3D=3D MO_64, l->datalo_reg, a0); + tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); =20 tcg_out_goto(s, l->raddr); return true; @@ -935,14 +931,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, T= CGLabelQemuLdst *l) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; - TCGReg a0 =3D tcg_target_call_iarg_regs[0]; - TCGReg a1 =3D tcg_target_call_iarg_regs[1]; - TCGReg a2 =3D tcg_target_call_iarg_regs[2]; - TCGReg a3 =3D tcg_target_call_iarg_regs[3]; - TCGReg a4 =3D tcg_target_call_iarg_regs[4]; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -950,13 +939,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, T= CGLabelQemuLdst *l) } =20 /* call store helper */ - tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); - tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); - tcg_out_movext(s, s_bits =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, a= 2, - l->type, s_bits, l->datalo_reg); - tcg_out_movi(s, TCG_TYPE_PTR, a3, oi); - tcg_out_movi(s, TCG_TYPE_PTR, a4, (tcg_target_long)l->raddr); - + tcg_out_st_helper_args(s, l, &ldst_helper_param); tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); =20 tcg_out_goto(s, l->raddr); --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683793008; cv=none; d=zohomail.com; s=zohoarc; b=ihnBdSd8BrxuCqIjX/KcqDJWKXeXPLXpAAGi/V5PCeTu22L3u6XpK4TCo+UsOOWuq/hif4mZYGnCeKHenokFYYFAxi9W08o+wIQnOvvPlhLVYRTE8sPDM5NpRC/+5MnihtDxtZOMU2dT15GoA2S406ZLTZKASUomS+wtP9EzcLY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683793008; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bppub7FI4906pQ2iK4M9ZUhUq2k0xoIDRWcVIzCDJ2k=; b=jz9B8v5nILKwtzhAjWWDGFf3KCDVefoa9kuSfGOUEGJmcleRt6uE+/FJvdwojCef1AH4H33eHyOKL2fxo+SWb6nuw0odAZKVZ0DdQWeLQQoBC4aXqrpOyL3/NFsOGzhzCt4+FT+pbgME9d7uVvvEb1vTAb/xjdCDWjctPsNgM5M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683793008534899.5022612963095; Thu, 11 May 2023 01:16:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Ir-0006xp-CX; Thu, 11 May 2023 04:05:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1If-0006RH-Pe for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:24 -0400 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IV-0000x2-6F for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:21 -0400 Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-50db7ec8188so4837329a12.2 for ; Thu, 11 May 2023 01:05:10 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792310; x=1686384310; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bppub7FI4906pQ2iK4M9ZUhUq2k0xoIDRWcVIzCDJ2k=; b=BBVLraMNAhzMjSmnZ36WBRQQ3q+6VElhcpc7+MBAc/Iz/Ltn43LFukAzwrpOCWlyUv FBeQrIjdjVFDz4C06nIVGd729E5i2P1+9Lvlk6XyWPDOE7BLEOncuhQusF2mPvMsKoXK Xa7SblB++aqbBbwFSvMsuBaB13PrYBk8iVVCJOFidpEauf4rd0ckHTfU7UPVb7Vg1vEg PLnm3dqtYf2vg97sURXfyplIvZPu0MWyGkw3eOPtSX/zTiak4PowAlMLDN+dHaHhdRnv 9CFd/a/QuCzAh5xP34JGz3MLGCHBGTObLERoEO5q9/Tjr4XPQ8lMxEd54CA40mUVLoEn 8tHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792310; x=1686384310; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bppub7FI4906pQ2iK4M9ZUhUq2k0xoIDRWcVIzCDJ2k=; b=UVonrwNm42iq7eb0PDBU/IiKdr6BpRizVN/pq0/nEaPfJgPoQr5+Oat60BvoKimbfC pe/uqI06Ec/deYeRg1pz4glU/Dq1K5BjsiTrCf3vxGhM80u+Ne4LXvkR2W6x9UUnjBAG rC8IfOdb/HHd1d0Yw4+SkHqMhytWvkEcaUWIKYW9gwUmDk6L0/HPIY7OamyzS0YZk4a7 GhtOKtZYYHKf3irC4oTDj/Cu8lZx6eq/DjbKCKmBzuF2NRC9dfMpeQxmw6FfofJpAxBF xsJ9oR/VQsvx7FJdC3t0ZuoeISALNGIyATB6x8kx6bb9oZlsWeUocNeugjeyAwU3ZJPW Z5zw== X-Gm-Message-State: AC+VfDzmMDcNxoM3W2gYgkT7mhu4vC3M20gimCyrgDeYx3v7kkW89Vyn GPWzqMP9hb13TbQROQntnwZQeoQoPvUpUyCXEGE7tg== X-Google-Smtp-Source: ACHHUZ7jqBjymbClbC9XumG6KXXoR7EAoq+GBCaWAeUau0jXCF7u7e3GVVuKhnagma8ozdnBUDCqvA== X-Received: by 2002:a50:fa86:0:b0:508:41df:b276 with SMTP id w6-20020a50fa86000000b0050841dfb276mr16865875edr.22.1683792310409; Thu, 11 May 2023 01:05:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 29/53] tcg/s390x: Convert tcg_out_qemu_{ld,st}_slow_path Date: Thu, 11 May 2023 09:04:26 +0100 Message-Id: <20230511080450.860923-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683793010207100003 Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 35 ++++++++++------------------------- 1 file changed, 10 insertions(+), 25 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index c3157d22be..dfcf4d9e34 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1718,26 +1718,22 @@ static void tcg_out_qemu_st_direct(TCGContext *s, M= emOp opc, TCGReg data, } =20 #if defined(CONFIG_SOFTMMU) +static const TCGLdstHelperParam ldst_helper_param =3D { + .ntmp =3D 1, .tmp =3D { TCG_TMP0 } +}; + static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGReg addr_reg =3D lb->addrlo_reg; - TCGReg data_reg =3D lb->datalo_reg; - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(lb->oi); =20 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg); - } - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, oi); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R5, (uintptr_t)lb->raddr); - tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]); - tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R2); + tcg_out_ld_helper_args(s, lb, &ldst_helper_param); + tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); =20 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); return true; @@ -1745,25 +1741,14 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGReg addr_reg =3D lb->addrlo_reg; - TCGReg data_reg =3D lb->datalo_reg; - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); - MemOp size =3D opc & MO_SIZE; + MemOp opc =3D get_memop(lb->oi); =20 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg); - } - tcg_out_movext(s, size =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, - TCG_REG_R4, lb->type, size, data_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, oi); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R6, (uintptr_t)lb->raddr); + tcg_out_st_helper_args(s, lb, &ldst_helper_param); tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792789; cv=none; d=zohomail.com; s=zohoarc; b=U7ae1D4Mt7rEG4jFiffsGQpWX/j/AdyYgE7ROK3nLq1XAFFM0d7/oHO4F3w12ROS4gz4XjaqV5F3a4Z7u7JjClmYyvKypd90qEHthVUgo6yzz2UZNOb0jsoUgegg4DFfEDvr85q6oF5k8XBfITfU5M+8vl1o6lXmudocRet+rQM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792789; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GVV1vYv+cOyGCa7huWy4GqRL3D/sT7PIBjJ5kRdmWHQ=; b=V8kwtDT/tJpTXfmBPNEjG+XJNhv2Yo3pBktBJSppB/IqrOGUhIAQy+nfTUBR8ulo41QDU65NMy1lCWnGDBIEMXdIlojGCVUYOTea+ojB92LVglwTN19v5Wwujl+reBWmPHukuyqx+qptfThcF+S9x8MYbUlX/JgziEHlfWgJZ20= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168379278996551.37154951190064; Thu, 11 May 2023 01:13:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Iq-0006tb-6l; Thu, 11 May 2023 04:05:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Ih-0006RQ-UB for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:25 -0400 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IW-00010s-Hr for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:23 -0400 Received: by mail-ed1-x529.google.com with SMTP id 4fb4d7f45d1cf-50bc4ba28cbso14721119a12.0 for ; Thu, 11 May 2023 01:05:12 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792311; x=1686384311; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GVV1vYv+cOyGCa7huWy4GqRL3D/sT7PIBjJ5kRdmWHQ=; b=rdKnzMh/nOd1RGaSYvMqUyIFnn1Cda2RZMYckjgoxzRgm/XfMgaOCKprC29gi+E7Jm 9RyoVz72lf5G8wBhY/ijIck60V+3EmJ1/NUeXjyaLybN/iRwqlr8o1JCYHqaYlk5rYBh leeOBbUx1U9DsPu8QEZCZqDGBSOdbW4tIwd+Qrc1SGQVdTAf+2vcm8/sl5GcpPRGAqRt ok2QSgHJyaRh3mmuynYG5qn1YUU8MGJeQ81HYRFLeNdfWK75Twuw8V1lMyUKtbepqIns KxUFOJl8ZhSZjribnW8xxsw3YA4wu/GfgPx3rnmBsXk21UN55mOLcJKub/KwxeTC/+tk u4Yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792311; x=1686384311; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GVV1vYv+cOyGCa7huWy4GqRL3D/sT7PIBjJ5kRdmWHQ=; b=ZZS5cOM/LktR0OshNqgI5ztBB4PZYX0AKA0Q7/qsvWFyrnxjBLsm+NBWBFjy8gnWJD qvJZTIifs12ml7r8QdLkadBwmqdDNm/NyxYIjhlDTWvu05VbX4CqRgVcn5FXkH+neQzB +tNoiJFt0gp9+jjvUnrlLRhcOQfdZth6eKNXD9+8XOym42/wqIchQGG2gwrGnGsewHx0 4VMBNocC9xT5BUHLsD2vVEjOQSqoKZ1Bobbcfla1+LnR9QoZu8WwizxcpXGwiXof5355 6M39yAmrWRvPqXA/iLtoEw8QOhbPUBwTX2kk3untacsKscruwzhybQNJYm3MaoMJVOqQ Qu2Q== X-Gm-Message-State: AC+VfDz2XQNk8qTru0FlrjX4gTakotOJlTiLrszxGo5S+d8gygM1FfBZ 4hwYqa6SHI/YsJLbSEcokV3KXjzMBIKIVnnh0UpeZw== X-Google-Smtp-Source: ACHHUZ7SG5h7bALI6d7F5laJBfFZ09W4PNb6IVllXTf93BUiK0ZKatOjT3FMnjtZrUQinYBe1XilIQ== X-Received: by 2002:a05:6402:886:b0:50d:b7e5:fde8 with SMTP id e6-20020a056402088600b0050db7e5fde8mr6478535edy.26.1683792311046; Thu, 11 May 2023 01:05:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 30/53] tcg/loongarch64: Simplify constraints on qemu_ld/st Date: Thu, 11 May 2023 09:04:27 +0100 Message-Id: <20230511080450.860923-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792790447100001 The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 2 -- tcg/loongarch64/tcg-target-con-str.h | 1 - tcg/loongarch64/tcg-target.c.inc | 23 ++++------------------- 3 files changed, 4 insertions(+), 22 deletions(-) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-tar= get-con-set.h index 172c107289..c2bde44613 100644 --- a/tcg/loongarch64/tcg-target-con-set.h +++ b/tcg/loongarch64/tcg-target-con-set.h @@ -17,9 +17,7 @@ C_O0_I1(r) C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) -C_O0_I2(LZ, L) C_O1_I1(r, r) -C_O1_I1(r, L) C_O1_I2(r, r, rC) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) diff --git a/tcg/loongarch64/tcg-target-con-str.h b/tcg/loongarch64/tcg-tar= get-con-str.h index 541ff47fa9..6e9ccca3ad 100644 --- a/tcg/loongarch64/tcg-target-con-str.h +++ b/tcg/loongarch64/tcg-target-con-str.h @@ -14,7 +14,6 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) -REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 60d2c904dd..83fa45c802 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -133,18 +133,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKi= nd kind, int slot) #define TCG_CT_CONST_C12 0x1000 #define TCG_CT_CONST_WSZ 0x2000 =20 -#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) -/* - * For softmmu, we need to avoid conflicts with the first 5 - * argument registers to call the helper. Some of these are - * also used for the tlb lookup. - */ -#ifdef CONFIG_SOFTMMU -#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5) -#else -#define SOFTMMU_RESERVE_REGS 0 -#endif - +#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) =20 static inline tcg_target_long sextreg(tcg_target_long val, int pos, int le= n) { @@ -1541,16 +1530,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) case INDEX_op_st32_i64: case INDEX_op_st_i32: case INDEX_op_st_i64: + case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st_i64: return C_O0_I2(rZ, r); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: return C_O0_I2(rZ, rZ); =20 - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_st_i64: - return C_O0_I2(LZ, L); - case INDEX_op_ext8s_i32: case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: @@ -1586,11 +1573,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_ld32u_i64: case INDEX_op_ld_i32: case INDEX_op_ld_i64: - return C_O1_I1(r, r); - case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return C_O1_I1(r, L); + return C_O1_I1(r, r); =20 case INDEX_op_andc_i32: case INDEX_op_andc_i64: --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683793001; cv=none; d=zohomail.com; s=zohoarc; b=KH/K6aaJnHiXFW4ZGMu0zw/b9DzxoBf2S+Nd7a1EI3WaP6nX7qmBBewekyb+qXZc9P0111+HDYiWQeD61ItvYCLmdM7kqJsvj+WUidcBjA/12VfAecOiYx4kLVHT8hZdWn/20i+35HCcYQrtbXyPxuq08Yi35WQRmy65rMg/sG4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683793001; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1/Ru4MgY/q1PdZJEQerRBQ2wst30TTc6WB5rVqnIgCQ=; b=FrdmBqiCIoFe2tulBiBpewFd0jOZ0w75L9xJvXkv4UL0i3BSFxhIDIkrh2GEKbGpcEJXYj56BVZ27BbXk+CPUpo9cEZAh2Rib8EwJGwa1Eh7iRh7mL3N2QLj5brsf1y126dREhEw4AmeoqsNlqS2HpORO63bCYlbkXZkO3T17MU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683793001512746.5481956495103; Thu, 11 May 2023 01:16:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Ir-0006x4-3c; Thu, 11 May 2023 04:05:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Ik-0006cv-JJ for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:27 -0400 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IX-00012X-9S for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:25 -0400 Received: by mail-ed1-x531.google.com with SMTP id 4fb4d7f45d1cf-50bc2feb320so12843871a12.3 for ; Thu, 11 May 2023 01:05:12 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792312; x=1686384312; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1/Ru4MgY/q1PdZJEQerRBQ2wst30TTc6WB5rVqnIgCQ=; b=r220tQfauULEGcIb+v3z0yRZlsA4PswHIwZmyGJAe91eocGufkOr8Q5RnbQvYbEiGj +vfiDpHpKtBnB/mKxQdtf+0o9HuyQMOG88agAoPxqGCokU9+sY98GKCz/6XtI8I8ymL5 DHw6tYeK6BOmNeWEZTzUSwOaUQQDJEDMBm9jArn1Im2LBUebYVYM8DTs6qLbeH2Q6Nrq xxXqALKsRrhbW3aNK7g1nVdxctT6aPSwIshnzmj1KfpLwNMvvd3BRMr3Xk5m28X4c5LL u0mFO2Tzk92wAMCT173XOPPbvj+UGh0uFDXG/xhlWzKyq/m26xS+pwtV2R5lR31e2p/r xHsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792312; x=1686384312; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1/Ru4MgY/q1PdZJEQerRBQ2wst30TTc6WB5rVqnIgCQ=; b=aA/ouz9zvKC5ReqYaOp0v0NQMKQtdGnu3AxJhfLD34fvEfYGNoevNq+7it6/HEGYLk GObK83R4ULmf1W/c1B+DnVAkIpMtyTA8Lju25QELON+lgBIyXRKccBnw3Uj6eDNwAIrf SgVLsUJijIcqb5aPcsuBJsQ2dAKOYgOa4WxkWlclU/8bLKlq6rATQkQoYnY54+seEMZf VCxU0hcoHnXPV+PDAraSfOBt+PkcC5s6/Y3BXHAIGGDa8bO2hRWllly4J/bUknvNAg3c TDCg/nhN3LzSUUPKcngYvS8nbchL+ZZpYe5uwO7FvztYphLzZHYRi2LeI+ap1xrD+qfU pgMQ== X-Gm-Message-State: AC+VfDyJKv4r8n9PD9fX9Ls07i931Hu2xfZIQy/bXr8VSCh00m9QiTxc fNlhObB0QBuKmRoUNSvCxfiYDN6n4exQeebx5o5nrA== X-Google-Smtp-Source: ACHHUZ4Zs9QPBWf+ufxghQ7dvS+a7lN3PW1jh4Z7ML9pUdTWGNXxfk82v4W9ek//KmjrhBAX7NgOQw== X-Received: by 2002:a05:6402:3445:b0:506:9984:9239 with SMTP id l5-20020a056402344500b0050699849239mr15237868edc.26.1683792311865; Thu, 11 May 2023 01:05:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 31/53] tcg/mips: Remove MO_BSWAP handling Date: Thu, 11 May 2023 09:04:28 +0100 Message-Id: <20230511080450.860923-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683793002182100009 While performing the load in the delay slot of the call to the common bswap helper function is cute, it is not worth the added complexity. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 4 +- tcg/mips/tcg-target.c.inc | 284 ++++++-------------------------------- 2 files changed, 48 insertions(+), 240 deletions(-) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 2431fc5353..42bd7fff01 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -204,8 +204,8 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_ext16u_i64 0 /* andi rt, rs, 0xffff */ #endif =20 -#define TCG_TARGET_DEFAULT_MO (0) -#define TCG_TARGET_HAS_MEMORY_BSWAP 1 +#define TCG_TARGET_DEFAULT_MO 0 +#define TCG_TARGET_HAS_MEMORY_BSWAP 0 =20 #define TCG_TARGET_NEED_LDST_LABELS =20 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 022960d79a..31d58e1977 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1088,31 +1088,35 @@ static void tcg_out_call(TCGContext *s, const tcg_i= nsn_unit *arg, } =20 #if defined(CONFIG_SOFTMMU) -static void * const qemu_ld_helpers[(MO_SSIZE | MO_BSWAP) + 1] =3D { +static void * const qemu_ld_helpers[MO_SSIZE + 1] =3D { [MO_UB] =3D helper_ret_ldub_mmu, [MO_SB] =3D helper_ret_ldsb_mmu, - [MO_LEUW] =3D helper_le_lduw_mmu, - [MO_LESW] =3D helper_le_ldsw_mmu, - [MO_LEUL] =3D helper_le_ldul_mmu, - [MO_LEUQ] =3D helper_le_ldq_mmu, - [MO_BEUW] =3D helper_be_lduw_mmu, - [MO_BESW] =3D helper_be_ldsw_mmu, - [MO_BEUL] =3D helper_be_ldul_mmu, - [MO_BEUQ] =3D helper_be_ldq_mmu, -#if TCG_TARGET_REG_BITS =3D=3D 64 - [MO_LESL] =3D helper_le_ldsl_mmu, - [MO_BESL] =3D helper_be_ldsl_mmu, +#if HOST_BIG_ENDIAN + [MO_UW] =3D helper_be_lduw_mmu, + [MO_SW] =3D helper_be_ldsw_mmu, + [MO_UL] =3D helper_be_ldul_mmu, + [MO_SL] =3D helper_be_ldsl_mmu, + [MO_UQ] =3D helper_be_ldq_mmu, +#else + [MO_UW] =3D helper_le_lduw_mmu, + [MO_SW] =3D helper_le_ldsw_mmu, + [MO_UL] =3D helper_le_ldul_mmu, + [MO_UQ] =3D helper_le_ldq_mmu, + [MO_SL] =3D helper_le_ldsl_mmu, #endif }; =20 -static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] =3D { +static void * const qemu_st_helpers[MO_SIZE + 1] =3D { [MO_UB] =3D helper_ret_stb_mmu, - [MO_LEUW] =3D helper_le_stw_mmu, - [MO_LEUL] =3D helper_le_stl_mmu, - [MO_LEUQ] =3D helper_le_stq_mmu, - [MO_BEUW] =3D helper_be_stw_mmu, - [MO_BEUL] =3D helper_be_stl_mmu, - [MO_BEUQ] =3D helper_be_stq_mmu, +#if HOST_BIG_ENDIAN + [MO_UW] =3D helper_be_stw_mmu, + [MO_UL] =3D helper_be_stl_mmu, + [MO_UQ] =3D helper_be_stq_mmu, +#else + [MO_UW] =3D helper_le_stw_mmu, + [MO_UL] =3D helper_le_stl_mmu, + [MO_UQ] =3D helper_le_stq_mmu, +#endif }; =20 /* We have four temps, we might as well expose three of them. */ @@ -1134,7 +1138,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) =20 tcg_out_ld_helper_args(s, l, &ldst_helper_param); =20 - tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], fals= e); + tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); /* delay slot */ tcg_out_nop(s); =20 @@ -1164,7 +1168,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) =20 tcg_out_st_helper_args(s, l, &ldst_helper_param); =20 - tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], false= ); + tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); /* delay slot */ tcg_out_nop(s); =20 @@ -1379,52 +1383,19 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, TCGReg base, MemOp opc, TCGType type) { - switch (opc & (MO_SSIZE | MO_BSWAP)) { + switch (opc & MO_SSIZE) { case MO_UB: tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); break; case MO_SB: tcg_out_opc_imm(s, OPC_LB, lo, base, 0); break; - case MO_UW | MO_BSWAP: - tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); - tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OZ); - break; case MO_UW: tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); break; - case MO_SW | MO_BSWAP: - tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); - tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OS); - break; case MO_SW: tcg_out_opc_imm(s, OPC_LH, lo, base, 0); break; - case MO_UL | MO_BSWAP: - if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64) { - if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); - tcg_out_bswap32(s, lo, lo, TCG_BSWAP_IZ | TCG_BSWAP_OZ); - } else { - tcg_out_bswap_subr(s, bswap32u_addr); - /* delay slot */ - tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0); - tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); - } - break; - } - /* FALLTHRU */ - case MO_SL | MO_BSWAP: - if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, OPC_LW, lo, base, 0); - tcg_out_bswap32(s, lo, lo, 0); - } else { - tcg_out_bswap_subr(s, bswap32_addr); - /* delay slot */ - tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); - tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3); - } - break; case MO_UL: if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64) { tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); @@ -1434,35 +1405,6 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TC= GReg lo, TCGReg hi, case MO_SL: tcg_out_opc_imm(s, OPC_LW, lo, base, 0); break; - case MO_UQ | MO_BSWAP: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, OPC_LD, lo, base, 0); - tcg_out_bswap64(s, lo, lo); - } else { - tcg_out_bswap_subr(s, bswap64_addr); - /* delay slot */ - tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0); - tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); - } - } else if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); - tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); - tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); - tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); - } else { - tcg_out_bswap_subr(s, bswap32_addr); - /* delay slot */ - tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); - tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4); - tcg_out_bswap_subr(s, bswap32_addr); - /* delay slot */ - tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); - tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); - } - break; case MO_UQ: /* Prefer to load from offset 0 first, but allow for overlap. */ if (TCG_TARGET_REG_BITS =3D=3D 64) { @@ -1487,25 +1429,20 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, = TCGReg lo, TCGReg hi, const MIPSInsn lw2 =3D MIPS_BE ? OPC_LWR : OPC_LWL; const MIPSInsn ld1 =3D MIPS_BE ? OPC_LDL : OPC_LDR; const MIPSInsn ld2 =3D MIPS_BE ? OPC_LDR : OPC_LDL; + bool sgn =3D opc & MO_SIGN; =20 - bool sgn =3D (opc & MO_SIGN); - - switch (opc & (MO_SSIZE | MO_BSWAP)) { - case MO_SW | MO_BE: - case MO_UW | MO_BE: - tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); - tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); - if (use_mips32r2_instructions) { - tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); - } else { - tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); - tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); - } - break; - - case MO_SW | MO_LE: - case MO_UW | MO_LE: - if (use_mips32r2_instructions && lo !=3D base) { + switch (opc & MO_SIZE) { + case MO_16: + if (HOST_BIG_ENDIAN) { + tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); + tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); + if (use_mips32r2_instructions) { + tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); + } else { + tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); + tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0); + } + } else if (use_mips32r2_instructions && lo !=3D base) { tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); @@ -1517,8 +1454,7 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TC= GReg lo, TCGReg hi, } break; =20 - case MO_SL: - case MO_UL: + case MO_32: tcg_out_opc_imm(s, lw1, lo, base, 0); tcg_out_opc_imm(s, lw2, lo, base, 3); if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64 && != sgn) { @@ -1526,28 +1462,7 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, T= CGReg lo, TCGReg hi, } break; =20 - case MO_UL | MO_BSWAP: - case MO_SL | MO_BSWAP: - if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, lw1, lo, base, 0); - tcg_out_opc_imm(s, lw2, lo, base, 3); - tcg_out_bswap32(s, lo, lo, - TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D T= CG_TYPE_I64 - ? (sgn ? TCG_BSWAP_OS : TCG_BSWAP_OZ) : 0); - } else { - const tcg_insn_unit *subr =3D - (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64= && !sgn - ? bswap32u_addr : bswap32_addr); - - tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0); - tcg_out_bswap_subr(s, subr); - /* delay slot */ - tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 3); - tcg_out_mov(s, type, lo, TCG_TMP3); - } - break; - - case MO_UQ: + case MO_64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_opc_imm(s, ld1, lo, base, 0); tcg_out_opc_imm(s, ld2, lo, base, 7); @@ -1559,42 +1474,6 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, T= CGReg lo, TCGReg hi, } break; =20 - case MO_UQ | MO_BSWAP: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, ld1, lo, base, 0); - tcg_out_opc_imm(s, ld2, lo, base, 7); - tcg_out_bswap64(s, lo, lo); - } else { - tcg_out_opc_imm(s, ld1, TCG_TMP0, base, 0); - tcg_out_bswap_subr(s, bswap64_addr); - /* delay slot */ - tcg_out_opc_imm(s, ld2, TCG_TMP0, base, 7); - tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); - } - } else if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0); - tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3); - tcg_out_opc_imm(s, lw1, TCG_TMP1, base, 4 + 0); - tcg_out_opc_imm(s, lw2, TCG_TMP1, base, 4 + 3); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); - tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); - tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); - } else { - tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0); - tcg_out_bswap_subr(s, bswap32_addr); - /* delay slot */ - tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3); - tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 4 + 0); - tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); - tcg_out_bswap_subr(s, bswap32_addr); - /* delay slot */ - tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 4 + 3); - tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); - } - break; - default: g_assert_not_reached(); } @@ -1627,50 +1506,16 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, TCGReg base, MemOp opc) { - /* Don't clutter the code below with checks to avoid bswapping ZERO. = */ - if ((lo | hi) =3D=3D 0) { - opc &=3D ~MO_BSWAP; - } - - switch (opc & (MO_SIZE | MO_BSWAP)) { + switch (opc & MO_SIZE) { case MO_8: tcg_out_opc_imm(s, OPC_SB, lo, base, 0); break; - - case MO_16 | MO_BSWAP: - tcg_out_bswap16(s, TCG_TMP1, lo, 0); - lo =3D TCG_TMP1; - /* FALLTHRU */ case MO_16: tcg_out_opc_imm(s, OPC_SH, lo, base, 0); break; - - case MO_32 | MO_BSWAP: - tcg_out_bswap32(s, TCG_TMP3, lo, 0); - lo =3D TCG_TMP3; - /* FALLTHRU */ case MO_32: tcg_out_opc_imm(s, OPC_SW, lo, base, 0); break; - - case MO_64 | MO_BSWAP: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_bswap64(s, TCG_TMP3, lo); - tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0); - } else if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo); - tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); - tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); - tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0); - tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4); - } else { - tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0); - tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0); - tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0); - tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4); - } - break; case MO_64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_opc_imm(s, OPC_SD, lo, base, 0); @@ -1679,7 +1524,6 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4); } break; - default: g_assert_not_reached(); } @@ -1693,54 +1537,18 @@ static void tcg_out_qemu_st_unalign(TCGContext *s, = TCGReg lo, TCGReg hi, const MIPSInsn sd1 =3D MIPS_BE ? OPC_SDL : OPC_SDR; const MIPSInsn sd2 =3D MIPS_BE ? OPC_SDR : OPC_SDL; =20 - /* Don't clutter the code below with checks to avoid bswapping ZERO. = */ - if ((lo | hi) =3D=3D 0) { - opc &=3D ~MO_BSWAP; - } - - switch (opc & (MO_SIZE | MO_BSWAP)) { - case MO_16 | MO_BE: + switch (opc & MO_SIZE) { + case MO_16: tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); - tcg_out_opc_imm(s, OPC_SB, TCG_TMP0, base, 0); - tcg_out_opc_imm(s, OPC_SB, lo, base, 1); + tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, = 0); + tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, = 1); break; =20 - case MO_16 | MO_LE: - tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); - tcg_out_opc_imm(s, OPC_SB, lo, base, 0); - tcg_out_opc_imm(s, OPC_SB, TCG_TMP0, base, 1); - break; - - case MO_32 | MO_BSWAP: - tcg_out_bswap32(s, TCG_TMP3, lo, 0); - lo =3D TCG_TMP3; - /* fall through */ case MO_32: tcg_out_opc_imm(s, sw1, lo, base, 0); tcg_out_opc_imm(s, sw2, lo, base, 3); break; =20 - case MO_64 | MO_BSWAP: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_bswap64(s, TCG_TMP3, lo); - lo =3D TCG_TMP3; - } else if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? hi : lo); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? lo : hi); - tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); - tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); - hi =3D MIPS_BE ? TCG_TMP0 : TCG_TMP1; - lo =3D MIPS_BE ? TCG_TMP1 : TCG_TMP0; - } else { - tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0); - tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 0 + 0); - tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 0 + 3); - tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0); - tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 4 + 0); - tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 4 + 3); - break; - } - /* fall through */ case MO_64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_opc_imm(s, sd1, lo, base, 0); --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792431; cv=none; d=zohomail.com; s=zohoarc; b=Z0m7kHw9Eq7ftslo3LHflHwEg6ucl7abmz7c8MZulewBflTpqbxZ65/qo0vdcPC30XpgyccItMyGMctYuqQ6P3kNOw0BvfHty7xozIPrOqgx5Yb/SCeN+roKLctdT+13+yn5V+Wkl6wlFSqlX5zpSuIWz2VXHbC7QQnpOLAnhM0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792431; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jLbBOadN4gZq1rFAvZjZjp7zJHx5OGq0m8coZ1qZSsg=; b=eULc3o5DsaL45gDIN9lcT3IYfovkFg4WZexD9lwo+VIt2OOuius8kfswPJ1qH7JU5tJvpB3ZiFzX7pHfmhR027efymaDSIA3CXc9knhVA2pI9pDymk607g2nu2gw7cXlfEJs09LcZ1KfdBeW2STsBs8WXAVSi30XP0dDB16mYHQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792431481987.3239829893504; Thu, 11 May 2023 01:07:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1JF-0007SV-PX; Thu, 11 May 2023 04:05:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Ir-00070W-Ms for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:33 -0400 Received: from mail-ed1-x533.google.com ([2a00:1450:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IZ-00012d-2m for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:33 -0400 Received: by mail-ed1-x533.google.com with SMTP id 4fb4d7f45d1cf-50bc075d6b2so15284761a12.0 for ; Thu, 11 May 2023 01:05:14 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792312; x=1686384312; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jLbBOadN4gZq1rFAvZjZjp7zJHx5OGq0m8coZ1qZSsg=; b=gKuIPvC86jJ849V6g5Uuanpx8nakrinYfSi5dMKOrvdBUvKaVrnO/fe7Cgx/EydUdF y/7Zh5CHq4sXEU3UIY5iCfhK9nbWFzRcNXJgEtSK58+ib7GL6oVaYwNdY9PZiTrQYq/7 AVY6jqX8/fx+9RH4pGdaUThjb2+Aea/ee/U5SDsVPMJqZoz6d180avhED3pRWFL1MDxy T3Cm9igL0e4yWAym7mNTK59nSceYUHRPT2lc0JGcGDf831/CKxp+XOC0a+lKQBLmtQkz GlUK3b+kgK+GUlea4UMAbwp7CEUvo4TGBvItprWHelq/Wasg52aLiuQq6qydiOe+JcS9 kLgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792312; x=1686384312; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jLbBOadN4gZq1rFAvZjZjp7zJHx5OGq0m8coZ1qZSsg=; b=C1eN+orU8ImKgOb+S1/0oaQ8rugLI2BaEJv2L7SoWGEv0Ft+o22jt4nmY4XLN0RKHB AsguaX/ZVx1VkXSdwgcI6dvd+0YTAj6q6ejYbehGodAUroQmYR7nme8ndVoz3CkkqWpq oel8v/NvDqE40qvxP1JaTYvQp0p7H7kjdfCn/j2+rJZcGO/vmPvMx/Lb05ojBRkeWUSn +CPXZYy18bisyRfZKi1QQziqqQZVA4l5FwkpFIFx+eNozjsY87+/qqqDbX8b3/c/FsW9 WUcTtWeJi0Rferswcp/49qQvrBMtqj18hSycutkNcUNA4chJanOF6YDZWxtdv1RXmsj7 DN9w== X-Gm-Message-State: AC+VfDypNfmg+/VPSq6WShKAzc41CEzEnNYbvK8zEoueXZqkLcXXtF+L bND1FOphKKC/YO83gXrIETku/ZOdmMp5LOrJTIdZAA== X-Google-Smtp-Source: ACHHUZ7Z4yYtPQ4eaYsOlY7S6ZaS8/Taztdpf1lafpNe8h3L1I7GLOSNbxDPOn0VGMRS8vyNTpbglQ== X-Received: by 2002:a05:6402:295:b0:50b:c6c9:2146 with SMTP id l21-20020a056402029500b0050bc6c92146mr14834422edv.24.1683792312414; Thu, 11 May 2023 01:05:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 32/53] tcg/mips: Reorg tlb load within prepare_host_addr Date: Thu, 11 May 2023 09:04:29 +0100 Message-Id: <20230511080450.860923-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792433061100005 Compare the address vs the tlb entry with sign-extended values. This simplifies the page+alignment mask constant, and the generation of the last byte address for the misaligned test. Move the tlb addend load up, and the zero-extension down. This frees up a register, which allows us use TMP3 as the returned base address register instead of A0, which we were using as a 5th temporary. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 38 ++++++++++++++++++-------------------- 1 file changed, 18 insertions(+), 20 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 31d58e1977..695c137023 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -370,6 +370,8 @@ typedef enum { ALIAS_PADDI =3D sizeof(void *) =3D=3D 4 ? OPC_ADDIU : OPC_DADDIU, ALIAS_TSRL =3D TARGET_LONG_BITS =3D=3D 32 || TCG_TARGET_REG_BITS = =3D=3D 32 ? OPC_SRL : OPC_DSRL, + ALIAS_TADDI =3D TARGET_LONG_BITS =3D=3D 32 || TCG_TARGET_REG_BITS = =3D=3D 32 + ? OPC_ADDIU : OPC_DADDIU, } MIPSInsn; =20 /* @@ -1263,14 +1265,12 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, int add_off =3D offsetof(CPUTLBEntry, addend); int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write); - target_ulong tlb_mask; =20 ldst =3D new_ldst_label(s); ldst->is_ld =3D is_ld; ldst->oi =3D oi; ldst->addrlo_reg =3D addrlo; ldst->addrhi_reg =3D addrhi; - base =3D TCG_REG_A0; =20 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); @@ -1290,15 +1290,12 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); } else { - tcg_out_ldst(s, (TARGET_LONG_BITS =3D=3D 64 ? OPC_LD - : TCG_TARGET_REG_BITS =3D=3D 64 ? OPC_LWU : OPC_L= W), - TCG_TMP0, TCG_TMP3, cmp_off); + tcg_out_ld(s, TCG_TYPE_TL, TCG_TMP0, TCG_TMP3, cmp_off); } =20 - /* Zero extend a 32-bit guest address for a 64-bit host. */ - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addrlo); - addrlo =3D base; + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + /* Load the tlb addend for the fast path. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); } =20 /* @@ -1306,18 +1303,18 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, * For unaligned accesses, compare against the end of the access to * verify that it does not cross a page boundary. */ - tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; - tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, tlb_mask); - if (a_mask >=3D s_mask) { - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo); - } else { - tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP2, addrlo, s_mask - a_mask); + tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, TARGET_PAGE_MASK | a_mask); + if (a_mask < s_mask) { + tcg_out_opc_imm(s, ALIAS_TADDI, TCG_TMP2, addrlo, s_mask - a_mask); tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); + } else { + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo); } =20 - if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { - /* Load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); + /* Zero extend a 32-bit guest address for a 64-bit host. */ + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_TMP2, addrlo); + addrlo =3D TCG_TMP2; } =20 ldst->label_ptr[0] =3D s->code_ptr; @@ -1329,14 +1326,15 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); =20 /* Load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); =20 ldst->label_ptr[1] =3D s->code_ptr; tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0); } =20 /* delay slot */ - tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrlo); + base =3D TCG_TMP3; + tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo); #else if (a_mask && (use_mips32r6_instructions || a_bits !=3D s_bits)) { ldst =3D new_ldst_label(s); --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792772; cv=none; d=zohomail.com; s=zohoarc; b=NFxr7PpsLy7ESJEHUJ2ZzZzxtZj+MhUw9Cv01HkT2WJ+5ALesD8HJCxRkYxUAUKBJJmdak3oh2i0ExYgIWvj+zGDepshL8rqxG5iGZBNl+JmtToxutHOfyvqQDAxpgBxjPUDT/DniaHQTfJHsHzhY+lyCf7Zu1DDReTrb4eSHXQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792772; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fl7pdu93dBMkROr4SQBfhDsQ0W729COy3s3bRXX2ht4=; b=lCMoj1rNKSqzUW5eR1GFI9fHED0y45rcCPVkz97AlPj8/Ae9KYk3TxOfJYY1elyHX/FuCmWvE7OL3O3aUpDy6yfAPKUGjS+9BgicG4CwBZtDR5uNJDFypngfe6ewsHYUOM70fcmrRGGEDjdbOlVnb60hjL/iCCTBJE7zJn9knmE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168379277229587.64212453065477; Thu, 11 May 2023 01:12:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Ix-0007EP-GO; Thu, 11 May 2023 04:05:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Ij-0006ZE-Px for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:26 -0400 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IY-00012m-9i for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:25 -0400 Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-50bd2d7ba74so76560084a12.1 for ; Thu, 11 May 2023 01:05:13 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792313; x=1686384313; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fl7pdu93dBMkROr4SQBfhDsQ0W729COy3s3bRXX2ht4=; b=DiuDx7546usrRNZm7Sire6vREkdJbMFi1zAt8BeXBm+/aDYzMc72UTV1xfH93r9UxH gKJpU3/w5m/bz2TcvQzULkRKP26vpfjhEvNnXPI0a4iokfWi6BySvQGaMmM8mcN7D7Jz eluNiVqOyL3Zdsx4B/0QUT4euCi6I9ESRWyADQg9aXuB89LlGAAB+Emca/6Ds/beYjtQ qNvT8MPLxrQqIcgtdRjyZD2w/CqSAfzatYfc55tLUVVckeFmwuFPYWfwZzzwhBdXK26F rHvnAcuONtu/9dAtxOKShZjf2M6fpwz9sXke3R/tQEG5MyNzTd/bDn0t193rF2/ycO90 Ub0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792313; x=1686384313; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fl7pdu93dBMkROr4SQBfhDsQ0W729COy3s3bRXX2ht4=; b=EB8qRCAu58d0Ur1u0OE614uL3TakVZ2Js1nW5fqevba37gCK6/Klebp+U0pcGTQ5mk TcIuVxb819/qVzNKmaM9G2/iS8xzEvkmIRcHVZQw6duDwMtqjVIeIfrtDV7lYDU1i+Si rzt9opwnB8ME601stiom1y2mO2AM08KmgwNrmjW31PQnD2JwIIXoO966z/kfbwETJoev EdwM71JVOGgaF0LdqD8sAvIXQZSgXkvmtz5+g2oWUO36d5IJDp4U5Kkorf2XBi740zQe th/NIVHmScTzkIMzT8TnxEt1OHQQfNVIKjSnbwjd/pX5xpZn6H6T2ME1qt1tbMhbc6wN wABg== X-Gm-Message-State: AC+VfDz8OVQ71nH0etdwzaONQr7X9ujtqrDpREs5zq4Ryv3Ks7sISKD4 0LJxrBVc1VSDbMmZXqyB1vPChv8gMMLqvdjXVL8NSg== X-Google-Smtp-Source: ACHHUZ4CkaghtfDKBx5crezUrxkcL3RduBWAc5hZRZUATk1I5xqN2HC+8MeGRoGNmaGvle4v68NEiw== X-Received: by 2002:a05:6402:78d:b0:50c:1677:91ad with SMTP id d13-20020a056402078d00b0050c167791admr18685396edy.17.1683792312931; Thu, 11 May 2023 01:05:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 33/53] tcg/mips: Simplify constraints on qemu_ld/st Date: Thu, 11 May 2023 09:04:30 +0100 Message-Id: <20230511080450.860923-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792774287100011 The softmmu tlb uses TCG_REG_TMP[0-3], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, and have eliminated use of A0, we can allow any allocatable reg. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-con-set.h | 13 +++++-------- tcg/mips/tcg-target-con-str.h | 2 -- tcg/mips/tcg-target.c.inc | 30 ++++++++---------------------- 3 files changed, 13 insertions(+), 32 deletions(-) diff --git a/tcg/mips/tcg-target-con-set.h b/tcg/mips/tcg-target-con-set.h index fe3e868a2f..864034f468 100644 --- a/tcg/mips/tcg-target-con-set.h +++ b/tcg/mips/tcg-target-con-set.h @@ -12,15 +12,13 @@ C_O0_I1(r) C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) -C_O0_I2(SZ, S) -C_O0_I3(SZ, S, S) -C_O0_I3(SZ, SZ, S) +C_O0_I3(rZ, r, r) +C_O0_I3(rZ, rZ, r) C_O0_I4(rZ, rZ, rZ, rZ) -C_O0_I4(SZ, SZ, S, S) -C_O1_I1(r, L) +C_O0_I4(rZ, rZ, r, r) C_O1_I1(r, r) C_O1_I2(r, 0, rZ) -C_O1_I2(r, L, L) +C_O1_I2(r, r, r) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) C_O1_I2(r, r, rIK) @@ -30,7 +28,6 @@ C_O1_I2(r, rZ, rN) C_O1_I2(r, rZ, rZ) C_O1_I4(r, rZ, rZ, rZ, 0) C_O1_I4(r, rZ, rZ, rZ, rZ) -C_O2_I1(r, r, L) -C_O2_I2(r, r, L, L) +C_O2_I1(r, r, r) C_O2_I2(r, r, r, r) C_O2_I4(r, r, rZ, rZ, rN, rN) diff --git a/tcg/mips/tcg-target-con-str.h b/tcg/mips/tcg-target-con-str.h index e4b2965c72..413c280a7a 100644 --- a/tcg/mips/tcg-target-con-str.h +++ b/tcg/mips/tcg-target-con-str.h @@ -9,8 +9,6 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) -REGS('L', ALL_QLOAD_REGS) -REGS('S', ALL_QSTORE_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 695c137023..5ad9867882 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -176,20 +176,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, #define TCG_CT_CONST_WSZ 0x2000 /* word size */ =20 #define ALL_GENERAL_REGS 0xffffffffu -#define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0)) - -#ifdef CONFIG_SOFTMMU -#define ALL_QLOAD_REGS \ - (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2)) -#define ALL_QSTORE_REGS \ - (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \ - ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \ - : (1 << TCG_REG_A1))) -#else -#define ALL_QLOAD_REGS NOA0_REGS -#define ALL_QSTORE_REGS NOA0_REGS -#endif - =20 static bool is_p2m1(tcg_target_long val) { @@ -2232,18 +2218,18 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_qemu_ld_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); + ? C_O1_I1(r, r) : C_O1_I2(r, r, r)); case INDEX_op_qemu_st_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S)); + ? C_O0_I2(rZ, r) : C_O0_I3(rZ, r, r)); case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) - : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(r, r, L) - : C_O2_I2(r, r, L, L)); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) + : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(r, r, r) + : C_O2_I2(r, r, r, r)); case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(SZ, S) - : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(SZ, SZ, S) - : C_O0_I4(SZ, SZ, S, S)); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(rZ, r) + : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(rZ, rZ, r) + : C_O0_I4(rZ, rZ, r, r)); =20 default: g_assert_not_reached(); --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792764; cv=none; d=zohomail.com; s=zohoarc; b=jK7VZ/hCtTDJU0I0T+nOoAyk6XXqXUc2p5rd1J6dQMIAIzDgqdkWtLtT+YAP0AWbBBAY5ifshxcwxqM45KXXmfN4bd8ARr65rqg0yQYvw6VozTUl2Fqsa6JzjdiYMMQdblOMPJga+hDjCc1h8ypt9OL89DRCZl6hN+QYz/UgDDg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792764; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UPlI92zXqreIEPb7PmskMpI4JW+xZWPxZMuY9l3rRHw=; b=gYkxZIqTOYAcVGIh2karx7GQnZ5x1kgVWN/2DI+o0Luxb9SffyeOkhm3GBD+VmLzl8Zrzc1SH0gXoF4ptSkeWQq3ltv5ayw8+gB3HAMJvVu1hjD1hlQOLk9gO1MCjtbmvKZrlG6eFz/QIrYwX+FewfD+++KPysmMglWZb96SIK8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792764267313.94929594014525; Thu, 11 May 2023 01:12:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Is-00071r-4J; Thu, 11 May 2023 04:05:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1In-0006hl-Dt for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:30 -0400 Received: from mail-ed1-x535.google.com ([2a00:1450:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IZ-00012r-2l for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:29 -0400 Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-50b9ef67f35so14689890a12.2 for ; Thu, 11 May 2023 01:05:14 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792313; x=1686384313; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UPlI92zXqreIEPb7PmskMpI4JW+xZWPxZMuY9l3rRHw=; b=D8XgrftACu3svwWQyItFhNhBWXtHNuGVKhdsPe2jktZ4zS8sgwCuyhOIEbH5rigPgn zPexQ65kQKS75c9anlKTYzVqbAZY0kMLAJ1XEOk3v1pJ7lKDLWXNKjHmhrMRbSrnIDtk jzmLobgJRYWO9c+MQkSac2AneVaDrBBCwiEraBGnej/KOJCH5OS6XqzcSCwXHW0y9OqQ s9Pl298vYePo0KtRLxOOELUjr0psCPCymZck5qiEHC1Weq65dqGw3AJ/YlOGqZUkfD/U WDsZyRunTcegJ3N54sdBY/r+qMZ5BVs+WJCjVF7QX8zrvQ/s9PuAmga6N/Yfv21Dyl92 QtuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792313; x=1686384313; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UPlI92zXqreIEPb7PmskMpI4JW+xZWPxZMuY9l3rRHw=; b=fEZ5Jryq/kYiZIN8ASL87YVq0+TFr24SHG5+PmcQd3u6xqQQ9Xorr0uXo6RHb87p7T OCPqAXudA3CILXl9TulcDvy+ECgSem2YFTgvBivl9D6eVaxE1NWatVkkXDPnAL8UOwDX 78s3iA7KxadgHEiX13RPEhCfdS72R/thK9TIbGfgGozQQa6dYTRERQC1KUYX2RfGZ+H4 eRflOxCuXKipdpR3TM7bD9SCiXEmNn4GeZR+a5AldpclJEE42+4knW4+aWhi9JieoObL vkyiVlSlzY1RHqdfIbfupfouaLPvISoYeSOrIzIZvubUMnKk3yqy3U91f7BMboGR1G2F hqxQ== X-Gm-Message-State: AC+VfDzKF2b853PWwFmYsGC0tz8eGCHbMwLvrk0XBa7JeJFUd49fD23w 35B+rhM+xVfpaeksTRMzmKfUyjNdinc1z78xFDvA+w== X-Google-Smtp-Source: ACHHUZ4Xi+3KZaGHpTLvhwmfdNOCyExxeOOTVK0fYbGA2xE1jg9M+ClpkQLkVwZq0qY/qYkJR3l3wA== X-Received: by 2002:aa7:c517:0:b0:504:b0d2:76c with SMTP id o23-20020aa7c517000000b00504b0d2076cmr17727039edq.32.1683792313491; Thu, 11 May 2023 01:05:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Daniel Henrique Barboza Subject: [PULL 34/53] tcg/ppc: Reorg tcg_out_tlb_read Date: Thu, 11 May 2023 09:04:31 +0100 Message-Id: <20230511080450.860923-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792765604100001 Allocate TCG_REG_TMP2. Use R0, TMP1, TMP2 instead of any of the normally allocated registers for the tlb load. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 78 ++++++++++++++++++++++++---------------- 1 file changed, 47 insertions(+), 31 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 4c479fdece..dbba304e42 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -68,6 +68,7 @@ #else # define TCG_REG_TMP1 TCG_REG_R12 #endif +#define TCG_REG_TMP2 TCG_REG_R11 =20 #define TCG_VEC_TMP1 TCG_REG_V0 #define TCG_VEC_TMP2 TCG_REG_V1 @@ -2015,13 +2016,11 @@ static TCGReg ldst_ra_gen(TCGContext *s, const TCGL= abelQemuLdst *l, int arg) /* * For the purposes of ppc32 sorting 4 input registers into 4 argument * registers, there is an outside chance we would require 3 temps. - * Because of constraints, no inputs are in r3, and env will not be - * placed into r3 until after the sorting is done, and is thus free. */ static const TCGLdstHelperParam ldst_helper_param =3D { .ra_gen =3D ldst_ra_gen, .ntmp =3D 3, - .tmp =3D { TCG_REG_TMP1, TCG_REG_R0, TCG_REG_R3 } + .tmp =3D { TCG_REG_TMP1, TCG_REG_TMP2, TCG_REG_R0 } }; =20 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) @@ -2135,31 +2134,31 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_AREG0, table_off); =20 /* Extract the page index, shifted into place for tlb index. */ if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_shri32(s, TCG_REG_TMP1, addrlo, + tcg_out_shri32(s, TCG_REG_R0, addrlo, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); } else { - tcg_out_shri64(s, TCG_REG_TMP1, addrlo, + tcg_out_shri64(s, TCG_REG_R0, addrlo, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); } - tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1)); + tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0)); =20 - /* Load the TLB comparator. */ + /* Load the (low part) TLB comparator into TMP2. */ if (cmp_off =3D=3D 0 && TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { uint32_t lxu =3D (TCG_TARGET_REG_BITS =3D=3D 32 || TARGET_LONG_BIT= S =3D=3D 32 ? LWZUX : LDUX); - tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4)); + tcg_out32(s, lxu | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2)); } else { - tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4)); + tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2)); if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off = + 4); - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, + TCG_REG_TMP1, cmp_off + 4 * HOST_BIG_ENDIAN); } else { - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off); + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off= ); } } =20 @@ -2167,11 +2166,12 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, * Load the TLB addend for use on the fast path. * Do this asap to minimize any load use delay. */ - h->base =3D TCG_REG_R3; - tcg_out_ld(s, TCG_TYPE_PTR, h->base, TCG_REG_R3, - offsetof(CPUTLBEntry, addend)); + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, + offsetof(CPUTLBEntry, addend)); + } =20 - /* Clear the non-page, non-alignment bits from the address */ + /* Clear the non-page, non-alignment bits from the address in R0. */ if (TCG_TARGET_REG_BITS =3D=3D 32) { /* * We don't support unaligned accesses on 32-bits. @@ -2204,9 +2204,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, if (TARGET_LONG_BITS =3D=3D 32) { tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); - /* Zero-extend the address for use in the final address. */ - tcg_out_ext32u(s, TCG_REG_R4, addrlo); - addrlo =3D TCG_REG_R4; } else if (a_bits =3D=3D 0) { tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS= ); } else { @@ -2215,21 +2212,36 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BIT= S, 0); } } - h->index =3D addrlo; =20 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, + /* Low part comparison into cr7. */ + tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 0, 7, TCG_TYPE_I32); - tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32= ); + + /* Load the high part TLB comparator into TMP2. */ + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1, + cmp_off + 4 * !HOST_BIG_ENDIAN); + + /* Load addend, deferred for this case. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, + offsetof(CPUTLBEntry, addend)); + + /* High part comparison into cr6. */ + tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_TMP2, 0, 6, TCG_TYPE_I= 32); + + /* Combine comparisons into cr7. */ tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); } else { - tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, + /* Full comparison into cr7. */ + tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 0, 7, TCG_TYPE_TL); } =20 /* Load a pointer into the current opcode w/conditional branch-link. */ ldst->label_ptr[0] =3D s->code_ptr; tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); + + h->base =3D TCG_REG_TMP1; #else if (a_bits) { ldst =3D new_ldst_label(s); @@ -2247,13 +2259,16 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, } =20 h->base =3D guest_base ? TCG_GUEST_BASE_REG : 0; - h->index =3D addrlo; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); - h->index =3D TCG_REG_TMP1; - } #endif =20 + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + /* Zero-extend the guest address for use in the host address. */ + tcg_out_ext32u(s, TCG_REG_R0, addrlo); + h->index =3D TCG_REG_R0; + } else { + h->index =3D addrlo; + } + return ldst; } =20 @@ -3905,7 +3920,8 @@ static void tcg_target_init(TCGContext *s) #if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS =3D=3D 64 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ #endif - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1); tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2); if (USE_REG_TB) { --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792736; cv=none; d=zohomail.com; s=zohoarc; b=QUSGD7h94dhYfHfYXisbIEHP4EITirEfJwtekOztND39YF352JKodT85UybiRTPmYYb/Mu2PHQtpkfXwe9QLvfpz666uENSu9EI1rwhaAaY14wS5Rmd6R3AbyLpnDDslO1ywfQrv7U+ZrMQ7t1jnsUcDxr1b/PmkyxcEbAI4QEo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792736; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=06h6yvJMyKq5VclqGY9lkGTNGgWZsKct+6eNF1BuBvk=; b=YNLyLbkNBjhnIEDEQmVNLeIqg1WDOkgJCaEZ4nGFzDP4vU4VmGVhYqOFQdNxetfuDI7IOeSocm9N8dk+JZeNEVbhG10hn9NXLZb6fE8tG3gpKyY2Ow8LTonjPi6+PpFNpx9dmnAz/weCSpxF036EfyC+A9xnFiieDwQCeeDmXO0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792736675722.1667292669432; Thu, 11 May 2023 01:12:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1JD-0007Ot-6l; Thu, 11 May 2023 04:05:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Il-0006eY-Ap for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:27 -0400 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IZ-000134-Ki for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:27 -0400 Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-9661047f8b8so1099438966b.0 for ; Thu, 11 May 2023 01:05:15 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792314; x=1686384314; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=06h6yvJMyKq5VclqGY9lkGTNGgWZsKct+6eNF1BuBvk=; b=WOfBHWh+4mMELfetvEQp4VkdVBiJmvYklAAbZtIcNoiMgZuAQy6vi/YPe21yJhFKHk Wo3AfsxhE/rJxNpX3S7PxV5Lw50U9QTZJwbzfRdb4dMaOoG4YyqoWcPfN3XmiEyCMMsd DivZsHa9yjV/ZpPiHITYAeKXBGZA1j9AP1pkoeYXzhxLDtWAHv3wbqPU971eT7o4Qrof lno3fuotzzwxtEw0IcdjLjGyBgXpGMXnbKeEl7SeW3tnqM+SsPDGSikc8I1OFKZ4f4ZD B1HCEypPAEvGJKBycw2DOtA1mrLn6FJMsptBVaAHPwhhHFIFF0p7GRoVR+oRS09qoQAN Yb7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792314; x=1686384314; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=06h6yvJMyKq5VclqGY9lkGTNGgWZsKct+6eNF1BuBvk=; b=QSJR6NOJ85zDcycy5W8Rd287sjgPSUVLAdQLGEuGWOs7aoZggQj2h0e0W4nNVfCY6I Vgz+K0zm/8FKIElHv+9eXRzElWZpYknWmY5ocpLTNZsFY+vraXuUu2wbZR/XZzp/ocQB aoomOTBV1xfvsB/1xCwosAn9+SSW0GVGDN9QbnoKeJ9tUMDoi940sgOIBV+ig2ZBsTPt i7o3/y6ucFBqI5q0XKM1ajL3DbSWdIlpCZ56TWoa5cQmYt5CfrRBoH8TWt9LRcdyS42o UO79xEvU7r0GCzRLb8hSnwhhqZsSNRvo281tJLLhw6rJ018ds+p21BeuzalInsB26rXI HIlQ== X-Gm-Message-State: AC+VfDxtOtPHn3dt3xcg/fs6JdljxZVfF1kyDwlPU68+PO3Z0rpBRsfY pFpPq1+oygK7D4IT/fovleFQXvCOjmB0Ve7m0Nt54g== X-Google-Smtp-Source: ACHHUZ4aFzoZ/bKXPPeNdL05Xfo4+IloS0Nl7GLN00OGKObM5WvcAqg16G41Tsq7A1TDNFBLUGrdqw== X-Received: by 2002:a17:907:971d:b0:966:d59a:4ba6 with SMTP id jg29-20020a170907971d00b00966d59a4ba6mr14574983ejc.43.1683792314064; Thu, 11 May 2023 01:05:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Daniel Henrique Barboza Subject: [PULL 35/53] tcg/ppc: Adjust constraints on qemu_ld/st Date: Thu, 11 May 2023 09:04:32 +0100 Message-Id: <20230511080450.860923-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792737443100001 The softmmu tlb uses TCG_REG_{TMP1,TMP2,R0}, not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h | 11 ++++------- tcg/ppc/tcg-target-con-str.h | 2 -- tcg/ppc/tcg-target.c.inc | 32 ++++++++++---------------------- 3 files changed, 14 insertions(+), 31 deletions(-) diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h index a1a345883d..f206b29205 100644 --- a/tcg/ppc/tcg-target-con-set.h +++ b/tcg/ppc/tcg-target-con-set.h @@ -12,18 +12,15 @@ C_O0_I1(r) C_O0_I2(r, r) C_O0_I2(r, ri) -C_O0_I2(S, S) C_O0_I2(v, r) -C_O0_I3(S, S, S) +C_O0_I3(r, r, r) C_O0_I4(r, r, ri, ri) -C_O0_I4(S, S, S, S) -C_O1_I1(r, L) +C_O0_I4(r, r, r, r) C_O1_I1(r, r) C_O1_I1(v, r) C_O1_I1(v, v) C_O1_I1(v, vr) C_O1_I2(r, 0, rZ) -C_O1_I2(r, L, L) C_O1_I2(r, rI, ri) C_O1_I2(r, rI, rT) C_O1_I2(r, r, r) @@ -36,7 +33,7 @@ C_O1_I2(v, v, v) C_O1_I3(v, v, v, v) C_O1_I4(r, r, ri, rZ, rZ) C_O1_I4(r, r, r, ri, ri) -C_O2_I1(L, L, L) -C_O2_I2(L, L, L, L) +C_O2_I1(r, r, r) +C_O2_I2(r, r, r, r) C_O2_I4(r, r, rI, rZM, r, r) C_O2_I4(r, r, r, r, rI, rZM) diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h index 298ca20d5b..f3bf030bc3 100644 --- a/tcg/ppc/tcg-target-con-str.h +++ b/tcg/ppc/tcg-target-con-str.h @@ -14,8 +14,6 @@ REGS('A', 1u << TCG_REG_R3) REGS('B', 1u << TCG_REG_R4) REGS('C', 1u << TCG_REG_R5) REGS('D', 1u << TCG_REG_R6) -REGS('L', ALL_QLOAD_REGS) -REGS('S', ALL_QSTORE_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index dbba304e42..fa016c02ee 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -93,18 +93,6 @@ #define ALL_GENERAL_REGS 0xffffffffu #define ALL_VECTOR_REGS 0xffffffff00000000ull =20 -#ifdef CONFIG_SOFTMMU -#define ALL_QLOAD_REGS \ - (ALL_GENERAL_REGS & \ - ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5))) -#define ALL_QSTORE_REGS \ - (ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \ - (1 << TCG_REG_R5) | (1 << TCG_REG_R6))) -#else -#define ALL_QLOAD_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3)) -#define ALL_QSTORE_REGS ALL_QLOAD_REGS -#endif - TCGPowerISA have_isa; static bool have_isel; bool have_altivec; @@ -3754,23 +3742,23 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_qemu_ld_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O1_I1(r, L) - : C_O1_I2(r, L, L)); + ? C_O1_I1(r, r) + : C_O1_I2(r, r, r)); =20 case INDEX_op_qemu_st_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O0_I2(S, S) - : C_O0_I3(S, S, S)); + ? C_O0_I2(r, r) + : C_O0_I3(r, r, r)); =20 case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) - : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(L, L, L) - : C_O2_I2(L, L, L, L)); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) + : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(r, r, r) + : C_O2_I2(r, r, r, r)); =20 case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(S, S) - : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(S, S, S) - : C_O0_I4(S, S, S, S)); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(r, r) + : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(r, r, r) + : C_O0_I4(r, r, r, r)); =20 case INDEX_op_add_vec: case INDEX_op_sub_vec: --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792392; cv=none; d=zohomail.com; s=zohoarc; b=MsVTyKUDHRnNY8iPWoUMnFyIAzTDDwS9J7cD5p94WMEHB92e9NphJcbvoBMrBi7kEjnFKzg/yINHSmwiVzOly6YiafsEfyzSN+nIyF3zrPAw0T743lVisW5cqrC/JdFSzzhB7FTaEZYeKdcLESpcCvdjlL3Y1D/LWW3a1+cZdkQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792392; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9OBWczxe5h53DTHTDxSKKonJLPbtryLCHBXLUcxswCo=; b=hor1Wh6m8DZgIpMehxR/pbPl/e/U0xnq2M4dqRRC9dgeaZ0eNv5k4B0LE6OptvO3+2rk4Z7iEl56AAuPLQFcvv8E5YskKNrhvCQ1u2cd+gHWCAM/zD5GDQBuaD+pKfPontmcSRNz1J4ZabmeNRzaz2xRSbUDnAw1oFvEnRV3rHQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792392949615.2476871624509; Thu, 11 May 2023 01:06:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Is-00072o-FZ; Thu, 11 May 2023 04:05:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Ik-0006e4-To for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:27 -0400 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1IZ-0000x5-EW for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:26 -0400 Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-50bcb4a81ceso14613694a12.2 for ; Thu, 11 May 2023 01:05:15 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792314; x=1686384314; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9OBWczxe5h53DTHTDxSKKonJLPbtryLCHBXLUcxswCo=; b=nP3eyBSWtMqwFJbFkMkh/+vp+qTyqHp4G/hcDnCFsiWCTH82TieP6Nsd5LOn7oKZtu hEGOxrrLjg7aGziFgfnOGmUqOqop8bbGjlS9XHpAueqTMnUzfadPp6gFZlDzenKgGH+r uhf3Ko9AxtcVM43lEsBoLbJHDzfNaHnvbfmW4GyNQ0D4Ju7/+3stmP3TD8OHd+2vvf5P 3XqxzqNuzkEIB+tsWbmY5Bhq+FyAMz6K1hanQAweCGl28v9gxC1cmKvs1fUQwo0lF1dt uAnaHVWRoQAv59yfVX7J3SxT0zON1wS1yxj+6fulOEZUo2zL/wDVrD2RSpTGSUYwnNNf w04w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792314; x=1686384314; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9OBWczxe5h53DTHTDxSKKonJLPbtryLCHBXLUcxswCo=; b=fCqvdhByRmqaWKj6vWzhl8R/+Lf9z1j4608TnUM0/Q9UMGUM06klhCDhp+pW+Y0mQd asOJLws6kMBwguycJ7hkFiUoS8Xbs3vBGPd0fbmKL6DXbC8CE1BNG5KDY0PD+Cgmmi4A hum99ac/QTbRJ0zu6DOxFY12crGaR3lwKARq1EZdkb8Y6E1vBTgzNC3TjHXuL3xeOgCL VN9QoVaKB8O5ntRvSLMspCMf7pWfDSJ2tQYx4PaqcJjMzvVTKatGFJc0N+0GqfyApwOI qptb35o9ZkBuCNZpRkfDGnvcQwcfzlP0QVRxFO2GAP6iS5X0CIwpbUDHDa7YxKU43WLN QFvg== X-Gm-Message-State: AC+VfDwAEsfDpy6y2uVnnH8H2av8KdNAYt48ObIwjFXQ0QPdyIVBKC4/ FhYn9UWkPtohgVcgwmnyA7IrhlKrDnOGEkOfVhwdPQ== X-Google-Smtp-Source: ACHHUZ4k2hMvspZaXrx8DTb15939ozrH40LK7h7bzwKbWBAeY6v6tJDmQqKZKNm1t1iBkm5jFoJhcQ== X-Received: by 2002:a50:ed99:0:b0:50b:d5cd:612e with SMTP id h25-20020a50ed99000000b0050bd5cd612emr15383180edr.3.1683792314664; Thu, 11 May 2023 01:05:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 36/53] tcg/ppc: Remove unused constraints A, B, C, D Date: Thu, 11 May 2023 09:04:33 +0100 Message-Id: <20230511080450.860923-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792394727100002 These constraints have not been used for quite some time. Fixes: 77b73de67632 ("Use rem/div[u]_i32 drop div[u]2_i32") Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-str.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h index f3bf030bc3..9dcbc3df50 100644 --- a/tcg/ppc/tcg-target-con-str.h +++ b/tcg/ppc/tcg-target-con-str.h @@ -10,10 +10,6 @@ */ REGS('r', ALL_GENERAL_REGS) REGS('v', ALL_VECTOR_REGS) -REGS('A', 1u << TCG_REG_R3) -REGS('B', 1u << TCG_REG_R4) -REGS('C', 1u << TCG_REG_R5) -REGS('D', 1u << TCG_REG_R6) =20 /* * Define constraint letters for constants: --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792770; cv=none; d=zohomail.com; s=zohoarc; b=Ac4krTtnwOVA06Trd6NX6hyKzhjfP2rOr+D8KAJSANYuUgHIekzll0ZkpW+b4LNXHPXcA2sigTPoAOdWMo2t4aZdW/b4Cmee7cgOs+9M2ZyHOW5lsIx6m+nXwqCZTXTOfn8si2wOFWVzDRHA01YTEqqJUEQ/qK8Uy5TX61jao50= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792770; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QU1syb+cc4YKGCG4Z49Hidz1m6+KfeR1vmxnC8mNNIs=; b=P86JZySPyMwoQ1qJ2++th02TTWtatyrRjKkQxZ4lAMArbqWlMl7hwqv46HeH4QUfrnuOS0hJ3bsjUEQwOlfFgoLZkTWF18DcrrN5y2Yz6qbo/HK78L6+NLJF+1/1g0qInFQ1D4mCx7ZS7uKGXCM/jLhJJiNdSRfWSVLTS+fyORE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168379277096852.84892620632297; Thu, 11 May 2023 01:12:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1JE-0007Rw-Fk; Thu, 11 May 2023 04:05:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Im-0006gE-Dg for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:28 -0400 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1Ia-00013H-Hu for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:27 -0400 Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-50c8d87c775so10951898a12.3 for ; Thu, 11 May 2023 01:05:16 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792315; x=1686384315; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QU1syb+cc4YKGCG4Z49Hidz1m6+KfeR1vmxnC8mNNIs=; b=jcIpcVMy0YbzCFwfBRLc1zrex+zsXqq9HSXo57XLJ10DjQgu7ElI2XxBgs1wBveVQO DUR1Ph/PcCA3a3xfP/O8AB1awXAsq7UBrqQjEaHjKspOOMcGY4f9fSC6034q+4Sum7k6 /xuS4wuDNgOFoLTdeYkDrkM5pmaFcgKvuTHNUbxs0bNypDDTC5VWmdSu5FHi4QHb0Gye sviAI/2LJuXpsX65ufR6OczoBo19tC9B+rNMdD2xFvEdNFdynIvVNUil57eF6tomdVnN xyMEYJ7gmQgMVhlFNNk++BGty9Ji890lu1YhXZK2jyRxM8B0KMaNd1/Y5GMgCzvNBc9u oQyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792315; x=1686384315; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QU1syb+cc4YKGCG4Z49Hidz1m6+KfeR1vmxnC8mNNIs=; b=k21XHe0U1ppra+0piwEos3TRjDvVbxKiaKFfrfcsxMzgEZdqHlHhM0YZBGPOPdK70D kJ048UNe+IaE3getlNBfxyA+csZ6H1IW1y60x2BeWqyaLVmTeya6knwNOBW0ExyvxbzR SChem0ptp0CF4G4Izx4pL0QLiMBzsm1nj9yR4vglMWYLLsAzVPAvzG0vU/TWGVYBG6m5 gXkX0Wgu7CX0vIvz2lRDJ7elns33B513ovKE1HDNsVOMMAGoYd6fm3PBYBolSLOM+wus A6AiQtXLwe10YcrvRlTy6vE4ctttDm8Ffyuzs+Rz3ohN5EdMI7E5O93UUe11bSkwS/vA 2gcg== X-Gm-Message-State: AC+VfDzLXmzC3zP5zH0fgLCS+Pv4LUoZWyWFUmjXdOyvxDLVywvJ9vxb gQPpVoruIClYIobWNYFhaYBlXGWe/pfOJlJdBrfz0g== X-Google-Smtp-Source: ACHHUZ6iiyZFlPJNVbkuIMjEgjsrzDJYFraAOPQjbVlt389DB553EyYUY+7EyhxB+SGwdW2658NZng== X-Received: by 2002:aa7:d705:0:b0:50d:8c5b:86b with SMTP id t5-20020aa7d705000000b0050d8c5b086bmr15355053edq.21.1683792315238; Thu, 11 May 2023 01:05:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 37/53] tcg/ppc: Remove unused constraint J Date: Thu, 11 May 2023 09:04:34 +0100 Message-Id: <20230511080450.860923-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792772220100001 Never used since its introduction. Fixes: 3d582c6179c ("tcg-ppc64: Rearrange integer constant constraints") Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-str.h | 1 - tcg/ppc/tcg-target.c.inc | 3 --- 2 files changed, 4 deletions(-) diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h index 9dcbc3df50..094613cbcb 100644 --- a/tcg/ppc/tcg-target-con-str.h +++ b/tcg/ppc/tcg-target-con-str.h @@ -16,7 +16,6 @@ REGS('v', ALL_VECTOR_REGS) * CONST(letter, TCG_CT_CONST_* bit set) */ CONST('I', TCG_CT_CONST_S16) -CONST('J', TCG_CT_CONST_U16) CONST('M', TCG_CT_CONST_MONE) CONST('T', TCG_CT_CONST_S32) CONST('U', TCG_CT_CONST_U32) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index fa016c02ee..29bfbfcc61 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -83,7 +83,6 @@ #define SZR (TCG_TARGET_REG_BITS / 8) =20 #define TCG_CT_CONST_S16 0x100 -#define TCG_CT_CONST_U16 0x200 #define TCG_CT_CONST_S32 0x400 #define TCG_CT_CONST_U32 0x800 #define TCG_CT_CONST_ZERO 0x1000 @@ -270,8 +269,6 @@ static bool tcg_target_const_match(int64_t val, TCGType= type, int ct) =20 if ((ct & TCG_CT_CONST_S16) && val =3D=3D (int16_t)val) { return 1; - } else if ((ct & TCG_CT_CONST_U16) && val =3D=3D (uint16_t)val) { - return 1; } else if ((ct & TCG_CT_CONST_S32) && val =3D=3D (int32_t)val) { return 1; } else if ((ct & TCG_CT_CONST_U32) && val =3D=3D (uint32_t)val) { --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792428; cv=none; d=zohomail.com; s=zohoarc; b=Wecx44I5sWBWz2icXWXrdOZJNFrfeaqQ8VcjZJ8fLsNSHaraaN0xGXK8unkzy4XvgFA6YhPRTVAyycdFIC95VHbmrNxwSxNynG6W8oZ5xLscilCIathdmWK9cdfs/yNtll1/+4Z2ed3DoBdo/jBgUM0mP9oLMUN0maQd2nTR0og= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792428; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YsEP/yJKwRseCt1X5kVWTrfw+UMz9PZRzJRXfMcyJV8=; b=GAbELssDfz/ix+vDufhFisIlTHyS0aNkW23XQWeRA2I+7SYS6aeLDg5QH2B9gQFz/ucLyMk6nvqcBcDCWSvDwSP/0w/wdgL1zwFcT/89s6voocWF4yuIdqFONkNfvc7kg9b3D4x9bPu6fro9lPFr/rsn/yOculBKfrTu3coneRg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792428727601.3870090444835; Thu, 11 May 2023 01:07:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1J8-0007Hp-7q; Thu, 11 May 2023 04:05:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1In-0006hx-Sh for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:30 -0400 Received: from mail-ed1-x52e.google.com ([2a00:1450:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1Ib-00013R-Bg for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:29 -0400 Received: by mail-ed1-x52e.google.com with SMTP id 4fb4d7f45d1cf-50db7f0a1b4so4809924a12.3 for ; Thu, 11 May 2023 01:05:16 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792316; x=1686384316; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YsEP/yJKwRseCt1X5kVWTrfw+UMz9PZRzJRXfMcyJV8=; b=EHxdL+/Zp4j8jQobbL+UE3dnjSUOvI/eaFYeRm+RUmfGBX3jP68BoXb1qrEfbEGC4Z +Ufjp2AEvpBW8GGHUk3XbRWnF0rulqVWNg6MozIqw3F8UnsEMIP4zUyNzZjWmlUqpr7r kVVOu6WTEQ5F3Of3P2h5UsHzJI/tgTX/+ilb7/a3/z/S2GuS4imnlXI9sZC8vOus35aF WHU53+iIaSzg+JnghnetvnJBEJThXw+WSIBqHEOSffFq54X8BNDXNfVDeulsWb+yiWde vcONq6I9er4gpp6A8MOOCJZhsu+CwwLlCxvmMPBpTQ9RQKoSRPusl8JgfTwbUir241fO CdZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792316; x=1686384316; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YsEP/yJKwRseCt1X5kVWTrfw+UMz9PZRzJRXfMcyJV8=; b=J6uEOvXIpbreR96yo+u5rQyqdRoY1S45QPKSnc3EfOxhrKw2b3jRkQwmapBfbE/n1s Hx9EMAI/+zLL2xWLCGjSftDMVZuUCTexTVNLTAH8kQsTAY3xdFkWyeiBTN/+3Pxmih/b QIJ7rbp3UeKHGGlLFOs3g51LaIEfd5Xts7ind7pBim05L9rUGIEWrN86Lvolmee93N0p YE4/2q5Frt696BCCb+pdYBq3OmPz9UKHuCGwhzCjQHTJPOIUurw/H807L97P2v6vPeH9 5qPArDA4JPuCyKs15gZK+LcHMKQovSoWxewTDyW1hDOyTq9xXcSeFeKGxrURkChnDUk8 j7JA== X-Gm-Message-State: AC+VfDyP7SPhuZLnacztrefuorjSruI6uQ7Il50r/xBoJgZ7cqRaB8eP NsRjkfFrHDSAviM+oJOd//YmZi4SL+TG/0UWCUjZRQ== X-Google-Smtp-Source: ACHHUZ7KQHpKfYVvCXVhUmElB7sSbtT9iYKsHH0wRJbt+f8hn9kf68xe/TnC7rcV1dbLBqkb6wTYNg== X-Received: by 2002:a50:ee0f:0:b0:504:9349:7901 with SMTP id g15-20020a50ee0f000000b0050493497901mr15162896eds.38.1683792315828; Thu, 11 May 2023 01:05:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Daniel Henrique Barboza Subject: [PULL 38/53] tcg/riscv: Simplify constraints on qemu_ld/st Date: Thu, 11 May 2023 09:04:35 +0100 Message-Id: <20230511080450.860923-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792428998100001 The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 2 -- tcg/riscv/tcg-target-con-str.h | 1 - tcg/riscv/tcg-target.c.inc | 16 +++------------- 3 files changed, 3 insertions(+), 16 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index d4cff673b0..d88888d3ac 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -10,10 +10,8 @@ * tcg-target-con-str.h; the constraint combination is inclusive or. */ C_O0_I1(r) -C_O0_I2(LZ, L) C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) -C_O1_I1(r, L) C_O1_I1(r, r) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h index 8d8afaee53..6f1cfb976c 100644 --- a/tcg/riscv/tcg-target-con-str.h +++ b/tcg/riscv/tcg-target-con-str.h @@ -9,7 +9,6 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) -REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index c22d1e35ac..d12b824d8c 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -125,17 +125,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKi= nd kind, int slot) #define TCG_CT_CONST_N12 0x400 #define TCG_CT_CONST_M12 0x800 =20 -#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) -/* - * For softmmu, we need to avoid conflicts with the first 5 - * argument registers to call the helper. Some of these are - * also used for the tlb lookup. - */ -#ifdef CONFIG_SOFTMMU -#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5) -#else -#define SOFTMMU_RESERVE_REGS 0 -#endif +#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) =20 #define sextreg sextract64 =20 @@ -1600,10 +1590,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return C_O1_I1(r, L); + return C_O1_I1(r, r); case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - return C_O0_I2(LZ, L); + return C_O0_I2(rZ, r); =20 default: g_assert_not_reached(); --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792734; cv=none; d=zohomail.com; s=zohoarc; b=aFzHlPBWgjW/7xLH5iytO7yrRR/nl3yyZC/bvHyHlILP96/Ub50+UBi/HePqQAAoayo4EQD+ppfaLrWP6wuk+WixQwyx0MZjbP/Kzwpyyfy5zi3wqsbgSjCqJXZNYp0mIp3EwnWNSEPAhHRaOGX6xR7x9fkJYdZF6ZlCmDd8zk0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792734; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=z9dBosImySTxw+alMraFP8+RgZnXakczEY05QormSAI=; b=jUs7N+EtUweY6kvYoNZu3kdgoleon0NFij0tGKjm8G8rEoVM7XJAcyCeCOuVF8/nJHeyOTlbOveOzN3/1x1VnQtMJzcHZFrmr62v3P2ucFHYylEyvMIo2NybAOg1LAIHz9AZcYpNFYb5rA08+cJVw/pNkrJpcwMwJ/dmdQWGeAw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792734081984.2221286465196; Thu, 11 May 2023 01:12:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1JG-0007UP-87; Thu, 11 May 2023 04:05:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Im-0006gz-Kl for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:29 -0400 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1Ic-00016C-80 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:05:28 -0400 Received: by mail-ed1-x52b.google.com with SMTP id 4fb4d7f45d1cf-50b8d2eed3dso12546869a12.0 for ; Thu, 11 May 2023 01:05:17 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id i12-20020aa7c70c000000b0050bd7267a5csm2662095edq.58.2023.05.11.01.05.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:05:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792316; x=1686384316; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=z9dBosImySTxw+alMraFP8+RgZnXakczEY05QormSAI=; b=YkAmARu+C0e4WFskePgIaWMTDdtuqmyjl3Dusjf3iYYhlk9ZSTeU0WEdGFGfenWw5v epeAu7yn1XqAJGDLTFY5S4xo8X5ibMktpyEvPz95uBmYQwAqwUcrpNPgSblvxRkPJ/qr X8porZgVhkkLh3skKe4B81TTkSvPKMgw6toTK6isGbzNL/SheeX/Pg6EcmapLa1I+fRw lsR/Nka36L4opDgNEknrM0yepPLWSIvrt7aod7vRrsq1/WkXkPIyz0RCLZYLhhikBDBJ AptC4oj7s/+tgLAgCD9N6sAQ1ipCQfjTQJ4VT3OSLfFYTJ/5FlyuPaKHLdTrcp+MHyP4 ygPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792316; x=1686384316; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z9dBosImySTxw+alMraFP8+RgZnXakczEY05QormSAI=; b=dq0UuN8hF0FudexOAR7kpHPJdHYNj+/e8SBCu0BTtEm8Zi6hZzHs2H7p5WRYJzAQe4 9R+0BANJAX+NBSBa3tDej6c+kfML+snet1qHmgcBd3IoLLg4xkUde4HfTFZg4YTKDqHP r/4cbMqLpQRsLAvuYNsIueJf4WWoBFRfgHmK8SzhCrI213+2lx0QZpgbiOiVx1k8r11+ RX5YA+V1HMlWZxKvuBG8oCHasDPJ/wSWOenI3GO9fGZtRmYJ4M/hpMcx68Su1yBisjXw Z48jbiwSLERQJwjXaLCRWoy1k/Ni+FJ+sCwzq1MusBmC9ve+XW5tGfxi0ymcUibHvr6B wiLA== X-Gm-Message-State: AC+VfDzxufmBuPBT+MyYPr53aLijBd3h7QbyH2qC2RjQIbOqGLEBsDei h72bXY8LPXXN7Idw6Svt3+hh+oEvW5KVOe6q8d7r5Q== X-Google-Smtp-Source: ACHHUZ6a/a21INyVQnJgvRWUjv/gtEzGGDGMaz5v5gvsieIM4gJCo1V3K5Isx7JMfOpJVTd1lwn/EA== X-Received: by 2002:aa7:dd11:0:b0:506:2c70:3066 with SMTP id i17-20020aa7dd11000000b005062c703066mr15776826edv.21.1683792316327; Thu, 11 May 2023 01:05:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 39/53] tcg/s390x: Use ALGFR in constructing softmmu host address Date: Thu, 11 May 2023 09:04:36 +0100 Message-Id: <20230511080450.860923-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792735341100001 Rather than zero-extend the guest address into a register, use an add instruction which zero-extends the second input. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index dfcf4d9e34..dd13326670 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -149,6 +149,7 @@ typedef enum S390Opcode { RRE_ALGR =3D 0xb90a, RRE_ALCR =3D 0xb998, RRE_ALCGR =3D 0xb988, + RRE_ALGFR =3D 0xb91a, RRE_CGR =3D 0xb920, RRE_CLGR =3D 0xb921, RRE_DLGR =3D 0xb987, @@ -1853,10 +1854,11 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, tcg_out_insn(s, RXY, LG, h->index, TCG_REG_R2, TCG_REG_NONE, offsetof(CPUTLBEntry, addend)); =20 - h->base =3D addr_reg; if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_R3, addr_reg); - h->base =3D TCG_REG_R3; + tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg); + h->base =3D TCG_REG_NONE; + } else { + h->base =3D addr_reg; } h->disp =3D 0; #else --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792804; cv=none; d=zohomail.com; s=zohoarc; b=YM/Cq9hJt0EVVtHR6EIDvbSRp04c9oXj4e+VLWAsy4b8M7c+FePMzWBiB/gNqhgBeejld33vlUcVFRwvw2QTfcnOp/SuSRukklcrEZWx3j8eKjP17PnWJCm+IGl2Ieqt6DSdCqiww/MJalvkrWBF+3vPidsvRx1RZuV7elQXjaw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792804; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cISiYMnSQzGuCQgPP8NYpc1CLEOshSGVWmc3Y1xiUV8=; b=fhk5CJOqboNmbW49QqDQWRAd//i3caDYD9pJOjYYK58c+gjQnCAkXwWoTgvEL5ClZB1hoIW6qrXluFqSOvWQueJTB4XgF8enS3bbx9apDmKmc3YeljWKFX3QdTDpR1Abyw8kzqvWmuZEvQqcMuH3bAqsN6yITE8XizW532G+DW4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792804958811.7660871794977; Thu, 11 May 2023 01:13:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1La-0007F0-UI; Thu, 11 May 2023 04:08:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1LY-0007Dl-PL for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:20 -0400 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1LW-0001wd-UA for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:20 -0400 Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-9661a1ff1e9so905601966b.1 for ; Thu, 11 May 2023 01:08:18 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b00959c6cb82basm3635225ejc.105.2023.05.11.01.08.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:08:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792497; x=1686384497; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cISiYMnSQzGuCQgPP8NYpc1CLEOshSGVWmc3Y1xiUV8=; b=oov+8Ws/1geVMPC29TUrOY0JeeOcHT8dgamDln7P7Hm5aOtlPnBzWMElDajBaMJTdB nwUqA74D7fUW/lgnkQNnyUNWKKEsNjptWAxuZGzKlNx6TeDNZnE7fZ3gDZgkSeBcrhca gXW8duKrdWOZN/QoXKUxFSyHMyUQOaR8H59MWChWekDusN5XV6mPlbfUM/KmuTHlNJLb nADV8AQXFIPmZi+WgJ+cmhxeMfX4u8i8qS0FWNqn3rK0mpvyLar8l6ODCz11R5m0+kPG Aln2wCE+hiKK+NbGrUHlUluNLrdWA7uiP4TUiqCZSBcAawRsBGqaxrLwTGdHqCajtzWA ZIAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792497; x=1686384497; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cISiYMnSQzGuCQgPP8NYpc1CLEOshSGVWmc3Y1xiUV8=; b=PNRJUDzrqIY7pxwpywag8lcoTdVh3x8Ntm4nQzKKHEZWoZKeXgDDCj1ha+7PlQF0Ox YzMwySlPV12Cg1+k8CMZTlJSI6cQC9H2LrL3CFeNaJOOqSQBLJcXuggbx601uceQkbpM sLDd5QG4BsCDaqoeWgU77kEfBYYHQRxabWNION9iCqUXIi6B6NcL3Xed5Kk12TvnDekS gIKXtEsmu4YO1p5zFUNsDJb2hyoxDUG+hYSA2ge7N4S8INj0I7XTr3PzEyl+034EqcXK Yc/sDtCSOQeF11RCsK+eXo2zYUs0iiiBFTaL/fVuqTjDE45upgCPO75kXOJybSUT4JoO WUsw== X-Gm-Message-State: AC+VfDynbL2nytyZKoYx3A0HwbDuJ+in8/I78XzvZTcK1gN6wZgBu1ez WS4puCxqSbEJL4u3UlHXPS6u1jT5GlvDmIQuP99bPw== X-Google-Smtp-Source: ACHHUZ7gw3BZA5RGQ7Cr5ELVPPlMOfX9O9LEmbN1/kt4G6X5xhWOA2eoff50djNzReyA8YxVeWwGeA== X-Received: by 2002:a17:906:dc89:b0:957:862a:9e6e with SMTP id cs9-20020a170906dc8900b00957862a9e6emr23355948ejc.73.1683792497264; Thu, 11 May 2023 01:08:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PULL 40/53] tcg/s390x: Simplify constraints on qemu_ld/st Date: Thu, 11 May 2023 09:04:37 +0100 Message-Id: <20230511080450.860923-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792806569100001 Adjust the softmmu tlb to use R0+R1, not any of the normally available registers. Since we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 2 -- tcg/s390x/tcg-target-con-str.h | 1 - tcg/s390x/tcg-target.c.inc | 36 ++++++++++++---------------------- 3 files changed, 12 insertions(+), 27 deletions(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index 15f1c55103..ecc079bb6d 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -10,12 +10,10 @@ * tcg-target-con-str.h; the constraint combination is inclusive or. */ C_O0_I1(r) -C_O0_I2(L, L) C_O0_I2(r, r) C_O0_I2(r, ri) C_O0_I2(r, rA) C_O0_I2(v, r) -C_O1_I1(r, L) C_O1_I1(r, r) C_O1_I1(v, r) C_O1_I1(v, v) diff --git a/tcg/s390x/tcg-target-con-str.h b/tcg/s390x/tcg-target-con-str.h index 6fa64a1ed6..25675b449e 100644 --- a/tcg/s390x/tcg-target-con-str.h +++ b/tcg/s390x/tcg-target-con-str.h @@ -9,7 +9,6 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) -REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) REGS('v', ALL_VECTOR_REGS) REGS('o', 0xaaaa) /* odd numbered general regs */ =20 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index dd13326670..aacbaf21d5 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -44,18 +44,6 @@ #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16) #define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) =20 -/* - * For softmmu, we need to avoid conflicts with the first 3 - * argument registers to perform the tlb lookup, and to call - * the helper function. - */ -#ifdef CONFIG_SOFTMMU -#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_R2, 3) -#else -#define SOFTMMU_RESERVE_REGS 0 -#endif - - /* Several places within the instruction set 0 means "no register" rather than TCG_REG_R0. */ #define TCG_REG_NONE 0 @@ -1814,13 +1802,13 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, ldst->oi =3D oi; ldst->addrlo_reg =3D addr_reg; =20 - tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE, + tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); =20 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); - tcg_out_insn(s, RXY, NG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, mask_off= ); - tcg_out_insn(s, RXY, AG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, table_of= f); + tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_off); + tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_off); =20 /* * For aligned accesses, we check the first byte and include the align= ment @@ -1830,10 +1818,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, a_off =3D (a_bits >=3D s_bits ? 0 : s_mask - a_mask); tlb_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; if (a_off =3D=3D 0) { - tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask); + tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); } else { - tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off); - tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask); + tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off); + tgen_andi(s, TCG_TYPE_TL, TCG_REG_R0, tlb_mask); } =20 if (is_ld) { @@ -1842,16 +1830,16 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, ofs =3D offsetof(CPUTLBEntry, addr_write); } if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_insn(s, RX, C, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs); + tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); } else { - tcg_out_insn(s, RXY, CG, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs= ); + tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); } =20 tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); ldst->label_ptr[0] =3D s->code_ptr++; =20 - h->index =3D TCG_REG_R2; - tcg_out_insn(s, RXY, LG, h->index, TCG_REG_R2, TCG_REG_NONE, + h->index =3D TCG_TMP0; + tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE, offsetof(CPUTLBEntry, addend)); =20 if (TARGET_LONG_BITS =3D=3D 32) { @@ -3155,10 +3143,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return C_O1_I1(r, L); + return C_O1_I1(r, r); case INDEX_op_qemu_st_i64: case INDEX_op_qemu_st_i32: - return C_O0_I2(L, L); + return C_O0_I2(r, r); =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792882; cv=none; d=zohomail.com; s=zohoarc; b=Yj2kOiqbIL+o7NLX+m2ZL/z6t9FlgdWx/Yxr/nDlhQ4BAKFv+IYY3ZHi9QhGC/2RJEKXkIKuwKyOAEvE6n8r2oAVJkxb/sW+VBhjoYMVaE0Au0b9PUFb8s90YwDmCWas1evE6c+e8NQt9KxFImgoUi0feaczP6avY2odrhOrmMc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792882; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ak9lI8a+Y3Ekw5fqxmz/fOYShDZB2hBrThel6H303CQ=; b=mTseviTO358JAeAOcG2/PoplWtSitLymHp+KvpNENFzzQjbJ5dKjXXjoQ1GEBFkae4CrPDwEoarBB3mMe1tHwy2oN0NRU+v7rHY6Q8dRBgagHrMa6+5MIL7BFAkfPOxF9vY8+VOlnjSOQrCLMq+U9BqWPBNihRYabfcH9CTSdIA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792881575692.2720684812168; Thu, 11 May 2023 01:14:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Lb-0007FR-G1; Thu, 11 May 2023 04:08:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1La-0007EQ-1J for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:22 -0400 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1LX-0001wf-B5 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:21 -0400 Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-965fc25f009so1205910566b.3 for ; Thu, 11 May 2023 01:08:18 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b00959c6cb82basm3635225ejc.105.2023.05.11.01.08.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:08:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792498; x=1686384498; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Ak9lI8a+Y3Ekw5fqxmz/fOYShDZB2hBrThel6H303CQ=; b=yoEwye4vPuvaZCOqtz7Ci10IRYorhjU3yizrwj3ov2anAg88+nhaiEO+D/aZ33gdLG l3xMe4BG0gBwpQqxagt6uP0JXAGsVC1plC4LgxWcPTUOn9RnWGsC8RL4lQZ/7S3f6J2m Y0jdThOViXlfuvCeZV+G3p7MwlfXEfttlg3Leo/QBYYucNHuXiUxEHtDLLpE7tAItzha pfPIQbP/jYhhpIxjbfhKgAZk2pQY4mmapTc+oTaHT5VayFkxQ4igKoRtZMGLjuo25ldZ k0+G6SkmLJ0g9L1j8RV6FjZmSF8DrSsQ31Yh78Yo7emgkvKJA8+xTqfEKdw2dCbB+JQ6 aKWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792498; x=1686384498; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ak9lI8a+Y3Ekw5fqxmz/fOYShDZB2hBrThel6H303CQ=; b=VPECSP7DIDHHImRELytgKcX2inecVEscPP9jqF0GJT0wVw32Z9Mqq2knTOIqwUIKv6 IglGj4mvJG6jF8usatunLOYmeoK10ShXtJiQvusgydqVQURbxJbYZDnsIxx/KYRtrPnw 6ZdwOmnqdk4+q6N2j8uI/x7W/R9X72G/vbXOK2STkbZBAo/yogWeexVYTLt1vE056zCV yrLwfwhPQ2jSy3qcz4xupSDLuQw1AMdffVO9QW2MVvldduQMfuuo0WdxUX8PoQGTfNv+ t3a+HqyvWNLwUD/v1BMUqE9w7s8IeXk3ytmR4UrPmPPtYcrd3DGesJx/leK4+fcqrAmc qe8A== X-Gm-Message-State: AC+VfDzAJZ4fe3rtXsz0rHmakRy7oSSeZeGlLcRcLfIqLjSACt/5lowW IH1soa5VZi2R8WVo7Qnyxl2z6PE3FOnhOv+dCOfXhA== X-Google-Smtp-Source: ACHHUZ7nJTxdZsGEwetsYAZS5Rb01E/IQXUhEGCsIX+PyOX64+5ftJPfoGMn09zttd10qt7a33kGug== X-Received: by 2002:a17:907:eab:b0:969:813c:9868 with SMTP id ho43-20020a1709070eab00b00969813c9868mr11197610ejc.18.1683792497717; Thu, 11 May 2023 01:08:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 41/53] target/mips: Add MO_ALIGN to gen_llwp, gen_scwp Date: Thu, 11 May 2023 09:04:38 +0100 Message-Id: <20230511080450.860923-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792883053100003 Content-Type: text/plain; charset="utf-8" These are atomic operations, so mark as requiring alignment. Signed-off-by: Richard Henderson --- target/mips/tcg/nanomips_translate.c.inc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nan= omips_translate.c.inc index 97b9572caa..e08343414c 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -998,7 +998,7 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, = int16_t offset, TCGv tmp2 =3D tcg_temp_new(); =20 gen_base_offset_addr(ctx, taddr, base, offset); - tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TEUQ | MO_ALIGN); if (cpu_is_bigendian(ctx)) { tcg_gen_extr_i64_tl(tmp2, tmp1, tval); } else { @@ -1039,7 +1039,8 @@ static void gen_scwp(DisasContext *ctx, uint32_t base= , int16_t offset, =20 tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp)); tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval, - eva ? MIPS_HFLAG_UM : ctx->mem_idx, MO_64); + eva ? MIPS_HFLAG_UM : ctx->mem_idx, + MO_64 | MO_ALIGN); if (reg1 !=3D 0) { tcg_gen_movi_tl(cpu_gpr[reg1], 1); } --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683793036; cv=none; d=zohomail.com; s=zohoarc; b=V3AlAvbs3VJRxl0So9EAVfhTZ3lfB8eEYm0/EUiyytQPjGvdoDwrtke4t8iEY025kt7OeRBiL6tSvsNXsS8MzTo4cniU46rwqyNk/BrkcliMwMMUUmrBICR4NiVy5W4PrvZVHYyvAFpWEENJ72vTUR7rCOWtPIDDBt5xkcI1IW8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683793036; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cqP+kmlr3vGIQ8ytEhUxnQ61nNI/I+I3GQWyWpYA5O0=; b=UktIf95zkxRcj6Zl9F+RSpwcnjKsYL00qeREAoDxfsMQJXHSDhXFOG3hYDK5qKTFTR9eEtZd5/srEAc7YSZmFM9LHnh/QEefChJpUEX6xnSpJd0qOrfF/0RXgDfdz05p2m/YxHyc1i4XSl95PD0JCTDf44E2NrlwnL7V1RZdjFw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683793036228827.2933616103618; Thu, 11 May 2023 01:17:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Ld-0007JJ-1Y; Thu, 11 May 2023 04:08:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1La-0007Ej-FZ for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:22 -0400 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1LX-0001wj-W5 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:22 -0400 Received: by mail-ed1-x52a.google.com with SMTP id 4fb4d7f45d1cf-50bd2d7ba74so76582923a12.1 for ; Thu, 11 May 2023 01:08:19 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b00959c6cb82basm3635225ejc.105.2023.05.11.01.08.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:08:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792498; x=1686384498; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=cqP+kmlr3vGIQ8ytEhUxnQ61nNI/I+I3GQWyWpYA5O0=; b=W2V6xVk1v8a2xUqrBw+rewNIEjN7SISGjnBZQ2J5rY6jor4UyTe+yLxxve560E5LmQ 2wN04+p2CTmrHUtISh9Ku6ADEouHr3U4N5dZhuCakKjbcTmnrgoGkHw9pySj+ipdZvcL iPXKkHGxMzisyt1zfSb0DmZd0Yrd0Gwfj5VZI1ES8npsJMUodHpCdxBGah7RJOWnr6Qb MQQxiPKJvncQLrOXet+X/5Sg0fyvDqww5P7/J1V9aD1nJkPHwFtN9g4JHkQGLUswM1rG dFL3SWZdl10l8YfAmc5f6AAi7KPx3FDo5yxt/a4wmOIVnK8gs6mYiAv3U3GU+VY88Ccm BD1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792498; x=1686384498; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cqP+kmlr3vGIQ8ytEhUxnQ61nNI/I+I3GQWyWpYA5O0=; b=SA4yS8I4HnvQcVyS4KJbx0SA8+dmlOUVI1JOSHlldc5C0adARJT/q5oJ8n8INwfErQ Fd15QaHJ7MgEHPf/bisTBaIo8AUvEbf6rWgXLl8BhBdqBieybPvylpKL75aY9hmkHj/q V7RC/XbZ5jABmIGqtprlF68VKkNMCqbXHMs73AROiAfjfFhF1etp1bvM2ELNJ22UYWZv TbwDEqLWBQHXHYrcK488YcoN/GGnoj2Wj5aQdbqb4pYz0jntnQMUTmrMuenTJoO1h8Nu 7Co/7Q6FeCqGNfXUhln3FqGtVdysCqifYvFiRCLwv0ZTADQesAdra76Rt00weWU5qmFe hXtw== X-Gm-Message-State: AC+VfDzLkquQbW+4vYQwmS8eh1sM625I9BVP669fKKJCnhalJBpoVXXH +ZQq1MRplg+F0cK06WnWy8F62BnX1y3aEtUrKZQ3mA== X-Google-Smtp-Source: ACHHUZ53wUdi4LT9XMF4JvfD1d3tAYBaD3u7i5nMO+lDl68xWVDAtO+zgjSOKfiJYwpLpCZ8UHg9KQ== X-Received: by 2002:a17:906:6a1c:b0:966:5fac:2e52 with SMTP id qw28-20020a1709066a1c00b009665fac2e52mr12207619ejc.9.1683792498407; Thu, 11 May 2023 01:08:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 42/53] target/mips: Add missing default_tcg_memop_mask Date: Thu, 11 May 2023 09:04:39 +0100 Message-Id: <20230511080450.860923-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683793037961100011 Content-Type: text/plain; charset="utf-8" Memory operations that are not already aligned, or otherwise marked up, require addition of ctx->default_tcg_memop_mask. Signed-off-by: Richard Henderson --- target/mips/tcg/mxu_translate.c | 3 ++- target/mips/tcg/micromips_translate.c.inc | 24 ++++++++++++++-------- target/mips/tcg/mips16e_translate.c.inc | 18 ++++++++++------ target/mips/tcg/nanomips_translate.c.inc | 25 +++++++++++------------ 4 files changed, 42 insertions(+), 28 deletions(-) diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translat= e.c index bdd20709c0..be038b5f07 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -831,7 +831,8 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx) tcg_gen_ori_tl(t1, t1, 0xFFFFF000); } tcg_gen_add_tl(t1, t0, t1); - tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_TESL ^ (sel * MO_BSWAP)); + tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, (MO_TESL ^ (sel * MO_BSWAP)) | + ctx->default_tcg_memop_mask); =20 gen_store_mxu_gpr(t1, XRa); } diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/mi= cromips_translate.c.inc index e8b193aeda..211d102cf6 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -977,20 +977,24 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t= opc, int rd, gen_reserved_instruction(ctx); return; } - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL | + ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd); tcg_gen_movi_tl(t1, 4); gen_op_addr_add(ctx, t0, t0, t1); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL | + ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd + 1); break; case SWP: gen_load_gpr(t1, rd); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); tcg_gen_movi_tl(t1, 4); gen_op_addr_add(ctx, t0, t0, t1); gen_load_gpr(t1, rd + 1); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); break; #ifdef TARGET_MIPS64 case LDP: @@ -998,20 +1002,24 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_= t opc, int rd, gen_reserved_instruction(ctx); return; } - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd); tcg_gen_movi_tl(t1, 8); gen_op_addr_add(ctx, t0, t0, t1); - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + ctx->default_tcg_memop_mask); gen_store_gpr(t1, rd + 1); break; case SDP: gen_load_gpr(t1, rd); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + ctx->default_tcg_memop_mask); tcg_gen_movi_tl(t1, 8); gen_op_addr_add(ctx, t0, t0, t1); gen_load_gpr(t1, rd + 1); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | + ctx->default_tcg_memop_mask); break; #endif } diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips= 16e_translate.c.inc index 602f5f0c02..5cffe0e412 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -172,22 +172,26 @@ static void gen_mips16_save(DisasContext *ctx, case 4: gen_base_offset_addr(ctx, t0, 29, 12); gen_load_gpr(t1, 7); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); /* Fall through */ case 3: gen_base_offset_addr(ctx, t0, 29, 8); gen_load_gpr(t1, 6); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); /* Fall through */ case 2: gen_base_offset_addr(ctx, t0, 29, 4); gen_load_gpr(t1, 5); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); /* Fall through */ case 1: gen_base_offset_addr(ctx, t0, 29, 0); gen_load_gpr(t1, 4); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | + ctx->default_tcg_memop_mask); } =20 gen_load_gpr(t0, 29); @@ -196,7 +200,8 @@ static void gen_mips16_save(DisasContext *ctx, tcg_gen_movi_tl(t2, -4); \ gen_op_addr_add(ctx, t0, t0, t2); \ gen_load_gpr(t1, reg); \ - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); \ + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | \ + ctx->default_tcg_memop_mask); \ } while (0) =20 if (do_ra) { @@ -298,7 +303,8 @@ static void gen_mips16_restore(DisasContext *ctx, #define DECR_AND_LOAD(reg) do { \ tcg_gen_movi_tl(t2, -4); \ gen_op_addr_add(ctx, t0, t0, t2); \ - tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); \ + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL | \ + ctx->default_tcg_memop_mask); \ gen_store_gpr(t1, reg); \ } while (0) =20 diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nan= omips_translate.c.inc index e08343414c..b96dcd2ae9 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -2641,52 +2641,49 @@ static void gen_p_lsx(DisasContext *ctx, int rd, in= t rs, int rt) =20 switch (extract32(ctx->opcode, 7, 4)) { case NM_LBX: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, - MO_SB); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB); gen_store_gpr(t0, rd); break; case NM_LHX: /*case NM_LHXS:*/ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, - MO_TESW); + MO_TESW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rd); break; case NM_LWX: /*case NM_LWXS:*/ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, - MO_TESL); + MO_TESL | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rd); break; case NM_LBUX: - tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, - MO_UB); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB); gen_store_gpr(t0, rd); break; case NM_LHUX: /*case NM_LHUXS:*/ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, - MO_TEUW); + MO_TEUW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rd); break; case NM_SBX: check_nms(ctx); gen_load_gpr(t1, rd); - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - MO_8); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_8); break; case NM_SHX: /*case NM_SHXS:*/ check_nms(ctx); gen_load_gpr(t1, rd); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - MO_TEUW); + MO_TEUW | ctx->default_tcg_memop_mask); break; case NM_SWX: /*case NM_SWXS:*/ check_nms(ctx); gen_load_gpr(t1, rd); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, - MO_TEUL); + MO_TEUL | ctx->default_tcg_memop_mask); break; case NM_LWC1X: /*case NM_LWC1XS:*/ @@ -3739,7 +3736,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) addr_off); =20 tcg_gen_movi_tl(t0, addr); - tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, MO_T= ESL); + tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, + MO_TESL | ctx->default_tcg_memop_ma= sk); } break; case NM_SWPC48: @@ -3755,7 +3753,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) tcg_gen_movi_tl(t0, addr); gen_load_gpr(t1, rt); =20 - tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, + MO_TEUL | ctx->default_tcg_memop_ma= sk); } break; default: --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683793000; cv=none; d=zohomail.com; s=zohoarc; b=MGV8NKumpfa1fmm2b5UIYjwN5jK3FMGLiEqhOSGAMYN7gEinezWGbSjFF+HVwTPx2muNEAMtIwC3f/q+DkpnixL11gtNZvY596Lc2drFHym0mXu7T8fHE9d3/ZvYWQgYWQDdxCPJ1bVywSQH+sDgx+e6U5ncrTkSB7l12Wimo0U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683793000; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zWzZj4XIntENO/xAWOBchS++0j1IHClHqbogxDhHrI8=; b=lfjiuEFAnTMkqxBnRLTJJJT8mVZ8ok+ROkI59uJ94aOPhQZ1+U9wYHc57VPOLZfQMibqEJYzhs3IXyAW9wnkUlOouvEo+BVb21ntMNalA2XU46Owe8IkVm7aM+QJvNaXITS+inHcvouyWctedzlDQgf/owWB0EVXCa0PTwCDxkI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683793000484645.2954709610996; Thu, 11 May 2023 01:16:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Lc-0007HU-96; Thu, 11 May 2023 04:08:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1La-0007ER-1o for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:22 -0400 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1LY-0001wp-Dx for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:21 -0400 Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-94a342f7c4cso1466701166b.0 for ; Thu, 11 May 2023 01:08:20 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b00959c6cb82basm3635225ejc.105.2023.05.11.01.08.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:08:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792499; x=1686384499; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zWzZj4XIntENO/xAWOBchS++0j1IHClHqbogxDhHrI8=; b=VfBD2Q3nC4FfGmqVFq0EB6nwR+TLWcysemzsSplOQzEtKgFl6R22yzishkDSGwVJxl R8V4zaXEDQKl6t+4NMTRKPIvsQj9pO4J7zmYIf7uZ9Ols7JRVry41PkwUoeLHNx/B7Lh RXg+kjLrVFumZVUQWnDW+L2o2oPdmZZCg7YC4STOqYFmnvh32evzSVjt+Pa3fJ9vQzwu VhkjvFQGW9K1ynlAwHgiu/rE/0POoJ4HjvC0uPTHzIaRZIxaOODefuHwHNPoFLEyXWKI +9lTBzyOJnRXrNtG29ISpJbfWZSRHXyA5hSX7VYMiKYkW3KZPe/EuZJaNWpZLVc91qP0 bk1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792499; x=1686384499; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zWzZj4XIntENO/xAWOBchS++0j1IHClHqbogxDhHrI8=; b=HO1TZZn3Kew/v+d7ONykjvzk9/w1NMpTl1/o3enpz8IrhXBThgUsR7TUrJNjH+PQl6 14Cm0+KufAw9+WmBkpToK091d4I9a+FfnWem0XRw++GcXX0tBKuzFYoVjTQ3x5r39WF9 Wy6uX7bDnLfMgypgQjLm6QZboQP1cA5D1FeCqp7R75P9wmm7CZFZBufTxKCmyHZtkv9a LJLht20j+pc/2lavAPwyZGSj3KWpctGn/A8e4OG5C8PO+S90RYphGmlqu5Gusjm0TLA/ 0J15+qvFkagATdfaNmzi2dyIhHYSorDw2/HIbxhW+Z98cZZGA9wbuc4PrRx/6oUoBeCc Q1rQ== X-Gm-Message-State: AC+VfDyZl9xdowq6APYuKnECNekqKXzaDIP0kq2QSvewUORNlK/ykePB UuPThczGfnOve28olu2/Uw8Q/GRQLJFzix1YbrZ7uQ== X-Google-Smtp-Source: ACHHUZ4mdEP09j27mpHkQ2/Qev0B+GeEpcefk6JzHcNmDCSzw+4BxeZSV49y5SZUqxAQaLrwGmGvbw== X-Received: by 2002:a17:907:869e:b0:93d:ae74:fa9e with SMTP id qa30-20020a170907869e00b0093dae74fa9emr19713813ejc.7.1683792498916; Thu, 11 May 2023 01:08:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 43/53] target/mips: Use MO_ALIGN instead of 0 Date: Thu, 11 May 2023 09:04:40 +0100 Message-Id: <20230511080450.860923-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683793001805100003 The opposite of MO_UNALN is MO_ALIGN. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/mips/tcg/nanomips_translate.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nan= omips_translate.c.inc index b96dcd2ae9..a98dde0d2e 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -4305,7 +4305,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) TCGv va =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); MemOp memop =3D (extract32(ctx->opcode, 8, 3)) =3D=3D - NM_P_LS_UAWM ? MO_UNALN : 0; + NM_P_LS_UAWM ? MO_UNALN : MO_ALIGN; =20 count =3D (count =3D=3D 0) ? 8 : count; while (counter !=3D count) { --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792883; cv=none; d=zohomail.com; s=zohoarc; b=ezjxa9osAkQcXlcJIQ+HFsHt+NBOXn33/K6Q6NkyLFvB6dD/ZB0I8+sW7zLjCrhLOfe2Wj2gs5MTQ6wj5xpUYXSjxGdcgGt4AMb20sC6CCZHf9nuFk93xIY79ixZP1SVfuq01Dc42peYbpTh5Q/LZRrzI3dERyTDYNQR2XTB2xA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792883; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=azGpR/vI4E4lJ27AqLH4AuBHdfSf/EVVZa9vn6F5YtM=; b=M/9ILGt3kIKdvrROuF7zo4ggvMgfEaEI7+UM4rhtKxOLDBhJgmAA4t0WjQgEB9uAiaDTUN5iCbBNkpWrPVb6UbZGv6UwV9jFwEqnFbTDF+j6Ujy1u9GYhgqpaulKTB+Z417VrHfaCBGqcM5u2kKpna9TwInZpMxP35XNxzMTWM0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16837928834728.609284658565116; Thu, 11 May 2023 01:14:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Lb-0007HG-Si; Thu, 11 May 2023 04:08:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1La-0007En-Lc for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:22 -0400 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1LY-0001wu-TI for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:22 -0400 Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-965f7bdab6bso1337278766b.3 for ; Thu, 11 May 2023 01:08:20 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b00959c6cb82basm3635225ejc.105.2023.05.11.01.08.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:08:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792499; x=1686384499; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=azGpR/vI4E4lJ27AqLH4AuBHdfSf/EVVZa9vn6F5YtM=; b=GHolTKxwWWyqiO5xU6FXGRkooH/fBFCjJDLReUe13UIFBppe3MzyPd8movtVAFcRvk 7uXN3rZdxdxwJo9XCeHMj7lmdsGeb6fqBr75xQqr3qP+/inwRzLvJusd8Q83I1DTX8VA dEaefLx8ZMdUMWPUPW46dMj/LtFsse34i5fqdA8ADk4fjlTRvdu9P1VjpunnEG9Fafa5 rRAB5OtwuqgdR3b5OwCS/yDhIsWHP2j85gCJA8SE9TeUngW1oYtCuVQ3tyjjQp4tZNct rjAil1tlv4p+hDvW2e8/8ALOcmjdvHUJX3e+7q5T9ToKoDpSkJuxe3bI5k0mL82PMiy1 mOzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792499; x=1686384499; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=azGpR/vI4E4lJ27AqLH4AuBHdfSf/EVVZa9vn6F5YtM=; b=MwZHSRrPMqBXZ77k1NNjBXLOuU2Og9oL7qwpuG/yglg6dSB+97UwVl17lo8JrQLL/G H2rlb8BxkMGf+ucrCIRaJEvt7yJ7WSxwuru/kqOFchfn342paK38lejMtP6B5eS2eoiz aiXxU3M6+A7tVUqp6n3/P5eVmIf1uEHWZtKqlJ7WKZb9PYch3QETQYROk5uH24n9YxIp LofXDlShIZnqiE007QcvRYAKf/iopUwkybvh27FYQacM4Lz6Siu7+qJjV8utYc9jSxel lYFfoD0qLQpE8xUEjnHfnBeHMeDK4LZrqv3U6oFKlg3HKpOHuF8/e1ObWy8LDf8A5Q02 Kt+Q== X-Gm-Message-State: AC+VfDw02M+nf1Aq69ZvKfjZkPS1W5UNWHJUeKs+XzOB3Ig/98rxXNqU 7UBM6YfY9RF2/rLzceE/YbvKidb20nL+JQpAeSNs4A== X-Google-Smtp-Source: ACHHUZ7d7LM405vR/zHAb+++fZwply5xpXETtJqXvKhZeknS/4QvtqFCvbihQGgV7sjOAKKc532X1Q== X-Received: by 2002:a17:907:d86:b0:953:42c0:86e7 with SMTP id go6-20020a1709070d8600b0095342c086e7mr18243083ejc.4.1683792499462; Thu, 11 May 2023 01:08:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 44/53] target/mips: Remove TARGET_ALIGNED_ONLY Date: Thu, 11 May 2023 09:04:41 +0100 Message-Id: <20230511080450.860923-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792884697100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- configs/targets/mips-linux-user.mak | 1 - configs/targets/mips-softmmu.mak | 1 - configs/targets/mips64-linux-user.mak | 1 - configs/targets/mips64-softmmu.mak | 1 - configs/targets/mips64el-linux-user.mak | 1 - configs/targets/mips64el-softmmu.mak | 1 - configs/targets/mipsel-linux-user.mak | 1 - configs/targets/mipsel-softmmu.mak | 1 - configs/targets/mipsn32-linux-user.mak | 1 - configs/targets/mipsn32el-linux-user.mak | 1 - 10 files changed, 10 deletions(-) diff --git a/configs/targets/mips-linux-user.mak b/configs/targets/mips-lin= ux-user.mak index 71fa77d464..b4569a9893 100644 --- a/configs/targets/mips-linux-user.mak +++ b/configs/targets/mips-linux-user.mak @@ -2,5 +2,4 @@ TARGET_ARCH=3Dmips TARGET_ABI_MIPSO32=3Dy TARGET_SYSTBL_ABI=3Do32 TARGET_SYSTBL=3Dsyscall_o32.tbl -TARGET_ALIGNED_ONLY=3Dy TARGET_BIG_ENDIAN=3Dy diff --git a/configs/targets/mips-softmmu.mak b/configs/targets/mips-softmm= u.mak index 7787a4d94c..d34b4083fc 100644 --- a/configs/targets/mips-softmmu.mak +++ b/configs/targets/mips-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=3Dmips -TARGET_ALIGNED_ONLY=3Dy TARGET_BIG_ENDIAN=3Dy TARGET_SUPPORTS_MTTCG=3Dy diff --git a/configs/targets/mips64-linux-user.mak b/configs/targets/mips64= -linux-user.mak index 5a4771f22d..d2ff509a11 100644 --- a/configs/targets/mips64-linux-user.mak +++ b/configs/targets/mips64-linux-user.mak @@ -3,5 +3,4 @@ TARGET_ABI_MIPSN64=3Dy TARGET_BASE_ARCH=3Dmips TARGET_SYSTBL_ABI=3Dn64 TARGET_SYSTBL=3Dsyscall_n64.tbl -TARGET_ALIGNED_ONLY=3Dy TARGET_BIG_ENDIAN=3Dy diff --git a/configs/targets/mips64-softmmu.mak b/configs/targets/mips64-so= ftmmu.mak index 568d66650c..12d9483bf0 100644 --- a/configs/targets/mips64-softmmu.mak +++ b/configs/targets/mips64-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=3Dmips64 TARGET_BASE_ARCH=3Dmips -TARGET_ALIGNED_ONLY=3Dy TARGET_BIG_ENDIAN=3Dy diff --git a/configs/targets/mips64el-linux-user.mak b/configs/targets/mips= 64el-linux-user.mak index f348f35997..f9efeec8ea 100644 --- a/configs/targets/mips64el-linux-user.mak +++ b/configs/targets/mips64el-linux-user.mak @@ -3,4 +3,3 @@ TARGET_ABI_MIPSN64=3Dy TARGET_BASE_ARCH=3Dmips TARGET_SYSTBL_ABI=3Dn64 TARGET_SYSTBL=3Dsyscall_n64.tbl -TARGET_ALIGNED_ONLY=3Dy diff --git a/configs/targets/mips64el-softmmu.mak b/configs/targets/mips64e= l-softmmu.mak index 5a52aa4b64..8d9ab3ddc4 100644 --- a/configs/targets/mips64el-softmmu.mak +++ b/configs/targets/mips64el-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=3Dmips64 TARGET_BASE_ARCH=3Dmips -TARGET_ALIGNED_ONLY=3Dy TARGET_NEED_FDT=3Dy diff --git a/configs/targets/mipsel-linux-user.mak b/configs/targets/mipsel= -linux-user.mak index e23793070c..e8d7241d31 100644 --- a/configs/targets/mipsel-linux-user.mak +++ b/configs/targets/mipsel-linux-user.mak @@ -2,4 +2,3 @@ TARGET_ARCH=3Dmips TARGET_ABI_MIPSO32=3Dy TARGET_SYSTBL_ABI=3Do32 TARGET_SYSTBL=3Dsyscall_o32.tbl -TARGET_ALIGNED_ONLY=3Dy diff --git a/configs/targets/mipsel-softmmu.mak b/configs/targets/mipsel-so= ftmmu.mak index c7c41f4fb7..0829659fc2 100644 --- a/configs/targets/mipsel-softmmu.mak +++ b/configs/targets/mipsel-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=3Dmips -TARGET_ALIGNED_ONLY=3Dy TARGET_SUPPORTS_MTTCG=3Dy diff --git a/configs/targets/mipsn32-linux-user.mak b/configs/targets/mipsn= 32-linux-user.mak index 1e80b302fc..206095da64 100644 --- a/configs/targets/mipsn32-linux-user.mak +++ b/configs/targets/mipsn32-linux-user.mak @@ -4,5 +4,4 @@ TARGET_ABI32=3Dy TARGET_BASE_ARCH=3Dmips TARGET_SYSTBL_ABI=3Dn32 TARGET_SYSTBL=3Dsyscall_n32.tbl -TARGET_ALIGNED_ONLY=3Dy TARGET_BIG_ENDIAN=3Dy diff --git a/configs/targets/mipsn32el-linux-user.mak b/configs/targets/mip= sn32el-linux-user.mak index f31a9c394b..ca2a3ed753 100644 --- a/configs/targets/mipsn32el-linux-user.mak +++ b/configs/targets/mipsn32el-linux-user.mak @@ -4,4 +4,3 @@ TARGET_ABI32=3Dy TARGET_BASE_ARCH=3Dmips TARGET_SYSTBL_ABI=3Dn32 TARGET_SYSTBL=3Dsyscall_n32.tbl -TARGET_ALIGNED_ONLY=3Dy --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792854; cv=none; d=zohomail.com; s=zohoarc; b=m9s4NsDHdfyU4PS5zCOPM5+lFK4Fk2Z4No+88tJO/tzA4knsbrj8K98s/B/Ef8seyY267yF9Uuc+njo4Izq/n6wvzm5q8OJPLzop7HzK3wfx9nL7bAIqfNZXMnvuTfVp2sMErr2+A9bUDkAF12dDCBIAXH77BIN8C+D09a6TKZM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792854; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7YTE8+U90t71rYiZfdQVcRBAJLXta/7RniwHriGZ9J4=; b=k9P5ikSJzAzChStP7hIhhm+PaVOU3wZ7U41hQcxeTVIioT5WGVbxEnD7j5QumJm/YBdA94RvKCQrZ3R4QuVVr3eeUh16xC+KRmU4TmCHzKZK5oT+zTOIWejFLw0/02UxUo8wTw4hRpOUooK1TOeU1KOVihvj8r9NkzvV9HfU5HM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792854404960.0630212548783; Thu, 11 May 2023 01:14:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Lc-0007IF-J7; Thu, 11 May 2023 04:08:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1La-0007F4-VJ for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:22 -0400 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1LZ-0001wz-95 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:22 -0400 Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-965fc25f009so1205916866b.3 for ; Thu, 11 May 2023 01:08:20 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b00959c6cb82basm3635225ejc.105.2023.05.11.01.08.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:08:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792500; x=1686384500; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7YTE8+U90t71rYiZfdQVcRBAJLXta/7RniwHriGZ9J4=; b=xMtzbCTnvs4yj9lBm86rQZ9NqoBI2uTRNxpHfl6eY8yvHSgGbNfLwIvOwpTmYUegeO GAHe8U0gfzPBBYuBixEkH6g7FcOs8LiUeXQHD0gobNpSJmwcc/xDGcSh+hxDO9BRnBlu UCivyRCcKkPmNIN8/fJW8Vlxb/+cvQXSXKxTvkCUHFeUDldP2CSLQ2kQTVHCEWXtQgFZ qpbK+WqSHsaLNvHzeqiYYeIiq/a9wQj0JOrWSlMyAA3u5pQmbOomUKsg2vZQ8SAZOa7Y tjlTOjwGjOrgkDeE0sZuBLlXkVDsiLM86SS7zv5b6usEzjjfEljodZQKafhmIp6xasdB TQHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792500; x=1686384500; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7YTE8+U90t71rYiZfdQVcRBAJLXta/7RniwHriGZ9J4=; b=aj5t+SdAVR5NWJzkYSp0VtfxaOAIllSLNhlrMHARzyghjdJ4TkgugIis5oBASRdapP AZqHggapkfwuZXVcPGMrvmnL10Fe/eUdvmc0Es+8j8FnTcDddiW6bOsN15TBtlZnBNzT ft4WCZl79tpZUiQvdQGr20DifYh9yNGFg9b71P9NKGditaB2VW7Dd+Qbqtu+kZFZCI4x cAOA22bciyFQWA4xo3sgufj6mTZhbbetlwmQa7bYyNH07x/HdOk3cjTkH88kQP5aPA93 fP+4F0RoGEcM7o8PVyz7qJVp+mx12q5EyD+aOIz9lS0zGGhgGYwjKgKn+amRIGbeWpf/ K96g== X-Gm-Message-State: AC+VfDyvvCEe2a1POO62ZZHb9nhwA0nbm//S2O5Ad05nDsO7Dbv/Qixd gSf6enDKaWS/0YieaDT4qnTc3jlhrJs1Z6hyGvXZ9g== X-Google-Smtp-Source: ACHHUZ4gZ6Duxy0cdsj3x7P6zDPLy+WnCI+VABWptSW2MjtBhPx2zlbyFPaPE09sf/8ia3VILKX0Sg== X-Received: by 2002:a17:907:da4:b0:966:4d99:b0aa with SMTP id go36-20020a1709070da400b009664d99b0aamr14336784ejc.59.1683792500001; Thu, 11 May 2023 01:08:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 45/53] target/nios2: Remove TARGET_ALIGNED_ONLY Date: Thu, 11 May 2023 09:04:42 +0100 Message-Id: <20230511080450.860923-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792856489100003 In gen_ldx/gen_stx, the only two locations for memory operations, mark the operation as either aligned (softmmu) or unaligned (user-only, as if emulated by the kernel). Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- configs/targets/nios2-softmmu.mak | 1 - target/nios2/translate.c | 10 ++++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/configs/targets/nios2-softmmu.mak b/configs/targets/nios2-soft= mmu.mak index 5823fc02c8..c99ae3777e 100644 --- a/configs/targets/nios2-softmmu.mak +++ b/configs/targets/nios2-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=3Dnios2 -TARGET_ALIGNED_ONLY=3Dy TARGET_NEED_FDT=3Dy diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 6610e22236..a548e16ed5 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -298,6 +298,11 @@ static void gen_ldx(DisasContext *dc, uint32_t code, u= int32_t flags) TCGv data =3D dest_gpr(dc, instr.b); =20 tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s); +#ifdef CONFIG_USER_ONLY + flags |=3D MO_UNALN; +#else + flags |=3D MO_ALIGN; +#endif tcg_gen_qemu_ld_tl(data, addr, dc->mem_idx, flags); } =20 @@ -309,6 +314,11 @@ static void gen_stx(DisasContext *dc, uint32_t code, u= int32_t flags) =20 TCGv addr =3D tcg_temp_new(); tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s); +#ifdef CONFIG_USER_ONLY + flags |=3D MO_UNALN; +#else + flags |=3D MO_ALIGN; +#endif tcg_gen_qemu_st_tl(val, addr, dc->mem_idx, flags); } =20 --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683793000; cv=none; d=zohomail.com; s=zohoarc; b=ZO427SSjoOns7PaA/jpkn5tnKLV4Dq5Fbm1TvDDnPZF7pNAf8WbeXuqJaF7XbyqtRlmd27jt6oWSK7GxXHLfF13SeJ6XGugFzzSj+MBw2fKGcX197ejT+i4UKN0gKQcDPzAl99XWtHfRnhOsaf2NVYdAlLr2B6sozLC4V9jT4Ko= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683793000; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+wqFaYX77FecfowzNUovNB3QQCjaKPzOWuhGxAc2Dtw=; b=AcbBzMuckgrZaijF51gVBwId5x4EfIhTGg052nHnwfamChqeEKeHjGABS1kolPiK6MzrxzywiEJ6+hGGxP1FtkH9Fs/lDR2sg2b5EwH9/3wj+zlwVB6qOrSJGqm7BioPWS258Xrjj4MthoImsVaBETHBOYztd0Rou6PfQXX1jcY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683793000634602.983631414088; Thu, 11 May 2023 01:16:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Lg-0007Lv-DS; Thu, 11 May 2023 04:08:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Lc-0007JH-Vg for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:26 -0400 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1La-0001xK-Eo for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:24 -0400 Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-965ab8ed1fcso1498792466b.2 for ; Thu, 11 May 2023 01:08:22 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b00959c6cb82basm3635225ejc.105.2023.05.11.01.08.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:08:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792501; x=1686384501; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+wqFaYX77FecfowzNUovNB3QQCjaKPzOWuhGxAc2Dtw=; b=ijm8h0FbbLfH6Ky8d9LKUGTxsgprnYKGZah64BDfJl2ng56KZhd/PV1EFOOovp9Y2F 7fGl++DXf5Y9UmWnAYg7Jx8lx7WnnHBphXgFhRsBjxIIvJteIm8N0j8PfBe3q+mdKEek kNLE34piGQa4ChkI93opraLV1p0OaWih+KXVzdGYbOS0EGhAZIgf2ZRAXF2+kaMjPsHw P0UoSL+7cf+AeMlH84hC57Bnxc9KZwM6abshaZhyY0QUJtJo7xjPmmScFC6t7KzlYFzU 1gA28HuBDYGMb4kJ1E97+j8emDb/uz5NVYi9I/f+M97TpasMVkrLjGe09vI3DAMyc2bx OqAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792501; x=1686384501; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+wqFaYX77FecfowzNUovNB3QQCjaKPzOWuhGxAc2Dtw=; b=PnkcBwqMVmO5ICJceaVGQlGW/y7anSpPMIgi3QyF0Q3S1ZHi6FXCJ+DnCZNW29z7jt La2ePyuW7pDSfJRzydLp9XMCHxW+zZbK0qbXjzuK2G0xOoyzhero8AzfcCO0Zhz68tl2 kQsksyznWfHShDiEylcmCxy/eRm4TW3omqQpBnVvBL01hqT73Ck5u5ieclpEj6HwLNoO NrZXx7QbQxY+gOAyrQqILiEbnmJs0/BLPc7AIPmmayFKhtNTwyzSUscEACFOvclyTn18 9PecOvKAxVC1x7I7vBpRR29ubl74K1Q9K/qGeJKwDQTZsmuem5eoQTXjVSbDhjWfUZF7 H57g== X-Gm-Message-State: AC+VfDzXQjQ7FD0jBQA/P2bKC0R4rc83UHreP5iU+bWlyJD2Jurgc6Xz +idO2k4sC04/IAVSxget2ZnnYTt8p5+3inI2jcF8Yw== X-Google-Smtp-Source: ACHHUZ6361kJbaPiCa+65kePoB0JUp3ann2tHJFXO7ekZIK/PIaNeOulkv6qyZCPAUvSlYXdAt/TSQ== X-Received: by 2002:a17:907:a08:b0:965:95ba:eacd with SMTP id bb8-20020a1709070a0800b0096595baeacdmr18489048ejc.17.1683792500784; Thu, 11 May 2023 01:08:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 46/53] target/sh4: Use MO_ALIGN where required Date: Thu, 11 May 2023 09:04:43 +0100 Message-Id: <20230511080450.860923-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683793001815100004 Mark all memory operations that are not already marked with UNALIGN. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/sh4/translate.c | 102 ++++++++++++++++++++++++++--------------- 1 file changed, 66 insertions(+), 36 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 6e40d5dd6a..0dedbb8210 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -527,13 +527,15 @@ static void _decode_opc(DisasContext * ctx) case 0x9000: /* mov.w @(disp,PC),Rn */ { TCGv addr =3D tcg_constant_i32(ctx->base.pc_next + 4 + B7_0 * = 2); - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, + MO_TESW | MO_ALIGN); } return; case 0xd000: /* mov.l @(disp,PC),Rn */ { TCGv addr =3D tcg_constant_i32((ctx->base.pc_next + 4 + B7_0 *= 4) & ~3); - tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, + MO_TESL | MO_ALIGN); } return; case 0x7000: /* add #imm,Rn */ @@ -801,9 +803,11 @@ static void _decode_opc(DisasContext * ctx) { TCGv arg0, arg1; arg0 =3D tcg_temp_new(); - tcg_gen_qemu_ld_i32(arg0, REG(B7_4), ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(arg0, REG(B7_4), ctx->memidx, + MO_TESL | MO_ALIGN); arg1 =3D tcg_temp_new(); - tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, + MO_TESL | MO_ALIGN); gen_helper_macl(cpu_env, arg0, arg1); tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); @@ -813,9 +817,11 @@ static void _decode_opc(DisasContext * ctx) { TCGv arg0, arg1; arg0 =3D tcg_temp_new(); - tcg_gen_qemu_ld_i32(arg0, REG(B7_4), ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(arg0, REG(B7_4), ctx->memidx, + MO_TESL | MO_ALIGN); arg1 =3D tcg_temp_new(); - tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, + MO_TESL | MO_ALIGN); gen_helper_macw(cpu_env, arg0, arg1); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2); tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); @@ -961,30 +967,36 @@ static void _decode_opc(DisasContext * ctx) if (ctx->tbflags & FPSCR_SZ) { TCGv_i64 fp =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp, XHACK(B7_4)); - tcg_gen_qemu_st_i64(fp, REG(B11_8), ctx->memidx, MO_TEUQ); + tcg_gen_qemu_st_i64(fp, REG(B11_8), ctx->memidx, + MO_TEUQ | MO_ALIGN); } else { - tcg_gen_qemu_st_i32(FREG(B7_4), REG(B11_8), ctx->memidx, MO_TE= UL); + tcg_gen_qemu_st_i32(FREG(B7_4), REG(B11_8), ctx->memidx, + MO_TEUL | MO_ALIGN); } return; case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { TCGv_i64 fp =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(fp, REG(B7_4), ctx->memidx, MO_TEUQ); + tcg_gen_qemu_ld_i64(fp, REG(B7_4), ctx->memidx, + MO_TEUQ | MO_ALIGN); gen_store_fpr64(ctx, fp, XHACK(B11_8)); } else { - tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TE= UL); + tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, + MO_TEUL | MO_ALIGN); } return; case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { TCGv_i64 fp =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(fp, REG(B7_4), ctx->memidx, MO_TEUQ); + tcg_gen_qemu_ld_i64(fp, REG(B7_4), ctx->memidx, + MO_TEUQ | MO_ALIGN); gen_store_fpr64(ctx, fp, XHACK(B11_8)); tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8); } else { - tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TE= UL); + tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, + MO_TEUL | MO_ALIGN); tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); } return; @@ -996,10 +1008,12 @@ static void _decode_opc(DisasContext * ctx) TCGv_i64 fp =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp, XHACK(B7_4)); tcg_gen_subi_i32(addr, REG(B11_8), 8); - tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, MO_TEUQ); + tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, + MO_TEUQ | MO_ALIGN); } else { tcg_gen_subi_i32(addr, REG(B11_8), 4); - tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL= ); + tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, + MO_TEUL | MO_ALIGN); } tcg_gen_mov_i32(REG(B11_8), addr); } @@ -1011,10 +1025,12 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_add_i32(addr, REG(B7_4), REG(0)); if (ctx->tbflags & FPSCR_SZ) { TCGv_i64 fp =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(fp, addr, ctx->memidx, MO_TEUQ); + tcg_gen_qemu_ld_i64(fp, addr, ctx->memidx, + MO_TEUQ | MO_ALIGN); gen_store_fpr64(ctx, fp, XHACK(B11_8)); } else { - tcg_gen_qemu_ld_i32(FREG(B11_8), addr, ctx->memidx, MO_TEU= L); + tcg_gen_qemu_ld_i32(FREG(B11_8), addr, ctx->memidx, + MO_TEUL | MO_ALIGN); } } return; @@ -1026,9 +1042,11 @@ static void _decode_opc(DisasContext * ctx) if (ctx->tbflags & FPSCR_SZ) { TCGv_i64 fp =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp, XHACK(B7_4)); - tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, MO_TEUQ); + tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, + MO_TEUQ | MO_ALIGN); } else { - tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL= ); + tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, + MO_TEUL | MO_ALIGN); } } return; @@ -1158,14 +1176,14 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2); - tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW); + tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW | MO_AL= IGN); } return; case 0xc600: /* mov.l @(disp,GBR),R0 */ { TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4); - tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESL | MO_AL= IGN); } return; case 0xc000: /* mov.b R0,@(disp,GBR) */ @@ -1179,14 +1197,14 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2); - tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW); + tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW | MO_AL= IGN); } return; case 0xc200: /* mov.l R0,@(disp,GBR) */ { TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4); - tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUL | MO_AL= IGN); } return; case 0x8000: /* mov.b R0,@(disp,Rn) */ @@ -1286,7 +1304,8 @@ static void _decode_opc(DisasContext * ctx) return; case 0x4087: /* ldc.l @Rm+,Rn_BANK */ CHECK_PRIVILEGED - tcg_gen_qemu_ld_i32(ALTREG(B6_4), REG(B11_8), ctx->memidx, MO_TESL= ); + tcg_gen_qemu_ld_i32(ALTREG(B6_4), REG(B11_8), ctx->memidx, + MO_TESL | MO_ALIGN); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); return; case 0x0082: /* stc Rm_BANK,Rn */ @@ -1298,7 +1317,8 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 4); - tcg_gen_qemu_st_i32(ALTREG(B6_4), addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(ALTREG(B6_4), addr, ctx->memidx, + MO_TEUL | MO_ALIGN); tcg_gen_mov_i32(REG(B11_8), addr); } return; @@ -1354,7 +1374,8 @@ static void _decode_opc(DisasContext * ctx) CHECK_PRIVILEGED { TCGv val =3D tcg_temp_new(); - tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, + MO_TESL | MO_ALIGN); tcg_gen_andi_i32(val, val, 0x700083f3); gen_write_sr(val); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); @@ -1372,7 +1393,7 @@ static void _decode_opc(DisasContext * ctx) TCGv val =3D tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 4); gen_read_sr(val); - tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_TEUL | MO_ALIGN= ); tcg_gen_mov_i32(REG(B11_8), addr); } return; @@ -1383,7 +1404,8 @@ static void _decode_opc(DisasContext * ctx) return; \ case ldpnum: \ prechk \ - tcg_gen_qemu_ld_i32(cpu_##reg, REG(B11_8), ctx->memidx, MO_TESL); \ + tcg_gen_qemu_ld_i32(cpu_##reg, REG(B11_8), ctx->memidx, \ + MO_TESL | MO_ALIGN); \ tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \ return; #define ST(reg,stnum,stpnum,prechk) \ @@ -1396,7 +1418,8 @@ static void _decode_opc(DisasContext * ctx) { \ TCGv addr =3D tcg_temp_new(); \ tcg_gen_subi_i32(addr, REG(B11_8), 4); \ - tcg_gen_qemu_st_i32(cpu_##reg, addr, ctx->memidx, MO_TEUL); \ + tcg_gen_qemu_st_i32(cpu_##reg, addr, ctx->memidx, \ + MO_TEUL | MO_ALIGN); \ tcg_gen_mov_i32(REG(B11_8), addr); \ } \ return; @@ -1423,7 +1446,8 @@ static void _decode_opc(DisasContext * ctx) CHECK_FPU_ENABLED { TCGv addr =3D tcg_temp_new(); - tcg_gen_qemu_ld_i32(addr, REG(B11_8), ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(addr, REG(B11_8), ctx->memidx, + MO_TESL | MO_ALIGN); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); gen_helper_ld_fpscr(cpu_env, addr); ctx->base.is_jmp =3D DISAS_STOP; @@ -1441,16 +1465,18 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff); addr =3D tcg_temp_new(); tcg_gen_subi_i32(addr, REG(B11_8), 4); - tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_TEUL | MO_ALIGN= ); tcg_gen_mov_i32(REG(B11_8), addr); } return; case 0x00c3: /* movca.l R0,@Rm */ { TCGv val =3D tcg_temp_new(); - tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, MO_TEUL); + tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, + MO_TEUL | MO_ALIGN); gen_helper_movcal(cpu_env, REG(B11_8), val); - tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL); + tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, + MO_TEUL | MO_ALIGN); } ctx->has_movcal =3D 1; return; @@ -1492,11 +1518,13 @@ static void _decode_opc(DisasContext * ctx) cpu_lock_addr, fail); tmp =3D tcg_temp_new(); tcg_gen_atomic_cmpxchg_i32(tmp, REG(B11_8), cpu_lock_value, - REG(0), ctx->memidx, MO_TEUL); + REG(0), ctx->memidx, + MO_TEUL | MO_ALIGN); tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_t, tmp, cpu_lock_v= alue); } else { tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_lock_addr, -1, fail); - tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TE= UL); + tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, + MO_TEUL | MO_ALIGN); tcg_gen_movi_i32(cpu_sr_t, 1); } tcg_gen_br(done); @@ -1521,11 +1549,13 @@ static void _decode_opc(DisasContext * ctx) if ((tb_cflags(ctx->base.tb) & CF_PARALLEL)) { TCGv tmp =3D tcg_temp_new(); tcg_gen_mov_i32(tmp, REG(B11_8)); - tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, + MO_TESL | MO_ALIGN); tcg_gen_mov_i32(cpu_lock_value, REG(0)); tcg_gen_mov_i32(cpu_lock_addr, tmp); } else { - tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL); + tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, + MO_TESL | MO_ALIGN); tcg_gen_movi_i32(cpu_lock_addr, 0); } return; --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792905; cv=none; d=zohomail.com; s=zohoarc; b=V0GV0INGgStTxSQy1bvVNhcezl/zXr4tfgfYdXHXh2rnevNpZpS7CaD+reBpvl1H/51OXZC8NtEQJHxUetIg0vz325L+jdoKxmD2lMrhnK+AnV5zXLZbJ2GvJUyp6eq48PsPJAnIJZ1LpnAWduLFcqTMbm6HbftT14lTV/KyfRk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792905; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yv5GDSNkMoJwJa++KtzHV6S4Ef0nvuMaGkkgYlahBCM=; b=hVk3ktG7DGnHf01IxA4/EKxvy6QpdxyrZ7M7QrIugoUz5+ME90IgdVazs8JQg1ND+PVIJoTkZY6JE+bRhcdNJRohNnlkLHWpORsy0UTD8gbc0c35qDaQpJlE2nxzaB7KxgokIdhypxOwoUUx3N82QiAZ04UfMebeLi2W45IWGg4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792905737387.91136945057815; Thu, 11 May 2023 01:15:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Lf-0007LV-Vz; Thu, 11 May 2023 04:08:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Lc-0007IW-NM for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:24 -0400 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1La-0001xO-V2 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:24 -0400 Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-966287b0f72so1059260166b.0 for ; Thu, 11 May 2023 01:08:22 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b00959c6cb82basm3635225ejc.105.2023.05.11.01.08.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:08:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792501; x=1686384501; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yv5GDSNkMoJwJa++KtzHV6S4Ef0nvuMaGkkgYlahBCM=; b=wu/pzBi0Jv+OdI3TcDJmlM5N1CoH3oRfVmQOHu/S9o19XsP1Yi1pOgmSvqHzsuOh0p wqm0O5abCCNpncGQGFS3RVPcahIShqIq6JDz8t3SKvE8HVehYqjEFnFuiXQbPXOVZy8c N4TZOj5J7pd/varIXqbJcJMt1/hOGtaa0Ghgq08Mzt9uxa41wJNqZ0BSSvsNRGVGA9Su bOa2pryzVHo9L6hllv6qiapFcJkbKbrhu+CcBSq2zkX9+/tS+MjWbDlyOBRy53eIJPG3 Nx+TC0DTxVc1oFuqFHrNO7b1KghwSWOhKwumuPHjT06dCourVI8sx3BiCvNBlO/tM/XA 2y8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792501; x=1686384501; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yv5GDSNkMoJwJa++KtzHV6S4Ef0nvuMaGkkgYlahBCM=; b=EKPQe9Xwa11JEAQ2yWoozfvLPQwKG6+RjpmnGj9Ia9hLXBvFFYnKqkLEFsi7tuMyGA 28cWrKKQfSjbM30ym1wan/q4BD8GRtpSjqrHp9vzIj1rfuu0+a00Vh26NWYQOqq46t78 JmFAVAQG0E4gLHpmMCKQBbhWgLdIPLL4pna0D1N7r0SL8aX7bNlK6WZkOcts7cCJBWzO TI4S+K7oir8lHmV2rmcYe8zsO7UA8MPEPRd8UC5A4Byg3QZMPO5owZnOOhmmTuSB4upM smTt+XTKn/z5gZV5yAvlZzbqA83eK7Gi1bESyL/47e6K0QC2w3nLys8mvEJPSKGIte67 0Mqw== X-Gm-Message-State: AC+VfDyqdDiKgr1P0OWAuknD8e98Dx43deux04KdRSuKeyBvIybYoJ1i Vacbd6igKtSAnYMwzgeOVjSTDD9kJaTTvR5aprAA2A== X-Google-Smtp-Source: ACHHUZ7xUyK8kNjfVI/EAdr9plBxjSKtCPqLBEQOl7F4u2VI8NYI64/Bo+2Hzg87gj81d8GKLkWHuw== X-Received: by 2002:a17:906:fe04:b0:966:1984:9d21 with SMTP id wy4-20020a170906fe0400b0096619849d21mr14355840ejb.9.1683792501383; Thu, 11 May 2023 01:08:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 47/53] target/sh4: Remove TARGET_ALIGNED_ONLY Date: Thu, 11 May 2023 09:04:44 +0100 Message-Id: <20230511080450.860923-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792906984100003 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- configs/targets/sh4-linux-user.mak | 1 - configs/targets/sh4-softmmu.mak | 1 - configs/targets/sh4eb-linux-user.mak | 1 - configs/targets/sh4eb-softmmu.mak | 1 - 4 files changed, 4 deletions(-) diff --git a/configs/targets/sh4-linux-user.mak b/configs/targets/sh4-linux= -user.mak index 0152d6621e..9908887566 100644 --- a/configs/targets/sh4-linux-user.mak +++ b/configs/targets/sh4-linux-user.mak @@ -1,5 +1,4 @@ TARGET_ARCH=3Dsh4 TARGET_SYSTBL_ABI=3Dcommon TARGET_SYSTBL=3Dsyscall.tbl -TARGET_ALIGNED_ONLY=3Dy TARGET_HAS_BFLT=3Dy diff --git a/configs/targets/sh4-softmmu.mak b/configs/targets/sh4-softmmu.= mak index 95896376c4..f9d62d91e4 100644 --- a/configs/targets/sh4-softmmu.mak +++ b/configs/targets/sh4-softmmu.mak @@ -1,2 +1 @@ TARGET_ARCH=3Dsh4 -TARGET_ALIGNED_ONLY=3Dy diff --git a/configs/targets/sh4eb-linux-user.mak b/configs/targets/sh4eb-l= inux-user.mak index 6724165efe..9db6b3609c 100644 --- a/configs/targets/sh4eb-linux-user.mak +++ b/configs/targets/sh4eb-linux-user.mak @@ -1,6 +1,5 @@ TARGET_ARCH=3Dsh4 TARGET_SYSTBL_ABI=3Dcommon TARGET_SYSTBL=3Dsyscall.tbl -TARGET_ALIGNED_ONLY=3Dy TARGET_BIG_ENDIAN=3Dy TARGET_HAS_BFLT=3Dy diff --git a/configs/targets/sh4eb-softmmu.mak b/configs/targets/sh4eb-soft= mmu.mak index dc8b30bf7a..226b1fc698 100644 --- a/configs/targets/sh4eb-softmmu.mak +++ b/configs/targets/sh4eb-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=3Dsh4 -TARGET_ALIGNED_ONLY=3Dy TARGET_BIG_ENDIAN=3Dy --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792723; cv=none; d=zohomail.com; s=zohoarc; b=HfVGbjFszayUHU0IufmT0xX90HTkBv7SbGqGBoLjQqOKJqq5LU8bS3/D29jTVLFPOfNmilf8ykWnRk7CTj+hzpVV3/y0inthsMANUKEFFcirAoz5DQ4tZaaNaA4GltvPnFVo0bMxyaZ7CitDj+vAry33rKxsXq+ufaZDjpPuCWs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792723; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lDcrnDhHvM2xbQPbYn7Q5HQ0RaVgZKVfyZ/oIHJzpXQ=; b=JiPwKgr3tBtLgt55oyU7VIlaSK8wW8JJQQYeLULFxbTWMeyUwg6xZe1pJDacEh+yLkOcKSX7reL0wIS2arqJObdCTz/vAiGT1aCsrg0LLmm+wg2BqfyYZeODOBpT+RiBotI/eq17MWE6llRevcVhdy5tmNNvWdvaQ5snfBCoqPw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792723456974.5555200660363; Thu, 11 May 2023 01:12:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Le-0007L4-Qy; Thu, 11 May 2023 04:08:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Ld-0007JI-01 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:25 -0400 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1Lb-0001xi-Aj for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:24 -0400 Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-96622bca286so1120310766b.1 for ; Thu, 11 May 2023 01:08:22 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b00959c6cb82basm3635225ejc.105.2023.05.11.01.08.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:08:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792502; x=1686384502; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lDcrnDhHvM2xbQPbYn7Q5HQ0RaVgZKVfyZ/oIHJzpXQ=; b=RZeuBEcEYMWzL+62VPyTKFbTcDN1k0wSmwhtb/bC6GW+QBdnUjShSxe8p+yPniCIRF KzZHM+5k/5AXlHxD4phPn3ATiUgjdwtkRayhkeUkkRm4LNSLuXuhVEclJcNClXXpvITu A4tLHgjm6Bhlk8ITHHFNlaspcoZUR93kBb5ftwSXavl27dNLh5jYjqMSQIy1b/ZBaIuS IzYMo8k3wwO+cGYq88ul9l2zhfERAXpaJ1THDhoCVr7ObsCn3sAvgeYosezUnvq9YYTm ZOW5dz0uBro6K+3vHyrIHWGxhj3WgwnkAoPeVuf1+pju+/hj4R1C36m+7rVx9+3Ot6MF tOqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792502; x=1686384502; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lDcrnDhHvM2xbQPbYn7Q5HQ0RaVgZKVfyZ/oIHJzpXQ=; b=ckHBaORYSQ/6Q3y5tZVYpzg6nSvUTZ1TLS5+BdrxfsLEky+7b4o+qifBYHAKw9O3TM x2J7tincEFuCwlgpfw0aSOlnaZdxJUFfA97YuVV3eZgvCssAddVDX9BYiGxy9FaEC63g Tlt7DNHxpXv+WYxxnRJnHtRlRUObGRElrJlEIfayE1X7PY9R/Wfn6+7YquzIbPVOhbys RtRWvwcY16Emp5M7FkLAeAw9Ka8NHg59NG5PsXS9y2q6oyxifdCUvMFg+g3K5UNEghUh lE/fddhr8My7c2fRJGUsGvPwWyQR1h7GKcMSMuTCpJ/nd2+nmGawbYiDhDxbvomnv/yN PESg== X-Gm-Message-State: AC+VfDyidiBddBSf21uCs3RmXQyJ9keQSQzPAHeD//qRN/s7SAwMG92b PcIQbGH17NvOpXJQf96jLA/0pPuZdFeu0R9LtpiraA== X-Google-Smtp-Source: ACHHUZ7x3MUMvUXBNC10rhx/jdMmGng+N/n+GJI0JkXZZpjcYxiqf4K+D6HlAEWHe7Dj+krXzpUnNA== X-Received: by 2002:a17:907:940c:b0:960:ddba:e5bb with SMTP id dk12-20020a170907940c00b00960ddbae5bbmr18342977ejc.43.1683792501858; Thu, 11 May 2023 01:08:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 48/53] tcg: Remove TARGET_ALIGNED_ONLY Date: Thu, 11 May 2023 09:04:45 +0100 Message-Id: <20230511080450.860923-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792725207100003 All uses have now been expunged. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/memop.h | 13 ++----------- include/exec/poison.h | 1 - tcg/tcg.c | 5 ----- 3 files changed, 2 insertions(+), 17 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index 25d027434a..07f5f88188 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -47,8 +47,6 @@ typedef enum MemOp { * MO_UNALN accesses are never checked for alignment. * MO_ALIGN accesses will result in a call to the CPU's * do_unaligned_access hook if the guest address is not aligned. - * The default depends on whether the target CPU defines - * TARGET_ALIGNED_ONLY. * * Some architectures (e.g. ARMv8) need the address which is aligned * to a size more than the size of the memory access. @@ -65,21 +63,14 @@ typedef enum MemOp { */ MO_ASHIFT =3D 5, MO_AMASK =3D 0x7 << MO_ASHIFT, -#ifdef NEED_CPU_H -#ifdef TARGET_ALIGNED_ONLY - MO_ALIGN =3D 0, - MO_UNALN =3D MO_AMASK, -#else - MO_ALIGN =3D MO_AMASK, - MO_UNALN =3D 0, -#endif -#endif + MO_UNALN =3D 0, MO_ALIGN_2 =3D 1 << MO_ASHIFT, MO_ALIGN_4 =3D 2 << MO_ASHIFT, MO_ALIGN_8 =3D 3 << MO_ASHIFT, MO_ALIGN_16 =3D 4 << MO_ASHIFT, MO_ALIGN_32 =3D 5 << MO_ASHIFT, MO_ALIGN_64 =3D 6 << MO_ASHIFT, + MO_ALIGN =3D MO_AMASK, =20 /* Combinations of the above, for ease of use. */ MO_UB =3D MO_8, diff --git a/include/exec/poison.h b/include/exec/poison.h index 140daa4a85..256736e11a 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -35,7 +35,6 @@ #pragma GCC poison TARGET_TRICORE #pragma GCC poison TARGET_XTENSA =20 -#pragma GCC poison TARGET_ALIGNED_ONLY #pragma GCC poison TARGET_HAS_BFLT #pragma GCC poison TARGET_NAME #pragma GCC poison TARGET_SUPPORTS_MTTCG diff --git a/tcg/tcg.c b/tcg/tcg.c index 88fe01f59f..1231c8ab4c 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2185,13 +2185,8 @@ static const char * const ldst_name[] =3D }; =20 static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] =3D { -#ifdef TARGET_ALIGNED_ONLY [MO_UNALN >> MO_ASHIFT] =3D "un+", - [MO_ALIGN >> MO_ASHIFT] =3D "", -#else - [MO_UNALN >> MO_ASHIFT] =3D "", [MO_ALIGN >> MO_ASHIFT] =3D "al+", -#endif [MO_ALIGN_2 >> MO_ASHIFT] =3D "al2+", [MO_ALIGN_4 >> MO_ASHIFT] =3D "al4+", [MO_ALIGN_8 >> MO_ASHIFT] =3D "al8+", --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792938; cv=none; d=zohomail.com; s=zohoarc; b=W8vhQ8go9FmxWaPl7otrEK41A5IapU7BvPmDX8PaK/YRL36zNRvGN8NktV8Iv0QArSWL8iLVd/1HBnsEIWu5GpLvq7wGCaCkUBUPgY8HFR0lhxCBlCobzbrtZ70nm4qbnsunGrhBDep0mWlojLudADBg6lcotYSu64G5PbXzbW8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792938; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1td0lL0uZaD5nr2SdTp9WbksdhKvAu45hDttDXAoNxs=; b=erDCaLoKUsyuPAbWf8gZhg7G9V6yBXSN0JLxPzzStxJ3n3sgrrLQrrRgpyfIdAWGLbwvUVAohjheAdPaMnCwBVxRO16O5vr91iwYmIDEHlXl81yng0LM5HMBZ+RC8Rx6SJC+QH6Gehz6hWgYZgC+26KcjJHPExWWOSTCwGE8SHs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792938776458.1139770948972; Thu, 11 May 2023 01:15:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Lg-0007Lz-KI; Thu, 11 May 2023 04:08:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Le-0007KT-69 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:26 -0400 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1Lb-0001xz-RZ for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:25 -0400 Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-50bc456cc39so12324150a12.1 for ; Thu, 11 May 2023 01:08:23 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b00959c6cb82basm3635225ejc.105.2023.05.11.01.08.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:08:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792502; x=1686384502; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1td0lL0uZaD5nr2SdTp9WbksdhKvAu45hDttDXAoNxs=; b=OCYaw0V7XnjiaIw05stxbkjyYISym8QxhBPJDm71DvvMmug5HukivZ7j794do6Dhk4 eSMBthWCoIxsGa7OF9AWiCJgXu+uNvvrWqqc8s0bPNImeg3QVeY+cczVWP67j/rTKXM7 dyxd10x0J9b5WnBFI189G/ksD0LGrdDBnWoHpnQKuqGL9YajXclC2l4jB5FCFEMckugS 5R0Tk8imjSEkSrmjJhGlRhZHM8nK6+EL6RkRsXzTKGwEo6N5uO3YmWno3XDwB6HAwWyO QjJoaQDWhck4EzGKZU1WwMX3yVHzSNNSlMmxAmtRQVReJXgtzyFWxjIryS6x+s9ppCa8 ggyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792502; x=1686384502; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1td0lL0uZaD5nr2SdTp9WbksdhKvAu45hDttDXAoNxs=; b=Q26w4f9HQErsHdsF+09/8rPGijddLZr2P6B2uKK+ExE24eug4p6cTZSgfDwW58vreK tbtvS4/ZYij2QWm7ehHRAZBYjHrgDiJDf6QmME5pSfzV/r3d6BhdYPc0Mo5rWeiQ5q40 7K8EAoL9fb+mPwyrkZS0yK27/bvc8IeKWUCUnXrcI2xwg/CTdafDrS5bl7PXb+iXuk5G 7BHcE+0O5cghscjGk/nFqbyjVzZBmNAN8+44PYzuD4Czy3n6sQDZztHD54wVRjwrGBYN 01vxMdbBourhFHAeOjQWjufXYKhnOyyNLTbbgpZfSvsbg0uaUvSLez5W6t/MsBguzx1t 0H/A== X-Gm-Message-State: AC+VfDxsun6vdcR/aJMtdsaOLWqEzLZMv3zEOg7wYwJU0Cko62HI+G7q Sp0YCwSKduVh9d8afYIMOYiZq5BC+JCvYYTjlQIYqQ== X-Google-Smtp-Source: ACHHUZ4DwxIlIkYT2DmgCE30Gh5QYwnZ/zKHrUx3t5IoRAEHitQCRYsBYGHxCUaUnBV6euHahruEzg== X-Received: by 2002:a17:907:1607:b0:96a:440b:d5c8 with SMTP id hb7-20020a170907160700b0096a440bd5c8mr3113691ejc.59.1683792502557; Thu, 11 May 2023 01:08:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PULL 49/53] accel/tcg: Add cpu_in_serial_context Date: Thu, 11 May 2023 09:04:46 +0100 Message-Id: <20230511080450.860923-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792939535100003 Like cpu_in_exclusive_context, but also true if there is no other cpu against which we could race. Use it in tb_flush as a direct replacement. Use it in cpu_loop_exit_atomic to ensure that there is no loop against cpu_exec_step_atomic. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- accel/tcg/internal.h | 9 +++++++++ accel/tcg/cpu-exec-common.c | 3 +++ accel/tcg/tb-maint.c | 2 +- 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h index 7bb0fdbe14..24f225cac7 100644 --- a/accel/tcg/internal.h +++ b/accel/tcg/internal.h @@ -64,6 +64,15 @@ static inline target_ulong log_pc(CPUState *cpu, const T= ranslationBlock *tb) } } =20 +/* + * Return true if CS is not running in parallel with other cpus, either + * because there are no other cpus or we are within an exclusive context. + */ +static inline bool cpu_in_serial_context(CPUState *cs) +{ + return !(cs->tcg_cflags & CF_PARALLEL) || cpu_in_exclusive_context(cs); +} + extern int64_t max_delay; extern int64_t max_advance; =20 diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c index e7962c9348..9a5fabf625 100644 --- a/accel/tcg/cpu-exec-common.c +++ b/accel/tcg/cpu-exec-common.c @@ -22,6 +22,7 @@ #include "sysemu/tcg.h" #include "exec/exec-all.h" #include "qemu/plugin.h" +#include "internal.h" =20 bool tcg_allowed; =20 @@ -81,6 +82,8 @@ void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc) =20 void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc) { + /* Prevent looping if already executing in a serial context. */ + g_assert(!cpu_in_serial_context(cpu)); cpu->exception_index =3D EXCP_ATOMIC; cpu_loop_exit_restore(cpu, pc); } diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index 0dd173fbf0..991746f80f 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -760,7 +760,7 @@ void tb_flush(CPUState *cpu) if (tcg_enabled()) { unsigned tb_flush_count =3D qatomic_read(&tb_ctx.tb_flush_count); =20 - if (cpu_in_exclusive_context(cpu)) { + if (cpu_in_serial_context(cpu)) { do_tb_flush(cpu, RUN_ON_CPU_HOST_INT(tb_flush_count)); } else { async_safe_run_on_cpu(cpu, do_tb_flush, --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683793003; cv=none; d=zohomail.com; s=zohoarc; b=cbIHQaeH7RdU7/jxqqb64htrGgFgzwCPECRs+DPYeT79p5MvqZ5KroQqY9qj9G5FsI5k6WeZp63KZDRxIwjFPBsny3vPEcrY7JsL+YZ7Gr9adA8heU3lM5VeuIol+S8MYqIsLnGdyv1mhZyRmd0imUPVoqqKRfw5HiJxkCHjapM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683793003; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=g/dmi9xjBdUQfTaksbEx13XlYlPUDWswdK9wXBJTckw=; b=m3wGNM5JWvyUmoAKST4XFIjBRyOD5oIwG3MhMVtsrE8PYQ7Xeu3dgB0cZlgGoYWiaPj7PctXT7eInsoz+prBEcrG+zhel5qWwLPxTWXCe6JPpdIYvJGbhFBJ4gzYqTj+koh+AEMGisDcttCLYkvxVsPeSdPnUhDXDL4koIu0Hxw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683793003042183.86247980947178; Thu, 11 May 2023 01:16:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Lu-0007gN-C7; Thu, 11 May 2023 04:08:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Ls-0007fP-C5 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:40 -0400 Received: from mail-ed1-x52e.google.com ([2a00:1450:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1Lc-0001y9-Pv for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:40 -0400 Received: by mail-ed1-x52e.google.com with SMTP id 4fb4d7f45d1cf-50bd875398dso12517524a12.1 for ; Thu, 11 May 2023 01:08:24 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b00959c6cb82basm3635225ejc.105.2023.05.11.01.08.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:08:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792503; x=1686384503; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g/dmi9xjBdUQfTaksbEx13XlYlPUDWswdK9wXBJTckw=; b=D4hkTnokiT2ryCCE29kGk78EmsWaERmMyqIYygqtdAbZWnc3c+jJPOq3Jg923piWYR h78JjKJcl448nqs5VYDKTw3A/Bck97VNT0xx1oMQxLzVFTK+c8Y1Gf/fzGiN4TWKFfq/ tr2vMPedvOQJvyX+9PCqIJFI68Y7GeWLNXwyQEywq9J2EbIQP0yhs90rtGkAdEZqpZGl mHsOpWuPzTWeYxTCq0vYMZa0DwfNmAhRMkyAZb8TVMeTIQTSnbWf6j6x+7PGpSSKqtBj TUyHjm54Z5BpIKg/jQcCNg4s+lDtHGSe6WG0Nsqye9nV1XGOsygqO6HxgsndmTDnzJn2 6Z/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792503; x=1686384503; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g/dmi9xjBdUQfTaksbEx13XlYlPUDWswdK9wXBJTckw=; b=h8aaYv/gfU0BxfQH/wFmZtdo9QWKvpdj7vyV+CIu5WaPj9k6Zr60TwH+9iYJxWzpxF KfztzYEhXfXXMgY2an1UX5v6+V5RRl8oDqZpcrI9MIhmSbUUW3cGJ68sjypwOriiRhmy ksjZgBgNDGFbRT12RxedvwGBTfE6oF25kd2uqSlS2wCyMKkrKGh9U6jkiFOkGEqZPH6F HtTuLcxn4ym+kryseaT4lprAIAImRV4wP2A13J+VFzg+uOGkXN7IDdRI1eJZANp4yz6h ALum2msZSdITkJ8oUFtIU+HH/dKDPXE3FG77rz9ci/bTTYnikirgLXd3AkDVX+pSYCDN LojA== X-Gm-Message-State: AC+VfDwJK+g6l0J1Dh5ePr/BeJlj12yc3K4vzSmUzsDSQy46HOhaLX39 BFkWIgoCMu6WxLYrHPdbP5Xd/WufGW+jURczocCOfA== X-Google-Smtp-Source: ACHHUZ6I8n+Y9Qr54dP+QcjLHxwBt0cP1g4L9q5HLL/32326NKQNU0SvhidJN+WPP2v45eU1N+1qjw== X-Received: by 2002:a17:907:928b:b0:966:2123:e0c3 with SMTP id bw11-20020a170907928b00b009662123e0c3mr13642791ejc.15.1683792503213; Thu, 11 May 2023 01:08:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PULL 50/53] accel/tcg: Introduce tlb_read_idx Date: Thu, 11 May 2023 09:04:47 +0100 Message-Id: <20230511080450.860923-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683793003831100013 Instead of playing with offsetof in various places, use MMUAccessType to index an array. This is easily defined instead of the previous dummy padding array in the union. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 7 ++- include/exec/cpu_ldst.h | 26 ++++++++-- accel/tcg/cputlb.c | 104 +++++++++++++--------------------------- 3 files changed, 59 insertions(+), 78 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index e1c498ef4b..a6e0cf1812 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -111,8 +111,11 @@ typedef struct CPUTLBEntry { use the corresponding iotlb value. */ uintptr_t addend; }; - /* padding to get a power of two size */ - uint8_t dummy[1 << CPU_TLB_ENTRY_BITS]; + /* + * Padding to get a power of two size, as well as index + * access to addr_{read,write,code}. + */ + target_ulong addr_idx[(1 << CPU_TLB_ENTRY_BITS) / TARGET_LONG_SIZE= ]; }; } CPUTLBEntry; =20 diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index c141f0394f..7c867c94c3 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -360,13 +360,29 @@ static inline void clear_helper_retaddr(void) /* Needed for TCG_OVERSIZED_GUEST */ #include "tcg/tcg.h" =20 +static inline target_ulong tlb_read_idx(const CPUTLBEntry *entry, + MMUAccessType access_type) +{ + /* Do not rearrange the CPUTLBEntry structure members. */ + QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_read) !=3D + MMU_DATA_LOAD * TARGET_LONG_SIZE); + QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_write) !=3D + MMU_DATA_STORE * TARGET_LONG_SIZE); + QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) !=3D + MMU_INST_FETCH * TARGET_LONG_SIZE); + + const target_ulong *ptr =3D &entry->addr_idx[access_type]; +#if TCG_OVERSIZED_GUEST + return *ptr; +#else + /* ofs might correspond to .addr_write, so use qatomic_read */ + return qatomic_read(ptr); +#endif +} + static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry) { -#if TCG_OVERSIZED_GUEST - return entry->addr_write; -#else - return qatomic_read(&entry->addr_write); -#endif + return tlb_read_idx(entry, MMU_DATA_STORE); } =20 /* Find the TLB index corresponding to the mmu_idx + address pair. */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 0b8a5f93d2..5051244c67 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1441,34 +1441,17 @@ static void io_writex(CPUArchState *env, CPUTLBEntr= yFull *full, } } =20 -static inline target_ulong tlb_read_ofs(CPUTLBEntry *entry, size_t ofs) -{ -#if TCG_OVERSIZED_GUEST - return *(target_ulong *)((uintptr_t)entry + ofs); -#else - /* ofs might correspond to .addr_write, so use qatomic_read */ - return qatomic_read((target_ulong *)((uintptr_t)entry + ofs)); -#endif -} - /* Return true if ADDR is present in the victim tlb, and has been copied back to the main tlb. */ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, - size_t elt_ofs, target_ulong page) + MMUAccessType access_type, target_ulong page) { size_t vidx; =20 assert_cpu_is_self(env_cpu(env)); for (vidx =3D 0; vidx < CPU_VTLB_SIZE; ++vidx) { CPUTLBEntry *vtlb =3D &env_tlb(env)->d[mmu_idx].vtable[vidx]; - target_ulong cmp; - - /* elt_ofs might correspond to .addr_write, so use qatomic_read */ -#if TCG_OVERSIZED_GUEST - cmp =3D *(target_ulong *)((uintptr_t)vtlb + elt_ofs); -#else - cmp =3D qatomic_read((target_ulong *)((uintptr_t)vtlb + elt_ofs)); -#endif + target_ulong cmp =3D tlb_read_idx(vtlb, access_type); =20 if (cmp =3D=3D page) { /* Found entry in victim tlb, swap tlb and iotlb. */ @@ -1490,11 +1473,6 @@ static bool victim_tlb_hit(CPUArchState *env, size_t= mmu_idx, size_t index, return false; } =20 -/* Macro to call the above, with local variables from the use context. */ -#define VICTIM_TLB_HIT(TY, ADDR) \ - victim_tlb_hit(env, mmu_idx, index, offsetof(CPUTLBEntry, TY), \ - (ADDR) & TARGET_PAGE_MASK) - static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size, CPUTLBEntryFull *full, uintptr_t retaddr) { @@ -1527,29 +1505,12 @@ static int probe_access_internal(CPUArchState *env,= target_ulong addr, { uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr, page_addr; - size_t elt_ofs; - int flags; + target_ulong tlb_addr =3D tlb_read_idx(entry, access_type); + target_ulong page_addr =3D addr & TARGET_PAGE_MASK; + int flags =3D TLB_FLAGS_MASK; =20 - switch (access_type) { - case MMU_DATA_LOAD: - elt_ofs =3D offsetof(CPUTLBEntry, addr_read); - break; - case MMU_DATA_STORE: - elt_ofs =3D offsetof(CPUTLBEntry, addr_write); - break; - case MMU_INST_FETCH: - elt_ofs =3D offsetof(CPUTLBEntry, addr_code); - break; - default: - g_assert_not_reached(); - } - tlb_addr =3D tlb_read_ofs(entry, elt_ofs); - - flags =3D TLB_FLAGS_MASK; - page_addr =3D addr & TARGET_PAGE_MASK; if (!tlb_hit_page(tlb_addr, page_addr)) { - if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) { + if (!victim_tlb_hit(env, mmu_idx, index, access_type, page_addr)) { CPUState *cs =3D env_cpu(env); =20 if (!cs->cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_ty= pe, @@ -1571,7 +1532,7 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, */ flags &=3D ~TLB_INVALID_MASK; } - tlb_addr =3D tlb_read_ofs(entry, elt_ofs); + tlb_addr =3D tlb_read_idx(entry, access_type); } flags &=3D tlb_addr; =20 @@ -1802,7 +1763,8 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, if (prot & PAGE_WRITE) { tlb_addr =3D tlb_addr_write(tlbe); if (!tlb_hit(tlb_addr, addr)) { - if (!VICTIM_TLB_HIT(addr_write, addr)) { + if (!victim_tlb_hit(env, mmu_idx, index, MMU_DATA_STORE, + addr & TARGET_PAGE_MASK)) { tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE, mmu_idx, retaddr); index =3D tlb_index(env, mmu_idx, addr); @@ -1835,7 +1797,8 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, } else /* if (prot & PAGE_READ) */ { tlb_addr =3D tlbe->addr_read; if (!tlb_hit(tlb_addr, addr)) { - if (!VICTIM_TLB_HIT(addr_read, addr)) { + if (!victim_tlb_hit(env, mmu_idx, index, MMU_DATA_LOAD, + addr & TARGET_PAGE_MASK)) { tlb_fill(env_cpu(env), addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); index =3D tlb_index(env, mmu_idx, addr); @@ -1929,13 +1892,9 @@ load_memop(const void *haddr, MemOp op) =20 static inline uint64_t QEMU_ALWAYS_INLINE load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi, - uintptr_t retaddr, MemOp op, bool code_read, + uintptr_t retaddr, MemOp op, MMUAccessType access_type, FullLoadHelper *full_load) { - const size_t tlb_off =3D code_read ? - offsetof(CPUTLBEntry, addr_code) : offsetof(CPUTLBEntry, addr_read= ); - const MMUAccessType access_type =3D - code_read ? MMU_INST_FETCH : MMU_DATA_LOAD; const unsigned a_bits =3D get_alignment_bits(get_memop(oi)); const size_t size =3D memop_size(op); uintptr_t mmu_idx =3D get_mmuidx(oi); @@ -1955,18 +1914,18 @@ load_helper(CPUArchState *env, target_ulong addr, M= emOpIdx oi, =20 index =3D tlb_index(env, mmu_idx, addr); entry =3D tlb_entry(env, mmu_idx, addr); - tlb_addr =3D code_read ? entry->addr_code : entry->addr_read; + tlb_addr =3D tlb_read_idx(entry, access_type); =20 /* If the TLB entry is for a different page, reload and try again. */ if (!tlb_hit(tlb_addr, addr)) { - if (!victim_tlb_hit(env, mmu_idx, index, tlb_off, + if (!victim_tlb_hit(env, mmu_idx, index, access_type, addr & TARGET_PAGE_MASK)) { tlb_fill(env_cpu(env), addr, size, access_type, mmu_idx, retaddr); index =3D tlb_index(env, mmu_idx, addr); entry =3D tlb_entry(env, mmu_idx, addr); } - tlb_addr =3D code_read ? entry->addr_code : entry->addr_read; + tlb_addr =3D tlb_read_idx(entry, access_type); tlb_addr &=3D ~TLB_INVALID_MASK; } =20 @@ -2052,7 +2011,8 @@ static uint64_t full_ldub_mmu(CPUArchState *env, targ= et_ulong addr, MemOpIdx oi, uintptr_t retaddr) { validate_memop(oi, MO_UB); - return load_helper(env, addr, oi, retaddr, MO_UB, false, full_ldub_mmu= ); + return load_helper(env, addr, oi, retaddr, MO_UB, MMU_DATA_LOAD, + full_ldub_mmu); } =20 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, @@ -2065,7 +2025,7 @@ static uint64_t full_le_lduw_mmu(CPUArchState *env, t= arget_ulong addr, MemOpIdx oi, uintptr_t retaddr) { validate_memop(oi, MO_LEUW); - return load_helper(env, addr, oi, retaddr, MO_LEUW, false, + return load_helper(env, addr, oi, retaddr, MO_LEUW, MMU_DATA_LOAD, full_le_lduw_mmu); } =20 @@ -2079,7 +2039,7 @@ static uint64_t full_be_lduw_mmu(CPUArchState *env, t= arget_ulong addr, MemOpIdx oi, uintptr_t retaddr) { validate_memop(oi, MO_BEUW); - return load_helper(env, addr, oi, retaddr, MO_BEUW, false, + return load_helper(env, addr, oi, retaddr, MO_BEUW, MMU_DATA_LOAD, full_be_lduw_mmu); } =20 @@ -2093,7 +2053,7 @@ static uint64_t full_le_ldul_mmu(CPUArchState *env, t= arget_ulong addr, MemOpIdx oi, uintptr_t retaddr) { validate_memop(oi, MO_LEUL); - return load_helper(env, addr, oi, retaddr, MO_LEUL, false, + return load_helper(env, addr, oi, retaddr, MO_LEUL, MMU_DATA_LOAD, full_le_ldul_mmu); } =20 @@ -2107,7 +2067,7 @@ static uint64_t full_be_ldul_mmu(CPUArchState *env, t= arget_ulong addr, MemOpIdx oi, uintptr_t retaddr) { validate_memop(oi, MO_BEUL); - return load_helper(env, addr, oi, retaddr, MO_BEUL, false, + return load_helper(env, addr, oi, retaddr, MO_BEUL, MMU_DATA_LOAD, full_be_ldul_mmu); } =20 @@ -2121,7 +2081,7 @@ uint64_t helper_le_ldq_mmu(CPUArchState *env, target_= ulong addr, MemOpIdx oi, uintptr_t retaddr) { validate_memop(oi, MO_LEUQ); - return load_helper(env, addr, oi, retaddr, MO_LEUQ, false, + return load_helper(env, addr, oi, retaddr, MO_LEUQ, MMU_DATA_LOAD, helper_le_ldq_mmu); } =20 @@ -2129,7 +2089,7 @@ uint64_t helper_be_ldq_mmu(CPUArchState *env, target_= ulong addr, MemOpIdx oi, uintptr_t retaddr) { validate_memop(oi, MO_BEUQ); - return load_helper(env, addr, oi, retaddr, MO_BEUQ, false, + return load_helper(env, addr, oi, retaddr, MO_BEUQ, MMU_DATA_LOAD, helper_be_ldq_mmu); } =20 @@ -2325,7 +2285,6 @@ store_helper_unaligned(CPUArchState *env, target_ulon= g addr, uint64_t val, uintptr_t retaddr, size_t size, uintptr_t mmu_idx, bool big_endian) { - const size_t tlb_off =3D offsetof(CPUTLBEntry, addr_write); uintptr_t index, index2; CPUTLBEntry *entry, *entry2; target_ulong page1, page2, tlb_addr, tlb_addr2; @@ -2347,7 +2306,7 @@ store_helper_unaligned(CPUArchState *env, target_ulon= g addr, uint64_t val, =20 tlb_addr2 =3D tlb_addr_write(entry2); if (page1 !=3D page2 && !tlb_hit_page(tlb_addr2, page2)) { - if (!victim_tlb_hit(env, mmu_idx, index2, tlb_off, page2)) { + if (!victim_tlb_hit(env, mmu_idx, index2, MMU_DATA_STORE, page2)) { tlb_fill(env_cpu(env), page2, size2, MMU_DATA_STORE, mmu_idx, retaddr); index2 =3D tlb_index(env, mmu_idx, page2); @@ -2400,7 +2359,6 @@ static inline void QEMU_ALWAYS_INLINE store_helper(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr, MemOp op) { - const size_t tlb_off =3D offsetof(CPUTLBEntry, addr_write); const unsigned a_bits =3D get_alignment_bits(get_memop(oi)); const size_t size =3D memop_size(op); uintptr_t mmu_idx =3D get_mmuidx(oi); @@ -2423,7 +2381,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, =20 /* If the TLB entry is for a different page, reload and try again. */ if (!tlb_hit(tlb_addr, addr)) { - if (!victim_tlb_hit(env, mmu_idx, index, tlb_off, + if (!victim_tlb_hit(env, mmu_idx, index, MMU_DATA_STORE, addr & TARGET_PAGE_MASK)) { tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE, mmu_idx, retaddr); @@ -2729,7 +2687,8 @@ void cpu_st16_le_mmu(CPUArchState *env, abi_ptr addr,= Int128 val, static uint64_t full_ldub_code(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, MO_8, true, full_ldub_code); + return load_helper(env, addr, oi, retaddr, MO_8, + MMU_INST_FETCH, full_ldub_code); } =20 uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr) @@ -2741,7 +2700,8 @@ uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr add= r) static uint64_t full_lduw_code(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, MO_TEUW, true, full_lduw_co= de); + return load_helper(env, addr, oi, retaddr, MO_TEUW, + MMU_INST_FETCH, full_lduw_code); } =20 uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr) @@ -2753,7 +2713,8 @@ uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr add= r) static uint64_t full_ldl_code(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, MO_TEUL, true, full_ldl_cod= e); + return load_helper(env, addr, oi, retaddr, MO_TEUL, + MMU_INST_FETCH, full_ldl_code); } =20 uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr) @@ -2765,7 +2726,8 @@ uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr) static uint64_t full_ldq_code(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, MO_TEUQ, true, full_ldq_cod= e); + return load_helper(env, addr, oi, retaddr, MO_TEUQ, + MMU_INST_FETCH, full_ldq_code); } =20 uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr) --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792977; cv=none; d=zohomail.com; s=zohoarc; b=QNrbDsPyuNVe0SkP0aqjcV3pjS0gArUHzDh55LHA5x6b2xLewJkn3Iqs1TCxoWiBAxQPUN9LAVSk6ZZQLhKPcygoWUTyejALETwdA0ty/pv8wLUphxMYu3BlYTi2xJR2IJOfdTorTwHNBkUu77zaCzd/A4KzUpNRKkvKySToq+4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792977; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GmpQgRav3/4O7T1GtYm2GYBY5JRmKoxdeunMGCNRMyA=; b=EGOEAJNn53bM8mJX+xS9owdeCkRmr5KlGQeilH7zPsOTAwTclmwsigTBvUBxVnK6KITeJRMw4lSwFHTXv32EiwHXYRVTQXEmK8AF3A6ABWfZ/HqxqUpyrh2Bft3grvvGeUd7uE4tJs9NwZCUKn34qBec2fke1YplXuleLZUwi0o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792977055283.1985351906693; Thu, 11 May 2023 01:16:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Li-0007MS-4z; Thu, 11 May 2023 04:08:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Lg-0007Lx-H3 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:28 -0400 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1Ld-0001yJ-8r for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:28 -0400 Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-965c3f9af2aso1239447066b.0 for ; Thu, 11 May 2023 01:08:24 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b00959c6cb82basm3635225ejc.105.2023.05.11.01.08.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:08:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792504; x=1686384504; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GmpQgRav3/4O7T1GtYm2GYBY5JRmKoxdeunMGCNRMyA=; b=R2q8o3hcZ+dxPF9ybOcR6MpX6BpDCWi3vk51JExy0bziheg/11N3MNsAI3KsGwUA+X iYQbb+zQBYQwhrgdruxY+Jgoz7/ngk+ADQp9laAQSfyAd1U/fdcH2UTcKEhItEg9T1e2 cetCxKux0RGmriBxtEN/j+SHW1PDaTRXhpDyjuFakIhLSez9Gmvb9nEZsjcXi+z4Vf5I oUX2iuDNSoLGgq4hDW7gykHvNmPvBfZPlORys8cOLE+AZmctCiXlY5jezEOAYe0gtVrB WvmrjgZY+8tfpf34VP02Sx2Ol9uuB9z82KU6GNZUJahjI13ZnxX53mjBm3/YOiVGrLgF utjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792504; x=1686384504; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GmpQgRav3/4O7T1GtYm2GYBY5JRmKoxdeunMGCNRMyA=; b=eemyHr5NZSQAFDAbYfh1MIHkQ/qlf9t6Ge3IUdTx1Wj/tFPTLUmylsZ2cAL2UGJsVx eG1dhDvhSmZB8r1G2CQLJ19RuykwoCJhzAaA9FIaVyLp6FhnvIrBy0PLSqL9KUAyryYM bk0x7GlfKRwKEF1XhtgZZoTZTkQsxXG0Moj0esF3G1Sx0KT6YvDs8MJjunobhFQV1wWj fjvnSRLi5Q4//Zv2uDxkXFazDuSo3MNFRJE7RqR16/LEzr+w3E3wDnm6EeMHR4NIGNzh +pxLEQUTQKw521zFaBtGzdTc7LS9RhPwEfTohxis8fVT4HvkjNtDOTbldrcbj55Ychqu VRKQ== X-Gm-Message-State: AC+VfDziKt1Q9VR4q5n0QRQhJskL7l222TYvkN9iK0KUfi2blmi88zXV 7X0PG3tZIiGZH34DmsNeQYxO2pHOxa5pKjpZcMrvig== X-Google-Smtp-Source: ACHHUZ5sN5cdEW1a9XuMlJ1bimar+SQNUW+X7/2VRnBzNKNrikI1lrEGdJXZ6sPUr17b4Oj/mPH2Uw== X-Received: by 2002:a17:907:70d:b0:948:eed:b4e0 with SMTP id xb13-20020a170907070d00b009480eedb4e0mr18549785ejb.61.1683792503742; Thu, 11 May 2023 01:08:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell Subject: [PULL 51/53] accel/tcg: Reorg system mode load helpers Date: Thu, 11 May 2023 09:04:48 +0100 Message-Id: <20230511080450.860923-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792977971100003 Instead of trying to unify all operations on uint64_t, pull out mmu_lookup() to perform the basic tlb hit and resolution. Create individual functions to handle access by size. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 645 +++++++++++++++++++++++++++++---------------- 1 file changed, 424 insertions(+), 221 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 5051244c67..a85edd8246 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1716,6 +1716,179 @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong = addr, int mmu_idx, =20 #endif =20 +/* + * Probe for a load/store operation. + * Return the host address and into @flags. + */ + +typedef struct MMULookupPageData { + CPUTLBEntryFull *full; + void *haddr; + target_ulong addr; + int flags; + int size; +} MMULookupPageData; + +typedef struct MMULookupLocals { + MMULookupPageData page[2]; + MemOp memop; + int mmu_idx; +} MMULookupLocals; + +/** + * mmu_lookup1: translate one page + * @env: cpu context + * @data: lookup parameters + * @mmu_idx: virtual address context + * @access_type: load/store/code + * @ra: return address into tcg generated code, or 0 + * + * Resolve the translation for the one page at @data.addr, filling in + * the rest of @data with the results. If the translation fails, + * tlb_fill will longjmp out. Return true if the softmmu tlb for + * @mmu_idx may have resized. + */ +static bool mmu_lookup1(CPUArchState *env, MMULookupPageData *data, + int mmu_idx, MMUAccessType access_type, uintptr_t = ra) +{ + target_ulong addr =3D data->addr; + uintptr_t index =3D tlb_index(env, mmu_idx, addr); + CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); + target_ulong tlb_addr =3D tlb_read_idx(entry, access_type); + bool maybe_resized =3D false; + + /* If the TLB entry is for a different page, reload and try again. */ + if (!tlb_hit(tlb_addr, addr)) { + if (!victim_tlb_hit(env, mmu_idx, index, access_type, + addr & TARGET_PAGE_MASK)) { + tlb_fill(env_cpu(env), addr, data->size, access_type, mmu_idx,= ra); + maybe_resized =3D true; + index =3D tlb_index(env, mmu_idx, addr); + entry =3D tlb_entry(env, mmu_idx, addr); + } + tlb_addr =3D tlb_read_idx(entry, access_type) & ~TLB_INVALID_MASK; + } + + data->flags =3D tlb_addr & TLB_FLAGS_MASK; + data->full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; + /* Compute haddr speculatively; depending on flags it might be invalid= . */ + data->haddr =3D (void *)((uintptr_t)addr + entry->addend); + + return maybe_resized; +} + +/** + * mmu_watch_or_dirty + * @env: cpu context + * @data: lookup parameters + * @access_type: load/store/code + * @ra: return address into tcg generated code, or 0 + * + * Trigger watchpoints for @data.addr:@data.size; + * record writes to protected clean pages. + */ +static void mmu_watch_or_dirty(CPUArchState *env, MMULookupPageData *data, + MMUAccessType access_type, uintptr_t ra) +{ + CPUTLBEntryFull *full =3D data->full; + target_ulong addr =3D data->addr; + int flags =3D data->flags; + int size =3D data->size; + + /* On watchpoint hit, this will longjmp out. */ + if (flags & TLB_WATCHPOINT) { + int wp =3D access_type =3D=3D MMU_DATA_STORE ? BP_MEM_WRITE : BP_M= EM_READ; + cpu_check_watchpoint(env_cpu(env), addr, size, full->attrs, wp, ra= ); + flags &=3D ~TLB_WATCHPOINT; + } + + /* Note that notdirty is only set for writes. */ + if (flags & TLB_NOTDIRTY) { + notdirty_write(env_cpu(env), addr, size, full, ra); + flags &=3D ~TLB_NOTDIRTY; + } + data->flags =3D flags; +} + +/** + * mmu_lookup: translate page(s) + * @env: cpu context + * @addr: virtual address + * @oi: combined mmu_idx and MemOp + * @ra: return address into tcg generated code, or 0 + * @access_type: load/store/code + * @l: output result + * + * Resolve the translation for the page(s) beginning at @addr, for MemOp.s= ize + * bytes. Return true if the lookup crosses a page boundary. + */ +static bool mmu_lookup(CPUArchState *env, target_ulong addr, MemOpIdx oi, + uintptr_t ra, MMUAccessType type, MMULookupLocals *= l) +{ + unsigned a_bits; + bool crosspage; + int flags; + + l->memop =3D get_memop(oi); + l->mmu_idx =3D get_mmuidx(oi); + + tcg_debug_assert(l->mmu_idx < NB_MMU_MODES); + + /* Handle CPU specific unaligned behaviour */ + a_bits =3D get_alignment_bits(l->memop); + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(env_cpu(env), addr, type, l->mmu_idx, ra); + } + + l->page[0].addr =3D addr; + l->page[0].size =3D memop_size(l->memop); + l->page[1].addr =3D (addr + l->page[0].size - 1) & TARGET_PAGE_MASK; + l->page[1].size =3D 0; + crosspage =3D (addr ^ l->page[1].addr) & TARGET_PAGE_MASK; + + if (likely(!crosspage)) { + mmu_lookup1(env, &l->page[0], l->mmu_idx, type, ra); + + flags =3D l->page[0].flags; + if (unlikely(flags & (TLB_WATCHPOINT | TLB_NOTDIRTY))) { + mmu_watch_or_dirty(env, &l->page[0], type, ra); + } + if (unlikely(flags & TLB_BSWAP)) { + l->memop ^=3D MO_BSWAP; + } + } else { + /* Finish compute of page crossing. */ + int size0 =3D l->page[1].addr - addr; + l->page[1].size =3D l->page[0].size - size0; + l->page[0].size =3D size0; + + /* + * Lookup both pages, recognizing exceptions from either. If the + * second lookup potentially resized, refresh first CPUTLBEntryFul= l. + */ + mmu_lookup1(env, &l->page[0], l->mmu_idx, type, ra); + if (mmu_lookup1(env, &l->page[1], l->mmu_idx, type, ra)) { + uintptr_t index =3D tlb_index(env, l->mmu_idx, addr); + l->page[0].full =3D &env_tlb(env)->d[l->mmu_idx].fulltlb[index= ]; + } + + flags =3D l->page[0].flags | l->page[1].flags; + if (unlikely(flags & (TLB_WATCHPOINT | TLB_NOTDIRTY))) { + mmu_watch_or_dirty(env, &l->page[0], type, ra); + mmu_watch_or_dirty(env, &l->page[1], type, ra); + } + + /* + * Since target/sparc is the only user of TLB_BSWAP, and all + * Sparc accesses are aligned, any treatment across two pages + * would be arbitrary. Refuse it until there's a use. + */ + tcg_debug_assert((flags & TLB_BSWAP) =3D=3D 0); + } + + return crosspage; +} + /* * Probe for an atomic operation. Do not allow unaligned operations, * or io operations to proceed. Return the host address. @@ -1890,113 +2063,6 @@ load_memop(const void *haddr, MemOp op) } } =20 -static inline uint64_t QEMU_ALWAYS_INLINE -load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi, - uintptr_t retaddr, MemOp op, MMUAccessType access_type, - FullLoadHelper *full_load) -{ - const unsigned a_bits =3D get_alignment_bits(get_memop(oi)); - const size_t size =3D memop_size(op); - uintptr_t mmu_idx =3D get_mmuidx(oi); - uintptr_t index; - CPUTLBEntry *entry; - target_ulong tlb_addr; - void *haddr; - uint64_t res; - - tcg_debug_assert(mmu_idx < NB_MMU_MODES); - - /* Handle CPU specific unaligned behaviour */ - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(env_cpu(env), addr, access_type, - mmu_idx, retaddr); - } - - index =3D tlb_index(env, mmu_idx, addr); - entry =3D tlb_entry(env, mmu_idx, addr); - tlb_addr =3D tlb_read_idx(entry, access_type); - - /* If the TLB entry is for a different page, reload and try again. */ - if (!tlb_hit(tlb_addr, addr)) { - if (!victim_tlb_hit(env, mmu_idx, index, access_type, - addr & TARGET_PAGE_MASK)) { - tlb_fill(env_cpu(env), addr, size, - access_type, mmu_idx, retaddr); - index =3D tlb_index(env, mmu_idx, addr); - entry =3D tlb_entry(env, mmu_idx, addr); - } - tlb_addr =3D tlb_read_idx(entry, access_type); - tlb_addr &=3D ~TLB_INVALID_MASK; - } - - /* Handle anything that isn't just a straight memory access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - CPUTLBEntryFull *full; - bool need_swap; - - /* For anything that is unaligned, recurse through full_load. */ - if ((addr & (size - 1)) !=3D 0) { - goto do_unaligned_access; - } - - full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; - - /* Handle watchpoints. */ - if (unlikely(tlb_addr & TLB_WATCHPOINT)) { - /* On watchpoint hit, this will longjmp out. */ - cpu_check_watchpoint(env_cpu(env), addr, size, - full->attrs, BP_MEM_READ, retaddr); - } - - need_swap =3D size > 1 && (tlb_addr & TLB_BSWAP); - - /* Handle I/O access. */ - if (likely(tlb_addr & TLB_MMIO)) { - return io_readx(env, full, mmu_idx, addr, retaddr, - access_type, op ^ (need_swap * MO_BSWAP)); - } - - haddr =3D (void *)((uintptr_t)addr + entry->addend); - - /* - * Keep these two load_memop separate to ensure that the compiler - * is able to fold the entire function to a single instruction. - * There is a build-time assert inside to remind you of this. ;-) - */ - if (unlikely(need_swap)) { - return load_memop(haddr, op ^ MO_BSWAP); - } - return load_memop(haddr, op); - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (size > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + size - 1 - >=3D TARGET_PAGE_SIZE)) { - target_ulong addr1, addr2; - uint64_t r1, r2; - unsigned shift; - do_unaligned_access: - addr1 =3D addr & ~((target_ulong)size - 1); - addr2 =3D addr1 + size; - r1 =3D full_load(env, addr1, oi, retaddr); - r2 =3D full_load(env, addr2, oi, retaddr); - shift =3D (addr & (size - 1)) * 8; - - if (memop_big_endian(op)) { - /* Big-endian combine. */ - res =3D (r1 << shift) | (r2 >> ((size * 8) - shift)); - } else { - /* Little-endian combine. */ - res =3D (r1 >> shift) | (r2 << ((size * 8) - shift)); - } - return res & MAKE_64BIT_MASK(0, size * 8); - } - - haddr =3D (void *)((uintptr_t)addr + entry->addend); - return load_memop(haddr, op); -} - /* * For the benefit of TCG generated code, we want to avoid the * complication of ABI-specific return type promotion and always @@ -2007,90 +2073,250 @@ load_helper(CPUArchState *env, target_ulong addr, = MemOpIdx oi, * We don't bother with this widened value for SOFTMMU_CODE_ACCESS. */ =20 -static uint64_t full_ldub_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) +/** + * do_ld_mmio_beN: + * @env: cpu context + * @p: translation parameters + * @ret_be: accumulated data + * @mmu_idx: virtual address context + * @ra: return address into tcg generated code, or 0 + * + * Load @p->size bytes from @p->addr, which is memory-mapped i/o. + * The bytes are concatenated in big-endian order with @ret_be. + */ +static uint64_t do_ld_mmio_beN(CPUArchState *env, MMULookupPageData *p, + uint64_t ret_be, int mmu_idx, + MMUAccessType type, uintptr_t ra) { - validate_memop(oi, MO_UB); - return load_helper(env, addr, oi, retaddr, MO_UB, MMU_DATA_LOAD, - full_ldub_mmu); + CPUTLBEntryFull *full =3D p->full; + target_ulong addr =3D p->addr; + int i, size =3D p->size; + + QEMU_IOTHREAD_LOCK_GUARD(); + for (i =3D 0; i < size; i++) { + uint8_t x =3D io_readx(env, full, mmu_idx, addr + i, ra, type, MO_= UB); + ret_be =3D (ret_be << 8) | x; + } + return ret_be; +} + +/** + * do_ld_bytes_beN + * @p: translation parameters + * @ret_be: accumulated data + * + * Load @p->size bytes from @p->haddr, which is RAM. + * The bytes to concatenated in big-endian order with @ret_be. + */ +static uint64_t do_ld_bytes_beN(MMULookupPageData *p, uint64_t ret_be) +{ + uint8_t *haddr =3D p->haddr; + int i, size =3D p->size; + + for (i =3D 0; i < size; i++) { + ret_be =3D (ret_be << 8) | haddr[i]; + } + return ret_be; +} + +/* + * Wrapper for the above. + */ +static uint64_t do_ld_beN(CPUArchState *env, MMULookupPageData *p, + uint64_t ret_be, int mmu_idx, + MMUAccessType type, uintptr_t ra) +{ + if (unlikely(p->flags & TLB_MMIO)) { + return do_ld_mmio_beN(env, p, ret_be, mmu_idx, type, ra); + } else { + return do_ld_bytes_beN(p, ret_be); + } +} + +static uint8_t do_ld_1(CPUArchState *env, MMULookupPageData *p, int mmu_id= x, + MMUAccessType type, uintptr_t ra) +{ + if (unlikely(p->flags & TLB_MMIO)) { + return io_readx(env, p->full, mmu_idx, p->addr, ra, type, MO_UB); + } else { + return *(uint8_t *)p->haddr; + } +} + +static uint16_t do_ld_2(CPUArchState *env, MMULookupPageData *p, int mmu_i= dx, + MMUAccessType type, MemOp memop, uintptr_t ra) +{ + uint64_t ret; + + if (unlikely(p->flags & TLB_MMIO)) { + return io_readx(env, p->full, mmu_idx, p->addr, ra, type, memop); + } + + /* Perform the load host endian, then swap if necessary. */ + ret =3D load_memop(p->haddr, MO_UW); + if (memop & MO_BSWAP) { + ret =3D bswap16(ret); + } + return ret; +} + +static uint32_t do_ld_4(CPUArchState *env, MMULookupPageData *p, int mmu_i= dx, + MMUAccessType type, MemOp memop, uintptr_t ra) +{ + uint32_t ret; + + if (unlikely(p->flags & TLB_MMIO)) { + return io_readx(env, p->full, mmu_idx, p->addr, ra, type, memop); + } + + /* Perform the load host endian. */ + ret =3D load_memop(p->haddr, MO_UL); + if (memop & MO_BSWAP) { + ret =3D bswap32(ret); + } + return ret; +} + +static uint64_t do_ld_8(CPUArchState *env, MMULookupPageData *p, int mmu_i= dx, + MMUAccessType type, MemOp memop, uintptr_t ra) +{ + uint64_t ret; + + if (unlikely(p->flags & TLB_MMIO)) { + return io_readx(env, p->full, mmu_idx, p->addr, ra, type, memop); + } + + /* Perform the load host endian. */ + ret =3D load_memop(p->haddr, MO_UQ); + if (memop & MO_BSWAP) { + ret =3D bswap64(ret); + } + return ret; +} + +static uint8_t do_ld1_mmu(CPUArchState *env, target_ulong addr, MemOpIdx o= i, + uintptr_t ra, MMUAccessType access_type) +{ + MMULookupLocals l; + bool crosspage; + + crosspage =3D mmu_lookup(env, addr, oi, ra, access_type, &l); + tcg_debug_assert(!crosspage); + + return do_ld_1(env, &l.page[0], l.mmu_idx, access_type, ra); } =20 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { - return full_ldub_mmu(env, addr, oi, retaddr); + validate_memop(oi, MO_UB); + return do_ld1_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); } =20 -static uint64_t full_le_lduw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) +static uint16_t do_ld2_mmu(CPUArchState *env, target_ulong addr, MemOpIdx = oi, + uintptr_t ra, MMUAccessType access_type) { - validate_memop(oi, MO_LEUW); - return load_helper(env, addr, oi, retaddr, MO_LEUW, MMU_DATA_LOAD, - full_le_lduw_mmu); + MMULookupLocals l; + bool crosspage; + uint16_t ret; + uint8_t a, b; + + crosspage =3D mmu_lookup(env, addr, oi, ra, access_type, &l); + if (likely(!crosspage)) { + return do_ld_2(env, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); + } + + a =3D do_ld_1(env, &l.page[0], l.mmu_idx, access_type, ra); + b =3D do_ld_1(env, &l.page[1], l.mmu_idx, access_type, ra); + + if ((l.memop & MO_BSWAP) =3D=3D MO_LE) { + ret =3D a | (b << 8); + } else { + ret =3D b | (a << 8); + } + return ret; } =20 tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { - return full_le_lduw_mmu(env, addr, oi, retaddr); -} - -static uint64_t full_be_lduw_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) -{ - validate_memop(oi, MO_BEUW); - return load_helper(env, addr, oi, retaddr, MO_BEUW, MMU_DATA_LOAD, - full_be_lduw_mmu); + validate_memop(oi, MO_LEUW); + return do_ld2_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); } =20 tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { - return full_be_lduw_mmu(env, addr, oi, retaddr); + validate_memop(oi, MO_BEUW); + return do_ld2_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); } =20 -static uint64_t full_le_ldul_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) +static uint32_t do_ld4_mmu(CPUArchState *env, target_ulong addr, MemOpIdx = oi, + uintptr_t ra, MMUAccessType access_type) { - validate_memop(oi, MO_LEUL); - return load_helper(env, addr, oi, retaddr, MO_LEUL, MMU_DATA_LOAD, - full_le_ldul_mmu); + MMULookupLocals l; + bool crosspage; + uint32_t ret; + + crosspage =3D mmu_lookup(env, addr, oi, ra, access_type, &l); + if (likely(!crosspage)) { + return do_ld_4(env, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); + } + + ret =3D do_ld_beN(env, &l.page[0], 0, l.mmu_idx, access_type, ra); + ret =3D do_ld_beN(env, &l.page[1], ret, l.mmu_idx, access_type, ra); + if ((l.memop & MO_BSWAP) =3D=3D MO_LE) { + ret =3D bswap32(ret); + } + return ret; } =20 tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { - return full_le_ldul_mmu(env, addr, oi, retaddr); -} - -static uint64_t full_be_ldul_mmu(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) -{ - validate_memop(oi, MO_BEUL); - return load_helper(env, addr, oi, retaddr, MO_BEUL, MMU_DATA_LOAD, - full_be_ldul_mmu); + validate_memop(oi, MO_LEUL); + return do_ld4_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); } =20 tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { - return full_be_ldul_mmu(env, addr, oi, retaddr); + validate_memop(oi, MO_BEUL); + return do_ld4_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); +} + +static uint64_t do_ld8_mmu(CPUArchState *env, target_ulong addr, MemOpIdx = oi, + uintptr_t ra, MMUAccessType access_type) +{ + MMULookupLocals l; + bool crosspage; + uint64_t ret; + + crosspage =3D mmu_lookup(env, addr, oi, ra, access_type, &l); + if (likely(!crosspage)) { + return do_ld_8(env, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); + } + + ret =3D do_ld_beN(env, &l.page[0], 0, l.mmu_idx, access_type, ra); + ret =3D do_ld_beN(env, &l.page[1], ret, l.mmu_idx, access_type, ra); + if ((l.memop & MO_BSWAP) =3D=3D MO_LE) { + ret =3D bswap64(ret); + } + return ret; } =20 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { validate_memop(oi, MO_LEUQ); - return load_helper(env, addr, oi, retaddr, MO_LEUQ, MMU_DATA_LOAD, - helper_le_ldq_mmu); + return do_ld8_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); } =20 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr) { validate_memop(oi, MO_BEUQ); - return load_helper(env, addr, oi, retaddr, MO_BEUQ, MMU_DATA_LOAD, - helper_be_ldq_mmu); + return do_ld8_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); } =20 /* @@ -2133,56 +2359,85 @@ tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *e= nv, target_ulong addr, * Load helpers for cpu_ldst.h. */ =20 -static inline uint64_t cpu_load_helper(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t retaddr, - FullLoadHelper *full_load) +static void plugin_load_cb(CPUArchState *env, abi_ptr addr, MemOpIdx oi) { - uint64_t ret; - - ret =3D full_load(env, addr, oi, retaddr); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return ret; } =20 uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_= t ra) { - return cpu_load_helper(env, addr, oi, ra, full_ldub_mmu); + uint8_t ret; + + validate_memop(oi, MO_UB); + ret =3D do_ld1_mmu(env, addr, oi, ra, MMU_DATA_LOAD); + plugin_load_cb(env, addr, oi); + return ret; } =20 uint16_t cpu_ldw_be_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - return cpu_load_helper(env, addr, oi, ra, full_be_lduw_mmu); + uint16_t ret; + + validate_memop(oi, MO_BEUW); + ret =3D do_ld2_mmu(env, addr, oi, ra, MMU_DATA_LOAD); + plugin_load_cb(env, addr, oi); + return ret; } =20 uint32_t cpu_ldl_be_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - return cpu_load_helper(env, addr, oi, ra, full_be_ldul_mmu); + uint32_t ret; + + validate_memop(oi, MO_BEUL); + ret =3D do_ld4_mmu(env, addr, oi, ra, MMU_DATA_LOAD); + plugin_load_cb(env, addr, oi); + return ret; } =20 uint64_t cpu_ldq_be_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - return cpu_load_helper(env, addr, oi, ra, helper_be_ldq_mmu); + uint64_t ret; + + validate_memop(oi, MO_BEUQ); + ret =3D do_ld8_mmu(env, addr, oi, ra, MMU_DATA_LOAD); + plugin_load_cb(env, addr, oi); + return ret; } =20 uint16_t cpu_ldw_le_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - return cpu_load_helper(env, addr, oi, ra, full_le_lduw_mmu); + uint16_t ret; + + validate_memop(oi, MO_LEUW); + ret =3D do_ld2_mmu(env, addr, oi, ra, MMU_DATA_LOAD); + plugin_load_cb(env, addr, oi); + return ret; } =20 uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - return cpu_load_helper(env, addr, oi, ra, full_le_ldul_mmu); + uint32_t ret; + + validate_memop(oi, MO_LEUL); + ret =3D do_ld4_mmu(env, addr, oi, ra, MMU_DATA_LOAD); + plugin_load_cb(env, addr, oi); + return ret; } =20 uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - return cpu_load_helper(env, addr, oi, ra, helper_le_ldq_mmu); + uint64_t ret; + + validate_memop(oi, MO_LEUQ); + ret =3D do_ld8_mmu(env, addr, oi, ra, MMU_DATA_LOAD); + plugin_load_cb(env, addr, oi); + return ret; } =20 Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr addr, @@ -2684,102 +2939,50 @@ void cpu_st16_le_mmu(CPUArchState *env, abi_ptr ad= dr, Int128 val, =20 /* Code access functions. */ =20 -static uint64_t full_ldub_code(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) -{ - return load_helper(env, addr, oi, retaddr, MO_8, - MMU_INST_FETCH, full_ldub_code); -} - uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr) { MemOpIdx oi =3D make_memop_idx(MO_UB, cpu_mmu_index(env, true)); - return full_ldub_code(env, addr, oi, 0); -} - -static uint64_t full_lduw_code(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) -{ - return load_helper(env, addr, oi, retaddr, MO_TEUW, - MMU_INST_FETCH, full_lduw_code); + return do_ld1_mmu(env, addr, oi, 0, MMU_INST_FETCH); } =20 uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr) { MemOpIdx oi =3D make_memop_idx(MO_TEUW, cpu_mmu_index(env, true)); - return full_lduw_code(env, addr, oi, 0); -} - -static uint64_t full_ldl_code(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) -{ - return load_helper(env, addr, oi, retaddr, MO_TEUL, - MMU_INST_FETCH, full_ldl_code); + return do_ld2_mmu(env, addr, oi, 0, MMU_INST_FETCH); } =20 uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr) { MemOpIdx oi =3D make_memop_idx(MO_TEUL, cpu_mmu_index(env, true)); - return full_ldl_code(env, addr, oi, 0); -} - -static uint64_t full_ldq_code(CPUArchState *env, target_ulong addr, - MemOpIdx oi, uintptr_t retaddr) -{ - return load_helper(env, addr, oi, retaddr, MO_TEUQ, - MMU_INST_FETCH, full_ldq_code); + return do_ld4_mmu(env, addr, oi, 0, MMU_INST_FETCH); } =20 uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr) { MemOpIdx oi =3D make_memop_idx(MO_TEUQ, cpu_mmu_index(env, true)); - return full_ldq_code(env, addr, oi, 0); + return do_ld8_mmu(env, addr, oi, 0, MMU_INST_FETCH); } =20 uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t retaddr) { - return full_ldub_code(env, addr, oi, retaddr); + return do_ld1_mmu(env, addr, oi, retaddr, MMU_INST_FETCH); } =20 uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t retaddr) { - MemOp mop =3D get_memop(oi); - int idx =3D get_mmuidx(oi); - uint16_t ret; - - ret =3D full_lduw_code(env, addr, make_memop_idx(MO_TEUW, idx), retadd= r); - if ((mop & MO_BSWAP) !=3D MO_TE) { - ret =3D bswap16(ret); - } - return ret; + return do_ld2_mmu(env, addr, oi, retaddr, MMU_INST_FETCH); } =20 uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t retaddr) { - MemOp mop =3D get_memop(oi); - int idx =3D get_mmuidx(oi); - uint32_t ret; - - ret =3D full_ldl_code(env, addr, make_memop_idx(MO_TEUL, idx), retaddr= ); - if ((mop & MO_BSWAP) !=3D MO_TE) { - ret =3D bswap32(ret); - } - return ret; + return do_ld4_mmu(env, addr, oi, retaddr, MMU_INST_FETCH); } =20 uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t retaddr) { - MemOp mop =3D get_memop(oi); - int idx =3D get_mmuidx(oi); - uint64_t ret; - - ret =3D full_ldq_code(env, addr, make_memop_idx(MO_TEUQ, idx), retaddr= ); - if ((mop & MO_BSWAP) !=3D MO_TE) { - ret =3D bswap64(ret); - } - return ret; + return do_ld8_mmu(env, addr, oi, retaddr, MMU_INST_FETCH); } --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792770; cv=none; d=zohomail.com; s=zohoarc; b=UAGWQ+dv7y0+W6xxhaBQmfKj/0Kt1HXKFvWZDVs9qHXPBvs8u04MXadsThW+kwuMw06K3liIVG6m7UTnq9YCXZzUYYsHaeb/HQiEKjAXH8yWf7vsh+A2b1Vd5Sic3a4B6l/NpTPYDFxqCLOjvRfJfkixS2liQTZKgt4I8XavPGM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792770; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AQDu2HKCDjr5A0VdwCNB/e4QqMUK+gBC/z+Nthp1m2c=; b=fuIFndmAAsM/v2OY2VgF6WDxgw+2n6Dy9WUlEbQwis67IUuifQVekk75G21d2PMgFVbmNQTqJ0mU8vvNvFDrxPrbSqUiyYFPmlX2xjHuFr7WCftPqAqBBxCVaE13GZMnDd5Oq5NH3cpU3A+/tFk193T+Ie9erL5/nvcETs7+fgc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792770799311.6999130586944; Thu, 11 May 2023 01:12:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Li-0007MQ-1M; Thu, 11 May 2023 04:08:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Lg-0007Lw-H1 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:28 -0400 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1Ld-0001yZ-R9 for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:28 -0400 Received: by mail-ed1-x531.google.com with SMTP id 4fb4d7f45d1cf-50bdd7b229cso15032033a12.0 for ; Thu, 11 May 2023 01:08:25 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b00959c6cb82basm3635225ejc.105.2023.05.11.01.08.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:08:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792504; x=1686384504; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AQDu2HKCDjr5A0VdwCNB/e4QqMUK+gBC/z+Nthp1m2c=; b=JJbnN6DxFldTJmY059JoVghqRBJHraK1atAdFekQseufGCs3oya/YUghEyqXIx1c7f sXn+CEg24twiep7w8HnXMHdH1TiWfjiVrFK0OiJLBUhCQWwCrsCFcPAd5OQbbGSrxmr3 9TviVNaO8CqgWmd1z5OWfZCmVipzoAwn930X7CbqAezh4ItleILtbc7xA/kAM4ww/pFZ QGiCwmVHmrBJFah7GnfGZlzk0ACe5Qw1SYmokG1qUXhW5gbQ8h45bRPflVvOH/SGHh6f Rp9gRJSc5oq9QnYfGfDZ0ROvHCGwSQAY9eRkC0abF7RPjlumHHW1SVpkkJuEpKeE1XGa 0Xfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792504; x=1686384504; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AQDu2HKCDjr5A0VdwCNB/e4QqMUK+gBC/z+Nthp1m2c=; b=hF3ecUeVB12nf+IutY+v+DQrf030/Cy2PvFO/R+DuiDfz5m6/03jeMArqvqCmT+iJc Un9PUsv4/bgNUVDmfmv6T83CYYhJ1LHsY6EVzzJEktZFR8yINC6NHUhLItCWz50T9Tsh 7fbJtX2ojW/WjsM/vF8xal9opCtM9ikfFsa0S9ZwL8G8YLDgwzbDQ31J+geBJLb9MN1h JYnde1Wv3APZpbhljeMFC1rTMppg9lqtCJk6EHCY3JpiuSGPw6ZoBTTE2YauNOYqJrKy liJ9VKJP+A99pMEL2o6hiD/jSRKLXMWiurxGiyaQmr+tjT0/VmefL2B9ZuC+4GN4gH/6 JmLg== X-Gm-Message-State: AC+VfDxrhuuO34Jg7bGusLWlSj9cwcZCjqhs4Redw0TwhX5EYxx7sb5K 5AjdxdvLNgmT4m09D7obT3BNt71P7eCSoyDha+mcIQ== X-Google-Smtp-Source: ACHHUZ5I8vGFU2ZcpxjXnyUBJDDlFVdtp/tOv601L/hEdvDDf1P65om1YsoG7NSJVGtdWXVhymXTsw== X-Received: by 2002:a17:907:97cb:b0:96a:4654:9a57 with SMTP id js11-20020a17090797cb00b0096a46549a57mr3623194ejc.54.1683792504336; Thu, 11 May 2023 01:08:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PULL 52/53] accel/tcg: Reorg system mode store helpers Date: Thu, 11 May 2023 09:04:49 +0100 Message-Id: <20230511080450.860923-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792772236100002 Content-Type: text/plain; charset="utf-8" Instead of trying to unify all operations on uint64_t, use mmu_lookup() to perform the basic tlb hit and resolution. Create individual functions to handle access by size. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 408 +++++++++++++++++++++------------------------ 1 file changed, 193 insertions(+), 215 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a85edd8246..617777055a 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2532,322 +2532,300 @@ store_memop(void *haddr, uint64_t val, MemOp op) } } =20 -static void full_stb_mmu(CPUArchState *env, target_ulong addr, uint64_t va= l, - MemOpIdx oi, uintptr_t retaddr); - -static void __attribute__((noinline)) -store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val, - uintptr_t retaddr, size_t size, uintptr_t mmu_idx, - bool big_endian) +/** + * do_st_mmio_leN: + * @env: cpu context + * @p: translation parameters + * @val_le: data to store + * @mmu_idx: virtual address context + * @ra: return address into tcg generated code, or 0 + * + * Store @p->size bytes at @p->addr, which is memory-mapped i/o. + * The bytes to store are extracted in little-endian order from @val_le; + * return the bytes of @val_le beyond @p->size that have not been stored. + */ +static uint64_t do_st_mmio_leN(CPUArchState *env, MMULookupPageData *p, + uint64_t val_le, int mmu_idx, uintptr_t ra) { - uintptr_t index, index2; - CPUTLBEntry *entry, *entry2; - target_ulong page1, page2, tlb_addr, tlb_addr2; - MemOpIdx oi; - size_t size2; - int i; + CPUTLBEntryFull *full =3D p->full; + target_ulong addr =3D p->addr; + int i, size =3D p->size; =20 - /* - * Ensure the second page is in the TLB. Note that the first page - * is already guaranteed to be filled, and that the second page - * cannot evict the first. An exception to this rule is PAGE_WRITE_INV - * handling: the first page could have evicted itself. - */ - page1 =3D addr & TARGET_PAGE_MASK; - page2 =3D (addr + size) & TARGET_PAGE_MASK; - size2 =3D (addr + size) & ~TARGET_PAGE_MASK; - index2 =3D tlb_index(env, mmu_idx, page2); - entry2 =3D tlb_entry(env, mmu_idx, page2); - - tlb_addr2 =3D tlb_addr_write(entry2); - if (page1 !=3D page2 && !tlb_hit_page(tlb_addr2, page2)) { - if (!victim_tlb_hit(env, mmu_idx, index2, MMU_DATA_STORE, page2)) { - tlb_fill(env_cpu(env), page2, size2, MMU_DATA_STORE, - mmu_idx, retaddr); - index2 =3D tlb_index(env, mmu_idx, page2); - entry2 =3D tlb_entry(env, mmu_idx, page2); - } - tlb_addr2 =3D tlb_addr_write(entry2); + QEMU_IOTHREAD_LOCK_GUARD(); + for (i =3D 0; i < size; i++, val_le >>=3D 8) { + io_writex(env, full, mmu_idx, val_le, addr + i, ra, MO_UB); } + return val_le; +} =20 - index =3D tlb_index(env, mmu_idx, addr); - entry =3D tlb_entry(env, mmu_idx, addr); - tlb_addr =3D tlb_addr_write(entry); +/** + * do_st_bytes_leN: + * @p: translation parameters + * @val_le: data to store + * + * Store @p->size bytes at @p->haddr, which is RAM. + * The bytes to store are extracted in little-endian order from @val_le; + * return the bytes of @val_le beyond @p->size that have not been stored. + */ +static uint64_t do_st_bytes_leN(MMULookupPageData *p, uint64_t val_le) +{ + uint8_t *haddr =3D p->haddr; + int i, size =3D p->size; =20 - /* - * Handle watchpoints. Since this may trap, all checks - * must happen before any store. - */ - if (unlikely(tlb_addr & TLB_WATCHPOINT)) { - cpu_check_watchpoint(env_cpu(env), addr, size - size2, - env_tlb(env)->d[mmu_idx].fulltlb[index].attrs, - BP_MEM_WRITE, retaddr); - } - if (unlikely(tlb_addr2 & TLB_WATCHPOINT)) { - cpu_check_watchpoint(env_cpu(env), page2, size2, - env_tlb(env)->d[mmu_idx].fulltlb[index2].attr= s, - BP_MEM_WRITE, retaddr); + for (i =3D 0; i < size; i++, val_le >>=3D 8) { + haddr[i] =3D val_le; } + return val_le; +} =20 - /* - * XXX: not efficient, but simple. - * This loop must go in the forward direction to avoid issues - * with self-modifying code in Windows 64-bit. - */ - oi =3D make_memop_idx(MO_UB, mmu_idx); - if (big_endian) { - for (i =3D 0; i < size; ++i) { - /* Big-endian extract. */ - uint8_t val8 =3D val >> (((size - 1) * 8) - (i * 8)); - full_stb_mmu(env, addr + i, val8, oi, retaddr); - } +/* + * Wrapper for the above. + */ +static uint64_t do_st_leN(CPUArchState *env, MMULookupPageData *p, + uint64_t val_le, int mmu_idx, uintptr_t ra) +{ + if (unlikely(p->flags & TLB_MMIO)) { + return do_st_mmio_leN(env, p, val_le, mmu_idx, ra); + } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { + return val_le >> (p->size * 8); } else { - for (i =3D 0; i < size; ++i) { - /* Little-endian extract. */ - uint8_t val8 =3D val >> (i * 8); - full_stb_mmu(env, addr + i, val8, oi, retaddr); - } + return do_st_bytes_leN(p, val_le); } } =20 -static inline void QEMU_ALWAYS_INLINE -store_helper(CPUArchState *env, target_ulong addr, uint64_t val, - MemOpIdx oi, uintptr_t retaddr, MemOp op) +static void do_st_1(CPUArchState *env, MMULookupPageData *p, uint8_t val, + int mmu_idx, uintptr_t ra) { - const unsigned a_bits =3D get_alignment_bits(get_memop(oi)); - const size_t size =3D memop_size(op); - uintptr_t mmu_idx =3D get_mmuidx(oi); - uintptr_t index; - CPUTLBEntry *entry; - target_ulong tlb_addr; - void *haddr; - - tcg_debug_assert(mmu_idx < NB_MMU_MODES); - - /* Handle CPU specific unaligned behaviour */ - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, - mmu_idx, retaddr); + if (unlikely(p->flags & TLB_MMIO)) { + io_writex(env, p->full, mmu_idx, val, p->addr, ra, MO_UB); + } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { + /* nothing */ + } else { + *(uint8_t *)p->haddr =3D val; } - - index =3D tlb_index(env, mmu_idx, addr); - entry =3D tlb_entry(env, mmu_idx, addr); - tlb_addr =3D tlb_addr_write(entry); - - /* If the TLB entry is for a different page, reload and try again. */ - if (!tlb_hit(tlb_addr, addr)) { - if (!victim_tlb_hit(env, mmu_idx, index, MMU_DATA_STORE, - addr & TARGET_PAGE_MASK)) { - tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE, - mmu_idx, retaddr); - index =3D tlb_index(env, mmu_idx, addr); - entry =3D tlb_entry(env, mmu_idx, addr); - } - tlb_addr =3D tlb_addr_write(entry) & ~TLB_INVALID_MASK; - } - - /* Handle anything that isn't just a straight memory access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - CPUTLBEntryFull *full; - bool need_swap; - - /* For anything that is unaligned, recurse through byte stores. */ - if ((addr & (size - 1)) !=3D 0) { - goto do_unaligned_access; - } - - full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; - - /* Handle watchpoints. */ - if (unlikely(tlb_addr & TLB_WATCHPOINT)) { - /* On watchpoint hit, this will longjmp out. */ - cpu_check_watchpoint(env_cpu(env), addr, size, - full->attrs, BP_MEM_WRITE, retaddr); - } - - need_swap =3D size > 1 && (tlb_addr & TLB_BSWAP); - - /* Handle I/O access. */ - if (tlb_addr & TLB_MMIO) { - io_writex(env, full, mmu_idx, val, addr, retaddr, - op ^ (need_swap * MO_BSWAP)); - return; - } - - /* Ignore writes to ROM. */ - if (unlikely(tlb_addr & TLB_DISCARD_WRITE)) { - return; - } - - /* Handle clean RAM pages. */ - if (tlb_addr & TLB_NOTDIRTY) { - notdirty_write(env_cpu(env), addr, size, full, retaddr); - } - - haddr =3D (void *)((uintptr_t)addr + entry->addend); - - /* - * Keep these two store_memop separate to ensure that the compiler - * is able to fold the entire function to a single instruction. - * There is a build-time assert inside to remind you of this. ;-) - */ - if (unlikely(need_swap)) { - store_memop(haddr, val, op ^ MO_BSWAP); - } else { - store_memop(haddr, val, op); - } - return; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (size > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + size - 1 - >=3D TARGET_PAGE_SIZE)) { - do_unaligned_access: - store_helper_unaligned(env, addr, val, retaddr, size, - mmu_idx, memop_big_endian(op)); - return; - } - - haddr =3D (void *)((uintptr_t)addr + entry->addend); - store_memop(haddr, val, op); } =20 -static void __attribute__((noinline)) -full_stb_mmu(CPUArchState *env, target_ulong addr, uint64_t val, - MemOpIdx oi, uintptr_t retaddr) +static void do_st_2(CPUArchState *env, MMULookupPageData *p, uint16_t val, + int mmu_idx, MemOp memop, uintptr_t ra) { - validate_memop(oi, MO_UB); - store_helper(env, addr, val, oi, retaddr, MO_UB); + if (unlikely(p->flags & TLB_MMIO)) { + io_writex(env, p->full, mmu_idx, val, p->addr, ra, memop); + } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { + /* nothing */ + } else { + /* Swap to host endian if necessary, then store. */ + if (memop & MO_BSWAP) { + val =3D bswap16(val); + } + store_memop(p->haddr, val, MO_UW); + } +} + +static void do_st_4(CPUArchState *env, MMULookupPageData *p, uint32_t val, + int mmu_idx, MemOp memop, uintptr_t ra) +{ + if (unlikely(p->flags & TLB_MMIO)) { + io_writex(env, p->full, mmu_idx, val, p->addr, ra, memop); + } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { + /* nothing */ + } else { + /* Swap to host endian if necessary, then store. */ + if (memop & MO_BSWAP) { + val =3D bswap32(val); + } + store_memop(p->haddr, val, MO_UL); + } +} + +static void do_st_8(CPUArchState *env, MMULookupPageData *p, uint64_t val, + int mmu_idx, MemOp memop, uintptr_t ra) +{ + if (unlikely(p->flags & TLB_MMIO)) { + io_writex(env, p->full, mmu_idx, val, p->addr, ra, memop); + } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { + /* nothing */ + } else { + /* Swap to host endian if necessary, then store. */ + if (memop & MO_BSWAP) { + val =3D bswap64(val); + } + store_memop(p->haddr, val, MO_UQ); + } } =20 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint32_t val, - MemOpIdx oi, uintptr_t retaddr) + MemOpIdx oi, uintptr_t ra) { - full_stb_mmu(env, addr, val, oi, retaddr); + MMULookupLocals l; + bool crosspage; + + validate_memop(oi, MO_UB); + crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); + tcg_debug_assert(!crosspage); + + do_st_1(env, &l.page[0], val, l.mmu_idx, ra); } =20 -static void full_le_stw_mmu(CPUArchState *env, target_ulong addr, uint64_t= val, - MemOpIdx oi, uintptr_t retaddr) +static void do_st2_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + MemOpIdx oi, uintptr_t ra) { - validate_memop(oi, MO_LEUW); - store_helper(env, addr, val, oi, retaddr, MO_LEUW); + MMULookupLocals l; + bool crosspage; + uint8_t a, b; + + crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); + if (likely(!crosspage)) { + do_st_2(env, &l.page[0], val, l.mmu_idx, l.memop, ra); + return; + } + + if ((l.memop & MO_BSWAP) =3D=3D MO_LE) { + a =3D val, b =3D val >> 8; + } else { + b =3D val, a =3D val >> 8; + } + do_st_1(env, &l.page[0], a, l.mmu_idx, ra); + do_st_1(env, &l.page[1], b, l.mmu_idx, ra); } =20 void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { - full_le_stw_mmu(env, addr, val, oi, retaddr); -} - -static void full_be_stw_mmu(CPUArchState *env, target_ulong addr, uint64_t= val, - MemOpIdx oi, uintptr_t retaddr) -{ - validate_memop(oi, MO_BEUW); - store_helper(env, addr, val, oi, retaddr, MO_BEUW); + validate_memop(oi, MO_LEUW); + do_st2_mmu(env, addr, val, oi, retaddr); } =20 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { - full_be_stw_mmu(env, addr, val, oi, retaddr); + validate_memop(oi, MO_BEUW); + do_st2_mmu(env, addr, val, oi, retaddr); } =20 -static void full_le_stl_mmu(CPUArchState *env, target_ulong addr, uint64_t= val, - MemOpIdx oi, uintptr_t retaddr) +static void do_st4_mmu(CPUArchState *env, target_ulong addr, uint32_t val, + MemOpIdx oi, uintptr_t ra) { - validate_memop(oi, MO_LEUL); - store_helper(env, addr, val, oi, retaddr, MO_LEUL); + MMULookupLocals l; + bool crosspage; + + crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); + if (likely(!crosspage)) { + do_st_4(env, &l.page[0], val, l.mmu_idx, l.memop, ra); + return; + } + + /* Swap to little endian for simplicity, then store by bytes. */ + if ((l.memop & MO_BSWAP) !=3D MO_LE) { + val =3D bswap32(val); + } + val =3D do_st_leN(env, &l.page[0], val, l.mmu_idx, ra); + (void) do_st_leN(env, &l.page[1], val, l.mmu_idx, ra); } =20 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { - full_le_stl_mmu(env, addr, val, oi, retaddr); -} - -static void full_be_stl_mmu(CPUArchState *env, target_ulong addr, uint64_t= val, - MemOpIdx oi, uintptr_t retaddr) -{ - validate_memop(oi, MO_BEUL); - store_helper(env, addr, val, oi, retaddr, MO_BEUL); + validate_memop(oi, MO_LEUL); + do_st4_mmu(env, addr, val, oi, retaddr); } =20 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { - full_be_stl_mmu(env, addr, val, oi, retaddr); + validate_memop(oi, MO_BEUL); + do_st4_mmu(env, addr, val, oi, retaddr); +} + +static void do_st8_mmu(CPUArchState *env, target_ulong addr, uint64_t val, + MemOpIdx oi, uintptr_t ra) +{ + MMULookupLocals l; + bool crosspage; + + crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); + if (likely(!crosspage)) { + do_st_8(env, &l.page[0], val, l.mmu_idx, l.memop, ra); + return; + } + + /* Swap to little endian for simplicity, then store by bytes. */ + if ((l.memop & MO_BSWAP) !=3D MO_LE) { + val =3D bswap64(val); + } + val =3D do_st_leN(env, &l.page[0], val, l.mmu_idx, ra); + (void) do_st_leN(env, &l.page[1], val, l.mmu_idx, ra); } =20 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr) { validate_memop(oi, MO_LEUQ); - store_helper(env, addr, val, oi, retaddr, MO_LEUQ); + do_st8_mmu(env, addr, val, oi, retaddr); } =20 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr) { validate_memop(oi, MO_BEUQ); - store_helper(env, addr, val, oi, retaddr, MO_BEUQ); + do_st8_mmu(env, addr, val, oi, retaddr); } =20 /* * Store Helpers for cpu_ldst.h */ =20 -typedef void FullStoreHelper(CPUArchState *env, target_ulong addr, - uint64_t val, MemOpIdx oi, uintptr_t retaddr); - -static inline void cpu_store_helper(CPUArchState *env, target_ulong addr, - uint64_t val, MemOpIdx oi, uintptr_t r= a, - FullStoreHelper *full_store) +static void plugin_store_cb(CPUArchState *env, abi_ptr addr, MemOpIdx oi) { - full_store(env, addr, val, oi, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 void cpu_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, oi, retaddr, full_stb_mmu); + helper_ret_stb_mmu(env, addr, val, oi, retaddr); + plugin_store_cb(env, addr, oi); } =20 void cpu_stw_be_mmu(CPUArchState *env, target_ulong addr, uint16_t val, MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, oi, retaddr, full_be_stw_mmu); + helper_be_stw_mmu(env, addr, val, oi, retaddr); + plugin_store_cb(env, addr, oi); } =20 void cpu_stl_be_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, oi, retaddr, full_be_stl_mmu); + helper_be_stl_mmu(env, addr, val, oi, retaddr); + plugin_store_cb(env, addr, oi); } =20 void cpu_stq_be_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, oi, retaddr, helper_be_stq_mmu); + helper_be_stq_mmu(env, addr, val, oi, retaddr); + plugin_store_cb(env, addr, oi); } =20 void cpu_stw_le_mmu(CPUArchState *env, target_ulong addr, uint16_t val, MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, oi, retaddr, full_le_stw_mmu); + helper_le_stw_mmu(env, addr, val, oi, retaddr); + plugin_store_cb(env, addr, oi); } =20 void cpu_stl_le_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, oi, retaddr, full_le_stl_mmu); + helper_le_stl_mmu(env, addr, val, oi, retaddr); + plugin_store_cb(env, addr, oi); } =20 void cpu_stq_le_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr) { - cpu_store_helper(env, addr, val, oi, retaddr, helper_le_stq_mmu); + helper_le_stq_mmu(env, addr, val, oi, retaddr); + plugin_store_cb(env, addr, oi); } =20 void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr, Int128 val, --=20 2.34.1 From nobody Sun May 19 00:47:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683792846; cv=none; d=zohomail.com; s=zohoarc; b=C8pqMAidiW9chGhOVPaInRMsN3yCKxPwl9AMexJzqoIVa2mJq17EyD1fHS9kHRAcXpA7WkX1m4Kakwbi2aZYgLlcLcBsCSpex1S21CQ7FNLP6zjmbiOCK5JNykIYGPjhSZpJV2he2NJxQ6DXe7Z5PS8w4d5pk3SHDWTZdhy+CbQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683792846; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4wNX1Pq98E0/bohWeUMs/8eeQ4iCUri+FDY9oiLUbo8=; b=GNEJi0cvWRjgUOPFQcjiQZT6vXDqM5N9BSwfVYAEtS5qfSKL8AWaZmk4WnDfmoAlwrcxaX0qLdv4MPqrv1PGvE35kIRjhfC2YtR2v2jHnM2AU5K3H3NDhwlerPw5zp41q65KS299BPSbqBTI/YVv4UXWvoOHtqbwWdGr1AcJJjY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683792846725142.122402442517; Thu, 11 May 2023 01:14:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px1Li-0007MV-78; Thu, 11 May 2023 04:08:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px1Lh-0007MH-FR for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:29 -0400 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px1Le-0001yi-AC for qemu-devel@nongnu.org; Thu, 11 May 2023 04:08:29 -0400 Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-953343581a4so1285022166b.3 for ; Thu, 11 May 2023 01:08:25 -0700 (PDT) Received: from stoup.. ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b00959c6cb82basm3635225ejc.105.2023.05.11.01.08.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 01:08:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683792505; x=1686384505; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4wNX1Pq98E0/bohWeUMs/8eeQ4iCUri+FDY9oiLUbo8=; b=n5gHSO/MGNkQU9z1FOgLloTlC2CT7mvym2hHWTYNAQ392P0jtWKlWRncgkvWFuMKdR JP+P7qE1lbr+YzCoJoaVfWEXXROn79swQtu2H7jmi0o3PkUGXsEdntwcXi3ra4RPbN33 lacY7AvynSXqq1UbsTLO/V1e0BPnZ7bCfYxq0JMvcvPx5gotXIo3cZvAnB4xwQ5Utjhv +7vvOna6VenTm2igkhq2+ZcBzjChIZziic4bTP8rU8TYNkd2VLLU2cLa+V7NqiSHkvcH SpXMuDKUpYKhxx+Kw5yQsvKO1PHHPpJEPyepUgfFeLJe7FGEN7sxFEWpipk4VPwJQ+ci OYxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683792505; x=1686384505; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4wNX1Pq98E0/bohWeUMs/8eeQ4iCUri+FDY9oiLUbo8=; b=kSMyrqRRVDcoVtGkpa/2Kx26tm/3JQu5KhVL9MHaYZqpS3m0FySAeFA8zJVfPk+Wze S3ELN3mwLLApclxc7+TIuN7uGYsPYBlarRub7cXvfGFnvvKQxeQdN8wKJRD/R5XYFIuV Qp1clBUiHjdM244S8UOxtyNDeXmH9Cy5RrTfEM2Y9RQKXgPs4FbEyH0saB2pjg3BsYY9 hkSYHUR6S0QS27hoatlUfo+o5xX8CUhEPo1EluArZGwYqItOaHm2Lg6BbOXgp6+if4kr d0nGImby5RpFbeTFaLua23kKYtNJBIJLVGP/OsDHyNak7VJk/7NE6cHDF5ANAl82Hw+b 3bHg== X-Gm-Message-State: AC+VfDyi7gIefWFHD4WKyUh/l9aq/NhlgJE2mjZe4ken1pAI/3gCvni1 PPF8qKrVpJeWzYWCVL5DAj9ZdmtREwGRyxZHFsSgww== X-Google-Smtp-Source: ACHHUZ75sKLaLp9rfLd6TWq3fCr0LXZwOyKqiBuoH6snL6wIuUb1yrnzF8YFp9sjd1BT4D8/6pJHEA== X-Received: by 2002:a17:907:2ce5:b0:969:9fd0:7ce7 with SMTP id hz5-20020a1709072ce500b009699fd07ce7mr11015893ejc.11.1683792504868; Thu, 11 May 2023 01:08:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Song Gao , Peter Maydell Subject: [PULL 53/53] target/loongarch: Do not include tcg-ldst.h Date: Thu, 11 May 2023 09:04:50 +0100 Message-Id: <20230511080450.860923-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org> References: <20230511080450.860923-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683792848505100005 Content-Type: text/plain; charset="utf-8" This header is supposed to be private to tcg and in fact does not need to be included here at all. Reviewed-by: Song Gao Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/loongarch/csr_helper.c | 1 - target/loongarch/iocsr_helper.c | 1 - 2 files changed, 2 deletions(-) diff --git a/target/loongarch/csr_helper.c b/target/loongarch/csr_helper.c index 7e02787895..6526367946 100644 --- a/target/loongarch/csr_helper.c +++ b/target/loongarch/csr_helper.c @@ -15,7 +15,6 @@ #include "exec/cpu_ldst.h" #include "hw/irq.h" #include "cpu-csr.h" -#include "tcg/tcg-ldst.h" =20 target_ulong helper_csrrd_pgd(CPULoongArchState *env) { diff --git a/target/loongarch/iocsr_helper.c b/target/loongarch/iocsr_helpe= r.c index 505853e17b..dda9845d6c 100644 --- a/target/loongarch/iocsr_helper.c +++ b/target/loongarch/iocsr_helper.c @@ -12,7 +12,6 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" -#include "tcg/tcg-ldst.h" =20 #define GET_MEMTXATTRS(cas) \ ((MemTxAttrs){.requester_id =3D env_cpu(cas)->cpu_index}) --=20 2.34.1