target/riscv/cpu.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
Zc* extensions (version 1.0) are ratified.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index db0875fb43..99ed9cb80e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1571,6 +1571,14 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
+ DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false),
+ DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false),
+ DEFINE_PROP_BOOL("zcd", RISCVCPU, cfg.ext_zcd, false),
+ DEFINE_PROP_BOOL("zce", RISCVCPU, cfg.ext_zce, false),
+ DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
+ DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
+ DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
+
/* Vendor-specific custom extensions */
DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
@@ -1588,14 +1596,6 @@ static Property riscv_cpu_extensions[] = {
/* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
- DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false),
- DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false),
- DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false),
- DEFINE_PROP_BOOL("x-zce", RISCVCPU, cfg.ext_zce, false),
- DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false),
- DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false),
- DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false),
-
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
--
2.25.1
On Wed, May 10, 2023 at 1:02 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > Zc* extensions (version 1.0) are ratified. > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index db0875fb43..99ed9cb80e 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1571,6 +1571,14 @@ static Property riscv_cpu_extensions[] = { > > DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), > > + DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false), > + DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false), > + DEFINE_PROP_BOOL("zcd", RISCVCPU, cfg.ext_zcd, false), > + DEFINE_PROP_BOOL("zce", RISCVCPU, cfg.ext_zce, false), > + DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false), > + DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false), > + DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false), > + > /* Vendor-specific custom extensions */ > DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), > DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), > @@ -1588,14 +1596,6 @@ static Property riscv_cpu_extensions[] = { > /* These are experimental so mark with 'x-' */ > DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), > > - DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), > - DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), > - DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false), > - DEFINE_PROP_BOOL("x-zce", RISCVCPU, cfg.ext_zce, false), > - DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false), > - DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false), > - DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), > - > /* ePMP 0.9.3 */ > DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), > DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), > -- > 2.25.1 > >
On 5/10/23 00:00, Weiwei Li wrote: > Zc* extensions (version 1.0) are ratified. > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > --- > target/riscv/cpu.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index db0875fb43..99ed9cb80e 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1571,6 +1571,14 @@ static Property riscv_cpu_extensions[] = { > > DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), > > + DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false), > + DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false), > + DEFINE_PROP_BOOL("zcd", RISCVCPU, cfg.ext_zcd, false), > + DEFINE_PROP_BOOL("zce", RISCVCPU, cfg.ext_zce, false), > + DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false), I see that zcf has a different ordering in isa_edata_arr[]. Is this intended? ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca), ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb), ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf), ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd), ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce), Not related to this patch per se. Just wondered if there's some reason for the different ordering between these arrays. Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > + DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false), > + DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false), > + > /* Vendor-specific custom extensions */ > DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), > DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), > @@ -1588,14 +1596,6 @@ static Property riscv_cpu_extensions[] = { > /* These are experimental so mark with 'x-' */ > DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), > > - DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), > - DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), > - DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false), > - DEFINE_PROP_BOOL("x-zce", RISCVCPU, cfg.ext_zce, false), > - DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false), > - DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false), > - DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), > - > /* ePMP 0.9.3 */ > DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), > DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
On 2023/5/10 20:23, Daniel Henrique Barboza wrote: > > > On 5/10/23 00:00, Weiwei Li wrote: >> Zc* extensions (version 1.0) are ratified. >> >> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> >> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> >> --- >> target/riscv/cpu.c | 16 ++++++++-------- >> 1 file changed, 8 insertions(+), 8 deletions(-) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index db0875fb43..99ed9cb80e 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -1571,6 +1571,14 @@ static Property riscv_cpu_extensions[] = { >> DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), >> + DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false), >> + DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false), >> + DEFINE_PROP_BOOL("zcd", RISCVCPU, cfg.ext_zcd, false), >> + DEFINE_PROP_BOOL("zce", RISCVCPU, cfg.ext_zce, false), >> + DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false), > > I see that zcf has a different ordering in isa_edata_arr[]. Is this > intended? Not really intended. But they are related to F and D extension, and F is before D insingle letter extensions. Regards, Weiwei Li > > ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca), > ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb), > ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf), > ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd), > ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce), > > > Not related to this patch per se. Just wondered if there's some reason > for the > different ordering between these arrays. > > > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > > >> + DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false), >> + DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false), >> + >> /* Vendor-specific custom extensions */ >> DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), >> DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), >> @@ -1588,14 +1596,6 @@ static Property riscv_cpu_extensions[] = { >> /* These are experimental so mark with 'x-' */ >> DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), >> - DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), >> - DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), >> - DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false), >> - DEFINE_PROP_BOOL("x-zce", RISCVCPU, cfg.ext_zce, false), >> - DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false), >> - DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false), >> - DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), >> - >> /* ePMP 0.9.3 */ >> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), >> DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
On 2023/5/10 11:00, Weiwei Li wrote: > Zc* extensions (version 1.0) are ratified. > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > --- > target/riscv/cpu.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index db0875fb43..99ed9cb80e 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1571,6 +1571,14 @@ static Property riscv_cpu_extensions[] = { > > DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), > > + DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false), > + DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false), > + DEFINE_PROP_BOOL("zcd", RISCVCPU, cfg.ext_zcd, false), > + DEFINE_PROP_BOOL("zce", RISCVCPU, cfg.ext_zce, false), > + DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false), > + DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false), > + DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false), > + Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Zhiwei > /* Vendor-specific custom extensions */ > DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), > DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), > @@ -1588,14 +1596,6 @@ static Property riscv_cpu_extensions[] = { > /* These are experimental so mark with 'x-' */ > DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), > > - DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), > - DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), > - DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false), > - DEFINE_PROP_BOOL("x-zce", RISCVCPU, cfg.ext_zce, false), > - DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false), > - DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false), > - DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), > - > /* ePMP 0.9.3 */ > DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), > DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
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