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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357758; x=1685949758; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=m5M2+WQKcwjiryfXWgTk/gb4/3Ri6GYlZz6tIioIz4E=; b=H580eDyNZdQANxFU9u3F92q+qXt+UCTuhVQgUcJMgI/TN9yWEiFDtZz79JURnBL06i gWdm1EcNkaDlg75x4sgv9pd6yWw+pUbhMT/61RQUUn6/9RPWQv9Ao9+hQ3siBAgHxNNW UxCp2s05REe7PLSiArmJ1Fq5+laK2QZL0aZpplTKTwEUxi9/PpIp/u4lxyAIXWhjVlKA AJj6jwWZ+MB1css9v7Noz72Zb96O6Bg0fdipE/L4CqhoCQjgCIzTQq78/I26E6E/Z4UA aBdWE3oYkMCEGW6RTg6ckWjtYgfrfDEdHjQwWfB+9znd26b4HMMgoVRGOa43+zzWf70g l/2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357758; x=1685949758; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m5M2+WQKcwjiryfXWgTk/gb4/3Ri6GYlZz6tIioIz4E=; b=ES7hOUo7aqeRpBQz3xNSsPw9tmtPcy2CDYyhpuseSv5+0fnUfLQ6/zv+sg1gZgUi85 19DhEhz/tr+PJhLWouw8ky6IUGnNBgq2wfb0P9IYd0kNZVIK0ZgBXZCOsCAdn2wk7bSU M5T1H4XkYFIRPVL+7Zus9oeD9T1Ub/UerplJ2MgbjhnEuBQ5efWl3XxC8KL7OQeGloDe MvWk9qOQEKyZAgNKfveLhKF/lausASn6StuolRdY7kjlzXJZ21pkDcDppMVeI+MigLC/ P3jPFRwGmNp5K50Klnxe3IfL8ngEiODSvFZcD2Omjm4tffmjqc3JQfVVBSFo+5Fo6hXR Pp4w== X-Gm-Message-State: AC+VfDwuqvN8eFLuV+wb63bMjvOhTXBPheRgWv/Bl/sD9W1WN1yj0IK2 xECnUSjbr9GQ2r1QXuELmHlUa+HbmnqyRNTtQJpysA== X-Google-Smtp-Source: ACHHUZ5aUxmhgpWASvqdHV+ZNasHrWlIETtOMdP2W6RZVYgDd6Fx+IeobYWKB8x/Yy3TAJmPCZ77jA== X-Received: by 2002:a5d:6081:0:b0:306:46ba:b2f1 with SMTP id w1-20020a5d6081000000b0030646bab2f1mr2958441wrt.50.1683357757852; Sat, 06 May 2023 00:22:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 01/30] tcg/i386: Introduce prepare_host_addr Date: Sat, 6 May 2023 08:22:06 +0100 Message-Id: <20230506072235.597467-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683358013901100003 Content-Type: text/plain; charset="utf-8" Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/i386/tcg-target.c.inc | 344 ++++++++++++++++---------------------- 1 file changed, 143 insertions(+), 201 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index aae698121a..237b154194 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1802,135 +1802,6 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_B= SWAP) + 1] =3D { [MO_BEUQ] =3D helper_be_stq_mmu, }; =20 -/* Perform the TLB load and compare. - - Inputs: - ADDRLO and ADDRHI contain the low and high part of the address. - - MEM_INDEX and S_BITS are the memory context and log2 size of the load. - - WHICH is the offset into the CPUTLBEntry structure of the slot to read. - This should be offsetof addr_read or addr_write. - - Outputs: - LABEL_PTRS is filled with 1 (32-bit addresses) or 2 (64-bit addresses) - positions of the displacements of forward jumps to the TLB miss case. - - Second argument register is loaded with the low part of the address. - In the TLB hit case, it has been adjusted as indicated by the TLB - and so is a host address. In the TLB miss case, it continues to - hold a guest address. - - First argument register is clobbered. */ - -static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg a= ddrhi, - int mem_index, MemOp opc, - tcg_insn_unit **label_ptr, int which) -{ - TCGType ttype =3D TCG_TYPE_I32; - TCGType tlbtype =3D TCG_TYPE_I32; - int trexw =3D 0, hrexw =3D 0, tlbrexw =3D 0; - unsigned a_bits =3D get_alignment_bits(opc); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_mask =3D (1 << a_bits) - 1; - unsigned s_mask =3D (1 << s_bits) - 1; - target_ulong tlb_mask; - - if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (TARGET_LONG_BITS =3D=3D 64) { - ttype =3D TCG_TYPE_I64; - trexw =3D P_REXW; - } - if (TCG_TYPE_PTR =3D=3D TCG_TYPE_I64) { - hrexw =3D P_REXW; - if (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32) { - tlbtype =3D TCG_TYPE_I64; - tlbrexw =3D P_REXW; - } - } - } - - tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo); - tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - - tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0, - TLB_MASK_TABLE_OFS(mem_index) + - offsetof(CPUTLBDescFast, mask)); - - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0, - TLB_MASK_TABLE_OFS(mem_index) + - offsetof(CPUTLBDescFast, table)); - - /* If the required alignment is at least as large as the access, simply - copy the address and mask. For lesser alignments, check that we do= n't - cross pages for the complete access. */ - if (a_bits >=3D s_bits) { - tcg_out_mov(s, ttype, TCG_REG_L1, addrlo); - } else { - tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1, - addrlo, s_mask - a_mask); - } - tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; - tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0); - - /* cmp 0(TCG_REG_L0), TCG_REG_L1 */ - tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, - TCG_REG_L1, TCG_REG_L0, which); - - /* Prepare for both the fast path add of the tlb addend, and the slow - path function argument setup. */ - tcg_out_mov(s, ttype, TCG_REG_L1, addrlo); - - /* jne slow_path */ - tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); - label_ptr[0] =3D s->code_ptr; - s->code_ptr +=3D 4; - - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - /* cmp 4(TCG_REG_L0), addrhi */ - tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, TCG_REG_L0, which + = 4); - - /* jne slow_path */ - tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); - label_ptr[1] =3D s->code_ptr; - s->code_ptr +=3D 4; - } - - /* TLB Hit. */ - - /* add addend(TCG_REG_L0), TCG_REG_L1 */ - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L1, TCG_REG_L0, - offsetof(CPUTLBEntry, addend)); -} - -/* - * Record the context of a call to the out of line helper code for the slo= w path - * for a load or store, so that we can later generate the correct helper c= ode - */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, - TCGType type, MemOpIdx oi, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addrhi, - tcg_insn_unit *raddr, - tcg_insn_unit **label_ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D type; - label->datalo_reg =3D datalo; - label->datahi_reg =3D datahi; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr[0]; - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - label->label_ptr[1] =3D label_ptr[1]; - } -} - /* * Generate code for the slow path for a load at the end of block */ @@ -2061,27 +1932,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) return true; } #else - -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrl= o, - TCGReg addrhi, unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *label; - - tcg_out_testi(s, addrlo, a_mask); - /* jne slow_path */ - tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); - - label =3D new_ldst_label(s); - label->is_ld =3D is_ld; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; - label->raddr =3D tcg_splitwx_to_rx(s->code_ptr + 4); - label->label_ptr[0] =3D s->code_ptr; - - s->code_ptr +=3D 4; -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { /* resolve label address */ @@ -2159,6 +2009,133 @@ static inline int setup_guest_base_seg(void) #endif /* setup_guest_base_seg */ #endif /* SOFTMMU */ =20 +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, bool is_ld) +{ + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned a_mask =3D (1 << a_bits) - 1; + +#ifdef CONFIG_SOFTMMU + int cmp_ofs =3D is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write); + TCGType ttype =3D TCG_TYPE_I32; + TCGType tlbtype =3D TCG_TYPE_I32; + int trexw =3D 0, hrexw =3D 0, tlbrexw =3D 0; + unsigned mem_index =3D get_mmuidx(oi); + unsigned s_bits =3D opc & MO_SIZE; + unsigned s_mask =3D (1 << s_bits) - 1; + target_ulong tlb_mask; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + if (TCG_TARGET_REG_BITS =3D=3D 64) { + if (TARGET_LONG_BITS =3D=3D 64) { + ttype =3D TCG_TYPE_I64; + trexw =3D P_REXW; + } + if (TCG_TYPE_PTR =3D=3D TCG_TYPE_I64) { + hrexw =3D P_REXW; + if (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32) { + tlbtype =3D TCG_TYPE_I64; + tlbrexw =3D P_REXW; + } + } + } + + tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo); + tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + + tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0, + TLB_MASK_TABLE_OFS(mem_index) + + offsetof(CPUTLBDescFast, mask)); + + tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0, + TLB_MASK_TABLE_OFS(mem_index) + + offsetof(CPUTLBDescFast, table)); + + /* If the required alignment is at least as large as the access, simply + copy the address and mask. For lesser alignments, check that we do= n't + cross pages for the complete access. */ + if (a_bits >=3D s_bits) { + tcg_out_mov(s, ttype, TCG_REG_L1, addrlo); + } else { + tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1, + addrlo, s_mask - a_mask); + } + tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; + tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0); + + /* cmp 0(TCG_REG_L0), TCG_REG_L1 */ + tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, + TCG_REG_L1, TCG_REG_L0, cmp_ofs); + + /* + * Prepare for both the fast path add of the tlb addend, and the slow + * path function argument setup. + */ + *h =3D (HostAddress) { + .base =3D TCG_REG_L1, + .index =3D -1 + }; + tcg_out_mov(s, ttype, h->base, addrlo); + + /* jne slow_path */ + tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); + ldst->label_ptr[0] =3D s->code_ptr; + s->code_ptr +=3D 4; + + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + /* cmp 4(TCG_REG_L0), addrhi */ + tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, TCG_REG_L0, cmp_ofs = + 4); + + /* jne slow_path */ + tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); + ldst->label_ptr[1] =3D s->code_ptr; + s->code_ptr +=3D 4; + } + + /* TLB Hit. */ + + /* add addend(TCG_REG_L0), TCG_REG_L1 */ + tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, h->base, TCG_REG_L0, + offsetof(CPUTLBEntry, addend)); +#else + if (a_bits) { + ldst =3D new_ldst_label(s); + + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + tcg_out_testi(s, addrlo, a_mask); + /* jne slow_path */ + tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); + ldst->label_ptr[0] =3D s->code_ptr; + s->code_ptr +=3D 4; + } + + *h =3D x86_guest_base; + h->base =3D addrlo; +#endif + + return ldst; +} + static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, HostAddress h, TCGType type, MemOp memo= p) { @@ -2258,35 +2235,18 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[2]; + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, true); + tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, get_memop(oi)); =20 - tcg_out_tlb_load(s, addrlo, addrhi, get_mmuidx(oi), opc, - label_ptr, offsetof(CPUTLBEntry, addr_read)); - - /* TLB Hit. */ - h.base =3D TCG_REG_L1; - h.index =3D -1; - h.ofs =3D 0; - h.seg =3D 0; - tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, opc); - - /* Record the current context of a load into ldst label */ - add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - - h =3D x86_guest_base; - h.base =3D addrlo; - tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, opc); -#endif } =20 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, @@ -2345,36 +2305,18 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[2]; + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, false); + tcg_out_qemu_st_direct(s, datalo, datahi, h, get_memop(oi)); =20 - tcg_out_tlb_load(s, addrlo, addrhi, get_mmuidx(oi), opc, - label_ptr, offsetof(CPUTLBEntry, addr_write)); - - /* TLB Hit. */ - h.base =3D TCG_REG_L1; - h.index =3D -1; - h.ofs =3D 0; - h.seg =3D 0; - tcg_out_qemu_st_direct(s, datalo, datahi, h, opc); - - /* Record the current context of a store into ldst label */ - add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - - h =3D x86_guest_base; - h.base =3D addrlo; - - tcg_out_qemu_st_direct(s, datalo, datahi, h, opc); -#endif } =20 static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683357881; cv=none; d=zohomail.com; s=zohoarc; b=PbbKl9MLCwJFyH17N/C4//JiImq4GXo/R+ZfG3L21Hl9w60PwYftagdeOBY5IGAK+pteGgvt5HVR+NqywalgAN7a5OqA9GW+qSqspXS20b28JPJECJIpA1duzFDVtopGdIUatFJELjyxRDPXRL2txTrYyjUe8u8AfD8XK7uw28s= ARC-Message-Signature: i=1; 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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357758; x=1685949758; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pkgYs/pHlLvep4nhbNf+04epzdD+G5zrqDmAy5YX7Hk=; b=xQTMA052TkRs05J0PuuQVEP3+FPs7wxhMPgVK9OkpkmWOZZhCbvQ56xoiKxMNCxmFo o7u2FaFx0MCKAbqxpWeF4SvzZMnyOq1JxKfGTYf2h5/qEjWRgds1/JkTKysPZDK3Yhls CsISa4QY7I2IAhwBANV9GJTLOZ2Glii+bsDXjbhfyu6+B3+G9n3guEr/5Y/KFn4+zgGz CAuHCsw0Q3A5k9hUZww75av17ZaIAfmZB2hbswCtI5cze8ADkv4sUJ4r6NOK+w27zSm+ G4t5VH+Z0xhbFxhKDREIwwGlTmiWlJsGnop+fsALAt1Sla+lN667t/zX2aop8JANMmAO a/oA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357758; x=1685949758; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pkgYs/pHlLvep4nhbNf+04epzdD+G5zrqDmAy5YX7Hk=; b=S2m211gs5dqCCRu98ykyPQy2SJ7ba+nEnoYm5r0I2szyR37lYGm9cXgHPMuFoGwZh3 tm1tbYXPT5RXqZFgZHJKYazxaLw7p6JNj5LmlKUuY9Aa47NOUa9nY2FNnL/osksq6pYB u8ZhiylE2p6eYDS36MOPe2G0WINl59D9w7UfM4vXHFLCkEvaGtjDoUtMGHWZePMZL6ru mEIIfN73r3+0HULi8Hj+E9bDGaPonSNfbRtaKAQ/XbOndYXWWTWa6GjQD+iswJCS+qK/ 0YXNJ//6t8xMLxGHeIpF1kB6pUHTLzui50GjYS2e4v8GjERSQzQUeCy3//I0yyVYHgix uiQg== X-Gm-Message-State: AC+VfDxA6zf6IQUXotVEkLim+Xa7IlRGGXKjv1JzUdVmyNMJC5GWbbtY 5MmWZKLWAEw3leDm3uLEl29TsxEfUgizhyaW6jVZjw== X-Google-Smtp-Source: ACHHUZ4p58Hg4KiwQRJBGeTc/UHy0xW/diElxva+USKuqRfgS+JTLzqnKTsshD76K35UfuiCv2uioA== X-Received: by 2002:a7b:c8c6:0:b0:3f1:979f:a736 with SMTP id f6-20020a7bc8c6000000b003f1979fa736mr2557796wml.34.1683357758623; Sat, 06 May 2023 00:22:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 02/30] tcg/i386: Use indexed addressing for softmmu fast path Date: Sat, 6 May 2023 08:22:07 +0100 Message-Id: <20230506072235.597467-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683357881960100001 Content-Type: text/plain; charset="utf-8" Since tcg_out_{ld,st}_helper_args, the slow path no longer requires the address argument to be set up by the tlb load sequence. Use a plain load for the addend and indexed addressing with the original input address register. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/i386/tcg-target.c.inc | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 237b154194..8752968af2 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1837,7 +1837,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) tcg_out_sti(s, TCG_TYPE_PTR, (uintptr_t)l->raddr, TCG_REG_ESP, ofs= ); } else { tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); - /* The second argument is already loaded with addrlo. */ + tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], + l->addrlo_reg); tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], oi); tcg_out_movi(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[3], (uintptr_t)l->raddr); @@ -1910,7 +1911,8 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, ofs); } else { tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); - /* The second argument is already loaded with addrlo. */ + tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], + l->addrlo_reg); tcg_out_mov(s, (s_bits =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), tcg_target_call_iarg_regs[2], l->datalo_reg); tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], oi); @@ -2083,16 +2085,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContex= t *s, HostAddress *h, tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, TCG_REG_L1, TCG_REG_L0, cmp_ofs); =20 - /* - * Prepare for both the fast path add of the tlb addend, and the slow - * path function argument setup. - */ - *h =3D (HostAddress) { - .base =3D TCG_REG_L1, - .index =3D -1 - }; - tcg_out_mov(s, ttype, h->base, addrlo); - /* jne slow_path */ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); ldst->label_ptr[0] =3D s->code_ptr; @@ -2109,10 +2101,13 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, } =20 /* TLB Hit. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0, + offsetof(CPUTLBEntry, addend)); =20 - /* add addend(TCG_REG_L0), TCG_REG_L1 */ - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, h->base, TCG_REG_L0, - offsetof(CPUTLBEntry, addend)); + *h =3D (HostAddress) { + .base =3D addrlo, + .index =3D TCG_REG_L0, + }; #else if (a_bits) { ldst =3D new_ldst_label(s); --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683357863; cv=none; d=zohomail.com; s=zohoarc; b=NClVIS/WTfaeOsn6yK1ZQNm1H2BxciSwWsMPmDk7hIJKyjC0RAzIouG6cjDwVFmgsvDx75DjSgp0/HfCGm6GFZTGJQyvf9KEcseTEGvdIdUyeFC08isokBBqakBd/L/19LBY9PFQL0w3BH0HIqMMqnvKIU/KksOnfs3tc4y2Lqo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683357863; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=E+QlOMba/aSBW632xLY397LQPEBGu7J2mpCgxpenFkM=; b=SDmC4IXY8AhcZM0Y3HlDpOXeZ9E7TbNPpPUi9d2DPkJlMu4oXpuMRVd4MprfizcKG7mfpFPL5Equ5JKzcV2S1yLxRIwETMFg/UMnTJNXHgb+gd664cruzTqvfo9wzC0JCuu1pSsGvTvFWnQ+9HqbHqr1BgDT0SwAETgfrfGCyEc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683357863542490.5320697128583; Sat, 6 May 2023 00:24:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCFl-0003zv-2u; Sat, 06 May 2023 03:22:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCFi-0003w8-AA for qemu-devel@nongnu.org; Sat, 06 May 2023 03:22:46 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFc-0004LI-UT for qemu-devel@nongnu.org; Sat, 06 May 2023 03:22:46 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-3f19a7f9424so26388815e9.2 for ; Sat, 06 May 2023 00:22:40 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357759; x=1685949759; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E+QlOMba/aSBW632xLY397LQPEBGu7J2mpCgxpenFkM=; b=pWhvCgUqcb7tNjpcPhdGMcKVoGgLPwFy9Vc1yNoZcKaEEbUNr7y0kS3GiK1R9UE0I9 Gxockawp7lTwJEHsb+nz5GBvF6zY5xIMEUWuZ8iFL09Bm2aCRyvrpQ5G93+2bq6L/+9L tHxwhNQurUZn/uuMoU3fcbnjPOFfuy8MsgD5tMU1cAu2DUNvA2JZ7Xt9TYliih+7uBGV NU/fhX21rOCAVWvncCArTHLO16oPozlaoIrlFSqIKf2mlDoG7rgF9mhJ+9MKxRVq9sy0 2Zi8TFn/uOiRCs9j/FwDYwEXFtCLe4AnFWLKOFf4KA8rahTOzGfvm+wfhuTSxWg8L9M3 qNjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357759; x=1685949759; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E+QlOMba/aSBW632xLY397LQPEBGu7J2mpCgxpenFkM=; b=WCGONEiGUm/Do5v9zDefSLedY1vcDjPw9Ik2NiNqJ6Q4iu4Fge3B9XArqy936q0vPT CAjmF284sAwgaj/eEt73QLL2bzfon2jD7kYbVx4RHC56+SxGLfkrsoL541uftfV58JTs aLwY0md9mkrs6+9u1WgmLe8c/yyHFlTiGaw5+qyxRouxzRZjbwMCMIfG5cceeu4I1k0x GIFrjLwrmyiIy1ScWVgHsxbSdcTjJQGPJOfKEDTBHQ/va40xAcdTG4o/ExpMJfDbhp4I c4Nv780udNxUlYDMSnDz37mWD/BXJ4pXi3wZkG8IyiJCKUV6bbM162z7fFkQubq6ZCS8 oTWg== X-Gm-Message-State: AC+VfDxFeMMBi6s44k7QTVB6TJ6YK7i6+QV6mWxSm6jktq8Y1OL0pOI+ h6g7CBrGHpWHqJcv2h/BcA3pACoqRVGQMU/1qBGvMQ== X-Google-Smtp-Source: ACHHUZ4xgtI2fPq3ueJ+TfTEwHlXOxajZDPn/HFs6iydGbrS2b4OxhiE8cbOKSQhpTNWlp065tcSiQ== X-Received: by 2002:a1c:790f:0:b0:3eb:3945:d405 with SMTP id l15-20020a1c790f000000b003eb3945d405mr2540690wme.38.1683357759438; Sat, 06 May 2023 00:22:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 03/30] tcg/aarch64: Introduce prepare_host_addr Date: Sat, 6 May 2023 08:22:08 +0100 Message-Id: <20230506072235.597467-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683357864341100001 Content-Type: text/plain; charset="utf-8" Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/aarch64/tcg-target.c.inc | 313 +++++++++++++++-------------------- 1 file changed, 133 insertions(+), 180 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index d8d464e4a0..202b90c001 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1667,113 +1667,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) tcg_out_goto(s, lb->raddr); return true; } - -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, - TCGType ext, TCGReg data_reg, TCGReg addr_= reg, - tcg_insn_unit *raddr, tcg_insn_unit *label= _ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D ext; - label->datalo_reg =3D data_reg; - label->addrlo_reg =3D addr_reg; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr; -} - -/* We expect to use a 7-bit scaled negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512); - -/* These offsets are built into the LDP below. */ -QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); -QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 8); - -/* Load and compare a TLB entry, emitting the conditional jump to the - slow path for the failure case, which will be patched later when finali= zing - the slow path. Generated code returns the host addend in X1, - clobbers X0,X2,X3,TMP. */ -static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc, - tcg_insn_unit **label_ptr, int mem_index, - bool is_read) -{ - unsigned a_bits =3D get_alignment_bits(opc); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_mask =3D (1u << a_bits) - 1; - unsigned s_mask =3D (1u << s_bits) - 1; - TCGReg x3; - TCGType mask_type; - uint64_t compare_mask; - - mask_type =3D (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32 - ? TCG_TYPE_I64 : TCG_TYPE_I32); - - /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */ - tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0, - TLB_MASK_TABLE_OFS(mem_index), 1, 0); - - /* Extract the TLB index from the address into X0. */ - tcg_out_insn(s, 3502S, AND_LSR, mask_type =3D=3D TCG_TYPE_I64, - TCG_REG_X0, TCG_REG_X0, addr_reg, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - - /* Add the tlb_table pointer, creating the CPUTLBEntry address into X1= . */ - tcg_out_insn(s, 3502, ADD, 1, TCG_REG_X1, TCG_REG_X1, TCG_REG_X0); - - /* Load the tlb comparator into X0, and the fast path addend into X1. = */ - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_X0, TCG_REG_X1, is_read - ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, TCG_REG_X1, - offsetof(CPUTLBEntry, addend)); - - /* For aligned accesses, we check the first byte and include the align= ment - bits within the address. For unaligned access, we check that we do= n't - cross pages using the address of the last byte of the access. */ - if (a_bits >=3D s_bits) { - x3 =3D addr_reg; - } else { - tcg_out_insn(s, 3401, ADDI, TARGET_LONG_BITS =3D=3D 64, - TCG_REG_X3, addr_reg, s_mask - a_mask); - x3 =3D TCG_REG_X3; - } - compare_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; - - /* Store the page mask part of the address into X3. */ - tcg_out_logicali(s, I3404_ANDI, TARGET_LONG_BITS =3D=3D 64, - TCG_REG_X3, x3, compare_mask); - - /* Perform the address comparison. */ - tcg_out_cmp(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X0, TCG_REG_X3, 0); - - /* If not equal, we jump to the slow path. */ - *label_ptr =3D s->code_ptr; - tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); -} - #else -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_= reg, - unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->addrlo_reg =3D addr_reg; - - /* tst addr, #mask */ - tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask); - - label->label_ptr[0] =3D s->code_ptr; - - /* b.ne slow_path */ - tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); - - label->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { if (!reloc_pc19(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -1801,6 +1695,125 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) } #endif /* CONFIG_SOFTMMU */ =20 +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addr_reg, MemOpIdx oi, + bool is_ld) +{ + TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned a_mask =3D (1u << a_bits) - 1; + +#ifdef CONFIG_SOFTMMU + unsigned s_bits =3D opc & MO_SIZE; + unsigned s_mask =3D (1u << s_bits) - 1; + unsigned mem_index =3D get_mmuidx(oi); + TCGReg x3; + TCGType mask_type; + uint64_t compare_mask; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + mask_type =3D (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32 + ? TCG_TYPE_I64 : TCG_TYPE_I32); + + /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */ + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512); + QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); + QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 8); + tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0, + TLB_MASK_TABLE_OFS(mem_index), 1, 0); + + /* Extract the TLB index from the address into X0. */ + tcg_out_insn(s, 3502S, AND_LSR, mask_type =3D=3D TCG_TYPE_I64, + TCG_REG_X0, TCG_REG_X0, addr_reg, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + + /* Add the tlb_table pointer, creating the CPUTLBEntry address into X1= . */ + tcg_out_insn(s, 3502, ADD, 1, TCG_REG_X1, TCG_REG_X1, TCG_REG_X0); + + /* Load the tlb comparator into X0, and the fast path addend into X1. = */ + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_X0, TCG_REG_X1, + is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, TCG_REG_X1, + offsetof(CPUTLBEntry, addend)); + + /* + * For aligned accesses, we check the first byte and include the align= ment + * bits within the address. For unaligned access, we check that we do= n't + * cross pages using the address of the last byte of the access. + */ + if (a_bits >=3D s_bits) { + x3 =3D addr_reg; + } else { + tcg_out_insn(s, 3401, ADDI, TARGET_LONG_BITS =3D=3D 64, + TCG_REG_X3, addr_reg, s_mask - a_mask); + x3 =3D TCG_REG_X3; + } + compare_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; + + /* Store the page mask part of the address into X3. */ + tcg_out_logicali(s, I3404_ANDI, TARGET_LONG_BITS =3D=3D 64, + TCG_REG_X3, x3, compare_mask); + + /* Perform the address comparison. */ + tcg_out_cmp(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X0, TCG_REG_X3, 0); + + /* If not equal, we jump to the slow path. */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); + + *h =3D (HostAddress){ + .base =3D TCG_REG_X1, + .index =3D addr_reg, + .index_ext =3D addr_type + }; +#else + if (a_mask) { + ldst =3D new_ldst_label(s); + + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + /* tst addr, #mask */ + tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask); + + /* b.ne slow_path */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); + } + + if (USE_GUEST_BASE) { + *h =3D (HostAddress){ + .base =3D TCG_REG_GUEST_BASE, + .index =3D addr_reg, + .index_ext =3D addr_type + }; + } else { + *h =3D (HostAddress){ + .base =3D addr_reg, + .index =3D TCG_REG_XZR, + .index_ext =3D TCG_TYPE_I64 + }; + } +#endif + + return ldst; +} + static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext, TCGReg data_r, HostAddress h) { @@ -1857,93 +1870,33 @@ static void tcg_out_qemu_st_direct(TCGContext *s, M= emOp memop, static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp memop =3D get_memop(oi); - TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; + TCGLabelQemuLdst *ldst; HostAddress h; =20 - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, true); + tcg_out_qemu_ld_direct(s, get_memop(oi), data_type, data_reg, h); =20 -#ifdef CONFIG_SOFTMMU - tcg_insn_unit *label_ptr; - - tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 1); - - h =3D (HostAddress){ - .base =3D TCG_REG_X1, - .index =3D addr_reg, - .index_ext =3D addr_type - }; - tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, h); - - add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ - unsigned a_bits =3D get_alignment_bits(memop); - if (a_bits) { - tcg_out_test_alignment(s, true, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - if (USE_GUEST_BASE) { - h =3D (HostAddress){ - .base =3D TCG_REG_GUEST_BASE, - .index =3D addr_reg, - .index_ext =3D addr_type - }; - } else { - h =3D (HostAddress){ - .base =3D addr_reg, - .index =3D TCG_REG_XZR, - .index_ext =3D TCG_TYPE_I64 - }; - } - tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, h); -#endif /* CONFIG_SOFTMMU */ } =20 static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp memop =3D get_memop(oi); - TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; + TCGLabelQemuLdst *ldst; HostAddress h; =20 - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, false); + tcg_out_qemu_st_direct(s, get_memop(oi), data_reg, h); =20 -#ifdef CONFIG_SOFTMMU - tcg_insn_unit *label_ptr; - - tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 0); - - h =3D (HostAddress){ - .base =3D TCG_REG_X1, - .index =3D addr_reg, - .index_ext =3D addr_type - }; - tcg_out_qemu_st_direct(s, memop, data_reg, h); - - add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ - unsigned a_bits =3D get_alignment_bits(memop); - if (a_bits) { - tcg_out_test_alignment(s, false, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - if (USE_GUEST_BASE) { - h =3D (HostAddress){ - .base =3D TCG_REG_GUEST_BASE, - .index =3D addr_reg, - .index_ext =3D addr_type - }; - } else { - h =3D (HostAddress){ - .base =3D addr_reg, - .index =3D TCG_REG_XZR, - .index_ext =3D TCG_TYPE_I64 - }; - } - tcg_out_qemu_st_direct(s, memop, data_reg, h); -#endif /* CONFIG_SOFTMMU */ } =20 static const tcg_insn_unit *tb_ret_addr; --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683357921; cv=none; d=zohomail.com; s=zohoarc; b=KsngGT1At7XOEtNKu/7+j/V8HWcHw38OnN6gDdojjttCpGP8PyV76sLp6Xrc0uOe8ro80iu5FDWWpK4HN1Sk9o+qGJE26uXmELqIu1c4FgPEKxOuk5AT365I07e+5Pxw4VX+fJexHhmsZY0hjgUqL7F+LuNKOK45AcF3jlzUo/Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683357921; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SdzMRJhqVnkJZuasJRxOLnNhkaxRsl4XQRta0/ryyec=; b=WUNENMFS54KqSkb8FnOaK6CsXYrsa7JdyBlPlZ87AlcdNIEFxLfO9eTanuBeBlQXYFVguf6QloL3xobUM31vh3iH1BWkAhp18DUgoMwxy4tWG+Q/senO6GPXJu1qUP1aT1ozUPMZ5fxYOcwxbvT4Y5bgxW8yAHnwDi7j7ayAkeA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683357921957361.01294345065685; Sat, 6 May 2023 00:25:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCFl-00040W-Ug; Sat, 06 May 2023 03:22:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCFj-0003y1-Hv for qemu-devel@nongnu.org; Sat, 06 May 2023 03:22:47 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFd-0004Lh-RW for qemu-devel@nongnu.org; Sat, 06 May 2023 03:22:47 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-3f315712406so120556965e9.0 for ; Sat, 06 May 2023 00:22:41 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357760; x=1685949760; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SdzMRJhqVnkJZuasJRxOLnNhkaxRsl4XQRta0/ryyec=; b=ErxfAaw7I4X+I4qJH0bPVZ8LS/xUZKchOihf9LOBrkKdgZEw6ain6WHXWpdJBNAADk vXnX5Bi/nIIYJ6sGfsPBT581tjrC8lXOiqqk2qUT34YyVq+b5p2Z9HYMPColU9Ylz4pG LlyWemmPIb8H+gIQzxJzxhp/E1YfY83VipeMbjeNxp2sa1quv/xc7E9DYMzamTSRum8c 86pRmQboPkrJFAydtNLKLZC1xMHQmsbuyiEecxqE9gqE0HE5f3emOLlvT0mRTrHDDo7u Atqp4BR3chUEQ/45Vu2+YO3OREw0a8WjeLHjhAPvBOA9F1bGdgWZhrFfGo877FnpJpnn FE8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357760; x=1685949760; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SdzMRJhqVnkJZuasJRxOLnNhkaxRsl4XQRta0/ryyec=; b=ID6ApqsdbwSUi7pWGKUDwmDSZwprdcJ/nSMOef1tGIOYUt9SzLTaZQVql+5kT3RHQc hJuMvjQGbeHGxgoyuu00GfPitKZtlBMxgrzo+5rLJOZcUrSGPWTkrIBzGu0rzSq9Os9j hk9e1NcFJvqmZSvBzAiheNmDd/q23VnK31emkPFRS+BX6Bu6LUyw5kofEf8y3fOxjMqp e+Gw89BAZJ0QJzDtFlXdL78/O3SJsN4mqGDNk8lBcZvp18yoO3O5bSNsLTv6+TN0zW73 bbK44xeJ9AyIuvFRqE4cvfRr6JemfIo6mTMwOlIPtBIvA4BYn/r8/pO0srJtj890yVdB JtPw== X-Gm-Message-State: AC+VfDwbniQJvWSiJqYaeu7lMniVhFJZuwStA8ov55W71WMFugYXYUDt PvRNwGTFDoz+ua0V+viLN3E2URHUirgLoufDgPDDVw== X-Google-Smtp-Source: ACHHUZ6qZ2XaoGTVtjvadP1VIlduJtYPdHT+4RpGFuI159G6+IhXrV4J5sZtCQRxnSRM5ypKtUGfQA== X-Received: by 2002:a5d:63cd:0:b0:306:31cb:25fb with SMTP id c13-20020a5d63cd000000b0030631cb25fbmr5765627wrw.17.1683357760251; Sat, 06 May 2023 00:22:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 04/30] tcg/arm: Introduce prepare_host_addr Date: Sat, 6 May 2023 08:22:09 +0100 Message-Id: <20230506072235.597467-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683357922364100001 Content-Type: text/plain; charset="utf-8" Merge tcg_out_tlb_load, add_qemu_ldst_label, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/arm/tcg-target.c.inc | 351 ++++++++++++++++++--------------------- 1 file changed, 159 insertions(+), 192 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index b6b4ffc546..c744512778 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1434,125 +1434,6 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGR= eg argreg, } } =20 -#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS) - -/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256); - -/* These offsets are built into the LDRD below. */ -QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); -QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 4); - -/* Load and compare a TLB entry, leaving the flags set. Returns the regis= ter - containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */ - -static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, - MemOp opc, int mem_index, bool is_load) -{ - int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); - unsigned s_mask =3D (1 << (opc & MO_SIZE)) - 1; - unsigned a_mask =3D (1 << get_alignment_bits(opc)) - 1; - TCGReg t_addr; - - /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */ - tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); - - /* Extract the tlb index from the address into R0. */ - tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo, - SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)); - - /* - * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. - * Load the tlb comparator into R2/R3 and the fast path addend into R1. - */ - if (cmp_off =3D=3D 0) { - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); - } else { - tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); - } - } else { - tcg_out_dat_reg(s, COND_AL, ARITH_ADD, - TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); - } else { - tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); - } - } - - /* Load the tlb addend. */ - tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, - offsetof(CPUTLBEntry, addend)); - - /* - * Check alignment, check comparators. - * Do this in 2-4 insns. Use MOVW for v7, if possible, - * to reduce the number of sequential conditional instructions. - * Almost all guests have at least 4k pages, which means that we need - * to clear at least 9 bits even for an 8-byte memory, which means it - * isn't worth checking for an immediate operand for BIC. - * - * For unaligned accesses, test the page of the last unit of alignment. - * This leaves the least significant alignment bits unchanged, and of - * course must be zero. - */ - t_addr =3D addrlo; - if (a_mask < s_mask) { - t_addr =3D TCG_REG_R0; - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, - addrlo, s_mask - a_mask); - } - if (use_armv7_instructions && TARGET_PAGE_BITS <=3D 16) { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(TARGET_PAGE_MASK | a_mas= k)); - tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, - t_addr, TCG_REG_TMP, 0); - tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP,= 0); - } else { - if (a_mask) { - tcg_debug_assert(a_mask <=3D 0xff); - tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); - } - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, - SHIFT_IMM_LSR(TARGET_PAGE_BITS)); - tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, - 0, TCG_REG_R2, TCG_REG_TMP, - SHIFT_IMM_LSL(TARGET_PAGE_BITS)); - } - - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0); - } - - return TCG_REG_R1; -} - -/* Record the context of a call to the out of line helper code for the slow - path for a load or store, so that we can later generate the correct - helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, - MemOpIdx oi, TCGType type, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addrhi, - tcg_insn_unit *raddr, - tcg_insn_unit *label_ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D type; - label->datalo_reg =3D datalo; - label->datahi_reg =3D datahi; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr; -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGReg argreg; @@ -1636,29 +1517,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) return true; } #else - -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrl= o, - TCGReg addrhi, unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; - - /* We are expecting a_bits to max out at 7, and can easily support 8. = */ - tcg_debug_assert(a_mask <=3D 0xff); - /* tst addr, #mask */ - tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); - - /* blne slow_path */ - label->label_ptr[0] =3D s->code_ptr; - tcg_out_bl_imm(s, COND_NE, 0); - - label->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { if (!reloc_pc24(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -1703,6 +1561,134 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) } #endif /* SOFTMMU */ =20 +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, bool is_ld) +{ + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + MemOp a_bits =3D get_alignment_bits(opc); + unsigned a_mask =3D (1 << a_bits) - 1; + +#ifdef CONFIG_SOFTMMU + int mem_index =3D get_mmuidx(oi); + int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write); + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + unsigned s_mask =3D (1 << (opc & MO_SIZE)) - 1; + TCGReg t_addr; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */ + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256); + QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); + QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 4); + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); + + /* Extract the tlb index from the address into R0. */ + tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo, + SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)); + + /* + * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. + * Load the tlb comparator into R2/R3 and the fast path addend into R1. + */ + if (cmp_off =3D=3D 0) { + if (TARGET_LONG_BITS =3D=3D 64) { + tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); + } else { + tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); + } + } else { + tcg_out_dat_reg(s, COND_AL, ARITH_ADD, + TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); + if (TARGET_LONG_BITS =3D=3D 64) { + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); + } else { + tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); + } + } + + /* Load the tlb addend. */ + tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, + offsetof(CPUTLBEntry, addend)); + + /* + * Check alignment, check comparators. + * Do this in 2-4 insns. Use MOVW for v7, if possible, + * to reduce the number of sequential conditional instructions. + * Almost all guests have at least 4k pages, which means that we need + * to clear at least 9 bits even for an 8-byte memory, which means it + * isn't worth checking for an immediate operand for BIC. + * + * For unaligned accesses, test the page of the last unit of alignment. + * This leaves the least significant alignment bits unchanged, and of + * course must be zero. + */ + t_addr =3D addrlo; + if (a_mask < s_mask) { + t_addr =3D TCG_REG_R0; + tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, + addrlo, s_mask - a_mask); + } + if (use_armv7_instructions && TARGET_PAGE_BITS <=3D 16) { + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(TARGET_PAGE_MASK | a_mas= k)); + tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, + t_addr, TCG_REG_TMP, 0); + tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP,= 0); + } else { + if (a_mask) { + tcg_debug_assert(a_mask <=3D 0xff); + tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); + } + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, + SHIFT_IMM_LSR(TARGET_PAGE_BITS)); + tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, + 0, TCG_REG_R2, TCG_REG_TMP, + SHIFT_IMM_LSL(TARGET_PAGE_BITS)); + } + + if (TARGET_LONG_BITS =3D=3D 64) { + tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0); + } + + *h =3D (HostAddress){ + .cond =3D COND_AL, + .base =3D addrlo, + .index =3D TCG_REG_R1, + .index_scratch =3D true, + }; +#else + if (a_mask) { + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + /* We are expecting a_bits to max out at 7 */ + tcg_debug_assert(a_mask <=3D 0xff); + /* tst addr, #mask */ + tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); + } + + *h =3D (HostAddress){ + .cond =3D COND_AL, + .base =3D addrlo, + .index =3D guest_base ? TCG_REG_GUEST_BASE : -1, + .index_scratch =3D false, + }; +#endif + + return ldst; +} + static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, TCGReg datahi, HostAddress h) { @@ -1799,37 +1785,28 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - h.cond =3D COND_AL; - h.base =3D addrlo; - h.index_scratch =3D true; - h.index =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 1= ); + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, true); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; =20 - /* - * This a conditional BL only to load a pointer within this opcode into - * LR for the slow path. We will not be using the value for a tail ca= ll. - */ - tcg_insn_unit *label_ptr =3D s->code_ptr; - tcg_out_bl_imm(s, COND_NE, 0); + /* + * This a conditional BL only to load a pointer within this + * opcode into LR for the slow path. We will not be using + * the value for a tail call. + */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_bl_imm(s, COND_NE, 0); =20 - tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); - - add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); + tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); + } else { + tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); } - - h.cond =3D COND_AL; - h.base =3D addrlo; - h.index =3D guest_base ? TCG_REG_GUEST_BASE : -1; - h.index_scratch =3D false; - tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); -#endif } =20 static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, @@ -1891,35 +1868,25 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - h.cond =3D COND_EQ; - h.base =3D addrlo; - h.index_scratch =3D true; - h.index =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 0= ); - tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, false); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; =20 - /* The conditional call must come last, as we're going to return here.= */ - tcg_insn_unit *label_ptr =3D s->code_ptr; - tcg_out_bl_imm(s, COND_NE, 0); - - add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - - h.cond =3D COND_AL; - if (a_bits) { - tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); h.cond =3D COND_EQ; - } + tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); =20 - h.base =3D addrlo; - h.index =3D guest_base ? TCG_REG_GUEST_BASE : -1; - h.index_scratch =3D false; - tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); -#endif + /* The conditional call is last, as we're going to return here. */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_bl_imm(s, COND_NE, 0); + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); + } else { + tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); + } } =20 static void tcg_out_epilogue(TCGContext *s); --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683358000; cv=none; d=zohomail.com; s=zohoarc; b=i4VbNOaDFOn3xDbNijGFUQFy9Dw5MPLpRlWcLjh72Oqa1Sp6aiF9LtEr5Rp7s+SFGnJaWrmZtwpwBwyp7wuEwPsXAPuQce1Z0LqXLqtVGewL1uaI8XYymuIwlInL3jADFdcfaWrMUZzil5BXVfRQv089DQJ3rbW3PxwR9ArIUbk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683358000; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=N0k727NYZjnrZBTMhehFGEr2gxv6PrKgfLN9LqxUppY=; b=noxmgj3UAPv5SaOGCjSlKXtiug89RVPBasEjHA2mBoVgjMouaSmkw8HvVXAUT/F7AEZdnQY2yEmdF3ZsJ8Eb0iZoN/RUeN69V+qI3dK/B22J25sH9aLHZAEN3UwSIQPHjuUPUmLdtJBtaSWBETnUTCrGmWk44nrYGiwKIxiAZoM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683358000643692.8292904111797; Sat, 6 May 2023 00:26:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCFm-00040Y-0X; Sat, 06 May 2023 03:22:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCFk-0003yy-4e for qemu-devel@nongnu.org; Sat, 06 May 2023 03:22:48 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFe-0004Lq-EG for qemu-devel@nongnu.org; Sat, 06 May 2023 03:22:47 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-3078c092056so17446f8f.1 for ; Sat, 06 May 2023 00:22:41 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/loongarch64/tcg-target.c.inc | 255 +++++++++++++------------------ 1 file changed, 105 insertions(+), 150 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 6a87a5e5a3..2f2c34b930 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -818,81 +818,12 @@ static void * const qemu_st_helpers[4] =3D { [MO_64] =3D helper_le_stq_mmu, }; =20 -/* We expect to use a 12-bit negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); - static bool tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) { tcg_out_opc_b(s, 0); return reloc_br_sd10k16(s->code_ptr - 1, target); } =20 -/* - * Emits common code for TLB addend lookup, that eventually loads the - * addend in TCG_REG_TMP2. - */ -static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, MemOpIdx oi, - tcg_insn_unit **label_ptr, bool is_load) -{ - MemOp opc =3D get_memop(oi); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_bits =3D get_alignment_bits(opc); - tcg_target_long compare_mask; - int mem_index =3D get_mmuidx(oi); - int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); - int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); - int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); - - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); - - tcg_out_opc_srli_d(s, TCG_REG_TMP2, addrl, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); - tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); - - /* Load the tlb comparator and the addend. */ - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, - is_load ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, - offsetof(CPUTLBEntry, addend)); - - /* We don't support unaligned accesses. */ - if (a_bits < s_bits) { - a_bits =3D s_bits; - } - /* Clear the non-page, non-alignment bits from the address. */ - compare_mask =3D (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - = 1); - tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); - tcg_out_opc_and(s, TCG_REG_TMP1, TCG_REG_TMP1, addrl); - - /* Compare masked address with the TLB entry. */ - label_ptr[0] =3D s->code_ptr; - tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0); - - /* TLB Hit - addend in TCG_REG_TMP2, ready for use. */ -} - -static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, - TCGType type, - TCGReg datalo, TCGReg addrlo, - void *raddr, tcg_insn_unit **label_ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D type; - label->datalo_reg =3D datalo; - label->datahi_reg =3D 0; /* unused */ - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D 0; /* unused */ - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr[0]; -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { MemOpIdx oi =3D l->oi; @@ -941,33 +872,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, T= CGLabelQemuLdst *l) return tcg_out_goto(s, l->raddr); } #else - -/* - * Alignment helpers for user-mode emulation - */ - -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_= reg, - unsigned a_bits) -{ - TCGLabelQemuLdst *l =3D new_ldst_label(s); - - l->is_ld =3D is_ld; - l->addrlo_reg =3D addr_reg; - - /* - * Without micro-architecture details, we don't know which of bstrpick= or - * andi is faster, so use bstrpick as it's not constrained by imm field - * width. (Not to say alignments >=3D 2^12 are going to happen any time - * soon, though) - */ - tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1); - - l->label_ptr[0] =3D s->code_ptr; - tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0); - - l->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { /* resolve label address */ @@ -997,27 +901,102 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) =20 #endif /* CONFIG_SOFTMMU */ =20 -/* - * `ext32u` the address register into the temp register given, - * if target is 32-bit, no-op otherwise. - * - * Returns the address register ready for use with TLB addend. - */ -static TCGReg tcg_out_zext_addr_if_32_bit(TCGContext *s, - TCGReg addr, TCGReg tmp) -{ - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, tmp, addr); - return tmp; - } - return addr; -} - typedef struct { TCGReg base; TCGReg index; } HostAddress; =20 +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addr_reg, MemOpIdx oi, + bool is_ld) +{ + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + +#ifdef CONFIG_SOFTMMU + unsigned s_bits =3D opc & MO_SIZE; + int mem_index =3D get_mmuidx(oi); + int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); + int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); + tcg_target_long compare_mask; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); + + tcg_out_opc_srli_d(s, TCG_REG_TMP2, addr_reg, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); + tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); + + /* Load the tlb comparator and the addend. */ + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, + is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, + offsetof(CPUTLBEntry, addend)); + + /* We don't support unaligned accesses. */ + if (a_bits < s_bits) { + a_bits =3D s_bits; + } + /* Clear the non-page, non-alignment bits from the address. */ + compare_mask =3D (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - = 1); + tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); + tcg_out_opc_and(s, TCG_REG_TMP1, TCG_REG_TMP1, addr_reg); + + /* Compare masked address with the TLB entry. */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0); + + h->index =3D TCG_REG_TMP2; +#else + if (a_bits) { + ldst =3D new_ldst_label(s); + + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + /* + * Without micro-architecture details, we don't know which of + * bstrpick or andi is faster, so use bstrpick as it's not + * constrained by imm field width. Not to say alignments >=3D 2^12 + * are going to happen any time soon. + */ + tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1); + + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0); + } + + h->index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; +#endif + + if (TARGET_LONG_BITS =3D=3D 32) { + h->base =3D TCG_REG_TMP0; + tcg_out_ext32u(s, h->base, addr_reg); + } else { + h->base =3D addr_reg; + } + + return ldst; +} + static void tcg_out_qemu_ld_indexed(TCGContext *s, MemOp opc, TCGType type, TCGReg rd, HostAddress h) { @@ -1057,29 +1036,17 @@ static void tcg_out_qemu_ld_indexed(TCGContext *s, = MemOp opc, TCGType type, static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - tcg_insn_unit *label_ptr[1]; + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, true); + tcg_out_qemu_ld_indexed(s, get_memop(oi), data_type, data_reg, h); =20 - tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1); - h.index =3D TCG_REG_TMP2; -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, true, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - h.index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; -#endif - - h.base =3D tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0); - tcg_out_qemu_ld_indexed(s, opc, data_type, data_reg, h); - -#ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#endif } =20 static void tcg_out_qemu_st_indexed(TCGContext *s, MemOp opc, @@ -1109,29 +1076,17 @@ static void tcg_out_qemu_st_indexed(TCGContext *s, = MemOp opc, static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - tcg_insn_unit *label_ptr[1]; + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, false); + tcg_out_qemu_st_indexed(s, get_memop(oi), data_reg, h); =20 - tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0); - h.index =3D TCG_REG_TMP2; -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, false, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - h.index =3D USE_GUEST_BASE ? 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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357762; x=1685949762; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XFFoGgTSegPUQaI6pnaNFJ9C8ggJbjecIiSqmvyzOfY=; b=LqfRYSLibNpB/iDQtSk19LJldUhiLUpGhoK+mNSxRoTwBJTvkfrD3AvWk6MwmErbLX +JcqRtp0hsnvb56FHZC3MBGBsJSfvfXeIE3WRXoMc5qoWPuLzBoAJjNh0yjyDbAf6hjk Rpr+wp37JnJAW4YxWdtoIxY62KzS46voPGTg+/eIeGCBWjRl5h25Jtr/LTLKBhuiiOXQ QrP9YN/CvS89P76WPwbT7HWAZLNySClygyh2xlllO6XcdNCyBwygagENxD+Wf/c/X+5H Iw32eHguMKRNBbMGBhHXo/GrOi1zLULb3BUBxSoAM7EXUIY2Ds7lVs7AcaTl11W/plIh mCMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357762; x=1685949762; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XFFoGgTSegPUQaI6pnaNFJ9C8ggJbjecIiSqmvyzOfY=; b=R/BsR3ZOGQJm94xi+xKxSbHA2EWJupQ9kHnngWtjai0wEzi08mpDFqeZS0AOHmWsPj vUTluPvCHeyN7N2QDaQpJwBOEKP9XH/1Mzq83oZe6F92pHkZ85eUAw6gV7wCBru/IsIM wrc+NJj0UIvWHm0HK9+t7BHQP7w1vVU5FmRHD3BodGmUqVVjLEPmo8BysT3NJFBjepk3 2eDv1RJSYKUsD6NqwzCXxyOwTrrHzJv69DZ1EzuRsdjMlsNpoST5HTjdvJwYb87VtRcK IFewP59yARMBmZijCQDvLUdJZAh9lg/5Ft7WZSkT2/lo+HAP9jOnR/qncKxSALy1LO2r DmDg== X-Gm-Message-State: AC+VfDzptuMa/hdmGKwqF03RJ27CuB1wNClW2Hmrf2VEvyWVC54F/JZZ 0xHfp1wQdnbPvo6e9r8F5F4DA9iR0qg8dnTn5Bcjuw== X-Google-Smtp-Source: ACHHUZ664OqJF6eTc3WCyACtOysFXY7olmjs002ZMzAqiSfmAktDKNbEQJ2LMxUraNG/pRFVxEQHlw== X-Received: by 2002:adf:ec0b:0:b0:306:4569:34a0 with SMTP id x11-20020adfec0b000000b00306456934a0mr3413880wrn.69.1683357761703; Sat, 06 May 2023 00:22:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 06/30] tcg/mips: Introduce prepare_host_addr Date: Sat, 6 May 2023 08:22:11 +0100 Message-Id: <20230506072235.597467-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683357981174100001 Content-Type: text/plain; charset="utf-8" Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/mips/tcg-target.c.inc | 404 ++++++++++++++++---------------------- 1 file changed, 172 insertions(+), 232 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index ef8350e9cd..94708e6ea7 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1181,120 +1181,6 @@ static int tcg_out_call_iarg_reg2(TCGContext *s, in= t i, TCGReg al, TCGReg ah) return i; } =20 -/* We expect to use a 16-bit negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); - -/* - * Perform the tlb comparison operation. - * The complete host address is placed in BASE. - * Clobbers TMP0, TMP1, TMP2, TMP3. - */ -static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, - TCGReg addrh, MemOpIdx oi, - tcg_insn_unit *label_ptr[2], bool is_load) -{ - MemOp opc =3D get_memop(oi); - unsigned a_bits =3D get_alignment_bits(opc); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_mask =3D (1 << a_bits) - 1; - unsigned s_mask =3D (1 << s_bits) - 1; - int mem_index =3D get_mmuidx(oi); - int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); - int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); - int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); - int add_off =3D offsetof(CPUTLBEntry, addend); - int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - target_ulong tlb_mask; - - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); - - /* Extract the TLB index from the address into TMP3. */ - tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); - - /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3= . */ - tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); - - /* Load the (low-half) tlb comparator. */ - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); - } else { - tcg_out_ldst(s, (TARGET_LONG_BITS =3D=3D 64 ? OPC_LD - : TCG_TARGET_REG_BITS =3D=3D 64 ? OPC_LWU : OPC_L= W), - TCG_TMP0, TCG_TMP3, cmp_off); - } - - /* Zero extend a 32-bit guest address for a 64-bit host. */ - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addrl); - addrl =3D base; - } - - /* - * Mask the page bits, keeping the alignment bits to compare against. - * For unaligned accesses, compare against the end of the access to - * verify that it does not cross a page boundary. - */ - tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; - tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, tlb_mask); - if (a_mask >=3D s_mask) { - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); - } else { - tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP2, addrl, s_mask - a_mask); - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); - } - - if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { - /* Load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); - } - - label_ptr[0] =3D s->code_ptr; - tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); - - /* Load and test the high half tlb comparator. */ - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - /* delay slot */ - tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); - - /* Load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); - - label_ptr[1] =3D s->code_ptr; - tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0); - } - - /* delay slot */ - tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl); -} - -static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, - TCGType ext, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addrhi, - void *raddr, tcg_insn_unit *label_ptr[2]) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D ext; - label->datalo_reg =3D datalo; - label->datahi_reg =3D datahi; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr[0]; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - label->label_ptr[1] =3D label_ptr[1]; - } -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { const tcg_insn_unit *tgt_rx =3D tcg_splitwx_to_rx(s->code_ptr); @@ -1403,32 +1289,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) } =20 #else - -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrl= o, - TCGReg addrhi, unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *l =3D new_ldst_label(s); - - l->is_ld =3D is_ld; - l->addrlo_reg =3D addrlo; - l->addrhi_reg =3D addrhi; - - /* We are expecting a_bits to max out at 7, much lower than ANDI. */ - tcg_debug_assert(a_bits < 16); - tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask); - - l->label_ptr[0] =3D s->code_ptr; - if (use_mips32r6_instructions) { - tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); - } else { - tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); - tcg_out_nop(s); - } - - l->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { void *target; @@ -1478,6 +1338,154 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) } #endif /* SOFTMMU */ =20 +typedef struct { + TCGReg base; + MemOp align; +} HostAddress; + +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, bool is_ld) +{ + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned s_bits =3D opc & MO_SIZE; + unsigned a_mask =3D (1 << a_bits) - 1; + TCGReg base; + +#ifdef CONFIG_SOFTMMU + unsigned s_mask =3D (1 << s_bits) - 1; + int mem_index =3D get_mmuidx(oi); + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); + int add_off =3D offsetof(CPUTLBEntry, addend); + int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write); + target_ulong tlb_mask; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + base =3D TCG_REG_A0; + + /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); + + /* Extract the TLB index from the address into TMP3. */ + tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrlo, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); + + /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3= . */ + tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); + + /* Load the (low-half) tlb comparator. */ + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); + } else { + tcg_out_ldst(s, (TARGET_LONG_BITS =3D=3D 64 ? OPC_LD + : TCG_TARGET_REG_BITS =3D=3D 64 ? OPC_LWU : OPC_L= W), + TCG_TMP0, TCG_TMP3, cmp_off); + } + + /* Zero extend a 32-bit guest address for a 64-bit host. */ + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, base, addrlo); + addrlo =3D base; + } + + /* + * Mask the page bits, keeping the alignment bits to compare against. + * For unaligned accesses, compare against the end of the access to + * verify that it does not cross a page boundary. + */ + tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; + tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, tlb_mask); + if (a_mask >=3D s_mask) { + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo); + } else { + tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP2, addrlo, s_mask - a_mask); + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); + } + + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + /* Load the tlb addend for the fast path. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); + } + + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); + + /* Load and test the high half tlb comparator. */ + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + /* delay slot */ + tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); + + /* Load the tlb addend for the fast path. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); + + ldst->label_ptr[1] =3D s->code_ptr; + tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0); + } + + /* delay slot */ + tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrlo); +#else + if (a_mask && (use_mips32r6_instructions || a_bits !=3D s_bits)) { + ldst =3D new_ldst_label(s); + + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + /* We are expecting a_bits to max out at 7, much lower than ANDI. = */ + tcg_debug_assert(a_bits < 16); + tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask); + + ldst->label_ptr[0] =3D s->code_ptr; + if (use_mips32r6_instructions) { + tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); + } else { + tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); + tcg_out_nop(s); + } + } + + base =3D addrlo; + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_A0, base); + base =3D TCG_REG_A0; + } + if (guest_base) { + if (guest_base =3D=3D (int16_t)guest_base) { + tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); + } else { + tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, + TCG_GUEST_BASE_REG); + } + base =3D TCG_REG_A0; + } +#endif + + h->base =3D base; + h->align =3D a_bits; + return ldst; +} + static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, TCGReg base, MemOp opc, TCGType type) { @@ -1707,57 +1715,23 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); - unsigned a_bits =3D get_alignment_bits(opc); - unsigned s_bits =3D opc & MO_SIZE; - TCGReg base; + TCGLabelQemuLdst *ldst; + HostAddress h; =20 - /* - * R6 removes the left/right instructions but requires the - * system to support misaligned memory accesses. - */ -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[2]; + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, true); =20 - base =3D TCG_REG_A0; - tcg_out_tlb_load(s, base, addrlo, addrhi, oi, label_ptr, 1); - if (use_mips32r6_instructions || a_bits >=3D s_bits) { - tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type); + if (use_mips32r6_instructions || h.align >=3D (opc & MO_SIZE)) { + tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); } else { - tcg_out_qemu_ld_unalign(s, datalo, datahi, base, opc, data_type); + tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type); } - add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#else - base =3D addrlo; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_A0, base); - base =3D TCG_REG_A0; + + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - if (guest_base) { - if (guest_base =3D=3D (int16_t)guest_base) { - tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); - } else { - tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, - TCG_GUEST_BASE_REG); - } - base =3D TCG_REG_A0; - } - if (use_mips32r6_instructions) { - if (a_bits) { - tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); - } - tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type); - } else { - if (a_bits && a_bits !=3D s_bits) { - tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); - } - if (a_bits >=3D s_bits) { - tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type= ); - } else { - tcg_out_qemu_ld_unalign(s, datalo, datahi, base, opc, data_typ= e); - } - } -#endif } =20 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, @@ -1899,57 +1873,23 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); - unsigned a_bits =3D get_alignment_bits(opc); - unsigned s_bits =3D opc & MO_SIZE; - TCGReg base; + TCGLabelQemuLdst *ldst; + HostAddress h; =20 - /* - * R6 removes the left/right instructions but requires the - * system to support misaligned memory accesses. - */ -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[2]; + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, false); =20 - base =3D TCG_REG_A0; - tcg_out_tlb_load(s, base, addrlo, addrhi, oi, label_ptr, 0); - if (use_mips32r6_instructions || a_bits >=3D s_bits) { - tcg_out_qemu_st_direct(s, datalo, datahi, base, opc); + if (use_mips32r6_instructions || h.align >=3D (opc & MO_SIZE)) { + tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); } else { - tcg_out_qemu_st_unalign(s, datalo, datahi, base, opc); + tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); } - add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#else - base =3D addrlo; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_A0, base); - base =3D TCG_REG_A0; + + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - if (guest_base) { - if (guest_base =3D=3D (int16_t)guest_base) { - tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); 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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357762; x=1685949762; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E8LkZay/KDgOZOAPr4+3iyW8Oh14XA3T4+Op1DdY80A=; b=ZT6t2IlVLOgJYqcQs4S/8oNLEXkWpvrKnAqRC74+fMrvG3Xc7racYhSfEzxui4wwqi xsD3kozAubHhDlqxmkiQ/e/z7UKumF7JoNzf3b7kpZmPTG1F4Rx/tedybPti9TX5t+tu OURu/A8O5W5nrhgi/F1WswhdlbzTQKiXErAYpLrj35f9pd1Jy6ljTm3WR4Ib7vojXI0R IEIrSZAcb4vk0nbAD+9prTRPUkFUiYX91TlT15zr4dDFiU3bLA4WW3/JlXMH0KQsJO2n lLN6nGT90CSGQXvnvCGF+Bg5DulBi4Dm99r7fDv1PuFb509gM8s3/nSLs1hrtADF0Tmh uOzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357762; x=1685949762; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E8LkZay/KDgOZOAPr4+3iyW8Oh14XA3T4+Op1DdY80A=; b=gQ++ebP8GrlRDNtm2tUJLfiXqUex6sbelJE1jM9dRhsXgTJtVXTWOwdhLwxUnvrHgW LMt0eaphfUPHRpnQr1JFQ4Jf2EMo1FxedomyQWagLRDk7uw2ZV73GqKS+cCKzdoFFabP 7lEno7b0zGDwG9D574FYCf+Noh5fB/3uM0oFhbu8spa53em1D/4tlwcDQe7a/hzsBSRy bkx8Bt6AQ6GnKVVBIDavEDdPAFpoFjQ7U2mQ2V51xErB+lphCVDnZRh8JLXSibimpfuS 9jDFLXUE+0H3a7qTG0ZYAXYbapgYtkClJ1SVB4rhIZgDrw56xQxHq3t8H0m3SeHv7u59 LppA== X-Gm-Message-State: AC+VfDzMGfYabrZfrmsqKQOLQd39Pgs+uyD22+jf/o04EhKxSdq89Fbq b47qVfDTKOUsSs6G9Am58JXe3G/qDQkYedv3VBpluA== X-Google-Smtp-Source: ACHHUZ6aPZEUpnzsNfegyeVia94ycODBUQEbnKgSbv9Fn5EVykgEk+ALlBBEYZEH0KkVExZQDWjVwA== X-Received: by 2002:adf:cd0e:0:b0:304:6a26:1f6 with SMTP id w14-20020adfcd0e000000b003046a2601f6mr2991806wrm.59.1683357762438; Sat, 06 May 2023 00:22:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 07/30] tcg/ppc: Introduce prepare_host_addr Date: Sat, 6 May 2023 08:22:12 +0100 Message-Id: <20230506072235.597467-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683357827218100001 Content-Type: text/plain; charset="utf-8" Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/ppc/tcg-target.c.inc | 377 +++++++++++++++++---------------------- 1 file changed, 168 insertions(+), 209 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index cd473deb36..7239335bdf 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2003,140 +2003,6 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_B= SWAP) + 1] =3D { [MO_BEUQ] =3D helper_be_stq_mmu, }; =20 -/* We expect to use a 16-bit negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); - -/* Perform the TLB load and compare. Places the result of the comparison - in CR7, loads the addend of the TLB into R3, and returns the register - containing the guest address (zero-extended into R4). Clobbers R0 and = R2. */ - -static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc, - TCGReg addrlo, TCGReg addrhi, - int mem_index, bool is_read) -{ - int cmp_off - =3D (is_read - ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); - int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); - int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_bits =3D get_alignment_bits(opc); - - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off); - - /* Extract the page index, shifted into place for tlb index. */ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_shri32(s, TCG_REG_TMP1, addrlo, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - } else { - tcg_out_shri64(s, TCG_REG_TMP1, addrlo, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - } - tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1)); - - /* Load the TLB comparator. */ - if (cmp_off =3D=3D 0 && TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { - uint32_t lxu =3D (TCG_TARGET_REG_BITS =3D=3D 32 || TARGET_LONG_BIT= S =3D=3D 32 - ? LWZUX : LDUX); - tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4)); - } else { - tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4)); - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off = + 4); - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off); - } else { - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off); - } - } - - /* Load the TLB addend for use on the fast path. Do this asap - to minimize any load use delay. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, - offsetof(CPUTLBEntry, addend)); - - /* Clear the non-page, non-alignment bits from the address */ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - /* We don't support unaligned accesses on 32-bits. - * Preserve the bottom bits and thus trigger a comparison - * failure on unaligned accesses. - */ - if (a_bits < s_bits) { - a_bits =3D s_bits; - } - tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0, - (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); - } else { - TCGReg t =3D addrlo; - - /* If the access is unaligned, we need to make sure we fail if we - * cross a page boundary. The trick is to add the access size-1 - * to the address before masking the low bits. That will make the - * address overflow to the next page if we cross a page boundary, - * which will then force a mismatch of the TLB compare. - */ - if (a_bits < s_bits) { - unsigned a_mask =3D (1 << a_bits) - 1; - unsigned s_mask =3D (1 << s_bits) - 1; - tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask)); - t =3D TCG_REG_R0; - } - - /* Mask the address for the requested alignment. */ - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, - (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); - /* Zero-extend the address for use in the final address. */ - tcg_out_ext32u(s, TCG_REG_R4, addrlo); - addrlo =3D TCG_REG_R4; - } else if (a_bits =3D=3D 0) { - tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS= ); - } else { - tcg_out_rld(s, RLDICL, TCG_REG_R0, t, - 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits); - tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BIT= S, 0); - } - } - - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, - 0, 7, TCG_TYPE_I32); - tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32= ); - tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); - } else { - tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, - 0, 7, TCG_TYPE_TL); - } - - return addrlo; -} - -/* Record the context of a call to the out of line helper code for the slow - path for a load or store, so that we can later generate the correct - helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, - TCGType type, MemOpIdx oi, - TCGReg datalo_reg, TCGReg datahi_reg, - TCGReg addrlo_reg, TCGReg addrhi_reg, - tcg_insn_unit *raddr, tcg_insn_unit *lptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->type =3D type; - label->oi =3D oi; - label->datalo_reg =3D datalo_reg; - label->datahi_reg =3D datahi_reg; - label->addrlo_reg =3D addrlo_reg; - label->addrhi_reg =3D addrhi_reg; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D lptr; -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { MemOpIdx oi =3D lb->oi; @@ -2225,27 +2091,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) return true; } #else - -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrl= o, - TCGReg addrhi, unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; - - /* We are expecting a_bits to max out at 7, much lower than ANDI. */ - tcg_debug_assert(a_bits < 16); - tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, a_mask)); - - label->label_ptr[0] =3D s->code_ptr; - tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK); - - label->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { if (!reloc_pc14(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -2294,37 +2139,167 @@ typedef struct { TCGReg index; } HostAddress; =20 +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, bool is_ld) +{ + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + +#ifdef CONFIG_SOFTMMU + int mem_index =3D get_mmuidx(oi); + int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write); + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); + unsigned s_bits =3D opc & MO_SIZE; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off); + + /* Extract the page index, shifted into place for tlb index. */ + if (TCG_TARGET_REG_BITS =3D=3D 32) { + tcg_out_shri32(s, TCG_REG_TMP1, addrlo, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + } else { + tcg_out_shri64(s, TCG_REG_TMP1, addrlo, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + } + tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1)); + + /* Load the TLB comparator. */ + if (cmp_off =3D=3D 0 && TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + uint32_t lxu =3D (TCG_TARGET_REG_BITS =3D=3D 32 || TARGET_LONG_BIT= S =3D=3D 32 + ? LWZUX : LDUX); + tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4)); + } else { + tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4)); + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off = + 4); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off); + } else { + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off); + } + } + + /* Load the TLB addend for use on the fast path. Do this asap + to minimize any load use delay. */ + h->base =3D TCG_REG_R3; + tcg_out_ld(s, TCG_TYPE_PTR, h->base, TCG_REG_R3, + offsetof(CPUTLBEntry, addend)); + + /* Clear the non-page, non-alignment bits from the address */ + if (TCG_TARGET_REG_BITS =3D=3D 32) { + /* We don't support unaligned accesses on 32-bits. + * Preserve the bottom bits and thus trigger a comparison + * failure on unaligned accesses. + */ + if (a_bits < s_bits) { + a_bits =3D s_bits; + } + tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0, + (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); + } else { + TCGReg t =3D addrlo; + + /* If the access is unaligned, we need to make sure we fail if we + * cross a page boundary. The trick is to add the access size-1 + * to the address before masking the low bits. That will make the + * address overflow to the next page if we cross a page boundary, + * which will then force a mismatch of the TLB compare. + */ + if (a_bits < s_bits) { + unsigned a_mask =3D (1 << a_bits) - 1; + unsigned s_mask =3D (1 << s_bits) - 1; + tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask)); + t =3D TCG_REG_R0; + } + + /* Mask the address for the requested alignment. */ + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, + (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); + /* Zero-extend the address for use in the final address. */ + tcg_out_ext32u(s, TCG_REG_R4, addrlo); + addrlo =3D TCG_REG_R4; + } else if (a_bits =3D=3D 0) { + tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS= ); + } else { + tcg_out_rld(s, RLDICL, TCG_REG_R0, t, + 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits); + tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BIT= S, 0); + } + } + h->index =3D addrlo; + + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, + 0, 7, TCG_TYPE_I32); + tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32= ); + tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); + } else { + tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, + 0, 7, TCG_TYPE_TL); + } + + /* Load a pointer into the current opcode w/conditional branch-link. */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); +#else + if (a_bits) { + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + /* We are expecting a_bits to max out at 7, much lower than ANDI. = */ + tcg_debug_assert(a_bits < 16); + tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, (1 << a_bits) - 1)); + + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK); + } + + h->base =3D guest_base ? TCG_GUEST_BASE_REG : 0; + h->index =3D addrlo; + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); + h->index =3D TCG_REG_TMP1; + } +#endif + + return ldst; +} + static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - tcg_insn_unit *label_ptr; + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, true); =20 - h.index =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), t= rue); - h.base =3D TCG_REG_R3; - - /* Load a pointer into the current opcode w/conditional branch-link. */ - label_ptr =3D s->code_ptr; - tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); -#else /* !CONFIG_SOFTMMU */ - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); - } - h.base =3D guest_base ? TCG_GUEST_BASE_REG : 0; - h.index =3D addrlo; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); - h.index =3D TCG_REG_TMP1; - } -#endif - - if (TCG_TARGET_REG_BITS =3D=3D 32 && s_bits =3D=3D MO_64) { + if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { if (opc & MO_BSWAP) { tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); @@ -2357,10 +2332,12 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, } } =20 -#ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#endif + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); + } } =20 static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, @@ -2368,32 +2345,12 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - tcg_insn_unit *label_ptr; + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, false); =20 - h.index =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), f= alse); - h.base =3D TCG_REG_R3; - - /* Load a pointer into the current opcode w/conditional branch-link. */ - label_ptr =3D s->code_ptr; - tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); -#else /* !CONFIG_SOFTMMU */ - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); - } - h.base =3D guest_base ? TCG_GUEST_BASE_REG : 0; - h.index =3D addrlo; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); - h.index =3D TCG_REG_TMP1; - } -#endif - - if (TCG_TARGET_REG_BITS =3D=3D 32 && s_bits =3D=3D MO_64) { + if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { if (opc & MO_BSWAP) { tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); @@ -2418,10 +2375,12 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, } } =20 -#ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#endif + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); + } } =20 static void tcg_out_nop_fill(tcg_insn_unit *p, int count) --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683358123; cv=none; d=zohomail.com; s=zohoarc; b=Gp2ce7ft7UG0QI3aaSkZ7CR2jKlUstwCjW3QeKs0GJv+9L7BRQNUcwkw9uR3PMKO0VJP85GdwyWEszS5vItH4F/wF2ENkGWtqGazEdumK8jqNkQ0mDQyHKe4LKuqAXF3c1yQOKNMnY6A8mb3JZ50JzUUd4bFQ7JfBTl/xBwuOD0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683358123; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=d+N50zI9kxk+jryuSplIHYSHO9fxLXxjXcTToUTMT0A=; b=ZVpCSc70wx6M/jxyytw2cMnxqKGomR1nRoV2CRtBJGmjtsWc5DkiOTmsgA1M7jbkmJvtiHCi8znl4N4axXWpVMbt6lXhLQrZsvnynca1lyEdAZuQDgZkKTpg05xTnGtw17gruU5JX0eVyfWvsRbtMIm91dWL0IWOKzi5AP1DCMQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683358123248494.1105989491957; Sat, 6 May 2023 00:28:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCFp-00047D-Sn; Sat, 06 May 2023 03:22:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCFo-000432-B2 for qemu-devel@nongnu.org; Sat, 06 May 2023 03:22:52 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFg-0004Kg-5u for qemu-devel@nongnu.org; Sat, 06 May 2023 03:22:52 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-3f19a80a330so17360825e9.2 for ; Sat, 06 May 2023 00:22:43 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357763; x=1685949763; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d+N50zI9kxk+jryuSplIHYSHO9fxLXxjXcTToUTMT0A=; b=MF1k6Xgxn5BAIgJFvE5TKdSsWUDs6LnvZtoc1K+wk+dm/0dGRw98BVPCYqVkRfpP5m Zpgxhd996b5PZbTPe4Av6OWhVX6vx+V7RDXApmQUxrDtu2+kkAbDjSxmfm4MV3vT3voo xcoJaQtFGC072mf5bdf2moBK0rGy8zwEhDHXIVwN4rR41Aft8jXahvGDHrbqWbHMl4S9 KT5RHw4SpM9q7E/8P/T448YNj1yQ5jvt0pJHVUjqp8uIr7FFkL4Kbdp8GF7wF9tYq5Y3 xVX9sjkQ6gNiZeS9AXShKT1Bh94mKCh3W1RrK1Vmlt+h3puLCt8v0EXpJqet7lC7tuxW OUzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357763; x=1685949763; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d+N50zI9kxk+jryuSplIHYSHO9fxLXxjXcTToUTMT0A=; b=hqJwr3LJZsAaRpFKsE+ogqDBujQhfQ3Pczb+K+1rXWknz99xSjmjm/ij+xX29eGnP3 X5Gfhs6+iPw0NEZPqcTi8eNCLoEgG84eIRNMMMA5Ll7zp3m7M+NT6WIVOWs7rJM9iVu1 IpRedI0skhR63i9HE1WsFavvKlPlM9yIgPXQizNvvALYkySujlXl7bXOtbYN5lqycNQt ToSclBSJNa26+AOJpX9T9Mmgs+ICkRRYR659zUK/A/ykSFl6tvEjUSXMgu/0vQ2FAKCB JwRojhkFf2hgNyECqBbEhI4ayeg7NS3gDcquq7V6ERawXE27rrW+3xyOzu66EW3HaPEd ru2w== X-Gm-Message-State: AC+VfDzzurBRXALq/mkE0Ad4jdVU9vf6gCxfAtut22X+0LrQXrscVi27 ysQsLHK4A9bjWmjSmVa2D7tR3mbqYSpYesYulm0PHA== X-Google-Smtp-Source: ACHHUZ5iSYHCKrJGqJ+Ok58DbuQ2L3857Q0sDCnPgtBIhM5JhLvvBWlGHddh1mKh1gANuODpwhu+og== X-Received: by 2002:adf:d092:0:b0:306:31fb:1c3d with SMTP id y18-20020adfd092000000b0030631fb1c3dmr2683879wrh.32.1683357763160; Sat, 06 May 2023 00:22:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 08/30] tcg/riscv: Introduce prepare_host_addr Date: Sat, 6 May 2023 08:22:13 +0100 Message-Id: <20230506072235.597467-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683358125474100003 Content-Type: text/plain; charset="utf-8" Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns TCGReg and TCGLabelQemuLdst. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/riscv/tcg-target.c.inc | 253 +++++++++++++++++-------------------- 1 file changed, 114 insertions(+), 139 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index a4cf60ca75..2b2d313fe2 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -899,10 +899,6 @@ static void * const qemu_st_helpers[MO_SIZE + 1] =3D { #endif }; =20 -/* We expect to use a 12-bit negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); - static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) { tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); @@ -910,76 +906,6 @@ static void tcg_out_goto(TCGContext *s, const tcg_insn= _unit *target) tcg_debug_assert(ok); } =20 -static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, MemOpIdx oi, - tcg_insn_unit **label_ptr, bool is_load) -{ - MemOp opc =3D get_memop(oi); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_bits =3D get_alignment_bits(opc); - tcg_target_long compare_mask; - int mem_index =3D get_mmuidx(oi); - int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); - int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); - int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); - TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; - - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs); - - tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); - - /* Load the tlb comparator and the addend. */ - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, - is_load ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, - offsetof(CPUTLBEntry, addend)); - - /* We don't support unaligned accesses. */ - if (a_bits < s_bits) { - a_bits =3D s_bits; - } - /* Clear the non-page, non-alignment bits from the address. */ - compare_mask =3D (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - = 1); - if (compare_mask =3D=3D sextreg(compare_mask, 0, 12)) { - tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr, compare_mask); - } else { - tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); - tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr); - } - - /* Compare masked address with the TLB entry. */ - label_ptr[0] =3D s->code_ptr; - tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); - - /* TLB Hit - translate address using addend. */ - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_TMP0, addr); - addr =3D TCG_REG_TMP0; - } - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addr); - return TCG_REG_TMP0; -} - -static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, - TCGType data_type, TCGReg data_reg, - TCGReg addr_reg, void *raddr, - tcg_insn_unit **label_ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D data_type; - label->datalo_reg =3D data_reg; - label->addrlo_reg =3D addr_reg; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr[0]; -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { MemOpIdx oi =3D l->oi; @@ -1037,26 +963,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) return true; } #else - -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_= reg, - unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *l =3D new_ldst_label(s); - - l->is_ld =3D is_ld; - l->addrlo_reg =3D addr_reg; - - /* We are expecting a_bits to max out at 7, so we can always use andi.= */ - tcg_debug_assert(a_bits < 12); - tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask); - - l->label_ptr[0] =3D s->code_ptr; - tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0); - - l->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { /* resolve label address */ @@ -1083,9 +989,108 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) { return tcg_out_fail_alignment(s, l); } - #endif /* CONFIG_SOFTMMU */ =20 +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, + TCGReg addr_reg, MemOpIdx oi, + bool is_ld) +{ + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned a_mask =3D (1u << a_bits) - 1; + +#ifdef CONFIG_SOFTMMU + unsigned s_bits =3D opc & MO_SIZE; + int mem_index =3D get_mmuidx(oi); + int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); + int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); + TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; + tcg_target_long compare_mask; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs); + + tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr_reg, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); + + /* Load the tlb comparator and the addend. */ + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, + is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, + offsetof(CPUTLBEntry, addend)); + + /* We don't support unaligned accesses. */ + if (a_bits < s_bits) { + a_bits =3D s_bits; + } + /* Clear the non-page, non-alignment bits from the address. */ + compare_mask =3D (tcg_target_long)TARGET_PAGE_MASK | a_mask; + if (compare_mask =3D=3D sextreg(compare_mask, 0, 12)) { + tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, compare_mask); + } else { + tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); + tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr_reg); + } + + /* Compare masked address with the TLB entry. */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); + + /* TLB Hit - translate address using addend. */ + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg); + addr_reg =3D TCG_REG_TMP0; + } + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addr_reg); + *pbase =3D TCG_REG_TMP0; +#else + if (a_mask) { + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + /* We are expecting a_bits max 7, so we can always use andi. */ + tcg_debug_assert(a_bits < 12); + tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask); + + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0); + } + + TCGReg base =3D addr_reg; + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_ext32u(s, TCG_REG_TMP0, base); + base =3D TCG_REG_TMP0; + } + if (guest_base !=3D 0) { + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base= ); + base =3D TCG_REG_TMP0; + } + *pbase =3D base; +#endif + + return ldst; +} + static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val, TCGReg base, MemOp opc, TCGType type) { @@ -1125,32 +1130,17 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg val, static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; TCGReg base; =20 -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[1]; + ldst =3D prepare_host_addr(s, &base, addr_reg, oi, true); + tcg_out_qemu_ld_direct(s, data_reg, base, get_memop(oi), data_type); =20 - base =3D tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1); - tcg_out_qemu_ld_direct(s, data_reg, base, opc, data_type); - add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, true, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - base =3D addr_reg; - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_TMP0, base); - base =3D TCG_REG_TMP0; - } - if (guest_base !=3D 0) { - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base= ); - base =3D TCG_REG_TMP0; - } - tcg_out_qemu_ld_direct(s, data_reg, base, opc, data_type); -#endif } =20 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg val, @@ -1180,32 +1170,17 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg val, static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; TCGReg base; =20 -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[1]; + ldst =3D prepare_host_addr(s, &base, addr_reg, oi, false); + tcg_out_qemu_st_direct(s, data_reg, base, get_memop(oi)); =20 - base =3D tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0); - tcg_out_qemu_st_direct(s, data_reg, base, opc); - add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, false, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - base =3D addr_reg; - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_TMP0, base); - base =3D TCG_REG_TMP0; - } - if (guest_base !=3D 0) { - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base= ); - base =3D TCG_REG_TMP0; - } - tcg_out_qemu_st_direct(s, data_reg, base, opc); -#endif } =20 static const tcg_insn_unit *tb_ret_addr; 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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357764; x=1685949764; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/+D3flHoA+lO9qFOAJD5/z5k4A1tFbbT3jeq7/jtxrQ=; b=yGvhL1E6195MFnoDw6ipjhBFWnd3Ms+fRiAJ3YP8ZgaZ1yMeysXAxqqRkymm1hZ0bq SC/RITQ9rQZ+4sEY6LAz0ijJMOudCs1JiEy05Spaf4g1MG1QJEZRg+r8lrXOI9YMfh3k klK9M9hD0e08Yj1ylkAmjnv/ITZEBgwbU3fHzIfl09XTLyF3oPTkEXiGfS2Jyj56UA1n vMwXs7Ggu2s/uOIioXT50YzeMsNIPYvqypvRK2dSOhJ6Tz6Hgq0V5Gf45Ya+fJljxHJ+ V/jrvP4SLDc38d3lecHgQf2OnAidOhwWkQoqadtdPexxOq3SWX9tTcDvGPIB4JmglwkA Mytw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357764; x=1685949764; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/+D3flHoA+lO9qFOAJD5/z5k4A1tFbbT3jeq7/jtxrQ=; b=gwWH9VklTo+sn92eQdbnUkwCMiAVBs/rV4t4TCO6jfvtj0jgKR0U4Ka399pr5HnyDn 6gXkt4tkArNwfE4dgizasZ+43+/Q7VYSutEjCl294tz2hI/lwaeYnXRwi5q/C/ehNWRn Oj/Ygn2Ne07M2b+e98paj8NY/wWfcMSWD0pV7+Q0uXC8y/rErCu8BmxUWltegPKgM7/y ssJ60cNL07H6LB9jwhTqBEK1ksOylTeo6+a/GZBA1Ak0kDkT2mJCXJFyT34Te7iSz0vH AcTMDunxnYg6bZC037bUVHDwMwaZFyeJzeZ8SJUbkat9cJDHmufkqgDmAVKrJBt2JIfR QUxQ== X-Gm-Message-State: AC+VfDxbDg7/9cmo4EWUNF4frxHy74Li42D/Tls7Gs84Ctbme9hI1T7g wDzZZoq8x92zmaoVshAHn1Iihb5kUWzXeGFsasHzKA== X-Google-Smtp-Source: ACHHUZ7PGF0obSNe/C4q0PKv7+5zKb+UkBrOn7UC/eAsCKyHReqoWO6b1gsIcNMH3ZYIz/55qZXGbg== X-Received: by 2002:a5d:6112:0:b0:306:2e62:7716 with SMTP id v18-20020a5d6112000000b003062e627716mr2507523wrt.56.1683357763837; Sat, 06 May 2023 00:22:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 09/30] tcg/s390x: Introduce prepare_host_addr Date: Sat, 6 May 2023 08:22:14 +0100 Message-Id: <20230506072235.597467-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683358053193100005 Content-Type: text/plain; charset="utf-8" Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, tcg_prepare_user_ldst, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/s390x/tcg-target.c.inc | 263 ++++++++++++++++--------------------- 1 file changed, 113 insertions(+), 150 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index da7ee5b085..c3157d22be 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1718,78 +1718,6 @@ static void tcg_out_qemu_st_direct(TCGContext *s, Me= mOp opc, TCGReg data, } =20 #if defined(CONFIG_SOFTMMU) -/* We're expecting to use a 20-bit negative offset on the tlb memory ops. = */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); - -/* Load and compare a TLB entry, leaving the flags set. Loads the TLB - addend into R2. Returns a register with the santitized guest address. = */ -static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc, - int mem_index, bool is_ld) -{ - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_bits =3D get_alignment_bits(opc); - unsigned s_mask =3D (1 << s_bits) - 1; - unsigned a_mask =3D (1 << a_bits) - 1; - int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); - int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); - int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); - int ofs, a_off; - uint64_t tlb_mask; - - tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - tcg_out_insn(s, RXY, NG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, mask_off= ); - tcg_out_insn(s, RXY, AG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, table_of= f); - - /* For aligned accesses, we check the first byte and include the align= ment - bits within the address. For unaligned access, we check that we do= n't - cross pages using the address of the last byte of the access. */ - a_off =3D (a_bits >=3D s_bits ? 0 : s_mask - a_mask); - tlb_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; - if (a_off =3D=3D 0) { - tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask); - } else { - tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off); - tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask); - } - - if (is_ld) { - ofs =3D offsetof(CPUTLBEntry, addr_read); - } else { - ofs =3D offsetof(CPUTLBEntry, addr_write); - } - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_insn(s, RX, C, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs); - } else { - tcg_out_insn(s, RXY, CG, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs= ); - } - - tcg_out_insn(s, RXY, LG, TCG_REG_R2, TCG_REG_R2, TCG_REG_NONE, - offsetof(CPUTLBEntry, addend)); - - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_R3, addr_reg); - return TCG_REG_R3; - } - return addr_reg; -} - -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, - TCGType type, TCGReg data, TCGReg addr, - tcg_insn_unit *raddr, tcg_insn_unit *label= _ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D type; - label->datalo_reg =3D data; - label->addrlo_reg =3D addr; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr; -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGReg addr_reg =3D lb->addrlo_reg; @@ -1842,26 +1770,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) return true; } #else -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, - TCGReg addrlo, unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *l =3D new_ldst_label(s); - - l->is_ld =3D is_ld; - l->addrlo_reg =3D addrlo; - - /* We are expecting a_bits to max out at 7, much lower than TMLL. */ - tcg_debug_assert(a_bits < 16); - tcg_out_insn(s, RI, TMLL, addrlo, a_mask); - - tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */ - l->label_ptr[0] =3D s->code_ptr; - s->code_ptr +=3D 1; - - l->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { if (!patch_reloc(l->label_ptr[0], R_390_PC16DBL, @@ -1888,91 +1796,146 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *= s, TCGLabelQemuLdst *l) { return tcg_out_fail_alignment(s, l); } +#endif /* CONFIG_SOFTMMU */ =20 -static HostAddress tcg_prepare_user_ldst(TCGContext *s, TCGReg addr_reg) +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addr_reg, MemOpIdx oi, + bool is_ld) { - TCGReg index; - int disp; + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned a_mask =3D (1u << a_bits) - 1; =20 +#ifdef CONFIG_SOFTMMU + unsigned s_bits =3D opc & MO_SIZE; + unsigned s_mask =3D (1 << s_bits) - 1; + int mem_index =3D get_mmuidx(oi); + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); + int ofs, a_off; + uint64_t tlb_mask; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); + tcg_out_insn(s, RXY, NG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, mask_off= ); + tcg_out_insn(s, RXY, AG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, table_of= f); + + /* + * For aligned accesses, we check the first byte and include the align= ment + * bits within the address. For unaligned access, we check that we do= n't + * cross pages using the address of the last byte of the access. + */ + a_off =3D (a_bits >=3D s_bits ? 0 : s_mask - a_mask); + tlb_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; + if (a_off =3D=3D 0) { + tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask); + } else { + tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off); + tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask); + } + + if (is_ld) { + ofs =3D offsetof(CPUTLBEntry, addr_read); + } else { + ofs =3D offsetof(CPUTLBEntry, addr_write); + } + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_insn(s, RX, C, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs); + } else { + tcg_out_insn(s, RXY, CG, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs= ); + } + + tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); + ldst->label_ptr[0] =3D s->code_ptr++; + + h->index =3D TCG_REG_R2; + tcg_out_insn(s, RXY, LG, h->index, TCG_REG_R2, TCG_REG_NONE, + offsetof(CPUTLBEntry, addend)); + + h->base =3D addr_reg; + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_ext32u(s, TCG_REG_R3, addr_reg); + h->base =3D TCG_REG_R3; + } + h->disp =3D 0; +#else + if (a_mask) { + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + /* We are expecting a_bits to max out at 7, much lower than TMLL. = */ + tcg_debug_assert(a_bits < 16); + tcg_out_insn(s, RI, TMLL, addr_reg, a_mask); + + tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */ + ldst->label_ptr[0] =3D s->code_ptr++; + } + + h->base =3D addr_reg; if (TARGET_LONG_BITS =3D=3D 32) { tcg_out_ext32u(s, TCG_TMP0, addr_reg); - addr_reg =3D TCG_TMP0; + h->base =3D TCG_TMP0; } if (guest_base < 0x80000) { - index =3D TCG_REG_NONE; - disp =3D guest_base; + h->index =3D TCG_REG_NONE; + h->disp =3D guest_base; } else { - index =3D TCG_GUEST_BASE_REG; - disp =3D 0; + h->index =3D TCG_GUEST_BASE_REG; + h->disp =3D 0; } - return (HostAddress){ .base =3D addr_reg, .index =3D index, .disp =3D = disp }; +#endif + + return ldst; } -#endif /* CONFIG_SOFTMMU */ =20 static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - unsigned mem_index =3D get_mmuidx(oi); - tcg_insn_unit *label_ptr; + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, true); + tcg_out_qemu_ld_direct(s, get_memop(oi), data_reg, h); =20 - h.base =3D tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1); - h.index =3D TCG_REG_R2; - h.disp =3D 0; - - tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); - label_ptr =3D s->code_ptr; - s->code_ptr +=3D 1; - - tcg_out_qemu_ld_direct(s, opc, data_reg, h); - - add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - - if (a_bits) { - tcg_out_test_alignment(s, true, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - h =3D tcg_prepare_user_ldst(s, addr_reg); - tcg_out_qemu_ld_direct(s, opc, data_reg, h); -#endif } =20 static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - unsigned mem_index =3D get_mmuidx(oi); - tcg_insn_unit *label_ptr; + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, false); + tcg_out_qemu_st_direct(s, get_memop(oi), data_reg, h); =20 - h.base =3D tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0); - h.index =3D TCG_REG_R2; - h.disp =3D 0; - - tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); - label_ptr =3D s->code_ptr; - s->code_ptr +=3D 1; - - tcg_out_qemu_st_direct(s, opc, data_reg, h); - - add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - - if (a_bits) { - tcg_out_test_alignment(s, false, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - h =3D tcg_prepare_user_ldst(s, addr_reg); - tcg_out_qemu_st_direct(s, opc, data_reg, h); -#endif } =20 static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357764; x=1685949764; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EpNKtjukrxBUClWMH96nkUvfEjdZcfT2lF+ZcStO9U4=; b=tueaRiN4fJieAaYGxwaFK0iePnLT0oneiZ72nu0w43c4SW4wpnZ/Z8rjDtLdGUShuQ jHwfn41qpUBseIntlXdYb3Sbgfm47YDHdSbX6tausltRU80SRtpjO3TFffPJXrQCUxqm XNpC25AEvvj2yU1GPR6ioXw6qkz9DZ/xi52EFtcCVrEdmNf+zoAryJQRWywRGrzQHJ+j +U6jIPjS95zkbJ6YjD+q8900L0vPqm4dus0CeaTWPUF8aPlcY0DwYIx8zAezKUa2Cb53 zMEVWK2pdEt3/rveqfoDDw2jLKW/tZ5q0kTszdqLXNgngIJUUVDNqyWbyloTa+nA/Rm+ 31gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357764; x=1685949764; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EpNKtjukrxBUClWMH96nkUvfEjdZcfT2lF+ZcStO9U4=; b=Tww6osbEPvPEJgAlH0n8gbyIsLK3zteQ9/mGCj+rKB2eXdpcFPHySGnldMQoPYcEAU lhftBMH7ckV7LWLUEhLSkimXXwlaPHRyQ6/4PcbPIXZ5ye+GzhQfB1n1uw1ZvIwxo0IX hDIskxZn2HYkwRRobzL1DBs+9zYBcurBhJuErTNqxhT11/X/9NDotB6LR7KNMXiaEQxy CGnklsR1tvI+durvJkUHv78IpfymrcGHqnz7oT6IrNUh3Y8VBiXBuhLIbwW/8ck+0E4G tMfJ5WLeM9aAABJnTcXlYzoFHP/tksZGVrNz5CwT/c0VCJvSqGAqS3X2+j+ckedocJKB 2wdw== X-Gm-Message-State: AC+VfDzAAICkCSupXNyZKZyZuPLkt3yJ7CSA0d6rCM7DDfmiFBXSq0/t j3Df4HXVFhJBvY+2sGvRVKbFLoVBY2ldP66Hbma++A== X-Google-Smtp-Source: ACHHUZ4sM3lZ/0LYYnD9au/Mb4e6vI/rPNaCnguJ8nCKmgpuxRUNG6DBqK2kZNY++oCW9aiDZDtk4w== X-Received: by 2002:adf:e904:0:b0:306:2d81:341d with SMTP id f4-20020adfe904000000b003062d81341dmr6447921wrm.24.1683357764601; Sat, 06 May 2023 00:22:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 10/30] tcg: Add routines for calling slow-path helpers Date: Sat, 6 May 2023 08:22:15 +0100 Message-Id: <20230506072235.597467-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683357946484100003 Content-Type: text/plain; charset="utf-8" Add tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. These and their subroutines use the existing knowledge of the host function call abi to load the function call arguments and return results. These will be used to simplify the backends in turn. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tcg.c | 456 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 453 insertions(+), 3 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 057423c121..748be8426a 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -181,6 +181,22 @@ static bool tcg_target_const_match(int64_t val, TCGTyp= e type, int ct); static int tcg_out_ldst_finalize(TCGContext *s); #endif =20 +typedef struct TCGLdstHelperParam { + TCGReg (*ra_gen)(TCGContext *s, const TCGLabelQemuLdst *l, int arg_reg= ); + unsigned ntmp; + int tmp[3]; +} TCGLdstHelperParam; + +static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *= l, + const TCGLdstHelperParam *p) + __attribute__((unused)); +static void tcg_out_ld_helper_ret(TCGContext *s, const TCGLabelQemuLdst *l, + bool load_sign, const TCGLdstHelperParam= *p) + __attribute__((unused)); +static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *= l, + const TCGLdstHelperParam *p) + __attribute__((unused)); + TCGContext tcg_init_ctx; __thread TCGContext *tcg_ctx; =20 @@ -459,9 +475,8 @@ static void tcg_out_movext1(TCGContext *s, const TCGMov= Extend *i) * between the sources and destinations. */ =20 -static void __attribute__((unused)) -tcg_out_movext2(TCGContext *s, const TCGMovExtend *i1, - const TCGMovExtend *i2, int scratch) +static void tcg_out_movext2(TCGContext *s, const TCGMovExtend *i1, + const TCGMovExtend *i2, int scratch) { TCGReg src1 =3D i1->src; TCGReg src2 =3D i2->src; @@ -715,6 +730,50 @@ static TCGHelperInfo all_helpers[] =3D { }; static GHashTable *helper_table; =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 +# define dh_typecode_ttl dh_typecode_i32 +#else +# define dh_typecode_ttl dh_typecode_i64 +#endif + +static TCGHelperInfo info_helper_ld32_mmu =3D { + .flags =3D TCG_CALL_NO_WG, + .typemask =3D dh_typemask(ttl, 0) /* return tcg_target_ulong */ + | dh_typemask(env, 1) + | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i32, 3) /* unsigned oi */ + | dh_typemask(ptr, 4) /* uintptr_t ra */ +}; + +static TCGHelperInfo info_helper_ld64_mmu =3D { + .flags =3D TCG_CALL_NO_WG, + .typemask =3D dh_typemask(i64, 0) /* return uint64_t */ + | dh_typemask(env, 1) + | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i32, 3) /* unsigned oi */ + | dh_typemask(ptr, 4) /* uintptr_t ra */ +}; + +static TCGHelperInfo info_helper_st32_mmu =3D { + .flags =3D TCG_CALL_NO_WG, + .typemask =3D dh_typemask(void, 0) + | dh_typemask(env, 1) + | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i32, 3) /* uint32_t data */ + | dh_typemask(i32, 4) /* unsigned oi */ + | dh_typemask(ptr, 5) /* uintptr_t ra */ +}; + +static TCGHelperInfo info_helper_st64_mmu =3D { + .flags =3D TCG_CALL_NO_WG, + .typemask =3D dh_typemask(void, 0) + | dh_typemask(env, 1) + | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i64, 3) /* uint64_t data */ + | dh_typemask(i32, 4) /* unsigned oi */ + | dh_typemask(ptr, 5) /* uintptr_t ra */ +}; + #ifdef CONFIG_TCG_INTERPRETER static ffi_type *typecode_to_ffi(int argmask) { @@ -1126,6 +1185,11 @@ static void tcg_context_init(unsigned max_cpus) (gpointer)&all_helpers[i]); } =20 + init_call_layout(&info_helper_ld32_mmu); + init_call_layout(&info_helper_ld64_mmu); + init_call_layout(&info_helper_st32_mmu); + init_call_layout(&info_helper_st64_mmu); + #ifdef CONFIG_TCG_INTERPRETER init_ffi_layouts(); #endif @@ -5011,6 +5075,392 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp= *op) } } =20 +/* + * Similarly for qemu_ld/st slow path helpers. + * We must re-implement tcg_gen_callN and tcg_reg_alloc_call simultaneousl= y, + * using only the provided backend tcg_out_* functions. + */ + +static int tcg_out_helper_stk_ofs(TCGType type, unsigned slot) +{ + int ofs =3D arg_slot_stk_ofs(slot); + + /* + * Each stack slot is TCG_TARGET_LONG_BITS. If the host does not + * require extension to uint64_t, adjust the address for uint32_t. + */ + if (HOST_BIG_ENDIAN && + TCG_TARGET_REG_BITS =3D=3D 64 && + type =3D=3D TCG_TYPE_I32) { + ofs +=3D 4; + } + return ofs; +} + +static void tcg_out_helper_load_regs(TCGContext *s, + unsigned nmov, TCGMovExtend *mov, + unsigned ntmp, const int *tmp) +{ + switch (nmov) { + default: + /* The backend must have provided enough temps for the worst case.= */ + tcg_debug_assert(ntmp + 1 >=3D nmov); + + for (unsigned i =3D nmov - 1; i >=3D 2; --i) { + TCGReg dst =3D mov[i].dst; + + for (unsigned j =3D 0; j < i; ++j) { + if (dst =3D=3D mov[j].src) { + /* + * Conflict. + * Copy the source to a temporary, recurse for the + * remaining moves, perform the extension from our + * scratch on the way out. + */ + TCGReg scratch =3D tmp[--ntmp]; + tcg_out_mov(s, mov[i].src_type, scratch, mov[i].src); + mov[i].src =3D scratch; + + tcg_out_helper_load_regs(s, i, mov, ntmp, tmp); + tcg_out_movext1(s, &mov[i]); + return; + } + } + + /* No conflicts: perform this move and continue. */ + tcg_out_movext1(s, &mov[i]); + } + /* fall through for the final two moves */ + + case 2: + tcg_out_movext2(s, mov, mov + 1, ntmp ? tmp[0] : -1); + return; + case 1: + tcg_out_movext1(s, mov); + return; + case 0: + g_assert_not_reached(); + } +} + +static void tcg_out_helper_load_slots(TCGContext *s, + unsigned nmov, TCGMovExtend *mov, + const TCGLdstHelperParam *parm) +{ + unsigned i; + + /* + * Start from the end, storing to the stack first. + * This frees those registers, so we need not consider overlap. + */ + for (i =3D nmov; i-- > 0; ) { + unsigned slot =3D mov[i].dst; + + if (arg_slot_reg_p(slot)) { + goto found_reg; + } + + TCGReg src =3D mov[i].src; + TCGType dst_type =3D mov[i].dst_type; + MemOp dst_mo =3D dst_type =3D=3D TCG_TYPE_I32 ? MO_32 : MO_64; + + /* The argument is going onto the stack; extend into scratch. */ + if ((mov[i].src_ext & MO_SIZE) !=3D dst_mo) { + tcg_debug_assert(parm->ntmp !=3D 0); + mov[i].dst =3D src =3D parm->tmp[0]; + tcg_out_movext1(s, &mov[i]); + } + + tcg_out_st(s, dst_type, src, TCG_REG_CALL_STACK, + tcg_out_helper_stk_ofs(dst_type, slot)); + } + return; + + found_reg: + /* + * The remaining arguments are in registers. + * Convert slot numbers to argument registers. + */ + nmov =3D i + 1; + for (i =3D 0; i < nmov; ++i) { + mov[i].dst =3D tcg_target_call_iarg_regs[mov[i].dst]; + } + tcg_out_helper_load_regs(s, nmov, mov, parm->ntmp, parm->tmp); +} + +static void tcg_out_helper_load_imm(TCGContext *s, unsigned slot, + TCGType type, tcg_target_long imm, + const TCGLdstHelperParam *parm) +{ + if (arg_slot_reg_p(slot)) { + tcg_out_movi(s, type, tcg_target_call_iarg_regs[slot], imm); + } else { + int ofs =3D tcg_out_helper_stk_ofs(type, slot); + if (!tcg_out_sti(s, type, imm, TCG_REG_CALL_STACK, ofs)) { + tcg_debug_assert(parm->ntmp !=3D 0); + tcg_out_movi(s, type, parm->tmp[0], imm); + tcg_out_st(s, type, parm->tmp[0], TCG_REG_CALL_STACK, ofs); + } + } +} + +static void tcg_out_helper_load_common_args(TCGContext *s, + const TCGLabelQemuLdst *ldst, + const TCGLdstHelperParam *parm, + const TCGHelperInfo *info, + unsigned next_arg) +{ + TCGMovExtend ptr_mov =3D { + .dst_type =3D TCG_TYPE_PTR, + .src_type =3D TCG_TYPE_PTR, + .src_ext =3D sizeof(void *) =3D=3D 4 ? MO_32 : MO_64 + }; + const TCGCallArgumentLoc *loc =3D &info->in[0]; + TCGType type; + unsigned slot; + tcg_target_ulong imm; + + /* + * Handle env, which is always first. + */ + ptr_mov.dst =3D loc->arg_slot; + ptr_mov.src =3D TCG_AREG0; + tcg_out_helper_load_slots(s, 1, &ptr_mov, parm); + + /* + * Handle oi. + */ + imm =3D ldst->oi; + loc =3D &info->in[next_arg]; + type =3D TCG_TYPE_I32; + switch (loc->kind) { + case TCG_CALL_ARG_NORMAL: + break; + case TCG_CALL_ARG_EXTEND_U: + case TCG_CALL_ARG_EXTEND_S: + /* No extension required for MemOpIdx. */ + tcg_debug_assert(imm <=3D INT32_MAX); + type =3D TCG_TYPE_REG; + break; + default: + g_assert_not_reached(); + } + tcg_out_helper_load_imm(s, loc->arg_slot, type, imm, parm); + next_arg++; + + /* + * Handle ra. + */ + loc =3D &info->in[next_arg]; + slot =3D loc->arg_slot; + if (parm->ra_gen) { + int arg_reg =3D -1; + TCGReg ra_reg; + + if (arg_slot_reg_p(slot)) { + arg_reg =3D tcg_target_call_iarg_regs[slot]; + } + ra_reg =3D parm->ra_gen(s, ldst, arg_reg); + + ptr_mov.dst =3D slot; + ptr_mov.src =3D ra_reg; + tcg_out_helper_load_slots(s, 1, &ptr_mov, parm); + } else { + imm =3D (uintptr_t)ldst->raddr; + tcg_out_helper_load_imm(s, slot, TCG_TYPE_PTR, imm, parm); + } +} + +static unsigned tcg_out_helper_add_mov(TCGMovExtend *mov, + const TCGCallArgumentLoc *loc, + TCGType dst_type, TCGType src_type, + TCGReg lo, TCGReg hi) +{ + if (dst_type <=3D TCG_TYPE_REG) { + MemOp src_ext; + + switch (loc->kind) { + case TCG_CALL_ARG_NORMAL: + src_ext =3D src_type =3D=3D TCG_TYPE_I32 ? MO_32 : MO_64; + break; + case TCG_CALL_ARG_EXTEND_U: + dst_type =3D TCG_TYPE_REG; + src_ext =3D MO_UL; + break; + case TCG_CALL_ARG_EXTEND_S: + dst_type =3D TCG_TYPE_REG; + src_ext =3D MO_SL; + break; + default: + g_assert_not_reached(); + } + + mov[0].dst =3D loc->arg_slot; + mov[0].dst_type =3D dst_type; + mov[0].src =3D lo; + mov[0].src_type =3D src_type; + mov[0].src_ext =3D src_ext; + return 1; + } + + assert(TCG_TARGET_REG_BITS =3D=3D 32); + + mov[0].dst =3D loc[HOST_BIG_ENDIAN].arg_slot; + mov[0].src =3D lo; + mov[0].dst_type =3D TCG_TYPE_I32; + mov[0].src_type =3D TCG_TYPE_I32; + mov[0].src_ext =3D MO_32; + + mov[1].dst =3D loc[!HOST_BIG_ENDIAN].arg_slot; + mov[1].src =3D hi; + mov[1].dst_type =3D TCG_TYPE_I32; + mov[1].src_type =3D TCG_TYPE_I32; + mov[1].src_ext =3D MO_32; + + return 2; +} + +static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *= ldst, + const TCGLdstHelperParam *parm) +{ + const TCGHelperInfo *info; + const TCGCallArgumentLoc *loc; + TCGMovExtend mov[2]; + unsigned next_arg, nmov; + MemOp mop =3D get_memop(ldst->oi); + + switch (mop & MO_SIZE) { + case MO_8: + case MO_16: + case MO_32: + info =3D &info_helper_ld32_mmu; + break; + case MO_64: + info =3D &info_helper_ld64_mmu; + break; + default: + g_assert_not_reached(); + } + + /* Defer env argument. */ + next_arg =3D 1; + + loc =3D &info->in[next_arg]; + nmov =3D tcg_out_helper_add_mov(mov, loc, TCG_TYPE_TL, TCG_TYPE_TL, + ldst->addrlo_reg, ldst->addrhi_reg); + next_arg +=3D nmov; + + tcg_out_helper_load_slots(s, nmov, mov, parm); + + /* No special attention for 32 and 64-bit return values. */ + tcg_debug_assert(info->out_kind =3D=3D TCG_CALL_RET_NORMAL); + + tcg_out_helper_load_common_args(s, ldst, parm, info, next_arg); +} + +static void tcg_out_ld_helper_ret(TCGContext *s, const TCGLabelQemuLdst *l= dst, + bool load_sign, + const TCGLdstHelperParam *parm) +{ + TCGMovExtend mov[2]; + + if (ldst->type <=3D TCG_TYPE_REG) { + MemOp mop =3D get_memop(ldst->oi); + + mov[0].dst =3D ldst->datalo_reg; + mov[0].src =3D tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, 0); + mov[0].dst_type =3D ldst->type; + mov[0].src_type =3D TCG_TYPE_REG; + + /* + * If load_sign, then we allowed the helper to perform the + * appropriate sign extension to tcg_target_ulong, and all + * we need now is a plain move. + * + * If they do not, then we expect the relevant extension + * instruction to be no more expensive than a move, and + * we thus save the icache etc by only using one of two + * helper functions. + */ + if (load_sign || !(mop & MO_SIGN)) { + if (TCG_TARGET_REG_BITS =3D=3D 32 || ldst->type =3D=3D TCG_TYP= E_I32) { + mov[0].src_ext =3D MO_32; + } else { + mov[0].src_ext =3D MO_64; + } + } else { + mov[0].src_ext =3D mop & MO_SSIZE; + } + tcg_out_movext1(s, mov); + } else { + assert(TCG_TARGET_REG_BITS =3D=3D 32); + + mov[0].dst =3D ldst->datalo_reg; + mov[0].src =3D + tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, HOST_BIG_ENDIAN); + mov[0].dst_type =3D TCG_TYPE_I32; + mov[0].src_type =3D TCG_TYPE_I32; + mov[0].src_ext =3D MO_32; + + mov[1].dst =3D ldst->datahi_reg; + mov[1].src =3D + tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, !HOST_BIG_ENDIAN= ); + mov[1].dst_type =3D TCG_TYPE_REG; + mov[1].src_type =3D TCG_TYPE_REG; + mov[1].src_ext =3D MO_32; + + tcg_out_movext2(s, mov, mov + 1, parm->ntmp ? parm->tmp[0] : -1); + } +} + +static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *= ldst, + const TCGLdstHelperParam *parm) +{ + const TCGHelperInfo *info; + const TCGCallArgumentLoc *loc; + TCGMovExtend mov[4]; + TCGType data_type; + unsigned next_arg, nmov, n; + MemOp mop =3D get_memop(ldst->oi); + + switch (mop & MO_SIZE) { + case MO_8: + case MO_16: + case MO_32: + info =3D &info_helper_st32_mmu; + data_type =3D TCG_TYPE_I32; + break; + case MO_64: + info =3D &info_helper_st64_mmu; + data_type =3D TCG_TYPE_I64; + break; + default: + g_assert_not_reached(); + } + + /* Defer env argument. */ + next_arg =3D 1; + nmov =3D 0; + + /* Handle addr argument. */ + loc =3D &info->in[next_arg]; + n =3D tcg_out_helper_add_mov(mov, loc, TCG_TYPE_TL, TCG_TYPE_TL, + ldst->addrlo_reg, ldst->addrhi_reg); + next_arg +=3D n; + nmov +=3D n; + + /* Handle data argument. */ + loc =3D &info->in[next_arg]; + n =3D tcg_out_helper_add_mov(mov + nmov, loc, data_type, ldst->type, + ldst->datalo_reg, ldst->datahi_reg); + next_arg +=3D n; + nmov +=3D n; + tcg_debug_assert(nmov <=3D ARRAY_SIZE(mov)); + + tcg_out_helper_load_slots(s, nmov, mov, parm); + tcg_out_helper_load_common_args(s, ldst, parm, info, next_arg); +} + #ifdef CONFIG_PROFILER =20 /* avoid copy/paste errors */ --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683358066; cv=none; d=zohomail.com; s=zohoarc; b=muLh3fMVLeTF4oviKzLY3A/tFYBwWrzWvKk2vfz3dq6VZ1O/Z0NnzZDMiGNJWTKqMU0bfNOadvFwis0JeHLSvBYeRrXkynPzywI53dxfh/8i8rmfjQrNrnZHg2d2t7xI+EUi/meBjVdqq73TfUJVUMfEdxXFoNm1mtEl8Obx/ig= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683358066; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=THr56viFSCoeoB94R860jIkFCIZg6mn2iR9owpi8fGQ=; b=FaEk6I7bmvBrIiDHF0WSEN4oQ5w34lpXNgnhJv6lL5XX8B9+gu10RIA0vfjoxmABQ2PaDMy0G0qqvOMBwNuCYmLO8jWusvAT+sSIFFldufvHVx3TG3qnaOjKrSIhRc7guUnDDivCAH1uk7bj4cbaJ8r40RexMzTgGem90J8VKMI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168335806693980.32821935143932; Sat, 6 May 2023 00:27:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCFx-0004FX-1e; Sat, 06 May 2023 03:23:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCFu-0004De-Ny for qemu-devel@nongnu.org; Sat, 06 May 2023 03:22:58 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFi-0004Ov-Sd for qemu-devel@nongnu.org; Sat, 06 May 2023 03:22:58 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-3062db220a3so1730203f8f.0 for ; Sat, 06 May 2023 00:22:46 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357765; x=1685949765; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=THr56viFSCoeoB94R860jIkFCIZg6mn2iR9owpi8fGQ=; b=QK0nyFdf20rKj8/faaA2oXX7Hw9iwozrCy6cothIsU8RO3TGnobI0iQEYPNo7V5/1E O8ukSnJepTdGJG8O7ULfEH1lpWHH8KcxxyTqajBGbejuhFFeQiZ8WOc5lCnTdshdFw6J JrxXwpzYkWLWyr+vUkbcLVtnRxyVv9b6FSvlpltUSLkYBz8dI56/jGSC+Y4oZdIwA690 JPNBlydSEIh95UZKgbG6o9ar8a22WsSlvACfot41OWoId0bYyC3BIj2gXRRu4g7WYP9g bY3Ahkfjm2fzSZuwGAk9NMt6nAYOI7ZkMP9zPAPMwgQdS1BTA9mH6h5txynNdyr5MUCt 3SXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357765; x=1685949765; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=THr56viFSCoeoB94R860jIkFCIZg6mn2iR9owpi8fGQ=; b=Z13ZXtNYSAcAmXwU2gg1XMXkMl0QgLMqbMvdh3vmmWwO1XIIhct5QS+eCAFX9lJuAm enVZX2NWBh3NauXKnEb49CglksxDOpOUPzYBE7XEByL/7JTplU2YtBYFdwLCESGLzj50 ft9496GN26wTHVv1TgyG47mV3Oc1vbSCQ66ohBfDubUZ/Aml6Mwvari7rC0vx45oZKD4 f8pTfzbxbXhzOFaWB4JjS1iplbOgt7KwcifKPkgDe8k46QmjTQu3mMy7MVESToqiXH/c SZdZN+O5vhrAd8x/mEpMv2UoIj+heAczyvyToXYvPTFT1dpefhVohnE9m6Fc+FcMM4aw pR3Q== X-Gm-Message-State: AC+VfDyoPYJMqM63VQ8CYjv1Mt0yaOqG77E79ROr8MFuRzbBLhJrhaiW 77mpB6Oa4FCeNfEJf6j7lO6uqPNbfGfUUO6LPhMX0A== X-Google-Smtp-Source: ACHHUZ6anSL9I1FYOmyELFFy7sBxZ63WzDtJnWhfC3bH7EffKQU9J+MNegITM+loUJ3RHjtnc8Zk4A== X-Received: by 2002:a5d:4701:0:b0:306:31e0:964 with SMTP id y1-20020a5d4701000000b0030631e00964mr2690814wrq.55.1683357765228; Sat, 06 May 2023 00:22:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 11/30] tcg/i386: Convert tcg_out_qemu_ld_slow_path Date: Sat, 6 May 2023 08:22:16 +0100 Message-Id: <20230506072235.597467-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683358067776100001 Content-Type: text/plain; charset="utf-8" Use tcg_out_ld_helper_args and tcg_out_ld_helper_ret. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/i386/tcg-target.c.inc | 71 +++++++++++++++------------------------ 1 file changed, 28 insertions(+), 43 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 8752968af2..17ad3c5963 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1802,13 +1802,37 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_B= SWAP) + 1] =3D { [MO_BEUQ] =3D helper_be_stq_mmu, }; =20 +/* + * Because i686 has no register parameters and because x86_64 has xchg + * to handle addr/data register overlap, we have placed all input arguments + * before we need might need a scratch reg. + * + * Even then, a scratch is only needed for l->raddr. Rather than expose + * a general-purpose scratch when we don't actually know it's available, + * use the ra_gen hook to load into RAX if needed. + */ +#if TCG_TARGET_REG_BITS =3D=3D 64 +static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int ar= g) +{ + if (arg < 0) { + arg =3D TCG_REG_RAX; + } + tcg_out_movi(s, TCG_TYPE_PTR, arg, (uintptr_t)l->raddr); + return arg; +} +static const TCGLdstHelperParam ldst_helper_param =3D { + .ra_gen =3D ldst_ra_gen +}; +#else +static const TCGLdstHelperParam ldst_helper_param =3D { }; +#endif + /* * Generate code for the slow path for a load at the end of block */ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(l->oi); tcg_insn_unit **label_ptr =3D &l->label_ptr[0]; =20 /* resolve label address */ @@ -1817,49 +1841,10 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); } =20 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - int ofs =3D 0; - - tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); - ofs +=3D 4; - - tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - } - - tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs); - ofs +=3D 4; - - tcg_out_sti(s, TCG_TYPE_PTR, (uintptr_t)l->raddr, TCG_REG_ESP, ofs= ); - } else { - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); - tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], - l->addrlo_reg); - tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], oi); - tcg_out_movi(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[3], - (uintptr_t)l->raddr); - } - + tcg_out_ld_helper_args(s, l, &ldst_helper_param); tcg_out_branch(s, 1, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param); =20 - if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { - TCGMovExtend ext[2] =3D { - { .dst =3D l->datalo_reg, .dst_type =3D TCG_TYPE_I32, - .src =3D TCG_REG_EAX, .src_type =3D TCG_TYPE_I32, .src_ext = =3D MO_UL }, - { .dst =3D l->datahi_reg, .dst_type =3D TCG_TYPE_I32, - .src =3D TCG_REG_EDX, .src_type =3D TCG_TYPE_I32, .src_ext = =3D MO_UL }, - }; - tcg_out_movext2(s, &ext[0], &ext[1], -1); - } else { - tcg_out_movext(s, l->type, l->datalo_reg, - TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_EAX); - } - - /* Jump to the code corresponding to next IR of qemu_st */ tcg_out_jmp(s, l->raddr); return true; } --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683358052; cv=none; d=zohomail.com; s=zohoarc; b=BVp4lW+ERXZllifCcZoaZUDmMeMAJxHio41q2ILSyj15xhcSPp/583c2j0aHZaGi5kBT4iAFg83myABBzj+JvFDtNxJWwnDWRa/WS6fV20PKllaHhA7/mFEfcatjgZA496VEqTZXzrXQ5b++lMHWZ+QW8aworCuYDbDnL8IycFY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683358052; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ewFnkUTNHWv3ml5hxpEpLBAtom/3ry8DZlVZK1eg3mU=; b=hgpXeyD9tQteIk8Men/jFSWqa7aRvgTwYcdygfMuwNGTpJSC+PcLUPPN0/I4676VUzgLtf/RL7e74JqK2Q9931AHMsZ8VVvsSxzEmrIfNpJ5vYf/6/ik0u5mrA0yqquJgWyN1S5aISWOnD8ZbJpWku5D7SVxLwtQY89JylQuTso= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683358052374204.82798889159903; Sat, 6 May 2023 00:27:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCG1-0004Jm-J0; Sat, 06 May 2023 03:23:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCFy-0004H4-Mg for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:02 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFj-0004PM-L1 for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:02 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-304935cc79bso2431799f8f.2 for ; Sat, 06 May 2023 00:22:46 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357766; x=1685949766; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ewFnkUTNHWv3ml5hxpEpLBAtom/3ry8DZlVZK1eg3mU=; b=RxM8tUQepHAaXG7+z+hp0L22t5C3njaSNTpWmwvIiVAhO4vwATQ8PgWkF5kc1Bg9DU 5PMucKCIl3JhhnRFiqIp4X1Q6qvo2V2Zb2stZVZqK22u6B9kpTkEbDiWDOrwHlyVI3MN drvUqUqe/ar7HMDxbMuEjAn0puEYCidr8Hg2ysJKouzEU2foBkGIm1EgOjrPUwGPO5Wj iCh8zFWh4Kw5OOCVQrEiZXQFH7CcjjzmukSqdPY4luxspoZuvBnq9ylWxDGif9/ZYAcX KFCY2MJcjO2ULOYjxE2tYdN4FFVGip1Vxo5PB7YfA/AyYjkjCsp+d9UubexGRcB1letA kahQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357766; x=1685949766; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ewFnkUTNHWv3ml5hxpEpLBAtom/3ry8DZlVZK1eg3mU=; b=R2WmOg372oEXZEpnykSWvA+N6mYPuC9Qbxwv9W+Lmp3vEbp0yCsHJunwQXhqsV/h72 Tl8pQyNv/B8GV1lIcClk0NzSIJOT8vLUAwhARHMD7vVWnC6CZ4of9iMQL4V+T45LePDP ggm7Qcn/gKB621vt2koORBJdNKuM+dxfS7ZLKt6mkFfy7Demogtv17y8rsy7aJ3yOVfI NjCO+wPHMWOCqh+WAuMpcmAX03KEyCO7W+vPiNMKAadQvcY7KDrRub9YN1BgcJa3SFCr P8wO555HEiKZuuxlfvZyHd3p7wHgXglSrVM9AzIYORMtXvj2xwfZew8Rt2zgkr8wChAG XSXg== X-Gm-Message-State: AC+VfDxsoIFx+jUOPC+JZ9xfyo/ByKbWU3ZMlKmDVyML1EiTrnijMybQ or/7121aPe4xwOMcRYEM7XypnID3EP6RIJ66R2Kz5w== X-Google-Smtp-Source: ACHHUZ6I3c8w9jLaAObA9qvmFWWPtAorhKbMTqtSCNXk5LTRrwPo52TFhIosma+Z3jzcajRwmNBHnA== X-Received: by 2002:a05:6000:1250:b0:306:266a:2dc8 with SMTP id j16-20020a056000125000b00306266a2dc8mr3018315wrx.64.1683357765916; Sat, 06 May 2023 00:22:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 12/30] tcg/i386: Convert tcg_out_qemu_st_slow_path Date: Sat, 6 May 2023 08:22:17 +0100 Message-Id: <20230506072235.597467-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683358052632100001 Content-Type: text/plain; charset="utf-8" Use tcg_out_st_helper_args. This eliminates the use of a tail call to the store helper. This may or may not be an improvement, depending on the call/return branch prediction of the host microarchitecture. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/i386/tcg-target.c.inc | 57 +++------------------------------------ 1 file changed, 4 insertions(+), 53 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 17ad3c5963..7dbfcbd20f 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1854,11 +1854,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) */ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; + MemOp opc =3D get_memop(l->oi); tcg_insn_unit **label_ptr =3D &l->label_ptr[0]; - TCGReg retaddr; =20 /* resolve label address */ tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); @@ -1866,56 +1863,10 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); } =20 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - int ofs =3D 0; + tcg_out_st_helper_args(s, l, &ldst_helper_param); + tcg_out_branch(s, 1, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 - tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); - ofs +=3D 4; - - tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - } - - tcg_out_st(s, TCG_TYPE_I32, l->datalo_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - - if (s_bits =3D=3D MO_64) { - tcg_out_st(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - } - - tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs); - ofs +=3D 4; - - retaddr =3D TCG_REG_EAX; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, ofs); - } else { - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); - tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], - l->addrlo_reg); - tcg_out_mov(s, (s_bits =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - tcg_target_call_iarg_regs[2], l->datalo_reg); - tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], oi); - - if (ARRAY_SIZE(tcg_target_call_iarg_regs) > 4) { - retaddr =3D tcg_target_call_iarg_regs[4]; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - } else { - retaddr =3D TCG_REG_RAX; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, - TCG_TARGET_CALL_STACK_OFFSET); - } - } - - /* "Tail call" to the helper, with the return address back inline. */ - tcg_out_push(s, retaddr); - tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_jmp(s, l->raddr); return true; } #else --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683357962; cv=none; d=zohomail.com; s=zohoarc; b=bD2Z0gPkysHYhg9CjQ9H6da26nsQhprKuBdjTFFNphqc+h7A0Qcvfx6dLGcu/Hzlk4+NToYmo29Nm9L8pnNx6l7uQ9DwXauiiRw9UJMPW/ClJ8/CxkWPkQTsXjzMP2Q3ZBIPbe97itX42M4RpRCO7/HHKuPAoaH2ud5R9aHneGo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683357962; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5ZL038/Ng9nS/xr0DDxwNdtMDtu/OB6KUuAjmGyJXv0=; b=i/knKoN6PvoYnBKXbpB+TtWQ0WGMd5ClJX+b3tS0HPzfDlifBKFsbAxvY8pI80D6S+YblJAn0JLx+ZBalxt+uYHEm1N/+6KaS0zNYOqBfTGdDPTQGbr/tsSRgPFmQki6y79CT8boG2JWjZieqM1rjs44ekVdvfr+GCe4xhB22hg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683357962344297.3166874809199; Sat, 6 May 2023 00:26:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCG3-0004PL-AZ; Sat, 06 May 2023 03:23:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCG0-0004Id-Dt for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:04 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFk-0004Pr-28 for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:03 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-307664010fdso2158378f8f.0 for ; Sat, 06 May 2023 00:22:47 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357766; x=1685949766; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5ZL038/Ng9nS/xr0DDxwNdtMDtu/OB6KUuAjmGyJXv0=; b=M+6wIx4ufFFDyNBBxwZi6PDn2lYhS0nxtj3bybjAbzgfdds1n2WAnrne4zI6HVL9bJ ktI5h+OsQzV+GbA9eIXt9JJsp90HybxpBcfC29OW6SEkcHrfvLTHhga1xD4hzpzwJESX XJSHdDpTxCgQXzPDcJuZzeiG8S7Zkm5PwscDmlN6ctYvBFuP+hNEa3UascrQV1AAUiC+ LrNYxVTtzOp4UVI1nIk5Tj1mqdTnU3v/dFYwDKYzW8lVfq4ouEFutri/CxdZlCondqAa pRoR2nYozlp0k7facE+sXfM+UHHMtnJwl38lB6EqIQ0SiCZkVWctWTCGgL7DlNGjgdDj FlOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357766; x=1685949766; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5ZL038/Ng9nS/xr0DDxwNdtMDtu/OB6KUuAjmGyJXv0=; b=XsA08twqggkNKuFee3k8KsKvj9x7YD/niaiHcA0VI7AJrpl5kGhr+Hjcu3gopnlrcA maoVESqLbDP6BU0yHzQC52AwXM7j8Xxi0I5a6UFjmxi4vNk+Fh71jX2J3s/MF2X5qcMZ FQgq0z0aP8bpqQ8OvXPd5ZnHjmg7DhJLnFUIz0WkaZVID3X77wTCg9Jc/zS+US3z5eZC 24CfA1CkdKvvGUIwkZ0j8/Y+IKqN01/qrWmVl13N1EN2NFFlc8C+redOgrGEJ1C0wkeH 44/frn2H3i/wLYJ38RnD7XnpdNOnft3BI7o+QC1S8GlyoJ0GltU0oERgQB+MhAAKOcSb u7Aw== X-Gm-Message-State: AC+VfDwOTw1qjwWWnH14G0QTmSEqg1ms8ZJZ+VnaDrc9mwKzPnjsSWJC +yO9RjbOn3vY4PY2I4omlrad2FvxXiIw1Md/l7soog== X-Google-Smtp-Source: ACHHUZ7yvfevj8BirJdBj3h2OyetaisSeomREIkn7+BbYSV2eCaVHm94qGbEy7IC51RSMlEN/GQQFA== X-Received: by 2002:adf:f7d1:0:b0:306:45ff:b527 with SMTP id a17-20020adff7d1000000b0030645ffb527mr2536272wrq.45.1683357766625; Sat, 06 May 2023 00:22:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 13/30] tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path Date: Sat, 6 May 2023 08:22:18 +0100 Message-Id: <20230506072235.597467-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683357964326100003 Content-Type: text/plain; charset="utf-8" Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/aarch64/tcg-target.c.inc | 40 +++++++++++++++--------------------- 1 file changed, 16 insertions(+), 24 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 202b90c001..62dd22d73c 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1580,13 +1580,6 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext,= TCGReg d, } } =20 -static void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target) -{ - ptrdiff_t offset =3D tcg_pcrel_diff(s, target); - tcg_debug_assert(offset =3D=3D sextract64(offset, 0, 21)); - tcg_out_insn(s, 3406, ADR, rd, offset); -} - typedef struct { TCGReg base; TCGReg index; @@ -1627,47 +1620,46 @@ static void * const qemu_st_helpers[MO_SIZE + 1] = =3D { #endif }; =20 +static const TCGLdstHelperParam ldst_helper_param =3D { + .ntmp =3D 1, .tmp =3D { TCG_REG_TMP } +}; + static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc19(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); - tcg_out_mov(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X1, lb->addrlo_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, oi); - tcg_out_adr(s, TCG_REG_X3, lb->raddr); + tcg_out_ld_helper_args(s, lb, &ldst_helper_param); tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); - - tcg_out_movext(s, lb->type, lb->datalo_reg, - TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_X0); + tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); tcg_out_goto(s, lb->raddr); return true; } =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); - MemOp size =3D opc & MO_SIZE; + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc19(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); - tcg_out_mov(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X1, lb->addrlo_reg); - tcg_out_mov(s, size =3D=3D MO_64, TCG_REG_X2, lb->datalo_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, oi); - tcg_out_adr(s, TCG_REG_X4, lb->raddr); + tcg_out_st_helper_args(s, lb, &ldst_helper_param); tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE]); tcg_out_goto(s, lb->raddr); return true; } #else +static void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target) +{ + ptrdiff_t offset =3D tcg_pcrel_diff(s, target); + tcg_debug_assert(offset =3D=3D sextract64(offset, 0, 21)); + tcg_out_insn(s, 3406, ADR, rd, offset); +} + static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { if (!reloc_pc19(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357767; x=1685949767; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e67Crv76HZSCg/mw2UfCxuP3kRlNk2dyxOLXgebiI/I=; b=iZxhVXakRRXfproXTv2rEIQE74Fiz5rLfn1gC8aZ2FwEu20ThU+0vCw8UK3NdZalX4 zXtj0wIKfVeG84G8ywChuy36idl6xm2CHzhYPA43Fw35ajGSCGvUkyIipwchTtnSEorl yf5tp4ow9mI1W31VO2USJzSyQty5Pmx9xKxaAjZHZtycTAzICmzwjLk3cjSNmkV/s9Lx B2Shkp5olIkFgNWBwV/wggM1WPGyvH94Ho94nEaeByaVzEoVmiSG8dqyav7ZwKO9zvSJ jKR4TeILG7wiIZgKRHo/uxbADtChh+YlQCE5zfjfdJd9W7I5rep9INt7N6G4/fI+YzZ0 Nw2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357767; x=1685949767; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e67Crv76HZSCg/mw2UfCxuP3kRlNk2dyxOLXgebiI/I=; b=HRwehJfUcBlvOeS96Abi3CYRzzWsoUe9e0OIeMfblz1ctqbap5oqcjz/UZtqeL6Rfi cfJG9EnavJgpHj3bFVuyug+NY8zzcdpexqOy9xVeXNfhialy8DENXDegqps3mplMD9C+ WVV8pCmHKUdEtgbtjvXKgEocyYGnnKE/3aKahIjg2qD4IBYw6qc9c9GFi6O/1G8w7lcG Y8ACcpqhBs+dof+dRMpRnh1So5u2rq0iIBIw1a/UF7Ijlyl7/ehQM3cPmCJYqXX0n9Jx 2vlEV16j12TG3R8Vj+5x4Zt8eHvxCyukMJm69cZVBq+jyafUASnhKcOtAuu8BS1gwonp XVUQ== X-Gm-Message-State: AC+VfDzRD/KxQt+5Io7a5grs0qVapqnlAWFOShylq7ow2vHJiGWhTaZK V0IkYTnx/Pb9iSmE40ekjUBJKFlHFSmc1sGJso5aIQ== X-Google-Smtp-Source: ACHHUZ69bEIAZL2MDZ63P7MDjVako3ut7UM+ZzQCsTpmNnyBiOAk0GveR16ROr7h0uPwJBkk5N61eg== X-Received: by 2002:a5d:6606:0:b0:2ef:b123:46d9 with SMTP id n6-20020a5d6606000000b002efb12346d9mr2975191wru.3.1683357767248; Sat, 06 May 2023 00:22:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 14/30] tcg/arm: Convert tcg_out_qemu_{ld,st}_slow_path Date: Sat, 6 May 2023 08:22:19 +0100 Message-Id: <20230506072235.597467-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683357942444100003 Content-Type: text/plain; charset="utf-8" Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. This allows our local tcg_out_arg_* infrastructure to be removed. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/arm/tcg-target.c.inc | 140 +++++---------------------------------- 1 file changed, 18 insertions(+), 122 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index c744512778..df514e56fc 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -690,8 +690,8 @@ tcg_out_ldrd_rwb(TCGContext *s, ARMCond cond, TCGReg rt= , TCGReg rn, TCGReg rm) tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 1); } =20 -static void tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, int imm8) +static void __attribute__((unused)) +tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); } @@ -969,28 +969,16 @@ static void tcg_out_ext8u(TCGContext *s, TCGReg rd, T= CGReg rn) tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff); } =20 -static void __attribute__((unused)) -tcg_out_ext8u_cond(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) -{ - tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff); -} - static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) { /* sxth */ tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn); } =20 -static void tcg_out_ext16u_cond(TCGContext *s, ARMCond cond, - TCGReg rd, TCGReg rn) -{ - /* uxth */ - tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn); -} - static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) { - tcg_out_ext16u_cond(s, COND_AL, rd, rn); + /* uxth */ + tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | (rd << 12) | rn); } =20 static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) @@ -1382,92 +1370,29 @@ static void * const qemu_st_helpers[MO_SIZE + 1] = =3D { #endif }; =20 -/* Helper routines for marshalling helper function arguments into - * the correct registers and stack. - * argreg is where we want to put this argument, arg is the argument itsel= f. - * Return value is the updated argreg ready for the next call. - * Note that argreg 0..3 is real registers, 4+ on stack. - * - * We provide routines for arguments which are: immediate, 32 bit - * value in register, 16 and 8 bit values in register (which must be zero - * extended before use) and 64 bit value in a lo:hi register pair. - */ -#define DEFINE_TCG_OUT_ARG(NAME, ARGTYPE, MOV_ARG, EXT_ARG) = \ -static TCGReg NAME(TCGContext *s, TCGReg argreg, ARGTYPE arg) = \ -{ = \ - if (argreg < 4) { = \ - MOV_ARG(s, COND_AL, argreg, arg); = \ - } else { = \ - int ofs =3D (argreg - 4) * 4; = \ - EXT_ARG; = \ - tcg_debug_assert(ofs + 4 <=3D TCG_STATIC_CALL_ARGS_SIZE); = \ - tcg_out_st32_12(s, COND_AL, arg, TCG_REG_CALL_STACK, ofs); = \ - } = \ - return argreg + 1; = \ -} - -DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32, uint32_t, tcg_out_movi32, - (tcg_out_movi32(s, COND_AL, TCG_REG_TMP, arg), arg =3D TCG_REG_TMP)) -DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8, TCGReg, tcg_out_ext8u_cond, - (tcg_out_ext8u_cond(s, COND_AL, TCG_REG_TMP, arg), arg =3D TCG_REG_TMP= )) -DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16, TCGReg, tcg_out_ext16u_cond, - (tcg_out_ext16u_cond(s, COND_AL, TCG_REG_TMP, arg), arg =3D TCG_REG_TM= P)) -DEFINE_TCG_OUT_ARG(tcg_out_arg_reg32, TCGReg, tcg_out_mov_reg, ) - -static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg, - TCGReg arglo, TCGReg arghi) +static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int ar= g) { - /* 64 bit arguments must go in even/odd register pairs - * and in 8-aligned stack slots. - */ - if (argreg & 1) { - argreg++; - } - if (argreg >=3D 4 && (arglo & 1) =3D=3D 0 && arghi =3D=3D arglo + 1) { - tcg_out_strd_8(s, COND_AL, arglo, - TCG_REG_CALL_STACK, (argreg - 4) * 4); - return argreg + 2; - } else { - argreg =3D tcg_out_arg_reg32(s, argreg, arglo); - argreg =3D tcg_out_arg_reg32(s, argreg, arghi); - return argreg; - } + /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */ + return TCG_REG_R14; } =20 +static const TCGLdstHelperParam ldst_helper_param =3D { + .ra_gen =3D ldst_ra_gen, + .ntmp =3D 1, + .tmp =3D { TCG_REG_TMP }, +}; + static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGReg argreg; - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - argreg =3D tcg_out_arg_reg32(s, TCG_REG_R0, TCG_AREG0); - if (TARGET_LONG_BITS =3D=3D 64) { - argreg =3D tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi= _reg); - } else { - argreg =3D tcg_out_arg_reg32(s, argreg, lb->addrlo_reg); - } - argreg =3D tcg_out_arg_imm32(s, argreg, oi); - argreg =3D tcg_out_arg_reg32(s, argreg, TCG_REG_R14); - - /* Use the canonical unsigned helpers and minimize icache usage. */ + tcg_out_ld_helper_args(s, lb, &ldst_helper_param); tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); - - if ((opc & MO_SIZE) =3D=3D MO_64) { - TCGMovExtend ext[2] =3D { - { .dst =3D lb->datalo_reg, .dst_type =3D TCG_TYPE_I32, - .src =3D TCG_REG_R0, .src_type =3D TCG_TYPE_I32, .src_ext = =3D MO_UL }, - { .dst =3D lb->datahi_reg, .dst_type =3D TCG_TYPE_I32, - .src =3D TCG_REG_R1, .src_type =3D TCG_TYPE_I32, .src_ext = =3D MO_UL }, - }; - tcg_out_movext2(s, &ext[0], &ext[1], TCG_REG_TMP); - } else { - tcg_out_movext(s, TCG_TYPE_I32, lb->datalo_reg, - TCG_TYPE_I32, opc & MO_SSIZE, TCG_REG_R0); - } + tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); =20 tcg_out_goto(s, COND_AL, lb->raddr); return true; @@ -1475,42 +1400,13 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGReg argreg, datalo, datahi; - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - argreg =3D TCG_REG_R0; - argreg =3D tcg_out_arg_reg32(s, argreg, TCG_AREG0); - if (TARGET_LONG_BITS =3D=3D 64) { - argreg =3D tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi= _reg); - } else { - argreg =3D tcg_out_arg_reg32(s, argreg, lb->addrlo_reg); - } - - datalo =3D lb->datalo_reg; - datahi =3D lb->datahi_reg; - switch (opc & MO_SIZE) { - case MO_8: - argreg =3D tcg_out_arg_reg8(s, argreg, datalo); - break; - case MO_16: - argreg =3D tcg_out_arg_reg16(s, argreg, datalo); - break; - case MO_32: - default: - argreg =3D tcg_out_arg_reg32(s, argreg, datalo); - break; - case MO_64: - argreg =3D tcg_out_arg_reg64(s, argreg, datalo, datahi); - break; - } - - argreg =3D tcg_out_arg_imm32(s, argreg, oi); - argreg =3D tcg_out_arg_reg32(s, argreg, TCG_REG_R14); + tcg_out_st_helper_args(s, lb, &ldst_helper_param); =20 /* Tail-call to the helper, which will return to the fast path. */ tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683358057662553.7540401055792; Sat, 6 May 2023 00:27:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCG4-0004TI-Kv; Sat, 06 May 2023 03:23:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCG1-0004Jt-HY for qemu-devel@nongnu.org; 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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357768; x=1685949768; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WIdMYknenlDL6zEabJSzjI8eOseBt6FLgSg6Xk98IsQ=; b=fHVcye5G3RY+8FuSS6nq+n9f05jzX3KflHRKycYoDbPpkxVTpn5Cn4VvuclAkN4Rf5 zErNDuZvmIL2cM4QN8XEjMmOvdxvHD8K6/PLhmlcrkdW3m6XyyS+jO15jdL2lnNNgs3A UU0TYeyd0tryGJjXBPrLG7u8IXIFdBaJyysww4DjY/uGd8OCzCzFLa2KK0t3wvGgwGLx 23GV7trlS/m6eON6jUXH2ofj3jK7sMU2Xu/uPtmxJtvtwM8TwfPg0paihzvxBtM78kOg 1N1Ns5z/2X5Ksz/aRtb/WRH7Zj15eLXeWbsLDdbUNSAJnkiOFlibqzUJTXDQJSy8u6bo Se8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357768; x=1685949768; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WIdMYknenlDL6zEabJSzjI8eOseBt6FLgSg6Xk98IsQ=; b=jGqYMidpWSTf5P+tfvoavFr4AW/lSpjBg+UhOg7eQcg/U7r69XfrsYhNS4ktxFNCPB 4PcuKPTLTsCIk7ngZ8OXlzQd2/Du6oMfJ3dC+i0H6ba3py7b8y2cNv5HdlcRLeXVSVrh NGeUfiQa5+Nhb1zxEzghiUJ8VYXRPUtswwlyCWNbyDdmqc98xyWfchDzUsYvsFQqO+Tf IqaY/Jw5ZFaPB3J/JEhIoDX8dOAPB1TV6xkRWLmpgulCr+Wz9MiU89uah/Gje4EcLpDa y7abcqt9GIRNRmUYhfaRT1wJQAPfO8g9tq0cZoxNW48v06dllwUHoUk+8upn4JcBG8w7 fbTg== X-Gm-Message-State: AC+VfDyHDWJOY5uwREwmIo0ybQr40EP1C0vFEVI4FfmVS7R/DVjdTf70 JT0cbv/TghdoweXMS3cBNdFAkzERFdBoSi8sSI5j2Q== X-Google-Smtp-Source: ACHHUZ53APRp5ke+/YyfVMBD9uGTQyjuyF4uduXLaoxgVKeteGATn6UJO/8CH8U25dHjf7XRwp3nig== X-Received: by 2002:a05:6000:104b:b0:2e4:eebe:aee3 with SMTP id c11-20020a056000104b00b002e4eebeaee3mr2472079wrx.60.1683357767931; Sat, 06 May 2023 00:22:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 15/30] tcg/loongarch64: Convert tcg_out_qemu_{ld, st}_slow_path Date: Sat, 6 May 2023 08:22:20 +0100 Message-Id: <20230506072235.597467-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683358059448100003 Content-Type: text/plain; charset="utf-8" Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/loongarch64/tcg-target.c.inc | 37 ++++++++++---------------------- 1 file changed, 11 insertions(+), 26 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 2f2c34b930..60d2c904dd 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -824,51 +824,36 @@ static bool tcg_out_goto(TCGContext *s, const tcg_ins= n_unit *target) return reloc_br_sd10k16(s->code_ptr - 1, target); } =20 +static const TCGLdstHelperParam ldst_helper_param =3D { + .ntmp =3D 1, .tmp =3D { TCG_REG_TMP0 } +}; + static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - MemOp size =3D opc & MO_SIZE; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - /* call load helper */ - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A1, l->addrlo_reg); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A2, oi); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, (tcg_target_long)l->raddr); - - tcg_out_call_int(s, qemu_ld_helpers[size], false); - - tcg_out_movext(s, l->type, l->datalo_reg, - TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_A0); + tcg_out_ld_helper_args(s, l, &ldst_helper_param); + tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE], false); + tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param); return tcg_out_goto(s, l->raddr); } =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - MemOp size =3D opc & MO_SIZE; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - /* call store helper */ - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A1, l->addrlo_reg); - tcg_out_movext(s, size =3D=3D MO_64 ? TCG_TYPE_I32 : TCG_TYPE_I32, TCG= _REG_A2, - l->type, size, l->datalo_reg); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, oi); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A4, (tcg_target_long)l->raddr); - - tcg_out_call_int(s, qemu_st_helpers[size], false); - + tcg_out_st_helper_args(s, l, &ldst_helper_param); + tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); return tcg_out_goto(s, l->raddr); } #else --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683358030; cv=none; d=zohomail.com; s=zohoarc; b=PjTzdHzBLywQOWJUrk+V0c09cTZYVOgxOX79k4dp2pjbywhbrbVCkVW5AuPN5VEKP7Cpwy0DjX0pgoc6V5Zn+vR83hi7VqfdgfcvcwhTOJMCjvpeg+tO/J53UeJAl34tjNAqoEaxf6tY7Ib1q0e2r4OXIKkM2OwPDpRN+JI8emY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683358030; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kF/KuD0+uQLXuYT2v2A5wco+ARF0bjd47P8BXDbif68=; b=Jk2LDLFKGKuR0wXawlMbB0nJ5YimdlczPv3ykrGa7sb/SAq5Ou7hoUAHjRxBupszd9xoU0d9X+gWdpT+2a0Iq60InddZomnOdeJAhFHa2s5ake6b/HfN0WVoL7lUUrtQzNXjJ4LGrzihv5xEP99HJSHS7alkxIU5wmad/HBikZw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683358030155183.59070478351998; Sat, 6 May 2023 00:27:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCG6-0004YN-9I; Sat, 06 May 2023 03:23:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCG3-0004Pu-Fn for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:07 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFm-0004RL-1t for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:06 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-3062db220a3so1730220f8f.0 for ; Sat, 06 May 2023 00:22:49 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357768; x=1685949768; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kF/KuD0+uQLXuYT2v2A5wco+ARF0bjd47P8BXDbif68=; b=Mv14RF7j6oK1HepClJ8lQVXqr4edH3XWDmFJfnvFINlbqy/uUeif83mU2McgdlwGBU pCigGeRLFA1Guy+Nh67Rgc5wh1rrA6IV4FnDwOXmHsV0YqIrc8O8MHiXg72ETz+qpe7h Ym+TyVE3TM3e21H/W1fMlp2IKndN09WzDhQbPBoaYeG+mjZjTMfzdoQ+ZVcf5vLSOKr/ XlQ5qAdDyJiH4k2r58jBmtX0dXZlK/f/X59EFFGQD8Azed0kQ0AcTYZi6G9OfaPvArTU 50X7O6VybLX1wEjoy3wDCgwZoEA/Bwoay8ejSGMPzFiHjXmh/90FT5vkN9CY9r/UCwG5 2vpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357768; x=1685949768; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kF/KuD0+uQLXuYT2v2A5wco+ARF0bjd47P8BXDbif68=; b=HIwuCnKkUXFV7D3db61MjLundDBPRuoDtsv9i7M00+QR0l5W4hTY5rJkq7a5anK8yD tZPtJZTYekNszxsiLvRsqD/8VSaOwZ/nxeN4KytXn7QZ8pmcd4ihUof02g3k14kZ+Uvn 0NAchtsq1c5zEsh2nrUheHmMjuAskkD+LttSAzPqvKaWCSz3nALQGFkLz06X8Z2BSh3n OU683ZOceVwf1cyBhpY2NebzK+i4QFP3SLzaDqbNMwZ9NjnuFapC8J411hb5ljHNocbG P3Apf70rHpNWuHL01ZvRmE3iXfVvuIjrIV43u4O8WaWZz1V3dcNDar9yfR70ZQbelv8i O3zQ== X-Gm-Message-State: AC+VfDx+QQCx7G96P9Cef0kmHbKSh/Y5nsraANJzD103il5E5vU493hZ IgUYfJYlK7KV9Zd8LNRCnu6HAiAWnRUSIvQKYYb+hA== X-Google-Smtp-Source: ACHHUZ4HL/SjDSPNzLIZabYCuenmK2IT+7eD7jihyvHcF2R258YUxbAWRqFbnSjno7TEDA1xEml6Xg== X-Received: by 2002:adf:e80e:0:b0:2f9:85ee:e031 with SMTP id o14-20020adfe80e000000b002f985eee031mr2866134wrm.26.1683357768633; Sat, 06 May 2023 00:22:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 16/30] tcg/mips: Convert tcg_out_qemu_{ld,st}_slow_path Date: Sat, 6 May 2023 08:22:21 +0100 Message-Id: <20230506072235.597467-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683358031617100003 Content-Type: text/plain; charset="utf-8" Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. This allows our local tcg_out_arg_* infrastructure to be removed. We are no longer filling the call or return branch delay slots, nor are we tail-calling for the store, but this seems a small price to pay. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/mips/tcg-target.c.inc | 154 ++++++-------------------------------- 1 file changed, 22 insertions(+), 132 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 94708e6ea7..022960d79a 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1115,79 +1115,15 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_B= SWAP) + 1] =3D { [MO_BEUQ] =3D helper_be_stq_mmu, }; =20 -/* Helper routines for marshalling helper function arguments into - * the correct registers and stack. - * I is where we want to put this argument, and is updated and returned - * for the next call. ARG is the argument itself. - * - * We provide routines for arguments which are: immediate, 32 bit - * value in register, 16 and 8 bit values in register (which must be zero - * extended before use) and 64 bit value in a lo:hi register pair. - */ - -static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg) -{ - if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { - tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg); - } else { - /* For N32 and N64, the initial offset is different. But there - we also have 8 argument register so we don't run out here. */ - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); - tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i); - } - return i + 1; -} - -static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg) -{ - TCGReg tmp =3D TCG_TMP0; - if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { - tmp =3D tcg_target_call_iarg_regs[i]; - } - tcg_out_ext8u(s, tmp, arg); - return tcg_out_call_iarg_reg(s, i, tmp); -} - -static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg) -{ - TCGReg tmp =3D TCG_TMP0; - if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { - tmp =3D tcg_target_call_iarg_regs[i]; - } - tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff); - return tcg_out_call_iarg_reg(s, i, tmp); -} - -static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg) -{ - TCGReg tmp =3D TCG_TMP0; - if (arg =3D=3D 0) { - tmp =3D TCG_REG_ZERO; - } else { - if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { - tmp =3D tcg_target_call_iarg_regs[i]; - } - tcg_out_movi(s, TCG_TYPE_REG, tmp, arg); - } - return tcg_out_call_iarg_reg(s, i, tmp); -} - -static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg = ah) -{ - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); - i =3D (i + 1) & ~1; - i =3D tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al)); - i =3D tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah)); - return i; -} +/* We have four temps, we might as well expose three of them. */ +static const TCGLdstHelperParam ldst_helper_param =3D { + .ntmp =3D 3, .tmp =3D { TCG_TMP0, TCG_TMP1, TCG_TMP2 } +}; =20 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { const tcg_insn_unit *tgt_rx =3D tcg_splitwx_to_rx(s->code_ptr); - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - TCGReg v0; - int i; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_pc16(l->label_ptr[0], tgt_rx) @@ -1196,29 +1132,13 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) return false; } =20 - i =3D 1; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - i =3D tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); - } else { - i =3D tcg_out_call_iarg_reg(s, i, l->addrlo_reg); - } - i =3D tcg_out_call_iarg_imm(s, i, oi); - i =3D tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr); + tcg_out_ld_helper_args(s, l, &ldst_helper_param); + tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], fals= e); /* delay slot */ - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); + tcg_out_nop(s); =20 - v0 =3D l->datalo_reg; - if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { - /* We eliminated V0 from the possible output registers, so it - cannot be clobbered here. So we must move V1 first. */ - if (MIPS_BE) { - tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1); - v0 =3D l->datahi_reg; - } else { - tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1); - } - } + tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); =20 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { @@ -1226,22 +1146,14 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) } =20 /* delay slot */ - if (TCG_TARGET_REG_BITS =3D=3D 64 && l->type =3D=3D TCG_TYPE_I32) { - /* we always sign-extend 32-bit loads */ - tcg_out_ext32s(s, v0, TCG_REG_V0); - } else { - tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO); - } + tcg_out_nop(s); return true; } =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { const tcg_insn_unit *tgt_rx =3D tcg_splitwx_to_rx(s->code_ptr); - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; - int i; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_pc16(l->label_ptr[0], tgt_rx) @@ -1250,41 +1162,19 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) return false; } =20 - i =3D 1; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - i =3D tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); - } else { - i =3D tcg_out_call_iarg_reg(s, i, l->addrlo_reg); - } - switch (s_bits) { - case MO_8: - i =3D tcg_out_call_iarg_reg8(s, i, l->datalo_reg); - break; - case MO_16: - i =3D tcg_out_call_iarg_reg16(s, i, l->datalo_reg); - break; - case MO_32: - i =3D tcg_out_call_iarg_reg(s, i, l->datalo_reg); - break; - case MO_64: - if (TCG_TARGET_REG_BITS =3D=3D 32) { - i =3D tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_re= g); - } else { - i =3D tcg_out_call_iarg_reg(s, i, l->datalo_reg); - } - break; - default: - g_assert_not_reached(); - } - i =3D tcg_out_call_iarg_imm(s, i, oi); + tcg_out_st_helper_args(s, l, &ldst_helper_param); =20 - /* Tail call to the store helper. Thus force the return address - computation to take place in the return address register. */ - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr); - i =3D tcg_out_call_iarg_reg(s, i, TCG_REG_RA); - tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true); + tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], false= ); /* delay slot */ - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); + tcg_out_nop(s); + + tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); + if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { + return false; + } + + /* delay slot */ + tcg_out_nop(s); return true; } =20 --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683358103; cv=none; d=zohomail.com; s=zohoarc; b=TWahr7t3zc+Fm3S4euGLiSUF3HIAQEFup8916N/ZVhdm2FwMmzIQbblcg1DKJT1wJFF+ZHEs8HUNHdghffOGsNHoJVr1b3dYX4FaSvrGn9AQwy9yH04+KpyNU13SZ9NgEMz249rttXsiMjUD5r2bCxtLgcuKzxbFuSEioVy3bP8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683358103; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Bp+7jHuRwCoumX81kkmi2LLSK4XPzI38mrYIrW5iAjM=; b=HG7dzC2eZi50ZX7x2v5cIbLXEJnONCxFExG9J4JQ6p0tmZqa1UY3GJdzuJo8qKm0ogKecjIOOHMyLht2dbh5XB3+muy2dIrkl4R3gr430ipvY4WVRfwTRRsUqF/qCDYtbP86BulH8rfFB9Dxzv35QQArDfxg+eZ9S6d4hwWAjCA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683358103946851.4099889497093; Sat, 6 May 2023 00:28:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCG8-0004gl-38; Sat, 06 May 2023 03:23:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCG4-0004SY-AY for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:08 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFm-0004LH-5i for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:08 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3f415a90215so6327885e9.0 for ; Sat, 06 May 2023 00:22:49 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357769; x=1685949769; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Bp+7jHuRwCoumX81kkmi2LLSK4XPzI38mrYIrW5iAjM=; b=RuPpVsg69wZKOXhZJXZGvrel3vwJkeiLbWsRHRKNhkuAVbXkWi/RgCI01gLVQw/u1e 2DjT0R/gJruizoYHzqLILaiebnpsRYb9DM1+O5oFA2z+RQOktgCKkyb2tEiVriTgdH2s dN8OqSmdt+bBOJ+ipT5XYmgxihdGLyVOe9ghbHmPvJEmGFc1BVDXC3NAita07AifBvIH Ym+aHnwVSp3eYKhyolzQIHbHGtG4Livy+E/XP/u8VCz/GrYrZVhr/b9dj9AGWvTAFisc BLX2kDT0OYENsd5wcJynbznpZ9q4A4wfSojUCoUhG+52N0GVQ2Sok9CPXilexURwR3fJ iC6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357769; x=1685949769; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Bp+7jHuRwCoumX81kkmi2LLSK4XPzI38mrYIrW5iAjM=; b=IfLJ8f9iA15/r7ShGwYaAbvGkiY6jU2b0Z6mFNMvJzbGwcOwj57KjbDZLrG0FPTiby 1jXtaYFK0dXjzNB29XjqLUlXDtAdYdH5JRlbUgJDzaL9LsGme6A9ljhIjMB7ShCU33DN 6aORsxT063GXKQXiMMxobQUoVtl2Qt0jQCRUsSepbQ8heQiffgZzXmVrtEV1lWxInIUz dC6WQpaV9r4UMwNeKAHQ3fHhgfyI3aJFiNmLHrdNHBgPSstt7A5sLiavzqIVZf6bbXm0 D9izMC7Zmias+7D8Jg4WVJnlIgY+xeZgN+CdTwfOD0l99GIoFyQ3HkeyrYqlnxJ/RTLM CkfA== X-Gm-Message-State: AC+VfDzMqP4eqdHxmm59EW9amXexlDll5QoXUeQ91qsxucXOXYMTPdKE dgQTUTLWsxbeUDGWAHNjA3r6Ru2rcIQlGRDaad3plg== X-Google-Smtp-Source: ACHHUZ6zmAb3COBB6G8a3/hJRcraPL06UVJKdAkWZOR9xTe8RPhtxW0RtwnHeSEo6BOtRvQDQCepXQ== X-Received: by 2002:a05:6000:12c9:b0:2d0:bba8:3901 with SMTP id l9-20020a05600012c900b002d0bba83901mr2702707wrx.62.1683357769412; Sat, 06 May 2023 00:22:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Daniel Henrique Barboza Subject: [PATCH v5 17/30] tcg/ppc: Convert tcg_out_qemu_{ld,st}_slow_path Date: Sat, 6 May 2023 08:22:22 +0100 Message-Id: <20230506072235.597467-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683358109332100001 Content-Type: text/plain; charset="utf-8" Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/ppc/tcg-target.c.inc | 88 ++++++++++++---------------------------- 1 file changed, 26 insertions(+), 62 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 7239335bdf..042136fee7 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2003,44 +2003,38 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_B= SWAP) + 1] =3D { [MO_BEUQ] =3D helper_be_stq_mmu, }; =20 +static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int ar= g) +{ + if (arg < 0) { + arg =3D TCG_REG_TMP1; + } + tcg_out32(s, MFSPR | RT(arg) | LR); + return arg; +} + +/* + * For the purposes of ppc32 sorting 4 input registers into 4 argument + * registers, there is an outside chance we would require 3 temps. + * Because of constraints, no inputs are in r3, and env will not be + * placed into r3 until after the sorting is done, and is thus free. + */ +static const TCGLdstHelperParam ldst_helper_param =3D { + .ra_gen =3D ldst_ra_gen, + .ntmp =3D 3, + .tmp =3D { TCG_REG_TMP1, TCG_REG_R0, TCG_REG_R3 } +}; + static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); - TCGReg hi, lo, arg =3D TCG_REG_R3; + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); - - lo =3D lb->addrlo_reg; - hi =3D lb->addrhi_reg; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - arg |=3D (TCG_TARGET_CALL_ARG_I64 =3D=3D TCG_CALL_ARG_EVEN); - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - } else { - /* If the address needed to be zero-extended, we'll have already - placed it in R4. The only remaining case is 64-bit guest. */ - tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); - } - - tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); - tcg_out32(s, MFSPR | RT(arg) | LR); - + tcg_out_ld_helper_args(s, lb, &ldst_helper_param); tcg_out_call_int(s, LK, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); - - lo =3D lb->datalo_reg; - hi =3D lb->datahi_reg; - if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { - tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4); - tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3); - } else { - tcg_out_movext(s, lb->type, lo, - TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_R3); - } + tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); =20 tcg_out_b(s, 0, lb->raddr); return true; @@ -2048,43 +2042,13 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; - TCGReg hi, lo, arg =3D TCG_REG_R3; + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); - - lo =3D lb->addrlo_reg; - hi =3D lb->addrhi_reg; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - arg |=3D (TCG_TARGET_CALL_ARG_I64 =3D=3D TCG_CALL_ARG_EVEN); - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - } else { - /* If the address needed to be zero-extended, we'll have already - placed it in R4. The only remaining case is 64-bit guest. */ - tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); - } - - lo =3D lb->datalo_reg; - hi =3D lb->datahi_reg; - if (TCG_TARGET_REG_BITS =3D=3D 32 && s_bits =3D=3D MO_64) { - arg |=3D (TCG_TARGET_CALL_ARG_I64 =3D=3D TCG_CALL_ARG_EVEN); - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - } else { - tcg_out_movext(s, s_bits =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I3= 2, - arg++, lb->type, s_bits, lo); - } - - tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); - tcg_out32(s, MFSPR | RT(arg) | LR); - + tcg_out_st_helper_args(s, lb, &ldst_helper_param); tcg_out_call_int(s, LK, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 tcg_out_b(s, 0, lb->raddr); --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683357817; cv=none; d=zohomail.com; s=zohoarc; b=IESPdzfcoCdriIMjz7yiWXASMS2LfwEA+ZEj+CRIh0iYiYIb+b971Qn5lNrW7uQDR0bz21CHRymZ2H1T3iKqto+7+SCWqKpe2jjhxRVQAI6z9pIzIP1VkuwXHMaX1Ftfmr7T6eUD5kPlShNWi/vWcvW5hyQCjkkXR1vfLfqU90w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683357817; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Mj3a+zcWVqs2C3w0reTnX7wZZ61td92YW4iK8rO87Zg=; b=gdj9RX78C8fO9Dt8sTMgi6riWI0xPF+k4ZZfCJi17DIItIAgmuBdUjSo3bXXfZJ8IJlHkz5VMmENRJRphiTob56Eec3Df45ReWU/oDO/kl9o2L32Xd77LCGQEmdvljj10cOjdy/LDp49nI+aSqweSNNKs6l7xJ68nUhpNXIAQ2k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683357817434393.5866204080023; Sat, 6 May 2023 00:23:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCG9-0004iz-6D; Sat, 06 May 2023 03:23:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCG7-0004f6-J2 for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:11 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFo-0004SD-Ic for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:11 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-3f193ca059bso16893855e9.3 for ; Sat, 06 May 2023 00:22:51 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357770; x=1685949770; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Mj3a+zcWVqs2C3w0reTnX7wZZ61td92YW4iK8rO87Zg=; b=Q7AUr5FfRa6JPB7ZgojgUuypgrcrd+YukMgxC9AMur5zGPVcIDlWfE04HkjGGFPqje L2fZLAZ0cwqwgZv0VnUfa7fCv0DeIpKs1Icp2QgjWDe27J2o3uuDfgmS7x1EMBAdITK/ 83HBgGz2b6vkLDjGNjiUqW5RoB091SwFuz5h/DhBOSwPu9wtWa5d2qBdyVmnd/kPAyGl ++nLOgILq80xYKXJCbzxj99C8av/CoB5lkX2P0v7OxkxXHMQ/IVntIKjvkE+7Zxl1txw RTOBFXIElKgorg4SZ794eVUlKaYHsLBHT5NUTm5brJrgW0/oxNOGS6PNmEwtKJP6NXhH zaLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357770; x=1685949770; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mj3a+zcWVqs2C3w0reTnX7wZZ61td92YW4iK8rO87Zg=; b=bXPPO7KEkC6K+92wn8JIG77g/0R286OpbkWXGI0ApIjL8uvdqaFfo+gjkEIl6AgTdc THqksE5sVucbBIbCLra67LDnwRBWd5KnmZuwn8BqldP3OPOcB+Qu9fQpTbP4DunNiOdP 6hm2wDkUvybVyZtyPdgUCjveJsdx0uulhyU0VvDfiK5BKrpy3bjhdgKQ3WHYTv4kdHAR /xuql5PvLoo1LsF5nhc9IU6KNKIg6qIC1BjktlcJLMuAKjgFJ4Owqk1oNEpRb7JaGjjP CYtE1Gr4nOqS0bzJCX7Tw735jBN7i6PpjOzjeWBgk4Or3c3D2hSEsYn18mAv6KoIx0eV fLPA== X-Gm-Message-State: AC+VfDy4US6pLRSbH6cWI4sv9yX+wzyvhbntB27cg4h/tGNxCa/QHjPa 5i7Oy/b0CFpv5kuWrSCjjhJ5hRYGxGJrsoZ2m5eEcA== X-Google-Smtp-Source: ACHHUZ5MuI33qUOB4uebDjvwEw6MRDGaqI/qqC6n1mjnb9iuEUW7P8iJ67FdyvxztGqQlXKmJWCBeA== X-Received: by 2002:a7b:c38e:0:b0:3f0:310c:e3cf with SMTP id s14-20020a7bc38e000000b003f0310ce3cfmr2887721wmj.37.1683357770164; Sat, 06 May 2023 00:22:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Daniel Henrique Barboza Subject: [PATCH v5 18/30] tcg/riscv: Convert tcg_out_qemu_{ld,st}_slow_path Date: Sat, 6 May 2023 08:22:23 +0100 Message-Id: <20230506072235.597467-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683357819168100001 Content-Type: text/plain; charset="utf-8" Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/riscv/tcg-target.c.inc | 37 ++++++++++--------------------------- 1 file changed, 10 insertions(+), 27 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 2b2d313fe2..c22d1e35ac 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -906,14 +906,14 @@ static void tcg_out_goto(TCGContext *s, const tcg_ins= n_unit *target) tcg_debug_assert(ok); } =20 +/* We have three temps, we might as well expose them. */ +static const TCGLdstHelperParam ldst_helper_param =3D { + .ntmp =3D 3, .tmp =3D { TCG_REG_TMP0, TCG_REG_TMP1, TCG_REG_TMP2 } +}; + static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - TCGReg a0 =3D tcg_target_call_iarg_regs[0]; - TCGReg a1 =3D tcg_target_call_iarg_regs[1]; - TCGReg a2 =3D tcg_target_call_iarg_regs[2]; - TCGReg a3 =3D tcg_target_call_iarg_regs[3]; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -921,13 +921,9 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, T= CGLabelQemuLdst *l) } =20 /* call load helper */ - tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); - tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); - tcg_out_movi(s, TCG_TYPE_PTR, a2, oi); - tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr); - + tcg_out_ld_helper_args(s, l, &ldst_helper_param); tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); - tcg_out_mov(s, (opc & MO_SIZE) =3D=3D MO_64, l->datalo_reg, a0); + tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); =20 tcg_out_goto(s, l->raddr); return true; @@ -935,14 +931,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, T= CGLabelQemuLdst *l) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; - TCGReg a0 =3D tcg_target_call_iarg_regs[0]; - TCGReg a1 =3D tcg_target_call_iarg_regs[1]; - TCGReg a2 =3D tcg_target_call_iarg_regs[2]; - TCGReg a3 =3D tcg_target_call_iarg_regs[3]; - TCGReg a4 =3D tcg_target_call_iarg_regs[4]; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -950,13 +939,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, T= CGLabelQemuLdst *l) } =20 /* call store helper */ - tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); - tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); - tcg_out_movext(s, s_bits =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, a= 2, - l->type, s_bits, l->datalo_reg); - tcg_out_movi(s, TCG_TYPE_PTR, a3, oi); - tcg_out_movi(s, TCG_TYPE_PTR, a4, (tcg_target_long)l->raddr); - + tcg_out_st_helper_args(s, l, &ldst_helper_param); tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); =20 tcg_out_goto(s, l->raddr); --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683358092; cv=none; d=zohomail.com; s=zohoarc; b=MO+9mROvikOi+1UwmWlJEaNNAF4tLMydEvffLg3I/D0cl0qpdohJ9RJyE23UGJ86dSLShuipioMiIPkZFjtL74VJuQLKkxwcWaU3dplfIboiUzd4KNz0BLOSXgK3ghGkM7KmLFsBdOPxfNgyEiMl6j5AAjN0IN9g6tFxvIZ/ESg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683358092; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8inodTGUilDAhT6OBmWmJGZ3vieMgwqC5uJSdvFYggQ=; b=P0vvILEyQrd12ttMK2T7qq0kVDSvsy2xg2C1qktXPnPTZlIXR6m0vSb2wkilO58I7+BZw3OsGeaSLYXsuT+aSP1JowPhqpvOIatO726N/PcfsdPAK1QhyPRSpWDX/bKt12tc+4dW8vR+YaS6zoHclAIXCfNC2/Dl/BUFjCSnVvE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683358092776700.5083812224987; Sat, 6 May 2023 00:28:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCG8-0004i6-O5; Sat, 06 May 2023 03:23:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCG7-0004c7-0w for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:11 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFo-0004SY-BK for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:10 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-3064099f9b6so1651688f8f.1 for ; Sat, 06 May 2023 00:22:51 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357771; x=1685949771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8inodTGUilDAhT6OBmWmJGZ3vieMgwqC5uJSdvFYggQ=; b=mIpqUy5ESK+cnzGBnByEF+zrbEq4AiX0bwxfBgdHOVN8z9EhahKHcDwNoidD4WOMAJ qGqzo2l1pbQV8gVE7a5fxIMlG/3xR/u++MndQBVEklVRw26YniFURqaSVA013I4eoGqA QE1LarIssaEfw47qUhEL98SQtyxFbOf/Uf6QDfrw3cRiJntsUjKdKNqoLT8hOROlSX8Y k6faQDE44VMivzHTscD1/klAwUrOIn7m4E5g5OeZAXk3Bp19IthEaHJuRsY6genBC7x3 qclwaQsbzIqEhHSJUvibDpis1AzsbGtpZxVSdaZQVjcrBGQx6jiFKWlsbZrWXLq4+rCQ TuWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357771; x=1685949771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8inodTGUilDAhT6OBmWmJGZ3vieMgwqC5uJSdvFYggQ=; b=gbSq8AeOxoDTpcd58JjeIf5uWN+cc+d5MgqzMdHu+Gu1Qat1rudbqYiATPp6ctXba4 8m5h4ds5ON7HpW8XMQLJ+DxCHNMC63Su+NcS1OIpHKnemP5ToPPRwRbGUImj4JGQGD4n 9dvNqraKFEo20ERqg0F81RjENEWZCeGe/zD50rFT76z9qVH/Jh7c9kN2Ef8BW9kls0xB DaLdZasvIqQeFPAFzfih017Jd/qhfjTULK3wyNYpoRuu5szEcO412MGFRgMRGlm/4RRJ A++c7o+kTizusaVXP6RmAp2Zg6m2sX+ZPVrCCCwRvz5CCwWOLbmiiLrS2CwklK7b8Hhn hW8Q== X-Gm-Message-State: AC+VfDz1KOQlwhRBaPmcILaydH6wx248miB+xw+BOdwmbEduQGXq9ZTF Pyc2DjpxJpsYBJNJZedzOYpoawPVeoviZIbLKls/Jw== X-Google-Smtp-Source: ACHHUZ6Dj88SGXDQuKj+LcvFLGOalSdSSD8MBUHsoSAtd4y0Rl1XBfpfL0gwGAQXKIMKZurFIMnUNQ== X-Received: by 2002:a5d:6a8b:0:b0:304:6762:2490 with SMTP id s11-20020a5d6a8b000000b0030467622490mr2934795wru.3.1683357770910; Sat, 06 May 2023 00:22:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 19/30] tcg/s390x: Convert tcg_out_qemu_{ld,st}_slow_path Date: Sat, 6 May 2023 08:22:24 +0100 Message-Id: <20230506072235.597467-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683358094791100005 Content-Type: text/plain; charset="utf-8" Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/s390x/tcg-target.c.inc | 35 ++++++++++------------------------- 1 file changed, 10 insertions(+), 25 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index c3157d22be..dfcf4d9e34 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1718,26 +1718,22 @@ static void tcg_out_qemu_st_direct(TCGContext *s, M= emOp opc, TCGReg data, } =20 #if defined(CONFIG_SOFTMMU) +static const TCGLdstHelperParam ldst_helper_param =3D { + .ntmp =3D 1, .tmp =3D { TCG_TMP0 } +}; + static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGReg addr_reg =3D lb->addrlo_reg; - TCGReg data_reg =3D lb->datalo_reg; - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(lb->oi); =20 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg); - } - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, oi); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R5, (uintptr_t)lb->raddr); - tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]); - tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R2); + tcg_out_ld_helper_args(s, lb, &ldst_helper_param); + tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); =20 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); return true; @@ -1745,25 +1741,14 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGReg addr_reg =3D lb->addrlo_reg; - TCGReg data_reg =3D lb->datalo_reg; - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); - MemOp size =3D opc & MO_SIZE; + MemOp opc =3D get_memop(lb->oi); =20 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg); - } - tcg_out_movext(s, size =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, - TCG_REG_R4, lb->type, size, data_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, oi); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R6, (uintptr_t)lb->raddr); + tcg_out_st_helper_args(s, lb, &ldst_helper_param); tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683357870; cv=none; d=zohomail.com; s=zohoarc; b=iqoSGOPGA8yXsvfp67/jjs0WHYgiDqxU6f0JX//FIki15qvQtncm/O0u4DpUUP7u3LuHBWGXm4l3DjuJXH4C8ICWeK4J4TkkVLRwoMeMJiEnjf3x7NqezOGmHgfsin1J4i3w9MbHnL4PCtqiEdT4fFXUfECd3kopklGYFk2hHSQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683357870; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=I/zSZo4J7v0p5c8aMIcv0bwGQ0NvaaNKP+yN/zUi81E=; b=bQdy6SWIl12ZHLaQTAqpZSdqvFFyGMmm1BJxsg19lqwbU+ixMqOlvElwflD2/eYHXpqvB04c96A9ykOymrjWmtTrcBLPPudSKkM0R/OVzs7BtdIgd1Vf4daauJjm6xPRm1Ki0OUTQo7ROOs4Wv3l+LM2cgM91MWFqD62HV5iY78= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683357870897381.4389242498519; Sat, 6 May 2023 00:24:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCGC-0004om-Da; Sat, 06 May 2023 03:23:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCG9-0004ir-2x for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:13 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFp-0004St-3f for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:12 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-3062c1e7df8so1731516f8f.1 for ; Sat, 06 May 2023 00:22:52 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357771; x=1685949771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=I/zSZo4J7v0p5c8aMIcv0bwGQ0NvaaNKP+yN/zUi81E=; b=rdirzeBmzWy7b77uv9eRgwWMPlRCnj5tkHB8XBQyOZUBEV+8dhTxdFQUxGR8HMj1tI TLO/Egd2knFHhSmC3Uoj/tIAlZccpOwZ/vLoXaCV8Ay9QaZchaJerI7+RHQIR8UXRq6S IHhq6LM9hlzylwOuiYYZgrqDyLZiSN4DM+pVuxrmelUpeiU6491sKRoLbqaXugI4IKA1 nyxaLJQ2UISSHslQEu4h8Kt5qYoQrBRqV1iUe/z7u5DNo0HFEpBvr+z1wuhq+JTPh+L3 8tx+KBWgUD4pJ8eIEV2s5oXNU6dTXWNuZCLP2tdyuTi8zq7J3wYtYDJXmvMOMbQnbllB k6kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357771; x=1685949771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I/zSZo4J7v0p5c8aMIcv0bwGQ0NvaaNKP+yN/zUi81E=; b=RfZWGpXIyLCsS8wioqFTSRfzp2xyF/yvReo4CIb3Ah7XxPVZgRockHMKuT3EvXJdvY 6YmF5m1cP0NeeaCL8NaDkQcDcbwjNoHDdta1uycRLapWDDmMfZM6aAFRyQxtBZuJtzUU IsmEpHVPbr7Xe+B1+wZC9fisNy9xZS2o44db/juYMt8iEpOz3r9pNsV4lk+8CqlG5VYY gmLAhX0zC4/Y+axRncvlReYFOMycM0Nnkeat0JpgiiJU2n9M8a84kPeUsHkW8ZZzqDWs RD5qoaNSHJS6/JnXHw4JI8rOoIsG3dowyHFdAWNgqBkPBKmoKX6a7lDQ1kiuXpjthqBo y6kQ== X-Gm-Message-State: AC+VfDw5EseQyCnk7wAtrPLfiZjHQUylgEn+4SAD69bU9fg21zBHllct xs6uBH5lGkpNZmXUTtHSiYQOo7bpSqRbn7t2HOmneA== X-Google-Smtp-Source: ACHHUZ5O55VR7LN+C53N7nuDehZANlZj3InMGmivqzbYYN9/9X8vMjbet+dzwpW+jywKZ7HciojAcQ== X-Received: by 2002:a5d:6183:0:b0:307:7f38:37f with SMTP id j3-20020a5d6183000000b003077f38037fmr2933451wru.66.1683357771749; Sat, 06 May 2023 00:22:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 20/30] tcg/loongarch64: Simplify constraints on qemu_ld/st Date: Sat, 6 May 2023 08:22:25 +0100 Message-Id: <20230506072235.597467-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683357872773100003 Content-Type: text/plain; charset="utf-8" The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/loongarch64/tcg-target-con-set.h | 2 -- tcg/loongarch64/tcg-target-con-str.h | 1 - tcg/loongarch64/tcg-target.c.inc | 23 ++++------------------- 3 files changed, 4 insertions(+), 22 deletions(-) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-tar= get-con-set.h index 172c107289..c2bde44613 100644 --- a/tcg/loongarch64/tcg-target-con-set.h +++ b/tcg/loongarch64/tcg-target-con-set.h @@ -17,9 +17,7 @@ C_O0_I1(r) C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) -C_O0_I2(LZ, L) C_O1_I1(r, r) -C_O1_I1(r, L) C_O1_I2(r, r, rC) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) diff --git a/tcg/loongarch64/tcg-target-con-str.h b/tcg/loongarch64/tcg-tar= get-con-str.h index 541ff47fa9..6e9ccca3ad 100644 --- a/tcg/loongarch64/tcg-target-con-str.h +++ b/tcg/loongarch64/tcg-target-con-str.h @@ -14,7 +14,6 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) -REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 60d2c904dd..83fa45c802 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -133,18 +133,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKi= nd kind, int slot) #define TCG_CT_CONST_C12 0x1000 #define TCG_CT_CONST_WSZ 0x2000 =20 -#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) -/* - * For softmmu, we need to avoid conflicts with the first 5 - * argument registers to call the helper. Some of these are - * also used for the tlb lookup. - */ -#ifdef CONFIG_SOFTMMU -#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5) -#else -#define SOFTMMU_RESERVE_REGS 0 -#endif - +#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) =20 static inline tcg_target_long sextreg(tcg_target_long val, int pos, int le= n) { @@ -1541,16 +1530,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) case INDEX_op_st32_i64: case INDEX_op_st_i32: case INDEX_op_st_i64: + case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st_i64: return C_O0_I2(rZ, r); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: return C_O0_I2(rZ, rZ); =20 - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_st_i64: - return C_O0_I2(LZ, L); - case INDEX_op_ext8s_i32: case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: @@ -1586,11 +1573,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_ld32u_i64: case INDEX_op_ld_i32: case INDEX_op_ld_i64: - return C_O1_I1(r, r); - case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return C_O1_I1(r, L); + return C_O1_I1(r, r); =20 case INDEX_op_andc_i32: case INDEX_op_andc_i64: --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683357911; cv=none; d=zohomail.com; s=zohoarc; b=jQ1jhWleg2zsx8S7zCiCionJLZKDqESMyifs0mzXWcoVbMv3Jd0SrU0B+XaQ7pOuNqhyMxd+nV/bTPAj3ZSwFRtjXU9HG6J0qg614p0ISm8E6b9jbqgkl9Z8soKyGpCeN21ZSiujsHWgB90e7JovBJTqQY8Pz6IUaZsrCMiiVmE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683357911; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aucysoTI00/6AHztRhanSz7uVuWer883go2thcLlz8w=; b=XbjiCLxfEbgnqxSVyOOrQzykwgzBJrVTW1Sr35jyIsdqf3zcd8zzx7J4yR1Xxlh8fQfjQR/WMGzHhxr2lnsc08OMXOJGMGwoNBna2ZqOedgj6bFBIXfhS7HhzgO7F5ptXfk4O7Y72r6xMxQlsbKtINSxYJPTlfH2mkvmcWdDDGs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683357911634685.9776205687383; Sat, 6 May 2023 00:25:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCGD-0004qH-1Y; Sat, 06 May 2023 03:23:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCGA-0004nA-OK for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:14 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFp-0004Kg-JB for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:14 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-3f19a80a330so17361285e9.2 for ; Sat, 06 May 2023 00:22:53 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357773; x=1685949773; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aucysoTI00/6AHztRhanSz7uVuWer883go2thcLlz8w=; b=a6EfgxfrQs/day4wTJl+pRzIfjC2BhUEv+fwlvTKTvxtfz+bnP/6f1CKgRU8Ly7YRP gI3w2Ch5HpU3CcNwIBg6zoUVGB7G8eIHz73z6aMenm8/gIceTMJrPLq7kqHKbhEthY/H 7aD1/3Ul7n5HaFuSfo4u+10X6V/qF4YrVyN7OyK4EccM0YXxUvxGIt2IczAr4HrLRmD0 81JsevkNowl2UwkMZnI4M9rAB38CJTIzECkSsWmSh4kYHQF/F66gBpNIkunnNOQOQaRa i3QGq1U0pWh8EJIIjPbZ1GGyiYr0AahROPXrzOMmcJvOHRkBlN3O8wh/EOJqg0Xoe+mW mpKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357773; x=1685949773; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aucysoTI00/6AHztRhanSz7uVuWer883go2thcLlz8w=; b=WJlPkJPKcv68eaJVBru2Hp45xi/eAt4T3y758p0/cY5XJgEO1ofaplemD9QBNm7B+u eU/3xVPjNRWDrbrbT6FJ0WurtFz5jfBF+Mj9WyV2wpCk5AC9LWSUPS6iN3vGmzucdRM/ fHCRlMdLaLVt6IznxmdO6pqF2/MlgqlxQKJlZ2frKRaOB2XjYWf3YISbDIx/H/fw0gv3 Fvz16JpCyaGlFwMu60KduShDVs3Rl/SNjPihuK++fZ5bvO+ZI6L4+Rgsd65D2ZsdgXE/ Yddhf5gqFZu4/C9e5hbRPbMOOFFNEpdXee/tc8vBqWGNSfseBRoJ5zZwQJQLkjTPHnB/ XLng== X-Gm-Message-State: AC+VfDxxPB8uyxCZwnvYWA2IQFQeNRSpfwz4ehaSx9Q7qVYWy9izA2ZE yv64uIsgbJZEGcdSTec1svqEGJjIYxDzEtbhn/PRSA== X-Google-Smtp-Source: ACHHUZ5ez8u/1cmIRkmcjxnFrUGQYSuQ4pG7qhq95LlwPWC0VqMS+li+SzCHxjTj3WPeXVn/eBBrrA== X-Received: by 2002:a1c:f20a:0:b0:3f1:819d:d050 with SMTP id s10-20020a1cf20a000000b003f1819dd050mr2735853wmc.37.1683357772694; Sat, 06 May 2023 00:22:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 21/30] tcg/mips: Remove MO_BSWAP handling Date: Sat, 6 May 2023 08:22:26 +0100 Message-Id: <20230506072235.597467-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683357913876100003 Content-Type: text/plain; charset="utf-8" While performing the load in the delay slot of the call to the common bswap helper function is cute, it is not worth the added complexity. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/mips/tcg-target.h | 4 +- tcg/mips/tcg-target.c.inc | 284 ++++++-------------------------------- 2 files changed, 48 insertions(+), 240 deletions(-) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 2431fc5353..42bd7fff01 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -204,8 +204,8 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_ext16u_i64 0 /* andi rt, rs, 0xffff */ #endif =20 -#define TCG_TARGET_DEFAULT_MO (0) -#define TCG_TARGET_HAS_MEMORY_BSWAP 1 +#define TCG_TARGET_DEFAULT_MO 0 +#define TCG_TARGET_HAS_MEMORY_BSWAP 0 =20 #define TCG_TARGET_NEED_LDST_LABELS =20 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 022960d79a..31d58e1977 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1088,31 +1088,35 @@ static void tcg_out_call(TCGContext *s, const tcg_i= nsn_unit *arg, } =20 #if defined(CONFIG_SOFTMMU) -static void * const qemu_ld_helpers[(MO_SSIZE | MO_BSWAP) + 1] =3D { +static void * const qemu_ld_helpers[MO_SSIZE + 1] =3D { [MO_UB] =3D helper_ret_ldub_mmu, [MO_SB] =3D helper_ret_ldsb_mmu, - [MO_LEUW] =3D helper_le_lduw_mmu, - [MO_LESW] =3D helper_le_ldsw_mmu, - [MO_LEUL] =3D helper_le_ldul_mmu, - [MO_LEUQ] =3D helper_le_ldq_mmu, - [MO_BEUW] =3D helper_be_lduw_mmu, - [MO_BESW] =3D helper_be_ldsw_mmu, - [MO_BEUL] =3D helper_be_ldul_mmu, - [MO_BEUQ] =3D helper_be_ldq_mmu, -#if TCG_TARGET_REG_BITS =3D=3D 64 - [MO_LESL] =3D helper_le_ldsl_mmu, - [MO_BESL] =3D helper_be_ldsl_mmu, +#if HOST_BIG_ENDIAN + [MO_UW] =3D helper_be_lduw_mmu, + [MO_SW] =3D helper_be_ldsw_mmu, + [MO_UL] =3D helper_be_ldul_mmu, + [MO_SL] =3D helper_be_ldsl_mmu, + [MO_UQ] =3D helper_be_ldq_mmu, +#else + [MO_UW] =3D helper_le_lduw_mmu, + [MO_SW] =3D helper_le_ldsw_mmu, + [MO_UL] =3D helper_le_ldul_mmu, + [MO_UQ] =3D helper_le_ldq_mmu, + [MO_SL] =3D helper_le_ldsl_mmu, #endif }; =20 -static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] =3D { +static void * const qemu_st_helpers[MO_SIZE + 1] =3D { [MO_UB] =3D helper_ret_stb_mmu, - [MO_LEUW] =3D helper_le_stw_mmu, - [MO_LEUL] =3D helper_le_stl_mmu, - [MO_LEUQ] =3D helper_le_stq_mmu, - [MO_BEUW] =3D helper_be_stw_mmu, - [MO_BEUL] =3D helper_be_stl_mmu, - [MO_BEUQ] =3D helper_be_stq_mmu, +#if HOST_BIG_ENDIAN + [MO_UW] =3D helper_be_stw_mmu, + [MO_UL] =3D helper_be_stl_mmu, + [MO_UQ] =3D helper_be_stq_mmu, +#else + [MO_UW] =3D helper_le_stw_mmu, + [MO_UL] =3D helper_le_stl_mmu, + [MO_UQ] =3D helper_le_stq_mmu, +#endif }; =20 /* We have four temps, we might as well expose three of them. */ @@ -1134,7 +1138,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) =20 tcg_out_ld_helper_args(s, l, &ldst_helper_param); =20 - tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], fals= e); + tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); /* delay slot */ tcg_out_nop(s); =20 @@ -1164,7 +1168,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) =20 tcg_out_st_helper_args(s, l, &ldst_helper_param); =20 - tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], false= ); + tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); /* delay slot */ tcg_out_nop(s); =20 @@ -1379,52 +1383,19 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, TCGReg base, MemOp opc, TCGType type) { - switch (opc & (MO_SSIZE | MO_BSWAP)) { + switch (opc & MO_SSIZE) { case MO_UB: tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); break; case MO_SB: tcg_out_opc_imm(s, OPC_LB, lo, base, 0); break; - case MO_UW | MO_BSWAP: - tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); - tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OZ); - break; case MO_UW: tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); break; - case MO_SW | MO_BSWAP: - tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); - tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OS); - break; case MO_SW: tcg_out_opc_imm(s, OPC_LH, lo, base, 0); break; - case MO_UL | MO_BSWAP: - if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64) { - if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); - tcg_out_bswap32(s, lo, lo, TCG_BSWAP_IZ | TCG_BSWAP_OZ); - } else { - tcg_out_bswap_subr(s, bswap32u_addr); - /* delay slot */ - tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0); - tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); - } - break; - } - /* FALLTHRU */ - case MO_SL | MO_BSWAP: - if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, OPC_LW, lo, base, 0); - tcg_out_bswap32(s, lo, lo, 0); - } else { - tcg_out_bswap_subr(s, bswap32_addr); - /* delay slot */ - tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); - tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3); - } - break; case MO_UL: if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64) { tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); @@ -1434,35 +1405,6 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TC= GReg lo, TCGReg hi, case MO_SL: tcg_out_opc_imm(s, OPC_LW, lo, base, 0); break; - case MO_UQ | MO_BSWAP: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, OPC_LD, lo, base, 0); - tcg_out_bswap64(s, lo, lo); - } else { - tcg_out_bswap_subr(s, bswap64_addr); - /* delay slot */ - tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0); - tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); - } - } else if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); - tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); - tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); - tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); - } else { - tcg_out_bswap_subr(s, bswap32_addr); - /* delay slot */ - tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); - tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4); - tcg_out_bswap_subr(s, bswap32_addr); - /* delay slot */ - tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); - tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); - } - break; case MO_UQ: /* Prefer to load from offset 0 first, but allow for overlap. */ if (TCG_TARGET_REG_BITS =3D=3D 64) { @@ -1487,25 +1429,20 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, = TCGReg lo, TCGReg hi, const MIPSInsn lw2 =3D MIPS_BE ? OPC_LWR : OPC_LWL; const MIPSInsn ld1 =3D MIPS_BE ? OPC_LDL : OPC_LDR; const MIPSInsn ld2 =3D MIPS_BE ? OPC_LDR : OPC_LDL; + bool sgn =3D opc & MO_SIGN; =20 - bool sgn =3D (opc & MO_SIGN); - - switch (opc & (MO_SSIZE | MO_BSWAP)) { - case MO_SW | MO_BE: - case MO_UW | MO_BE: - tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); - tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); - if (use_mips32r2_instructions) { - tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); - } else { - tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); - tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); - } - break; - - case MO_SW | MO_LE: - case MO_UW | MO_LE: - if (use_mips32r2_instructions && lo !=3D base) { + switch (opc & MO_SIZE) { + case MO_16: + if (HOST_BIG_ENDIAN) { + tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); + tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); + if (use_mips32r2_instructions) { + tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); + } else { + tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); + tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0); + } + } else if (use_mips32r2_instructions && lo !=3D base) { tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); @@ -1517,8 +1454,7 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TC= GReg lo, TCGReg hi, } break; =20 - case MO_SL: - case MO_UL: + case MO_32: tcg_out_opc_imm(s, lw1, lo, base, 0); tcg_out_opc_imm(s, lw2, lo, base, 3); if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64 && != sgn) { @@ -1526,28 +1462,7 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, T= CGReg lo, TCGReg hi, } break; =20 - case MO_UL | MO_BSWAP: - case MO_SL | MO_BSWAP: - if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, lw1, lo, base, 0); - tcg_out_opc_imm(s, lw2, lo, base, 3); - tcg_out_bswap32(s, lo, lo, - TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D T= CG_TYPE_I64 - ? (sgn ? TCG_BSWAP_OS : TCG_BSWAP_OZ) : 0); - } else { - const tcg_insn_unit *subr =3D - (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64= && !sgn - ? bswap32u_addr : bswap32_addr); - - tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0); - tcg_out_bswap_subr(s, subr); - /* delay slot */ - tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 3); - tcg_out_mov(s, type, lo, TCG_TMP3); - } - break; - - case MO_UQ: + case MO_64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_opc_imm(s, ld1, lo, base, 0); tcg_out_opc_imm(s, ld2, lo, base, 7); @@ -1559,42 +1474,6 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, T= CGReg lo, TCGReg hi, } break; =20 - case MO_UQ | MO_BSWAP: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, ld1, lo, base, 0); - tcg_out_opc_imm(s, ld2, lo, base, 7); - tcg_out_bswap64(s, lo, lo); - } else { - tcg_out_opc_imm(s, ld1, TCG_TMP0, base, 0); - tcg_out_bswap_subr(s, bswap64_addr); - /* delay slot */ - tcg_out_opc_imm(s, ld2, TCG_TMP0, base, 7); - tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); - } - } else if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0); - tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3); - tcg_out_opc_imm(s, lw1, TCG_TMP1, base, 4 + 0); - tcg_out_opc_imm(s, lw2, TCG_TMP1, base, 4 + 3); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); - tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); - tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); - } else { - tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0); - tcg_out_bswap_subr(s, bswap32_addr); - /* delay slot */ - tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3); - tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 4 + 0); - tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); - tcg_out_bswap_subr(s, bswap32_addr); - /* delay slot */ - tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 4 + 3); - tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); - } - break; - default: g_assert_not_reached(); } @@ -1627,50 +1506,16 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, TCGReg base, MemOp opc) { - /* Don't clutter the code below with checks to avoid bswapping ZERO. = */ - if ((lo | hi) =3D=3D 0) { - opc &=3D ~MO_BSWAP; - } - - switch (opc & (MO_SIZE | MO_BSWAP)) { + switch (opc & MO_SIZE) { case MO_8: tcg_out_opc_imm(s, OPC_SB, lo, base, 0); break; - - case MO_16 | MO_BSWAP: - tcg_out_bswap16(s, TCG_TMP1, lo, 0); - lo =3D TCG_TMP1; - /* FALLTHRU */ case MO_16: tcg_out_opc_imm(s, OPC_SH, lo, base, 0); break; - - case MO_32 | MO_BSWAP: - tcg_out_bswap32(s, TCG_TMP3, lo, 0); - lo =3D TCG_TMP3; - /* FALLTHRU */ case MO_32: tcg_out_opc_imm(s, OPC_SW, lo, base, 0); break; - - case MO_64 | MO_BSWAP: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_bswap64(s, TCG_TMP3, lo); - tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0); - } else if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo); - tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); - tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); - tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0); - tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4); - } else { - tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0); - tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0); - tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0); - tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4); - } - break; case MO_64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_opc_imm(s, OPC_SD, lo, base, 0); @@ -1679,7 +1524,6 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4); } break; - default: g_assert_not_reached(); } @@ -1693,54 +1537,18 @@ static void tcg_out_qemu_st_unalign(TCGContext *s, = TCGReg lo, TCGReg hi, const MIPSInsn sd1 =3D MIPS_BE ? OPC_SDL : OPC_SDR; const MIPSInsn sd2 =3D MIPS_BE ? OPC_SDR : OPC_SDL; =20 - /* Don't clutter the code below with checks to avoid bswapping ZERO. = */ - if ((lo | hi) =3D=3D 0) { - opc &=3D ~MO_BSWAP; - } - - switch (opc & (MO_SIZE | MO_BSWAP)) { - case MO_16 | MO_BE: + switch (opc & MO_SIZE) { + case MO_16: tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); - tcg_out_opc_imm(s, OPC_SB, TCG_TMP0, base, 0); - tcg_out_opc_imm(s, OPC_SB, lo, base, 1); + tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, = 0); + tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, = 1); break; =20 - case MO_16 | MO_LE: - tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); - tcg_out_opc_imm(s, OPC_SB, lo, base, 0); - tcg_out_opc_imm(s, OPC_SB, TCG_TMP0, base, 1); - break; - - case MO_32 | MO_BSWAP: - tcg_out_bswap32(s, TCG_TMP3, lo, 0); - lo =3D TCG_TMP3; - /* fall through */ case MO_32: tcg_out_opc_imm(s, sw1, lo, base, 0); tcg_out_opc_imm(s, sw2, lo, base, 3); break; =20 - case MO_64 | MO_BSWAP: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_bswap64(s, TCG_TMP3, lo); - lo =3D TCG_TMP3; - } else if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? hi : lo); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? lo : hi); - tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); - tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); - hi =3D MIPS_BE ? TCG_TMP0 : TCG_TMP1; - lo =3D MIPS_BE ? TCG_TMP1 : TCG_TMP0; - } else { - tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0); - tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 0 + 0); - tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 0 + 3); - tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0); - tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 4 + 0); - tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 4 + 3); - break; - } - /* fall through */ case MO_64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_opc_imm(s, sd1, lo, base, 0); --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683357921; cv=none; d=zohomail.com; s=zohoarc; b=iwwM7YBZvdLcrckLNXS2g8xBJZZQUAKpp42kVXoTSlu7PRsqWc+T1KB3MJYatO1SEgFrHJ4T7OmeLq8qOO/FQJiQtFDjL8xiciuOnFBmi5STHW3a4j+0XJTbI6LLxEKU5NJzEPpUE0Xf2DjHRaJp9uuA8xaXf6s4Tiq+4mylG18= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683357921; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=64H1HdxJ2Vo9fMDDBGxTfjpGZYN3L1dEu1eUYP7zZpo=; b=AMAMz/zY7DNRZgaVF+UixeGVYpDxn383TDPQWI207DL/mlp/UfZGnYpuypUGyRe/VdA6HqbiW+NjtVkmL1slMNFIPZBHiSTyPFIWHYxpC/8HZyopMAnB0jsZD/hTpcE9qgpOcV3R2LfFnvrqt4dz5Wx6G6lXnfECq93PurmyC/w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683357921708127.49469507461151; Sat, 6 May 2023 00:25:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCGF-0004wL-KR; Sat, 06 May 2023 03:23:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCGE-0004sT-31 for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:18 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFr-0004Tn-1N for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:16 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-30639daee76so1725661f8f.1 for ; Sat, 06 May 2023 00:22:54 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357773; x=1685949773; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=64H1HdxJ2Vo9fMDDBGxTfjpGZYN3L1dEu1eUYP7zZpo=; b=ky2YCrj7nprVSv+K8+hY7vYElXahHAbysB5tyFC89LHGUxORGeWj+oLX8m9pzG6kS5 m6pGvcdZjKKtCZ6YjOVS83sAbUf4eXoeFNHbnLsLs/qfb6gpP7Ag4e+yC4ZxchR5V1lI D97gm72qSPsgcss/pA/gp9GWJHnJaO1v7E9aKTl/LNBHj6FrbLg++1ZNviZXRt5Bm4Xb Rd0dASC4qerJXjcdh6w3yaaeQr75qKmR3rVLXu4kkObz7app4mMDYBmY0b7Z4hy2OOdg FKbcEDdGTzbQpFgUvrVw0RL+m7B2uTDJxZTSKBNm7puMrXbMK948ScX9JsBke0mcRAw8 uxwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357773; x=1685949773; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=64H1HdxJ2Vo9fMDDBGxTfjpGZYN3L1dEu1eUYP7zZpo=; b=jhgNjfgPhaRwRh0wbyzxBB39X7cXBG0f1ZnhSXECEN8V4oVNI0TFpTtSYVmtkdD3Sr 7soUuXd/PK7c2zzmditz8Hx4OGM6r63RkEjkj5wQatTHKlnWE3KkseQeyzEuJEMBJ0vc tOx7m0ckLAtf4qvazqfCwD2Et1uSTI4pF8ZBS2zBICPgxPQrIAp7IiILajo1b3f40k2j RuXMutU0yF8yQp0zVPm0JL4VMlHaWV9zWNJYs2FIHghLCtojFTyUzjMIgW8kAVtudibm GzJhybagYSswMcz8PJ83GzJN7k+ZNPPAtQzCvLfP0QGeOBSjpvVX59w85/vgtyPfXYyB DLug== X-Gm-Message-State: AC+VfDwDwl4+PXUh6tx7t2EnA10uvDhok/Me1N9D8uhGxjNMEyRsJqNb KOs1luyjS3JviM/A+hZluDOWzySpekZKwm2l/9HpMQ== X-Google-Smtp-Source: ACHHUZ6cSsxoSW4ssoD4taDX/pqF0KXwUKGponZZwhL1XCkNgAqQX3jL7rlM+zUIBN8bJV+sttqvoQ== X-Received: by 2002:adf:e80e:0:b0:2f9:85ee:e031 with SMTP id o14-20020adfe80e000000b002f985eee031mr2866309wrm.26.1683357773603; Sat, 06 May 2023 00:22:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 22/30] tcg/mips: Reorg tlb load within prepare_host_addr Date: Sat, 6 May 2023 08:22:27 +0100 Message-Id: <20230506072235.597467-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683357922966100003 Content-Type: text/plain; charset="utf-8" Compare the address vs the tlb entry with sign-extended values. This simplifies the page+alignment mask constant, and the generation of the last byte address for the misaligned test. Move the tlb addend load up, and the zero-extension down. This frees up a register, which allows us use TMP3 as the returned base address register instead of A0, which we were using as a 5th temporary. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/mips/tcg-target.c.inc | 38 ++++++++++++++++++-------------------- 1 file changed, 18 insertions(+), 20 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 31d58e1977..695c137023 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -370,6 +370,8 @@ typedef enum { ALIAS_PADDI =3D sizeof(void *) =3D=3D 4 ? OPC_ADDIU : OPC_DADDIU, ALIAS_TSRL =3D TARGET_LONG_BITS =3D=3D 32 || TCG_TARGET_REG_BITS = =3D=3D 32 ? OPC_SRL : OPC_DSRL, + ALIAS_TADDI =3D TARGET_LONG_BITS =3D=3D 32 || TCG_TARGET_REG_BITS = =3D=3D 32 + ? OPC_ADDIU : OPC_DADDIU, } MIPSInsn; =20 /* @@ -1263,14 +1265,12 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, int add_off =3D offsetof(CPUTLBEntry, addend); int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write); - target_ulong tlb_mask; =20 ldst =3D new_ldst_label(s); ldst->is_ld =3D is_ld; ldst->oi =3D oi; ldst->addrlo_reg =3D addrlo; ldst->addrhi_reg =3D addrhi; - base =3D TCG_REG_A0; =20 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); @@ -1290,15 +1290,12 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); } else { - tcg_out_ldst(s, (TARGET_LONG_BITS =3D=3D 64 ? OPC_LD - : TCG_TARGET_REG_BITS =3D=3D 64 ? OPC_LWU : OPC_L= W), - TCG_TMP0, TCG_TMP3, cmp_off); + tcg_out_ld(s, TCG_TYPE_TL, TCG_TMP0, TCG_TMP3, cmp_off); } =20 - /* Zero extend a 32-bit guest address for a 64-bit host. */ - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addrlo); - addrlo =3D base; + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + /* Load the tlb addend for the fast path. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); } =20 /* @@ -1306,18 +1303,18 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, * For unaligned accesses, compare against the end of the access to * verify that it does not cross a page boundary. */ - tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; - tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, tlb_mask); - if (a_mask >=3D s_mask) { - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo); - } else { - tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP2, addrlo, s_mask - a_mask); + tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, TARGET_PAGE_MASK | a_mask); + if (a_mask < s_mask) { + tcg_out_opc_imm(s, ALIAS_TADDI, TCG_TMP2, addrlo, s_mask - a_mask); tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); + } else { + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo); } =20 - if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { - /* Load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); + /* Zero extend a 32-bit guest address for a 64-bit host. */ + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_TMP2, addrlo); + addrlo =3D TCG_TMP2; } =20 ldst->label_ptr[0] =3D s->code_ptr; @@ -1329,14 +1326,15 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); =20 /* Load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); =20 ldst->label_ptr[1] =3D s->code_ptr; tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0); } =20 /* delay slot */ - tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrlo); + base =3D TCG_TMP3; + tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo); #else if (a_mask && (use_mips32r6_instructions || a_bits !=3D s_bits)) { ldst =3D new_ldst_label(s); --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683357915; cv=none; d=zohomail.com; s=zohoarc; b=P7svtHupJ5jY93wUNtEx/GdzaDKLhKMzsY1z43Edht2zzSFn0JKpzX2SLINAgkVvvFKect6ILNID3gQPATo/JUo9v6PzbM9tAQrKk8C+s6mem/BWqKXXQYOwjm73ZA2NNNlncNhPKuRyBFJt4T1cTiWDBmehQ3JyC2FBMVg9FaM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683357915; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=k8auTOlyLXqTfCckvUiWN7Zc35mefBco1qqtfpVHTz4=; b=GYVQsG7Pud3L3y05S0gCspWmDr7zwNpY29uUyoaDi3xuKF1nLfAKZrXeuf9Z4I3jydbFMgRzCuZPUQY03Dw6eB/n55h2vSKDOLcjoNmijKF7xhuyiqhPhoLqMTGdjndhjjUuV1pj07X/WhPmzZg5m9PIBMczBncovhRLxSGTet4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683357915414845.6299140765226; Sat, 6 May 2023 00:25:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCGH-000506-H6; Sat, 06 May 2023 03:23:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCGE-0004uc-QP for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:18 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFr-0004UU-Js for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:18 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-30786c6082dso243131f8f.2 for ; Sat, 06 May 2023 00:22:55 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357774; x=1685949774; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=k8auTOlyLXqTfCckvUiWN7Zc35mefBco1qqtfpVHTz4=; b=x+yANA2bNIHsW5uCAzNLl6dZO+XABhxnF1ydGZETotZlZtDjoZCAh3oKLQbqG9JIv6 6/hPGUMpcDCMo7/Gl3xk/mfhI0HTIQnQYA1WbIRsVCXVOH3OLuWiqJ8ORFrHbzqLwsyg oac2lkaSZGrksejngXcNjH/24V9F7m6kmjLxzgjqTRSqbrHlLofFWhLekAGFffLBXiUd NuDpy0Ypf7Osui1ZAo9PvlZlX0/HSDpKy0cJecOxFjOJLVCDojrArd0HqfIxAYuIyTdJ UtYwb+2Bmvm2Z3xH4aG8MajyknkpGWpGrmzzTht+DTxdFnhb4Qzy1Z0t+bMzdtAcAM2R oKyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357774; x=1685949774; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k8auTOlyLXqTfCckvUiWN7Zc35mefBco1qqtfpVHTz4=; b=TYViDvNHozGq4L1RKfppdVd1je95vmL0lExqaCwcrt+xH+kwqa5/1RRYP8J3p+5Aw6 OxQTdbV4oAQbqhNchPSpzwS3a2HVWmt8vkRnWG/cHYvF+pEWF9hxc9ZFh4o/0TsLyDa2 jimgoFZ5i0BTfq6+cBc4yNOjHl4OB9BrZo5+XCJdK9Pv8H/7/1wBY9zICqa94y+WhZK1 zd253s7hMU8C8DSuVS/qYZneVdJQzwb5KzokoY8PvwvW7rXVL/kVp12rv1h6mPQSlhVk oLrYA5Awll3zbAMmOgzMtZa78reEPYR2rZiVHdN4IOORuIglN+yJYuXaYDzvFk2tp92Z T1Dg== X-Gm-Message-State: AC+VfDwagkclvinnbmh1VRj7cTN7k9v/fNOPxlc+4fcQa7v/AK+PDsx7 IZlFteo5mLe2hzg8xwhTqbuSqatC068tpxkf8e2Iuw== X-Google-Smtp-Source: ACHHUZ60T7Wrr3A3JmJY0cOff/9gWNAo7COtx71m6eAJAadaIaiGdQIMI0alJ7f0Ot/mObtFVVnGbA== X-Received: by 2002:adf:fbc8:0:b0:306:2b40:1258 with SMTP id d8-20020adffbc8000000b003062b401258mr2575885wrs.21.1683357774246; Sat, 06 May 2023 00:22:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 23/30] tcg/mips: Simplify constraints on qemu_ld/st Date: Sat, 6 May 2023 08:22:28 +0100 Message-Id: <20230506072235.597467-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683357917466100003 Content-Type: text/plain; charset="utf-8" The softmmu tlb uses TCG_REG_TMP[0-3], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, and have eliminated use of A0, we can allow any allocatable reg. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/mips/tcg-target-con-set.h | 13 +++++-------- tcg/mips/tcg-target-con-str.h | 2 -- tcg/mips/tcg-target.c.inc | 30 ++++++++---------------------- 3 files changed, 13 insertions(+), 32 deletions(-) diff --git a/tcg/mips/tcg-target-con-set.h b/tcg/mips/tcg-target-con-set.h index fe3e868a2f..864034f468 100644 --- a/tcg/mips/tcg-target-con-set.h +++ b/tcg/mips/tcg-target-con-set.h @@ -12,15 +12,13 @@ C_O0_I1(r) C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) -C_O0_I2(SZ, S) -C_O0_I3(SZ, S, S) -C_O0_I3(SZ, SZ, S) +C_O0_I3(rZ, r, r) +C_O0_I3(rZ, rZ, r) C_O0_I4(rZ, rZ, rZ, rZ) -C_O0_I4(SZ, SZ, S, S) -C_O1_I1(r, L) +C_O0_I4(rZ, rZ, r, r) C_O1_I1(r, r) C_O1_I2(r, 0, rZ) -C_O1_I2(r, L, L) +C_O1_I2(r, r, r) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) C_O1_I2(r, r, rIK) @@ -30,7 +28,6 @@ C_O1_I2(r, rZ, rN) C_O1_I2(r, rZ, rZ) C_O1_I4(r, rZ, rZ, rZ, 0) C_O1_I4(r, rZ, rZ, rZ, rZ) -C_O2_I1(r, r, L) -C_O2_I2(r, r, L, L) +C_O2_I1(r, r, r) C_O2_I2(r, r, r, r) C_O2_I4(r, r, rZ, rZ, rN, rN) diff --git a/tcg/mips/tcg-target-con-str.h b/tcg/mips/tcg-target-con-str.h index e4b2965c72..413c280a7a 100644 --- a/tcg/mips/tcg-target-con-str.h +++ b/tcg/mips/tcg-target-con-str.h @@ -9,8 +9,6 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) -REGS('L', ALL_QLOAD_REGS) -REGS('S', ALL_QSTORE_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 695c137023..5ad9867882 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -176,20 +176,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, #define TCG_CT_CONST_WSZ 0x2000 /* word size */ =20 #define ALL_GENERAL_REGS 0xffffffffu -#define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0)) - -#ifdef CONFIG_SOFTMMU -#define ALL_QLOAD_REGS \ - (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2)) -#define ALL_QSTORE_REGS \ - (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \ - ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \ - : (1 << TCG_REG_A1))) -#else -#define ALL_QLOAD_REGS NOA0_REGS -#define ALL_QSTORE_REGS NOA0_REGS -#endif - =20 static bool is_p2m1(tcg_target_long val) { @@ -2232,18 +2218,18 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_qemu_ld_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); + ? C_O1_I1(r, r) : C_O1_I2(r, r, r)); case INDEX_op_qemu_st_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S)); + ? C_O0_I2(rZ, r) : C_O0_I3(rZ, r, r)); case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) - : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(r, r, L) - : C_O2_I2(r, r, L, L)); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) + : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(r, r, r) + : C_O2_I2(r, r, r, r)); case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(SZ, S) - : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(SZ, SZ, S) - : C_O0_I4(SZ, SZ, S, S)); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(rZ, r) + : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(rZ, rZ, r) + : C_O0_I4(rZ, rZ, r, r)); =20 default: g_assert_not_reached(); --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683358139; cv=none; d=zohomail.com; s=zohoarc; b=lU8Lo7oncx5+cnc2Mxa4mnyWtZuDG1OUAlTdQ6ncSKTDi9sYY6w5t2yUIiNbsq8MPn94lqCdnHvXKZWtEW8L/icF5rumKtmy/jTRO+8bxYKbUQO/wkH3wckepTBohyCQaaYKw+TAqrzbqanpQxhQovYo8kMbk8A+o5qplCjv2ac= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683358139; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eTTppFvpCeQOyLgVasYHuYDrv+swYGMzo0e4SF2rHxM=; b=k6l8T3b/TBQHDYivZzLsClRg1r7RNTCL4kwtMxPev+d7CUDLmD3oBYTXZb1vOJAqNIblmfIsgEQU2g9I9yUhirJ9hZU9d+UvHaJlUn/zudLkDFev0x+ww1/UU1dzRY9c4zrcHdrB1KkOi07+/Su13oXAe5VKcr8WowsRme7rrY4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683358139889951.971352154246; Sat, 6 May 2023 00:28:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCGd-00063N-5L; Sat, 06 May 2023 03:23:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCGV-0005ec-Ip for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:35 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFs-0004Uy-H2 for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:35 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-3075e802738so2157540f8f.1 for ; Sat, 06 May 2023 00:22:55 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357775; x=1685949775; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eTTppFvpCeQOyLgVasYHuYDrv+swYGMzo0e4SF2rHxM=; b=DUzw+UaOPPxYVzNmzhu2Aohkpl2pf/iKeo5HhhI7hvbKBjB9mSupc4DOhN0LaRifDU iMJzkbjAvU9SLSnwtLtp9bpNTMcrKJevN9qsgJmfj/etWlKIY22gACJNEozb2KSL6PW2 yYoKCSbgzYmMSOSu9hbDsGK0tLwuLxmysE4IKR9SZoJeS2mVKrPuBzAxC9xqWwu4O9s2 aJ3e4UULg7LdxUyosKYI56RjzNxulPZJnQ6ejHqqRH5XVWuLZjE6Eshzm4lMmBC6dMjN APCKuZ2u2eiMu8IXUREHo1EPiYPzEZuMT5PlLJXWqswkWnJm2BcmlnE2Rh+aXhcYHSc/ SacA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357775; x=1685949775; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eTTppFvpCeQOyLgVasYHuYDrv+swYGMzo0e4SF2rHxM=; b=TMQnOt9A/q1qM/dfDPXZ1/1DqxUawIqHIqnn1lAZ+WqS4+P7Vwjr9CjUVxwxzeF2zQ 6nwz32U1X70dIAgUdMM/CYIPFjzf1dMIyeBHe4HMHyW2NzdhF9B3CWAShmp+zX+Rnt/f XdtMObl93IU0gtQaY73SvtQF4/PofxD/tqC1n7LwDr9rI1U9I5iYf40ilRDIVdr8/J8b 8aVeHov4ZHj2VX40vmh0kZEUT+XzRn8X38n9xpV77fiymZkFQ/o+JMwR2XmMwcvQCsUF PayLAhjfjwpcWI1ewSbzvdDJTA6E3TWAJdcCKYtZzl4zuGgnfUZL/4rTfWvMvknCQUKx wfJw== X-Gm-Message-State: AC+VfDziH4dk1A8RRp/m4ba4vKe7hmrBHAsjawo2E+1gvCw3cmzfmUku TQTtXz1Hxiwq/zuZWlPyBawTgOqPP6J3K9UPWgc5xA== X-Google-Smtp-Source: ACHHUZ7JW9Askfgc8QwSK8XEJLsRIBk/6sZcXB6eGdvXMkd5IV6rLNSTo/BnMwMcK17h/fptCI2k5g== X-Received: by 2002:a5d:53c7:0:b0:306:2db9:a33a with SMTP id a7-20020a5d53c7000000b003062db9a33amr3169248wrw.33.1683357775029; Sat, 06 May 2023 00:22:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Daniel Henrique Barboza Subject: [PATCH v5 24/30] tcg/ppc: Reorg tcg_out_tlb_read Date: Sat, 6 May 2023 08:22:29 +0100 Message-Id: <20230506072235.597467-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683358141608100001 Content-Type: text/plain; charset="utf-8" Allocate TCG_REG_TMP2. Use R0, TMP1, TMP2 instead of any of the normally allocated registers for the tlb load. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/ppc/tcg-target.c.inc | 84 ++++++++++++++++++++++++---------------- 1 file changed, 51 insertions(+), 33 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 042136fee7..6850ecbc80 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -68,6 +68,7 @@ #else # define TCG_REG_TMP1 TCG_REG_R12 #endif +#define TCG_REG_TMP2 TCG_REG_R11 =20 #define TCG_VEC_TMP1 TCG_REG_V0 #define TCG_VEC_TMP2 TCG_REG_V1 @@ -2015,13 +2016,11 @@ static TCGReg ldst_ra_gen(TCGContext *s, const TCGL= abelQemuLdst *l, int arg) /* * For the purposes of ppc32 sorting 4 input registers into 4 argument * registers, there is an outside chance we would require 3 temps. - * Because of constraints, no inputs are in r3, and env will not be - * placed into r3 until after the sorting is done, and is thus free. */ static const TCGLdstHelperParam ldst_helper_param =3D { .ra_gen =3D ldst_ra_gen, .ntmp =3D 3, - .tmp =3D { TCG_REG_TMP1, TCG_REG_R0, TCG_REG_R3 } + .tmp =3D { TCG_REG_TMP1, TCG_REG_TMP2, TCG_REG_R0 } }; =20 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) @@ -2135,41 +2134,44 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_AREG0, table_off); =20 /* Extract the page index, shifted into place for tlb index. */ if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_shri32(s, TCG_REG_TMP1, addrlo, + tcg_out_shri32(s, TCG_REG_R0, addrlo, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); } else { - tcg_out_shri64(s, TCG_REG_TMP1, addrlo, + tcg_out_shri64(s, TCG_REG_R0, addrlo, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); } - tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1)); + tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0)); =20 - /* Load the TLB comparator. */ + /* Load the (low part) TLB comparator into TMP2. */ if (cmp_off =3D=3D 0 && TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { uint32_t lxu =3D (TCG_TARGET_REG_BITS =3D=3D 32 || TARGET_LONG_BIT= S =3D=3D 32 ? LWZUX : LDUX); - tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4)); + tcg_out32(s, lxu | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2)); } else { - tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4)); + tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2)); if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off = + 4); - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, + TCG_REG_TMP1, cmp_off + 4 * HOST_BIG_ENDIAN); } else { - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off); + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off= ); } } =20 - /* Load the TLB addend for use on the fast path. Do this asap - to minimize any load use delay. */ - h->base =3D TCG_REG_R3; - tcg_out_ld(s, TCG_TYPE_PTR, h->base, TCG_REG_R3, - offsetof(CPUTLBEntry, addend)); + /* + * Load the TLB addend for use on the fast path. + * Do this asap to minimize any load use delay. + */ + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, + offsetof(CPUTLBEntry, addend)); + } =20 - /* Clear the non-page, non-alignment bits from the address */ + /* Clear the non-page, non-alignment bits from the address in R0. */ if (TCG_TARGET_REG_BITS =3D=3D 32) { /* We don't support unaligned accesses on 32-bits. * Preserve the bottom bits and thus trigger a comparison @@ -2200,9 +2202,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, if (TARGET_LONG_BITS =3D=3D 32) { tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); - /* Zero-extend the address for use in the final address. */ - tcg_out_ext32u(s, TCG_REG_R4, addrlo); - addrlo =3D TCG_REG_R4; } else if (a_bits =3D=3D 0) { tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS= ); } else { @@ -2211,21 +2210,36 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BIT= S, 0); } } - h->index =3D addrlo; =20 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, + /* Low part comparison into cr7. */ + tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 0, 7, TCG_TYPE_I32); - tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32= ); + + /* Load the high part TLB comparator into TMP2. */ + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1, + cmp_off + 4 * !HOST_BIG_ENDIAN); + + /* Load addend, deferred for this case. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, + offsetof(CPUTLBEntry, addend)); + + /* High part comparison into cr6. */ + tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_TMP2, 0, 6, TCG_TYPE_I= 32); + + /* Combine comparisons into cr7. */ tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); } else { - tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, + /* Full comparison into cr7. */ + tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 0, 7, TCG_TYPE_TL); } =20 /* Load a pointer into the current opcode w/conditional branch-link. */ ldst->label_ptr[0] =3D s->code_ptr; tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); + + h->base =3D TCG_REG_TMP1; #else if (a_bits) { ldst =3D new_ldst_label(s); @@ -2243,13 +2257,16 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, } =20 h->base =3D guest_base ? TCG_GUEST_BASE_REG : 0; - h->index =3D addrlo; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); - h->index =3D TCG_REG_TMP1; - } #endif =20 + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + /* Zero-extend the guest address for use in the host address. */ + tcg_out_ext32u(s, TCG_REG_R0, addrlo); + h->index =3D TCG_REG_R0; + } else { + h->index =3D addrlo; + } + return ldst; } =20 @@ -3901,7 +3918,8 @@ static void tcg_target_init(TCGContext *s) #if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS =3D=3D 64 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ #endif - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1); tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2); if (USE_REG_TB) { --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683358093; cv=none; d=zohomail.com; s=zohoarc; b=F9yhiDuKeRDTCW8Wx/RHdFuTULGilFfpaMKQcO5IAWc2DBEsqTZ8e2sVlg6X7TElwb+uowl9+zYDBy3qkmz81oY8jovBJyg4RZELx/IgL5F6GJ1h989aqmEY3uqsJFMThaTN00QIKjO9hA5k6sgF88BvcoFNLoHfh6ITCmjA/J8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683358093; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=M0CeyWjMqe57NR22sbQHD4MYtLkRo2vj3jA4zBvWRdg=; b=AI/+7OWMLdl4DcAJK4a4L9x45uKAUPvHkKmUrVA2R3ra+GgN18FeCibDVwf+yeqzsj9b0MTzEiq2v7IV+6pXAig8nhH32ANPKjfdVSiTvLWhEKyuX9e3p1bO4E0YFMlhUz0PAV7j4owTiZuk8qGrhFZxlH/5EjqVa5v5tKMq5Wc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683358093453644.8829233301458; Sat, 6 May 2023 00:28:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCGZ-0005tW-B2; Sat, 06 May 2023 03:23:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCGT-0005SQ-1X for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:35 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFu-0004Ve-8N for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:32 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-3f420618d5bso113745e9.1 for ; Sat, 06 May 2023 00:22:57 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357776; x=1685949776; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=M0CeyWjMqe57NR22sbQHD4MYtLkRo2vj3jA4zBvWRdg=; b=Jo1c1OocbpZioobhHwIxjN7vHeowKGFTA35RtHXKEcJ2EX0kVUCgm7eptIQbvUTNLP 8Sw1voQg0whDbg3xkPLgD6Lk+kMJyqWnKB4Dcb9N0GezG46MbNTik1fB3zQElzbKRAA0 19eevzWjJHNedrffklD2xmXfLtaKlj0pO3DGo2N4KrqOQNR5uLczrABz0cVcw2A7xC0k wMCgkh+at9fYtOEi1YOX5D4GgRgNOrVVsmT1o0g3kOWAj5YPFTbuchUX6wAw3gs8OmR8 i4kAqj8u3GWLehqvwgCdM49gEhBulFL0MA8FyocCNs19F7684zXHttplvAN+FvXvup9+ ek1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357776; x=1685949776; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M0CeyWjMqe57NR22sbQHD4MYtLkRo2vj3jA4zBvWRdg=; b=CYhqqowWot9u9oY3Wy+d6IztbgJGoKqe+ndb0TTjKe0wsuWC5qFz+4Sp/+Cy27IT1f MAqGHk3z9jIsN5G5LzQ619Xvmn381nXSDD+d34o09B254Set2ciHeicUfsEXl5XaNeOG IfRYPfdxAHjp7DoD4gFU2tuHNUlrYOa0yxzZZ/3XVvfYKqFZfBxlBqdeuqVosoco5wSB VCffBaVPxkJm3CNsEutBSBY4eDaMLD1sGaFPFH+A+wf06RQi/0yIYpXUfvx4+g3tDqS8 rc7RQiglM4cwGfEJbr6g1i67pubMUn70ENuuCJ84glqeflNJ2Jp6AyiAJLlYnfPVinGP kqig== X-Gm-Message-State: AC+VfDyrXQAb/jo05/7n0BZGLPSYseogLyiiDjaClKSSsbvAYZpbvKpm NBMHhaeCH11CTnUUVFX9QpACbZRahmXBX+wvTZkLxw== X-Google-Smtp-Source: ACHHUZ6A2ZYyUkMpjfeif3huU6kMBy4nJPjrPSCLR2DMigpe1xZ1FjHwxMYzIopreOCrEvzHbOVNQA== X-Received: by 2002:a05:600c:2248:b0:3f3:46d9:4046 with SMTP id a8-20020a05600c224800b003f346d94046mr2763963wmm.32.1683357775871; Sat, 06 May 2023 00:22:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Daniel Henrique Barboza Subject: [PATCH v5 25/30] tcg/ppc: Adjust constraints on qemu_ld/st Date: Sat, 6 May 2023 08:22:30 +0100 Message-Id: <20230506072235.597467-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683358094836100007 Content-Type: text/plain; charset="utf-8" The softmmu tlb uses TCG_REG_{TMP1,TMP2,R0}, not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/ppc/tcg-target-con-set.h | 11 ++++------- tcg/ppc/tcg-target-con-str.h | 2 -- tcg/ppc/tcg-target.c.inc | 32 ++++++++++---------------------- 3 files changed, 14 insertions(+), 31 deletions(-) diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h index a1a345883d..f206b29205 100644 --- a/tcg/ppc/tcg-target-con-set.h +++ b/tcg/ppc/tcg-target-con-set.h @@ -12,18 +12,15 @@ C_O0_I1(r) C_O0_I2(r, r) C_O0_I2(r, ri) -C_O0_I2(S, S) C_O0_I2(v, r) -C_O0_I3(S, S, S) +C_O0_I3(r, r, r) C_O0_I4(r, r, ri, ri) -C_O0_I4(S, S, S, S) -C_O1_I1(r, L) +C_O0_I4(r, r, r, r) C_O1_I1(r, r) C_O1_I1(v, r) C_O1_I1(v, v) C_O1_I1(v, vr) C_O1_I2(r, 0, rZ) -C_O1_I2(r, L, L) C_O1_I2(r, rI, ri) C_O1_I2(r, rI, rT) C_O1_I2(r, r, r) @@ -36,7 +33,7 @@ C_O1_I2(v, v, v) C_O1_I3(v, v, v, v) C_O1_I4(r, r, ri, rZ, rZ) C_O1_I4(r, r, r, ri, ri) -C_O2_I1(L, L, L) -C_O2_I2(L, L, L, L) +C_O2_I1(r, r, r) +C_O2_I2(r, r, r, r) C_O2_I4(r, r, rI, rZM, r, r) C_O2_I4(r, r, r, r, rI, rZM) diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h index 298ca20d5b..f3bf030bc3 100644 --- a/tcg/ppc/tcg-target-con-str.h +++ b/tcg/ppc/tcg-target-con-str.h @@ -14,8 +14,6 @@ REGS('A', 1u << TCG_REG_R3) REGS('B', 1u << TCG_REG_R4) REGS('C', 1u << TCG_REG_R5) REGS('D', 1u << TCG_REG_R6) -REGS('L', ALL_QLOAD_REGS) -REGS('S', ALL_QSTORE_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 6850ecbc80..5a4ec0470a 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -93,18 +93,6 @@ #define ALL_GENERAL_REGS 0xffffffffu #define ALL_VECTOR_REGS 0xffffffff00000000ull =20 -#ifdef CONFIG_SOFTMMU -#define ALL_QLOAD_REGS \ - (ALL_GENERAL_REGS & \ - ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5))) -#define ALL_QSTORE_REGS \ - (ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \ - (1 << TCG_REG_R5) | (1 << TCG_REG_R6))) -#else -#define ALL_QLOAD_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3)) -#define ALL_QSTORE_REGS ALL_QLOAD_REGS -#endif - TCGPowerISA have_isa; static bool have_isel; bool have_altivec; @@ -3752,23 +3740,23 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_qemu_ld_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O1_I1(r, L) - : C_O1_I2(r, L, L)); + ? C_O1_I1(r, r) + : C_O1_I2(r, r, r)); =20 case INDEX_op_qemu_st_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O0_I2(S, S) - : C_O0_I3(S, S, S)); + ? C_O0_I2(r, r) + : C_O0_I3(r, r, r)); =20 case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) - : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(L, L, L) - : C_O2_I2(L, L, L, L)); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) + : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(r, r, r) + : C_O2_I2(r, r, r, r)); =20 case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(S, S) - : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(S, S, S) - : C_O0_I4(S, S, S, S)); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(r, r) + : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(r, r, r) + : C_O0_I4(r, r, r, r)); =20 case INDEX_op_add_vec: case INDEX_op_sub_vec: --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683357828; cv=none; d=zohomail.com; s=zohoarc; b=TP2MSAGDOx66VmenKCnKTMF22fMRbl+XROK0E/OOJsA2JKzt05/gI3EsvWFEK/iLf8dv+zCK5QEOvLOdZRwcFbRPZ/gctp4keSH8CpN+23PNkFJdtiGfDmBOrkkBHm8jTejo0mUofSyOOLG+s55Xy15yDkbSo8+h9vOvrW8FaQA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683357828; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3fy0vmCrTrGncYxmSNiskWJCsJlGLSETPcKSq6VV7UU=; b=Uo4N7A7v7FoI3LO6ZtdrgzROXWi22KjDFDFcZz1UyECGOh6o5r5HkEqAVzEMDkfki4t9yaWb4ay/SHEzB4/zzECkso+STGWiJzgMKJD8gfKVu+PVnCC44QyeEONXexNhk4yO0MwdIucIafGPcBsjijJTsv+cvRHyp+yloHz+HOs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683357828613769.6147429295621; Sat, 6 May 2023 00:23:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCGT-0005S1-0q; Sat, 06 May 2023 03:23:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCGP-0005Nw-Sr for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:30 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFt-0004N9-CW for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:29 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-3063208beedso2452836f8f.1 for ; Sat, 06 May 2023 00:22:56 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357776; x=1685949776; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3fy0vmCrTrGncYxmSNiskWJCsJlGLSETPcKSq6VV7UU=; b=UC/Q9hR5AQYAyrfjS2LKyfwcxMPqjhaiWxTYGlWipBbSyqZ01wF296JnKKEhTBQPda ss8GjSgCiKQAqM7QfDdgNWKdr8JkZieDm1jD7xfhI4J+5VFMOcFoJ/bsnmob9YHWD73R l0Z0iUtgrwK7KUX0lhHwrkrhiWxxBlC7mA386HX/OrJoy50+G8smerZZgtLw6g6ig6sv vAkpy+xG6QAK6flps/znbs0S2ECWZOuuvVbZd3s0U9ktHvMWS/b3sC5J+9PCQYdqNLka myQY9L2hmz/EDFxlyJBzU5ymSRhmmL863qUYpxB958JKVABD1uXub5nRT1m/KMezMfeG E5rQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357776; x=1685949776; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3fy0vmCrTrGncYxmSNiskWJCsJlGLSETPcKSq6VV7UU=; b=koGj5UHYziYg8usHpXgsyhKsfV34mBO7Vr0CMwO5nVtJ7X3BEf+yAOrfCCepZ2Efvf /Yuik+JzYy0+b16du078m+6d8X3XBdvJqmu0D8GqlkKM4rvwZCaSVCW9M8vTmfM2sJEu 0JBqZGf5dYiIDXDAVM2Ouil2Ip7E1tP2mcllI5blLD5J6beVBDDFGahFa4XqEoFUUaJs 7mCNXg3kbWqlt/faR0xHsL9yK6W1wUow0s52g2wihXkBHiI14UQTGa0P7YDkXUNrBvCe m58FAkPQTI0LCAU1ZrzpU5wuC/VCA3fARNvsW0PQc7e/sAdvLP2L8hZWqJ50BxAzgGuG pZ8Q== X-Gm-Message-State: AC+VfDytg8cLBUAIXaqseMkzXriD/FQ/dFZWX/CyqgT90hGOV0dlIn0/ vBCUdZWY4m4GS2CCVynVINHzuwPYRWN+OwxaWKCLgw== X-Google-Smtp-Source: ACHHUZ7GC12AEDn1Ft1uzPO2lP11E7I2E3AFECRJcuCd3sxRwb1BKlvyUydH/JkfblgadQeY+7WXkg== X-Received: by 2002:adf:f849:0:b0:306:35d4:566f with SMTP id d9-20020adff849000000b0030635d4566fmr2752644wrq.65.1683357776639; Sat, 06 May 2023 00:22:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Daniel Henrique Barboza Subject: [PATCH v5 26/30] tcg/ppc: Remove unused constraints A, B, C, D Date: Sat, 6 May 2023 08:22:31 +0100 Message-Id: <20230506072235.597467-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683357830138100011 These constraints have not been used for quite some time. Fixes: 77b73de67632 ("Use rem/div[u]_i32 drop div[u]2_i32") Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/ppc/tcg-target-con-str.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h index f3bf030bc3..9dcbc3df50 100644 --- a/tcg/ppc/tcg-target-con-str.h +++ b/tcg/ppc/tcg-target-con-str.h @@ -10,10 +10,6 @@ */ REGS('r', ALL_GENERAL_REGS) REGS('v', ALL_VECTOR_REGS) -REGS('A', 1u << TCG_REG_R3) -REGS('B', 1u << TCG_REG_R4) -REGS('C', 1u << TCG_REG_R5) -REGS('D', 1u << TCG_REG_R6) =20 /* * Define constraint letters for constants: --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683358100; cv=none; d=zohomail.com; s=zohoarc; b=JYl9/JzsJdFVCk+etJ7YndZSLOuFWUXT0XszEsIfnvKnvN2mlCbeg3hQfh/OL4hi9fp/6M2Wkbf/2dYtvu9g2rEjoh33gO7YDBmfOVf8d8Im86e6BgxQYz9tjqZJ3FtY8duHLbsUH9CIMrVGw+UxJh5SUPkNb+up1qbc/t3i1k8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683358100; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=O4O2YAeN9cb5anbyImPMVEQOY1pM7UmSuOPh7iKYeY4=; b=OmI0I9MpymsK6bj24rllz3XqLf4QX51qiB/WwiXDLSRs1gN1Ibz0KXYgsiX5SmA68uumsmYeCdL9K3W1zWoIecM2pWOwGDmXoNS3L3d6j4dIleg+02Q5O/8jgzLWgz6A6HNZRhgcf8tPo3A1TKOkNnKJDo1Vt/hqsxO3R7+DwAc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683358100496192.38945802049284; Sat, 6 May 2023 00:28:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCGY-0005nI-4V; Sat, 06 May 2023 03:23:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCGU-0005bf-Vx for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:35 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFu-0004XB-Nz for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:34 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-30644c18072so1726906f8f.2 for ; Sat, 06 May 2023 00:22:58 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357777; x=1685949777; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=O4O2YAeN9cb5anbyImPMVEQOY1pM7UmSuOPh7iKYeY4=; b=UUB9heQZK2dk3DkWZJ+PK33dPI7Dph7mEO7jvS0vPMU8y9q1tDHSw34jXYSyBh/bkI WXx12h1YirRPxICSp07nqIEzO2XTR+uwCb7FBvVQAHX1RiWLsXXrVxxngrkpE0Xu+ngr SkURFJ42IBa8diQRAj3UDBtGVizvWUJhr/Sou20BFDD5yPj63M1yPTWYwubG6BSta6+h 5m9b344tcSxJLs7I2Iczm8jZBuSVGQ9jJ8ILU4WuF/PPTXAlTj6qEqwVAAg9UOQZ5E1z bZPTXzMBhF9XDDehj1s8wbZHHyGWy2UDyrJ8X8Yf4qtolVvRixtnQIZJ8IvztY4eZQXX fsng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357777; x=1685949777; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=O4O2YAeN9cb5anbyImPMVEQOY1pM7UmSuOPh7iKYeY4=; b=c4Gd3iEZyrHIqwiTHBAi/diuTlMEhxPRiZcS1zACu/vsfc6EfCQv3eYGSmxuzaILQJ gAx3AJQSr8rqC86XiOXWSwFTd2VCMiYYLIYG8wU/hKeVJZGB5IZD2DRnMMmGW7cnSVUl OWUdKYSSIHfWnmux24pL5gXq5QTJC4Tph+vad0Upl8Bm/lmGFoLWlv55sOOn2cpEfmUC 0JMGcC778/nv757p2zudYaSQ8VPmawAG1WPFZAIEZCmxcGpKvy7iU2O1/ee3/RbM/Gqi GYzSOOP6xd1/2cvYDNckbbgZ84Rrj129lyq+bVOf52305sQgE/D9VchgeG1xe8/LMvlN zllw== X-Gm-Message-State: AC+VfDz0K8hJgOJ1LB/ji4XWaaqVXDA5A0uCPsSRjFi5ljINkiySLP5O aYNeY5q4+BN24W5LK5UCaIxLx+dGedNwrAFTlIP14A== X-Google-Smtp-Source: ACHHUZ4/P0AFvJ7GR9ZcslfSm5QnkTPYJwrb9+Id3AaB1BrqbrITgvME3z/xb5GqyLldhpbAn2b3ZQ== X-Received: by 2002:a5d:6b86:0:b0:306:2fd1:a91f with SMTP id n6-20020a5d6b86000000b003062fd1a91fmr2458522wrx.61.1683357777330; Sat, 06 May 2023 00:22:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 27/30] tcg/ppc: Remove unused constraint J Date: Sat, 6 May 2023 08:22:32 +0100 Message-Id: <20230506072235.597467-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683358102175100001 Content-Type: text/plain; charset="utf-8" Never used since its introduction. Fixes: 3d582c6179c ("tcg-ppc64: Rearrange integer constant constraints") Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/ppc/tcg-target-con-str.h | 1 - tcg/ppc/tcg-target.c.inc | 3 --- 2 files changed, 4 deletions(-) diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h index 9dcbc3df50..094613cbcb 100644 --- a/tcg/ppc/tcg-target-con-str.h +++ b/tcg/ppc/tcg-target-con-str.h @@ -16,7 +16,6 @@ REGS('v', ALL_VECTOR_REGS) * CONST(letter, TCG_CT_CONST_* bit set) */ CONST('I', TCG_CT_CONST_S16) -CONST('J', TCG_CT_CONST_U16) CONST('M', TCG_CT_CONST_MONE) CONST('T', TCG_CT_CONST_S32) CONST('U', TCG_CT_CONST_U32) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 5a4ec0470a..0a14c3e997 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -83,7 +83,6 @@ #define SZR (TCG_TARGET_REG_BITS / 8) =20 #define TCG_CT_CONST_S16 0x100 -#define TCG_CT_CONST_U16 0x200 #define TCG_CT_CONST_S32 0x400 #define TCG_CT_CONST_U32 0x800 #define TCG_CT_CONST_ZERO 0x1000 @@ -270,8 +269,6 @@ static bool tcg_target_const_match(int64_t val, TCGType= type, int ct) =20 if ((ct & TCG_CT_CONST_S16) && val =3D=3D (int16_t)val) { return 1; - } else if ((ct & TCG_CT_CONST_U16) && val =3D=3D (uint16_t)val) { - return 1; } else if ((ct & TCG_CT_CONST_S32) && val =3D=3D (int32_t)val) { return 1; } else if ((ct & TCG_CT_CONST_U32) && val =3D=3D (uint32_t)val) { --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683358116; cv=none; d=zohomail.com; s=zohoarc; b=ZdlcZJ9WIa0H66VSiyFquGisVjJSEU84cXVinG3T7JFVAWQdVKHxPTxFIaUTWBrEa6Nz+HxMoef8L2SOryavOffmfcndmgJcSzxfDg5P/XevldVsCUtrHDBWB0OJdgPs71yEImg8fKbSsVmGHztcAzBsn2Jji8o3PzJOWXaMiQY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683358116; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4FwbXCfJhxIqyab8rUpzADm0cxrqrrSpiPKuK+rasgY=; b=dfcLokSX1ckp0/GRBT6l6rBeCQAkO6hwjr41j0Q8LdPqXje6nZ/itninESad9iNsj2FJFehTE3zGbLjKV/7mHOGZN7svCUYoLY4ZO0WxfWMM2eYH6OamNQxPDe8tWNj/++lQAK258WKebxlTaImRX4gxFhRKd/unEntcjNadNZI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683358116458222.58194370875867; Sat, 6 May 2023 00:28:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCGZ-0005sk-8k; Sat, 06 May 2023 03:23:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCGW-0005gO-8t for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:36 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFv-0004Xp-CV for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:36 -0400 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-3062c1e7df8so1731556f8f.1 for ; Sat, 06 May 2023 00:22:58 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357778; x=1685949778; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4FwbXCfJhxIqyab8rUpzADm0cxrqrrSpiPKuK+rasgY=; b=q4NPOj9/E+zXYe/Zd3aMwxW38WnbsUv/LrnxjyrUyqRetTj8CpVgMTLPp93IC2Jc0Z OKy2/Ct/HVz4Ci56jwggj0kV1ij0MuPSOqlRgTS2Yei0rtwINNDKxjn+D4YUx96jJUTC k7DYbjOvQfJHKng5G6jhsNshWFwIyaB0YokThGDvwSOozkkcG+N9sLguhbAY0qooRjYV +siGncxgkENvCkBcRRZjXkNuRW0NAeduVpVpVUwlCOTxzy4M92QqNjwU5cGdSFuMPWsd y/MiUJbc7s1jk7NZqWpuM2bLI3BNlegW6L5GtLje110xN65kK/cnbvnqZd1zNFbvy0L5 hsNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357778; x=1685949778; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4FwbXCfJhxIqyab8rUpzADm0cxrqrrSpiPKuK+rasgY=; b=SY08MnTUm7ABNHMp1Ad9JgUqYtxPE5Y4p6n0D9Q+h50lZCFZinqzhRqgsdxhPonHzk d7KcAKTEoOc/UwCS6tW70dRDMGbArkxvntLhn3af6nvQJhhNB1r6NXGFSqxV8KheFohF VtDKfjsgn6pwS9v/+GaF7BFF63k/lz0EA4JiIvCzO5JVBY5KXILyT9kH4wXsjkzhrRDv h8gSZVlD3760I67nDJbKoPMo4cuEg/JzcKXUqV8SfTIfXYC836jb47JunepdWdKqX8iW LP2e9OUS6iVIs9/vcQaep2kxo++LimiSLMQ/NxxoYz63ypLxQe97EaT1UQC3S0izm/G7 GWEw== X-Gm-Message-State: AC+VfDx54akLN92hBFqeVOTOhgISN2uToc3HvaoIS1iQDE+gAZl2N1hM KQm7BGVG7XPLJZYyKo7VFqt2GMOemskSH0Tzk1wS9A== X-Google-Smtp-Source: ACHHUZ4OXtX7ABpVOie++W8GF2F6Gp1/PJd1+WNRKcfP98KZSA6+0qKlpCMt0xL2P5gKYFnnKrhCTQ== X-Received: by 2002:a5d:6801:0:b0:306:2b64:fd1b with SMTP id w1-20020a5d6801000000b003062b64fd1bmr2828134wru.52.1683357778081; Sat, 06 May 2023 00:22:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Daniel Henrique Barboza Subject: [PATCH v5 28/30] tcg/riscv: Simplify constraints on qemu_ld/st Date: Sat, 6 May 2023 08:22:33 +0100 Message-Id: <20230506072235.597467-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683358117295100001 Content-Type: text/plain; charset="utf-8" The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/riscv/tcg-target-con-set.h | 2 -- tcg/riscv/tcg-target-con-str.h | 1 - tcg/riscv/tcg-target.c.inc | 16 +++------------- 3 files changed, 3 insertions(+), 16 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index d4cff673b0..d88888d3ac 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -10,10 +10,8 @@ * tcg-target-con-str.h; the constraint combination is inclusive or. */ C_O0_I1(r) -C_O0_I2(LZ, L) C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) -C_O1_I1(r, L) C_O1_I1(r, r) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h index 8d8afaee53..6f1cfb976c 100644 --- a/tcg/riscv/tcg-target-con-str.h +++ b/tcg/riscv/tcg-target-con-str.h @@ -9,7 +9,6 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) -REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index c22d1e35ac..d12b824d8c 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -125,17 +125,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKi= nd kind, int slot) #define TCG_CT_CONST_N12 0x400 #define TCG_CT_CONST_M12 0x800 =20 -#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) -/* - * For softmmu, we need to avoid conflicts with the first 5 - * argument registers to call the helper. Some of these are - * also used for the tlb lookup. - */ -#ifdef CONFIG_SOFTMMU -#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5) -#else -#define SOFTMMU_RESERVE_REGS 0 -#endif +#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) =20 #define sextreg sextract64 =20 @@ -1600,10 +1590,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return C_O1_I1(r, L); + return C_O1_I1(r, r); case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - return C_O0_I2(LZ, L); + return C_O0_I2(rZ, r); =20 default: g_assert_not_reached(); --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683358129; cv=none; d=zohomail.com; s=zohoarc; b=hcd3RV0TtIiytzQ3XLFHLNfso9bPVkzBViM4neebATGlLv5WvnOFllaq5BaAw3z+1Fu2m00V54/woWeUMoou0J9pMPb0awgEKq8kZXOuAxdppVIju10fAOztq2YyXoCjoCebaeAB+MDcCyjUC3S8yZDOfXoYuw7wRDNcNW89kD0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683358129; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WrmqAOuR2/yJANGPopXn5FwM+vXCIwdTliCaNgd+uz0=; b=Tc4aGVmbx/iY1+luR+HDiY5nLVRRcifD56DEvpF8oLZrdJN7ENBaDFYyolkwVMQPVOfoJSAzuzmMexVRYVBHYl2m3RIMA1lQBPRvsD+hdK3aQl3RAWoIhD/gDfKA1eZWyANY0n+9q5YNqp2SCR62+I2l61sRnr0aOeGs2Y5/E0k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683358129705773.2578928527898; Sat, 6 May 2023 00:28:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCGd-00063V-6F; Sat, 06 May 2023 03:23:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCGY-0005ny-9W for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:38 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCFv-0004Lx-Np for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:37 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-2f55ffdbaedso1705226f8f.2 for ; Sat, 06 May 2023 00:22:59 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357779; x=1685949779; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WrmqAOuR2/yJANGPopXn5FwM+vXCIwdTliCaNgd+uz0=; b=AlTo+1iIaFMaKTLUngVBwZ7LoNaDenv9K07t7v4Drur3M+qp3yNmfrrwBBARTUlOVG TP789aXPGsX1hnLD1vfJimaK76dMQS40aecOt7gjlhwq6gtVY4j2dYhSF9jhWx3+yZM3 sEHSmzKFPNvIIu3x0N/XkqqIeaA+W0d2ilsRAP8v6ljc8sJttI4rWg7hHxuNfzKHYA6z 0AmT1SEbQ/k9UEBBlloPGtxLlhNPM2PqeWykt0i4fvdSzQb26X6GFT/35nFqihBnHIz6 E0Y0N1SB65JbVUZQlRr/UmS1Rc7qU7UcFmCzd6v7E7vKlBRCbL3iTSZX2FNhqTi+yggA 08lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357779; x=1685949779; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WrmqAOuR2/yJANGPopXn5FwM+vXCIwdTliCaNgd+uz0=; b=Y4SSC4Tcngh1qESAafz96846LdKocTxCBkLjjWtDyGjsKyfAahYqR9orZHzoA1gwo6 Up8QFPZklzH3jWrzOKURyHCDO+zK0pfs/BiaTFdtX58xQJwf6TFuKzChDqayBF8Uz2MU bqVa332MQHLhwnU5uGbXHtfL3smrRpOvHTT3nadvWV2dVDHFnECliQJI5Ks6kPPTro7t pyi9uw1edWgOrOXl0u8OnzEKLV2dosi30IwXWEzc6xG2RNQfTn6Qjo34Lei0IZyNEdvJ nsyUc0NiVF9FstjCPuyi7BeOcTbdgM/G9ytWUVYVrFgjCX37OrmO6xzGgtoMJ/ujCZL7 +/Hg== X-Gm-Message-State: AC+VfDxT4z+oZCb6iuS778bqx5eFTUkGKAaq6ABPck2XtXEziy7Abq+n hCdAfGxDPQu3lS02uyEfiQOMxQT8lGT6U/MVPp3nFA== X-Google-Smtp-Source: ACHHUZ7z2OEu5BRFZ8ww5XEvNhuNoswH/Ro+/uVdF6mo3XMPvdJhPgoDuOGD50DG4V/OpbKFf0uhFg== X-Received: by 2002:adf:df0c:0:b0:307:5912:789 with SMTP id y12-20020adfdf0c000000b0030759120789mr2872297wrl.66.1683357778828; Sat, 06 May 2023 00:22:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 29/30] tcg/s390x: Use ALGFR in constructing softmmu host address Date: Sat, 6 May 2023 08:22:34 +0100 Message-Id: <20230506072235.597467-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683358131327100001 Content-Type: text/plain; charset="utf-8" Rather than zero-extend the guest address into a register, use an add instruction which zero-extends the second input. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/s390x/tcg-target.c.inc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index dfcf4d9e34..dd13326670 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -149,6 +149,7 @@ typedef enum S390Opcode { RRE_ALGR =3D 0xb90a, RRE_ALCR =3D 0xb998, RRE_ALCGR =3D 0xb988, + RRE_ALGFR =3D 0xb91a, RRE_CGR =3D 0xb920, RRE_CLGR =3D 0xb921, RRE_DLGR =3D 0xb987, @@ -1853,10 +1854,11 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, tcg_out_insn(s, RXY, LG, h->index, TCG_REG_R2, TCG_REG_NONE, offsetof(CPUTLBEntry, addend)); =20 - h->base =3D addr_reg; if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_R3, addr_reg); - h->base =3D TCG_REG_R3; + tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg); + h->base =3D TCG_REG_NONE; + } else { + h->base =3D addr_reg; } h->disp =3D 0; #else --=20 2.34.1 From nobody Fri May 17 11:05:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683358090; cv=none; d=zohomail.com; s=zohoarc; b=Xo7LKIFlGx1I+uFVUxvDekYLXlC7A2dr8b4n/tc80onGy+zk/pDNflSP3DOMGZXLpU4sww9JGl14fy2kAFhFz7MPNPny57rMhXSxBVS+RWfdsjJ9fGZktAPgJCuABgSepMe5msquw7qQm184hutxG7ChmrTe3n7Q3xJyZySzIO8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683358090; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=V0NN2hpnzMNaQXsS3LeulCiRo0il3NBwU75zZGVxlFw=; b=WUeyIBe69LCVL0RVkHOdBLSeq97DNJY+YfySy/TO+Uebcf26SouB7ayhaj4kyB7quF9Y/Uvq5G70K/OAPjy8GPbEEQ4ZdUIyrd31SjlMyliBwhCdDGISEAHDlyjoKaYoE0dpkqVWq2b8GjIy9MnxyHldAUQKSoAqhtcbUxcQ020= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683358090353126.50266695706819; Sat, 6 May 2023 00:28:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvCGf-000680-9b; Sat, 06 May 2023 03:23:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvCGa-0005wX-0O for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:40 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pvCG7-0004Yz-03 for qemu-devel@nongnu.org; Sat, 06 May 2023 03:23:39 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-30786c87cdaso419083f8f.2 for ; Sat, 06 May 2023 00:23:00 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id x9-20020adfec09000000b002faaa9a1721sm4481223wrn.58.2023.05.06.00.22.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 May 2023 00:22:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683357779; x=1685949779; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=V0NN2hpnzMNaQXsS3LeulCiRo0il3NBwU75zZGVxlFw=; b=Lzmq8af5w8UUTWeis3i2Xh1P48fJNle9jBlibB1cS64uxNlCTBq8oEgSM+L58DBeIH BlsUG4GbnlsAISXOjpM6eXxA/4uPqenfutf76/TE8Si1JgRdmLqgOpIlH/Y2yhU4UMHK axhulhnqHVu8bkDeFjol9hkiijs3yt8A6EnT/XXdLhYg9bzOsOoSVWVShXcEngv1bCwf qm5/lvK8mJiYiJ5t7aT4mxullYXq53OYPYNF8nl3Jl/Bg6BoeA2dBqEWeRVsrvHPEVoi PjQRtueWsxnX28R9HQ5q8YAZB0sNLj2SsSgn7ELAcffiwXHbLIINGVmgQB3OmMfq3NNT 0NBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683357779; x=1685949779; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V0NN2hpnzMNaQXsS3LeulCiRo0il3NBwU75zZGVxlFw=; b=LUXVRD+NEeodlECo2lTZK36XTqutbJ27FWVGMd2LTTbzO+xVG+GMAfhnUsMBkV9Cbe 1fDOMaoItLox9unUNV666bHctOrTtp2rBYpsns6ZSQzw1dKQSLM+/Ka3VEDEMa5ma1iS f1rdBceqQnFYrD+U5n1D3LDg/c5XngMcgggksc0i2Q4hgN4L73B+HjvpwfO9n9A+7nu4 l/rowQNRJrbZ1gXW2/8k0VvNN6ds49LKh3aNcfEvEhep63tYhMaevyZEeP3deFvR1AQ5 zT/TKDaRW4U5SiFplcYEOzs/pKJA15qcoLp7ABpEh4g0glDKBtG6l/p+yoGfzTLGY5f7 rksw== X-Gm-Message-State: AC+VfDyevqMvZCBt7qrQZyZ2n07F1AIa0ayfuutE+RAcJCrfjOyhy3jh NgY31zibLN0v6MtRNrCjNmvNB3864hphTMgQc4ghkA== X-Google-Smtp-Source: ACHHUZ4hueHLOHnT9EgUdcsgRKzIcN8zjbueEgoL7kohNJgjsGQrCDym/1EbPmKMOJ6islBM6Tx8vg== X-Received: by 2002:a5d:574e:0:b0:306:2cd4:b021 with SMTP id q14-20020a5d574e000000b003062cd4b021mr2939853wrw.13.1683357779649; Sat, 06 May 2023 00:22:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH v5 30/30] tcg/s390x: Simplify constraints on qemu_ld/st Date: Sat, 6 May 2023 08:22:35 +0100 Message-Id: <20230506072235.597467-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230506072235.597467-1-richard.henderson@linaro.org> References: <20230506072235.597467-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683358090827100001 Content-Type: text/plain; charset="utf-8" Adjust the softmmu tlb to use R0+R1, not any of the normally available registers. Since we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/s390x/tcg-target-con-set.h | 2 -- tcg/s390x/tcg-target-con-str.h | 1 - tcg/s390x/tcg-target.c.inc | 36 ++++++++++++---------------------- 3 files changed, 12 insertions(+), 27 deletions(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index 15f1c55103..ecc079bb6d 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -10,12 +10,10 @@ * tcg-target-con-str.h; the constraint combination is inclusive or. */ C_O0_I1(r) -C_O0_I2(L, L) C_O0_I2(r, r) C_O0_I2(r, ri) C_O0_I2(r, rA) C_O0_I2(v, r) -C_O1_I1(r, L) C_O1_I1(r, r) C_O1_I1(v, r) C_O1_I1(v, v) diff --git a/tcg/s390x/tcg-target-con-str.h b/tcg/s390x/tcg-target-con-str.h index 6fa64a1ed6..25675b449e 100644 --- a/tcg/s390x/tcg-target-con-str.h +++ b/tcg/s390x/tcg-target-con-str.h @@ -9,7 +9,6 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) -REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) REGS('v', ALL_VECTOR_REGS) REGS('o', 0xaaaa) /* odd numbered general regs */ =20 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index dd13326670..aacbaf21d5 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -44,18 +44,6 @@ #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16) #define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) =20 -/* - * For softmmu, we need to avoid conflicts with the first 3 - * argument registers to perform the tlb lookup, and to call - * the helper function. - */ -#ifdef CONFIG_SOFTMMU -#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_R2, 3) -#else -#define SOFTMMU_RESERVE_REGS 0 -#endif - - /* Several places within the instruction set 0 means "no register" rather than TCG_REG_R0. */ #define TCG_REG_NONE 0 @@ -1814,13 +1802,13 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, ldst->oi =3D oi; ldst->addrlo_reg =3D addr_reg; =20 - tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE, + tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); =20 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); - tcg_out_insn(s, RXY, NG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, mask_off= ); - tcg_out_insn(s, RXY, AG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, table_of= f); + tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_off); + tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_off); =20 /* * For aligned accesses, we check the first byte and include the align= ment @@ -1830,10 +1818,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, a_off =3D (a_bits >=3D s_bits ? 0 : s_mask - a_mask); tlb_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; if (a_off =3D=3D 0) { - tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask); + tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); } else { - tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off); - tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask); + tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off); + tgen_andi(s, TCG_TYPE_TL, TCG_REG_R0, tlb_mask); } =20 if (is_ld) { @@ -1842,16 +1830,16 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, ofs =3D offsetof(CPUTLBEntry, addr_write); } if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_insn(s, RX, C, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs); + tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); } else { - tcg_out_insn(s, RXY, CG, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs= ); + tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); } =20 tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); ldst->label_ptr[0] =3D s->code_ptr++; =20 - h->index =3D TCG_REG_R2; - tcg_out_insn(s, RXY, LG, h->index, TCG_REG_R2, TCG_REG_NONE, + h->index =3D TCG_TMP0; + tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE, offsetof(CPUTLBEntry, addend)); =20 if (TARGET_LONG_BITS =3D=3D 32) { @@ -3155,10 +3143,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return C_O1_I1(r, L); + return C_O1_I1(r, r); case INDEX_op_qemu_st_i64: case INDEX_op_qemu_st_i32: - return C_O0_I2(L, L); + return C_O0_I2(r, r); =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: --=20 2.34.1