From nobody Sat May 18 12:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322138; cv=none; d=zohomail.com; s=zohoarc; b=Xj/Gy1OMB31+ad360Y9x7a3+z+vXWbPiVlhECRDBaEQytXjZ9w47KA/0fQf8NCx2f0UN/M0whtPgA89mkH8XcULD10HGrO1dq3p6NqSuFvhrCWW1m8vIQR2uRt06naj0QQk019Su83wmBkLHTPZkRMkqDdc4qMh02rR2jFInB1w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683322138; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kq84wZCoWT9GZQmQJJ9plEHUAG17CGw73/IKgsrL81c=; b=BwCy2Y7f1TivzW0Zth/Q6L1S1sgG8iM47Eq94kMMtPYtJPGxBVFrFkVZ4cpgyW1BN7PhqLV+Vu+Wia06BLztmnZA/i95SK5p9MENN2KfPYzhRYUCbZx7fZvbAYqoYnSdibh++Vz323GXq27mBsBrCP6MNWc28MK1lLhWLD/W4cY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683322138236745.9188087317285; Fri, 5 May 2023 14:28:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vA-0000cT-Qh; Fri, 05 May 2023 17:24:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2v8-0000aU-FT for qemu-devel@nongnu.org; Fri, 05 May 2023 17:24:54 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2v6-0004Nd-24 for qemu-devel@nongnu.org; Fri, 05 May 2023 17:24:54 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-3063891d61aso2161440f8f.0 for ; Fri, 05 May 2023 14:24:50 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.24.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:24:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321889; x=1685913889; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kq84wZCoWT9GZQmQJJ9plEHUAG17CGw73/IKgsrL81c=; b=yqf5s2/5Ctg/k8vcsCVocDjvzCPevSPPITah508l8bZMA6Ypn4bqQrCMZMjgyntug6 NP7BbMELp7Toej3XNb4fhkv1drXpbD8dbMYcTa+9Clf8/RujNBcErG8fRmVf5zTkS49U qUN2jtJldgyb7/appwQ/DOBQvmjBbFRnu2Nl/UEBYv392+inBFvTWlAqpy/lYBmq80WM Er9nIMBpT1SCSbZMIFtLiczfvt8dR8bDPBykpTbRsmapeYOCcZflknBVgiJTeeHS9/KZ QGie9a+hGNSe09tx2VFYu8N35v4xfntiBLcopG7N5LdsZH9fNWAZINx/gODqla8KUSuI MunQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321889; x=1685913889; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kq84wZCoWT9GZQmQJJ9plEHUAG17CGw73/IKgsrL81c=; b=gfY/I7Jsyq5NEqLbNHlWOq+4arJakx8mhc8GI3uDykN1PLmsEFqIgML47k6P2p+8/S rZQXRPF6FMGat6WusfTSXpQXSLuFcZOXLqzDll587K8PNOfZLzbNiRDWtBQ65QIxiilM x1mKfj13ICdcXkJg8L+dotyG8YN9dyHnoN8tUc9Sr/fFDi0EiiMkR7UDbI344HC4RnKC g3iNZSprEFT0SX/O0Tn+3XjL+vrJSnKXmozlzE0svvSF2Knjd6mVgVxHIzOrHQZIMFIm 8CRddto0nhpwXUQKElKnYicTLEjxXeiifD2fxOsgWR4Xh+tdEWvCNxuOsqh21vn93LIF Gseg== X-Gm-Message-State: AC+VfDzHDfFQFy9IZspAchisDbOJpmPKIsHgy6o8y366jKl7ASfntvKX 6R2YxhfME1hiuV8ZS+HouQ8yhgSPHwBHh0TzCIvgow== X-Google-Smtp-Source: ACHHUZ4NLwbl6JXkbVK6XeFQxM+mv+TmnvsVR7eF2ieg1VmFfuALKxOMw+Hlk57f2B5TZzofQivcDw== X-Received: by 2002:a5d:67c7:0:b0:306:2fd3:2edb with SMTP id n7-20020a5d67c7000000b003062fd32edbmr2027178wrw.61.1683321889486; Fri, 05 May 2023 14:24:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Shivaprasad G Bhat , qemu-stable@nongnu.org, Vaibhav Jain Subject: [PULL 01/42] softfloat: Fix the incorrect computation in float32_exp2 Date: Fri, 5 May 2023 22:24:06 +0100 Message-Id: <20230505212447.374546-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322139964100003 Content-Type: text/plain; charset="utf-8" From: Shivaprasad G Bhat The float32_exp2 function is computing wrong exponent of 2. For example, with the following set of values {0.1, 2.0, 2.0, -1.0}, the expected output would be {1.071773, 4.000000, 4.000000, 0.500000}. Instead, the function is computing {1.119102, 3.382044, 3.382044, -0.191022} Looking at the code, the float32_exp2() attempts to do this 2 3 4 5 n x x x x x x x e =3D 1 + --- + --- + --- + --- + --- + ... + --- + ... 1! 2! 3! 4! 5! n! But because of the typo it ends up doing x x x x x x x e =3D 1 + --- + --- + --- + --- + --- + ... + --- + ... 1! 2! 3! 4! 5! n! This is because instead of the xnp which holds the numerator, parts_muladd is using the xp which is just 'x'. Commit '572c4d862ff2' refactored this function, and mistakenly used xp instead of xnp. Cc: qemu-stable@nongnu.org Fixes: 572c4d862ff2 "softfloat: Convert float32_exp2 to FloatParts" Partially-Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1623 Reported-By: Luca Barbato (https://gitlab.com/lu-zero) Signed-off-by: Shivaprasad G Bhat Signed-off-by: Vaibhav Jain Message-Id: <168304110865.537992.13059030916325018670.stgit@localhost.local= domain> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- fpu/softfloat.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index c7454c3eb1..108f9cb224 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -5135,7 +5135,7 @@ float32 float32_exp2(float32 a, float_status *status) float64_unpack_canonical(&rp, float64_one, status); for (i =3D 0 ; i < 15 ; i++) { float64_unpack_canonical(&tp, float32_exp2_coefficients[i], status= ); - rp =3D *parts_muladd(&tp, &xp, &rp, 0, status); + rp =3D *parts_muladd(&tp, &xnp, &rp, 0, status); xnp =3D *parts_mul(&xnp, &xp, status); } =20 --=20 2.34.1 From nobody Sat May 18 12:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322121; cv=none; d=zohomail.com; s=zohoarc; b=T6aiqKgfkFby0WIXsXy4Sy2Ne5hP1gAzV3O41GbBehC9xfE3ImKI8+rnXc1Hcj0FTnm48qz3t4gcrW83JZ1FIRXvZBnO9y/6oJSBsKHulVQCl/gsLaAsEWSlpWRmGe3v8Z/kpCFh/IpJF2nSL+XrQMhTEkVr2LUS7usl5MLUKcA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683322121; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jDjzkdTI/MWyIO68yFYfphv3aGgKEw/onagZANA7ylI=; b=cVd5pPCF45zVyvD55UcYp1WJSdeQXWsnOGP8ehWhqWPX3oySn6SN+FXAudwvBo8JO8kpmhtiGE14mSoTsJhmtBZZMIvQdNPABqTHxp/7LuE+cnCi8Xk5LdXMcvSxBQxkePefnTS2M+3ocfbnhTe+IFR7uohY+Ps1Ub7qun2uaxQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683322121083203.16051960739628; Fri, 5 May 2023 14:28:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vA-0000c5-7W; Fri, 05 May 2023 17:24:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2v8-0000aY-I2 for qemu-devel@nongnu.org; Fri, 05 May 2023 17:24:54 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2v6-0004Ni-Jx for qemu-devel@nongnu.org; Fri, 05 May 2023 17:24:54 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-30644c18072so1555776f8f.2 for ; Fri, 05 May 2023 14:24:52 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.24.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:24:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321890; x=1685913890; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jDjzkdTI/MWyIO68yFYfphv3aGgKEw/onagZANA7ylI=; b=Sy+JawUOvpXkrqtoQ/p1KsSZugG75Wg+XQ5C8aaIuR+FugQKWCzZhOCp30nypFp+D6 Dybg3e2ThFU8T7ijEkinmRXN5GZxhY5SEdXluvlCwFnyRXYEBrjM2lu5ZKBBjBgzjEqQ S+h14z+0ON9e5DM56aLlI4xBcCAosck+7SY/SErgdP22vmjMoteIMC9k7GLuDNm3UROj KtS3bQJZSADb3wV+0yAxqsCsLsa+jhiKle6uM+c0YUyVVUdQi0VxZ0CJ4vmQ6pkFRzje p14ztSyo68lle55BOuqhh6LZGDXSQ6hvPZx0bmTBtPa/NTn3HQ6WjgcZAHBnt1ZEbiKJ UQWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321890; x=1685913890; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jDjzkdTI/MWyIO68yFYfphv3aGgKEw/onagZANA7ylI=; b=dqmOdOMVyE/Ajk2nrjev+6ous0S+K7jSc7LGfhhBnw/rbNrHebhvSsyGKOLGvPDkHl x2jsI+G68sRldJIu/fYEELZIWgBUk+QLRucFOjoImewwtTPek+Cr3LTGFMh9pMTo7VHj qRGzP5DhZ+jYKUG1nmZb0XBQAnphuoiwKRj4qjlIIaNY3NNHq5rB/hmOZgLZUGzaVUXd KNz4Ta0wXY2c78va4HL1uObpuTHGfgH2mdR/TeybXpEGryDzZtrm5+kfCarN+2VvAvPE QMFeVistYS3Qi0CglwRGNhQjCqlzWlTIpbpMeaqUM1wCUcKjiGDt8bD56hekgCcwk7uf tnpg== X-Gm-Message-State: AC+VfDxOBPKmeK/V2cklGzIjaovGFl35aX0EAvnjUhaw31AKJJWBm1fi RGHpjIowmTvsCw8ecseFMb76IMsXzsJKIGwH4FCdWA== X-Google-Smtp-Source: ACHHUZ55kOmnQAj2yO3iEWXV1bXbw7tv7IsFPwH3vHbQozkqdrgv2NJhFGrN10q/A4tgx0Dh+SewDA== X-Received: by 2002:adf:f1d1:0:b0:306:30e2:c84c with SMTP id z17-20020adff1d1000000b0030630e2c84cmr2285242wro.49.1683321890086; Fri, 05 May 2023 14:24:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PULL 02/42] target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_* Date: Fri, 5 May 2023 22:24:07 +0100 Message-Id: <20230505212447.374546-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322123200100008 Content-Type: text/plain; charset="utf-8" Convert away from the old interface with the implicit MemOp argument. Signed-off-by: Richard Henderson Reviewed-by: Anton Johansson Message-Id: <20230502135741.1158035-2-richard.henderson@linaro.org> --- target/avr/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index a6aeae6dfa..cd82f5d591 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -1492,7 +1492,7 @@ static void gen_data_store(DisasContext *ctx, TCGv da= ta, TCGv addr) if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { gen_helper_fullwr(cpu_env, data, addr); } else { - tcg_gen_qemu_st8(data, addr, MMU_DATA_IDX); /* mem[addr] =3D data = */ + tcg_gen_qemu_st_tl(data, addr, MMU_DATA_IDX, MO_UB); } } =20 @@ -1501,7 +1501,7 @@ static void gen_data_load(DisasContext *ctx, TCGv dat= a, TCGv addr) if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { gen_helper_fullrd(data, cpu_env, addr); } else { - tcg_gen_qemu_ld8u(data, addr, MMU_DATA_IDX); /* data =3D mem[addr]= */ + tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB); } } =20 @@ -1979,7 +1979,7 @@ static bool trans_LPM1(DisasContext *ctx, arg_LPM1 *a) =20 tcg_gen_shli_tl(addr, H, 8); /* addr =3D H:L */ tcg_gen_or_tl(addr, addr, L); - tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd =3D mem[addr] */ + tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB); return true; } =20 @@ -1996,7 +1996,7 @@ static bool trans_LPM2(DisasContext *ctx, arg_LPM2 *a) =20 tcg_gen_shli_tl(addr, H, 8); /* addr =3D H:L */ tcg_gen_or_tl(addr, addr, L); - tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd =3D mem[addr] */ + tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB); return true; } =20 @@ -2013,7 +2013,7 @@ static bool trans_LPMX(DisasContext *ctx, arg_LPMX *a) =20 tcg_gen_shli_tl(addr, H, 8); /* addr =3D H:L */ tcg_gen_or_tl(addr, addr, L); - tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd =3D mem[addr] */ + tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB); tcg_gen_addi_tl(addr, addr, 1); /* addr =3D addr + 1 */ tcg_gen_andi_tl(L, addr, 0xff); tcg_gen_shri_tl(addr, addr, 8); @@ -2045,7 +2045,7 @@ static bool trans_ELPM1(DisasContext *ctx, arg_ELPM1 = *a) TCGv Rd =3D cpu_r[0]; TCGv addr =3D gen_get_zaddr(); =20 - tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd =3D mem[addr] */ + tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB); return true; } =20 @@ -2058,7 +2058,7 @@ static bool trans_ELPM2(DisasContext *ctx, arg_ELPM2 = *a) TCGv Rd =3D cpu_r[a->rd]; TCGv addr =3D gen_get_zaddr(); =20 - tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd =3D mem[addr] */ + tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB); return true; } =20 @@ -2071,7 +2071,7 @@ static bool trans_ELPMX(DisasContext *ctx, arg_ELPMX = *a) TCGv Rd =3D cpu_r[a->rd]; TCGv addr =3D gen_get_zaddr(); =20 - tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd =3D mem[addr] */ + tcg_gen_qemu_ld_tl(Rd, addr, MMU_CODE_IDX, MO_UB); tcg_gen_addi_tl(addr, addr, 1); /* addr =3D addr + 1 */ gen_set_zaddr(addr); return true; --=20 2.34.1 From nobody Sat May 18 12:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683322119719370.4095159146567; Fri, 5 May 2023 14:28:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vC-0000cw-5S; Fri, 05 May 2023 17:24:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2v8-0000aW-Hr for qemu-devel@nongnu.org; Fri, 05 May 2023 17:24:54 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2v6-0004Np-5m for qemu-devel@nongnu.org; Fri, 05 May 2023 17:24:54 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-30639daee76so1558176f8f.1 for ; Fri, 05 May 2023 14:24:51 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.24.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:24:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321890; x=1685913890; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JRV8Cx+YlPo92Hwls/dIiJIZvxAoW7WnNpj6EC6C0nA=; b=nMEdyNZr8J2zalF2AC/biAderraInxqmsecXzXHMJXTPfrPDbtCjjGQhH83Jz21C0R En6JOfS8FUd25DaYya3LABgLmDdtqjYDcyHyr8bIvr2oHi/ZKKeboUWWJSAMewWQT/er qfsPTDEDcF9P0H3HNcAfg2J10boaa4Rs95cJMjoJH0ak7NUw4H8UX4zLuR8DirM6/zPo aZQ8UY75B3xTmRlZSa6YIbF1TH2vHrymBAQk+EZA7asWgXwiQXF5/eYXN5l5/roxgb01 3tLIio687XNddyC8yFQeeOF/7NpNHwockAOVEtMgSGmwxrpGzSQzoVtgNAYs7thmbXKd EhBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321890; x=1685913890; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JRV8Cx+YlPo92Hwls/dIiJIZvxAoW7WnNpj6EC6C0nA=; b=lfD8diWwaT0bapbHQrEakxEHkbgJeU+vRinZna7I66yQ3wh8T8KlGKp8uRxADehdAv yGp9laYN7KbMSDc+BMNVKMiyVBxckoBYHOJrkv9RQxfXiZOyLxSX7Xjp10aMK2jNjLqV QwHVy6rSCRRVTbPXPlQlwiPJJs8yiM67ZYvl3KBqWuSK6Se+1ZbQ8warcxS67j3abdRc OLWg+gg/LtcbNS97XVrwk7V5l9W32mSZrh2FwRPVVo/iF2xCpshPr9ehOnd3I60TfhIj PJwmZaZmZlLNp35pFo6B4ZYJKRtUGZdz6IiHKQhlpMpomtHFI+sTNMHdb3ZzZQpmzr88 /HOw== X-Gm-Message-State: AC+VfDxlWHfVXNbeVu1dceDW4GJ2YqrJN7rLaoj0gMaSmnxrSxBJCE9e VCu5aNa9doMpidIE7yDN2lKro6J8eI2zb28zEKGxng== X-Google-Smtp-Source: ACHHUZ6SgWfnKHF3tEdO8zqmSprvFOGvpPywvooQcwK2zyV0RQ1X/yhQ01k09kcRQr5yTHSEV8m7Cw== X-Received: by 2002:a5d:6803:0:b0:306:4586:28c7 with SMTP id w3-20020a5d6803000000b00306458628c7mr2003654wru.39.1683321890581; Fri, 05 May 2023 14:24:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PULL 03/42] target/cris: Finish conversion to tcg_gen_qemu_{ld, st}_* Date: Fri, 5 May 2023 22:24:08 +0100 Message-Id: <20230505212447.374546-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683322121497100004 Content-Type: text/plain; charset="utf-8" Convert away from the old interface with the implicit MemOp argument. In this case we can fold the calls using the size bits of MemOp. Signed-off-by: Richard Henderson Reviewed-by: Anton Johansson Message-Id: <20230502135741.1158035-3-richard.henderson@linaro.org> --- target/cris/translate_v10.c.inc | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/target/cris/translate_v10.c.inc b/target/cris/translate_v10.c.= inc index 32338bb69b..b7b0517982 100644 --- a/target/cris/translate_v10.c.inc +++ b/target/cris/translate_v10.c.inc @@ -80,13 +80,9 @@ static void gen_store_v10_conditional(DisasContext *dc, = TCGv addr, TCGv val, /* Store only if F flag isn't set */ tcg_gen_andi_tl(t1, cpu_PR[PR_CCS], F_FLAG_V10); tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); - if (size =3D=3D 1) { - tcg_gen_qemu_st8(tval, taddr, mem_index); - } else if (size =3D=3D 2) { - tcg_gen_qemu_st16(tval, taddr, mem_index); - } else { - tcg_gen_qemu_st32(tval, taddr, mem_index); - } + + tcg_gen_qemu_st_tl(tval, taddr, mem_index, ctz32(size) | MO_TE); + gen_set_label(l1); tcg_gen_shri_tl(t1, t1, 1); /* shift F to P position */ tcg_gen_or_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], t1); /*P=3DF*/ @@ -109,13 +105,7 @@ static void gen_store_v10(DisasContext *dc, TCGv addr,= TCGv val, return; } =20 - if (size =3D=3D 1) { - tcg_gen_qemu_st8(val, addr, mem_index); - } else if (size =3D=3D 2) { - tcg_gen_qemu_st16(val, addr, mem_index); - } else { - tcg_gen_qemu_st32(val, addr, mem_index); - } + tcg_gen_qemu_st_tl(val, addr, mem_index, ctz32(size) | MO_TE); } =20 =20 --=20 2.34.1 From nobody Sat May 18 12:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683321999; cv=none; d=zohomail.com; s=zohoarc; b=SjC2eWwFxqUjkOtp34gTvn7sAZiOX+LQN6bHHebRs67DIB326cIh7eyXKYLXOpSO4VUZKa87GJ0d20X0vtWce8BcVv4pW0RUExOzot9/Sdl7wo2UBf8CelQEMuaG3j2iueekDQDyuBWPArBDne5EsJeGE97fWlkPBYwwCphF0JA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683321999; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5Po/b9RUKIX4ZcUJrZzR6FduMnLEh3zUsfIIwnwg6Cs=; b=m/70CKIZV4ZTi7y6RKTKgCec/JsqWos5NutH3BEnVl3gV+SeipAcmRC5cfDtnra1nHMSdUT2qsZADw1E15g3fXbh+4Ie8n0UeBE+DzFzfcSr6EmcOo7Y9TYAWem2+8LOuzexzQobvZpy4Xp+B9PfYhX1dgqAtOhvBjBHmVobK7c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683321999213495.42620748959496; Fri, 5 May 2023 14:26:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vD-0000e3-GA; Fri, 05 May 2023 17:24:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2v8-0000bF-Uo for qemu-devel@nongnu.org; Fri, 05 May 2023 17:24:54 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2v6-0004Ns-PU for qemu-devel@nongnu.org; Fri, 05 May 2023 17:24:54 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-3f19b9d5358so22933275e9.1 for ; Fri, 05 May 2023 14:24:52 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.24.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:24:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321891; x=1685913891; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5Po/b9RUKIX4ZcUJrZzR6FduMnLEh3zUsfIIwnwg6Cs=; b=utZjXax9avcX2/Vs6st0pQ+fC/SkbPe6XhwixmGvXIwesYEJikjsc62DsAiRQPxBcU bKvlxX7hWWK6cmabIJqcdZ6WN25yNsmSwhYvw/4sIsezAc9h4WPvxxrh8g7axnsYItzu UIlHqU/O/DiTyJr72NOpddxSDrFqjJOHdp9L6SPpHpcQ6h2a4axP3lEccllsBEdbghmb UyPG+ap9VEU+IPR1bVeu/HFqNmkMy/G5qmwqNktbPCVBSCmty/rglMstwb5ydMzN0K3u lT1iLQPWrWxUmA+ESjxdGNJDzszizl3/g9I3fRcL1HSiVhKOTEA9m5M/8Q18KPJve6Co ccRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321891; x=1685913891; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5Po/b9RUKIX4ZcUJrZzR6FduMnLEh3zUsfIIwnwg6Cs=; b=KTvS8E2ZWGw1FNW8LV9SOISz/JCNUfAyiZJ6Req6Z4CcIg0dlFYnCS8cngh2cwi4EG 4jjHXx651wvPTnxhb2X7Q71UPHDabj+JOMAwOybXscgVszffXVW0NMj4Tcu3KJhle6Al d0Z12nN1KFhL04/eba/WEKMhdWiqShPkpJ5b0JpNntQb0F5dICQ280N23XKu6erynQQN vIMTti3Ks6G6g0JI6kcTQwMVBANF3xRHbdaxCRJkdEs5VwJWMx7XwXkzwxUm1DPS+5Cy r2DD0p6p+13WGiizg33DgboZ4+ElZlh4WOu8H07UNT/CYDvl/PBjQjYakAmymditahZx yZ3A== X-Gm-Message-State: AC+VfDxjc6rH87fK1IiXsWrJzoiKIg84W4kYG+lf13OCyofdByJdG+Gm Wj+/1kIh1adCDvhBNZiUJLfoParr/hynQ7GCxMQoTg== X-Google-Smtp-Source: ACHHUZ7iyeaL9rrGzOHh0zQehlfiqQv2nrGT4jFJs/MV0/1MDJ8QhAACWeLvcEIaw9KkID3cIAHgFA== X-Received: by 2002:a5d:5003:0:b0:306:3408:f9a8 with SMTP id e3-20020a5d5003000000b003063408f9a8mr2261993wrt.11.1683321891121; Fri, 05 May 2023 14:24:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Taylor Simpson , Anton Johansson Subject: [PULL 04/42] target/Hexagon: Finish conversion to tcg_gen_qemu_{ld, st}_* Date: Fri, 5 May 2023 22:24:09 +0100 Message-Id: <20230505212447.374546-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683321999725100001 Content-Type: text/plain; charset="utf-8" Convert away from the old interface with the implicit MemOp argument. Importantly, this removes some incorrect casts generated by idef-parser's gen_load(). Signed-off-by: Richard Henderson Tested-by: Taylor Simpson Reviewed-by: Taylor Simpson Reviewed-by: Anton Johansson Message-Id: <20230502135741.1158035-4-richard.henderson@linaro.org> --- target/hexagon/macros.h | 14 ++++----- target/hexagon/genptr.c | 8 +++--- target/hexagon/idef-parser/parser-helpers.c | 28 +++++++++--------- target/hexagon/translate.c | 32 ++++++++++----------- 4 files changed, 40 insertions(+), 42 deletions(-) diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 3e162de3a7..760630de8f 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -99,37 +99,37 @@ #define MEM_LOAD1s(DST, VA) \ do { \ CHECK_NOSHUF(VA, 1); \ - tcg_gen_qemu_ld8s(DST, VA, ctx->mem_idx); \ + tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_SB); \ } while (0) #define MEM_LOAD1u(DST, VA) \ do { \ CHECK_NOSHUF(VA, 1); \ - tcg_gen_qemu_ld8u(DST, VA, ctx->mem_idx); \ + tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_UB); \ } while (0) #define MEM_LOAD2s(DST, VA) \ do { \ CHECK_NOSHUF(VA, 2); \ - tcg_gen_qemu_ld16s(DST, VA, ctx->mem_idx); \ + tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESW); \ } while (0) #define MEM_LOAD2u(DST, VA) \ do { \ CHECK_NOSHUF(VA, 2); \ - tcg_gen_qemu_ld16u(DST, VA, ctx->mem_idx); \ + tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUW); \ } while (0) #define MEM_LOAD4s(DST, VA) \ do { \ CHECK_NOSHUF(VA, 4); \ - tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \ + tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESL); \ } while (0) #define MEM_LOAD4u(DST, VA) \ do { \ CHECK_NOSHUF(VA, 4); \ - tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \ + tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUL); \ } while (0) #define MEM_LOAD8u(DST, VA) \ do { \ CHECK_NOSHUF(VA, 8); \ - tcg_gen_qemu_ld64(DST, VA, ctx->mem_idx); \ + tcg_gen_qemu_ld_i64(DST, VA, ctx->mem_idx, MO_TEUQ); \ } while (0) =20 #define MEM_STORE1_FUNC(X) \ diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 502c85ae35..244063b1d2 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -320,14 +320,14 @@ void gen_set_byte_i64(int N, TCGv_i64 result, TCGv sr= c) =20 static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index) { - tcg_gen_qemu_ld32u(dest, vaddr, mem_index); + tcg_gen_qemu_ld_tl(dest, vaddr, mem_index, MO_TEUL); tcg_gen_mov_tl(hex_llsc_addr, vaddr); tcg_gen_mov_tl(hex_llsc_val, dest); } =20 static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_in= dex) { - tcg_gen_qemu_ld64(dest, vaddr, mem_index); + tcg_gen_qemu_ld_i64(dest, vaddr, mem_index, MO_TEUQ); tcg_gen_mov_tl(hex_llsc_addr, vaddr); tcg_gen_mov_i64(hex_llsc_val_i64, dest); } @@ -678,7 +678,7 @@ static void gen_load_frame(DisasContext *ctx, TCGv_i64 = frame, TCGv EA) { Insn *insn =3D ctx->insn; /* Needed for CHECK_NOSHUF */ CHECK_NOSHUF(EA, 8); - tcg_gen_qemu_ld64(frame, EA, ctx->mem_idx); + tcg_gen_qemu_ld_i64(frame, EA, ctx->mem_idx, MO_TEUQ); } =20 static void gen_return(DisasContext *ctx, TCGv_i64 dst, TCGv src) @@ -1019,7 +1019,7 @@ static void gen_vreg_load(DisasContext *ctx, intptr_t= dstoff, TCGv src, tcg_gen_andi_tl(src, src, ~((int32_t)sizeof(MMVector) - 1)); } for (int i =3D 0; i < sizeof(MMVector) / 8; i++) { - tcg_gen_qemu_ld64(tmp, src, ctx->mem_idx); + tcg_gen_qemu_ld_i64(tmp, src, ctx->mem_idx, MO_TEUQ); tcg_gen_addi_tl(src, src, 8); tcg_gen_st_i64(tmp, cpu_env, dstoff + i * 8); } diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/i= def-parser/parser-helpers.c index 86511efb62..8734218e51 100644 --- a/target/hexagon/idef-parser/parser-helpers.c +++ b/target/hexagon/idef-parser/parser-helpers.c @@ -1737,36 +1737,34 @@ void gen_load_cancel(Context *c, YYLTYPE *locp) void gen_load(Context *c, YYLTYPE *locp, HexValue *width, HexSignedness signedness, HexValue *ea, HexValue *dst) { - char size_suffix[4] =3D {0}; - const char *sign_suffix; + unsigned dst_bit_width; + unsigned src_bit_width; + /* Memop width is specified in the load macro */ assert_signedness(c, locp, signedness); - sign_suffix =3D (width->imm.value > 4) - ? "" - : ((signedness =3D=3D UNSIGNED) ? "u" : "s"); + /* If dst is a variable, assert that is declared and load the type inf= o */ if (dst->type =3D=3D VARID) { find_variable(c, locp, dst, dst); } =20 - snprintf(size_suffix, 4, "%" PRIu64, width->imm.value * 8); + src_bit_width =3D width->imm.value * 8; + dst_bit_width =3D MAX(dst->bit_width, 32); + /* Lookup the effective address EA */ find_variable(c, locp, ea, ea); OUT(c, locp, "if (insn->slot =3D=3D 0 && pkt->pkt_has_store_s1) {\n"); OUT(c, locp, "probe_noshuf_load(", ea, ", ", width, ", ctx->mem_idx);\= n"); OUT(c, locp, "process_store(ctx, 1);\n"); OUT(c, locp, "}\n"); - OUT(c, locp, "tcg_gen_qemu_ld", size_suffix, sign_suffix); + + OUT(c, locp, "tcg_gen_qemu_ld_i", &dst_bit_width); OUT(c, locp, "("); - if (dst->bit_width > width->imm.value * 8) { - /* - * Cast to the correct TCG type if necessary, to avoid implict cast - * warnings. This is needed when the width of the destination var = is - * larger than the size of the requested load. - */ - OUT(c, locp, "(TCGv) "); + OUT(c, locp, dst, ", ", ea, ", ctx->mem_idx, MO_", &src_bit_width); + if (signedness =3D=3D SIGNED) { + OUT(c, locp, " | MO_SIGN"); } - OUT(c, locp, dst, ", ", ea, ", ctx->mem_idx);\n"); + OUT(c, locp, " | MO_TE);\n"); } =20 void gen_store(Context *c, YYLTYPE *locp, HexValue *width, HexValue *ea, diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index c087f183d0..cddd7c5db4 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -627,27 +627,27 @@ void process_store(DisasContext *ctx, int slot_num) switch (ctx->store_width[slot_num]) { case 1: gen_check_store_width(ctx, slot_num); - tcg_gen_qemu_st8(hex_store_val32[slot_num], - hex_store_addr[slot_num], - ctx->mem_idx); + tcg_gen_qemu_st_tl(hex_store_val32[slot_num], + hex_store_addr[slot_num], + ctx->mem_idx, MO_UB); break; case 2: gen_check_store_width(ctx, slot_num); - tcg_gen_qemu_st16(hex_store_val32[slot_num], - hex_store_addr[slot_num], - ctx->mem_idx); + tcg_gen_qemu_st_tl(hex_store_val32[slot_num], + hex_store_addr[slot_num], + ctx->mem_idx, MO_TEUW); break; case 4: gen_check_store_width(ctx, slot_num); - tcg_gen_qemu_st32(hex_store_val32[slot_num], - hex_store_addr[slot_num], - ctx->mem_idx); + tcg_gen_qemu_st_tl(hex_store_val32[slot_num], + hex_store_addr[slot_num], + ctx->mem_idx, MO_TEUL); break; case 8: gen_check_store_width(ctx, slot_num); - tcg_gen_qemu_st64(hex_store_val64[slot_num], - hex_store_addr[slot_num], - ctx->mem_idx); + tcg_gen_qemu_st_i64(hex_store_val64[slot_num], + hex_store_addr[slot_num], + ctx->mem_idx, MO_TEUQ); break; default: { @@ -693,13 +693,13 @@ static void process_dczeroa(DisasContext *ctx) TCGv_i64 zero =3D tcg_constant_i64(0); =20 tcg_gen_andi_tl(addr, hex_dczero_addr, ~0x1f); - tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); + tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); + tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); + tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); + tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ); } } =20 --=20 2.34.1 From nobody Sat May 18 12:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683321973543406.4018157674933; Fri, 5 May 2023 14:26:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vB-0000cX-DO; Fri, 05 May 2023 17:24:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2v9-0000bV-4I for qemu-devel@nongnu.org; Fri, 05 May 2023 17:24:55 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2v7-0004Nx-AB for qemu-devel@nongnu.org; Fri, 05 May 2023 17:24:54 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-3f315712406so113476895e9.0 for ; Fri, 05 May 2023 14:24:52 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.24.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:24:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321892; x=1685913892; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QbWtBg5qzToLARYA6QIUcOajHeUi5qAypv5e+z+/edQ=; b=Iy5LVwcklcSsIuu1Cf+FVeUtx+/3bbpCVZuygLWWcD52ykgL34sfhakiOPsrKpcjmh Ji1v9JSvXvlo9UwHDxSz6jf6mNzjqnn6dBH+CqXZaxW11tlXmBm0ghjfdlDlsChJflTF vAEwtkyeG93/jKq6NqVddLXWSgoe1Cq8gSwW2IMcxJEOiAmsi/HQo+NLAEuFmncVZvkH dbSOjzl9S7Zew6+5Dj9E1X+efZO+RyY3xstjJnetkwY7qmlk3g/MMvnSiSB1XSHf5ebj 2xd/uz3YZ/v90RQ1O9sGbzbz3doZ60gRCyAWAbnEY4H55V2cCs8xG/i9bbqFNw192Yrm QSJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321892; x=1685913892; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QbWtBg5qzToLARYA6QIUcOajHeUi5qAypv5e+z+/edQ=; b=Gc/8MxL/8YJ++X40qOYcyiZjfaUNuDY/llHYwvZ+mBfRX+PGPWu333MOeRJO85jhq9 y3OBDtYp1t0tG03xEmi9LRYW4TsBPd6D9UX3cyk3J54ph9EWxplzULLBd5Fal+tEAtO2 WqzoholEQcyilkXpWmU7xzjYg3kiM7jcCPVtoSROv1BfVEyK+Qal9pudxRVIFuGbs6TR E0jmAO+HeQN08tFfDxv+mS5282xC3QZF46EAbJttHb/MCRyee/0fAWTian1+vJcdwczG 6TxFPm/XQYYnLJ91Lg3SB/5XVb/+Iw9TZqzCNOPaji/N5Ww4fuo93LyiuEC0orJvpRDO DGag== X-Gm-Message-State: AC+VfDzbAamnlV90aWlBcuVZOQsLt5iMKijg2tSz6BB56qTUQjVby5ie HA8cGZps8SW+VqQLZDoeIfhv/imLZm435wk1d+7kRw== X-Google-Smtp-Source: ACHHUZ6Jqjdck3QZLNl6ckB6X2H5q17c4Waw2hP0KC3qncAiOyamPE6/b38AI0GZrDrSQ0Ck5z3Lwg== X-Received: by 2002:a05:600c:b41:b0:3f1:94e2:e5bc with SMTP id k1-20020a05600c0b4100b003f194e2e5bcmr2038017wmr.11.1683321891705; Fri, 05 May 2023 14:24:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PULL 05/42] target/m68k: Finish conversion to tcg_gen_qemu_{ld, st}_* Date: Fri, 5 May 2023 22:24:10 +0100 Message-Id: <20230505212447.374546-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683321975549100011 Content-Type: text/plain; charset="utf-8" Convert away from the old interface with the implicit MemOp argument. Signed-off-by: Richard Henderson Reviewed-by: Anton Johansson Message-Id: <20230502135741.1158035-5-richard.henderson@linaro.org> --- target/m68k/translate.c | 76 ++++++++++++++--------------------------- 1 file changed, 25 insertions(+), 51 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 422f4652f1..744eb3748b 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -304,23 +304,14 @@ static inline void gen_addr_fault(DisasContext *s) static inline TCGv gen_load(DisasContext *s, int opsize, TCGv addr, int sign, int index) { - TCGv tmp; - tmp =3D tcg_temp_new_i32(); - switch(opsize) { + TCGv tmp =3D tcg_temp_new_i32(); + + switch (opsize) { case OS_BYTE: - if (sign) - tcg_gen_qemu_ld8s(tmp, addr, index); - else - tcg_gen_qemu_ld8u(tmp, addr, index); - break; case OS_WORD: - if (sign) - tcg_gen_qemu_ld16s(tmp, addr, index); - else - tcg_gen_qemu_ld16u(tmp, addr, index); - break; case OS_LONG: - tcg_gen_qemu_ld32u(tmp, addr, index); + tcg_gen_qemu_ld_tl(tmp, addr, index, + opsize | (sign ? MO_SIGN : 0) | MO_TE); break; default: g_assert_not_reached(); @@ -332,15 +323,11 @@ static inline TCGv gen_load(DisasContext *s, int opsi= ze, TCGv addr, static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv = val, int index) { - switch(opsize) { + switch (opsize) { case OS_BYTE: - tcg_gen_qemu_st8(val, addr, index); - break; case OS_WORD: - tcg_gen_qemu_st16(val, addr, index); - break; case OS_LONG: - tcg_gen_qemu_st32(val, addr, index); + tcg_gen_qemu_st_tl(val, addr, index, opsize | MO_TE); break; default: g_assert_not_reached(); @@ -971,23 +958,16 @@ static void gen_load_fp(DisasContext *s, int opsize, = TCGv addr, TCGv_ptr fp, tmp =3D tcg_temp_new(); switch (opsize) { case OS_BYTE: - tcg_gen_qemu_ld8s(tmp, addr, index); - gen_helper_exts32(cpu_env, fp, tmp); - break; case OS_WORD: - tcg_gen_qemu_ld16s(tmp, addr, index); - gen_helper_exts32(cpu_env, fp, tmp); - break; - case OS_LONG: - tcg_gen_qemu_ld32u(tmp, addr, index); + tcg_gen_qemu_ld_tl(tmp, addr, index, opsize | MO_SIGN | MO_TE); gen_helper_exts32(cpu_env, fp, tmp); break; case OS_SINGLE: - tcg_gen_qemu_ld32u(tmp, addr, index); + tcg_gen_qemu_ld_tl(tmp, addr, index, MO_TEUL); gen_helper_extf32(cpu_env, fp, tmp); break; case OS_DOUBLE: - tcg_gen_qemu_ld64(t64, addr, index); + tcg_gen_qemu_ld_i64(t64, addr, index, MO_TEUQ); gen_helper_extf64(cpu_env, fp, t64); break; case OS_EXTENDED: @@ -995,11 +975,11 @@ static void gen_load_fp(DisasContext *s, int opsize, = TCGv addr, TCGv_ptr fp, gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP); break; } - tcg_gen_qemu_ld32u(tmp, addr, index); + tcg_gen_qemu_ld_i32(tmp, addr, index, MO_TEUL); tcg_gen_shri_i32(tmp, tmp, 16); tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper)); tcg_gen_addi_i32(tmp, addr, 4); - tcg_gen_qemu_ld64(t64, tmp, index); + tcg_gen_qemu_ld_i64(t64, tmp, index, MO_TEUQ); tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower)); break; case OS_PACKED: @@ -1024,24 +1004,18 @@ static void gen_store_fp(DisasContext *s, int opsiz= e, TCGv addr, TCGv_ptr fp, tmp =3D tcg_temp_new(); switch (opsize) { case OS_BYTE: - gen_helper_reds32(tmp, cpu_env, fp); - tcg_gen_qemu_st8(tmp, addr, index); - break; case OS_WORD: - gen_helper_reds32(tmp, cpu_env, fp); - tcg_gen_qemu_st16(tmp, addr, index); - break; case OS_LONG: gen_helper_reds32(tmp, cpu_env, fp); - tcg_gen_qemu_st32(tmp, addr, index); + tcg_gen_qemu_st_tl(tmp, addr, index, opsize | MO_TE); break; case OS_SINGLE: gen_helper_redf32(tmp, cpu_env, fp); - tcg_gen_qemu_st32(tmp, addr, index); + tcg_gen_qemu_st_tl(tmp, addr, index, MO_TEUL); break; case OS_DOUBLE: gen_helper_redf64(t64, cpu_env, fp); - tcg_gen_qemu_st64(t64, addr, index); + tcg_gen_qemu_st_i64(t64, addr, index, MO_TEUQ); break; case OS_EXTENDED: if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) { @@ -1050,10 +1024,10 @@ static void gen_store_fp(DisasContext *s, int opsiz= e, TCGv addr, TCGv_ptr fp, } tcg_gen_ld16u_i32(tmp, fp, offsetof(FPReg, l.upper)); tcg_gen_shli_i32(tmp, tmp, 16); - tcg_gen_qemu_st32(tmp, addr, index); + tcg_gen_qemu_st_i32(tmp, addr, index, MO_TEUL); tcg_gen_addi_i32(tmp, addr, 4); tcg_gen_ld_i64(t64, fp, offsetof(FPReg, l.lower)); - tcg_gen_qemu_st64(t64, tmp, index); + tcg_gen_qemu_st_i64(t64, tmp, index, MO_TEUQ); break; case OS_PACKED: /* @@ -2079,14 +2053,14 @@ DISAS_INSN(movep) if (insn & 0x80) { for ( ; i > 0 ; i--) { tcg_gen_shri_i32(dbuf, reg, (i - 1) * 8); - tcg_gen_qemu_st8(dbuf, abuf, IS_USER(s)); + tcg_gen_qemu_st_i32(dbuf, abuf, IS_USER(s), MO_UB); if (i > 1) { tcg_gen_addi_i32(abuf, abuf, 2); } } } else { for ( ; i > 0 ; i--) { - tcg_gen_qemu_ld8u(dbuf, abuf, IS_USER(s)); + tcg_gen_qemu_ld_tl(dbuf, abuf, IS_USER(s), MO_UB); tcg_gen_deposit_i32(reg, reg, dbuf, (i - 1) * 8, 8); if (i > 1) { tcg_gen_addi_i32(abuf, abuf, 2); @@ -4337,14 +4311,14 @@ static void m68k_copy_line(TCGv dst, TCGv src, int = index) t1 =3D tcg_temp_new_i64(); =20 tcg_gen_andi_i32(addr, src, ~15); - tcg_gen_qemu_ld64(t0, addr, index); + tcg_gen_qemu_ld_i64(t0, addr, index, MO_TEUQ); tcg_gen_addi_i32(addr, addr, 8); - tcg_gen_qemu_ld64(t1, addr, index); + tcg_gen_qemu_ld_i64(t1, addr, index, MO_TEUQ); =20 tcg_gen_andi_i32(addr, dst, ~15); - tcg_gen_qemu_st64(t0, addr, index); + tcg_gen_qemu_st_i64(t0, addr, index, MO_TEUQ); tcg_gen_addi_i32(addr, addr, 8); - tcg_gen_qemu_st64(t1, addr, index); + tcg_gen_qemu_st_i64(t1, addr, index, MO_TEUQ); } =20 DISAS_INSN(move16_reg) @@ -4767,7 +4741,7 @@ static void gen_qemu_store_fcr(DisasContext *s, TCGv = addr, int reg) =20 tmp =3D tcg_temp_new(); gen_load_fcr(s, tmp, reg); - tcg_gen_qemu_st32(tmp, addr, index); + tcg_gen_qemu_st_tl(tmp, addr, index, MO_TEUL); } =20 static void gen_qemu_load_fcr(DisasContext *s, TCGv addr, int reg) @@ -4776,7 +4750,7 @@ static void gen_qemu_load_fcr(DisasContext *s, TCGv a= ddr, int reg) TCGv tmp; =20 tmp =3D tcg_temp_new(); - tcg_gen_qemu_ld32u(tmp, addr, index); + tcg_gen_qemu_ld_tl(tmp, addr, index, MO_TEUL); gen_store_fcr(s, tmp, reg); } =20 --=20 2.34.1 From nobody Sat May 18 12:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.24.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:24:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321892; x=1685913892; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7k6JbT1Cu9D6+D63VgpuW6vTvCzozecySlTlgzNc9d0=; b=mejBC6cATgoFyX/YdI5ycgQU2F3VEGtewOzIJDkBztdRKENNL0ZItMTOpQDexpR6SW vr9ZKY7LG3X9oQ5Chkejy6Dyh1AguMLV/KcX43NweAuECsemdyy5ZNjOxvkNBki+Gf1U WRkZPOPhGmLiAkDYXQcxOr9fVCk3iDMB/N9g/OoJVyVrPWGgnNWM2GLpcMST2QABKO03 J4hLyxNyFNUU3B5N7n8SXjXthk9NZ65CpvhcrJORzjz8CtOyX17gZGwX4fDPPzeHstmm F5PN5bZ1O7wmSX39VhoiuaBvWEqsHdgvSE9yYFsj1MqD3/UIexK3dUmnbq0gwSFHaUNP bXxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321892; x=1685913892; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7k6JbT1Cu9D6+D63VgpuW6vTvCzozecySlTlgzNc9d0=; b=N3/DKlrPgRq5PJs/B8w3RIc9dDax1g2jn5pvZds3B5NXFgLrLUQB2uYuIFLVcSs3P+ Mqdu2C94dACL/kJlPlesyPR8sN8ZgKO+Y3XFHwA4z78qBk07eZqO19snFNBqj0uImSnD GMVQK/eUsp+mmw4Gqw1sHgJMHonCgefUe8wthFhO5Ju6oco5n7NKe55hsu2UOxwIsx7G DHHX9eZhEj+IQzqEvKTHwsykpwqdt2Kjoiiv07in2eKNvVxW7/+hZ0pkW0Vd6P638qko cm+DcVenv2g6rkvNRTV2x5eHBKQ7r4CGnFDYkqF/dfbvZURx1piO6H+407HBNRZIeGdK bMpw== X-Gm-Message-State: AC+VfDzBrTqrdmynhu9+UbTpR6cH9JJZDSRdSd0lEqRhtPPwRI3V6yFY THcJfnl0aNvHqGHTLx4tEkGklmP5GkzTBEx8KbHBjg== X-Google-Smtp-Source: ACHHUZ4f40hphY+/ut5BvWhJUahsSDzHkq1aIKob5qOchkPLdEHBkjN8oMtHLh3RFK1+ntqTZB8haw== X-Received: by 2002:a1c:f408:0:b0:3f1:7372:f98f with SMTP id z8-20020a1cf408000000b003f17372f98fmr1839311wma.41.1683321892348; Fri, 05 May 2023 14:24:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PULL 06/42] target/mips: Finish conversion to tcg_gen_qemu_{ld, st}_* Date: Fri, 5 May 2023 22:24:11 +0100 Message-Id: <20230505212447.374546-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683322130049100003 Content-Type: text/plain; charset="utf-8" Convert away from the old interface with the implicit MemOp argument. Signed-off-by: Richard Henderson Reviewed-by: Anton Johansson Message-Id: <20230502135741.1158035-6-richard.henderson@linaro.org> --- target/mips/tcg/translate.c | 8 ++++---- target/mips/tcg/nanomips_translate.c.inc | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 999fbb7cc1..a6ca2e5a3b 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1949,13 +1949,13 @@ FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, = fd)) =20 /* load/store instructions. */ #ifdef CONFIG_USER_ONLY -#define OP_LD_ATOMIC(insn, fname) = \ +#define OP_LD_ATOMIC(insn, memop) = \ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, = \ DisasContext *ctx) = \ { = \ TCGv t0 =3D tcg_temp_new(); = \ tcg_gen_mov_tl(t0, arg1); = \ - tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); = \ + tcg_gen_qemu_ld_tl(ret, arg1, ctx->mem_idx, memop); = \ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); = \ tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); = \ } @@ -1967,9 +1967,9 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, = int mem_idx, \ gen_helper_##insn(ret, cpu_env, arg1, tcg_constant_i32(mem_idx)); = \ } #endif -OP_LD_ATOMIC(ll, ld32s); +OP_LD_ATOMIC(ll, MO_TESL); #if defined(TARGET_MIPS64) -OP_LD_ATOMIC(lld, ld64); +OP_LD_ATOMIC(lld, MO_TEUQ); #endif #undef OP_LD_ATOMIC =20 diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nan= omips_translate.c.inc index 9398e28000..97b9572caa 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -998,7 +998,7 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, = int16_t offset, TCGv tmp2 =3D tcg_temp_new(); =20 gen_base_offset_addr(ctx, taddr, base, offset); - tcg_gen_qemu_ld64(tval, taddr, ctx->mem_idx); + tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TEUQ); if (cpu_is_bigendian(ctx)) { tcg_gen_extr_i64_tl(tmp2, tmp1, tval); } else { --=20 2.34.1 From nobody Sat May 18 12:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322015; cv=none; d=zohomail.com; s=zohoarc; b=VHYzJzLwZArvh/cdS/rT0Lsn2Qx1o1yfr4Sa+tPzfmecB59V9LoaSPmkUwlPxiuFw+BrUflxRaDdrV36y3h852Owcj7uRhRfjuoizUHxEaWzpP7gzm50aMkwFC6WNm0f3jFV3abIFQEtmAGMMslOpjj8F+ap3nZIzzOBVLbzSq4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683322015; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=W4lFFawE3xIDuNSdeSLKcLA/U4uM/LgDoGJspbHlWdI=; b=K0ZSvoO38h25FJG1vfUY/wHrxMYXOZByemCnHRpkUNYQbQkKT5cZ59IzfK/BXhDgJ3mrvvQI+7VF30GTGH8mAjwfsNEp4Fz0Q9hPjIqfBS8nPo0lmPE2Yfcx6XVejgdNmnrF8OfvBVHXwh96OgRP/N0OJ5JcaPUr8gHsNP8oEK8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683322015164801.3984279944458; Fri, 5 May 2023 14:26:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vE-0000eJ-4f; Fri, 05 May 2023 17:25:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vB-0000cW-B6 for qemu-devel@nongnu.org; Fri, 05 May 2023 17:24:57 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2v8-0004ON-LG for qemu-devel@nongnu.org; Fri, 05 May 2023 17:24:57 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-30771c68a9eso1772342f8f.2 for ; Fri, 05 May 2023 14:24:54 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.24.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:24:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321893; x=1685913893; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W4lFFawE3xIDuNSdeSLKcLA/U4uM/LgDoGJspbHlWdI=; b=YkNOgkh4PYLB6Z6JgGBgnovLxIH70+57tCMC4mnFJV8c5fb3ZAi/ddMRAVw9X7knLZ IUfiWnZZN8LP6mQLDA+Q7TY3cJNzuKYSa3FwvBHw2M/esSXGj9PXvjVZe94oMdkeo10v DH8BSe0tLW6Yf9LXKk3NpZS/HKr9qihDa0rTcqASmrAZ+GTr8QXL44NW4uoMvULRbHto 3tK5LFrUwC+v+dGKqTNT/s+r1dLS+MyIebYxXgErX5TJ4nQCVqn41sjdPImR+q2G502Y BTgSEX1PofS3XA5V8+oczS2ZgNpUngbp1UeijC0rXl5erw+qkJDD/+mbr3wQFoYDyz6O sObA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321893; x=1685913893; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W4lFFawE3xIDuNSdeSLKcLA/U4uM/LgDoGJspbHlWdI=; b=jfJQnKSKLD8iegS3a92Mh38mBZz7KtjCpKTOXbnDy6r5XYLwJj7FUtEqdmpRuiN3y2 oXT6cIIyJ7MaVf3sjLTHxDoY5n7F4mR4Hq9MHLCXWV7UwWN3flzurO+kjC3Csn+h4dX2 UnEKN+YbHNeBiXZmY0gQInwv62EnvJ/iarT+iBpC2ZY8SGh7iqtaCwN9WsbdgylBX6sN jyRRKmuCVaRR+kWg5TJ6KMV7R6Cx0DzqqPpnFXIoeYU5nlToTFNLLj6lu3eQ/2S5VTAG iMmZXsbqOpJHqUvb/T3fvF2Y69LS8x0er4MtyDLsANVjpWrC38pvpo1tN4AnLBBzR3bY QXww== X-Gm-Message-State: AC+VfDza4OQU0/AankzRDXZ5I4sbioC8o5+uevAGBAi9Ew8TaGqwfHGg bwJzQfd9/I4Weon2vIITnCOmwlWd253goVOmC6E6mA== X-Google-Smtp-Source: ACHHUZ4NwkOe7pCyFEIdavENJA7I5kgcL0Scd5QJ1qUUfx+jDZ89mUUWuSb+qiGy+zh40333Q3FzUw== X-Received: by 2002:adf:fc8c:0:b0:306:3204:3633 with SMTP id g12-20020adffc8c000000b0030632043633mr2244337wrr.22.1683321892999; Fri, 05 May 2023 14:24:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: David Hildenbrand , Ilya Leoshkevich Subject: [PULL 07/42] target/s390x: Finish conversion to tcg_gen_qemu_{ld, st}_* Date: Fri, 5 May 2023 22:24:12 +0100 Message-Id: <20230505212447.374546-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322017237100005 Content-Type: text/plain; charset="utf-8" Convert away from the old interface with the implicit MemOp argument. Signed-off-by: Richard Henderson Reviewed-by: David Hildenbrand Reviewed-by: Ilya Leoshkevich Message-Id: <20230502135741.1158035-7-richard.henderson@linaro.org> --- target/s390x/tcg/translate.c | 152 ++++++++++++++++------------------- 1 file changed, 71 insertions(+), 81 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 46b874e94d..a05205beb1 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1973,32 +1973,24 @@ static DisasJumpType op_clc(DisasContext *s, DisasO= ps *o) { int l =3D get_field(s, l1); TCGv_i32 vl; + MemOp mop; =20 switch (l + 1) { case 1: - tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s)); - tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s)); - break; case 2: - tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s)); - tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s)); - break; case 4: - tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s)); - tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s)); - break; case 8: - tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s)); - tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s)); - break; + mop =3D ctz32(l + 1) | MO_TE; + tcg_gen_qemu_ld_tl(cc_src, o->addr1, get_mem_index(s), mop); + tcg_gen_qemu_ld_tl(cc_dst, o->in2, get_mem_index(s), mop); + gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst); + return DISAS_NEXT; default: vl =3D tcg_constant_i32(l); gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2); set_cc_static(s); return DISAS_NEXT; } - gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst); - return DISAS_NEXT; } =20 static DisasJumpType op_clcl(DisasContext *s, DisasOps *o) @@ -2199,7 +2191,7 @@ static DisasJumpType op_cvd(DisasContext *s, DisasOps= *o) TCGv_i32 t2 =3D tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(t2, o->in1); gen_helper_cvd(t1, t2); - tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s)); + tcg_gen_qemu_st_i64(t1, o->in2, get_mem_index(s), MO_TEUQ); return DISAS_NEXT; } =20 @@ -2457,7 +2449,7 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps= *o) switch (m3) { case 0xf: /* Effectively a 32-bit load. */ - tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_TEUL); len =3D 32; goto one_insert; =20 @@ -2465,7 +2457,7 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps= *o) case 0x6: case 0x3: /* Effectively a 16-bit load. */ - tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_TEUW); len =3D 16; goto one_insert; =20 @@ -2474,7 +2466,7 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps= *o) case 0x2: case 0x1: /* Effectively an 8-bit load. */ - tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB); len =3D 8; goto one_insert; =20 @@ -2490,7 +2482,7 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps= *o) ccm =3D 0; while (m3) { if (m3 & 0x8) { - tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB); tcg_gen_addi_i64(o->in2, o->in2, 1); tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8); ccm |=3D 0xffull << pos; @@ -2746,25 +2738,25 @@ static DisasJumpType op_llgt(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_ld8s(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_SB); return DISAS_NEXT; } =20 static DisasJumpType op_ld8u(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_UB); return DISAS_NEXT; } =20 static DisasJumpType op_ld16s(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TESW); return DISAS_NEXT; } =20 static DisasJumpType op_ld16u(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUW); return DISAS_NEXT; } =20 @@ -2803,7 +2795,7 @@ static DisasJumpType op_lat(DisasContext *s, DisasOps= *o) static DisasJumpType op_lgat(DisasContext *s, DisasOps *o) { TCGLabel *lab =3D gen_new_label(); - tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUQ); /* The value is stored even in case of trap. */ tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab); gen_trap(s); @@ -2825,7 +2817,8 @@ static DisasJumpType op_lfhat(DisasContext *s, DisasO= ps *o) static DisasJumpType op_llgfat(DisasContext *s, DisasOps *o) { TCGLabel *lab =3D gen_new_label(); - tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s)); + + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUL); /* The value is stored even in case of trap. */ tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab); gen_trap(s); @@ -2942,7 +2935,7 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasO= ps *o) tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUQ | MO_ALIGN_8); tcg_gen_addi_i64(o->in2, o->in2, 8); - tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(t2, o->in2, get_mem_index(s), MO_TEUQ); gen_helper_load_psw(cpu_env, t1, t2); return DISAS_NORETURN; } @@ -2966,7 +2959,7 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOp= s *o) /* Only one register to read. */ t1 =3D tcg_temp_new_i64(); if (unlikely(r1 =3D=3D r3)) { - tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); store_reg32_i64(r1, t1); return DISAS_NEXT; } @@ -2974,9 +2967,9 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOp= s *o) /* First load the values of the first and last registers to trigger possible page faults. */ t2 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); tcg_gen_addi_i64(t2, o->in2, 4 * ((r3 - r1) & 15)); - tcg_gen_qemu_ld32u(t2, t2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_TEUL); store_reg32_i64(r1, t1); store_reg32_i64(r3, t2); =20 @@ -2991,7 +2984,7 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOp= s *o) while (r1 !=3D r3) { r1 =3D (r1 + 1) & 15; tcg_gen_add_i64(o->in2, o->in2, t2); - tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); store_reg32_i64(r1, t1); } return DISAS_NEXT; @@ -3006,7 +2999,7 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps= *o) /* Only one register to read. */ t1 =3D tcg_temp_new_i64(); if (unlikely(r1 =3D=3D r3)) { - tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); store_reg32h_i64(r1, t1); return DISAS_NEXT; } @@ -3014,9 +3007,9 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps= *o) /* First load the values of the first and last registers to trigger possible page faults. */ t2 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); tcg_gen_addi_i64(t2, o->in2, 4 * ((r3 - r1) & 15)); - tcg_gen_qemu_ld32u(t2, t2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_TEUL); store_reg32h_i64(r1, t1); store_reg32h_i64(r3, t2); =20 @@ -3031,7 +3024,7 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps= *o) while (r1 !=3D r3) { r1 =3D (r1 + 1) & 15; tcg_gen_add_i64(o->in2, o->in2, t2); - tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL); store_reg32h_i64(r1, t1); } return DISAS_NEXT; @@ -3045,7 +3038,7 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOp= s *o) =20 /* Only one register to read. */ if (unlikely(r1 =3D=3D r3)) { - tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_TEUQ); return DISAS_NEXT; } =20 @@ -3053,9 +3046,9 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOp= s *o) possible page faults. */ t1 =3D tcg_temp_new_i64(); t2 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld64(t1, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUQ); tcg_gen_addi_i64(t2, o->in2, 8 * ((r3 - r1) & 15)); - tcg_gen_qemu_ld64(regs[r3], t2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(regs[r3], t2, get_mem_index(s), MO_TEUQ); tcg_gen_mov_i64(regs[r1], t1); =20 /* Only two registers to read. */ @@ -3069,7 +3062,7 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOp= s *o) while (r1 !=3D r3) { r1 =3D (r1 + 1) & 15; tcg_gen_add_i64(o->in2, o->in2, t1); - tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_TEUQ); } return DISAS_NEXT; } @@ -3923,15 +3916,15 @@ static DisasJumpType op_soc(DisasContext *s, DisasO= ps *o) a =3D get_address(s, 0, get_field(s, b2), get_field(s, d2)); switch (s->insn->data) { case 1: /* STOCG */ - tcg_gen_qemu_st64(regs[r1], a, get_mem_index(s)); + tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_TEUQ); break; case 0: /* STOC */ - tcg_gen_qemu_st32(regs[r1], a, get_mem_index(s)); + tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_TEUL); break; case 2: /* STOCFH */ h =3D tcg_temp_new_i64(); tcg_gen_shri_i64(h, regs[r1], 32); - tcg_gen_qemu_st32(h, a, get_mem_index(s)); + tcg_gen_qemu_st_i64(h, a, get_mem_index(s), MO_TEUL); break; default: g_assert_not_reached(); @@ -4050,7 +4043,7 @@ static DisasJumpType op_ectg(DisasContext *s, DisasOp= s *o) gen_addi_and_wrap_i64(s, o->addr1, regs[r3], 0); =20 /* load the third operand into r3 before modifying anything */ - tcg_gen_qemu_ld64(regs[r3], o->addr1, get_mem_index(s)); + tcg_gen_qemu_ld_i64(regs[r3], o->addr1, get_mem_index(s), MO_TEUQ); =20 /* subtract CPU timer from first operand and store in GR0 */ gen_helper_stpt(tmp, cpu_env); @@ -4128,9 +4121,9 @@ static DisasJumpType op_stcke(DisasContext *s, DisasO= ps *o) tcg_gen_shri_i64(c1, c1, 8); tcg_gen_ori_i64(c2, c2, 0x10000); tcg_gen_or_i64(c2, c2, todpr); - tcg_gen_qemu_st64(c1, o->in2, get_mem_index(s)); + tcg_gen_qemu_st_i64(c1, o->in2, get_mem_index(s), MO_TEUQ); tcg_gen_addi_i64(o->in2, o->in2, 8); - tcg_gen_qemu_st64(c2, o->in2, get_mem_index(s)); + tcg_gen_qemu_st_i64(c2, o->in2, get_mem_index(s), MO_TEUQ); /* ??? We don't implement clock states. */ gen_op_movi_cc(s, 0); return DISAS_NEXT; @@ -4343,7 +4336,7 @@ static DisasJumpType op_stnosm(DisasContext *s, Disas= Ops *o) restart, we'll have the wrong SYSTEM MASK in place. */ t =3D tcg_temp_new_i64(); tcg_gen_shri_i64(t, psw_mask, 56); - tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s)); + tcg_gen_qemu_st_i64(t, o->addr1, get_mem_index(s), MO_UB); =20 if (s->fields.op =3D=3D 0xac) { tcg_gen_andi_i64(psw_mask, psw_mask, @@ -4380,13 +4373,13 @@ static DisasJumpType op_stfle(DisasContext *s, Disa= sOps *o) =20 static DisasJumpType op_st8(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s)); + tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_UB); return DISAS_NEXT; } =20 static DisasJumpType op_st16(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s)); + tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_TEUW); return DISAS_NEXT; } =20 @@ -4424,7 +4417,7 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOp= s *o) case 0xf: /* Effectively a 32-bit store. */ tcg_gen_shri_i64(tmp, o->in1, pos); - tcg_gen_qemu_st32(tmp, o->in2, get_mem_index(s)); + tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_TEUL); break; =20 case 0xc: @@ -4432,7 +4425,7 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOp= s *o) case 0x3: /* Effectively a 16-bit store. */ tcg_gen_shri_i64(tmp, o->in1, pos); - tcg_gen_qemu_st16(tmp, o->in2, get_mem_index(s)); + tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_TEUW); break; =20 case 0x8: @@ -4441,7 +4434,7 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOp= s *o) case 0x1: /* Effectively an 8-bit store. */ tcg_gen_shri_i64(tmp, o->in1, pos); - tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s)); + tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_UB); break; =20 default: @@ -4450,7 +4443,7 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOp= s *o) while (m3) { if (m3 & 0x8) { tcg_gen_shri_i64(tmp, o->in1, pos); - tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s)); + tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_UB); tcg_gen_addi_i64(o->in2, o->in2, 1); } m3 =3D (m3 << 1) & 0xf; @@ -4469,11 +4462,8 @@ static DisasJumpType op_stm(DisasContext *s, DisasOp= s *o) TCGv_i64 tsize =3D tcg_constant_i64(size); =20 while (1) { - if (size =3D=3D 8) { - tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s)); - } else { - tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s)); - } + tcg_gen_qemu_st_i64(regs[r1], o->in2, get_mem_index(s), + size =3D=3D 8 ? MO_TEUQ : MO_TEUL); if (r1 =3D=3D r3) { break; } @@ -4494,7 +4484,7 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOp= s *o) =20 while (1) { tcg_gen_shl_i64(t, regs[r1], t32); - tcg_gen_qemu_st32(t, o->in2, get_mem_index(s)); + tcg_gen_qemu_st_i64(t, o->in2, get_mem_index(s), MO_TEUL); if (r1 =3D=3D r3) { break; } @@ -4804,28 +4794,28 @@ static DisasJumpType op_xc(DisasContext *s, DisasOp= s *o) =20 l++; while (l >=3D 8) { - tcg_gen_qemu_st64(o->in2, o->addr1, get_mem_index(s)); + tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UQ); l -=3D 8; if (l > 0) { tcg_gen_addi_i64(o->addr1, o->addr1, 8); } } if (l >=3D 4) { - tcg_gen_qemu_st32(o->in2, o->addr1, get_mem_index(s)); + tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UL); l -=3D 4; if (l > 0) { tcg_gen_addi_i64(o->addr1, o->addr1, 4); } } if (l >=3D 2) { - tcg_gen_qemu_st16(o->in2, o->addr1, get_mem_index(s)); + tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UW); l -=3D 2; if (l > 0) { tcg_gen_addi_i64(o->addr1, o->addr1, 2); } } if (l) { - tcg_gen_qemu_st8(o->in2, o->addr1, get_mem_index(s)); + tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UB); } gen_op_movi_cc(s, 0); return DISAS_NEXT; @@ -5314,13 +5304,13 @@ static void wout_cond_e1e2(DisasContext *s, DisasOp= s *o) =20 static void wout_m1_8(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s)); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_UB); } #define SPEC_wout_m1_8 0 =20 static void wout_m1_16(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s)); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUW); } #define SPEC_wout_m1_16 0 =20 @@ -5334,7 +5324,7 @@ static void wout_m1_16a(DisasContext *s, DisasOps *o) =20 static void wout_m1_32(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s)); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUL); } #define SPEC_wout_m1_32 0 =20 @@ -5348,7 +5338,7 @@ static void wout_m1_32a(DisasContext *s, DisasOps *o) =20 static void wout_m1_64(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s)); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUQ); } #define SPEC_wout_m1_64 0 =20 @@ -5362,7 +5352,7 @@ static void wout_m1_64a(DisasContext *s, DisasOps *o) =20 static void wout_m2_32(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s)); + tcg_gen_qemu_st_i64(o->out, o->in2, get_mem_index(s), MO_TEUL); } #define SPEC_wout_m2_32 0 =20 @@ -5557,7 +5547,7 @@ static void in1_m1_8u(DisasContext *s, DisasOps *o) { in1_la1(s, o); o->in1 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_UB); } #define SPEC_in1_m1_8u 0 =20 @@ -5565,7 +5555,7 @@ static void in1_m1_16s(DisasContext *s, DisasOps *o) { in1_la1(s, o); o->in1 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TESW); } #define SPEC_in1_m1_16s 0 =20 @@ -5573,7 +5563,7 @@ static void in1_m1_16u(DisasContext *s, DisasOps *o) { in1_la1(s, o); o->in1 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUW); } #define SPEC_in1_m1_16u 0 =20 @@ -5581,7 +5571,7 @@ static void in1_m1_32s(DisasContext *s, DisasOps *o) { in1_la1(s, o); o->in1 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TESL); } #define SPEC_in1_m1_32s 0 =20 @@ -5589,7 +5579,7 @@ static void in1_m1_32u(DisasContext *s, DisasOps *o) { in1_la1(s, o); o->in1 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUL); } #define SPEC_in1_m1_32u 0 =20 @@ -5597,7 +5587,7 @@ static void in1_m1_64(DisasContext *s, DisasOps *o) { in1_la1(s, o); o->in1 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUQ); } #define SPEC_in1_m1_64 0 =20 @@ -5811,35 +5801,35 @@ static void in2_sh(DisasContext *s, DisasOps *o) static void in2_m2_8u(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_UB); } #define SPEC_in2_m2_8u 0 =20 static void in2_m2_16s(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TESW); } #define SPEC_in2_m2_16s 0 =20 static void in2_m2_16u(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUW); } #define SPEC_in2_m2_16u 0 =20 static void in2_m2_32s(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TESL); } #define SPEC_in2_m2_32s 0 =20 static void in2_m2_32u(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUL); } #define SPEC_in2_m2_32u 0 =20 @@ -5855,14 +5845,14 @@ static void in2_m2_32ua(DisasContext *s, DisasOps *= o) static void in2_m2_64(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ); } #define SPEC_in2_m2_64 0 =20 static void in2_m2_64w(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ); gen_addi_and_wrap_i64(s, o->in2, o->in2, 0); } #define SPEC_in2_m2_64w 0 @@ -5879,14 +5869,14 @@ static void in2_m2_64a(DisasContext *s, DisasOps *o) static void in2_mri2_16s(DisasContext *s, DisasOps *o) { o->in2 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld16s(o->in2, gen_ri2(s), get_mem_index(s)); + tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_TESW); } #define SPEC_in2_mri2_16s 0 =20 static void in2_mri2_16u(DisasContext *s, DisasOps *o) { o->in2 =3D tcg_temp_new_i64(); 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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.24.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:24:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321893; x=1685913893; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TjEbOkYEfaAbJuhH9vdQBxzxPZocmNlfqwwgZV5jixE=; b=D2fWycMlUcVt7T+cMw7HWLKWlV5M+MTKwt5eUBLJG5jI+OW0PK1I+2V5vxVxGK2Yf9 jITcXwKwAtv/cGQl1bzJXE1rqEdwmaHhwQBYSQhzopS/MNvOHQcFOC0LNGTB9dR0o0lw U4d5N1PB1w1sJZC4EQUZWi/xTL99yEgGmCYPxaBz6XI4t0Gj/O/q87aqqF/UhfLE9L0I e0LAgBcwhB2kLfB1jMNWjyXkxCJRplnjyjKOryB616PyfbfkStQy01OojmT8MnZidaFw X2N4T2AZhJPEck8KL/sRzuHezx3YQdurA6jyS9/bFC/5AgqNx/f5yX07F8rMCmWVDvcf I3uA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321893; x=1685913893; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TjEbOkYEfaAbJuhH9vdQBxzxPZocmNlfqwwgZV5jixE=; b=baL3rkCMOZtRO4cO8rLJI7eDRLnbFsRgX1xvw4z1DYjdOpMb5N5Rr6sYoSw4NDXVDT GoSY0iQRcsZJpMPrI1UzB0av0QZeDeIIyLZJJQN3g2WNYqHZSzH5FTcyJNwnmDMT+uMO zowcH+xqX+Nbgu1jVb77ipyTT7ezDrK4xAqz99ousRCv+q5PuBoO2x/UPSBy2zvICrGJ pxRRFp+58a8Y7ITr+OU9mKylhkr2FxFxhsaMhBmZgouB3JPzQbwDCvlnvGBKf7WfzZeu sdPDLpmRrQbd0udHPPdZta0qhgxn8r5TpsA3pD6eMXk7ohQQ7QUrBTfpu2xi60ezKFLp u5MA== X-Gm-Message-State: AC+VfDwAYCmUrJ9eo8cNObtjNIB5HpHRvY/eJJEsb38eoAJdAiZOWLzy ttOJBF+YwAn6QHOiMpU6B89FVhvVNsWW2f/d6GyBPQ== X-Google-Smtp-Source: ACHHUZ4+OLS+Ep+cuvrJuFfnx9F8kCCUWQAp0FXP0ArT/xbNSQKqlkE1gLInDJ12jzlkpkKIzLDt3A== X-Received: by 2002:a7b:c8d9:0:b0:3f2:5be3:cd67 with SMTP id f25-20020a7bc8d9000000b003f25be3cd67mr1983578wml.18.1683321893542; Fri, 05 May 2023 14:24:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PULL 08/42] target/sparc: Finish conversion to tcg_gen_qemu_{ld, st}_* Date: Fri, 5 May 2023 22:24:13 +0100 Message-Id: <20230505212447.374546-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683321973556100001 Content-Type: text/plain; charset="utf-8" Convert away from the old interface with the implicit MemOp argument. Signed-off-by: Richard Henderson Reviewed-by: Anton Johansson Message-Id: <20230502135741.1158035-8-richard.henderson@linaro.org> --- target/sparc/translate.c | 43 ++++++++++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 15 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 137bdc5159..bc71e44e66 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5179,15 +5179,18 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) switch (xop) { case 0x0: /* ld, V9 lduw, load unsigned word */ gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx); + tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, + dc->mem_idx, MO_TEUL); break; case 0x1: /* ldub, load unsigned byte */ gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx); + tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, + dc->mem_idx, MO_UB); break; case 0x2: /* lduh, load unsigned halfword */ gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx); + tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, + dc->mem_idx, MO_TEUW); break; case 0x3: /* ldd, load double word */ if (rd & 1) @@ -5197,7 +5200,8 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) =20 gen_address_mask(dc, cpu_addr); t64 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld64(t64, cpu_addr, dc->mem_idx); + tcg_gen_qemu_ld_i64(t64, cpu_addr, + dc->mem_idx, MO_TEUQ); tcg_gen_trunc_i64_tl(cpu_val, t64); tcg_gen_ext32u_tl(cpu_val, cpu_val); gen_store_gpr(dc, rd + 1, cpu_val); @@ -5208,11 +5212,12 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) break; case 0x9: /* ldsb, load signed byte */ gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); + tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, dc->mem_idx, MO_= SB); break; case 0xa: /* ldsh, load signed halfword */ gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx); + tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, + dc->mem_idx, MO_TESW); break; case 0xd: /* ldstub */ gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx); @@ -5266,11 +5271,13 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) #ifdef TARGET_SPARC64 case 0x08: /* V9 ldsw */ gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx); + tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, + dc->mem_idx, MO_TESL); break; case 0x0b: /* V9 ldx */ gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx); + tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, + dc->mem_idx, MO_TEUQ); break; case 0x18: /* V9 ldswa */ gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL); @@ -5369,15 +5376,17 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) switch (xop) { case 0x4: /* st, store word */ gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); + tcg_gen_qemu_st_tl(cpu_val, cpu_addr, + dc->mem_idx, MO_TEUL); break; case 0x5: /* stb, store byte */ gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx); + tcg_gen_qemu_st_tl(cpu_val, cpu_addr, dc->mem_idx, MO_= UB); break; case 0x6: /* sth, store halfword */ gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx); + tcg_gen_qemu_st_tl(cpu_val, cpu_addr, + dc->mem_idx, MO_TEUW); break; case 0x7: /* std, store double word */ if (rd & 1) @@ -5390,7 +5399,8 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) lo =3D gen_load_gpr(dc, rd + 1); t64 =3D tcg_temp_new_i64(); tcg_gen_concat_tl_i64(t64, lo, cpu_val); - tcg_gen_qemu_st64(t64, cpu_addr, dc->mem_idx); + tcg_gen_qemu_st_i64(t64, cpu_addr, + dc->mem_idx, MO_TEUQ); } break; #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) @@ -5413,7 +5423,8 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) #ifdef TARGET_SPARC64 case 0x0e: /* V9 stx */ gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx); + tcg_gen_qemu_st_tl(cpu_val, cpu_addr, + dc->mem_idx, MO_TEUQ); break; case 0x1e: /* V9 stxa */ gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ); @@ -5438,11 +5449,13 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) #ifdef TARGET_SPARC64 gen_address_mask(dc, cpu_addr); if (rd =3D=3D 1) { - tcg_gen_qemu_st64(cpu_fsr, cpu_addr, dc->mem_i= dx); + tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr, + dc->mem_idx, MO_TEUQ); break; } #endif - tcg_gen_qemu_st32(cpu_fsr, cpu_addr, dc->mem_idx); + tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr, + dc->mem_idx, MO_TEUL); } break; case 0x26: --=20 2.34.1 From nobody Sat May 18 12:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322200; cv=none; d=zohomail.com; s=zohoarc; b=ATlmWR7jOkqSJh+XhvMiOfHDtFvJPlVkqviwlunnRipVItGKTK1mLgHUztNANHSfrs5aPcFJQu8PX6T43LJiTXcJnwX9IE1dfLC6TynV4V4PsU6KrKDBiOlP/ifYN89qQcWcog5ZnlN1wbek6zlSOusqXJxsMtvgo/vOGeGHsB0= ARC-Message-Signature: i=1; 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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.24.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:24:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321894; x=1685913894; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7LBuNmVB+VRtISP57Rd/VwE7/BgCkmrVs2in5OT4+XQ=; b=m9U60h9k0ecvMxfzjSNT7HSUkVnYikEPFPwr5W/cR9r3smJse/IlM8rLWAGkEAoNFG DoZVoluy8lMA+eKzt5WZ/Fom4g2/v368JkfBrq7hvMeYq3zAZyCtQWn8ROiR1RAOauZb YbMkynyieCoeDyRswHdO6FNVviZfrBggPPUrWq/5J53abzmcjnTNd1oF3tN0c8kDCyvk xR6opaLmDazu9Uorox/ZurLT+mltUKiWa6OEIqQn/mvMXCk6Xh1Co0WMVp06CLIiK/R8 TA6Ooi5VeSCqQ77+a1eqJSjgGmCZCu6o6awACrXLp9EUMVh2ClnHiagkop9HPrPY9MH7 kJzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321894; x=1685913894; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7LBuNmVB+VRtISP57Rd/VwE7/BgCkmrVs2in5OT4+XQ=; b=fSuSP+SN6uzbVGjLiF0ZcqGV2fG5dGwDe2Xtfvw+NedEHn9SAcSXyKLxkRgM03Elrz FWnyr07+ktncgoj6XPW10byo2GvuXcumWY2zcFksPZxjheR7IFSP3gLQImp+uEbSTAib 0grELdoxaV8OnXyvrSas9foKob9tzrsxT4aPCxseNr6u87dv5wWFAk+oz6UTJwmTSCKl HEJK5dKu80n+Vfp5ptSmNiydzfbkd40UGB7VGM+xemVQT0ZAOJNkmkEZadWczAlRIZIR cvzVWpYbYpIX1w5WdTzBnbzQH/wTLWlRuCeGVrREz7WRDy/ORy3tEyEd5FV+pApZfuaE ImBw== X-Gm-Message-State: AC+VfDxHHXW781TKQ1Rjp+/dCClS/lLorkepDZ5rTPeNaLfO102ZwAYK LvrFAnlelt+X1qGdro+CnFGcopFdsXJlBXUu7X1EYQ== X-Google-Smtp-Source: ACHHUZ4X20/2kSJY3a9mrScZXtFolm8q/5KZdehzpnA6BGNtfWvqxxf5OiR97Z+mHQ56BD56MLlK/g== X-Received: by 2002:a05:600c:21cf:b0:3dc:55d9:ec8 with SMTP id x15-20020a05600c21cf00b003dc55d90ec8mr1908505wmj.41.1683321894046; Fri, 05 May 2023 14:24:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Max Filippov Subject: [PULL 09/42] target/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_* Date: Fri, 5 May 2023 22:24:14 +0100 Message-Id: <20230505212447.374546-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322201848100003 Content-Type: text/plain; charset="utf-8" Convert away from the old interface with the implicit MemOp argument. Signed-off-by: Richard Henderson Reviewed-by: Max Filippov Message-Id: <20230502135741.1158035-9-richard.henderson@linaro.org> --- target/xtensa/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 0cf3075649..728aeebebf 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1549,7 +1549,7 @@ static void translate_dcache(DisasContext *dc, const = OpcodeArg arg[], TCGv_i32 res =3D tcg_temp_new_i32(); =20 tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm); - tcg_gen_qemu_ld8u(res, addr, dc->cring); + tcg_gen_qemu_ld_i32(res, addr, dc->cring, MO_UB); } =20 static void translate_depbits(DisasContext *dc, const OpcodeArg arg[], @@ -1726,7 +1726,7 @@ static void translate_l32r(DisasContext *dc, const Op= codeArg arg[], } else { tmp =3D tcg_constant_i32(arg[1].imm); } - tcg_gen_qemu_ld32u(arg[0].out, tmp, dc->cring); + tcg_gen_qemu_ld_i32(arg[0].out, tmp, dc->cring, MO_TEUL); } =20 static void translate_loop(DisasContext *dc, const OpcodeArg arg[], --=20 2.34.1 From nobody Sat May 18 12:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322001; cv=none; d=zohomail.com; s=zohoarc; b=HafyW0dBCLBwqIj3cP/o2OvyxNFMvBWk1QoXQHvrmsGTGv+mEeUKZySQ85+YIBGq5kazbG8e1IkUEdMmScXOjacvoeJdoMlP3meB0Avwhzoq8J/SF7l0r7CwfXHM6dDJylQpORraOgxiV7ZcxlhGihhST65LllBt04wmmE8KBRE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683322001; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bOXqUcEIKY7lYB4B2J+FOo94uyYip8zFUIfwUoelhLc=; b=L+d4Hhuwoo7LsxubN0Mbd7t0v2IuULxGYR+n3jEtyIP9SoqRbVQ/zpBmMb7hDgBsAFu/btOuaB2DGsF0W7VHbvqyc8Ndtfk1LdiPm/p62ehKY572kgK8EfVxNyQYwcQUYN9KJ7Mvt4/uNlCDhE5UdYqCh5EdJw0Cn05aKnsyLw8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168332200120789.21199257388855; Fri, 5 May 2023 14:26:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vD-0000eB-Mj; Fri, 05 May 2023 17:24:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vC-0000dL-LM for qemu-devel@nongnu.org; Fri, 05 May 2023 17:24:58 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2vA-0004P4-2M for qemu-devel@nongnu.org; Fri, 05 May 2023 17:24:58 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-3f19a7f9424so23070775e9.2 for ; Fri, 05 May 2023 14:24:55 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.24.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:24:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321894; x=1685913894; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bOXqUcEIKY7lYB4B2J+FOo94uyYip8zFUIfwUoelhLc=; b=N8XbGOn3jryyqdBF+LSeNzvGmLZhb12N8iNx1K9pHJI0odgUrgb3QyVLJVoNN3LPbB D0CtxOX83zjUhe1Z55h0RDfqaisbjI1ghtH3kXgWuHuiwlVgQQy0xz2j445IHMxXO7y+ ioR4NxRRZ28mO4SxY6fYasjpqznUkd9GmQ4/BZEURLg+4/Ppuf4BTVjW6kOgk5vLjYJ/ AkDE4Vxt0bwrEJHgBdMNBK7k9ktsvxmdm0LOZkUqnjQOL9tgEb6MHAH2X6orFgBcFQtQ W32nHlK2OmfIvSCLDE373ARKBLIsTESTX6GK1KN84Bm33xN3Ez/PL4TuhQtblUnQ/zfR Qo8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321894; x=1685913894; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bOXqUcEIKY7lYB4B2J+FOo94uyYip8zFUIfwUoelhLc=; b=fHhI1RAlnW5bLR7E4G2Rc0AKhF3+VNd9sT5REzD4Uh3KiK3X8KSp4I28k/eh2zJi85 ajkOKcn3zp6Z4GonhBughYd+Nm/VG5WDy8i4jdI5hbBeXM+iqUZ7o0oP/eP5rYdZyPta 8OD6QTbVnscMx2k662806WbWhXpQT4j0IL0qs81a2h2VOK6dnC+LK0Lqx7PfiW8A7oNW 4C7iAVI+Pg2LsB2KOHlcbrRUt+8f6um8sT8jV+EcfnFcvSODUMKEw+5D5+yeaJNOQR+v kTcQUEFvoiMzJ/+JMLjL8WxE8djgPn6+IVz2qEsf0BWTnSKj3/GR6K97XUPRTIFdAwLQ rduQ== X-Gm-Message-State: AC+VfDyEA3YK62NSmFmXZ49n1uz9ZP0rZuWDkJM2Mdhqh57pldhFt2/4 v2zWSTm280b5qYgGwMLtNu/KtMdWDuqM6kaZoF2HPA== X-Google-Smtp-Source: ACHHUZ7p9FQOSAiTO9VD1hvDZ4+jt8dYm4H3B5k+Z11J2xbwRSmxvKuj1XC9YBvJNxk7T3wgxbQX4g== X-Received: by 2002:a5d:4570:0:b0:306:44a9:76a1 with SMTP id a16-20020a5d4570000000b0030644a976a1mr2040826wrc.17.1683321894682; Fri, 05 May 2023 14:24:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: David Hildenbrand Subject: [PULL 10/42] tcg: Remove compatability helpers for qemu ld/st Date: Fri, 5 May 2023 22:24:15 +0100 Message-Id: <20230505212447.374546-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322003288100003 Content-Type: text/plain; charset="utf-8" Remove the old interfaces with the implicit MemOp argument. Signed-off-by: Richard Henderson Acked-by: David Hildenbrand Message-Id: <20230502135741.1158035-10-richard.henderson@linaro.org> --- include/tcg/tcg-op.h | 55 -------------------------------------------- 1 file changed, 55 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index dff17c7072..4401fa493c 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -841,61 +841,6 @@ void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, MemOp= ); void tcg_gen_qemu_ld_i128(TCGv_i128, TCGv, TCGArg, MemOp); void tcg_gen_qemu_st_i128(TCGv_i128, TCGv, TCGArg, MemOp); =20 -static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) -{ - tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB); -} - -static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) -{ - tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB); -} - -static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) -{ - tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW); -} - -static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) -{ - tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW); -} - -static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) -{ - tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL); -} - -static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) -{ - tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL); -} - -static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_inde= x) -{ - tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEUQ); -} - -static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) -{ - tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB); -} - -static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) -{ - tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW); -} - -static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) -{ - tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL); -} - -static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_inde= x) -{ - tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEUQ); -} - void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32, TCGArg, MemOp); void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, --=20 2.34.1 From nobody Sat May 18 12:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683321989; cv=none; d=zohomail.com; s=zohoarc; b=Lgp4jFuTzf6qiI5vw2N2rX7SbfPhOMbtduD1rug1F4g42YvMnXXsc5X1qlT3Xg0c1PyMlhQRiMVoI1eP3OwgdQwcQRldGNsxpUML8b2T2wNqw0cYr0Ii9CJd8hZ0+8Lx+s+YI1bfCTrYqjEElqE0eMm5q53zGzwFGjSW8zY2sl8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683321989; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yNUcAaiIsith4A3MmMU6YaHlVSgymDmwyA221woU1dE=; b=QD9Mc24Ztu4q8FtYzhuKejKzSYJNKD9YEsJIH/zdaVMxvn2EWOgkrTQpVBytrES6cirnAE10c8I7LMisBgDuVkDqpUdWe+wbNFSTk9QhildbRn4NOaiqqxW2CyezZSVsX/2ztm0ODH2gE4BE4h51zTZ89/YyR5Cab9eYclSH8Tk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683321989007394.9900287500776; Fri, 5 May 2023 14:26:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vQ-0000ik-4d; Fri, 05 May 2023 17:25:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vG-0000fU-Gj for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:02 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2vA-0004PE-Jp for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:01 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-3f19a7f9424so23070825e9.2 for ; Fri, 05 May 2023 14:24:56 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.24.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:24:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321895; x=1685913895; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=yNUcAaiIsith4A3MmMU6YaHlVSgymDmwyA221woU1dE=; b=Cyb9TpQ/l0BUxNmuXvWt6Aj15lIAMnoJq0RLiab7h9mVHunwInJZdxPq8NNmgXAhEX i7DmspPioHFYW6v5vxcS2HA886pD7PuJNFYRAaBkwSef6vgrXsUOnYYlSxHOVWzF4DcB Qe6QdfcReVAOcTeoNQZsKX8UlBZtaIaHqH/0lurmXumC3RgK/Fmdw3amtxK4BvCERV6j OaXxMFafqEHzVEmryinUbUIcONS82v5G1JHL0rReqn+/TYdSrBLIWgwQZuYJIcIuMv8w VSIBJhqiG8JUSOtTedN4Y8Is5XOmYd1y/otDvsNIlgPwQH16EbbrI9zXmAgFVUjAgSoa NyEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321895; x=1685913895; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683321991000100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/alpha/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 9d25e21164..ffbac1c114 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -72,7 +72,7 @@ struct DisasContext { #ifdef CONFIG_USER_ONLY #define UNALIGN(C) (C)->unalign #else -#define UNALIGN(C) 0 +#define UNALIGN(C) MO_ALIGN #endif =20 /* Target-specific return values from translate_one, indicating the --=20 2.34.1 From nobody Sat May 18 12:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.24.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:24:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321895; x=1685913895; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ElGkLkSZPG5U6w3IO50r2nvTqh+XRQqzsanCGPviKUM=; b=P11v89p/kYe/QKuxd5Q+vYui7Z9Y2GSwDaurVNDl6QX0xFizo3ICsLRvRxDrjKytUT Iz4RpbqrucY6uKu1Inv7VQr+UiDirbHQCaLBcoZqJEy3xNyfYy1Kxkh/74l8GcW1lUgl r+HfgQ+REFqBYPUAzeHew0pU1Nd4lYq3FEMeOeSI9p6feHV+GQIrsrY8ck2JRgALDg0X rk8yLXsoSWa/5jnR3fhXaYqRBLMxH+QX4dDimHtV6NIja0mVuGvbIyZy5iPHovUPNVK2 pQKfBuzw6AlYvYJ5NzzspCMh6UQVJ2Sh8I2ltzx6SdyTkjdrv1joGDrgPxdwFLRCyE1+ xwPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321895; x=1685913895; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ElGkLkSZPG5U6w3IO50r2nvTqh+XRQqzsanCGPviKUM=; b=DK0YF/IxkuX2J2Bp3lg+Ks9mmlfiY2Q+b1XQWFdd2l/D+lNUk8f9ReZg92s/aPBH+4 0aphv4lsaeZctfmVEYXQk9sT2WrJFD7Dxcq0lTyxTjUHNes7AE67OJKH+mCJIm4CP/BF AlWoHyS5knpGDqNmJ6xGbGMalGFE1+esYy4tHbgcwI41aSwc84BAPgpYS5V4ZhVZPWnU lSLMfn0wmrV2pRlEOD2Gfd2ltQThfPJMfs/ME1zEMI4O0kFp8WBMEk59I3leeMqBKrrJ MiRbssMO5B0CDsp+qwIpdvAKcp9+roZkZ4HyXCFECqosvYmlthCcp7sF3vtGAd/Rz4DN LHiA== X-Gm-Message-State: AC+VfDxyaoZRLS5iNRjz8pKDgKB8nHvpLur0TIMqZr2y/or2pylGT/oa y9C+rW8GF640/Z8wXDtOzDGJP8R38SRZbriKWYXT0A== X-Google-Smtp-Source: ACHHUZ4vYXmccZmbBm+oGX7Y7ZdsETqLqOIcLKl1kyWdRR4ZRKVFla4jqOQpahfwUVX649n1W98lZQ== X-Received: by 2002:a5d:6309:0:b0:304:7eaa:b196 with SMTP id i9-20020a5d6309000000b003047eaab196mr2343596wru.24.1683321895740; Fri, 05 May 2023 14:24:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 12/42] target/alpha: Use MO_ALIGN where required Date: Fri, 5 May 2023 22:24:17 +0100 Message-Id: <20230505212447.374546-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322162178100001 Content-Type: text/plain; charset="utf-8" Mark all memory operations that are not already marked with UNALIGN. Signed-off-by: Richard Henderson --- target/alpha/translate.c | 36 ++++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index ffbac1c114..be8adb2526 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2399,21 +2399,21 @@ static DisasJumpType translate_one(DisasContext *ct= x, uint32_t insn) switch ((insn >> 12) & 0xF) { case 0x0: /* Longword physical access (hw_ldl/p) */ - tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL); + tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL | MO_A= LIGN); break; case 0x1: /* Quadword physical access (hw_ldq/p) */ - tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEUQ); + tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEUQ | MO_A= LIGN); break; case 0x2: /* Longword physical access with lock (hw_ldl_l/p) */ - tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL); + tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL | MO_A= LIGN); tcg_gen_mov_i64(cpu_lock_addr, addr); tcg_gen_mov_i64(cpu_lock_value, va); break; case 0x3: /* Quadword physical access with lock (hw_ldq_l/p) */ - tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEUQ); + tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEUQ | MO_A= LIGN); tcg_gen_mov_i64(cpu_lock_addr, addr); tcg_gen_mov_i64(cpu_lock_value, va); break; @@ -2438,11 +2438,13 @@ static DisasJumpType translate_one(DisasContext *ct= x, uint32_t insn) goto invalid_opc; case 0xA: /* Longword virtual access with protection check (hw_ldl/w= ) */ - tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX, MO_LESL); + tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX, + MO_LESL | MO_ALIGN); break; case 0xB: /* Quadword virtual access with protection check (hw_ldq/w= ) */ - tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX, MO_LEUQ); + tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX, + MO_LEUQ | MO_ALIGN); break; case 0xC: /* Longword virtual access with alt access mode (hw_ldl/a)= */ @@ -2453,12 +2455,14 @@ static DisasJumpType translate_one(DisasContext *ct= x, uint32_t insn) case 0xE: /* Longword virtual access with alternate access mode and protection checks (hw_ldl/wa) */ - tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX, MO_LESL); + tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX, + MO_LESL | MO_ALIGN); break; case 0xF: /* Quadword virtual access with alternate access mode and protection checks (hw_ldq/wa) */ - tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX, MO_LEUQ); + tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX, + MO_LEUQ | MO_ALIGN); break; } break; @@ -2659,7 +2663,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) vb =3D load_gpr(ctx, rb); tmp =3D tcg_temp_new(); tcg_gen_addi_i64(tmp, vb, disp12); - tcg_gen_qemu_st_i64(va, tmp, MMU_PHYS_IDX, MO_LESL); + tcg_gen_qemu_st_i64(va, tmp, MMU_PHYS_IDX, MO_LESL | MO_AL= IGN); break; case 0x1: /* Quadword physical access */ @@ -2667,17 +2671,17 @@ static DisasJumpType translate_one(DisasContext *ct= x, uint32_t insn) vb =3D load_gpr(ctx, rb); tmp =3D tcg_temp_new(); tcg_gen_addi_i64(tmp, vb, disp12); - tcg_gen_qemu_st_i64(va, tmp, MMU_PHYS_IDX, MO_LEUQ); + tcg_gen_qemu_st_i64(va, tmp, MMU_PHYS_IDX, MO_LEUQ | MO_AL= IGN); break; case 0x2: /* Longword physical access with lock */ ret =3D gen_store_conditional(ctx, ra, rb, disp12, - MMU_PHYS_IDX, MO_LESL); + MMU_PHYS_IDX, MO_LESL | MO_ALI= GN); break; case 0x3: /* Quadword physical access with lock */ ret =3D gen_store_conditional(ctx, ra, rb, disp12, - MMU_PHYS_IDX, MO_LEUQ); + MMU_PHYS_IDX, MO_LEUQ | MO_ALI= GN); break; case 0x4: /* Longword virtual access */ @@ -2771,11 +2775,11 @@ static DisasJumpType translate_one(DisasContext *ct= x, uint32_t insn) break; case 0x2A: /* LDL_L */ - gen_load_int(ctx, ra, rb, disp16, MO_LESL, 0, 1); + gen_load_int(ctx, ra, rb, disp16, MO_LESL | MO_ALIGN, 0, 1); break; case 0x2B: /* LDQ_L */ - gen_load_int(ctx, ra, rb, disp16, MO_LEUQ, 0, 1); + gen_load_int(ctx, ra, rb, disp16, MO_LEUQ | MO_ALIGN, 0, 1); break; case 0x2C: /* STL */ @@ -2788,12 +2792,12 @@ static DisasJumpType translate_one(DisasContext *ct= x, uint32_t insn) case 0x2E: /* STL_C */ ret =3D gen_store_conditional(ctx, ra, rb, disp16, - ctx->mem_idx, MO_LESL); + ctx->mem_idx, MO_LESL | MO_ALIGN); break; case 0x2F: /* STQ_C */ ret =3D gen_store_conditional(ctx, ra, rb, disp16, - ctx->mem_idx, MO_LEUQ); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322050484100015 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- configs/targets/alpha-linux-user.mak | 1 - configs/targets/alpha-softmmu.mak | 1 - 2 files changed, 2 deletions(-) diff --git a/configs/targets/alpha-linux-user.mak b/configs/targets/alpha-l= inux-user.mak index 7e62fd796a..f7d3fb4afa 100644 --- a/configs/targets/alpha-linux-user.mak +++ b/configs/targets/alpha-linux-user.mak @@ -1,4 +1,3 @@ TARGET_ARCH=3Dalpha TARGET_SYSTBL_ABI=3Dcommon TARGET_SYSTBL=3Dsyscall.tbl -TARGET_ALIGNED_ONLY=3Dy diff --git a/configs/targets/alpha-softmmu.mak b/configs/targets/alpha-soft= mmu.mak index e4b874a19e..9dbe160740 100644 --- a/configs/targets/alpha-softmmu.mak +++ b/configs/targets/alpha-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=3Dalpha -TARGET_ALIGNED_ONLY=3Dy TARGET_SUPPORTS_MTTCG=3Dy --=20 2.34.1 From nobody Sat May 18 12:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683321997235100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 6a3154ebc6..59e4688bfa 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -271,7 +271,7 @@ typedef struct DisasContext { #ifdef CONFIG_USER_ONLY #define UNALIGN(C) (C)->unalign #else -#define UNALIGN(C) 0 +#define UNALIGN(C) MO_ALIGN #endif =20 /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ --=20 2.34.1 From nobody Sat May 18 12:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322064809100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- configs/targets/hppa-linux-user.mak | 1 - configs/targets/hppa-softmmu.mak | 1 - 2 files changed, 2 deletions(-) diff --git a/configs/targets/hppa-linux-user.mak b/configs/targets/hppa-lin= ux-user.mak index db873a8796..361ea39d71 100644 --- a/configs/targets/hppa-linux-user.mak +++ b/configs/targets/hppa-linux-user.mak @@ -1,5 +1,4 @@ TARGET_ARCH=3Dhppa TARGET_SYSTBL_ABI=3Dcommon,32 TARGET_SYSTBL=3Dsyscall.tbl -TARGET_ALIGNED_ONLY=3Dy TARGET_BIG_ENDIAN=3Dy diff --git a/configs/targets/hppa-softmmu.mak b/configs/targets/hppa-softmm= u.mak index 44f07b0332..a41662aa99 100644 --- a/configs/targets/hppa-softmmu.mak +++ b/configs/targets/hppa-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=3Dhppa -TARGET_ALIGNED_ONLY=3Dy TARGET_BIG_ENDIAN=3Dy TARGET_SUPPORTS_MTTCG=3Dy --=20 2.34.1 From nobody Sat May 18 12:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322108140100003 Content-Type: text/plain; charset="utf-8" Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 66 +++++++++++++++++++++------------------- 1 file changed, 34 insertions(+), 32 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index bc71e44e66..414e014b11 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1899,7 +1899,7 @@ static void gen_swap(DisasContext *dc, TCGv dst, TCGv= src, TCGv addr, int mmu_idx, MemOp memop) { gen_address_mask(dc, addr); - tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop); + tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop | MO_ALIGN); } =20 static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx) @@ -2155,12 +2155,12 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, = TCGv addr, break; case GET_ASI_DIRECT: gen_address_mask(dc, addr); - tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop); + tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop | MO_ALIGN); break; default: { TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); - TCGv_i32 r_mop =3D tcg_constant_i32(memop); + TCGv_i32 r_mop =3D tcg_constant_i32(memop | MO_ALIGN); =20 save_state(dc); #ifdef TARGET_SPARC64 @@ -2201,7 +2201,7 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TC= Gv addr, /* fall through */ case GET_ASI_DIRECT: gen_address_mask(dc, addr); - tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop); + tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop | MO_ALIGN); break; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) case GET_ASI_BCOPY: @@ -2233,7 +2233,7 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TC= Gv addr, default: { TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); - TCGv_i32 r_mop =3D tcg_constant_i32(memop & MO_SIZE); + TCGv_i32 r_mop =3D tcg_constant_i32(memop | MO_ALIGN); =20 save_state(dc); #ifdef TARGET_SPARC64 @@ -2283,7 +2283,7 @@ static void gen_cas_asi(DisasContext *dc, TCGv addr, = TCGv cmpv, case GET_ASI_DIRECT: oldv =3D tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd), - da.mem_idx, da.memop); + da.mem_idx, da.memop | MO_ALIGN); gen_store_gpr(dc, rd, oldv); break; default: @@ -2347,7 +2347,7 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr, switch (size) { case 4: d32 =3D gen_dest_fpr_F(dc); - tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop); + tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop | MO_ALIGN= ); gen_store_fpr_F(dc, rd, d32); break; case 8: @@ -2397,7 +2397,8 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr, /* Valid for lddfa only. */ if (size =3D=3D 8) { gen_address_mask(dc, addr); - tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memo= p); + tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, + da.memop | MO_ALIGN); } else { gen_exception(dc, TT_ILL_INSN); } @@ -2406,7 +2407,7 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr, default: { TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); - TCGv_i32 r_mop =3D tcg_constant_i32(da.memop); + TCGv_i32 r_mop =3D tcg_constant_i32(da.memop | MO_ALIGN); =20 save_state(dc); /* According to the table in the UA2011 manual, the only @@ -2454,7 +2455,7 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr, switch (size) { case 4: d32 =3D gen_load_fpr_F(dc, rd); - tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop); + tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop | MO_ALIGN= ); break; case 8: tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, @@ -2506,7 +2507,8 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr, /* Valid for stdfa only. */ if (size =3D=3D 8) { gen_address_mask(dc, addr); - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, da.memo= p); + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, + da.memop | MO_ALIGN); } else { gen_exception(dc, TT_ILL_INSN); } @@ -2543,7 +2545,7 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr,= int insn, int rd) TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 gen_address_mask(dc, addr); - tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop); + tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop | MO_ALIGN= ); =20 /* Note that LE ldda acts as if each 32-bit register result is byte swapped. Having just performed one @@ -2613,7 +2615,7 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, T= CGv addr, tcg_gen_concat32_i64(t64, hi, lo); } gen_address_mask(dc, addr); - tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop); + tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN= ); } break; =20 @@ -2651,7 +2653,7 @@ static void gen_casx_asi(DisasContext *dc, TCGv addr,= TCGv cmpv, case GET_ASI_DIRECT: oldv =3D tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd), - da.mem_idx, da.memop); + da.mem_idx, da.memop | MO_ALIGN); gen_store_gpr(dc, rd, oldv); break; default: @@ -2678,7 +2680,7 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr,= int insn, int rd) return; case GET_ASI_DIRECT: gen_address_mask(dc, addr); - tcg_gen_qemu_ld_i64(t64, addr, da.mem_idx, da.memop); + tcg_gen_qemu_ld_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN); break; default: { @@ -2710,7 +2712,7 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, T= CGv addr, break; case GET_ASI_DIRECT: gen_address_mask(dc, addr); - tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop); + tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN); break; case GET_ASI_BFILL: /* Store 32 bytes of T64 to ADDR. */ @@ -5180,7 +5182,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) case 0x0: /* ld, V9 lduw, load unsigned word */ gen_address_mask(dc, cpu_addr); tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUL); + dc->mem_idx, MO_TEUL | MO_ALIGN); break; case 0x1: /* ldub, load unsigned byte */ gen_address_mask(dc, cpu_addr); @@ -5190,7 +5192,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) case 0x2: /* lduh, load unsigned halfword */ gen_address_mask(dc, cpu_addr); tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUW); + dc->mem_idx, MO_TEUW | MO_ALIGN); break; case 0x3: /* ldd, load double word */ if (rd & 1) @@ -5201,7 +5203,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) gen_address_mask(dc, cpu_addr); t64 =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(t64, cpu_addr, - dc->mem_idx, MO_TEUQ); + dc->mem_idx, MO_TEUQ | MO_ALIG= N); tcg_gen_trunc_i64_tl(cpu_val, t64); tcg_gen_ext32u_tl(cpu_val, cpu_val); gen_store_gpr(dc, rd + 1, cpu_val); @@ -5217,7 +5219,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) case 0xa: /* ldsh, load signed halfword */ gen_address_mask(dc, cpu_addr); tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TESW); + dc->mem_idx, MO_TESW | MO_ALIGN); break; case 0xd: /* ldstub */ gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx); @@ -5272,12 +5274,12 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) case 0x08: /* V9 ldsw */ gen_address_mask(dc, cpu_addr); tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TESL); + dc->mem_idx, MO_TESL | MO_ALIGN); break; case 0x0b: /* V9 ldx */ gen_address_mask(dc, cpu_addr); tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUQ); + dc->mem_idx, MO_TEUQ | MO_ALIGN); break; case 0x18: /* V9 ldswa */ gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL); @@ -5328,7 +5330,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) gen_address_mask(dc, cpu_addr); cpu_dst_32 =3D gen_dest_fpr_F(dc); tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr, - dc->mem_idx, MO_TEUL); + dc->mem_idx, MO_TEUL | MO_ALIGN); gen_store_fpr_F(dc, rd, cpu_dst_32); break; case 0x21: /* ldfsr, V9 ldxfsr */ @@ -5337,14 +5339,14 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) if (rd =3D=3D 1) { TCGv_i64 t64 =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(t64, cpu_addr, - dc->mem_idx, MO_TEUQ); + dc->mem_idx, MO_TEUQ | MO_ALIG= N); gen_helper_ldxfsr(cpu_fsr, cpu_env, cpu_fsr, t64); break; } #endif cpu_dst_32 =3D tcg_temp_new_i32(); tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr, - dc->mem_idx, MO_TEUL); + dc->mem_idx, MO_TEUL | MO_ALIGN); gen_helper_ldfsr(cpu_fsr, cpu_env, cpu_fsr, cpu_dst_32= ); break; case 0x22: /* ldqf, load quad fpreg */ @@ -5377,7 +5379,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) case 0x4: /* st, store word */ gen_address_mask(dc, cpu_addr); tcg_gen_qemu_st_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUL); + dc->mem_idx, MO_TEUL | MO_ALIGN); break; case 0x5: /* stb, store byte */ gen_address_mask(dc, cpu_addr); @@ -5386,7 +5388,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) case 0x6: /* sth, store halfword */ gen_address_mask(dc, cpu_addr); tcg_gen_qemu_st_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUW); + dc->mem_idx, MO_TEUW | MO_ALIGN); break; case 0x7: /* std, store double word */ if (rd & 1) @@ -5400,7 +5402,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) t64 =3D tcg_temp_new_i64(); tcg_gen_concat_tl_i64(t64, lo, cpu_val); tcg_gen_qemu_st_i64(t64, cpu_addr, - dc->mem_idx, MO_TEUQ); + dc->mem_idx, MO_TEUQ | MO_ALIG= N); } break; #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) @@ -5424,7 +5426,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) case 0x0e: /* V9 stx */ gen_address_mask(dc, cpu_addr); tcg_gen_qemu_st_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUQ); + dc->mem_idx, MO_TEUQ | MO_ALIGN); break; case 0x1e: /* V9 stxa */ gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ); @@ -5442,7 +5444,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) gen_address_mask(dc, cpu_addr); cpu_src1_32 =3D gen_load_fpr_F(dc, rd); tcg_gen_qemu_st_i32(cpu_src1_32, cpu_addr, - dc->mem_idx, MO_TEUL); + dc->mem_idx, MO_TEUL | MO_ALIGN); break; case 0x25: /* stfsr, V9 stxfsr */ { @@ -5450,12 +5452,12 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) gen_address_mask(dc, cpu_addr); if (rd =3D=3D 1) { tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr, - dc->mem_idx, MO_TEUQ); + dc->mem_idx, MO_TEUQ | MO_A= LIGN); break; } #endif tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr, - dc->mem_idx, MO_TEUL); + dc->mem_idx, MO_TEUL | MO_ALIGN= ); } break; case 0x26: --=20 2.34.1 From nobody Sat May 18 12:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.24.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:24:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321898; x=1685913898; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6kaCkf+tWgS3OG0dqcISJnpxG2CWngLV2cNCMJMkKlk=; b=N5mwmqihnMzDQOu0vsvkhdsS4l8oNxUmVigBAtMArDCbfhfSX626a+7Bbjf3GGgGNx 6D+rdDT+V+7BVJfnfCZRPOrKoew9ew+DqeFkMNyIEJToRoAlrNrB7RgwLKR4KF6/FVX0 ydwdwwT4so5UzDIRnSM066O+gUkdpbjW+dD2sOg0pPBA1JrJ7CkmiaTNHUVq6x1XHgMV lIgRx5+gWOfcvbD2IN0ryH8LZIM2gZ/2OBafasJmpgku7pcMqNSX/Aa9BhJWT0FrAVh7 FRE6fG4OUrU9H1kpWlaCAPM+o2dRsoxETzXo6RrJ6ra9W6Dpd6d0aa1Kjnnr7U5Oeom9 3Lig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321898; x=1685913898; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6kaCkf+tWgS3OG0dqcISJnpxG2CWngLV2cNCMJMkKlk=; b=A65WwW0/atVIQ0UFA8K4l0hwwlXliJX4A7wYSd19ICDNOiyx+kswzp4QvO4Q4qCVpg mqlRbjnz8Y8e0kl0B3fv5LVictgPTOfisNzU8xJJdTFnEOPVQuvP/7A0voEoqfkRXr51 b8k4deoG4qkGLBa0vML7p7o9iPAONFbX5OVfsrtH3LI7H04ZPnwOQQDBAiiOsfSfv6h6 6NqDGHDfLIlUIljyvZDe4CQaN3v7ZrZ9tyKqaK6WFlqrqw3XbArNGql4Durvxa2Dd75J Hq2K27GtPwXXbpJptIM04a5PW07Vm1kmz/CXeNHl1oFki0LF+J9tNHcUdmKUPbKKDEve EHcQ== X-Gm-Message-State: AC+VfDxOMzTqceCArrYycSubX9X2r00xETWRiCcjzW3k3+BexERFR28W 6ID7Fiz3A6JXYwVK99MR+sb8Rh2XI/H/llJ9Qa9ZvA== X-Google-Smtp-Source: ACHHUZ6ggrtqpiftcYnt4QOu1yW3D7LlxcPT1PdD8WrNcARsQzJvjMuLPB7JXJN++z+cT62y32oJhA== X-Received: by 2002:adf:de8d:0:b0:306:2e04:5925 with SMTP id w13-20020adfde8d000000b003062e045925mr2296422wrl.17.1683321898432; Fri, 05 May 2023 14:24:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 17/42] target/sparc: Use cpu_ld*_code_mmu Date: Fri, 5 May 2023 22:24:22 +0100 Message-Id: <20230505212447.374546-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683321990367100001 Content-Type: text/plain; charset="utf-8" This passes on the memop as given as argument to helper_ld_asi to the ultimate load primitive. Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index a53580d9e4..7972d56a72 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -593,6 +593,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong= addr, #if defined(DEBUG_MXCC) || defined(DEBUG_ASI) uint32_t last_addr =3D addr; #endif + MemOpIdx oi; =20 do_check_align(env, addr, size - 1, GETPC()); switch (asi) { @@ -692,19 +693,20 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulo= ng addr, case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */ break; case ASI_KERNELTXT: /* Supervisor code access */ + oi =3D make_memop_idx(memop, cpu_mmu_index(env, true)); switch (size) { case 1: - ret =3D cpu_ldub_code(env, addr); + ret =3D cpu_ldb_code_mmu(env, addr, oi, GETPC()); break; case 2: - ret =3D cpu_lduw_code(env, addr); + ret =3D cpu_ldw_code_mmu(env, addr, oi, GETPC()); break; default: case 4: - ret =3D cpu_ldl_code(env, addr); + ret =3D cpu_ldl_code_mmu(env, addr, oi, GETPC()); break; case 8: - ret =3D cpu_ldq_code(env, addr); + ret =3D cpu_ldq_code_mmu(env, addr, oi, GETPC()); break; } break; --=20 2.34.1 From nobody Sat May 18 12:05:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683321973; cv=none; d=zohomail.com; s=zohoarc; b=kkECynt0zasWAsfiCon6tnllojTBFF2VAAmUaVXV0GqvBEWknIf1/KzXHzoFKkGdnvZoCFl21luPZUEd976pMTrekcQKtlWF2qAaMtBokvUwOxSqnT/OKQyTVl7pno9CLRWHdxZnP6yHTGYQcv/9h0QV61FzE5p2hPd2z6sH870= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683321973; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pbAgzG/DXQiDwooC2dp0ZtQphp0ZPty+CqajwWoQmzw=; b=C4ATeVcMQa7klKQ0ZIFoLLqCS7x7Gv9iosiYCyiciUXoxhyWlRi/5tgKJT19A8jFfd5y3PEwrXPkctGIUn3nVc3S91/gm/Ur2UcDrOUHyTQ1/8nBO0tUHY3M3eDK/MbHdtiuKnfgTOzGBLukR3BSaXp6MjiPeVXeMQ5IhHIyQQo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683321973145764.9775164852794; Fri, 5 May 2023 14:26:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vL-0000iS-R6; Fri, 05 May 2023 17:25:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vG-0000fz-VR for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:02 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2vE-0004Ru-Sl for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:02 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-3f19a80a330so15628955e9.2 for ; Fri, 05 May 2023 14:24:59 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.24.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:24:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321899; x=1685913899; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pbAgzG/DXQiDwooC2dp0ZtQphp0ZPty+CqajwWoQmzw=; b=dUn3JjmOo22s80wkeP+kv/sE+yQNTnsxCQNFMyuJ2/ZVQpvCFehwXdCeoqVQBNQgb1 Qz1PsFA6ExMvZu3jglPLAoEb/kNjR8QHzvhm6rtseRBwOtkbY8kU5v2RKzHro8fpor2C Hp4ViCMtLbcrn2Ubou57YYW+wILs9OSfXiHU55fi6v0cD1LptI9C/YFAmWzd882jKwXg orY4PuBXB1+89XGvaSPIZVvhSFBznkEOkqXAm8fjR11QEuG5bTqxv9EmJTqxcZpUbW5m pYB27H03DVf74SM/UfWdf8L7yQ7EMCuDJqjutadSrjyRlosoLVi+qucQupP+TbqXkJ7t qagQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321899; x=1685913899; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SPACE_RATIO=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683321974432100005 Content-Type: text/plain; charset="utf-8" Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- configs/targets/sparc-linux-user.mak | 1 - configs/targets/sparc-softmmu.mak | 1 - configs/targets/sparc32plus-linux-user.mak | 1 - configs/targets/sparc64-linux-user.mak | 1 - configs/targets/sparc64-softmmu.mak | 1 - 5 files changed, 5 deletions(-) diff --git a/configs/targets/sparc-linux-user.mak b/configs/targets/sparc-l= inux-user.mak index 00e7bc1f07..abcfb8fc62 100644 --- a/configs/targets/sparc-linux-user.mak +++ b/configs/targets/sparc-linux-user.mak @@ -1,5 +1,4 @@ TARGET_ARCH=3Dsparc TARGET_SYSTBL_ABI=3Dcommon,32 TARGET_SYSTBL=3Dsyscall.tbl -TARGET_ALIGNED_ONLY=3Dy TARGET_BIG_ENDIAN=3Dy diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-soft= mmu.mak index a849190f01..454eb35499 100644 --- a/configs/targets/sparc-softmmu.mak +++ b/configs/targets/sparc-softmmu.mak @@ -1,3 +1,2 @@ TARGET_ARCH=3Dsparc -TARGET_ALIGNED_ONLY=3Dy TARGET_BIG_ENDIAN=3Dy diff --git a/configs/targets/sparc32plus-linux-user.mak b/configs/targets/s= parc32plus-linux-user.mak index a65c0951a1..6cc8fa516b 100644 --- a/configs/targets/sparc32plus-linux-user.mak +++ b/configs/targets/sparc32plus-linux-user.mak @@ -4,5 +4,4 @@ TARGET_BASE_ARCH=3Dsparc TARGET_ABI_DIR=3Dsparc TARGET_SYSTBL_ABI=3Dcommon,32 TARGET_SYSTBL=3Dsyscall.tbl -TARGET_ALIGNED_ONLY=3Dy TARGET_BIG_ENDIAN=3Dy diff --git a/configs/targets/sparc64-linux-user.mak b/configs/targets/sparc= 64-linux-user.mak index 20fcb93fa4..52f05ec000 100644 --- a/configs/targets/sparc64-linux-user.mak +++ b/configs/targets/sparc64-linux-user.mak @@ -3,5 +3,4 @@ TARGET_BASE_ARCH=3Dsparc TARGET_ABI_DIR=3Dsparc TARGET_SYSTBL_ABI=3Dcommon,64 TARGET_SYSTBL=3Dsyscall.tbl -TARGET_ALIGNED_ONLY=3Dy TARGET_BIG_ENDIAN=3Dy diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-= softmmu.mak index c626ac3eae..d3f8a3b710 100644 --- a/configs/targets/sparc64-softmmu.mak +++ b/configs/targets/sparc64-softmmu.mak @@ -1,4 +1,3 @@ TARGET_ARCH=3Dsparc64 TARGET_BASE_ARCH=3Dsparc -TARGET_ALIGNED_ONLY=3Dy TARGET_BIG_ENDIAN=3Dy --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.24.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:24:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321899; x=1685913899; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zSj12nfEvRnhBgqE2PJi/TGBu9PPVa2e0rcdWimFZ2s=; b=NocjMrDeevHobWcnJciOuxbGGRLbVPsaFSe+GQasftaj9W56++z6jUygBagX88LQ1s 3I2r+q2IzCYwfYviLcbnP13GxHBOyCBXJOXqaXUDMd6PzxGR6FEEIzCN1pjy8dSAZ++u ty4H9j8Sp59wDD/1dHpUyRguAcUhC5F67ClDEyoRE5OGM/BSMBjR79v9AGiNBU6gnh+K iXTlselrQYZK2uJkKRFAcex8aDR/anoiifLYeHGfJQsWMUMWq/Y7qpKehhn9D8IcdopN LdpswPTomTO5ET6FkpNseQLh+7Zfph1hclxYlJlpJ8m8bx92gqZoQ2Pt/xyc3XNw/fQs oOPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321899; x=1685913899; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zSj12nfEvRnhBgqE2PJi/TGBu9PPVa2e0rcdWimFZ2s=; b=ZEWnZKtko8yBe8AVRRMdd1mSHn6iP+d1OTCGVqsz+nCwekAfxvLniHQhuwjYodg5wA hBX/bxoMVcEb+eB9H1PnPiygR2HKi4VVnIz9ILecxs8j4y3jBbSurff8N/6K2oYsI9dr yL9WJFc6S1cRXfrNnqNZ1M0PJceRfyp3yPFeJT8Eak1CEts1WbyeFRbgdTlGSXlALgoR n5Q88YQodbTuDWP7Idn29cV2D1usw2ukLUYmVGTmXBi7xBH/K+1BJR6lFsTfqK6T0O+M NsGEdAAO9s+2o67Oyd/EVJTAOYoElgUT4xm/Y8ifdi0uHt6ghd7s9BdQ2AZDHOyYYkZQ FiUA== X-Gm-Message-State: AC+VfDxnpRl4ImprSHc5P62gbA79d+OBbu402187wjJllsM6xmmv0Tha 4av9wY7jO9mKbrATsSd8OvJuRQuENmlVYyhkJqs9nw== X-Google-Smtp-Source: ACHHUZ7AhKzPt09GV9sx9nzK6L7ZwewOfrUH6n24qTE1lJmwVTBwOod82jV2D90xMAFVErtmt9wahQ== X-Received: by 2002:a5d:6941:0:b0:306:31d4:43 with SMTP id r1-20020a5d6941000000b0030631d40043mr2288671wrw.63.1683321899469; Fri, 05 May 2023 14:24:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 19/42] tcg/i386: Rationalize args to tcg_out_qemu_{ld,st} Date: Fri, 5 May 2023 22:24:24 +0100 Message-Id: <20230505212447.374546-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322190881100001 Interpret the variable argument placement in the caller. Pass data_type instead of is64 -- there are several places where we already convert back from bool to type. Clean things up by using type throughout. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 111 +++++++++++++++++--------------------- 1 file changed, 50 insertions(+), 61 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index caf91a3151..cfa2349b03 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1884,8 +1884,8 @@ static inline void tcg_out_tlb_load(TCGContext *s, TC= GReg addrlo, TCGReg addrhi, * Record the context of a call to the out of line helper code for the slo= w path * for a load or store, so that we can later generate the correct helper c= ode */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64, - MemOpIdx oi, +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, + TCGType type, MemOpIdx oi, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, tcg_insn_unit *raddr, @@ -1895,7 +1895,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, bool is_64, =20 label->is_ld =3D is_ld; label->oi =3D oi; - label->type =3D is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32; + label->type =3D type; label->datalo_reg =3D datalo; label->datahi_reg =3D datahi; label->addrlo_reg =3D addrlo; @@ -2152,11 +2152,10 @@ static inline int setup_guest_base_seg(void) =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, TCGReg base, int index, intptr_t ofs, - int seg, bool is64, MemOp memop) + int seg, TCGType type, MemOp memop) { - TCGType type =3D is64 ? TCG_TYPE_I64 : TCG_TYPE_I32; bool use_movbe =3D false; - int rexw =3D is64 * P_REXW; + int rexw =3D (type =3D=3D TCG_TYPE_I32 ? 0 : P_REXW); int movop =3D OPC_MOVL_GvEv; =20 /* Do big-endian loads with movbe. */ @@ -2246,50 +2245,34 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, } } =20 -/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and - EAX. It will be useful once fixed registers globals are less - common. */ -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) +static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, TCGType data_type) { - TCGReg datalo, datahi, addrlo; - TCGReg addrhi __attribute__((unused)); - MemOpIdx oi; - MemOp opc; + MemOp opc =3D get_memop(oi); + #if defined(CONFIG_SOFTMMU) - int mem_index; tcg_insn_unit *label_ptr[2]; -#else - unsigned a_bits; -#endif =20 - datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); - -#if defined(CONFIG_SOFTMMU) - mem_index =3D get_mmuidx(oi); - - tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, + tcg_out_tlb_load(s, addrlo, addrhi, get_mmuidx(oi), opc, label_ptr, offsetof(CPUTLBEntry, addr_read)); =20 /* TLB Hit. */ - tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, is64, = opc); + tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, + -1, 0, 0, data_type, opc); =20 /* Record the current context of a load into ldst label */ - add_qemu_ldst_label(s, true, is64, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #else - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } =20 tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index, x86_guest_base_offset, x86_guest_base_seg, - is64, opc); + data_type, opc); #endif } =20 @@ -2345,40 +2328,26 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, } } =20 -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) +static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, TCGType data_type) { - TCGReg datalo, datahi, addrlo; - TCGReg addrhi __attribute__((unused)); - MemOpIdx oi; - MemOp opc; + MemOp opc =3D get_memop(oi); + #if defined(CONFIG_SOFTMMU) - int mem_index; tcg_insn_unit *label_ptr[2]; -#else - unsigned a_bits; -#endif =20 - datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); - -#if defined(CONFIG_SOFTMMU) - mem_index =3D get_mmuidx(oi); - - tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, + tcg_out_tlb_load(s, addrlo, addrhi, get_mmuidx(oi), opc, label_ptr, offsetof(CPUTLBEntry, addr_write)); =20 /* TLB Hit. */ tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc); =20 /* Record the current context of a store into ldst label */ - add_qemu_ldst_label(s, false, is64, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #else - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); } @@ -2673,17 +2642,37 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, 0); + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I32); + } else { + tcg_out_qemu_ld(s, a0, -1, a1, a2, args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, 1); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I64); + } else if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_ld(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); + } break; case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st8_i32: - tcg_out_qemu_st(s, args, 0); + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I32); + } else { + tcg_out_qemu_st(s, a0, -1, a1, a2, args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, 1); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I64); + } else if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_st(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); + } break; =20 OP_32_64(mulu2): --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322191; cv=none; d=zohomail.com; s=zohoarc; b=FKFM6Vq1NboaUkryo2MeisEUNXcjRhb5hRWxf7dF6u95JREK7pTw8yEaJ246DRzz6qZ34wz6a+OrtDEF6GUToXPTgLVO+MY7Pypyk6G4LQtynFAN2jjKITmdXvm7LPXtsPFI0GdhWLpqyT46vCc49IuxmehgpRMUh+Kqo5GYee8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683322191; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Op61LyFiNoJTk9LIzK5doaDEyxOgewGDHJjDkfUTrQ4=; b=nEpW/ocMtj8RAePpZmMuAZ8qz5+R5kKeqFwbdsI4UIHJPt3Kk9P18C4Ya5olZzh0kE8UaTcP0mYbj/cPdMNepzN7iNXxnHOnt/R34PP0G5rJh55be+kFfIfAXTXIePpCeiBY+5SwqYhrfmp4AT8JAHBqvPoWR4/HzIdUXVw7gUo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16833221910841015.9406147262647; Fri, 5 May 2023 14:29:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vW-0000pf-Py; Fri, 05 May 2023 17:25:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vU-0000nS-F1 for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:16 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2vF-0004ST-5T for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:16 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-307664010fdso1855863f8f.0 for ; Fri, 05 May 2023 14:25:00 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.24.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:24:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321900; x=1685913900; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Op61LyFiNoJTk9LIzK5doaDEyxOgewGDHJjDkfUTrQ4=; b=XtIEOaEuhG17hyduWVNQq+sloifk1TKf/Sxnie+7YP0ip0KD80J/tIpvyGhNlS+Tro 6e2mYd4W+V/4q00CcIoxQij/lLnbVksbU0lE4BvvJ+QWX+gPBg+u+Prlt/THZbM+WQ2d lhDCGeIG8XkArvFs3rfGb1RehMy91L8rqcpHNT6fJ1merp5Ev/yc83NwYaSYKy3EvkRp m8hLt+yXvOgBo0SABNkEDpXphMIlCJAoMeThzi6YNp+g9bgHlsr+6GkssWOdhR5FyoRL NCpJkTK/iL8cPiwzdu5NnuideFZYVjIixl+grtkuOt/SBO3pmAkHXDn2nZdcQFvmXkCp FXrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321900; x=1685913900; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Op61LyFiNoJTk9LIzK5doaDEyxOgewGDHJjDkfUTrQ4=; b=UGW1mjlwL4rhItEnHDHyj+tdO8zYpsbASXlu22mRnjOkopPqiHdZOxrw2my9QIDUqq x2XTB9hXjBDuo9cFX1w3ZDAEl8mSbeEpXe8cnq21ovdlEqoSilJbKwsHotbCTK//xN9F 3QleaSExjgjf88UEI1L0xnz7EdcssBmEGVuG4X7QmR4ku5pUkl+uaUx0JzGUmesYlP1e 8GFDYhDjglz7EGIElhTw8gAxY+ay57jP8VobyGTQuQi2wrE1KPABhCm1fE2m0X0R3xjw N1UP67HhIZBvQG+vUTYfBUmA5gYuYVDToERdhwFqS99TNPk/kO3XONjk3AFdHFqB+kX1 HsHA== X-Gm-Message-State: AC+VfDx0FX1HnT1Qrpz9mRiBGQmo3fNHX7MACocunNGGnh1O1u7KREpg TND7Qq1lHUEfsk1sFkckBb7oOjEhBc3+S+2x9keK/Q== X-Google-Smtp-Source: ACHHUZ7GsyjKIF4rxOuy+Vvk4Qhl7Cabj26NLXoNwGG/pCRzvjDfm+rxc8J3iO8tyxFOjRfxIaHoyQ== X-Received: by 2002:adf:fb06:0:b0:307:7bca:2964 with SMTP id c6-20020adffb06000000b003077bca2964mr2180418wrr.14.1683321899915; Fri, 05 May 2023 14:24:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 20/42] tcg/i386: Generalize multi-part load overlap test Date: Fri, 5 May 2023 22:24:25 +0100 Message-Id: <20230505212447.374546-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322191381100003 Content-Type: text/plain; charset="utf-8" Test for both base and index; use datahi as a temporary, overwritten by the final load. Always perform the loads in ascending order, so that any (user-only) fault sees the correct address. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index cfa2349b03..173f3c3172 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2221,23 +2221,22 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, base, index, 0, ofs); + break; + } + if (use_movbe) { + TCGReg t =3D datalo; + datalo =3D datahi; + datahi =3D t; + } + if (base =3D=3D datalo || index =3D=3D datalo) { + tcg_out_modrm_sib_offset(s, OPC_LEA, datahi, base, index, 0, o= fs); + tcg_out_modrm_offset(s, movop + seg, datalo, datahi, 0); + tcg_out_modrm_offset(s, movop + seg, datahi, datahi, 4); } else { - if (use_movbe) { - TCGReg t =3D datalo; - datalo =3D datahi; - datahi =3D t; - } - if (base !=3D datalo) { - tcg_out_modrm_sib_offset(s, movop + seg, datalo, - base, index, 0, ofs); - tcg_out_modrm_sib_offset(s, movop + seg, datahi, - base, index, 0, ofs + 4); - } else { - tcg_out_modrm_sib_offset(s, movop + seg, datahi, - base, index, 0, ofs + 4); - tcg_out_modrm_sib_offset(s, movop + seg, datalo, - base, index, 0, ofs); - } + tcg_out_modrm_sib_offset(s, movop + seg, datalo, + base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, movop + seg, datahi, + base, index, 0, ofs + 4); } break; default: --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322190; cv=none; d=zohomail.com; s=zohoarc; b=g5jngW22XKjeDyjdzTlfm816RghS46xvTq0vlNuSnI77c31cqzC7OzTCDthHn1Pz8MamKAQvMrudNW2OPFcRd6VzKNzVRaQJ9dKziHv6CsMTp9PnU4ORfHjkP7RM4MjVEMI0NVcjCSqCXSqhlmqIgDSFMxdHPA+2ZCgBx6jvPyI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683322190; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/6oOL9Qxq+7huZ1LmoWKmGGF4tAmAVlunpyi8FXbSEY=; b=IvH/UwzT1D0gRbrzpe/IISdMFFH0ZV3bUDd5JMgHDb8asN3MTWfgeHAt5mC9yomKfZuduVFJiV5ReH6Fmp2KnTgJxHAL5m/RQ7il5y/REQMXCSTO/QoV59Kp0J8gxJ7WghoYnUTl8Psl79likfBkhTz589c5udxPV7g48Ao3RJA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683322190543993.2852173617376; Fri, 5 May 2023 14:29:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vR-0000k9-5R; Fri, 05 May 2023 17:25:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vK-0000hK-KU for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:06 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2vF-0004Qe-70 for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:06 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-304935cc79bso2125260f8f.2 for ; Fri, 05 May 2023 14:25:00 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321900; x=1685913900; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/6oOL9Qxq+7huZ1LmoWKmGGF4tAmAVlunpyi8FXbSEY=; b=k2KzRVnL5OQqcVF7KjwapyQNJhwud7N8EgbUa5YiLq4t7DXHaldGcQOfG+Gom7WDXm pzNsBXQaWHDJUGq+N2PtcGP1sdsMK3Vpr5I01AxxsSrhvAwr1wS8gY2AnfcQ2eNLHRec m4ZqIt0UW3BbotP2jqb00pptOSqbrMW6MqgoPDL6BPP8spacIg0EI1Hq5zhWSk03IOW2 bE/g1kaue7HHdNWRwDKcOkjmQoD5Cleu13vtkzerq8odF152lFiiD5eOuilL92rNpzQ3 DCIrd7zmdgA1FgaHVs1Rb8dAvTgY/Z/RxiaIh7fX7qFP/jPLi0K7pYuTLUs3Q0watgSt hppg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321900; x=1685913900; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/6oOL9Qxq+7huZ1LmoWKmGGF4tAmAVlunpyi8FXbSEY=; b=E4Y98NW/iJ5YcaEz2qS8svgUStcUHSE+k249OpMUvse78UpJFFYu/UXf1IIK9FJAD/ YSb3DeKQiaGCVYN6/4uW/3JyYyioZoy1xi2ZMzFbQot8OujmlgtY+DRPN0B65L6htPEE oizaEQIitmmSgnr6QyFQitBXEZfljLqYbuonyvncJMLjhPdDMgxrTS1VjIR44EoeFsoz brlmF6bUOIzh8JHxQPv0tkpvBsIg6jHtoxQ0qXAeCb6jtyUb+KZMT7csOXQJ8EHkzkI9 J6BdlHnw/lyv6toRxWw657I+VIpjkrstL3QxmmVC1HdEFO/xybAgqzp1d16jrxYle7qh fYng== X-Gm-Message-State: AC+VfDyaK5zLIPzUkUGNHH4P+7iWttVzn8CvG3K1ufPs5z0zojYY1rSX ZlRXbHSwKxezC2E1DLBnbo8JloTzVnrh+SWMRdeKSw== X-Google-Smtp-Source: ACHHUZ6uBXEj1qWH7QlGFJvVuc/itAh/8sQhABZAuvYjdfPUOKSbupVFHg9u/yZCY5F9WYskMte/xw== X-Received: by 2002:adf:fd06:0:b0:306:46c5:d41 with SMTP id e6-20020adffd06000000b0030646c50d41mr2674519wrr.8.1683321900415; Fri, 05 May 2023 14:25:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 21/42] tcg/i386: Introduce HostAddress Date: Fri, 5 May 2023 22:24:26 +0100 Message-Id: <20230505212447.374546-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322191825100009 Collect the 4 potential parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st}_direct to use it. Reorg guest_base handling to use it. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 165 +++++++++++++++++++++----------------- 1 file changed, 90 insertions(+), 75 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 173f3c3172..909eecd4a3 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1751,6 +1751,13 @@ static void tcg_out_nopn(TCGContext *s, int n) tcg_out8(s, 0x90); } =20 +typedef struct { + TCGReg base; + int index; + int ofs; + int seg; +} HostAddress; + #if defined(CONFIG_SOFTMMU) /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) @@ -2113,17 +2120,13 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) return tcg_out_fail_alignment(s, l); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 -# define x86_guest_base_seg 0 -# define x86_guest_base_index -1 -# define x86_guest_base_offset guest_base -#else -static int x86_guest_base_seg; -static int x86_guest_base_index =3D -1; -static int32_t x86_guest_base_offset; -# if defined(__x86_64__) && defined(__linux__) -# include -# include +static HostAddress x86_guest_base =3D { + .index =3D -1 +}; + +#if defined(__x86_64__) && defined(__linux__) +# include +# include int arch_prctl(int code, unsigned long addr); static inline int setup_guest_base_seg(void) { @@ -2132,8 +2135,9 @@ static inline int setup_guest_base_seg(void) } return 0; } -# elif defined (__FreeBSD__) || defined (__FreeBSD_kernel__) -# include +#elif defined(__x86_64__) && \ + (defined (__FreeBSD__) || defined (__FreeBSD_kernel__)) +# include static inline int setup_guest_base_seg(void) { if (sysarch(AMD64_SET_GSBASE, &guest_base) =3D=3D 0) { @@ -2141,18 +2145,16 @@ static inline int setup_guest_base_seg(void) } return 0; } -# else +#else static inline int setup_guest_base_seg(void) { return 0; } -# endif -#endif +#endif /* setup_guest_base_seg */ #endif /* SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, - TCGReg base, int index, intptr_t ofs, - int seg, TCGType type, MemOp memop) + HostAddress h, TCGType type, MemOp memo= p) { bool use_movbe =3D false; int rexw =3D (type =3D=3D TCG_TYPE_I32 ? 0 : P_REXW); @@ -2167,60 +2169,61 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, =20 switch (memop & MO_SSIZE) { case MO_UB: - tcg_out_modrm_sib_offset(s, OPC_MOVZBL + seg, datalo, - base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVZBL + h.seg, datalo, + h.base, h.index, 0, h.ofs); break; case MO_SB: - tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + seg, datalo, - base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + h.seg, datalo, + h.base, h.index, 0, h.ofs); break; case MO_UW: if (use_movbe) { /* There is no extending movbe; only low 16-bits are modified.= */ - if (datalo !=3D base && datalo !=3D index) { + if (datalo !=3D h.base && datalo !=3D h.index) { /* XOR breaks dependency chains. */ tgen_arithr(s, ARITH_XOR, datalo, datalo); - tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + se= g, - datalo, base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.= seg, + datalo, h.base, h.index, 0, h.ofs= ); } else { - tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + se= g, - datalo, base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.= seg, + datalo, h.base, h.index, 0, h.ofs= ); tcg_out_ext16u(s, datalo, datalo); } } else { - tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, - base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVZWL + h.seg, datalo, + h.base, h.index, 0, h.ofs); } break; case MO_SW: if (use_movbe) { - tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, - datalo, base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.seg, + datalo, h.base, h.index, 0, h.ofs); tcg_out_ext16s(s, type, datalo, datalo); } else { - tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + seg, - datalo, base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + h.seg, + datalo, h.base, h.index, 0, h.ofs); } break; case MO_UL: - tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, o= fs); + tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, + h.base, h.index, 0, h.ofs); break; #if TCG_TARGET_REG_BITS =3D=3D 64 case MO_SL: if (use_movbe) { - tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + seg, datalo, - base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + h.seg, datalo, + h.base, h.index, 0, h.ofs); tcg_out_ext32s(s, datalo, datalo); } else { - tcg_out_modrm_sib_offset(s, OPC_MOVSLQ + seg, datalo, - base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVSLQ + h.seg, datalo, + h.base, h.index, 0, h.ofs); } break; #endif case MO_UQ: if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, - base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, + h.base, h.index, 0, h.ofs); break; } if (use_movbe) { @@ -2228,15 +2231,16 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, datalo =3D datahi; datahi =3D t; } - if (base =3D=3D datalo || index =3D=3D datalo) { - tcg_out_modrm_sib_offset(s, OPC_LEA, datahi, base, index, 0, o= fs); - tcg_out_modrm_offset(s, movop + seg, datalo, datahi, 0); - tcg_out_modrm_offset(s, movop + seg, datahi, datahi, 4); + if (h.base =3D=3D datalo || h.index =3D=3D datalo) { + tcg_out_modrm_sib_offset(s, OPC_LEA, datahi, + h.base, h.index, 0, h.ofs); + tcg_out_modrm_offset(s, movop + h.seg, datalo, datahi, 0); + tcg_out_modrm_offset(s, movop + h.seg, datahi, datahi, 4); } else { - tcg_out_modrm_sib_offset(s, movop + seg, datalo, - base, index, 0, ofs); - tcg_out_modrm_sib_offset(s, movop + seg, datahi, - base, index, 0, ofs + 4); + tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, + h.base, h.index, 0, h.ofs); + tcg_out_modrm_sib_offset(s, movop + h.seg, datahi, + h.base, h.index, 0, h.ofs + 4); } break; default: @@ -2249,6 +2253,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= alo, TCGReg datahi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); + HostAddress h; =20 #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[2]; @@ -2257,8 +2262,11 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg da= talo, TCGReg datahi, label_ptr, offsetof(CPUTLBEntry, addr_read)); =20 /* TLB Hit. */ - tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, - -1, 0, 0, data_type, opc); + h.base =3D TCG_REG_L1; + h.index =3D -1; + h.ofs =3D 0; + h.seg =3D 0; + tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, opc); =20 /* Record the current context of a load into ldst label */ add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi, @@ -2269,15 +2277,14 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } =20 - tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index, - x86_guest_base_offset, x86_guest_base_seg, - data_type, opc); + h =3D x86_guest_base; + h.base =3D addrlo; + tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, opc); #endif } =20 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, - TCGReg base, int index, intptr_t ofs, - int seg, MemOp memop) + HostAddress h, MemOp memop) { bool use_movbe =3D false; int movop =3D OPC_MOVL_EvGv; @@ -2296,30 +2303,31 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, case MO_8: /* This is handled with constraints on INDEX_op_qemu_st8_i32. */ tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || datalo < 4); - tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg, - datalo, base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + h.seg, + datalo, h.base, h.index, 0, h.ofs); break; case MO_16: - tcg_out_modrm_sib_offset(s, movop + P_DATA16 + seg, datalo, - base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, movop + P_DATA16 + h.seg, datalo, + h.base, h.index, 0, h.ofs); break; case MO_32: - tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, o= fs); + tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, + h.base, h.index, 0, h.ofs); break; case MO_64: if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, - base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, + h.base, h.index, 0, h.ofs); } else { if (use_movbe) { TCGReg t =3D datalo; datalo =3D datahi; datahi =3D t; } - tcg_out_modrm_sib_offset(s, movop + seg, datalo, - base, index, 0, ofs); - tcg_out_modrm_sib_offset(s, movop + seg, datahi, - base, index, 0, ofs + 4); + tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, + h.base, h.index, 0, h.ofs); + tcg_out_modrm_sib_offset(s, movop + h.seg, datahi, + h.base, h.index, 0, h.ofs + 4); } break; default: @@ -2332,6 +2340,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= alo, TCGReg datahi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); + HostAddress h; =20 #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[2]; @@ -2340,7 +2349,11 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg da= talo, TCGReg datahi, label_ptr, offsetof(CPUTLBEntry, addr_write)); =20 /* TLB Hit. */ - tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc); + h.base =3D TCG_REG_L1; + h.index =3D -1; + h.ofs =3D 0; + h.seg =3D 0; + tcg_out_qemu_st_direct(s, datalo, datahi, h, opc); =20 /* Record the current context of a store into ldst label */ add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi, @@ -2351,8 +2364,10 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg da= talo, TCGReg datahi, tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); } =20 - tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, x86_guest_base_index, - x86_guest_base_offset, x86_guest_base_seg, opc); + h =3D x86_guest_base; + h.base =3D addrlo; + + tcg_out_qemu_st_direct(s, datalo, datahi, h, opc); #endif } =20 @@ -4058,18 +4073,18 @@ static void tcg_target_qemu_prologue(TCGContext *s) (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4 + stack_addend); #else -# if !defined(CONFIG_SOFTMMU) && TCG_TARGET_REG_BITS =3D=3D 64 +# if !defined(CONFIG_SOFTMMU) if (guest_base) { int seg =3D setup_guest_base_seg(); if (seg !=3D 0) { - x86_guest_base_seg =3D seg; + x86_guest_base.seg =3D seg; } else if (guest_base =3D=3D (int32_t)guest_base) { - x86_guest_base_offset =3D guest_base; + x86_guest_base.ofs =3D guest_base; } else { /* Choose R12 because, as a base, it requires a SIB byte. */ - x86_guest_base_index =3D TCG_REG_R12; - tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base_index, guest_base= ); - tcg_regset_set_reg(s->reserved_regs, x86_guest_base_index); + x86_guest_base.index =3D TCG_REG_R12; + tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base.index, guest_base= ); + tcg_regset_set_reg(s->reserved_regs, x86_guest_base.index); } } # endif --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322180; cv=none; d=zohomail.com; s=zohoarc; b=SHw1rSWj5pZvx4ScGx9c7yaEiMBJUQXikVvm0u+9W+8G18FUcaUoEsGvnw10aDyZXPr2V2TjoSFPQKFGVeSe6J1tIAwc1Fnp3JGkEQ7h6anh5uJVXnG3rRLqMrBDusY6KDzrAahYdaVOcnAMpjM2ibLpqfbpXvN9P8uwnHJjdkU= ARC-Message-Signature: i=1; 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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321901; x=1685913901; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x6nk5/t6hIQSKL184WGvYaEyCfzzvv964RsZWo7l2GI=; b=cGMRD4iy0O/rwkLcRaGC1EdhTJVNlb3mL/xtLENVwtwwo6b681rW7vSvrGiDanlV8k xdTjXphZPw+KM2O5JPTlx6UY49/SkO6HMVWDFWMs5pJFKn6GdvsVLv4ZFslCpPeEjYGT rWmZZ5Ocj372ocdiE2Oxwspi7UEBygyPP2rdvyo5d+pgizYwJScWQFM+wqXca8GirR31 Bl4qq46sS5BtS+TEw9au27nBDWKNmRmmU68ejsL3jXr/bk0EmcXPZh9huhuLuYALZQWn 69jTu1In5T5bJzQiADwvR8aaZNx+FAaYW8iPL4IrJqTFEUfhIu1infzVWHUoGnck2i8N UCXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321901; x=1685913901; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x6nk5/t6hIQSKL184WGvYaEyCfzzvv964RsZWo7l2GI=; b=iOwEPjOvpeUwspxM9tZ/nMT67dsFy4npyKN/doVOFzp9vq+2IzUwUA/PhXVqjsHlPY vXR28Jv+FP6lqde4m3TK10oGDNQq/c9zkrAQvD31vNnBmQJHIQ48ItfuJBJU/BMdqLBQ 752bw4Pp2yTMwniJuW0PGB8yXP3zjoJIWLp0RMmJyuwUtH1pcafd5VhgUxHy5fkzUjtt +vAX0dRSQ3VGe9p3wQwcXteiyKkaafM9o07wFcmMs4UyuP4X1kY51J30BQtBEDJDqkq1 uaoj6nipVqzSxZkBKtydnU7m1oqYS/Yo2oYirph+gHaY6SOwyHelkQtALKoZRZsX6jfn qlHw== X-Gm-Message-State: AC+VfDxcOyCp0PiHMcdNAYFaLU8BoVVNnQWdotZPJVwRYRfDAnB5M8Va TLdRR+nOBGAPVKUPAhxi7Ig/PSEJXozE1k1HuyfQpw== X-Google-Smtp-Source: ACHHUZ7/Ybqe3ajJ+ejzg7//uKwhHUWbIGSFCZAH4OeHxEPo6fBsoctENvFQvNSYUWeVTBpy08UGrQ== X-Received: by 2002:a5d:6711:0:b0:306:39f5:e1a8 with SMTP id o17-20020a5d6711000000b0030639f5e1a8mr2190075wru.14.1683321900979; Fri, 05 May 2023 14:25:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 22/42] tcg/i386: Drop r0+r1 local variables from tcg_out_tlb_load Date: Fri, 5 May 2023 22:24:27 +0100 Message-Id: <20230505212447.374546-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322181420100001 Use TCG_REG_L[01] constants directly. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 909eecd4a3..78160f453b 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1810,8 +1810,6 @@ static inline void tcg_out_tlb_load(TCGContext *s, TC= GReg addrlo, TCGReg addrhi, int mem_index, MemOp opc, tcg_insn_unit **label_ptr, int which) { - const TCGReg r0 =3D TCG_REG_L0; - const TCGReg r1 =3D TCG_REG_L1; TCGType ttype =3D TCG_TYPE_I32; TCGType tlbtype =3D TCG_TYPE_I32; int trexw =3D 0, hrexw =3D 0, tlbrexw =3D 0; @@ -1835,15 +1833,15 @@ static inline void tcg_out_tlb_load(TCGContext *s, = TCGReg addrlo, TCGReg addrhi, } } =20 - tcg_out_mov(s, tlbtype, r0, addrlo); - tcg_out_shifti(s, SHIFT_SHR + tlbrexw, r0, + tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo); + tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); =20 - tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0, + tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0, TLB_MASK_TABLE_OFS(mem_index) + offsetof(CPUTLBDescFast, mask)); =20 - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0, + tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0, TLB_MASK_TABLE_OFS(mem_index) + offsetof(CPUTLBDescFast, table)); =20 @@ -1851,19 +1849,21 @@ static inline void tcg_out_tlb_load(TCGContext *s, = TCGReg addrlo, TCGReg addrhi, copy the address and mask. For lesser alignments, check that we do= n't cross pages for the complete access. */ if (a_bits >=3D s_bits) { - tcg_out_mov(s, ttype, r1, addrlo); + tcg_out_mov(s, ttype, TCG_REG_L1, addrlo); } else { - tcg_out_modrm_offset(s, OPC_LEA + trexw, r1, addrlo, s_mask - a_ma= sk); + tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1, + addrlo, s_mask - a_mask); } tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; - tgen_arithi(s, ARITH_AND + trexw, r1, tlb_mask, 0); + tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0); =20 - /* cmp 0(r0), r1 */ - tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, r1, r0, which); + /* cmp 0(TCG_REG_L0), TCG_REG_L1 */ + tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, + TCG_REG_L1, TCG_REG_L0, which); =20 /* Prepare for both the fast path add of the tlb addend, and the slow path function argument setup. */ - tcg_out_mov(s, ttype, r1, addrlo); + tcg_out_mov(s, ttype, TCG_REG_L1, addrlo); =20 /* jne slow_path */ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); @@ -1871,8 +1871,8 @@ static inline void tcg_out_tlb_load(TCGContext *s, TC= GReg addrlo, TCGReg addrhi, s->code_ptr +=3D 4; =20 if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - /* cmp 4(r0), addrhi */ - tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, r0, which + 4); + /* cmp 4(TCG_REG_L0), addrhi */ + tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, TCG_REG_L0, which + = 4); =20 /* jne slow_path */ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); @@ -1882,8 +1882,8 @@ static inline void tcg_out_tlb_load(TCGContext *s, TC= GReg addrlo, TCGReg addrhi, =20 /* TLB Hit. */ =20 - /* add addend(r0), r1 */ - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0, + /* add addend(TCG_REG_L0), TCG_REG_L1 */ + tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L1, TCG_REG_L0, offsetof(CPUTLBEntry, addend)); } =20 --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322046; cv=none; d=zohomail.com; s=zohoarc; b=XIzaHIWII26cMV3NBp/uexK5rIIFLgpHXV51vKn9ho+P0iQclxXfWLAFgf+cnLfRkknRgt09+Lv0rnMs5SH5PBE5VF8T/hw6MEl+SaO1xux1k6YCNPIngGvS8Dkww147x+MR1CYA1qh9a+ouiMSDlCHGmKDBJs47/YeE62DPJRc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683322046; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=l0A/LgUi4z6B1lwW4uNcjXdWAYm4PmHLzeyxMeuQV08=; b=nJxnpOZIIBxg4tCRhMddN9g+GfdJqrBl3Siwh2hslE0HKyHSZnL9TIrrrOY2E+uH4HyIma2ReWzcRR9jch2tNOy/k4STJXlUh96myWy/u+VpoDexkeIDnVk1WUNigwbnjhSN9FM+yOjdtdaDk4aGrHd/uny6mpFdj9RggEahLyo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683322046321855.3013816920451; Fri, 5 May 2023 14:27:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2ve-0000sN-Fc; Fri, 05 May 2023 17:25:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vV-0000oZ-Ck for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:17 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2vH-0004TJ-LR for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:17 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-3f173af665fso15920855e9.3 for ; Fri, 05 May 2023 14:25:02 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321901; x=1685913901; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l0A/LgUi4z6B1lwW4uNcjXdWAYm4PmHLzeyxMeuQV08=; b=JVY0lvMpyVLRAVSp/Z6fB/aClgYH0Lg2BZ0yKWpmWY2KFECZ+d8KW//52TJJF6IEM7 G9r1gqBmo3ZUJSaSw8GvxZqVR1vq4SwZdK3CRrLGR3J6cX5KYRkhUUcOlfJLtgnfD3HP L2RyWkOa6AQGm/gEu0yWXpoVbYP3rVQMHiPy0beH1tz27vKVrCLVV0eQ7eYD/wdJUDlN MQap36yWYu7mKFTaY/pwhN/xWnPVbliEqLHh7mBDmV0V9/LbheAlVxYw3jNI5CeF2cz8 V2MLnmfTBQfJsYeQ4qutTPJdX39qdGj79m/fzFv53hm5Vhn6vJ6HAlZ1e22U4OAlVCeP O0nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321901; x=1685913901; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l0A/LgUi4z6B1lwW4uNcjXdWAYm4PmHLzeyxMeuQV08=; b=coZ/4Zde/K9f3RWjRjkOtOr3v9yQC3ZFJHi0XsH5fljPD2AfyGVpSHjcp4iQvinjuU KJ9r6aGbQDyFLOqy8USa65bBe47HleexnQK80gKMglNERbw2viIhzV8WnsfZQ5bEQJ1E onZa4s0pVB3e4mMwse/j/0isu+T01Vp2Z8q/ozbNhwpY4q8cvvhKN+JHllsSU/XoJFeY tOiBgaS3DCEbjqMdDO7+Ut2Y/7r9JkOB93tuWXyHCH3N2WEOxju0iSnth5WagWSQBt4T ufhk7eHoekPM2hg3o/mkwGqh+cDNeeAAH0+ti6Yy0CFIx0aXRLuBacPOUbsAMTff+gkt TgfA== X-Gm-Message-State: AC+VfDzj6s3oReW8MotdmoJQf9kgJME+/vOIKwiRxzQH1arSgT3IJfGb gimPQsPGEe01UTer42Cgb2yNZcxfiY2LNwXYN2cgcw== X-Google-Smtp-Source: ACHHUZ42PVh9BwlnZzYlSq+c6XqXaEd1FUqsyXiuCsVqBUOk5DwF3EWKuK27KrpiOmtecHTpQx6EmQ== X-Received: by 2002:a7b:cb57:0:b0:3f1:7a4a:7f9 with SMTP id v23-20020a7bcb57000000b003f17a4a07f9mr2094554wmj.7.1683321901521; Fri, 05 May 2023 14:25:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 23/42] tcg/i386: Introduce tcg_out_testi Date: Fri, 5 May 2023 22:24:28 +0100 Message-Id: <20230505212447.374546-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322046754100003 Split out a helper for choosing testb vs testl. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 78160f453b..aae698121a 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1751,6 +1751,23 @@ static void tcg_out_nopn(TCGContext *s, int n) tcg_out8(s, 0x90); } =20 +/* Test register R vs immediate bits I, setting Z flag for EQ/NE. */ +static void __attribute__((unused)) +tcg_out_testi(TCGContext *s, TCGReg r, uint32_t i) +{ + /* + * This is used for testing alignment, so we can usually use testb. + * For i686, we have to use testl for %esi/%edi. + */ + if (i <=3D 0xff && (TCG_TARGET_REG_BITS =3D=3D 64 || r < 4)) { + tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, r); + tcg_out8(s, i); + } else { + tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_TESTi, r); + tcg_out32(s, i); + } +} + typedef struct { TCGReg base; int index; @@ -2051,18 +2068,7 @@ static void tcg_out_test_alignment(TCGContext *s, bo= ol is_ld, TCGReg addrlo, unsigned a_mask =3D (1 << a_bits) - 1; TCGLabelQemuLdst *label; =20 - /* - * We are expecting a_bits to max out at 7, so we can usually use test= b. - * For i686, we have to use testl for %esi/%edi. - */ - if (a_mask <=3D 0xff && (TCG_TARGET_REG_BITS =3D=3D 64 || addrlo < 4))= { - tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, addrlo); - tcg_out8(s, a_mask); - } else { - tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_TESTi, addrlo); - tcg_out32(s, a_mask); - } - + tcg_out_testi(s, addrlo, a_mask); /* jne slow_path */ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); =20 --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322093; cv=none; d=zohomail.com; s=zohoarc; b=e0t/co71sZ9Ok301mRRJvY/DywVRzrCMw+ftzaPSNW2y8PeokveXg8Vkj6THKJMVUm0XenDyZzUYQpLHNaYmp27COIBc5obiSZdpHZzfjYAVSgHdKy7qJbIGt4MWjcuQB/lQEhnyJx5+Gjf3XffWOzH+ZVZF2M9kDhp0hF8gE48= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683322093; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8x8nNgwxVzWwlXkH7TC04g8D23cjiNxwy3VmZPjq5To=; b=D8HZ0BnrrIp1QU+5946YX5bnK4FEy66RQCH5YZqENinZYbPIL2AWWhgWfo0Ry/XuBi8aRwjL2q/sghW670k/aTopeJdTQyr7iCpO/1ftM0LysIyt6KTBMrZvZkeJYtAcPrGXU6WwvAz00ITXWMKjdGEkkHoHNcvLFnCE7X3DTvw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683322093524965.1398830122774; Fri, 5 May 2023 14:28:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vS-0000lX-5E; Fri, 05 May 2023 17:25:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vO-0000iv-Gj for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:11 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2vJ-0004TS-Ls for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:10 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-2fa0ce30ac2so2146411f8f.3 for ; Fri, 05 May 2023 14:25:04 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321902; x=1685913902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8x8nNgwxVzWwlXkH7TC04g8D23cjiNxwy3VmZPjq5To=; b=i4oYycOLf7R3lsNPmjV/umMKcr94LAJscgCpWuaDs5wOcAKx44G9dkptqjlHxcVvqM JahqY/jR1klgtFNQQUuATXf4iFKYVxIq9a3a/lXVdqyREHhXXidfllsXlTJTh9Z5A3t3 uBgOyU8jcv6GPQW5fUq1LAxpYQbZJS7MjjTcxIhHwqgvzS2jQuuZcFDw+wpAUD0x16pA qtxIYNucoQPHMhjtDCdY7g49hJlVRpkzxwg26C3DmNdzct6cIOcK8f/IfGJINCQwabf2 MrNIW+ionzgT/Gn/C9jzw+vLSX/XnZiOECTuYFEwnN7jpuo6Om3KU9lkdISLE8iF1YN3 JbGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321902; x=1685913902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8x8nNgwxVzWwlXkH7TC04g8D23cjiNxwy3VmZPjq5To=; b=X/IsduhdAuQnrhyKywFimREa8cTBGb/pGfucARCb8GtfrH8iX19nMBo+5SO1eVT3Iq xs5344Tghj2C6axXO+fJBUnvHWQ0Prg551DhZbhdORstnh+X2bcscditAiTkg3OVwa3x Zsu/Gz0SUrTnT1DxVVrXSOoevMnNX6v3sxVjQc1yhd1FuNfpLChnUJ2d0Jt45zQKGf1V 92GDICp+H0TPxJ1NmjuecatjCaY6i2Dbt89Nk1VpxSYAWCMNG806V26KOrt15+SQEhqG n5L+1x4W9RoEmxt5XOOm9JwkcZWbYawI/hmGIJna45bfsA9BI0WRgajDJMoHVQHiWGTy qY6A== X-Gm-Message-State: AC+VfDzfGq+QbYVHPY7i/jJQiTMItF0GHqwpmpld/V9zxkTnLEAGbEDG LbHlZ+O2IKfH1Fln47+KbuVkQUPllgLlP4VBw4WkNw== X-Google-Smtp-Source: ACHHUZ6auVliJVz2lQEwyUZN1kNC9y7z9q97HkQ942um5QVrF5sw1PA6uLf/yQxfc7rZsRqJYjQ8WQ== X-Received: by 2002:a5d:6dce:0:b0:306:db7b:bb2d with SMTP id d14-20020a5d6dce000000b00306db7bbb2dmr2165606wrz.38.1683321901977; Fri, 05 May 2023 14:25:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 24/42] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld,st} Date: Fri, 5 May 2023 22:24:29 +0100 Message-Id: <20230505212447.374546-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322093757100005 Rename the 'ext' parameter 'data_type' to make the use clearer; pass it to tcg_out_qemu_st as well to even out the interfaces. Rename the 'otype' local 'addr_type' to make the use clearer. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 36 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 4ec3cf3172..ecbf6564fc 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1851,22 +1851,21 @@ static void tcg_out_qemu_st_direct(TCGContext *s, M= emOp memop, } =20 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, - MemOpIdx oi, TCGType ext) + MemOpIdx oi, TCGType data_type) { MemOp memop =3D get_memop(oi); - const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; + TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; =20 /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); =20 #ifdef CONFIG_SOFTMMU - unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; =20 - tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1); - tcg_out_qemu_ld_direct(s, memop, ext, data_reg, - TCG_REG_X1, otype, addr_reg); - add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg, + tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 1); + tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, + TCG_REG_X1, addr_type, addr_reg); + add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ unsigned a_bits =3D get_alignment_bits(memop); @@ -1874,33 +1873,32 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, tcg_out_test_alignment(s, true, addr_reg, a_bits); } if (USE_GUEST_BASE) { - tcg_out_qemu_ld_direct(s, memop, ext, data_reg, - TCG_REG_GUEST_BASE, otype, addr_reg); + tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, + TCG_REG_GUEST_BASE, addr_type, addr_reg); } else { - tcg_out_qemu_ld_direct(s, memop, ext, data_reg, + tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, addr_reg, TCG_TYPE_I64, TCG_REG_XZR); } #endif /* CONFIG_SOFTMMU */ } =20 static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, - MemOpIdx oi) + MemOpIdx oi, TCGType data_type) { MemOp memop =3D get_memop(oi); - const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; + TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; =20 /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); =20 #ifdef CONFIG_SOFTMMU - unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; =20 - tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0); + tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 0); tcg_out_qemu_st_direct(s, memop, data_reg, - TCG_REG_X1, otype, addr_reg); - add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)=3D=3D MO_64, - data_reg, addr_reg, s->code_ptr, label_ptr); + TCG_REG_X1, addr_type, addr_reg); + add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, + s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ unsigned a_bits =3D get_alignment_bits(memop); if (a_bits) { @@ -1908,7 +1906,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= a_reg, TCGReg addr_reg, } if (USE_GUEST_BASE) { tcg_out_qemu_st_direct(s, memop, data_reg, - TCG_REG_GUEST_BASE, otype, addr_reg); + TCG_REG_GUEST_BASE, addr_type, addr_reg); } else { tcg_out_qemu_st_direct(s, memop, data_reg, addr_reg, TCG_TYPE_I64, TCG_REG_XZR); @@ -2249,7 +2247,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, REG0(0), a1, a2); + tcg_out_qemu_st(s, REG0(0), a1, a2, ext); break; =20 case INDEX_op_bswap64_i64: --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683321976; cv=none; d=zohomail.com; s=zohoarc; b=jYPhnyX17Nyh3NY7xb+9lXgf5qFbdrdu9GiVSa7MB7Utr5S4kXjcbHxFNZP/XnkzsXI8z9VHtUv5htxqAr8U2wgaJdnbiuBaKYXCHkwC8ADtKdE4pbf84ib0ZZAl9rMoSG1A9Slf237ZvmZjUP5URosYDMNE/zP5wKKuFmZLRDY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683321976; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1bbEpaIXXaTgQeWDYcOIlkZ67YetPKNrTK/y3Em/irY=; b=FSfTNFhHskI1azKzCKhDLMam/Wbno0Stgq1mAm/XeF1LkkpF75n8juy4gMG/HSQ1QOmEfgQZggPK5rGVRISx0CuvV72pDJZob+XthBrXJQ/UCiStAEWfIHJj5G9HMscw8zaaNh1+MaTDItmbNRxW0NYdab+t4Ds6pyo5ouin26c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683321976667321.25366488411123; Fri, 5 May 2023 14:26:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vS-0000lq-88; Fri, 05 May 2023 17:25:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vO-0000ix-TW for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:11 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2vK-0004VO-IS for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:10 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-3f192c23fffso15659655e9.3 for ; Fri, 05 May 2023 14:25:04 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321902; x=1685913902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1bbEpaIXXaTgQeWDYcOIlkZ67YetPKNrTK/y3Em/irY=; b=wbHIUEm89CNyzcB3l5mPbcVXeuPl9l2q6/P7EW+gXW0dT1W8qPA/ibQ2KSY8ytXaxC HEZip7nBE6vzmF1Wto33UtcCHjYO2DGGunm+YVQjXdowuqY4GOuCTX16cfqo4PlM/a6S WiayI6mVbM8ZdtQEzJvft2uJAdXyyGQbzZFlx4jT8vLUuwH3ePGM0Uzzh3H3eR3eLWuQ Taz87ViPx7mn85BviitQiSf2iGqj+9VntCxkVviNZW6ADFOKOrkqwsZXjNqmh0TEvxU2 QsUtsJFHP179m/VfXrhtHeF6MzB6dBIK31RqwtLGFj5G8QXzNxhR9E+t7+3A9Eyn3AGI lrFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321902; x=1685913902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1bbEpaIXXaTgQeWDYcOIlkZ67YetPKNrTK/y3Em/irY=; b=WicaaaLFJII/irJFvFUTjOfCHZhs/8hwJSPsU3G4CcJeD/dYfaLPb2cLQ/bUoxqiHS 4GyB110VdrGgTWHfTb4HiE1L7+hrbnt8orxJqcTlfxxCjPzFzIQQuvcsELbkJHSdpaQq 0FYcoCrzn/vi7fl1+JlKpng7qRz2A5/2y4NY1NMp1z8wI2zSFXnpCZ/rPC+3SmopO7S6 meXENkho/j1c0+NR+WazmSKKuLh5PXgEqlvr7udfTP6T+hUcYTFeTxJh2H3n6W0Bkgov yrXw4m4UxIcwk0sL+gDFUQ6u0km7HNJRWfqIKhHHsslmIJxsSqVDZX/OlI4I92VFUNn2 Nn3Q== X-Gm-Message-State: AC+VfDx5PCQg7af+ybHPXyKywaY6DUiqGzRz4n8wzxPiQmg1Q4I6QYbK jiD87+VfwOHiwywOI92RTH5CN8X2AW6wee4UxHtA5Q== X-Google-Smtp-Source: ACHHUZ6rWqjJWKy0k8Jc2aeFy4GV+BPbIsPLmqG6LVmzQRkHDnLFdaAD25xHVsHNhJRtw4WaE5UALQ== X-Received: by 2002:a1c:7408:0:b0:3f3:2ba9:94d1 with SMTP id p8-20020a1c7408000000b003f32ba994d1mr1975102wmc.20.1683321902562; Fri, 05 May 2023 14:25:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 25/42] tcg/aarch64: Introduce HostAddress Date: Fri, 5 May 2023 22:24:30 +0100 Message-Id: <20230505212447.374546-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683321977568100013 Collect the 3 potential parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st}_direct to use it. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 86 +++++++++++++++++++++++++----------- 1 file changed, 59 insertions(+), 27 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index ecbf6564fc..d8d464e4a0 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1587,6 +1587,12 @@ static void tcg_out_adr(TCGContext *s, TCGReg rd, co= nst void *target) tcg_out_insn(s, 3406, ADR, rd, offset); } =20 +typedef struct { + TCGReg base; + TCGReg index; + TCGType index_ext; +} HostAddress; + #ifdef CONFIG_SOFTMMU /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * MemOpIdx oi, uintptr_t ra) @@ -1796,32 +1802,31 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) #endif /* CONFIG_SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext, - TCGReg data_r, TCGReg addr_r, - TCGType otype, TCGReg off_r) + TCGReg data_r, HostAddress h) { switch (memop & MO_SSIZE) { case MO_UB: - tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRB, data_r, h.base, h.index_ext, h.index= ); break; case MO_SB: tcg_out_ldst_r(s, ext ? I3312_LDRSBX : I3312_LDRSBW, - data_r, addr_r, otype, off_r); + data_r, h.base, h.index_ext, h.index); break; case MO_UW: - tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRH, data_r, h.base, h.index_ext, h.index= ); break; case MO_SW: tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW), - data_r, addr_r, otype, off_r); + data_r, h.base, h.index_ext, h.index); break; case MO_UL: - tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRW, data_r, h.base, h.index_ext, h.index= ); break; case MO_SL: - tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRSWX, data_r, h.base, h.index_ext, h.ind= ex); break; case MO_UQ: - tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRX, data_r, h.base, h.index_ext, h.index= ); break; default: g_assert_not_reached(); @@ -1829,21 +1834,20 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, M= emOp memop, TCGType ext, } =20 static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop, - TCGReg data_r, TCGReg addr_r, - TCGType otype, TCGReg off_r) + TCGReg data_r, HostAddress h) { switch (memop & MO_SIZE) { case MO_8: - tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_STRB, data_r, h.base, h.index_ext, h.index= ); break; case MO_16: - tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_STRH, data_r, h.base, h.index_ext, h.index= ); break; case MO_32: - tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_STRW, data_r, h.base, h.index_ext, h.index= ); break; case MO_64: - tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_STRX, data_r, h.base, h.index_ext, h.index= ); break; default: g_assert_not_reached(); @@ -1855,6 +1859,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a_reg, TCGReg addr_reg, { MemOp memop =3D get_memop(oi); TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; + HostAddress h; =20 /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); @@ -1863,8 +1868,14 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg da= ta_reg, TCGReg addr_reg, tcg_insn_unit *label_ptr; =20 tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 1); - tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, - TCG_REG_X1, addr_type, addr_reg); + + h =3D (HostAddress){ + .base =3D TCG_REG_X1, + .index =3D addr_reg, + .index_ext =3D addr_type + }; + tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, h); + add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ @@ -1873,12 +1884,19 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, tcg_out_test_alignment(s, true, addr_reg, a_bits); } if (USE_GUEST_BASE) { - tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, - TCG_REG_GUEST_BASE, addr_type, addr_reg); + h =3D (HostAddress){ + .base =3D TCG_REG_GUEST_BASE, + .index =3D addr_reg, + .index_ext =3D addr_type + }; } else { - tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, - addr_reg, TCG_TYPE_I64, TCG_REG_XZR); + h =3D (HostAddress){ + .base =3D addr_reg, + .index =3D TCG_REG_XZR, + .index_ext =3D TCG_TYPE_I64 + }; } + tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, h); #endif /* CONFIG_SOFTMMU */ } =20 @@ -1887,6 +1905,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= a_reg, TCGReg addr_reg, { MemOp memop =3D get_memop(oi); TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; + HostAddress h; =20 /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); @@ -1895,8 +1914,14 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg da= ta_reg, TCGReg addr_reg, tcg_insn_unit *label_ptr; =20 tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 0); - tcg_out_qemu_st_direct(s, memop, data_reg, - TCG_REG_X1, addr_type, addr_reg); + + h =3D (HostAddress){ + .base =3D TCG_REG_X1, + .index =3D addr_reg, + .index_ext =3D addr_type + }; + tcg_out_qemu_st_direct(s, memop, data_reg, h); + add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ @@ -1905,12 +1930,19 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, tcg_out_test_alignment(s, false, addr_reg, a_bits); } if (USE_GUEST_BASE) { - tcg_out_qemu_st_direct(s, memop, data_reg, - TCG_REG_GUEST_BASE, addr_type, addr_reg); + h =3D (HostAddress){ + .base =3D TCG_REG_GUEST_BASE, + .index =3D addr_reg, + .index_ext =3D addr_type + }; } else { - tcg_out_qemu_st_direct(s, memop, data_reg, - addr_reg, TCG_TYPE_I64, TCG_REG_XZR); + h =3D (HostAddress){ + .base =3D addr_reg, + .index =3D TCG_REG_XZR, + .index_ext =3D TCG_TYPE_I64 + }; } + tcg_out_qemu_st_direct(s, memop, data_reg, h); #endif /* CONFIG_SOFTMMU */ } =20 --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322020; cv=none; d=zohomail.com; s=zohoarc; b=HWZGdgLZ+xXkndcgxfjV0FXl429oru75Cp510VBvcoNMNE3ViAg1S7WVBD/L7g1jOhw03aUyFzohiXUft8MW+7t0QXxV5LqZ2VZ6ArOWEALpQdQ7n1TCL9DszW5q9TAYKa98C2FB2736eE3k6UmHsMNaNwC2CUho1vWXyFpJWKA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683322020; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/LNx4AQ8LEDs2bqV5zvn6xWFsTqqlF00MmHmvqgX6b8=; b=VHTd/MWeAqlPq9xVEprZKjEcD1qtvYG1LUvtJAmk4hAzVRvpy9q4yZD19bWj3m318kIKR0HZ7jSbmdoXoLsz6xGaIvQZb47q+5CJwSl1uu3kMuEzvDzESGT7i638QpMv4rCBOkR1uYfYpp41HogU0GuM1jpP55tfbYD4Sm9USok= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16833220202125.729776363261863; Fri, 5 May 2023 14:27:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vS-0000m9-Sj; Fri, 05 May 2023 17:25:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vN-0000iq-H9 for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:11 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2vJ-0004ZQ-B0 for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:09 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-3f1950f5628so23133275e9.3 for ; Fri, 05 May 2023 14:25:03 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321903; x=1685913903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/LNx4AQ8LEDs2bqV5zvn6xWFsTqqlF00MmHmvqgX6b8=; b=bO5309AlG6qM7HIvTzwKgZzR+vqsFbNgoYSHRjgCv84HjB6Fv7P/H17LNOBshUocfp N4dE9sPztx87MWgh2ML2X+j35nJjD74IVdHy2d6DIVt9v8pGxaEOBp8dw3Q+O+X28H3w hR4CFBSvIUldeQeZssDSG5R7Du/5Xwi2J3IbrrsJFZtm7AJVIg8PATF2A5Wi42B7UMzE JJkccV2ASr6NKG0mmrATbUjANuW19yM4FC+8m0mPLX3MvNPenI6SXINesqIL43qi8Lau TK2VcFqJ2qzbS6vMoUORm3mlZgzBYS9pl1BiIygbPaeApZ+7ZJkKRSBrOWyxDKpENzZl Mwqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321903; x=1685913903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/LNx4AQ8LEDs2bqV5zvn6xWFsTqqlF00MmHmvqgX6b8=; b=bz4NK7xKLfgBKevpsAYtWaTCrUO4tKL+l1dosQ+y4itoClKaiOcaUR60gM0SYMrIv5 hION2ZLXQVp+RqjOXvG+aCyREArGCSdiqLLcbiUhjIhCAuQoR2rF2YgoQsxlCQsqfRyW HCDrUdnV4Q+UpVxof3t3sA3fTgV/Ta+d9fJNXixtsgEfEIfJ/FiClLDxKcrEpdgBlLQj c76Uv13inRxqIzZ71vXwcCRv85BKv1kzhdNkjhJj4SAYymTZwIRw+JyStDz3+4kRuQ/6 1QVqUOBI7wdiR+XfkJP6duDqssI0FUQ070cX29PrvnkpIf4bk8oCL7RvNPMmw2NExsFn boqw== X-Gm-Message-State: AC+VfDxuLZb6QOtaBEKuRwHELfvTBcoztqcHntcJ3N446P1LL2vgqzx/ vjpmPFiNWQQGEy6dFsIhhcQvIpATZ0PZs0YmrEjupg== X-Google-Smtp-Source: ACHHUZ56T/3D+ifZCU07fWYGdDlWFe+0HQlY8QMdudJtbW3DGg8hgG/D6RJpM7165gC4rJtKZN4BRA== X-Received: by 2002:a1c:4b19:0:b0:3f1:78d0:fc4e with SMTP id y25-20020a1c4b19000000b003f178d0fc4emr2111817wma.32.1683321903079; Fri, 05 May 2023 14:25:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 26/42] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st} Date: Fri, 5 May 2023 22:24:31 +0100 Message-Id: <20230505212447.374546-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322021807100003 Interpret the variable argument placement in the caller. Pass data_type instead of is_64. We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 113 +++++++++++++++++++-------------------- 1 file changed, 56 insertions(+), 57 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 83c818a58b..6ce52b9612 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1526,15 +1526,18 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, /* Record the context of a call to the out of line helper code for the slow path for a load or store, so that we can later generate the correct helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, - TCGReg datalo, TCGReg datahi, TCGReg addrl= o, - TCGReg addrhi, tcg_insn_unit *raddr, +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, + MemOpIdx oi, TCGType type, + TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + tcg_insn_unit *raddr, tcg_insn_unit *label_ptr) { TCGLabelQemuLdst *label =3D new_ldst_label(s); =20 label->is_ld =3D is_ld; label->oi =3D oi; + label->type =3D type; label->datalo_reg =3D datalo; label->datahi_reg =3D datahi; label->addrlo_reg =3D addrlo; @@ -1796,41 +1799,28 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, M= emOp opc, TCGReg datalo, } #endif =20 -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) +static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, TCGType data_type) { - TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); - MemOpIdx oi; - MemOp opc; -#ifdef CONFIG_SOFTMMU - int mem_index; - TCGReg addend; - tcg_insn_unit *label_ptr; -#else - unsigned a_bits; -#endif - - datalo =3D *args++; - datahi =3D (is64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TARGET_LONG_BITS =3D=3D 64 ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); + MemOp opc =3D get_memop(oi); =20 #ifdef CONFIG_SOFTMMU - mem_index =3D get_mmuidx(oi); - addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1); + TCGReg addend=3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(o= i), 1); =20 - /* This a conditional BL only to load a pointer within this opcode int= o LR - for the slow path. We will not be using the value for a tail call.= */ - label_ptr =3D s->code_ptr; + /* + * This a conditional BL only to load a pointer within this opcode into + * LR for the slow path. We will not be using the value for a tail ca= ll. + */ + tcg_insn_unit *label_ptr =3D s->code_ptr; tcg_out_bl_imm(s, COND_NE, 0); =20 tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend, true); =20 - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } @@ -1918,41 +1908,26 @@ static void tcg_out_qemu_st_direct(TCGContext *s, M= emOp opc, TCGReg datalo, } #endif =20 -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) +static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, TCGType data_type) { - TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); - MemOpIdx oi; - MemOp opc; -#ifdef CONFIG_SOFTMMU - int mem_index; - TCGReg addend; - tcg_insn_unit *label_ptr; -#else - unsigned a_bits; -#endif - - datalo =3D *args++; - datahi =3D (is64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TARGET_LONG_BITS =3D=3D 64 ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); + MemOp opc =3D get_memop(oi); =20 #ifdef CONFIG_SOFTMMU - mem_index =3D get_mmuidx(oi); - addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0); + TCGReg addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(= oi), 0); =20 tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, addrlo, addend, true); =20 /* The conditional call must come last, as we're going to return here.= */ - label_ptr =3D s->code_ptr; + tcg_insn_unit *label_ptr =3D s->code_ptr; tcg_out_bl_imm(s, COND_NE, 0); =20 - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); } @@ -2245,16 +2220,40 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, 0); + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_ld(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I32); + } else { + tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], + args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, 1); + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_ld(s, args[0], args[1], args[2], -1, + args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], + args[4], TCG_TYPE_I64); + } break; case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, 0); + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_st(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I32); + } else { + tcg_out_qemu_st(s, args[0], -1, args[1], args[2], + args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, 1); + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_st(s, args[0], args[1], args[2], -1, + args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], + args[4], TCG_TYPE_I64); + } break; =20 case INDEX_op_bswap16_i32: --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322192; cv=none; d=zohomail.com; s=zohoarc; b=KQ+i3/JOeFU3HrJdqsTbME1IwosoVx5OahFZJSpVKAeSM2y3TEpVkFrwTSge4eb+ZZeWcg8o3v0+2AneiO9CosNmJA10Dvq+vu/ubUGZGwDrCiui16vUoK9bfHKTZjJZhX92YNy4+qoDQLO3FBzfCUwwO2wMQYVriQw2DQb99uU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683322192; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZLKOkrrM6X6Chuoo3/tcJ4CYY7RF9VAHo0E2og71vlU=; b=Eplm5V5Y/J8bnyIXtThNtI9KCq9vwWYgj6XPQFn3+Dc+w6E2bulgXuxyT4Xn41C1AvkASHQvjzo10bBsMDV06BBOaRG4QtZqERMp4N+35Z45u6TDQbjMapzy/1Ral8YtAqHmT0cc/IKPjcYjc1g45HaGz/RO0O4ku1+6yfzQUM0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683322192823111.57862817406601; Fri, 5 May 2023 14:29:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vW-0000pd-M9; Fri, 05 May 2023 17:25:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vT-0000mu-Q9 for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:15 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2vL-0004eC-PA for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:15 -0400 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-3077d134028so817064f8f.3 for ; Fri, 05 May 2023 14:25:05 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321903; x=1685913903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ZLKOkrrM6X6Chuoo3/tcJ4CYY7RF9VAHo0E2og71vlU=; b=N97QupoH4M0BRRKYI4+tlPbzg2kjWCLr93jtqfpCV7dHYdjWor/ZQ8yOUiH7vIi2xN cnuNESIW6GunmREzEP26B80gq2dwwKcj3G6KdhH+4kUFqAqfrBWxxk5UpepyX2HaFco/ xtb2nc+F+7C+L9ezeHermPf/V1LzgAUAkmrc+tXwkklt4YhnMlasjwp+CVCnEQvGC3JF PfjZdyvxA0pCYkKUrHh3CV59tHDtoooYAsT2NFSGXkkeJplck9ivaJ6HR0SEavNUD2/H 3jtnkF56mDtL1GE683qnO2eMRaZ9SI/hdICFP/WiXyy124mP0aldycdNKNpcGHB/C8yS WFcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321903; x=1685913903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZLKOkrrM6X6Chuoo3/tcJ4CYY7RF9VAHo0E2og71vlU=; b=EdzsfUf6EDzGlOorCiiDmXbTPw1742lFQsPCUahLNh5LX2ayxBW2ANNw4oDr6d99UA 0sjFC3ZYGKbgubvoZS7rcpVGXEgwhFn4Quxyxr4AFXuydsDZhBoRZk/KG/hTyHWfblgn vQXYo+ShH1KVY+Pu/1bJ+yPQETtWs+WiL9vU6ZDHDqXv2ZwBDEfTcm5MKiCugdyQpdK/ L3v162qvEHECTb0PKearj87SQDjL5tz8HKH+nvRYBQz8CHGvbaoyr3afyTRou0sFA1oC 8+lFmVvkLTCSwrD6dLxWgdH2on11KtoS1nA6whSi5UfdwYyXIerhdKkwbJwgQ5Wg1cTn LmRg== X-Gm-Message-State: AC+VfDy7sYtF4g9Llx4ozxlZujSxytKb2tHiXlg5DqeG0YCktVgB29nb 39bDhnc5llc74of90BjQ73sD4mwX6g+fdypnQwXYhw== X-Google-Smtp-Source: ACHHUZ77f4uSZNPocOggauDkQxUW3cC06M2GZA7Noaojhqg5lOgalxPDgk8gwV5nYW2dhNwFvphNoA== X-Received: by 2002:adf:fe47:0:b0:306:434:f8ef with SMTP id m7-20020adffe47000000b003060434f8efmr1943858wrs.70.1683321903644; Fri, 05 May 2023 14:25:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 27/42] tcg/arm: Introduce HostAddress Date: Fri, 5 May 2023 22:24:32 +0100 Message-Id: <20230505212447.374546-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322194938100015 Content-Type: text/plain; charset="utf-8" Collect the parts of the host address, and condition, into a struct. Merge tcg_out_qemu_*_{index,direct} and use it. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 248 ++++++++++++++++++--------------------- 1 file changed, 115 insertions(+), 133 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 6ce52b9612..b6b4ffc546 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1337,6 +1337,13 @@ static void tcg_out_vldst(TCGContext *s, ARMInsn ins= n, tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf); } =20 +typedef struct { + ARMCond cond; + TCGReg base; + int index; + bool index_scratch; +} HostAddress; + #ifdef CONFIG_SOFTMMU /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) @@ -1696,29 +1703,49 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) } #endif /* SOFTMMU */ =20 -static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addend, - bool scratch_addend) +static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, + TCGReg datahi, HostAddress h) { + TCGReg base; + /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); =20 switch (opc & MO_SSIZE) { case MO_UB: - tcg_out_ld8_r(s, COND_AL, datalo, addrlo, addend); + if (h.index < 0) { + tcg_out_ld8_12(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_ld8_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_SB: - tcg_out_ld8s_r(s, COND_AL, datalo, addrlo, addend); + if (h.index < 0) { + tcg_out_ld8s_8(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_ld8s_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_UW: - tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend); + if (h.index < 0) { + tcg_out_ld16u_8(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_ld16u_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_SW: - tcg_out_ld16s_r(s, COND_AL, datalo, addrlo, addend); + if (h.index < 0) { + tcg_out_ld16s_8(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_ld16s_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_UL: - tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend); + if (h.index < 0) { + tcg_out_ld32_12(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_ld32_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_UQ: /* We used pair allocation for datalo, so already should be aligne= d. */ @@ -1726,87 +1753,59 @@ static void tcg_out_qemu_ld_index(TCGContext *s, Me= mOp opc, tcg_debug_assert(datahi =3D=3D datalo + 1); /* LDRD requires alignment; double-check that. */ if (get_alignment_bits(opc) >=3D MO_64) { + if (h.index < 0) { + tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); + break; + } /* * Rm (the second address op) must not overlap Rt or Rt + 1. * Since datalo is aligned, we can simplify the test via align= ment. * Flip the two address arguments if that works. */ - if ((addend & ~1) !=3D datalo) { - tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend); + if ((h.index & ~1) !=3D datalo) { + tcg_out_ldrd_r(s, h.cond, datalo, h.base, h.index); break; } - if ((addrlo & ~1) !=3D datalo) { - tcg_out_ldrd_r(s, COND_AL, datalo, addend, addrlo); + if ((h.base & ~1) !=3D datalo) { + tcg_out_ldrd_r(s, h.cond, datalo, h.index, h.base); break; } } - if (scratch_addend) { - tcg_out_ld32_rwb(s, COND_AL, datalo, addend, addrlo); - tcg_out_ld32_12(s, COND_AL, datahi, addend, 4); + if (h.index < 0) { + base =3D h.base; + if (datalo =3D=3D h.base) { + tcg_out_mov_reg(s, h.cond, TCG_REG_TMP, base); + base =3D TCG_REG_TMP; + } + } else if (h.index_scratch) { + tcg_out_ld32_rwb(s, h.cond, datalo, h.index, h.base); + tcg_out_ld32_12(s, h.cond, datahi, h.index, 4); + break; } else { - tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP, - addend, addrlo, SHIFT_IMM_LSL(0)); - tcg_out_ld32_12(s, COND_AL, datalo, TCG_REG_TMP, 0); - tcg_out_ld32_12(s, COND_AL, datahi, TCG_REG_TMP, 4); + tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, + h.base, h.index, SHIFT_IMM_LSL(0)); + base =3D TCG_REG_TMP; } + tcg_out_ld32_12(s, h.cond, datalo, base, 0); + tcg_out_ld32_12(s, h.cond, datahi, base, 4); break; default: g_assert_not_reached(); } } =20 -#ifndef CONFIG_SOFTMMU -static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, - TCGReg datahi, TCGReg addrlo) -{ - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); - - switch (opc & MO_SSIZE) { - case MO_UB: - tcg_out_ld8_12(s, COND_AL, datalo, addrlo, 0); - break; - case MO_SB: - tcg_out_ld8s_8(s, COND_AL, datalo, addrlo, 0); - break; - case MO_UW: - tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0); - break; - case MO_SW: - tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0); - break; - case MO_UL: - tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); - break; - case MO_UQ: - /* We used pair allocation for datalo, so already should be aligne= d. */ - tcg_debug_assert((datalo & 1) =3D=3D 0); - tcg_debug_assert(datahi =3D=3D datalo + 1); - /* LDRD requires alignment; double-check that. */ - if (get_alignment_bits(opc) >=3D MO_64) { - tcg_out_ldrd_8(s, COND_AL, datalo, addrlo, 0); - } else if (datalo =3D=3D addrlo) { - tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4); - tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); - } else { - tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); - tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4); - } - break; - default: - g_assert_not_reached(); - } -} -#endif - static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); + HostAddress h; =20 #ifdef CONFIG_SOFTMMU - TCGReg addend=3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(o= i), 1); + h.cond =3D COND_AL; + h.base =3D addrlo; + h.index_scratch =3D true; + h.index =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 1= ); =20 /* * This a conditional BL only to load a pointer within this opcode into @@ -1815,80 +1814,51 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, tcg_insn_unit *label_ptr =3D s->code_ptr; tcg_out_bl_imm(s, COND_NE, 0); =20 - tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend, true); + tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); =20 add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ +#else unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } - if (guest_base) { - tcg_out_qemu_ld_index(s, opc, datalo, datahi, - addrlo, TCG_REG_GUEST_BASE, false); - } else { - tcg_out_qemu_ld_direct(s, opc, datalo, datahi, addrlo); - } + + h.cond =3D COND_AL; + h.base =3D addrlo; + h.index =3D guest_base ? TCG_REG_GUEST_BASE : -1; + h.index_scratch =3D false; + tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); #endif } =20 -static void tcg_out_qemu_st_index(TCGContext *s, ARMCond cond, MemOp opc, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addend, - bool scratch_addend) -{ - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); - - switch (opc & MO_SIZE) { - case MO_8: - tcg_out_st8_r(s, cond, datalo, addrlo, addend); - break; - case MO_16: - tcg_out_st16_r(s, cond, datalo, addrlo, addend); - break; - case MO_32: - tcg_out_st32_r(s, cond, datalo, addrlo, addend); - break; - case MO_64: - /* We used pair allocation for datalo, so already should be aligne= d. */ - tcg_debug_assert((datalo & 1) =3D=3D 0); - tcg_debug_assert(datahi =3D=3D datalo + 1); - /* STRD requires alignment; double-check that. */ - if (get_alignment_bits(opc) >=3D MO_64) { - tcg_out_strd_r(s, cond, datalo, addrlo, addend); - } else if (scratch_addend) { - tcg_out_st32_rwb(s, cond, datalo, addend, addrlo); - tcg_out_st32_12(s, cond, datahi, addend, 4); - } else { - tcg_out_dat_reg(s, cond, ARITH_ADD, TCG_REG_TMP, - addend, addrlo, SHIFT_IMM_LSL(0)); - tcg_out_st32_12(s, cond, datalo, TCG_REG_TMP, 0); - tcg_out_st32_12(s, cond, datahi, TCG_REG_TMP, 4); - } - break; - default: - g_assert_not_reached(); - } -} - -#ifndef CONFIG_SOFTMMU static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, - TCGReg datahi, TCGReg addrlo) + TCGReg datahi, HostAddress h) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); =20 switch (opc & MO_SIZE) { case MO_8: - tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0); + if (h.index < 0) { + tcg_out_st8_12(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_st8_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_16: - tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0); + if (h.index < 0) { + tcg_out_st16_8(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_st16_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_32: - tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); + if (h.index < 0) { + tcg_out_st32_12(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_st32_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_64: /* We used pair allocation for datalo, so already should be aligne= d. */ @@ -1896,29 +1866,39 @@ static void tcg_out_qemu_st_direct(TCGContext *s, M= emOp opc, TCGReg datalo, tcg_debug_assert(datahi =3D=3D datalo + 1); /* STRD requires alignment; double-check that. */ if (get_alignment_bits(opc) >=3D MO_64) { - tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0); + if (h.index < 0) { + tcg_out_strd_8(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_strd_r(s, h.cond, datalo, h.base, h.index); + } + } else if (h.index_scratch) { + tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base); + tcg_out_st32_12(s, h.cond, datahi, h.index, 4); } else { - tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); - tcg_out_st32_12(s, COND_AL, datahi, addrlo, 4); + tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, + h.base, h.index, SHIFT_IMM_LSL(0)); + tcg_out_st32_12(s, h.cond, datalo, TCG_REG_TMP, 0); + tcg_out_st32_12(s, h.cond, datahi, TCG_REG_TMP, 4); } break; default: g_assert_not_reached(); } } -#endif =20 static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); + HostAddress h; =20 #ifdef CONFIG_SOFTMMU - TCGReg addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(= oi), 0); - - tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, - addrlo, addend, true); + h.cond =3D COND_EQ; + h.base =3D addrlo; + h.index_scratch =3D true; + h.index =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 0= ); + tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); =20 /* The conditional call must come last, as we're going to return here.= */ tcg_insn_unit *label_ptr =3D s->code_ptr; @@ -1926,17 +1906,19 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, =20 add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ +#else unsigned a_bits =3D get_alignment_bits(opc); + + h.cond =3D COND_AL; if (a_bits) { tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); + h.cond =3D COND_EQ; } - if (guest_base) { - tcg_out_qemu_st_index(s, COND_AL, opc, datalo, datahi, - addrlo, TCG_REG_GUEST_BASE, false); - } else { - tcg_out_qemu_st_direct(s, opc, datalo, datahi, addrlo); - } + + h.base =3D addrlo; + h.index =3D guest_base ? TCG_REG_GUEST_BASE : -1; + h.index_scratch =3D false; + tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); #endif } =20 --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683321977726975.1653323414745; Fri, 5 May 2023 14:26:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vU-0000nA-50; Fri, 05 May 2023 17:25:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vR-0000lR-VN for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:13 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2vL-0004eL-Dc for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:13 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-3f4000ec74aso16111355e9.3 for ; Fri, 05 May 2023 14:25:05 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321904; x=1685913904; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PC+Gw/9P+2wBG7ELo5n/093Z6DPtUA9B8lGYDE8K0ac=; b=PEa+IglBaJl6WTCT7/pVaQnFyn3/uyO7VY3EoBCKqUHIKs4aiP+KYAyOAXRlrZXhPs FwFKkjppNMiDD+FYe2kv4CHQsnvd/dEjemuWFMfvr2a4mHqc9Z3DTd739tLi+Yzv8A7J HPPfkbQMncqofMQ0ptEPeLXwV5O6tlMq9gcJhCmM4+HXgzKYdKTLLQnTtChU2zzOYqcF MWTrcj/yBqlUjNVjOLL9yMhwLbNqDaEDRp3OuXRTgFUDW2C9T64gD4ylPh2VxZy5WDeY TqL2B3CrapVR5Qyk2mVgy/n+u0Zy79tfeMPjojCc6fomir4n9Ve1uj0Pxave1nV23Nsx 5utQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321904; x=1685913904; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PC+Gw/9P+2wBG7ELo5n/093Z6DPtUA9B8lGYDE8K0ac=; b=bhN4RBbcxGPR13XXxCSRj12nfFiNSBUFp7KDvyRugDfwvM5qH0vya/FYLnO+ALM52a Q50VduO/T4rDAG0yEcCctiHkNYfFT78ZBqAKp5lXEFYSaYhut5q2Hv4x75HMypFZtW82 fvLYHSRt0q7poilFp+KLvIUc2AD1JHTZb+6SHkmJCQ59OWmDaUVn/AShr/ZrcLprW227 jSzym6sVZRaQNwXi/SMVeWHmPvrTM47MUdok8aXdK3mFjCbW6A+CL/mfNg9AkcIiAejb Tf4ik5DuMnv7n4TcTG915KTiDAyqZk5w/Zp+bphbMOY86RGlPIjE67FtfzW6WxEbGErk 3ngw== X-Gm-Message-State: AC+VfDyt88s8quopO7H9Ggpsde6Vb/VEEoAidfFotEdVgH+c5HloQUc4 292jm0CtCADCbMLwSjNi4N/iCbW8yBYs/Of1p9SQXg== X-Google-Smtp-Source: ACHHUZ5/JpihHe7DKLNrhfI86y+CDFz8Atjm0GhwdNJ/qknU39zfHNOQ56szjxxlkImB6jJ/97sN/Q== X-Received: by 2002:a05:6000:192:b0:2f2:7a7e:6ac with SMTP id p18-20020a056000019200b002f27a7e06acmr2102674wrx.48.1683321904165; Fri, 05 May 2023 14:25:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 28/42] tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld, st} Date: Fri, 5 May 2023 22:24:33 +0100 Message-Id: <20230505212447.374546-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683321978960100017 Interpret the variable argument placement in the caller. Shift some code around slightly to share more between softmmu and user-only. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 100 +++++++++++++------------------ 1 file changed, 42 insertions(+), 58 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 0940788c6f..2e3c67054b 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1049,39 +1049,31 @@ static void tcg_out_qemu_ld_indexed(TCGContext *s, = TCGReg rd, TCGReg rj, } } =20 -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGType typ= e) +static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, + MemOpIdx oi, TCGType data_type) { - TCGReg addr_regl; - TCGReg data_regl; - MemOpIdx oi; - MemOp opc; -#if defined(CONFIG_SOFTMMU) + MemOp opc =3D get_memop(oi); + TCGReg base, index; + +#ifdef CONFIG_SOFTMMU tcg_insn_unit *label_ptr[1]; -#else - unsigned a_bits; -#endif - TCGReg base; =20 - data_regl =3D *args++; - addr_regl =3D *args++; - oi =3D *args++; - opc =3D get_memop(oi); - -#if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 1); - base =3D tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); - tcg_out_qemu_ld_indexed(s, data_regl, base, TCG_REG_TMP2, opc, type); - add_qemu_ldst_label(s, 1, oi, type, - data_regl, addr_regl, - s->code_ptr, label_ptr); + tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1); + index =3D TCG_REG_TMP2; #else - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { - tcg_out_test_alignment(s, true, addr_regl, a_bits); + tcg_out_test_alignment(s, true, addr_reg, a_bits); } - base =3D tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); - TCGReg guest_base_reg =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_RE= G_ZERO; - tcg_out_qemu_ld_indexed(s, data_regl, base, guest_base_reg, opc, type); + index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; +#endif + + base =3D tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0); + tcg_out_qemu_ld_indexed(s, data_reg, base, index, opc, data_type); + +#ifdef CONFIG_SOFTMMU + add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, + s->code_ptr, label_ptr); #endif } =20 @@ -1109,39 +1101,31 @@ static void tcg_out_qemu_st_indexed(TCGContext *s, = TCGReg data, } } =20 -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGType typ= e) +static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, + MemOpIdx oi, TCGType data_type) { - TCGReg addr_regl; - TCGReg data_regl; - MemOpIdx oi; - MemOp opc; -#if defined(CONFIG_SOFTMMU) + MemOp opc =3D get_memop(oi); + TCGReg base, index; + +#ifdef CONFIG_SOFTMMU tcg_insn_unit *label_ptr[1]; -#else - unsigned a_bits; -#endif - TCGReg base; =20 - data_regl =3D *args++; - addr_regl =3D *args++; - oi =3D *args++; - opc =3D get_memop(oi); - -#if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 0); - base =3D tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); - tcg_out_qemu_st_indexed(s, data_regl, base, TCG_REG_TMP2, opc); - add_qemu_ldst_label(s, 0, oi, type, - data_regl, addr_regl, - s->code_ptr, label_ptr); + tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0); + index =3D TCG_REG_TMP2; #else - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { - tcg_out_test_alignment(s, false, addr_regl, a_bits); + tcg_out_test_alignment(s, false, addr_reg, a_bits); } - base =3D tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); - TCGReg guest_base_reg =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_RE= G_ZERO; - tcg_out_qemu_st_indexed(s, data_regl, base, guest_base_reg, opc); + index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; +#endif + + base =3D tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0); + tcg_out_qemu_st_indexed(s, data_reg, base, index, opc); + +#ifdef CONFIG_SOFTMMU + add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, + s->code_ptr, label_ptr); #endif } =20 @@ -1564,16 +1548,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, TCG_TYPE_I32); + tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, TCG_TYPE_I64); + tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); break; case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, TCG_TYPE_I32); + tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, TCG_TYPE_I64); + tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); break; =20 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322091; cv=none; d=zohomail.com; s=zohoarc; b=cvh6x6QcssYTlrmPY0M839uOp7Oo6m1AJ2WpRFumPtjsFbaYCgf23nOK/WoAP5yX8jwT96Dd4QfMVMXoy2H12qv16YVFKBK8WvOsLeIjUIiZtNODidAQmG3m7vY8ec7As+aG0OttndIuJdpabgDPDDgQpxHQ6qWmaeOkESPEtIk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683322091; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=N3QoKqsv+R/CZvxHdMJxo06yfgQBTVK77OIFinD6LW0=; b=YVyXqdQ5ZouforgJjWp2w7E48kBn6Tpno94zHxPjbqb3NyC87tP1+t+HJYcC2t/2wGpyppow3huDX2e86RGM0d63fi74EyzpejSOUujNm7eqLm88gtcWKmqhPq4CEKwowxLNcDK7CtJVhSLTZAh2g9pxz3gWEXPbBeGVjGWB170= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683322091394847.8126372285291; Fri, 5 May 2023 14:28:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vU-0000n8-3C; Fri, 05 May 2023 17:25:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vQ-0000jn-DB for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:12 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2vK-0004eP-Ki for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:12 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-3023a56048bso2068746f8f.3 for ; Fri, 05 May 2023 14:25:05 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321904; x=1685913904; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N3QoKqsv+R/CZvxHdMJxo06yfgQBTVK77OIFinD6LW0=; b=lCcnUi1PNBXtVTJG9bDLiZ+8llf4r1cNbKK/Y6LPEnovFCGoIW2aqmicEMk+peJ1ZL Wm9fijbi8Kd2Sd3kLi3K32Dbi+oSj9UbGheOHRkpHCQy5gm5hJVxvfrQWACgCK3wI52o FkR/jABsLj/g+YzblDLKZ3AEW40XzWpCzGnzLIlktpNKbq9YuparbFoLLwH3GedWv5U3 yCV0TBK34E8TK1YmmI0GgJ+QboUNkT/9zxC2iC9z+01krc5W+gtI1b/3wN6RgxnaehTa wpCVIeDtLfKnjRDSlkHs6PWcz7RtMSWwUVc5/C2Q0OP23mADVqs5yeCdARS9UPkLaRMv edgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321904; x=1685913904; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N3QoKqsv+R/CZvxHdMJxo06yfgQBTVK77OIFinD6LW0=; b=cgamqStpaUJX936O8p/SagAnX8f2MaERHL/AYIop0FQas6eWN12q5ZdDANqQMxQgmN LtpxdIQMV11CKp7B594rC0LCc1HARgT6nfHNdW4Lm3fkoe8IhhIisEY751pD6GbhehoE G7XjFEo67ysWyxqKDSrrk9klVK08b41uiswACf92Co9HvQ1LBcV1Jmz8Hv/q/vaGKXkj bO9s3/3YtLeZogLgjuxVIQdGrmYr+XASnzLXi/XBxKkkfVpjMh/kJgQNUxdBbdPNpqbq rvCDIu7umFr0QC8WprLAH5B2Qhf6S7x8Xz5HEMR7Zab0MyThj9qS5//SEZkWx3yiFKbV kZeg== X-Gm-Message-State: AC+VfDw64WvvggopYYZBquyvHBjbSpjOiAhS2kFJjFg2/72Vpq+FBmuN xUu7cHrzAHPvMB5yPdrEtl1TmGnaQqO97V2xHJz+zQ== X-Google-Smtp-Source: ACHHUZ7Zzba5vUmKapSdmehTlDwTNBVfHZA2onHL+oFM9mWPPdgnc/ZRW+sxsJNln1tU1YWCr8Do9g== X-Received: by 2002:adf:e70c:0:b0:306:330e:bfe3 with SMTP id c12-20020adfe70c000000b00306330ebfe3mr2555508wrm.19.1683321904687; Fri, 05 May 2023 14:25:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 29/42] tcg/loongarch64: Introduce HostAddress Date: Fri, 5 May 2023 22:24:34 +0100 Message-Id: <20230505212447.374546-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322093354100003 Collect the 2 parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st}_direct to use it. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 55 +++++++++++++++++--------------- 1 file changed, 30 insertions(+), 25 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 2e3c67054b..6a87a5e5a3 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1013,36 +1013,41 @@ static TCGReg tcg_out_zext_addr_if_32_bit(TCGContex= t *s, return addr; } =20 -static void tcg_out_qemu_ld_indexed(TCGContext *s, TCGReg rd, TCGReg rj, - TCGReg rk, MemOp opc, TCGType type) +typedef struct { + TCGReg base; + TCGReg index; +} HostAddress; + +static void tcg_out_qemu_ld_indexed(TCGContext *s, MemOp opc, TCGType type, + TCGReg rd, HostAddress h) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); =20 switch (opc & MO_SSIZE) { case MO_UB: - tcg_out_opc_ldx_bu(s, rd, rj, rk); + tcg_out_opc_ldx_bu(s, rd, h.base, h.index); break; case MO_SB: - tcg_out_opc_ldx_b(s, rd, rj, rk); + tcg_out_opc_ldx_b(s, rd, h.base, h.index); break; case MO_UW: - tcg_out_opc_ldx_hu(s, rd, rj, rk); + tcg_out_opc_ldx_hu(s, rd, h.base, h.index); break; case MO_SW: - tcg_out_opc_ldx_h(s, rd, rj, rk); + tcg_out_opc_ldx_h(s, rd, h.base, h.index); break; case MO_UL: if (type =3D=3D TCG_TYPE_I64) { - tcg_out_opc_ldx_wu(s, rd, rj, rk); + tcg_out_opc_ldx_wu(s, rd, h.base, h.index); break; } /* fallthrough */ case MO_SL: - tcg_out_opc_ldx_w(s, rd, rj, rk); + tcg_out_opc_ldx_w(s, rd, h.base, h.index); break; case MO_UQ: - tcg_out_opc_ldx_d(s, rd, rj, rk); + tcg_out_opc_ldx_d(s, rd, h.base, h.index); break; default: g_assert_not_reached(); @@ -1053,23 +1058,23 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); - TCGReg base, index; + HostAddress h; =20 #ifdef CONFIG_SOFTMMU tcg_insn_unit *label_ptr[1]; =20 tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1); - index =3D TCG_REG_TMP2; + h.index =3D TCG_REG_TMP2; #else unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addr_reg, a_bits); } - index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; + h.index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; #endif =20 - base =3D tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0); - tcg_out_qemu_ld_indexed(s, data_reg, base, index, opc, data_type); + h.base =3D tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0); + tcg_out_qemu_ld_indexed(s, opc, data_type, data_reg, h); =20 #ifdef CONFIG_SOFTMMU add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, @@ -1077,24 +1082,24 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, #endif } =20 -static void tcg_out_qemu_st_indexed(TCGContext *s, TCGReg data, - TCGReg rj, TCGReg rk, MemOp opc) +static void tcg_out_qemu_st_indexed(TCGContext *s, MemOp opc, + TCGReg rd, HostAddress h) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); =20 switch (opc & MO_SIZE) { case MO_8: - tcg_out_opc_stx_b(s, data, rj, rk); + tcg_out_opc_stx_b(s, rd, h.base, h.index); break; case MO_16: - tcg_out_opc_stx_h(s, data, rj, rk); + tcg_out_opc_stx_h(s, rd, h.base, h.index); break; case MO_32: - tcg_out_opc_stx_w(s, data, rj, rk); + tcg_out_opc_stx_w(s, rd, h.base, h.index); break; case MO_64: - tcg_out_opc_stx_d(s, data, rj, rk); + tcg_out_opc_stx_d(s, rd, h.base, h.index); break; default: g_assert_not_reached(); @@ -1105,23 +1110,23 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); - TCGReg base, index; + HostAddress h; =20 #ifdef CONFIG_SOFTMMU tcg_insn_unit *label_ptr[1]; =20 tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0); - index =3D TCG_REG_TMP2; + h.index =3D TCG_REG_TMP2; #else unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, false, addr_reg, a_bits); } - index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; + h.index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; #endif =20 - base =3D tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0); - tcg_out_qemu_st_indexed(s, data_reg, base, index, opc); + h.base =3D tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0); + tcg_out_qemu_st_indexed(s, opc, data_reg, h); =20 #ifdef CONFIG_SOFTMMU add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322045; cv=none; d=zohomail.com; s=zohoarc; b=Nv9L+bq5Gxb/iYH2ez/fXS0EkdWWWBvm/G3636Bv6Rzr/Zy+XaCfgutsLWl2ODuI41ysdJzxHHWMd+x9OvgJKYEu20cwAVjoLQMig4aez6R6Y52XcvYlVtkauGR9jX3tSv5eF0YnEgXGinWqg+G3kc7cPWeqP1Ly9rL2Mpje+XM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683322045; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Wb60bEd1se1ur05309xVh3zsavyenSUVa4kDdGCo6us=; b=Uu4EPFZk5206ujKaL2a/5WpHbTXKKTmbzVeatGcINJAvdTB6kUzzsUH1Ygdlb90oDNA/Mepd3pTVLNL5LwUtYdPh/IOeyRu02LgaKwrGmGVNdGLRj2ZBQUrnr5eHK3GdQ1Z6MeNqVeP1m508pObEuIIlYmi/S6FIZSP4B9JRPpI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683322045960171.22242150266402; Fri, 5 May 2023 14:27:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vV-0000pD-S0; Fri, 05 May 2023 17:25:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vQ-0000jb-8o for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:12 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2vK-0004Oi-Ia for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:12 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-3f182d745deso23288245e9.0 for ; Fri, 05 May 2023 14:25:05 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321905; x=1685913905; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Wb60bEd1se1ur05309xVh3zsavyenSUVa4kDdGCo6us=; b=yMaffd2X0g0y8AY94gyZ2HZ0jS6KNHphSs1YLF5fVa/f9UMPtkwxpfQRDgvnkYxlmf wo++/gVa4QE9zNgiEb4FF5CrXU3fRaLQ0Om7xTDA5uwHfCMH2vBKT6izZIWe5zaQzAjG UDHVLTF9BMDBD/cXI6v7mNOOu5Md93k/1Fvyeit7l3cw+OD2ij9rH0RULDMz6gb+qOym NqfrTNXeJQW12Afs+YBLx/QgReU1re1OwrbtFgt06KI0Ik2/nLvNFr6KHAZb0QQpklN1 q20cw79JN2oXaERmvo5QWc7eyvJKsIoxKB2ZzbN7jS8mJb5VipL/KnXPI4ueKWCPoq6j N0qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321905; x=1685913905; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Wb60bEd1se1ur05309xVh3zsavyenSUVa4kDdGCo6us=; b=VefKhqW59QmrOsHWnARpaXb4luzKKZPDdKeSEHKg5XtQFjwplIWAW1kS73FhvxT6vH RErLB/G4k+5iAfU12QMPaGAG67LMPSIMMn9XPHCkJirsZX1LIXg6e7WLY0Z3lGJGP2/h LjHeg7MnL7ASg2PZreOMW2IdNNxARIr01oZAEdm+SsH+b4MQCtMRUOccT2Fo+18YWqeD Y6PJrW7QzVO9XD9cxloI6BX1ree53nFuA7AiJI1O0NaxMzTPk/BA+H3j5CB1lDvTd3Fy 6WK6rIR4IZJoL9WIxRfaUekSJ8Ez+TAxD7kgAdFp2emNb8aoabzPsZFT9LrBiPWIxi38 yd1g== X-Gm-Message-State: AC+VfDyBP6FwFu7Y27lrOqYVEIhmmL11cgbMcWhjyvPc261WVVzKDVii /M8HO75I0tcrp9oBYlm1tOegVrXnMWI56ZWRBrmJ3A== X-Google-Smtp-Source: ACHHUZ6Rd1VRmH0HDc+lgCoKjk2AMwmhNx0lQjUX1ax0xfW5mm0umYAypshxRI5ZXQ74w3OCYrWO0Q== X-Received: by 2002:a1c:f715:0:b0:3f1:661e:4686 with SMTP id v21-20020a1cf715000000b003f1661e4686mr2160880wmh.7.1683321905230; Fri, 05 May 2023 14:25:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 30/42] tcg/mips: Rationalize args to tcg_out_qemu_{ld,st} Date: Fri, 5 May 2023 22:24:35 +0100 Message-Id: <20230505212447.374546-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322046597100001 Interpret the variable argument placement in the caller. There are several places where we already convert back from bool to type. Clean things up by using type throughout. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 186 +++++++++++++++++++------------------- 1 file changed, 95 insertions(+), 91 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index a83ebe8729..ef8350e9cd 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1479,7 +1479,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) #endif /* SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, - TCGReg base, MemOp opc, bool is_64) + TCGReg base, MemOp opc, TCGType type) { switch (opc & (MO_SSIZE | MO_BSWAP)) { case MO_UB: @@ -1503,7 +1503,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, tcg_out_opc_imm(s, OPC_LH, lo, base, 0); break; case MO_UL | MO_BSWAP: - if (TCG_TARGET_REG_BITS =3D=3D 64 && is_64) { + if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64) { if (use_mips32r2_instructions) { tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); tcg_out_bswap32(s, lo, lo, TCG_BSWAP_IZ | TCG_BSWAP_OZ); @@ -1528,7 +1528,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, } break; case MO_UL: - if (TCG_TARGET_REG_BITS =3D=3D 64 && is_64) { + if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64) { tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); break; } @@ -1583,7 +1583,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, } =20 static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, - TCGReg base, MemOp opc, bool is_64) + TCGReg base, MemOp opc, TCGType type) { const MIPSInsn lw1 =3D MIPS_BE ? OPC_LWL : OPC_LWR; const MIPSInsn lw2 =3D MIPS_BE ? OPC_LWR : OPC_LWL; @@ -1623,7 +1623,7 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TC= GReg lo, TCGReg hi, case MO_UL: tcg_out_opc_imm(s, lw1, lo, base, 0); tcg_out_opc_imm(s, lw2, lo, base, 3); - if (TCG_TARGET_REG_BITS =3D=3D 64 && is_64 && !sgn) { + if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64 && != sgn) { tcg_out_ext32u(s, lo, lo); } break; @@ -1634,18 +1634,18 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, = TCGReg lo, TCGReg hi, tcg_out_opc_imm(s, lw1, lo, base, 0); tcg_out_opc_imm(s, lw2, lo, base, 3); tcg_out_bswap32(s, lo, lo, - TCG_TARGET_REG_BITS =3D=3D 64 && is_64 + TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D T= CG_TYPE_I64 ? (sgn ? TCG_BSWAP_OS : TCG_BSWAP_OZ) : 0); } else { const tcg_insn_unit *subr =3D - (TCG_TARGET_REG_BITS =3D=3D 64 && is_64 && !sgn + (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64= && !sgn ? bswap32u_addr : bswap32_addr); =20 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0); tcg_out_bswap_subr(s, subr); /* delay slot */ tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 3); - tcg_out_mov(s, is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, lo, TCG_TM= P3); + tcg_out_mov(s, type, lo, TCG_TMP3); } break; =20 @@ -1702,68 +1702,59 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, = TCGReg lo, TCGReg hi, } } =20 -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, TCGType data_type) { - TCGReg addr_regl, addr_regh __attribute__((unused)); - TCGReg data_regl, data_regh; - MemOpIdx oi; - MemOp opc; -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[2]; -#else -#endif - unsigned a_bits, s_bits; - TCGReg base =3D TCG_REG_A0; - - data_regl =3D *args++; - data_regh =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); - addr_regl =3D *args++; - addr_regh =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); - a_bits =3D get_alignment_bits(opc); - s_bits =3D opc & MO_SIZE; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned s_bits =3D opc & MO_SIZE; + TCGReg base; =20 /* * R6 removes the left/right instructions but requires the * system to support misaligned memory accesses. */ #if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1); + tcg_insn_unit *label_ptr[2]; + + base =3D TCG_REG_A0; + tcg_out_tlb_load(s, base, addrlo, addrhi, oi, label_ptr, 1); if (use_mips32r6_instructions || a_bits >=3D s_bits) { - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type); } else { - tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is_64); + tcg_out_qemu_ld_unalign(s, datalo, datahi, base, opc, data_type); } - add_qemu_ldst_label(s, 1, oi, - (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_regl, data_regh, addr_regl, addr_regh, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #else + base =3D addrlo; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addr_regl); - addr_regl =3D base; + tcg_out_ext32u(s, TCG_REG_A0, base); + base =3D TCG_REG_A0; } - if (guest_base =3D=3D 0 && data_regl !=3D addr_regl) { - base =3D addr_regl; - } else if (guest_base =3D=3D (int16_t)guest_base) { - tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); - } else { - tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl= ); + if (guest_base) { + if (guest_base =3D=3D (int16_t)guest_base) { + tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); + } else { + tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, + TCG_GUEST_BASE_REG); + } + base =3D TCG_REG_A0; } if (use_mips32r6_instructions) { if (a_bits) { - tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); + tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type); } else { if (a_bits && a_bits !=3D s_bits) { - tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); + tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } if (a_bits >=3D s_bits) { - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_= 64); + tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type= ); } else { - tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is= _64); + tcg_out_qemu_ld_unalign(s, datalo, datahi, base, opc, data_typ= e); } } #endif @@ -1902,67 +1893,60 @@ static void tcg_out_qemu_st_unalign(TCGContext *s, = TCGReg lo, TCGReg hi, g_assert_not_reached(); } } -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) -{ - TCGReg addr_regl, addr_regh __attribute__((unused)); - TCGReg data_regl, data_regh; - MemOpIdx oi; - MemOp opc; -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[2]; -#endif - unsigned a_bits, s_bits; - TCGReg base =3D TCG_REG_A0; =20 - data_regl =3D *args++; - data_regh =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); - addr_regl =3D *args++; - addr_regh =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); - a_bits =3D get_alignment_bits(opc); - s_bits =3D opc & MO_SIZE; +static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, TCGType data_type) +{ + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned s_bits =3D opc & MO_SIZE; + TCGReg base; =20 /* * R6 removes the left/right instructions but requires the * system to support misaligned memory accesses. */ #if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0); + tcg_insn_unit *label_ptr[2]; + + base =3D TCG_REG_A0; + tcg_out_tlb_load(s, base, addrlo, addrhi, oi, label_ptr, 0); if (use_mips32r6_instructions || a_bits >=3D s_bits) { - tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + tcg_out_qemu_st_direct(s, datalo, datahi, base, opc); } else { - tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc); + tcg_out_qemu_st_unalign(s, datalo, datahi, base, opc); } - add_qemu_ldst_label(s, 0, oi, - (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_regl, data_regh, addr_regl, addr_regh, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #else + base =3D addrlo; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addr_regl); - addr_regl =3D base; + tcg_out_ext32u(s, TCG_REG_A0, base); + base =3D TCG_REG_A0; } - if (guest_base =3D=3D 0) { - base =3D addr_regl; - } else if (guest_base =3D=3D (int16_t)guest_base) { - tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); - } else { - tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl= ); + if (guest_base) { + if (guest_base =3D=3D (int16_t)guest_base) { + tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); + } else { + tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, + TCG_GUEST_BASE_REG); + } + base =3D TCG_REG_A0; } if (use_mips32r6_instructions) { if (a_bits) { - tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); + tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } - tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + tcg_out_qemu_st_direct(s, datalo, datahi, base, opc); } else { if (a_bits && a_bits !=3D s_bits) { - tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); + tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } if (a_bits >=3D s_bits) { - tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + tcg_out_qemu_st_direct(s, datalo, datahi, base, opc); } else { - tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc); + tcg_out_qemu_st_unalign(s, datalo, datahi, base, opc); } } #endif @@ -2425,16 +2409,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, false); + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); + } else { + tcg_out_qemu_ld(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, true); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); + } else if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); + } break; case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, false); + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); + } else { + tcg_out_qemu_st(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, true); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); + } else if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); + } break; =20 case INDEX_op_add2_i32: --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321906; x=1685913906; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KyKsoDmohPBZSp4W8unRK+Qo86bIZbr6mB+lGKIr14Y=; b=POJ4mVR+N8EGJp8WKt2woor3Rykxe2h34lswvNIkTnFHUTmtnKWTV9PVrjMo10Oj8h 8tHJUZn7+sybF6Sm7BYbqAbW3+Wnd7GF84yIe80+S17PeT9HlrjFDHVX0VufvcmLSL7M kfg9igCKD3ub7NuXMbGOKTA8OoP33AuZ6Xb+1ST5EoAYGziuogA1uWLKoWC2jEHzIqOx ApzImhI/vtOtiiFZc2mAUnNIhr6rKED5ihd5IY2PYh0UOlzv/NQPheqBrQD6n3p5CHPF YIz+M/zOtVggSKQaJds6TnzwFQHIoMoED6gZJ6rLwdK/uSKcNlja0C6LoBBUeLItiNpe Lf4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321906; x=1685913906; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KyKsoDmohPBZSp4W8unRK+Qo86bIZbr6mB+lGKIr14Y=; b=T6kLDpI+B4hom7k1XTa0UsAz8QfPpCVyxIK+qx5gT2FeyW43LUupmVlGnpNnwpSXTn de/1oyZPZh+sKvsJJSCrdPwSdZ/bTaK3NuLPz3UTIiDgZ/C2T9zgqVKjdxoD9laaHHXL 7JVvELKEc+bIYSr/Lt1DQv+6rsNdikkzYeTbCG3Fcfd/uQqVxbhg/580OfHkS5frrjMF 7pzEbhI1SINbVqZRag0qTLWvP5b9ATcw5PoeweXoVbT0eq/EsYGivcgJ+bE8NWgBauG9 CcLicGGB8z41npYvVMaPgdo9jwAPwDE3hDwM2lIkI8WgRl00kYFBupj4DNPG2lJrWLBt YPFw== X-Gm-Message-State: AC+VfDzkFuWwLNn3/o0I/h2IMIdxzaCBwSjdPA2G6dYYh3w0GsOYNgS4 3S7BUPlV2331N2QmKjkFM/VMklOZ90dSDVp5YIPa5g== X-Google-Smtp-Source: ACHHUZ63tOr8i+5kQ2hdoU532KN/p8A8RNDYB4F8iv6fuM/rNRl3BFv8gdwv2T6jXBPSK9UEgJ3Heg== X-Received: by 2002:adf:e60b:0:b0:306:2aa7:2ed2 with SMTP id p11-20020adfe60b000000b003062aa72ed2mr2004829wrm.61.1683321905877; Fri, 05 May 2023 14:25:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Daniel Henrique Barboza Subject: [PULL 31/42] tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st} Date: Fri, 5 May 2023 22:24:36 +0100 Message-Id: <20230505212447.374546-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322017363100007 Interpret the variable argument placement in the caller. Pass data_type instead of is64 -- there are several places where we already convert back from bool to type. Clean things up by using type throughout. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 110 +++++++++++++++++++++------------------ 1 file changed, 59 insertions(+), 51 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 77abb7d20c..d1aa2a9f53 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2118,7 +2118,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp o= pc, /* Record the context of a call to the out of line helper code for the slow path for a load or store, so that we can later generate the correct helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, + TCGType type, MemOpIdx oi, TCGReg datalo_reg, TCGReg datahi_reg, TCGReg addrlo_reg, TCGReg addrhi_reg, tcg_insn_unit *raddr, tcg_insn_unit *lptr) @@ -2126,6 +2127,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, MemOpIdx oi, TCGLabelQemuLdst *label =3D new_ldst_label(s); =20 label->is_ld =3D is_ld; + label->type =3D type; label->oi =3D oi; label->datalo_reg =3D datalo_reg; label->datahi_reg =3D datahi_reg; @@ -2288,30 +2290,18 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) =20 #endif /* SOFTMMU */ =20 -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, TCGType data_type) { - TCGReg datalo, datahi, addrlo, rbase; - TCGReg addrhi __attribute__((unused)); - MemOpIdx oi; - MemOp opc, s_bits; + MemOp opc =3D get_memop(oi); + MemOp s_bits =3D opc & MO_SIZE; + TCGReg rbase; + #ifdef CONFIG_SOFTMMU - int mem_index; tcg_insn_unit *label_ptr; -#else - unsigned a_bits; -#endif =20 - datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); - s_bits =3D opc & MO_SIZE; - -#ifdef CONFIG_SOFTMMU - mem_index =3D get_mmuidx(oi); - addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true); + addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), tr= ue); =20 /* Load a pointer into the current opcode w/conditional branch-link. */ label_ptr =3D s->code_ptr; @@ -2319,7 +2309,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) =20 rbase =3D TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } @@ -2364,35 +2354,23 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is_64) } =20 #ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #endif } =20 -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, TCGType data_type) { - TCGReg datalo, datahi, addrlo, rbase; - TCGReg addrhi __attribute__((unused)); - MemOpIdx oi; - MemOp opc, s_bits; + MemOp opc =3D get_memop(oi); + MemOp s_bits =3D opc & MO_SIZE; + TCGReg rbase; + #ifdef CONFIG_SOFTMMU - int mem_index; tcg_insn_unit *label_ptr; -#else - unsigned a_bits; -#endif =20 - datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); - s_bits =3D opc & MO_SIZE; - -#ifdef CONFIG_SOFTMMU - mem_index =3D get_mmuidx(oi); - addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false); + addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), fa= lse); =20 /* Load a pointer into the current opcode w/conditional branch-link. */ label_ptr =3D s->code_ptr; @@ -2400,7 +2378,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) =20 rbase =3D TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); } @@ -2437,8 +2415,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) } =20 #ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #endif } =20 @@ -2972,16 +2950,46 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, false); + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_qemu_ld(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I32); + } else { + tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], + args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, true); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_ld(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I64); + } else if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_ld(s, args[0], args[1], args[2], -1, + args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], + args[4], TCG_TYPE_I64); + } break; case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, false); + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_qemu_st(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I32); + } else { + tcg_out_qemu_st(s, args[0], -1, args[1], args[2], + args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, true); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_st(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I64); + } else if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_st(s, args[0], args[1], args[2], -1, + args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], + args[4], TCG_TYPE_I64); + } break; =20 case INDEX_op_setcond_i32: --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322034; cv=none; d=zohomail.com; s=zohoarc; b=f0vlxBB4kBjLNwJjl4d8i9+CjF5XYcIhJ6cIzWuBvDp6OJGI7q2EfPLlv7SEUyh8Qa2T2E9up6Qtw7jvbwFCOImgzHclVOmqtzeh8eBsyaO9HhBpWkwajdvS/bRPi32Tt1qze0eyuVdSPMNJFPydDc2153cR8j7CTQKrHhlPcjg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683322034; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9gzBsBjNi69rBqU30/4XrEpjrpJ6MM+4FytYgW6co40=; b=nPu1qh6bsgBbgYqYpHkh28Qb9DnH9VypATbpYBhfN7K/Pr3CVSrt6QwFEHoJMsfTKLEVEcqHqfo479b7KUQnJYZGU8K0OWAy+kPnojyprox/aCUR7FKCzFRmcWvhwooJjkPKnaIMaVBkSxtcieKeMqbDsdNJuYt9n7fk0LrUBWw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683322034089171.83383145533628; Fri, 5 May 2023 14:27:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vV-0000oS-DP; Fri, 05 May 2023 17:25:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vT-0000mj-F9 for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:15 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2vN-0004ev-9E for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:15 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-3062c1e7df8so1561438f8f.1 for ; Fri, 05 May 2023 14:25:08 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321906; x=1685913906; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9gzBsBjNi69rBqU30/4XrEpjrpJ6MM+4FytYgW6co40=; b=GF4IS9Km+m4zOmTaU20reXjv2kLIAOHtBpaSiPKFtGyWn/Seq4t54+q0TZNeUA3EBr qK0910pMZEXXwfOmY0xTR49HfDILTxtTawCBVUfSx7ovKSawuqifLlMg8Ie73gSmGjBe GSEL3UBkcxelahdpcn0MLXtZHnkqz1E/kbjZNxnyYsBJmJOeIAj7BgMyN/ukVfFFZ4MY lGv5nmaogn4quAfKoE3M124svQCYj6Cl+9UHLIQl7ATQbg0Aa3aiPEUrTQ7OJzAwM6km sfzs81FwBHm3resoVKZw9XQILvgiEjSvme4RhbwcfSAjT7T7A+PoF5OtO8pqFvrkTs4A lknw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321906; x=1685913906; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9gzBsBjNi69rBqU30/4XrEpjrpJ6MM+4FytYgW6co40=; b=M5QyA+nQ9WZ43pMNJmE68sNGS+luOCQzMps7Cy9AlTXit2DIU8jMcMXn6QvlBJnY34 U5FzLdGLEjat3ovrPL41svvCOMuzM4q5Xp8qqvK01Qn+JTKN3HyIJimMn4u9bOiZaYTO M12sKJqmiundaubsKXjkR743MLny3zuouHKlB0V/NfHSRKGC4K7sYbDhHzobERiCuxxn uyZlT2kvdvB94zhsdAUwgqGkwdPawLnHcuR3FFS4sCnOB4bgg6rb570IL+BS4kroT5Ei cWC5oo6baqRcAjPeC/fpE+ahkhKMs6s/0gzqlMPJQacg3J8gXsK5N05MwMzBWUOZCenK ygxw== X-Gm-Message-State: AC+VfDy4fBCX29w9hLfyttgzkYlOm4vEBzNJHBstpfdu/NaSxa8e+cdP fLZkC8eu7yznlnaIS0IlO1jyzD9kPKCQxI95sEMz2Q== X-Google-Smtp-Source: ACHHUZ4hIt92OiGaSvzj0CDGeGspPtaIzVzi92HWZ8xnMwanP1MCj+uQIr9Kdi2hNnxKWWmPkMm0Hg== X-Received: by 2002:a05:6000:cd:b0:306:37ac:ef8c with SMTP id q13-20020a05600000cd00b0030637acef8cmr2493281wrx.39.1683321906587; Fri, 05 May 2023 14:25:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 32/42] tcg/ppc: Introduce HostAddress Date: Fri, 5 May 2023 22:24:37 +0100 Message-Id: <20230505212447.374546-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322035108100003 Collect the parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st} to use it. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 90 +++++++++++++++++++++------------------- 1 file changed, 47 insertions(+), 43 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index d1aa2a9f53..cd473deb36 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2287,67 +2287,71 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) { return tcg_out_fail_alignment(s, l); } - #endif /* SOFTMMU */ =20 +typedef struct { + TCGReg base; + TCGReg index; +} HostAddress; + static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); MemOp s_bits =3D opc & MO_SIZE; - TCGReg rbase; + HostAddress h; =20 #ifdef CONFIG_SOFTMMU tcg_insn_unit *label_ptr; =20 - addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), tr= ue); + h.index =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), t= rue); + h.base =3D TCG_REG_R3; =20 /* Load a pointer into the current opcode w/conditional branch-link. */ label_ptr =3D s->code_ptr; tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); - - rbase =3D TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } - rbase =3D guest_base ? TCG_GUEST_BASE_REG : 0; + h.base =3D guest_base ? TCG_GUEST_BASE_REG : 0; + h.index =3D addrlo; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); - addrlo =3D TCG_REG_TMP1; + h.index =3D TCG_REG_TMP1; } #endif =20 if (TCG_TARGET_REG_BITS =3D=3D 32 && s_bits =3D=3D MO_64) { if (opc & MO_BSWAP) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); - tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo)); - tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0)); - } else if (rbase !=3D 0) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); - tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo)); - tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0)); - } else if (addrlo =3D=3D datahi) { - tcg_out32(s, LWZ | TAI(datalo, addrlo, 4)); - tcg_out32(s, LWZ | TAI(datahi, addrlo, 0)); + tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); + tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); + tcg_out32(s, LWBRX | TAB(datahi, h.base, TCG_REG_R0)); + } else if (h.base !=3D 0) { + tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); + tcg_out32(s, LWZX | TAB(datahi, h.base, h.index)); + tcg_out32(s, LWZX | TAB(datalo, h.base, TCG_REG_R0)); + } else if (h.index =3D=3D datahi) { + tcg_out32(s, LWZ | TAI(datalo, h.index, 4)); + tcg_out32(s, LWZ | TAI(datahi, h.index, 0)); } else { - tcg_out32(s, LWZ | TAI(datahi, addrlo, 0)); - tcg_out32(s, LWZ | TAI(datalo, addrlo, 4)); + tcg_out32(s, LWZ | TAI(datahi, h.index, 0)); + tcg_out32(s, LWZ | TAI(datalo, h.index, 4)); } } else { uint32_t insn =3D qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)]; if (!have_isa_2_06 && insn =3D=3D LDBRX) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); - tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo)); - tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0)); + tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); + tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); + tcg_out32(s, LWBRX | TAB(TCG_REG_R0, h.base, TCG_REG_R0)); tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0); } else if (insn) { - tcg_out32(s, insn | TAB(datalo, rbase, addrlo)); + tcg_out32(s, insn | TAB(datalo, h.base, h.index)); } else { insn =3D qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)]; - tcg_out32(s, insn | TAB(datalo, rbase, addrlo)); + tcg_out32(s, insn | TAB(datalo, h.base, h.index)); tcg_out_movext(s, TCG_TYPE_REG, datalo, TCG_TYPE_REG, opc & MO_SSIZE, datalo); } @@ -2365,52 +2369,52 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, { MemOp opc =3D get_memop(oi); MemOp s_bits =3D opc & MO_SIZE; - TCGReg rbase; + HostAddress h; =20 #ifdef CONFIG_SOFTMMU tcg_insn_unit *label_ptr; =20 - addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), fa= lse); + h.index =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), f= alse); + h.base =3D TCG_REG_R3; =20 /* Load a pointer into the current opcode w/conditional branch-link. */ label_ptr =3D s->code_ptr; tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); - - rbase =3D TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); } - rbase =3D guest_base ? TCG_GUEST_BASE_REG : 0; + h.base =3D guest_base ? TCG_GUEST_BASE_REG : 0; + h.index =3D addrlo; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); - addrlo =3D TCG_REG_TMP1; + h.index =3D TCG_REG_TMP1; } #endif =20 if (TCG_TARGET_REG_BITS =3D=3D 32 && s_bits =3D=3D MO_64) { if (opc & MO_BSWAP) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); - tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo)); - tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0)); - } else if (rbase !=3D 0) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); - tcg_out32(s, STWX | SAB(datahi, rbase, addrlo)); - tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0)); + tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); + tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); + tcg_out32(s, STWBRX | SAB(datahi, h.base, TCG_REG_R0)); + } else if (h.base !=3D 0) { + tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); + tcg_out32(s, STWX | SAB(datahi, h.base, h.index)); + tcg_out32(s, STWX | SAB(datalo, h.base, TCG_REG_R0)); } else { - tcg_out32(s, STW | TAI(datahi, addrlo, 0)); - tcg_out32(s, STW | TAI(datalo, addrlo, 4)); + tcg_out32(s, STW | TAI(datahi, h.index, 0)); + tcg_out32(s, STW | TAI(datalo, h.index, 4)); } } else { uint32_t insn =3D qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)]; if (!have_isa_2_06 && insn =3D=3D STDBRX) { - tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo)); - tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4)); + tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); + tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, h.index, 4)); tcg_out_shri64(s, TCG_REG_R0, datalo, 32); - tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1)); + tcg_out32(s, STWBRX | SAB(TCG_REG_R0, h.base, TCG_REG_TMP1)); } else { - tcg_out32(s, insn | SAB(datalo, rbase, addrlo)); + tcg_out32(s, insn | SAB(datalo, h.base, h.index)); } } =20 --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322034; cv=none; d=zohomail.com; s=zohoarc; b=Rvt4AObQWaPDpFKL5TPjQxEM4/JwKIAhZAFDsDw43lrDilqjXrYfNm+85/9fUESUUct8ERX9/yvkXHPwA6xFGE2q7uKNlM+FoRyzMU9lPMjPEmI49PleLDn+kavZj3FOc6pnE3r/WjIdI3ZngFpw53Tx4kn1UhAKsPR5atcPCXI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683322034; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hqgJM4jiiEYSIDdDGQtynirAlpokMCsK+dA8u2mZ2eA=; b=elGQETYN6Es9SFQHRbKdYe5LshPFKpoq3an+HrIhE2ayaENQdDJAP/AYHGep9KlqZjeuQuSyJfRfDNZUb2DBVXdqQL7fSPGRTJTqNbRB7gFC3DgqYKDhO7vnDLIevBBa29jwsaF0iQMtW/vMJ2IHf4COYN2WxbWEcP6pFtf6Sgw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683322034826825.004495644366; Fri, 5 May 2023 14:27:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vm-00018U-16; Fri, 05 May 2023 17:25:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vW-0000pT-4p for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:18 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2vN-0004Ni-9X for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:17 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-30644c18072so1555887f8f.2 for ; Fri, 05 May 2023 14:25:07 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321907; x=1685913907; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hqgJM4jiiEYSIDdDGQtynirAlpokMCsK+dA8u2mZ2eA=; b=Hn9Cmkep7eqcMP7uz0h3VwTzjVoOehD9tF6SFzx+BkJeDMS/YvqQgO/59IPwPZhawk WF/SJsfW0RX7BJ06e+xzZPMgpIa6i8l+hrHAkkldQqgBWe/8HLHgl9YxAKHiH1t01ydx m/GOIYOPA7U50kXAewdiQgsKvnOZBqSbN8hoxy2NAH+HOC1fR8lwpKYYiSquIx92qpBX 8286BVWdDugcHmiNMklwrP9i2YZrE/2KNNivEFc/lVXQi6JZcD474Ryx5ykoBJnO4f+L 0BCnaSCMrObKqNRhB6XfwSllDgNWh8183Kz4tg1PIDt6plIYbGBirpKAmqEcaxQhbdu6 Ajug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321907; x=1685913907; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hqgJM4jiiEYSIDdDGQtynirAlpokMCsK+dA8u2mZ2eA=; b=b/PkBnd0/g8KV4jgtIY50ctNJZZqo4yYkrJyShtNHOqcR4HQDp2tmybQkrMQ6ScPhs LGzjLZL6DAGPA7IH6mOJo+cjRPMN7C9K/cMEhu0tNjPeRJ5/letrZDc3Ipj65HYTE1Gi 2VfgCrWCpUYzHuqOtmhjleVl10K2qGUpzL1q/UO84BVI39dVCIzGTGUQD+J4pbxLjqnH tyGVStnPow5Nac+AWZeKrsW7zn3XfWnHx1i5UqMFhPrmdwXt/na19Bd6mFPbuBAyWr2o 2D6/fLQ5EwTgGlwBC9mIwKZ/gmMeDSKhdxCXLFbHo3S/AM/JodUafwV3AzcaDyEZA4Uj lGdw== X-Gm-Message-State: AC+VfDxL8x5p8DdY6vs4c0OdZgqzh/UspfyDC60nYA4tmqXjQHXBuPyS RKZj7M/3RTXVumYvAcgTCJknu9HMz+GkLu0fAhf7PQ== X-Google-Smtp-Source: ACHHUZ5uvZ83yUpKSZr8vgrQeGNoy2BtV4ER69F9aQobjOeAgrytNAXyFDJUprYRGZds4bEpRnLFMQ== X-Received: by 2002:adf:e852:0:b0:2f2:783f:ae4a with SMTP id d18-20020adfe852000000b002f2783fae4amr2093413wrn.32.1683321907399; Fri, 05 May 2023 14:25:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Daniel Henrique Barboza Subject: [PULL 33/42] tcg/riscv: Require TCG_TARGET_REG_BITS == 64 Date: Fri, 5 May 2023 22:24:38 +0100 Message-Id: <20230505212447.374546-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322036506100007 The port currently does not support "oversize" guests, which means riscv32 can only target 32-bit guests. We will soon be building TCG once for all guests. This implies that we can only support riscv64. Since all Linux distributions target riscv64 not riscv32, this is not much of a restriction and simplifies the code. The brcond2 and setcond2 opcodes are exclusive to 32-bit hosts, so we can and should remove the stubs. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 8 -- tcg/riscv/tcg-target.h | 22 ++-- tcg/riscv/tcg-target.c.inc | 232 +++++++++------------------------ 3 files changed, 72 insertions(+), 190 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index cf0ac4d751..d4cff673b0 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -13,18 +13,10 @@ C_O0_I1(r) C_O0_I2(LZ, L) C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) -C_O0_I3(LZ, L, L) -C_O0_I3(LZ, LZ, L) -C_O0_I4(LZ, LZ, L, L) -C_O0_I4(rZ, rZ, rZ, rZ) C_O1_I1(r, L) C_O1_I1(r, r) -C_O1_I2(r, L, L) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) C_O1_I2(r, rZ, rN) C_O1_I2(r, rZ, rZ) -C_O1_I4(r, rZ, rZ, rZ, rZ) -C_O2_I1(r, r, L) -C_O2_I2(r, r, L, L) C_O2_I4(r, r, rZ, rZ, rM, rM) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 0deb33701f..dddf2486c1 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -25,11 +25,14 @@ #ifndef RISCV_TCG_TARGET_H #define RISCV_TCG_TARGET_H =20 -#if __riscv_xlen =3D=3D 32 -# define TCG_TARGET_REG_BITS 32 -#elif __riscv_xlen =3D=3D 64 -# define TCG_TARGET_REG_BITS 64 +/* + * We don't support oversize guests. + * Since we will only build tcg once, this in turn requires a 64-bit host. + */ +#if __riscv_xlen !=3D 64 +#error "unsupported code generation mode" #endif +#define TCG_TARGET_REG_BITS 64 =20 #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 20 @@ -83,13 +86,8 @@ typedef enum { #define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL -#if TCG_TARGET_REG_BITS =3D=3D 32 -#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN -#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN -#else #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL -#endif #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 /* optional instructions */ @@ -106,8 +104,8 @@ typedef enum { #define TCG_TARGET_HAS_sub2_i32 1 #define TCG_TARGET_HAS_mulu2_i32 0 #define TCG_TARGET_HAS_muls2_i32 0 -#define TCG_TARGET_HAS_muluh_i32 (TCG_TARGET_REG_BITS =3D=3D 32) -#define TCG_TARGET_HAS_mulsh_i32 (TCG_TARGET_REG_BITS =3D=3D 32) +#define TCG_TARGET_HAS_muluh_i32 0 +#define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_ext8s_i32 1 #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 1 @@ -128,7 +126,6 @@ typedef enum { #define TCG_TARGET_HAS_setcond2 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 #define TCG_TARGET_HAS_movcond_i64 0 #define TCG_TARGET_HAS_div_i64 1 #define TCG_TARGET_HAS_rem_i64 1 @@ -165,7 +162,6 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 -#endif =20 #define TCG_TARGET_DEFAULT_MO (0) =20 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 266fe1433d..7a674ff5ce 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -137,15 +137,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKi= nd kind, int slot) #define SOFTMMU_RESERVE_REGS 0 #endif =20 - -static inline tcg_target_long sextreg(tcg_target_long val, int pos, int le= n) -{ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - return sextract32(val, pos, len); - } else { - return sextract64(val, pos, len); - } -} +#define sextreg sextract64 =20 /* test if a constant matches the constraint */ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) @@ -235,7 +227,6 @@ typedef enum { OPC_XOR =3D 0x4033, OPC_XORI =3D 0x4013, =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 OPC_ADDIW =3D 0x1b, OPC_ADDW =3D 0x3b, OPC_DIVUW =3D 0x200503b, @@ -250,23 +241,6 @@ typedef enum { OPC_SRLIW =3D 0x501b, OPC_SRLW =3D 0x503b, OPC_SUBW =3D 0x4000003b, -#else - /* Simplify code throughout by defining aliases for RV32. */ - OPC_ADDIW =3D OPC_ADDI, - OPC_ADDW =3D OPC_ADD, - OPC_DIVUW =3D OPC_DIVU, - OPC_DIVW =3D OPC_DIV, - OPC_MULW =3D OPC_MUL, - OPC_REMUW =3D OPC_REMU, - OPC_REMW =3D OPC_REM, - OPC_SLLIW =3D OPC_SLLI, - OPC_SLLW =3D OPC_SLL, - OPC_SRAIW =3D OPC_SRAI, - OPC_SRAW =3D OPC_SRA, - OPC_SRLIW =3D OPC_SRLI, - OPC_SRLW =3D OPC_SRL, - OPC_SUBW =3D OPC_SUB, -#endif =20 OPC_FENCE =3D 0x0000000f, OPC_NOP =3D OPC_ADDI, /* nop =3D addi r0,r0,0 */ @@ -500,7 +474,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, T= CGReg rd, tcg_target_long lo, hi, tmp; int shift, ret; =20 - if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I32) { + if (type =3D=3D TCG_TYPE_I32) { val =3D (int32_t)val; } =20 @@ -511,7 +485,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, T= CGReg rd, } =20 hi =3D val - lo; - if (TCG_TARGET_REG_BITS =3D=3D 32 || val =3D=3D (int32_t)val) { + if (val =3D=3D (int32_t)val) { tcg_out_opc_upper(s, OPC_LUI, rd, hi); if (lo !=3D 0) { tcg_out_opc_imm(s, OPC_ADDIW, rd, rd, lo); @@ -519,7 +493,6 @@ static void tcg_out_movi(TCGContext *s, TCGType type, T= CGReg rd, return; } =20 - /* We can only be here if TCG_TARGET_REG_BITS !=3D 32 */ tmp =3D tcg_pcrel_diff(s, (void *)val); if (tmp =3D=3D (int32_t)tmp) { tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); @@ -668,15 +641,15 @@ static void tcg_out_ldst(TCGContext *s, RISCVInsn opc= , TCGReg data, static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { - bool is32bit =3D (TCG_TARGET_REG_BITS =3D=3D 32 || type =3D=3D TCG_TYP= E_I32); - tcg_out_ldst(s, is32bit ? OPC_LW : OPC_LD, arg, arg1, arg2); + RISCVInsn insn =3D type =3D=3D TCG_TYPE_I32 ? OPC_LW : OPC_LD; + tcg_out_ldst(s, insn, arg, arg1, arg2); } =20 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { - bool is32bit =3D (TCG_TARGET_REG_BITS =3D=3D 32 || type =3D=3D TCG_TYP= E_I32); - tcg_out_ldst(s, is32bit ? OPC_SW : OPC_SD, arg, arg1, arg2); + RISCVInsn insn =3D type =3D=3D TCG_TYPE_I32 ? OPC_SW : OPC_SD; + tcg_out_ldst(s, insn, arg, arg1, arg2); } =20 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, @@ -829,20 +802,6 @@ static void tcg_out_setcond(TCGContext *s, TCGCond con= d, TCGReg ret, } } =20 -static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg= ah, - TCGReg bl, TCGReg bh, TCGLabel *l) -{ - /* todo */ - g_assert_not_reached(); -} - -static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) -{ - /* todo */ - g_assert_not_reached(); -} - static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool= tail) { TCGReg link =3D tail ? TCG_REG_ZERO : TCG_REG_RA; @@ -853,20 +812,18 @@ static void tcg_out_call_int(TCGContext *s, const tcg= _insn_unit *arg, bool tail) if (offset =3D=3D sextreg(offset, 0, 20)) { /* short jump: -2097150 to 2097152 */ tcg_out_opc_jump(s, OPC_JAL, link, offset); - } else if (TCG_TARGET_REG_BITS =3D=3D 32 || offset =3D=3D (int32_t)off= set) { + } else if (offset =3D=3D (int32_t)offset) { /* long jump: -2147483646 to 2147483648 */ tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0); tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0); ret =3D reloc_call(s->code_ptr - 2, arg); tcg_debug_assert(ret =3D=3D true); - } else if (TCG_TARGET_REG_BITS =3D=3D 64) { + } else { /* far jump: 64-bit */ tcg_target_long imm =3D sextreg((tcg_target_long)arg, 0, 12); tcg_target_long base =3D (tcg_target_long)arg - imm; tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base); tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm); - } else { - g_assert_not_reached(); } } =20 @@ -942,9 +899,6 @@ static void * const qemu_st_helpers[MO_SIZE + 1] =3D { #endif }; =20 -/* We don't support oversize guests */ -QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); - /* We expect to use a 12-bit negative offset from ENV. */ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); @@ -956,8 +910,7 @@ static void tcg_out_goto(TCGContext *s, const tcg_insn_= unit *target) tcg_debug_assert(ok); } =20 -static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrl, - TCGReg addrh, MemOpIdx oi, +static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, MemOpIdx oi, tcg_insn_unit **label_ptr, bool is_load) { MemOp opc =3D get_memop(oi); @@ -973,7 +926,7 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg ad= drl, tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs); =20 - tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addrl, + tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); @@ -992,10 +945,10 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg = addrl, /* Clear the non-page, non-alignment bits from the address. */ compare_mask =3D (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - = 1); if (compare_mask =3D=3D sextreg(compare_mask, 0, 12)) { - tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addrl, compare_mask); + tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr, compare_mask); } else { tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); - tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addrl); + tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr); } =20 /* Compare masked address with the TLB entry. */ @@ -1003,29 +956,26 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg= addrl, tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); =20 /* TLB Hit - translate address using addend. */ - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP0, addrl); - addrl =3D TCG_REG_TMP0; + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_ext32u(s, TCG_REG_TMP0, addr); + addr =3D TCG_REG_TMP0; } - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl); + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addr); return TCG_REG_TMP0; } =20 static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, - TCGType ext, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addrhi, - void *raddr, tcg_insn_unit **label_ptr) + TCGType data_type, TCGReg data_reg, + TCGReg addr_reg, void *raddr, + tcg_insn_unit **label_ptr) { TCGLabelQemuLdst *label =3D new_ldst_label(s); =20 label->is_ld =3D is_ld; label->oi =3D oi; - label->type =3D ext; - label->datalo_reg =3D datalo; - label->datahi_reg =3D datahi; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; + label->type =3D data_type; + label->datalo_reg =3D data_reg; + label->addrlo_reg =3D addr_reg; label->raddr =3D tcg_splitwx_to_rx(raddr); label->label_ptr[0] =3D label_ptr[0]; } @@ -1039,11 +989,6 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) TCGReg a2 =3D tcg_target_call_iarg_regs[2]; TCGReg a3 =3D tcg_target_call_iarg_regs[3]; =20 - /* We don't support oversize guests */ - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - g_assert_not_reached(); - } - /* resolve label address */ if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; @@ -1073,11 +1018,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) TCGReg a3 =3D tcg_target_call_iarg_regs[3]; TCGReg a4 =3D tcg_target_call_iarg_regs[4]; =20 - /* We don't support oversize guests */ - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - g_assert_not_reached(); - } - /* resolve label address */ if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; @@ -1146,7 +1086,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) =20 #endif /* CONFIG_SOFTMMU */ =20 -static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, +static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val, TCGReg base, MemOp opc, bool is_64) { /* Byte swapping is left to middle-end expansion. */ @@ -1154,37 +1094,28 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg lo, TCGReg hi, =20 switch (opc & (MO_SSIZE)) { case MO_UB: - tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); + tcg_out_opc_imm(s, OPC_LBU, val, base, 0); break; case MO_SB: - tcg_out_opc_imm(s, OPC_LB, lo, base, 0); + tcg_out_opc_imm(s, OPC_LB, val, base, 0); break; case MO_UW: - tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); + tcg_out_opc_imm(s, OPC_LHU, val, base, 0); break; case MO_SW: - tcg_out_opc_imm(s, OPC_LH, lo, base, 0); + tcg_out_opc_imm(s, OPC_LH, val, base, 0); break; case MO_UL: - if (TCG_TARGET_REG_BITS =3D=3D 64 && is_64) { - tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); + if (is_64) { + tcg_out_opc_imm(s, OPC_LWU, val, base, 0); break; } /* FALLTHRU */ case MO_SL: - tcg_out_opc_imm(s, OPC_LW, lo, base, 0); + tcg_out_opc_imm(s, OPC_LW, val, base, 0); break; case MO_UQ: - /* Prefer to load from offset 0 first, but allow for overlap. */ - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_opc_imm(s, OPC_LD, lo, base, 0); - } else if (lo !=3D base) { - tcg_out_opc_imm(s, OPC_LW, lo, base, 0); - tcg_out_opc_imm(s, OPC_LW, hi, base, 4); - } else { - tcg_out_opc_imm(s, OPC_LW, hi, base, 4); - tcg_out_opc_imm(s, OPC_LW, lo, base, 0); - } + tcg_out_opc_imm(s, OPC_LD, val, base, 0); break; default: g_assert_not_reached(); @@ -1193,8 +1124,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, =20 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) { - TCGReg addr_regl, addr_regh __attribute__((unused)); - TCGReg data_regl, data_regh; + TCGReg addr_reg, data_reg; MemOpIdx oi; MemOp opc; #if defined(CONFIG_SOFTMMU) @@ -1204,27 +1134,23 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is_64) #endif TCGReg base; =20 - data_regl =3D *args++; - data_regh =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); - addr_regl =3D *args++; - addr_regh =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); + data_reg =3D *args++; + addr_reg =3D *args++; oi =3D *args++; opc =3D get_memop(oi); =20 #if defined(CONFIG_SOFTMMU) - base =3D tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1); - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); - add_qemu_ldst_label(s, 1, oi, - (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_regl, data_regh, addr_regl, addr_regh, - s->code_ptr, label_ptr); + base =3D tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1); + tcg_out_qemu_ld_direct(s, data_reg, base, opc, is_64); + add_qemu_ldst_label(s, 1, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), + data_reg, addr_reg, s->code_ptr, label_ptr); #else a_bits =3D get_alignment_bits(opc); if (a_bits) { - tcg_out_test_alignment(s, true, addr_regl, a_bits); + tcg_out_test_alignment(s, true, addr_reg, a_bits); } - base =3D addr_regl; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + base =3D addr_reg; + if (TARGET_LONG_BITS =3D=3D 32) { tcg_out_ext32u(s, TCG_REG_TMP0, base); base =3D TCG_REG_TMP0; } @@ -1232,11 +1158,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is_64) tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base= ); base =3D TCG_REG_TMP0; } - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + tcg_out_qemu_ld_direct(s, data_reg, base, opc, is_64); #endif } =20 -static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, +static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg val, TCGReg base, MemOp opc) { /* Byte swapping is left to middle-end expansion. */ @@ -1244,21 +1170,16 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg lo, TCGReg hi, =20 switch (opc & (MO_SSIZE)) { case MO_8: - tcg_out_opc_store(s, OPC_SB, base, lo, 0); + tcg_out_opc_store(s, OPC_SB, base, val, 0); break; case MO_16: - tcg_out_opc_store(s, OPC_SH, base, lo, 0); + tcg_out_opc_store(s, OPC_SH, base, val, 0); break; case MO_32: - tcg_out_opc_store(s, OPC_SW, base, lo, 0); + tcg_out_opc_store(s, OPC_SW, base, val, 0); break; case MO_64: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_opc_store(s, OPC_SD, base, lo, 0); - } else { - tcg_out_opc_store(s, OPC_SW, base, lo, 0); - tcg_out_opc_store(s, OPC_SW, base, hi, 4); - } + tcg_out_opc_store(s, OPC_SD, base, val, 0); break; default: g_assert_not_reached(); @@ -1267,8 +1188,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, =20 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) { - TCGReg addr_regl, addr_regh __attribute__((unused)); - TCGReg data_regl, data_regh; + TCGReg addr_reg, data_reg; MemOpIdx oi; MemOp opc; #if defined(CONFIG_SOFTMMU) @@ -1278,27 +1198,23 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg *args, bool is_64) #endif TCGReg base; =20 - data_regl =3D *args++; - data_regh =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); - addr_regl =3D *args++; - addr_regh =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); + data_reg =3D *args++; + addr_reg =3D *args++; oi =3D *args++; opc =3D get_memop(oi); =20 #if defined(CONFIG_SOFTMMU) - base =3D tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0); - tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); - add_qemu_ldst_label(s, 0, oi, - (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_regl, data_regh, addr_regl, addr_regh, - s->code_ptr, label_ptr); + base =3D tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0); + tcg_out_qemu_st_direct(s, data_reg, base, opc); + add_qemu_ldst_label(s, 0, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), + data_reg, addr_reg, s->code_ptr, label_ptr); #else a_bits =3D get_alignment_bits(opc); if (a_bits) { - tcg_out_test_alignment(s, false, addr_regl, a_bits); + tcg_out_test_alignment(s, false, addr_reg, a_bits); } - base =3D addr_regl; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + base =3D addr_reg; + if (TARGET_LONG_BITS =3D=3D 32) { tcg_out_ext32u(s, TCG_REG_TMP0, base); base =3D TCG_REG_TMP0; } @@ -1306,7 +1222,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base= ); base =3D TCG_REG_TMP0; } - tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + tcg_out_qemu_st_direct(s, data_reg, base, opc); #endif } =20 @@ -1585,17 +1501,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_brcond_i64: tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); break; - case INDEX_op_brcond2_i32: - tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]= )); - break; =20 case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: tcg_out_setcond(s, args[3], a0, a1, a2); break; - case INDEX_op_setcond2_i32: - tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); - break; =20 case INDEX_op_qemu_ld_i32: tcg_out_qemu_ld(s, args, false); @@ -1748,26 +1658,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) case INDEX_op_sub2_i64: return C_O2_I4(r, r, rZ, rZ, rM, rM); =20 - case INDEX_op_brcond2_i32: - return C_O0_I4(rZ, rZ, rZ, rZ); - - case INDEX_op_setcond2_i32: - return C_O1_I4(r, rZ, rZ, rZ, rZ); - case INDEX_op_qemu_ld_i32: - return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS - ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); - case INDEX_op_qemu_st_i32: - return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS - ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L)); case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O2_I1(r, r,= L) - : C_O2_I2(r, r, L, L)); + return C_O1_I1(r, L); + case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(LZ, L) - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O0_I3(LZ, L= Z, L) - : C_O0_I4(LZ, LZ, L, L)); + return C_O0_I2(LZ, L); =20 default: g_assert_not_reached(); @@ -1843,9 +1739,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) static void tcg_target_init(TCGContext *s) { tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffff; - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffff; - } + tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffff; =20 tcg_target_call_clobber_regs =3D -1u; tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683321991; cv=none; d=zohomail.com; s=zohoarc; b=bxHvHw+ZDKYncf9eXIsM8vOw5r5It1cZWwci/2X7UVwb6ehc0kJbndpLzesA4KVZxrk11Yh5dX0YUcGsbon0tHyepo1Uln24YvgbQEZfMmDLWTFaJukdvg7MOVGpR/tMgY81gMyXVHXmVN0gpbMyd7+DrHCa+8EpjqvRIM66Qbk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683321991; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JJxFOupgqcim/2LBci4akZwRhrdPcb3HeKNOODAh8Zc=; b=TrG/53YsWgPCcDWh4n6lQRtK4MWerlozA8VZ1SqjMEvq3Z3BppoYweOzm7GNmsIa3gAU7sTshOIlAGMBjkcdj5iwmrSLqDvjJpGrXlE9onw2RQ+Qto0Z5SK2OeWh2ZvjZGo4hom15GU434W0Btfere98tcfJv1AXkJwS3XI3ZJc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683321991036878.8889873372528; Fri, 5 May 2023 14:26:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vX-0000q2-Do; Fri, 05 May 2023 17:25:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vU-0000o2-U9 for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:16 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2vN-0004fB-9k for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:16 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-3f415a9015bso3039355e9.2 for ; Fri, 05 May 2023 14:25:08 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321908; x=1685913908; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JJxFOupgqcim/2LBci4akZwRhrdPcb3HeKNOODAh8Zc=; b=Y4hyb2jTAechR5AjeQC8iE8o5K2DTu7jdbaZpRb74ZdIVk9RdF53GP2o4PdawrUt8r 1EcLKBpxg1Lw+6JYAHilQ701Wl0D2wqpn9/A4sNcngWi6wwRSVRfl5OgH9PoZ25gVvyU aIAeZ4Dte5V2E63bbXqBXpDBxeDYHntlyDNEg3QHC8INcX0TZNKo5rsVjrKdIhSqBJO4 BI7XFapPHEA/lqEV8WRh1TtVm5O7bcJm6uCNCCsFSyUIKHO+Qm/pJHTIypTdDp+o2WOW rnaVMpEn5G4+O1aPLmliN9Ct+d1GBvV4lrv9TC6sWgWmbtVSla/Z+YeggB5fX/zBMXjm Urcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321908; x=1685913908; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JJxFOupgqcim/2LBci4akZwRhrdPcb3HeKNOODAh8Zc=; b=NvQYhZhAV9HXZg1OFeCvU3aud5wXKtCEmT4H6DaC5VdAQgB/YgE77iAJgbmvlDQpOf /7fKYxHKxobNX+/iUVjrJN7aRuoSONRTZ9/hca2ENMVTcQwIMPQr/LHiTQ3yIFmYt5ac kaXCJ5zPFkRlf2vcNM/eyxgzKdmXoU0BrlsY+5cCQQEn8v2giPuZJb5ujhDyXPZoGTWS ov/GYJ2MqZcZWZvF2FjzjBFpGipy5rWF8skYCaBuU++gkHo7SUkGns4SzJm3nKvvbMl9 9lFdW7KOZs/jqVSCQOMOw0H8S+ib8CxA56wXN6Q/MxqN2S6HadRw6IZARNaNcehaN8WP yyUg== X-Gm-Message-State: AC+VfDxK4oZRSqiD5eVdaqOsIFRcIiY0KCgx4txDKcaPFpVx5DCSss4I S8u7biXdiKocfAGP1/DYLaelmWwe9X3nR4epkWMjvA== X-Google-Smtp-Source: ACHHUZ7oPnuz7ebKtpu1mt++EOVrRU5KvssqLSmx5Vz1eY8GPSRn1G59QpBoCS3jt9XUcgQaaUROag== X-Received: by 2002:a7b:c5c3:0:b0:3f3:2ba9:94e1 with SMTP id n3-20020a7bc5c3000000b003f32ba994e1mr2118353wmk.25.1683321907965; Fri, 05 May 2023 14:25:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Daniel Henrique Barboza Subject: [PULL 34/42] tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st} Date: Fri, 5 May 2023 22:24:39 +0100 Message-Id: <20230505212447.374546-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683321992670100009 Interpret the variable argument placement in the caller. Pass data_type instead of is64 -- there are several places where we already convert back from bool to type. Clean things up by using type throughout. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 66 ++++++++++++++------------------------ 1 file changed, 24 insertions(+), 42 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 7a674ff5ce..a4cf60ca75 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1087,7 +1087,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) #endif /* CONFIG_SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val, - TCGReg base, MemOp opc, bool is_64) + TCGReg base, MemOp opc, TCGType type) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); @@ -1106,7 +1106,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg val, tcg_out_opc_imm(s, OPC_LH, val, base, 0); break; case MO_UL: - if (is_64) { + if (type =3D=3D TCG_TYPE_I64) { tcg_out_opc_imm(s, OPC_LWU, val, base, 0); break; } @@ -1122,30 +1122,21 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg val, } } =20 -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, + MemOpIdx oi, TCGType data_type) { - TCGReg addr_reg, data_reg; - MemOpIdx oi; - MemOp opc; -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[1]; -#else - unsigned a_bits; -#endif + MemOp opc =3D get_memop(oi); TCGReg base; =20 - data_reg =3D *args++; - addr_reg =3D *args++; - oi =3D *args++; - opc =3D get_memop(oi); - #if defined(CONFIG_SOFTMMU) + tcg_insn_unit *label_ptr[1]; + base =3D tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1); - tcg_out_qemu_ld_direct(s, data_reg, base, opc, is_64); - add_qemu_ldst_label(s, 1, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_reg, addr_reg, s->code_ptr, label_ptr); + tcg_out_qemu_ld_direct(s, data_reg, base, opc, data_type); + add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, + s->code_ptr, label_ptr); #else - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addr_reg, a_bits); } @@ -1158,7 +1149,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base= ); base =3D TCG_REG_TMP0; } - tcg_out_qemu_ld_direct(s, data_reg, base, opc, is_64); + tcg_out_qemu_ld_direct(s, data_reg, base, opc, data_type); #endif } =20 @@ -1186,30 +1177,21 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg val, } } =20 -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, + MemOpIdx oi, TCGType data_type) { - TCGReg addr_reg, data_reg; - MemOpIdx oi; - MemOp opc; -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[1]; -#else - unsigned a_bits; -#endif + MemOp opc =3D get_memop(oi); TCGReg base; =20 - data_reg =3D *args++; - addr_reg =3D *args++; - oi =3D *args++; - opc =3D get_memop(oi); - #if defined(CONFIG_SOFTMMU) + tcg_insn_unit *label_ptr[1]; + base =3D tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0); tcg_out_qemu_st_direct(s, data_reg, base, opc); - add_qemu_ldst_label(s, 0, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_reg, addr_reg, s->code_ptr, label_ptr); + add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, + s->code_ptr, label_ptr); #else - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, false, addr_reg, a_bits); } @@ -1508,16 +1490,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, false); + tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, true); + tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); break; case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, false); + tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, true); + tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); break; =20 case INDEX_op_extrh_i64_i32: --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322035; cv=none; d=zohomail.com; s=zohoarc; b=NuyvtuO3C0i+LEdQhOnwPKHETkofyQOv6LLH+xaj9VZtR2I0DbCF1p83TYXvsifI0Cn1uX7ZmZETNxBvw5EQf40N2GyqhL9i6aZs+tPkIHlCHHFh3JgnIr5xe/vufvY6/CqLnke+j2bc61ZdRF9tUVSuo/gVcaM/Rv/1x6/ovcI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683322035; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=h+hQGAfxVGFgcw51jDi1fjFbmaS4u/aJWSe3Wo6FlWM=; b=NFnQTBwmGbLCmhu41VUojOXyeqoMM6F+wfwyBd+Ist6r9xPOj7vT9gbJs10BiJjnwv1lVmvDWi07FCqf0tXOb73mpLTdSre16atgoeQYR3IeH/Gs78TfrD042/nLOlDG5oJYOyWBigseF4V6SEFuVznRwIf3ZGZm6d1JVnu2rQI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683322035704493.50777538562033; Fri, 5 May 2023 14:27:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2va-0000rm-NT; Fri, 05 May 2023 17:25:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vW-0000pg-RA for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:18 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2vN-0004fL-Tm for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:18 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-2f9b9aa9d75so1537732f8f.0 for ; Fri, 05 May 2023 14:25:09 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321908; x=1685913908; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h+hQGAfxVGFgcw51jDi1fjFbmaS4u/aJWSe3Wo6FlWM=; b=vBEkUKD0FyLWal8CfY05BLNWBzt5lhP5YAWEGlXLanN24eBfW7O3D8LvzNP3aozre4 yGWc7yn9Dnl/y6gurVo1wn+kZzrATxnssZD6MRM4uW2Kd2KZHZ4HCC8R9CX5zzZkBlvg 3Nic/YfilOuppAoToqTNDyEiKdUameRebGtj+ie5NXyhez+pl9YKSK7VILcqE7KtdNNx 9+C2i8RLHLAGr23fjX8sIjwcM3+A8qDoIm1y/bUe7W20iBr+T6AZKYZIBsKR/xvVVBUG nTauO4cTNyB/LZ4qrQYG0sF69K4/lbw+0JAa1P8q3z/lXNZBnuN9lOe5690FW4a0RcYj 2qKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321908; x=1685913908; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h+hQGAfxVGFgcw51jDi1fjFbmaS4u/aJWSe3Wo6FlWM=; b=WWobypYl5aTVHN1slIqifO6v1MLFCVxEGfGvkdLcAc0wAKreP6+ghhHulTnPwo8pzK DCl51Lp1xJZu5RZMCpa1Oc9BUnkVpIJn8MQkisgTh/PYY/uw2B7R1zGKNaO+jGDWkM2o ms7TYjyMLNgF7yjQM1bRcOQZmooYcfpXrMo8I7tlnM2UCKXTsiytrTTkVCyzDiGuPzh0 WACML+rYPbB/eX3H0WClXz3Ltsvmp+o66BnU+KHoCvrz5cIGM2743m9+CpYDypa0VhvW HSvzOWnAxiLlCEL5FuMVBPAWJ2fPpT6HAocksQosHxO8LMoR41auc0I9gqDIunv+f0xP tFzw== X-Gm-Message-State: AC+VfDznk42Fiz8WbQgmeOloF+H5LBXJZQyX2ZnYRNcTCDDlZftauu/n 36+VW4Jxs+VSgcbNVgnXXw/rljIVgL/5o0Rbl6fzNw== X-Google-Smtp-Source: ACHHUZ74kXZKnJZKMS1s2fPKH4zcV0AHr+fmyNLlMsjpBcF1J/U9jhmufrMtHE4hd1xq7G29Xgci7w== X-Received: by 2002:a5d:4b91:0:b0:2ef:b19f:b24c with SMTP id b17-20020a5d4b91000000b002efb19fb24cmr2464846wrt.0.1683321908592; Fri, 05 May 2023 14:25:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 35/42] tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st} Date: Fri, 5 May 2023 22:24:40 +0100 Message-Id: <20230505212447.374546-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322035959100005 We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index b399798664..e931f0cde4 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1770,13 +1770,14 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addr_reg, MemOp opc, } =20 static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, - TCGReg data, TCGReg addr, + TCGType type, TCGReg data, TCGReg addr, tcg_insn_unit *raddr, tcg_insn_unit *label= _ptr) { TCGLabelQemuLdst *label =3D new_ldst_label(s); =20 label->is_ld =3D is_ld; label->oi =3D oi; + label->type =3D type; label->datalo_reg =3D data; label->addrlo_reg =3D addr; label->raddr =3D tcg_splitwx_to_rx(raddr); @@ -1900,7 +1901,7 @@ static void tcg_prepare_user_ldst(TCGContext *s, TCGR= eg *addr_reg, #endif /* CONFIG_SOFTMMU */ =20 static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_re= g, - MemOpIdx oi) + MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); #ifdef CONFIG_SOFTMMU @@ -1916,7 +1917,8 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg dat= a_reg, TCGReg addr_reg, =20 tcg_out_qemu_ld_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0); =20 - add_qemu_ldst_label(s, 1, oi, data_reg, addr_reg, s->code_ptr, label_p= tr); + add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, + s->code_ptr, label_ptr); #else TCGReg index_reg; tcg_target_long disp; @@ -1931,7 +1933,7 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg dat= a_reg, TCGReg addr_reg, } =20 static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_re= g, - MemOpIdx oi) + MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); #ifdef CONFIG_SOFTMMU @@ -1947,7 +1949,8 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg dat= a_reg, TCGReg addr_reg, =20 tcg_out_qemu_st_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0); =20 - add_qemu_ldst_label(s, 0, oi, data_reg, addr_reg, s->code_ptr, label_p= tr); + add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, + s->code_ptr, label_ptr); #else TCGReg index_reg; tcg_target_long disp; @@ -2307,13 +2310,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, break; =20 case INDEX_op_qemu_ld_i32: - /* ??? Technically we can use a non-extending instruction. */ + tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I32); + break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args[0], args[1], args[2]); + tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I64); break; case INDEX_op_qemu_st_i32: + tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I32); + break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args[0], args[1], args[2]); + tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I64); break; =20 case INDEX_op_ld16s_i64: --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322170; cv=none; d=zohomail.com; s=zohoarc; b=h0WFWc3G77XYurl0tDlDJz/dBO+U6KLylCR46ro3I482Ozu9i0XRvbrGhOt/P47rW89WAGkoabR6HFQewlOj6DW+yoB3M7QFih8dVLE9wT1UmQB/HWnUU9aCdy7pwPFQUwo/X5QN6T6T3LqT2Wzo19TarEU5Ojz4/w1UqIc4oOg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683322170; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wieZHyAasr1N3tLh9UlWK+BlLvLaFAxyqWZefWKXIaw=; b=G0DZI40FoQjzeGub9ZBxgctB/17UxJ91hsopvU8V4SENpQDU0JmiQwtl3nKrsVzTdZlagJkxldWKd4n4VPTLXRP3yacb4id9KP00oZpzEf/gurDmAAvKb4v+2ahsdxHuMIC0UP5hZcmcWCTUAgfKdGpg4MRftkEaFEwo8Nkptd8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683322170849275.44233976751684; Fri, 5 May 2023 14:29:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vt-0001Oz-1P; Fri, 05 May 2023 17:25:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vW-0000ph-Rm for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:19 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2vO-0004ff-F4 for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:18 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-3f192c23fffso15660245e9.3 for ; Fri, 05 May 2023 14:25:10 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321909; x=1685913909; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wieZHyAasr1N3tLh9UlWK+BlLvLaFAxyqWZefWKXIaw=; b=uh4uEyVAuJ15wvRvZlhKswVhqfs/5TJ4qOPDwC+GavFrMDtbCxGwGhlUERseWrxxdl wXtiBBxaaFQOO+n1nwBv14vj60lXuRLXW2FbpwMTlE2gFh45ihDopRHPtBs2EtN6gv+k UgAvCTS2LIq2Whfgfkc3XicqJvRwpUo5Kq1653Nl9JsAGCQ0auoMkvVKui2ffnWTJCpO uWDO3HoGg/mJ746axY9sbQjMmPHBueyuBP3mXhuP5hJcEFtJeMLT84ou7+oBWmvbhtr/ G9yAxKQ4vRHy/i7aJKmWx1jxsuaXGHs40mVqd4JcE2NpwlELRTbSGa7L4Om9jiIeqgcc bSLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321909; x=1685913909; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wieZHyAasr1N3tLh9UlWK+BlLvLaFAxyqWZefWKXIaw=; b=WvsghxPFWojNY0n7P77fx90Irb+uA1pujyJJYz7Y5z49OqTv4KTihh9lPKTkDMb3Q6 i223Etl5SaoMtsZacJvaJ+3GTc667buSQhMTOvRTkGvCow7siV2KgXpO1ujv0pgqo+X1 tB8fKHcCHnm0M6u+VBJsjIAz8cqeT0O4gVBWRZB4BrrMpELF43JVBVY9xA2Zv4B+cJEb 6etWaK+BxRK7KvqPRnkra9EIA3ero7YUpNTecJIQjTAhPi4p1PsGaHkwcUOxf7DlB5Pi Oa1QgMC4pvWa2f3AWTMd5HZzI4bo0XKbHC8laB3lKJIx3ONo411yvXQAPd0WhbNsvoyo Mcew== X-Gm-Message-State: AC+VfDxUw1f8Vk/pSCC8l3mrOYwW4ZMCDDQdgY7ImWksfK/Ts0jxHOkb k6P6ldDsE7lnZYQm8Vj49aKbzJNiol9g1nSZxlW4pg== X-Google-Smtp-Source: ACHHUZ44BouEF53U9n10Y1sf6bRBpk+99XhZRetUOav3WLWZVlufKqgeb3uL856D1szo5Q8Xxfpxsg== X-Received: by 2002:a5d:4b4b:0:b0:306:2cf5:79d7 with SMTP id w11-20020a5d4b4b000000b003062cf579d7mr2277179wrs.17.1683321909170; Fri, 05 May 2023 14:25:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 36/42] tcg/s390x: Introduce HostAddress Date: Fri, 5 May 2023 22:24:41 +0100 Message-Id: <20230505212447.374546-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322171702100001 Collect the 3 potential parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st}_direct to use it. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 109 ++++++++++++++++++++----------------- 1 file changed, 60 insertions(+), 49 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index e931f0cde4..da7ee5b085 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1606,58 +1606,64 @@ static void tcg_out_call(TCGContext *s, const tcg_i= nsn_unit *dest, tcg_out_call_int(s, dest); } =20 +typedef struct { + TCGReg base; + TCGReg index; + int disp; +} HostAddress; + static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data, - TCGReg base, TCGReg index, int disp) + HostAddress h) { switch (opc & (MO_SSIZE | MO_BSWAP)) { case MO_UB: - tcg_out_insn(s, RXY, LLGC, data, base, index, disp); + tcg_out_insn(s, RXY, LLGC, data, h.base, h.index, h.disp); break; case MO_SB: - tcg_out_insn(s, RXY, LGB, data, base, index, disp); + tcg_out_insn(s, RXY, LGB, data, h.base, h.index, h.disp); break; =20 case MO_UW | MO_BSWAP: /* swapped unsigned halfword load with upper bits zeroed */ - tcg_out_insn(s, RXY, LRVH, data, base, index, disp); + tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp); tcg_out_ext16u(s, data, data); break; case MO_UW: - tcg_out_insn(s, RXY, LLGH, data, base, index, disp); + tcg_out_insn(s, RXY, LLGH, data, h.base, h.index, h.disp); break; =20 case MO_SW | MO_BSWAP: /* swapped sign-extended halfword load */ - tcg_out_insn(s, RXY, LRVH, data, base, index, disp); + tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp); tcg_out_ext16s(s, TCG_TYPE_REG, data, data); break; case MO_SW: - tcg_out_insn(s, RXY, LGH, data, base, index, disp); + tcg_out_insn(s, RXY, LGH, data, h.base, h.index, h.disp); break; =20 case MO_UL | MO_BSWAP: /* swapped unsigned int load with upper bits zeroed */ - tcg_out_insn(s, RXY, LRV, data, base, index, disp); + tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp); tcg_out_ext32u(s, data, data); break; case MO_UL: - tcg_out_insn(s, RXY, LLGF, data, base, index, disp); + tcg_out_insn(s, RXY, LLGF, data, h.base, h.index, h.disp); break; =20 case MO_SL | MO_BSWAP: /* swapped sign-extended int load */ - tcg_out_insn(s, RXY, LRV, data, base, index, disp); + tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp); tcg_out_ext32s(s, data, data); break; case MO_SL: - tcg_out_insn(s, RXY, LGF, data, base, index, disp); + tcg_out_insn(s, RXY, LGF, data, h.base, h.index, h.disp); break; =20 case MO_UQ | MO_BSWAP: - tcg_out_insn(s, RXY, LRVG, data, base, index, disp); + tcg_out_insn(s, RXY, LRVG, data, h.base, h.index, h.disp); break; case MO_UQ: - tcg_out_insn(s, RXY, LG, data, base, index, disp); + tcg_out_insn(s, RXY, LG, data, h.base, h.index, h.disp); break; =20 default: @@ -1666,44 +1672,44 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, M= emOp opc, TCGReg data, } =20 static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data, - TCGReg base, TCGReg index, int disp) + HostAddress h) { switch (opc & (MO_SIZE | MO_BSWAP)) { case MO_UB: - if (disp >=3D 0 && disp < 0x1000) { - tcg_out_insn(s, RX, STC, data, base, index, disp); + if (h.disp >=3D 0 && h.disp < 0x1000) { + tcg_out_insn(s, RX, STC, data, h.base, h.index, h.disp); } else { - tcg_out_insn(s, RXY, STCY, data, base, index, disp); + tcg_out_insn(s, RXY, STCY, data, h.base, h.index, h.disp); } break; =20 case MO_UW | MO_BSWAP: - tcg_out_insn(s, RXY, STRVH, data, base, index, disp); + tcg_out_insn(s, RXY, STRVH, data, h.base, h.index, h.disp); break; case MO_UW: - if (disp >=3D 0 && disp < 0x1000) { - tcg_out_insn(s, RX, STH, data, base, index, disp); + if (h.disp >=3D 0 && h.disp < 0x1000) { + tcg_out_insn(s, RX, STH, data, h.base, h.index, h.disp); } else { - tcg_out_insn(s, RXY, STHY, data, base, index, disp); + tcg_out_insn(s, RXY, STHY, data, h.base, h.index, h.disp); } break; =20 case MO_UL | MO_BSWAP: - tcg_out_insn(s, RXY, STRV, data, base, index, disp); + tcg_out_insn(s, RXY, STRV, data, h.base, h.index, h.disp); break; case MO_UL: - if (disp >=3D 0 && disp < 0x1000) { - tcg_out_insn(s, RX, ST, data, base, index, disp); + if (h.disp >=3D 0 && h.disp < 0x1000) { + tcg_out_insn(s, RX, ST, data, h.base, h.index, h.disp); } else { - tcg_out_insn(s, RXY, STY, data, base, index, disp); + tcg_out_insn(s, RXY, STY, data, h.base, h.index, h.disp); } break; =20 case MO_UQ | MO_BSWAP: - tcg_out_insn(s, RXY, STRVG, data, base, index, disp); + tcg_out_insn(s, RXY, STRVG, data, h.base, h.index, h.disp); break; case MO_UQ: - tcg_out_insn(s, RXY, STG, data, base, index, disp); + tcg_out_insn(s, RXY, STG, data, h.base, h.index, h.disp); break; =20 default: @@ -1883,20 +1889,23 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) return tcg_out_fail_alignment(s, l); } =20 -static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg, - TCGReg *index_reg, tcg_target_long *disp) +static HostAddress tcg_prepare_user_ldst(TCGContext *s, TCGReg addr_reg) { + TCGReg index; + int disp; + if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_TMP0, *addr_reg); - *addr_reg =3D TCG_TMP0; + tcg_out_ext32u(s, TCG_TMP0, addr_reg); + addr_reg =3D TCG_TMP0; } if (guest_base < 0x80000) { - *index_reg =3D TCG_REG_NONE; - *disp =3D guest_base; + index =3D TCG_REG_NONE; + disp =3D guest_base; } else { - *index_reg =3D TCG_GUEST_BASE_REG; - *disp =3D 0; + index =3D TCG_GUEST_BASE_REG; + disp =3D 0; } + return (HostAddress){ .base =3D addr_reg, .index =3D index, .disp =3D = disp }; } #endif /* CONFIG_SOFTMMU */ =20 @@ -1904,31 +1913,32 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg d= ata_reg, TCGReg addr_reg, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); + HostAddress h; + #ifdef CONFIG_SOFTMMU unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; - TCGReg base_reg; =20 - base_reg =3D tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1); + h.base =3D tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1); + h.index =3D TCG_REG_R2; + h.disp =3D 0; =20 tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); label_ptr =3D s->code_ptr; s->code_ptr +=3D 1; =20 - tcg_out_qemu_ld_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0); + tcg_out_qemu_ld_direct(s, opc, data_reg, h); =20 add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, s->code_ptr, label_ptr); #else - TCGReg index_reg; - tcg_target_long disp; unsigned a_bits =3D get_alignment_bits(opc); =20 if (a_bits) { tcg_out_test_alignment(s, true, addr_reg, a_bits); } - tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp); - tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, index_reg, disp); + h =3D tcg_prepare_user_ldst(s, addr_reg); + tcg_out_qemu_ld_direct(s, opc, data_reg, h); #endif } =20 @@ -1936,31 +1946,32 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg d= ata_reg, TCGReg addr_reg, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); + HostAddress h; + #ifdef CONFIG_SOFTMMU unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; - TCGReg base_reg; =20 - base_reg =3D tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0); + h.base =3D tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0); + h.index =3D TCG_REG_R2; + h.disp =3D 0; =20 tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); label_ptr =3D s->code_ptr; s->code_ptr +=3D 1; =20 - tcg_out_qemu_st_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0); + tcg_out_qemu_st_direct(s, opc, data_reg, h); =20 add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, s->code_ptr, label_ptr); #else - TCGReg index_reg; - tcg_target_long disp; unsigned a_bits =3D get_alignment_bits(opc); =20 if (a_bits) { tcg_out_test_alignment(s, false, addr_reg, a_bits); } - tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp); - tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, index_reg, disp); + h =3D tcg_prepare_user_ldst(s, addr_reg); + tcg_out_qemu_st_direct(s, opc, data_reg, h); #endif } =20 --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322081; cv=none; d=zohomail.com; s=zohoarc; b=hskZqr1+tZkU6wi0R3NVxdBSkA6noBB0XGUD0Vy/x5a0nK8T3P9E2l8WXt6gVXZbM8CE16kW++CRu805BQeZBOMIHIZ1FkVECkRmA0Zhs4eOtQx7rUx8HY/GK1XKkYwIcXdGHcmRwAmcESZDEtvNiVQBflq9G/lYBjJ/Hb3ELpU= ARC-Message-Signature: i=1; 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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321909; x=1685913909; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ePGQgjAgeqBpbV0KhHIgImg7evASXxc6+J4X6wS7qUw=; b=PoJFVQmNC4JODmzmFFJcuuY9BoF2sBO0MY4msxPJWJsLpHwEj8inGAdm3uqcZS0wvD pj+MgPjUwr/RrXKD3jweYq2tQngH/8PQtvqeoKCoRco6iEkaescFYjjAZzcYEpQ3oHia wOXSLkie7RtM5DvZYACKUR2k/9a7i0FOdSY02hfNECl9+LXTCH4EBeKS4nUqjH85igm7 Gb/qXJuuw+vKzD5zynNJRWjmcAPFQ8xGf1V/wR8U1dLFutwsBiE9O5upyCwsicLRWan+ CaaZGhmPBCxQRtMf2BZtsFpX2oEi0E3/FYXyPbF4WgA4Z0YPHbEUfZNb+4ATyM3iJ6rJ Cjiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321909; x=1685913909; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ePGQgjAgeqBpbV0KhHIgImg7evASXxc6+J4X6wS7qUw=; b=XQK9zSem0kWNglDiUALXQII1h9HSrF874OEQuH8BznyU2U0fbc/dbNUOS9PIQ9jA2Y IRPayB6d4fHkoDkO+ulZLRfd3wISIu5gUjpOAVdsyUIzaQGvFZhhSTCu0X7N3NFQTXpp HoUVxR89oK3vJuWILZKq/UdqB/CWsu6tsXLFPvIicmwOwWUxxxVdk4Qh8zDi8KmHQCTL o5enuHIxTrdvlyN5maJvgQN9PaPdNRj0sxOTVJpZ0fsxcKsB5uR3Wp/qgkr4zX4up+91 Bd5CkqSVklbjtE/9QcgennWXF8uv2DQ86vBlR3T8S5wBhydyjyjX4ohL2CHDZSSoHHv7 dl9A== X-Gm-Message-State: AC+VfDz7lO0QdqTIJIphplRpep5SlqTgLR1tCKa5AzWiZYt+uARt8Zc3 fx2OkstorShJPp2Gdh4E3fhFKM2Eetjzfo3rPJyA4Q== X-Google-Smtp-Source: ACHHUZ5BPRQA+pcRxu8KoxXh+7H4tzKb0QoRc3njipk/kngjt7hAV34uWMisV4LsxesmSQY08dGEhg== X-Received: by 2002:adf:fcc7:0:b0:2fa:36db:8060 with SMTP id f7-20020adffcc7000000b002fa36db8060mr2267977wrs.60.1683321909631; Fri, 05 May 2023 14:25:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 37/42] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return Date: Fri, 5 May 2023 22:24:42 +0100 Message-Id: <20230505212447.374546-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322083333100003 In tcg_canonicalize_memop, we remove MO_SIGN from MO_32 operations with TCG_TYPE_I32. Thus this is never set. We already have an identical test just above which does not include is_64 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 4f477d539c..dbe4bf96b9 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1220,7 +1220,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a, TCGReg addr, tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_O2, oi); =20 /* We let the helper sign-extend SB and SW, but leave SL for here. */ - if (is_64 && (memop & MO_SSIZE) =3D=3D MO_SL) { + if ((memop & MO_SSIZE) =3D=3D MO_SL) { tcg_out_ext32s(s, data, TCG_REG_O0); } else { tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0); --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322105; cv=none; d=zohomail.com; s=zohoarc; b=j+MfmkYXYMQ/xdH/7we3+kliff+gzCAcDIO3Y6N8BA2T9WJCRa8jZVBSfoiNL1JeHTUJwadzSOXkFpLjQHQzyXCWDvQ+uHJyclmXNZcHFL0BF5y470GtpQBkQPbHROaIvJ88hemj3vvyuMoPLhJPiDkn+F7vs6BjekHUKHowz4k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683322105; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Bq2h9X5UNDb637fCQb6pFT3eLaF1A8JaUegXUakX2qE=; b=LWE7zQjb/Rk173No+FcYNqIL6zfGm6Ca8/CSYLmLYQd2wKLqemfqvTekcEFiNF1nJM9B6q11PRqOieqKVcI1RT1/8vEip2dA3O08PBoUlvmWgsG36+TCTai3/TZi61yQynjR/p77ptLEh5y1IrRgxBNC+XDa8bbdcDJunc0qmw4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683322105979963.2838656615183; Fri, 5 May 2023 14:28:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2va-0000rh-3w; Fri, 05 May 2023 17:25:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vX-0000q4-F3 for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:19 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2vP-0004fw-G7 for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:19 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-3f1e2555b5aso16256345e9.0 for ; Fri, 05 May 2023 14:25:11 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321910; x=1685913910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Bq2h9X5UNDb637fCQb6pFT3eLaF1A8JaUegXUakX2qE=; b=OibSM4vE2KwV+ScIoiCvrsYDbgSRWzHCgdY3uAPxGJAYTj8crdHJptn27iRPOEuG+e xyhSzmi9AV7HNr1ymbaUnmL/ANTvZ3Pa+qruthJk8fm9yW1n1Vv2c8+Hc8goMr+MGYjQ eEc0R9hLgi8B5hAELMzcUpJ6SRaaUy85w1B3J4zH99ilNIqpA5nR1JLbqIa9HFIKg1G7 bW50P+A6nRDwkBulD/pxm//VcqPn6W+ftFj6Yw6zYfjZSNGY66CL1rCT5VubSwUpmk2c DWlCc0LJ0X75exZnvBG9JKLsySxe6w1Rrwllazipde6YAQxJzeQP79+wH7bNNKojuE4V GuZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321910; x=1685913910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Bq2h9X5UNDb637fCQb6pFT3eLaF1A8JaUegXUakX2qE=; b=DEqK6pp78/DGbxBTYI6WjuozOOa5gX9MUPTSfIi2yJJ9po2LJPq+vfNdQ59OvuZ9jj 85FQ6a4IXzb7F9aLvjux3vdSl0p7zjoDmwEgGLr+vmhdHGtDiwfOsUXHskL5vE4linQm zkJqdOi2bUfuWDxVpDgS6beFUC//x91w3yNB3w7/T8d15e9fsXhdDQo0fBRcWjdbRVYZ qRjZ8B6jD7QWHquK1jz2I/xqPjSBR+B9AVIFYjTnGaARLpDx4r7jQ66CtB41VZehlJpD OiODE7n4nCiR86E9a/cISO+DvzHiX3lp3zqDU8vhI/wvDYy78mL8E6lA/2DiijJRjQud ttbQ== X-Gm-Message-State: AC+VfDxEB7b2B3XElRcekqaHR95Kc7n0nhhhCI8qOiynQEiyUZ2XsQo/ 4zV3z++gLAsxSnHXRMSO5SKFnALkihWPVsfn+O2lwg== X-Google-Smtp-Source: ACHHUZ6vHaHs6yClLSUCbHP4C6xOe50fZC5yUJjG38FNKiS1/3kZUVDCTfh/V03wnOUj81IP9ZDjQg== X-Received: by 2002:a7b:c38c:0:b0:3f4:e5c:794 with SMTP id s12-20020a7bc38c000000b003f40e5c0794mr1957297wmj.3.1683321910150; Fri, 05 May 2023 14:25:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 38/42] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st} Date: Fri, 5 May 2023 22:24:43 +0100 Message-Id: <20230505212447.374546-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322108178100004 We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index dbe4bf96b9..7e6466d3b6 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1178,7 +1178,7 @@ static const int qemu_st_opc[(MO_SIZE | MO_BSWAP) + 1= ] =3D { }; =20 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, - MemOpIdx oi, bool is_64) + MemOpIdx oi, TCGType data_type) { MemOp memop =3D get_memop(oi); tcg_insn_unit *label_ptr; @@ -1636,10 +1636,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, a0, a1, a2, false); + tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, a0, a1, a2, true); + tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); break; case INDEX_op_qemu_st_i32: tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322047; cv=none; d=zohomail.com; s=zohoarc; b=H/a/nfmqa6aE/HD5mz8s5BzyyveXgoM9TGJZ5/7t8nbJ/YOq7AlV0XYsfnG7CFgeEIWB+yViRCvBdrnm3CQXQqNd7V0yvt1anJ69pmkLVgUg05oOY0sNxTFEdRw+rHDKF+veD+ta3zSugk9J+/mBFVU8cJwuZhsNEAyxTm4+lZA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683322047; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JBlLTyWKOiEkOq0J5b/GXBVDB4TkoIkhZS8BOvAsaM4=; b=EBir/hHWd4Pn6y/RR4OGjOnPsdxeBEfSMXe58DaGMaceV1IaUxKZxQb214pj0mJ5Hni+NfYe/QV63hg/+qaAYFuo3jEtQ6il9P2jhu052CFhBRO59ilvdebYc6fKt7ThQCAwI00jceBTggNvX9MUhc/ifyLxFoD5ovcag6QnBKU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683322047446183.22242479402087; Fri, 5 May 2023 14:27:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2vq-0001H9-Al; Fri, 05 May 2023 17:25:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2vX-0000qh-Q2 for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:19 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2vQ-0004g4-11 for qemu-devel@nongnu.org; Fri, 05 May 2023 17:25:19 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-3023a56048bso2068801f8f.3 for ; Fri, 05 May 2023 14:25:11 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id t14-20020a5d460e000000b003047ae72b14sm3426709wrq.82.2023.05.05.14.25.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:25:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683321910; x=1685913910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JBlLTyWKOiEkOq0J5b/GXBVDB4TkoIkhZS8BOvAsaM4=; b=kDLX2I/ck4Y1SWTYt3GY7GLelgGdJEDdkhKvGdzf+Bpz04Vx6ybwmomd2LbATuojc+ GcoZ5Er/bdWZm7OLlC7I4grDSBjRaHLbxouhhZZ4ZJbGJak3VMMWlwu8NadX08RjknIq FAh93bsJnhq+Jqf8Yek1Qb9hY4WxfmWSKh5Qlp7LOV+AxVo1liN6k9yh4GYqklCYNPVa 16BlzlfvLTShpE8v5R1k1SFdq0jYh0PstSQ+1SDXoMVgp/0PwFUV87ISXQGWRpsXHQON r7wLgNHGYkp2X0ulna/Jn5OQ3NEx2rkkKubPoEeLsw1MnwZFbAKil8FNcO8nR62ydV7C pOIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683321910; x=1685913910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322049157100012 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tcg.c | 13 +++++++++++++ tcg/tcg-ldst.c.inc | 14 -------------- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index cfd3262a4a..6f5daaee5f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -94,6 +94,19 @@ typedef struct QEMU_PACKED { DebugFrameFDEHeader fde; } DebugFrameHeader; =20 +typedef struct TCGLabelQemuLdst { + bool is_ld; /* qemu_ld: true, qemu_st: false */ + MemOpIdx oi; + TCGType type; /* result type of a load */ + TCGReg addrlo_reg; /* reg index for low word of guest virtual add= r */ + TCGReg addrhi_reg; /* reg index for high word of guest virtual ad= dr */ + TCGReg datalo_reg; /* reg index for low word to be loaded or stor= ed */ + TCGReg datahi_reg; /* reg index for high word to be loaded or sto= red */ + const tcg_insn_unit *raddr; /* addr of the next IR of qemu_ld/st IR = */ + tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */ + QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next; +} TCGLabelQemuLdst; + static void tcg_register_jit_int(const void *buf, size_t size, const void *debug_frame, size_t debug_frame_size) diff --git a/tcg/tcg-ldst.c.inc b/tcg/tcg-ldst.c.inc index 403cbb0f06..ffada04af0 100644 --- a/tcg/tcg-ldst.c.inc +++ b/tcg/tcg-ldst.c.inc @@ -20,20 +20,6 @@ * THE SOFTWARE. */ =20 -typedef struct TCGLabelQemuLdst { - bool is_ld; /* qemu_ld: true, qemu_st: false */ - MemOpIdx oi; - TCGType type; /* result type of a load */ - TCGReg addrlo_reg; /* reg index for low word of guest virtual add= r */ - TCGReg addrhi_reg; /* reg index for high word of guest virtual ad= dr */ - TCGReg datalo_reg; /* reg index for low word to be loaded or stor= ed */ - TCGReg datahi_reg; /* reg index for high word to be loaded or sto= red */ - const tcg_insn_unit *raddr; /* addr of the next IR of qemu_ld/st IR = */ - tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */ - QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next; -} TCGLabelQemuLdst; - - /* * Generate TB finalization at the end of block */ --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id z10-20020a05600c220a00b003f171234a08sm9009001wml.20.2023.05.05.14.28.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:28:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683322091; x=1685914091; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rivgwXGbdDw6Y7e7EyPZeewGUUT+LzpYCC2kVwog6co=; b=MGcPSU05QSoaIJeE+CcKiV4dDlK+PgptfX5wel1q8uEr8SuYXvgAXyCqGTE52WmMmK dc+urEssY27vwZ50bsLihJ2Rz4Bh3SAeH0P1pjKC/0FW5jiJNSGQ+Xedc8iRlNsef3BD YB4bRiRJJQ0JboU97YZfSYSCD/U1olf1dFRtjVdwiL9tJOngs1++fVH2k65yadBlXVgE tWOy+EfwgCL5X2jUssN0rO9r1ih4V29JYf0GCZvWIoW2VE92T5rujQGRYw5N1SNO36F4 9haMPMZJ7nC+otA9oTnkzC1YXyCnPMqzi9Hq1zGVFlJfHupRX2Q6mNIHotpnNDiAiA23 D2hA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683322091; x=1685914091; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rivgwXGbdDw6Y7e7EyPZeewGUUT+LzpYCC2kVwog6co=; b=bgeBdluRHR60Dv/NwU+8VRYoTrX6o4vgEfP3kF7TRa/jxi3PyMYOZVUgejPwwFItlS 7S1iYhUdyRPLe2VufTWKC3jLFfc1m7ZxmZAqV5u0RcUtONTDGDwupKydvPffx0wWpnnl 9hqf44zrnt4g+4HJCkx5piNq6X3Z5I0BgNtiZ8Tz6AnjX3761v+iG1ltjbdzBzTWA1u/ kODYrY74GbdpIXaiCBsTb5ZdlQ8FauhPUwxLypBoR1l3GH6VaOo/pzCPYrvHGKypKqe/ MVpj3YUV/Vhact3X504TXH5yvOP3EDHYAlIVT243soEyKsiEP16t6iYyc3WTZ0VtHgY2 fqgA== X-Gm-Message-State: AC+VfDzMPAGz2Xnqy7wCy2FmeDCb/eR6j4hGSWVlzKuR/qkMvibLH00t wpcTAwAwMckjVoWBR+scndPP3zNtf4pp0AH45cHWDA== X-Google-Smtp-Source: ACHHUZ5/MYFhXBsZ2uJdWqP4DmT9btEI4hLXO7+D4GoQ8sn3fXYoiePax9bM3Y6qleVmwD7IjYtnNQ== X-Received: by 2002:a7b:cc05:0:b0:3f1:7581:eaaf with SMTP id f5-20020a7bcc05000000b003f17581eaafmr2066801wmh.4.1683322091644; Fri, 05 May 2023 14:28:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 40/42] tcg: Replace REG_P with arg_loc_reg_p Date: Fri, 5 May 2023 22:24:45 +0100 Message-Id: <20230505212447.374546-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322167274100001 An inline function is safer than a macro, and REG_P was rather too generic. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 4 ---- tcg/tcg.c | 16 +++++++++++++--- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index e542a4e9b7..0f1ba01a9a 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -58,10 +58,6 @@ typedef struct TCGCallArgumentLoc { unsigned tmp_subindex : 2; } TCGCallArgumentLoc; =20 -/* Avoid "unsigned < 0 is always false" Werror, when iarg_regs is empty. */ -#define REG_P(L) \ - ((int)(L)->arg_slot < (int)ARRAY_SIZE(tcg_target_call_iarg_regs)) - typedef struct TCGHelperInfo { void *func; const char *name; diff --git a/tcg/tcg.c b/tcg/tcg.c index 6f5daaee5f..fa28db0188 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -806,6 +806,16 @@ static void init_ffi_layouts(void) } #endif /* CONFIG_TCG_INTERPRETER */ =20 +static inline bool arg_slot_reg_p(unsigned arg_slot) +{ + /* + * Split the sizeof away from the comparison to avoid Werror from + * "unsigned < 0 is always false", when iarg_regs is empty. + */ + unsigned nreg =3D ARRAY_SIZE(tcg_target_call_iarg_regs); + return arg_slot < nreg; +} + typedef struct TCGCumulativeArgs { int arg_idx; /* tcg_gen_callN args[] */ int info_in_idx; /* TCGHelperInfo in[] */ @@ -3231,7 +3241,7 @@ liveness_pass_1(TCGContext *s) case TCG_CALL_ARG_NORMAL: case TCG_CALL_ARG_EXTEND_U: case TCG_CALL_ARG_EXTEND_S: - if (REG_P(loc)) { + if (arg_slot_reg_p(loc->arg_slot)) { *la_temp_pref(ts) =3D 0; break; } @@ -3258,7 +3268,7 @@ liveness_pass_1(TCGContext *s) case TCG_CALL_ARG_NORMAL: case TCG_CALL_ARG_EXTEND_U: case TCG_CALL_ARG_EXTEND_S: - if (REG_P(loc)) { + if (arg_slot_reg_p(loc->arg_slot)) { tcg_regset_set_reg(*la_temp_pref(ts), tcg_target_call_iarg_regs[loc->arg_slot]); } @@ -4833,7 +4843,7 @@ static void load_arg_stk(TCGContext *s, int stk_slot,= TCGTemp *ts, static void load_arg_normal(TCGContext *s, const TCGCallArgumentLoc *l, TCGTemp *ts, TCGRegSet *allocated_regs) { - if (REG_P(l)) { + if (arg_slot_reg_p(l->arg_slot)) { TCGReg reg =3D tcg_target_call_iarg_regs[l->arg_slot]; load_arg_reg(s, reg, ts, *allocated_regs); tcg_regset_set_reg(*allocated_regs, reg); --=20 2.34.1 From nobody Sat May 18 12:05:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1683322215; cv=none; d=zohomail.com; s=zohoarc; b=YakzRdu1ZajtTxINpeSGOH73YYKEVyQBgj8TLdxIZvaAv/RBRl8XCBR9t86oF//f8B0YZPjtMCP67ghrfeopM61xScY019pm6Y+LZBkx6Jzpta1SK4/nrSo/jBAsTEffxIZz89xzDqx4vHuMnjVJRRWomcu2TGVJ0w8HyyQ+hDA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683322215; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Yu6T1N8rjMDvjcqVloIbI64DCiKYMAX1Jvlpvr4G/Zc=; b=S8gBdXPnhkAKlEomvowv52e4zhUb+c0LjNsfkWTu3go3Z2OrdqUBLqJTS4pluevsV8J+qv/W+WOnN/AERc4DuAdyVXtUNul0MKZQ86DQRot/329fjEW+rOv75C2YDd+9x+q5CF0p5+BCXfi9cNsAncnKZnAgkpgLVzArpVBkfkU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683322215004809.7595204603792; Fri, 5 May 2023 14:30:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pv2yR-0006mN-Cs; Fri, 05 May 2023 17:28:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pv2yO-0006bm-R2 for qemu-devel@nongnu.org; Fri, 05 May 2023 17:28:16 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pv2yL-0005SE-OO for qemu-devel@nongnu.org; Fri, 05 May 2023 17:28:16 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3f19b9d5358so22961625e9.1 for ; Fri, 05 May 2023 14:28:13 -0700 (PDT) Received: from stoup.. ([212.241.182.8]) by smtp.gmail.com with ESMTPSA id z10-20020a05600c220a00b003f171234a08sm9009001wml.20.2023.05.05.14.28.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:28:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683322092; x=1685914092; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Yu6T1N8rjMDvjcqVloIbI64DCiKYMAX1Jvlpvr4G/Zc=; b=mdheJA/Gwu2S4s+zM7DrfAwI0C+a3YjIS3/Q2E8eusWP7QbcQFEKenicfBjcwI+VV/ hAbHKcU1izwfho4yCeVbdG9x9Pn5R/EYf2lpbUFhatdi+LtJDuKZMQA8hDOkiOt+hSDN Cx0bTl/2BE3UhM+0Tk6uoE0FUs3Kd1Q2FSd6alzOE6czspQdPYLLN5xkYa0NO4qv59PX owXmrRsXDRy6iASD+F7C5FO64B34BJKQBrFvEqQCjxLyl4c+gk9IfojwOT5eLBOFCmV0 gOxaPDvCpDaQHaq/qf4bRuuugwKrmHCLx1ua3lQajzyzz6Gf965ObbJs664ftl35olj4 t5/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683322092; x=1685914092; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Yu6T1N8rjMDvjcqVloIbI64DCiKYMAX1Jvlpvr4G/Zc=; b=e7lRA50h8gG6Gd++pvnDEyJV26q+cpPXvz6p9lw4N1TGJiT2giDt81heZcnL5SXTG/ zr28wqw3cbXAyyiZfUKp1Sl5J4R11JkLH7afmotVZAdWC5A8aLgi+oCaeHfoYGe5gqep 6gnNyn038IhRSwywfCAI5J1XJhcT28JJ1pHonXn6nXoLr9u3hnZ9cDNCuk0KyFj5B4QV vzsezeJhi/9ElqEuCnOibqWcgAUcdk7s0JGw66vLMdOnvxvIFIkkBOs6UIyT1OYt+Vn1 bCwp6Mh2li4YQt2HU7BbEDU38l6H/j5fAqRRZER9izG1sXzKsH5/KOcBJZAcmvfSysNO aXZQ== X-Gm-Message-State: AC+VfDxzjzg6u1lIzDFSHJ4sy3HeibhvIwM1TosqkDljaNuJkj7XXpTm pm+kXdlBYVPs46HithNs1OEapabOMlqtwQag3tiKMQ== X-Google-Smtp-Source: ACHHUZ5S9DsPZofiXQjo1H6G76XHwh6U3E+/qnIGRKwOkHhqKpWw2L/gCFU9xXbGnotvtF/LnK8HaQ== X-Received: by 2002:a5d:470b:0:b0:306:2ddb:47ab with SMTP id y11-20020a5d470b000000b003062ddb47abmr2397988wrq.39.1683322092209; Fri, 05 May 2023 14:28:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 41/42] tcg: Introduce arg_slot_stk_ofs Date: Fri, 5 May 2023 22:24:46 +0100 Message-Id: <20230505212447.374546-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322215593100001 Unify all computation of argument stack offset in one function. This requires that we adjust ref_slot to be in the same units, by adding max_reg_slots during init_call_layout. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tcg.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index fa28db0188..057423c121 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -816,6 +816,15 @@ static inline bool arg_slot_reg_p(unsigned arg_slot) return arg_slot < nreg; } =20 +static inline int arg_slot_stk_ofs(unsigned arg_slot) +{ + unsigned max =3D TCG_STATIC_CALL_ARGS_SIZE / sizeof(tcg_target_long); + unsigned stk_slot =3D arg_slot - ARRAY_SIZE(tcg_target_call_iarg_regs); + + tcg_debug_assert(stk_slot < max); + return TCG_TARGET_CALL_STACK_OFFSET + stk_slot * sizeof(tcg_target_lon= g); +} + typedef struct TCGCumulativeArgs { int arg_idx; /* tcg_gen_callN args[] */ int info_in_idx; /* TCGHelperInfo in[] */ @@ -1055,6 +1064,7 @@ static void init_call_layout(TCGHelperInfo *info) } } assert(ref_base + cum.ref_slot <=3D max_stk_slots); + ref_base +=3D max_reg_slots; =20 if (ref_base !=3D 0) { for (int i =3D cum.info_in_idx - 1; i >=3D 0; --i) { @@ -4826,7 +4836,7 @@ static void load_arg_reg(TCGContext *s, TCGReg reg, T= CGTemp *ts, } } =20 -static void load_arg_stk(TCGContext *s, int stk_slot, TCGTemp *ts, +static void load_arg_stk(TCGContext *s, unsigned arg_slot, TCGTemp *ts, TCGRegSet allocated_regs) { /* @@ -4836,8 +4846,7 @@ static void load_arg_stk(TCGContext *s, int stk_slot,= TCGTemp *ts, */ temp_load(s, ts, tcg_target_available_regs[ts->type], allocated_regs, = 0); tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, - TCG_TARGET_CALL_STACK_OFFSET + - stk_slot * sizeof(tcg_target_long)); + arg_slot_stk_ofs(arg_slot)); } =20 static void load_arg_normal(TCGContext *s, const TCGCallArgumentLoc *l, @@ -4848,18 +4857,16 @@ static void load_arg_normal(TCGContext *s, const TC= GCallArgumentLoc *l, load_arg_reg(s, reg, ts, *allocated_regs); tcg_regset_set_reg(*allocated_regs, reg); } else { - load_arg_stk(s, l->arg_slot - ARRAY_SIZE(tcg_target_call_iarg_regs= ), - ts, *allocated_regs); + load_arg_stk(s, l->arg_slot, ts, *allocated_regs); } } =20 -static void load_arg_ref(TCGContext *s, int arg_slot, TCGReg ref_base, +static void load_arg_ref(TCGContext *s, unsigned arg_slot, TCGReg ref_base, intptr_t ref_off, TCGRegSet *allocated_regs) { TCGReg reg; - int stk_slot =3D arg_slot - ARRAY_SIZE(tcg_target_call_iarg_regs); =20 - if (stk_slot < 0) { + if (arg_slot_reg_p(arg_slot)) { reg =3D tcg_target_call_iarg_regs[arg_slot]; tcg_reg_free(s, reg, *allocated_regs); tcg_out_addi_ptr(s, reg, ref_base, ref_off); @@ -4869,8 +4876,7 @@ static void load_arg_ref(TCGContext *s, int arg_slot,= TCGReg ref_base, *allocated_regs, 0, false); tcg_out_addi_ptr(s, reg, ref_base, ref_off); tcg_out_st(s, TCG_TYPE_PTR, reg, TCG_REG_CALL_STACK, - TCG_TARGET_CALL_STACK_OFFSET - + stk_slot * sizeof(tcg_target_long)); + arg_slot_stk_ofs(arg_slot)); } } =20 @@ -4900,8 +4906,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *= op) case TCG_CALL_ARG_BY_REF: load_arg_stk(s, loc->ref_slot, ts, allocated_regs); load_arg_ref(s, loc->arg_slot, TCG_REG_CALL_STACK, - TCG_TARGET_CALL_STACK_OFFSET - + loc->ref_slot * sizeof(tcg_target_long), + arg_slot_stk_ofs(loc->ref_slot), &allocated_regs); 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([212.241.182.8]) by smtp.gmail.com with ESMTPSA id z10-20020a05600c220a00b003f171234a08sm9009001wml.20.2023.05.05.14.28.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 14:28:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683322093; x=1685914093; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=I4w3bX0EvMhXa1FPvD+aIFFJRHstVlIrJSKr2TPnALg=; b=tvwGAkuZcct1ba7lwM/DR25lP0a//EAh+BE3T+QAOUHDIOMdcIBRTemi6/66L9C5bl X+lZ121x2YvtuJ74TWuaxTRAHbzQwQTiCYGIgEjRwHtVLG48G0Q3UDvr+u6wbXGRtWri 3EBUIwLv6avgKmCK5iQKQcSdJgMfhU1D5aZkaICwT8Pl5FvvTQhgGtAeT/tcibvLD63s csT19BgYKehyxDgxWXAbwikFvZnD6r9fXgTZuws97Lz4bjPXTYmZzbnd0wZ9LgizSkRe 49Lc2JsQx97QwgbF+Xj504h87xogTe1IjH0NAdiBFisIfzJZFq/iXO08mg+4mcl10SRY dG5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683322093; x=1685914093; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I4w3bX0EvMhXa1FPvD+aIFFJRHstVlIrJSKr2TPnALg=; b=GNzCizlgnTHNM75kOExYtT7DUeZySf23OB3g1DfRjkHf+wmbuWUcVLa4Gi4V9rQY3+ ES31RCj4zolK8Fm15x4xD4yNMO7Bcq2B8osTQPCCEkBejMI/nNjVN2bcGhTaaMmWgO2n BRpfXdxRoNU/1pmcN2jFm+Yp0SeJS2jzurFEQ2mduYGnaoo207mGzR+DAeOEAGkTIzxS WyBFhxZEooeyXO8ku5y+26rDahrCxwT3SKUPcu2AlZoF2udKQd2pyL1D3Pcj7d3NX86k 4L+1IlbEZZNaQ6z9Z4nKdapwIiDPANaG5cDTi+GN8A1mcXnclS3hQ+Boz29tbi91F0a+ eanQ== X-Gm-Message-State: AC+VfDw5SjL/O0uGJjzX6Bn3B0ImsICvRzd5QbBhxWyOudoRgabXTPQH 7Ub1XKp+HmAoZaNnMxJbouEEs2jTlFnuywsXhSr0Wg== X-Google-Smtp-Source: ACHHUZ6kxri/ilT9GjakQFIrmX0vHAQcmi1lF+Y1hgmaeGlfljZ1N6CnL4rtgFmKjsC7wpkAl3HvhA== X-Received: by 2002:a7b:c7c3:0:b0:3f1:72f8:6a92 with SMTP id z3-20020a7bc7c3000000b003f172f86a92mr2082123wmk.20.1683322092688; Fri, 05 May 2023 14:28:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 42/42] tcg: Widen helper_*_st[bw]_mmu val arguments Date: Fri, 5 May 2023 22:24:47 +0100 Message-Id: <20230505212447.374546-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org> References: <20230505212447.374546-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1683322123188100007 While the old type was correct in the ideal sense, some ABIs require the argument to be zero-extended. Using uint32_t for all such values is a decent compromise. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 10 +++++++--- accel/tcg/cputlb.c | 6 +++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h index 2ba22bd5fe..684e394b06 100644 --- a/include/tcg/tcg-ldst.h +++ b/include/tcg/tcg-ldst.h @@ -55,15 +55,19 @@ tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, = target_ulong addr, tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr); =20 -void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, +/* + * Value extended to at least uint32_t, so that some ABIs do not require + * zero-extension from uint8_t or uint16_t. + */ +void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr); -void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, +void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr); void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr); void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr); -void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, +void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr); void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c8bd642d0e..3117886af1 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2508,7 +2508,7 @@ full_stb_mmu(CPUArchState *env, target_ulong addr, ui= nt64_t val, store_helper(env, addr, val, oi, retaddr, MO_UB); } =20 -void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, +void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { full_stb_mmu(env, addr, val, oi, retaddr); @@ -2521,7 +2521,7 @@ static void full_le_stw_mmu(CPUArchState *env, target= _ulong addr, uint64_t val, store_helper(env, addr, val, oi, retaddr, MO_LEUW); } =20 -void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, +void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { full_le_stw_mmu(env, addr, val, oi, retaddr); @@ -2534,7 +2534,7 @@ static void full_be_stw_mmu(CPUArchState *env, target= _ulong addr, uint64_t val, store_helper(env, addr, val, oi, retaddr, MO_BEUW); } =20 -void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, +void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { full_be_stw_mmu(env, addr, val, oi, retaddr); --=20 2.34.1