From nobody Sat May 18 12:12:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1683296197; cv=none; d=zohomail.com; s=zohoarc; b=kM/rhr58P3reNGLY15BNrvw0CGToie72JByuniKUxw2b3QIhmm8tLkbd+sDdFOmddVCIqKdxefLvg8hpBZPRGJr1nuyWWCzLZbdkNp9Bd/iyC5AIPkxkWt1XGCzJavimdLcuMEynM9Ur16tWvNJ4pdpj6+8dghyAlXpFqIkoxTs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683296197; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Kbk8Cge/n32Mft+yWDtH9/RLhQFRShDEjTE8Wg5RC00=; b=nmtYfTLIMkKS/Xy/K93QgjwVq7pNySAJdbLOElRcs6/qzQQjGgTJuKDm9WinGqYW3PIZCXwh+47ez+SUY8WQ6C0H1ZE79pgoG232XNoNVZbM4jMVp+P88HWNELnqiCNnCDY8DttdTNC9BK8/s9VR8lPKs15ezIFxQMaCykaXqmg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683296197707385.40712221460694; Fri, 5 May 2023 07:16:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1puwCT-0004sx-Pm; Fri, 05 May 2023 10:14:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1puwCR-0004sD-NY for qemu-devel@nongnu.org; Fri, 05 May 2023 10:14:19 -0400 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1puwCO-0000yF-BC for qemu-devel@nongnu.org; Fri, 05 May 2023 10:14:19 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=Kbk8Cge/n32Mft+yWDtH9/RLhQFRShDEjTE8Wg5RC00=; b=JMHgNdq4F78WMRBbI5fD0LHswo AMuAif9IlMrCeIr4YYWjnuXNngAvI+iLRcugjKXTHXX6KK4ULaRadhIWzyIPeycRHLXbjbAqjx7qp +ko7VJc6uRtL2vvMDPTksm4WIaXkSuo2hSchpPilCYiCGy1osPQqI+0zuT0o424buAFM=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, philmd@linaro.org, marcel.apfelbaum@gmail.com, wangyanan55@huawei.com Subject: [PATCH v2 01/12] accel: Replace target_ulong in tlb_*() Date: Fri, 5 May 2023 16:13:52 +0200 Message-Id: <20230505141403.25735-2-anjo@rev.ng> In-Reply-To: <20230505141403.25735-1-anjo@rev.ng> References: <20230505141403.25735-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683296198184100002 Content-Type: text/plain; charset="utf-8" Replaces target_ulong with vaddr for guest virtual addresses in tlb_*() functions and auxilliary structs. Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- accel/stubs/tcg-stub.c | 2 +- accel/tcg/cputlb.c | 177 +++++++++++++++++------------------ accel/tcg/tb-maint.c | 2 +- include/exec/cpu-defs.h | 4 +- include/exec/exec-all.h | 79 ++++++++-------- include/qemu/plugin-memory.h | 2 +- 6 files changed, 131 insertions(+), 135 deletions(-) diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c index 813695b402..0998e601ad 100644 --- a/accel/stubs/tcg-stub.c +++ b/accel/stubs/tcg-stub.c @@ -18,7 +18,7 @@ void tb_flush(CPUState *cpu) { } =20 -void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) +void tlb_set_dirty(CPUState *cpu, vaddr vaddr) { } =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 207da51772..4807f1836d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -427,7 +427,7 @@ void tlb_flush_all_cpus_synced(CPUState *src_cpu) } =20 static bool tlb_hit_page_mask_anyprot(CPUTLBEntry *tlb_entry, - target_ulong page, target_ulong mask) + vaddr page, vaddr mask) { page &=3D mask; mask &=3D TARGET_PAGE_MASK | TLB_INVALID_MASK; @@ -437,8 +437,7 @@ static bool tlb_hit_page_mask_anyprot(CPUTLBEntry *tlb_= entry, page =3D=3D (tlb_entry->addr_code & mask)); } =20 -static inline bool tlb_hit_page_anyprot(CPUTLBEntry *tlb_entry, - target_ulong page) +static inline bool tlb_hit_page_anyprot(CPUTLBEntry *tlb_entry, vaddr page) { return tlb_hit_page_mask_anyprot(tlb_entry, page, -1); } @@ -454,8 +453,8 @@ static inline bool tlb_entry_is_empty(const CPUTLBEntry= *te) =20 /* Called with tlb_c.lock held */ static bool tlb_flush_entry_mask_locked(CPUTLBEntry *tlb_entry, - target_ulong page, - target_ulong mask) + vaddr page, + vaddr mask) { if (tlb_hit_page_mask_anyprot(tlb_entry, page, mask)) { memset(tlb_entry, -1, sizeof(*tlb_entry)); @@ -464,16 +463,15 @@ static bool tlb_flush_entry_mask_locked(CPUTLBEntry *= tlb_entry, return false; } =20 -static inline bool tlb_flush_entry_locked(CPUTLBEntry *tlb_entry, - target_ulong page) +static inline bool tlb_flush_entry_locked(CPUTLBEntry *tlb_entry, vaddr pa= ge) { return tlb_flush_entry_mask_locked(tlb_entry, page, -1); } =20 /* Called with tlb_c.lock held */ static void tlb_flush_vtlb_page_mask_locked(CPUArchState *env, int mmu_idx, - target_ulong page, - target_ulong mask) + vaddr page, + vaddr mask) { CPUTLBDesc *d =3D &env_tlb(env)->d[mmu_idx]; int k; @@ -487,21 +485,20 @@ static void tlb_flush_vtlb_page_mask_locked(CPUArchSt= ate *env, int mmu_idx, } =20 static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_i= dx, - target_ulong page) + vaddr page) { tlb_flush_vtlb_page_mask_locked(env, mmu_idx, page, -1); } =20 -static void tlb_flush_page_locked(CPUArchState *env, int midx, - target_ulong page) +static void tlb_flush_page_locked(CPUArchState *env, int midx, vaddr page) { - target_ulong lp_addr =3D env_tlb(env)->d[midx].large_page_addr; - target_ulong lp_mask =3D env_tlb(env)->d[midx].large_page_mask; + vaddr lp_addr =3D env_tlb(env)->d[midx].large_page_addr; + vaddr lp_mask =3D env_tlb(env)->d[midx].large_page_mask; =20 /* Check if we need to flush due to large pages. */ if ((page & lp_mask) =3D=3D lp_addr) { - tlb_debug("forcing full flush midx %d (" - TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", + tlb_debug("forcing full flush midx %d (%" + VADDR_PRIx "/%" VADDR_PRIx ")\n", midx, lp_addr, lp_mask); tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime()); } else { @@ -522,7 +519,7 @@ static void tlb_flush_page_locked(CPUArchState *env, in= t midx, * at @addr from the tlbs indicated by @idxmap from @cpu. */ static void tlb_flush_page_by_mmuidx_async_0(CPUState *cpu, - target_ulong addr, + vaddr addr, uint16_t idxmap) { CPUArchState *env =3D cpu->env_ptr; @@ -530,7 +527,7 @@ static void tlb_flush_page_by_mmuidx_async_0(CPUState *= cpu, =20 assert_cpu_is_self(cpu); =20 - tlb_debug("page addr:" TARGET_FMT_lx " mmu_map:0x%x\n", addr, idxmap); + tlb_debug("page addr: %" VADDR_PRIx " mmu_map:0x%x\n", addr, idxmap); =20 qemu_spin_lock(&env_tlb(env)->c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { @@ -561,15 +558,15 @@ static void tlb_flush_page_by_mmuidx_async_0(CPUState= *cpu, static void tlb_flush_page_by_mmuidx_async_1(CPUState *cpu, run_on_cpu_data data) { - target_ulong addr_and_idxmap =3D (target_ulong) data.target_ptr; - target_ulong addr =3D addr_and_idxmap & TARGET_PAGE_MASK; + vaddr addr_and_idxmap =3D data.target_ptr; + vaddr addr =3D addr_and_idxmap & TARGET_PAGE_MASK; uint16_t idxmap =3D addr_and_idxmap & ~TARGET_PAGE_MASK; =20 tlb_flush_page_by_mmuidx_async_0(cpu, addr, idxmap); } =20 typedef struct { - target_ulong addr; + vaddr addr; uint16_t idxmap; } TLBFlushPageByMMUIdxData; =20 @@ -592,9 +589,9 @@ static void tlb_flush_page_by_mmuidx_async_2(CPUState *= cpu, g_free(d); } =20 -void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, uint16_t i= dxmap) +void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, uint16_t idxmap) { - tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:%" PRIx16 "\n", addr, idxmap); + tlb_debug("addr: %" VADDR_PRIx " mmu_idx:%" PRIx16 "\n", addr, idxmap); =20 /* This should already be page aligned */ addr &=3D TARGET_PAGE_MASK; @@ -620,15 +617,15 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_u= long addr, uint16_t idxmap) } } =20 -void tlb_flush_page(CPUState *cpu, target_ulong addr) +void tlb_flush_page(CPUState *cpu, vaddr addr) { tlb_flush_page_by_mmuidx(cpu, addr, ALL_MMUIDX_BITS); } =20 -void tlb_flush_page_by_mmuidx_all_cpus(CPUState *src_cpu, target_ulong add= r, +void tlb_flush_page_by_mmuidx_all_cpus(CPUState *src_cpu, vaddr addr, uint16_t idxmap) { - tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:%"PRIx16"\n", addr, idxmap); + tlb_debug("addr: %" VADDR_PRIx " mmu_idx:%"PRIx16"\n", addr, idxmap); =20 /* This should already be page aligned */ addr &=3D TARGET_PAGE_MASK; @@ -660,16 +657,16 @@ void tlb_flush_page_by_mmuidx_all_cpus(CPUState *src_= cpu, target_ulong addr, tlb_flush_page_by_mmuidx_async_0(src_cpu, addr, idxmap); } =20 -void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr) +void tlb_flush_page_all_cpus(CPUState *src, vaddr addr) { tlb_flush_page_by_mmuidx_all_cpus(src, addr, ALL_MMUIDX_BITS); } =20 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *src_cpu, - target_ulong addr, + vaddr addr, uint16_t idxmap) { - tlb_debug("addr: "TARGET_FMT_lx" mmu_idx:%"PRIx16"\n", addr, idxmap); + tlb_debug("addr: %" VADDR_PRIx " mmu_idx:%"PRIx16"\n", addr, idxmap); =20 /* This should already be page aligned */ addr &=3D TARGET_PAGE_MASK; @@ -706,18 +703,18 @@ void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUStat= e *src_cpu, } } =20 -void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr) +void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr) { tlb_flush_page_by_mmuidx_all_cpus_synced(src, addr, ALL_MMUIDX_BITS); } =20 static void tlb_flush_range_locked(CPUArchState *env, int midx, - target_ulong addr, target_ulong len, + vaddr addr, vaddr len, unsigned bits) { CPUTLBDesc *d =3D &env_tlb(env)->d[midx]; CPUTLBDescFast *f =3D &env_tlb(env)->f[midx]; - target_ulong mask =3D MAKE_64BIT_MASK(0, bits); + vaddr mask =3D MAKE_64BIT_MASK(0, bits); =20 /* * If @bits is smaller than the tlb size, there may be multiple entries @@ -731,7 +728,7 @@ static void tlb_flush_range_locked(CPUArchState *env, i= nt midx, */ if (mask < f->mask || len > f->mask) { tlb_debug("forcing full flush midx %d (" - TARGET_FMT_lx "/" TARGET_FMT_lx "+" TARGET_FMT_lx ")\n", + "%" VADDR_PRIx "/%" VADDR_PRIx "+%" VADDR_PRIx ")\n", midx, addr, mask, len); tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime()); return; @@ -744,14 +741,14 @@ static void tlb_flush_range_locked(CPUArchState *env,= int midx, */ if (((addr + len - 1) & d->large_page_mask) =3D=3D d->large_page_addr)= { tlb_debug("forcing full flush midx %d (" - TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", + "%" VADDR_PRIx "/%" VADDR_PRIx ")\n", midx, d->large_page_addr, d->large_page_mask); tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime()); return; } =20 - for (target_ulong i =3D 0; i < len; i +=3D TARGET_PAGE_SIZE) { - target_ulong page =3D addr + i; + for (vaddr i =3D 0; i < len; i +=3D TARGET_PAGE_SIZE) { + vaddr page =3D addr + i; CPUTLBEntry *entry =3D tlb_entry(env, midx, page); =20 if (tlb_flush_entry_mask_locked(entry, page, mask)) { @@ -762,8 +759,8 @@ static void tlb_flush_range_locked(CPUArchState *env, i= nt midx, } =20 typedef struct { - target_ulong addr; - target_ulong len; + vaddr addr; + vaddr len; uint16_t idxmap; uint16_t bits; } TLBFlushRangeData; @@ -776,7 +773,7 @@ static void tlb_flush_range_by_mmuidx_async_0(CPUState = *cpu, =20 assert_cpu_is_self(cpu); =20 - tlb_debug("range:" TARGET_FMT_lx "/%u+" TARGET_FMT_lx " mmu_map:0x%x\n= ", + tlb_debug("range: %" VADDR_PRIx "/%u+%" VADDR_PRIx " mmu_map:0x%x\n", d.addr, d.bits, d.len, d.idxmap); =20 qemu_spin_lock(&env_tlb(env)->c.lock); @@ -801,7 +798,7 @@ static void tlb_flush_range_by_mmuidx_async_0(CPUState = *cpu, * overlap the flushed pages, which includes the previous. */ d.addr -=3D TARGET_PAGE_SIZE; - for (target_ulong i =3D 0, n =3D d.len / TARGET_PAGE_SIZE + 1; i < n; = i++) { + for (vaddr i =3D 0, n =3D d.len / TARGET_PAGE_SIZE + 1; i < n; i++) { tb_jmp_cache_clear_page(cpu, d.addr); d.addr +=3D TARGET_PAGE_SIZE; } @@ -815,8 +812,8 @@ static void tlb_flush_range_by_mmuidx_async_1(CPUState = *cpu, g_free(d); } =20 -void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr, - target_ulong len, uint16_t idxmap, +void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, + vaddr len, uint16_t idxmap, unsigned bits) { TLBFlushRangeData d; @@ -851,14 +848,14 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, target_= ulong addr, } } =20 -void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr, +void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, uint16_t idxmap, unsigned bits) { tlb_flush_range_by_mmuidx(cpu, addr, TARGET_PAGE_SIZE, idxmap, bits); } =20 void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src_cpu, - target_ulong addr, target_ulong le= n, + vaddr addr, vaddr len, uint16_t idxmap, unsigned bits) { TLBFlushRangeData d; @@ -898,16 +895,16 @@ void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src= _cpu, } =20 void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *src_cpu, - target_ulong addr, - uint16_t idxmap, unsigned bits) + vaddr addr, uint16_t idxmap, + unsigned bits) { tlb_flush_range_by_mmuidx_all_cpus(src_cpu, addr, TARGET_PAGE_SIZE, idxmap, bits); } =20 void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *src_cpu, - target_ulong addr, - target_ulong len, + vaddr addr, + vaddr len, uint16_t idxmap, unsigned bits) { @@ -949,7 +946,7 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState= *src_cpu, } =20 void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, - target_ulong addr, + vaddr addr, uint16_t idxmap, unsigned bits) { @@ -1055,32 +1052,32 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t star= t1, ram_addr_t length) =20 /* Called with tlb_c.lock held */ static inline void tlb_set_dirty1_locked(CPUTLBEntry *tlb_entry, - target_ulong vaddr) + vaddr addr) { - if (tlb_entry->addr_write =3D=3D (vaddr | TLB_NOTDIRTY)) { - tlb_entry->addr_write =3D vaddr; + if (tlb_entry->addr_write =3D=3D (addr | TLB_NOTDIRTY)) { + tlb_entry->addr_write =3D addr; } } =20 /* update the TLB corresponding to virtual page vaddr so that it is no longer dirty */ -void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) +void tlb_set_dirty(CPUState *cpu, vaddr addr) { CPUArchState *env =3D cpu->env_ptr; int mmu_idx; =20 assert_cpu_is_self(cpu); =20 - vaddr &=3D TARGET_PAGE_MASK; + addr &=3D TARGET_PAGE_MASK; qemu_spin_lock(&env_tlb(env)->c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - tlb_set_dirty1_locked(tlb_entry(env, mmu_idx, vaddr), vaddr); + tlb_set_dirty1_locked(tlb_entry(env, mmu_idx, addr), addr); } =20 for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { int k; for (k =3D 0; k < CPU_VTLB_SIZE; k++) { - tlb_set_dirty1_locked(&env_tlb(env)->d[mmu_idx].vtable[k], vad= dr); + tlb_set_dirty1_locked(&env_tlb(env)->d[mmu_idx].vtable[k], add= r); } } qemu_spin_unlock(&env_tlb(env)->c.lock); @@ -1089,20 +1086,20 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vadd= r) /* Our TLB does not support large pages, so remember the area covered by large pages and trigger a full TLB flush if these are invalidated. */ static void tlb_add_large_page(CPUArchState *env, int mmu_idx, - target_ulong vaddr, target_ulong size) + vaddr addr, uint64_t size) { - target_ulong lp_addr =3D env_tlb(env)->d[mmu_idx].large_page_addr; - target_ulong lp_mask =3D ~(size - 1); + vaddr lp_addr =3D env_tlb(env)->d[mmu_idx].large_page_addr; + vaddr lp_mask =3D ~(size - 1); =20 - if (lp_addr =3D=3D (target_ulong)-1) { + if (lp_addr =3D=3D (vaddr)-1) { /* No previous large page. */ - lp_addr =3D vaddr; + lp_addr =3D addr; } else { /* Extend the existing region to include the new page. This is a compromise between unnecessary flushes and the cost of maintaining a full variable size TLB. */ lp_mask &=3D env_tlb(env)->d[mmu_idx].large_page_mask; - while (((lp_addr ^ vaddr) & lp_mask) !=3D 0) { + while (((lp_addr ^ addr) & lp_mask) !=3D 0) { lp_mask <<=3D 1; } } @@ -1119,19 +1116,19 @@ static void tlb_add_large_page(CPUArchState *env, i= nt mmu_idx, * critical section. */ void tlb_set_page_full(CPUState *cpu, int mmu_idx, - target_ulong vaddr, CPUTLBEntryFull *full) + vaddr addr, CPUTLBEntryFull *full) { CPUArchState *env =3D cpu->env_ptr; CPUTLB *tlb =3D env_tlb(env); CPUTLBDesc *desc =3D &tlb->d[mmu_idx]; MemoryRegionSection *section; unsigned int index; - target_ulong address; - target_ulong write_address; + vaddr address; + vaddr write_address; uintptr_t addend; CPUTLBEntry *te, tn; hwaddr iotlb, xlat, sz, paddr_page; - target_ulong vaddr_page; + vaddr addr_page; int asidx, wp_flags, prot; bool is_ram, is_romd; =20 @@ -1141,9 +1138,9 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, sz =3D TARGET_PAGE_SIZE; } else { sz =3D (hwaddr)1 << full->lg_page_size; - tlb_add_large_page(env, mmu_idx, vaddr, sz); + tlb_add_large_page(env, mmu_idx, addr, sz); } - vaddr_page =3D vaddr & TARGET_PAGE_MASK; + addr_page =3D addr & TARGET_PAGE_MASK; paddr_page =3D full->phys_addr & TARGET_PAGE_MASK; =20 prot =3D full->prot; @@ -1152,11 +1149,11 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, &xlat, &sz, full->attrs, &= prot); assert(sz >=3D TARGET_PAGE_SIZE); =20 - tlb_debug("vaddr=3D" TARGET_FMT_lx " paddr=3D0x" HWADDR_FMT_plx + tlb_debug("vaddr=3D%" VADDR_PRIx " paddr=3D0x" HWADDR_FMT_plx " prot=3D%x idx=3D%d\n", - vaddr, full->phys_addr, prot, mmu_idx); + addr, full->phys_addr, prot, mmu_idx); =20 - address =3D vaddr_page; + address =3D addr_page; if (full->lg_page_size < TARGET_PAGE_BITS) { /* Repeat the MMU check and TLB fill on every access. */ address |=3D TLB_INVALID_MASK; @@ -1204,11 +1201,11 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, } } =20 - wp_flags =3D cpu_watchpoint_address_matches(cpu, vaddr_page, + wp_flags =3D cpu_watchpoint_address_matches(cpu, addr_page, TARGET_PAGE_SIZE); =20 - index =3D tlb_index(env, mmu_idx, vaddr_page); - te =3D tlb_entry(env, mmu_idx, vaddr_page); + index =3D tlb_index(env, mmu_idx, addr_page); + te =3D tlb_entry(env, mmu_idx, addr_page); =20 /* * Hold the TLB lock for the rest of the function. We could acquire/re= lease @@ -1223,13 +1220,13 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, tlb->c.dirty |=3D 1 << mmu_idx; =20 /* Make sure there's no cached translation for the new page. */ - tlb_flush_vtlb_page_locked(env, mmu_idx, vaddr_page); + tlb_flush_vtlb_page_locked(env, mmu_idx, addr_page); =20 /* * Only evict the old entry to the victim tlb if it's for a * different page; otherwise just overwrite the stale data. */ - if (!tlb_hit_page_anyprot(te, vaddr_page) && !tlb_entry_is_empty(te)) { + if (!tlb_hit_page_anyprot(te, addr_page) && !tlb_entry_is_empty(te)) { unsigned vidx =3D desc->vindex++ % CPU_VTLB_SIZE; CPUTLBEntry *tv =3D &desc->vtable[vidx]; =20 @@ -1253,11 +1250,11 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). */ desc->fulltlb[index] =3D *full; - desc->fulltlb[index].xlat_section =3D iotlb - vaddr_page; + desc->fulltlb[index].xlat_section =3D iotlb - addr_page; desc->fulltlb[index].phys_addr =3D paddr_page; =20 /* Now calculate the new entry */ - tn.addend =3D addend - vaddr_page; + tn.addend =3D addend - addr_page; if (prot & PAGE_READ) { tn.addr_read =3D address; if (wp_flags & BP_MEM_READ) { @@ -1289,9 +1286,9 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, qemu_spin_unlock(&tlb->c.lock); } =20 -void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, +void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, hwaddr paddr, MemTxAttrs attrs, int prot, - int mmu_idx, target_ulong size) + int mmu_idx, uint64_t size) { CPUTLBEntryFull full =3D { .phys_addr =3D paddr, @@ -1301,14 +1298,14 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_= ulong vaddr, }; =20 assert(is_power_of_2(size)); - tlb_set_page_full(cpu, mmu_idx, vaddr, &full); + tlb_set_page_full(cpu, mmu_idx, addr, &full); } =20 -void tlb_set_page(CPUState *cpu, target_ulong vaddr, +void tlb_set_page(CPUState *cpu, vaddr addr, hwaddr paddr, int prot, - int mmu_idx, target_ulong size) + int mmu_idx, uint64_t size) { - tlb_set_page_with_attrs(cpu, vaddr, paddr, MEMTXATTRS_UNSPECIFIED, + tlb_set_page_with_attrs(cpu, addr, paddr, MEMTXATTRS_UNSPECIFIED, prot, mmu_idx, size); } =20 @@ -1317,7 +1314,7 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, * caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) = must * be discarded and looked up again (e.g. via tlb_entry()). */ -static void tlb_fill(CPUState *cpu, target_ulong addr, int size, +static void tlb_fill(CPUState *cpu, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t ret= addr) { bool ok; @@ -1357,7 +1354,7 @@ static inline void cpu_transaction_failed(CPUState *c= pu, hwaddr physaddr, } =20 static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full, - int mmu_idx, target_ulong addr, uintptr_t retaddr, + int mmu_idx, vaddr addr, uintptr_t retaddr, MMUAccessType access_type, MemOp op) { CPUState *cpu =3D env_cpu(env); @@ -1407,7 +1404,7 @@ static void save_iotlb_data(CPUState *cs, MemoryRegio= nSection *section, } =20 static void io_writex(CPUArchState *env, CPUTLBEntryFull *full, - int mmu_idx, uint64_t val, target_ulong addr, + int mmu_idx, uint64_t val, vaddr addr, uintptr_t retaddr, MemOp op) { CPUState *cpu =3D env_cpu(env); @@ -1449,7 +1446,7 @@ static void io_writex(CPUArchState *env, CPUTLBEntryF= ull *full, /* Return true if ADDR is present in the victim tlb, and has been copied back to the main tlb. */ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, - MMUAccessType access_type, target_ulong page) + MMUAccessType access_type, vaddr page) { size_t vidx; =20 @@ -1691,13 +1688,13 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchStat= e *env, target_ulong addr, * from the same thread (which a mem callback will be) this is safe. */ =20 -bool tlb_plugin_lookup(CPUState *cpu, target_ulong addr, int mmu_idx, +bool tlb_plugin_lookup(CPUState *cpu, vaddr addr, int mmu_idx, bool is_store, struct qemu_plugin_hwaddr *data) { CPUArchState *env =3D cpu->env_ptr; CPUTLBEntry *tlbe =3D tlb_entry(env, mmu_idx, addr); uintptr_t index =3D tlb_index(env, mmu_idx, addr); - target_ulong tlb_addr =3D is_store ? tlb_addr_write(tlbe) : tlbe->addr= _read; + vaddr tlb_addr =3D is_store ? tlb_addr_write(tlbe) : tlbe->addr_read; =20 if (likely(tlb_hit(tlb_addr, addr))) { /* We must have an iotlb entry for MMIO */ diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index 7d613d36d2..e79b054f36 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -99,7 +99,7 @@ static void tb_remove_all(void) /* Call with mmap_lock held. */ static void tb_record(TranslationBlock *tb, PageDesc *p1, PageDesc *p2) { - target_ulong addr; + vaddr addr; int flags; =20 assert_memory_lock(); diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 0d418a0384..8f776878f3 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -147,8 +147,8 @@ typedef struct CPUTLBDesc { * we must flush the entire tlb. The region is matched if * (addr & large_page_mask) =3D=3D large_page_addr. */ - target_ulong large_page_addr; - target_ulong large_page_mask; + vaddr large_page_addr; + vaddr large_page_mask; /* host time (in ns) at the beginning of the time window */ int64_t window_begin_ns; /* maximum number of entries observed in the window */ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 698943d58f..f5508e242b 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -94,7 +94,7 @@ void tlb_destroy(CPUState *cpu); * Flush one page from the TLB of the specified CPU, for all * MMU indexes. */ -void tlb_flush_page(CPUState *cpu, target_ulong addr); +void tlb_flush_page(CPUState *cpu, vaddr addr); /** * tlb_flush_page_all_cpus: * @cpu: src CPU of the flush @@ -103,7 +103,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr); * Flush one page from the TLB of the specified CPU, for all * MMU indexes. */ -void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr); +void tlb_flush_page_all_cpus(CPUState *src, vaddr addr); /** * tlb_flush_page_all_cpus_synced: * @cpu: src CPU of the flush @@ -115,7 +115,7 @@ void tlb_flush_page_all_cpus(CPUState *src, target_ulon= g addr); * the source vCPUs safe work is complete. This will depend on when * the guests translation ends the TB. */ -void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr); +void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr); /** * tlb_flush: * @cpu: CPU whose TLB should be flushed @@ -150,7 +150,7 @@ void tlb_flush_all_cpus_synced(CPUState *src_cpu); * Flush one page from the TLB of the specified CPU, for the specified * MMU indexes. */ -void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, +void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, uint16_t idxmap); /** * tlb_flush_page_by_mmuidx_all_cpus: @@ -161,7 +161,7 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulo= ng addr, * Flush one page from the TLB of all CPUs, for the specified * MMU indexes. */ -void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr, +void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr, uint16_t idxmap); /** * tlb_flush_page_by_mmuidx_all_cpus_synced: @@ -175,7 +175,7 @@ void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, t= arget_ulong addr, * complete once the source vCPUs safe work is complete. This will * depend on when the guests translation ends the TB. */ -void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong = addr, +void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, uint16_t idxmap); /** * tlb_flush_by_mmuidx: @@ -218,14 +218,14 @@ void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cp= u, uint16_t idxmap); * * Similar to tlb_flush_page_mask, but with a bitmap of indexes. */ -void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr, +void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, uint16_t idxmap, unsigned bits); =20 /* Similarly, with broadcast and syncing. */ -void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, target_ulong ad= dr, +void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr, uint16_t idxmap, unsigned bits= ); void tlb_flush_page_bits_by_mmuidx_all_cpus_synced - (CPUState *cpu, target_ulong addr, uint16_t idxmap, unsigned bits); + (CPUState *cpu, vaddr addr, uint16_t idxmap, unsigned bits); =20 /** * tlb_flush_range_by_mmuidx @@ -238,17 +238,17 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len), * comparing only the low @bits worth of each virtual page. */ -void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr, - target_ulong len, uint16_t idxmap, +void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, + vaddr len, uint16_t idxmap, unsigned bits); =20 /* Similarly, with broadcast and syncing. */ -void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr, - target_ulong len, uint16_t idxmap, +void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr, + vaddr len, uint16_t idxmap, unsigned bits); void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, - target_ulong addr, - target_ulong len, + vaddr addr, + vaddr len, uint16_t idxmap, unsigned bits); =20 @@ -256,7 +256,7 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState= *cpu, * tlb_set_page_full: * @cpu: CPU context * @mmu_idx: mmu index of the tlb to modify - * @vaddr: virtual address of the entry to add + * @addr: virtual address of the entry to add * @full: the details of the tlb entry * * Add an entry to @cpu tlb index @mmu_idx. All of the fields of @@ -271,13 +271,13 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUSta= te *cpu, * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only * used by tlb_flush_page. */ -void tlb_set_page_full(CPUState *cpu, int mmu_idx, target_ulong vaddr, +void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, CPUTLBEntryFull *full); =20 /** * tlb_set_page_with_attrs: * @cpu: CPU to add this TLB entry for - * @vaddr: virtual address of page to add entry for + * @addr: virtual address of page to add entry for * @paddr: physical address of the page * @attrs: memory transaction attributes * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) @@ -285,7 +285,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, targ= et_ulong vaddr, * @size: size of the page in bytes * * Add an entry to this CPU's TLB (a mapping from virtual address - * @vaddr to physical address @paddr) with the specified memory + * @addr to physical address @paddr) with the specified memory * transaction attributes. This is generally called by the target CPU * specific code after it has been called through the tlb_fill() * entry point and performed a successful page table walk to find @@ -296,18 +296,18 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, ta= rget_ulong vaddr, * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only * used by tlb_flush_page. */ -void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, +void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, hwaddr paddr, MemTxAttrs attrs, - int prot, int mmu_idx, target_ulong size); + int prot, int mmu_idx, vaddr size); /* tlb_set_page: * * This function is equivalent to calling tlb_set_page_with_attrs() * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided * as a convenience for CPUs which don't use memory transaction attributes. */ -void tlb_set_page(CPUState *cpu, target_ulong vaddr, +void tlb_set_page(CPUState *cpu, vaddr addr, hwaddr paddr, int prot, - int mmu_idx, target_ulong size); + int mmu_idx, vaddr size); #else static inline void tlb_init(CPUState *cpu) { @@ -315,14 +315,13 @@ static inline void tlb_init(CPUState *cpu) static inline void tlb_destroy(CPUState *cpu) { } -static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) +static inline void tlb_flush_page(CPUState *cpu, vaddr addr) { } -static inline void tlb_flush_page_all_cpus(CPUState *src, target_ulong add= r) +static inline void tlb_flush_page_all_cpus(CPUState *src, vaddr addr) { } -static inline void tlb_flush_page_all_cpus_synced(CPUState *src, - target_ulong addr) +static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr add= r) { } static inline void tlb_flush(CPUState *cpu) @@ -335,7 +334,7 @@ static inline void tlb_flush_all_cpus_synced(CPUState *= src_cpu) { } static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, - target_ulong addr, uint16_t id= xmap) + vaddr addr, uint16_t idxmap) { } =20 @@ -343,12 +342,12 @@ static inline void tlb_flush_by_mmuidx(CPUState *cpu,= uint16_t idxmap) { } static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, - target_ulong addr, + vaddr addr, uint16_t idxmap) { } static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, - target_ulong a= ddr, + vaddr addr, uint16_t idxma= p) { } @@ -361,37 +360,37 @@ static inline void tlb_flush_by_mmuidx_all_cpus_synce= d(CPUState *cpu, { } static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, - target_ulong addr, + vaddr addr, uint16_t idxmap, unsigned bits) { } static inline void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, - target_ulong add= r, + vaddr addr, uint16_t idxmap, unsigned bits) { } static inline void -tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong = addr, +tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, uint16_t idxmap, unsigned bi= ts) { } -static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong a= ddr, - target_ulong len, uint16_t id= xmap, +static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, + vaddr len, uint16_t idxmap, unsigned bits) { } static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, - target_ulong addr, - target_ulong len, + vaddr addr, + vaddr len, uint16_t idxmap, unsigned bits) { } static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, - target_ulong = addr, - target_long l= en, + vaddr addr, + vaddr len, uint16_t idxm= ap, unsigned bits) { @@ -663,7 +662,7 @@ static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} =20 void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); -void tlb_set_dirty(CPUState *cpu, target_ulong vaddr); +void tlb_set_dirty(CPUState *cpu, vaddr addr); =20 MemoryRegionSection * address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, diff --git a/include/qemu/plugin-memory.h b/include/qemu/plugin-memory.h index 6fd539022a..43165f2452 100644 --- a/include/qemu/plugin-memory.h +++ b/include/qemu/plugin-memory.h @@ -37,7 +37,7 @@ struct qemu_plugin_hwaddr { * It would only fail if not called from an instrumented memory access * which would be an abuse of the API. */ -bool tlb_plugin_lookup(CPUState *cpu, target_ulong addr, int mmu_idx, +bool tlb_plugin_lookup(CPUState *cpu, vaddr addr, int mmu_idx, bool is_store, struct qemu_plugin_hwaddr *data); =20 #endif /* PLUGIN_MEMORY_H */ --=20 2.39.1 From nobody Sat May 18 12:12:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683296196846635.5861301641762; Fri, 5 May 2023 07:16:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1puwCU-0004t4-4n; Fri, 05 May 2023 10:14:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1puwCT-0004sR-2W for qemu-devel@nongnu.org; Fri, 05 May 2023 10:14:21 -0400 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1puwCO-0000yH-B2 for qemu-devel@nongnu.org; Fri, 05 May 2023 10:14:20 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=ImehzQv7zZ1ca13cDZJt7BKSrdiV3yGCoHcAjkx8g/w=; b=ZSdyj16fS6A4LHYs2BiSydxOGs 0fzZCXr5Q8faPC9FVxIsqzigCTclQNhSU499j0WZiAL/sAJCn5HpQBRvIQmbG/MZIHMavrnEAmnrx gaZMA8h5cwvPmKIhbZkAwsyc0gwLMVx21i3FEVf9/r/haEe10DSOOw71asRLGSerg2Ak=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, philmd@linaro.org, marcel.apfelbaum@gmail.com, wangyanan55@huawei.com Subject: [PATCH v2 02/12] accel/tcg/translate-all.c: Widen pc and cs_base Date: Fri, 5 May 2023 16:13:53 +0200 Message-Id: <20230505141403.25735-3-anjo@rev.ng> In-Reply-To: <20230505141403.25735-1-anjo@rev.ng> References: <20230505141403.25735-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683296198882100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- accel/tcg/internal.h | 6 +++--- accel/tcg/translate-all.c | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h index 8ca24420ea..9b04a33d58 100644 --- a/accel/tcg/internal.h +++ b/accel/tcg/internal.h @@ -42,8 +42,8 @@ void tb_invalidate_phys_range_fast(ram_addr_t ram_addr, G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); #endif /* CONFIG_SOFTMMU */ =20 -TranslationBlock *tb_gen_code(CPUState *cpu, target_ulong pc, - target_ulong cs_base, uint32_t flags, +TranslationBlock *tb_gen_code(CPUState *cpu, vaddr pc, + uint64_t cs_base, uint32_t flags, int cflags); void page_init(void); void tb_htable_init(void); @@ -55,7 +55,7 @@ void cpu_restore_state_from_tb(CPUState *cpu, Translation= Block *tb, uintptr_t host_pc); =20 /* Return the current PC from CPU, which may be cached in TB. */ -static inline target_ulong log_pc(CPUState *cpu, const TranslationBlock *t= b) +static inline vaddr log_pc(CPUState *cpu, const TranslationBlock *tb) { if (tb_cflags(tb) & CF_PCREL) { return cpu->cc->get_pc(cpu); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index dd19b3ca78..6a40bb83be 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -276,7 +276,7 @@ void page_init(void) * Return the size of the generated code, or negative on error. */ static int setjmp_gen_code(CPUArchState *env, TranslationBlock *tb, - target_ulong pc, void *host_pc, + vaddr pc, void *host_pc, int *max_insns, int64_t *ti) { int ret =3D sigsetjmp(tcg_ctx->jmp_trans, 0); @@ -304,7 +304,7 @@ static int setjmp_gen_code(CPUArchState *env, Translati= onBlock *tb, =20 /* Called with mmap_lock held for user mode emulation. */ TranslationBlock *tb_gen_code(CPUState *cpu, - target_ulong pc, target_ulong cs_base, + vaddr pc, uint64_t cs_base, uint32_t flags, int cflags) { CPUArchState *env =3D cpu->env_ptr; @@ -637,10 +637,10 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retadd= r) cpu->cflags_next_tb =3D curr_cflags(cpu) | CF_MEMI_ONLY | CF_LAST_IO |= n; =20 if (qemu_loglevel_mask(CPU_LOG_EXEC)) { - target_ulong pc =3D log_pc(cpu, tb); + vaddr pc =3D log_pc(cpu, tb); if (qemu_log_in_addr_range(pc)) { - qemu_log("cpu_io_recompile: rewound execution of TB to " - TARGET_FMT_lx "\n", pc); + qemu_log("cpu_io_recompile: rewound execution of TB to %" + VADDR_PRIx "\n", pc); } } =20 --=20 2.39.1 From nobody Sat May 18 12:12:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=Vssj+j7Kn/Bu/ljFBDAqfiURYBzt+p6xfSsLpuVA0OM=; b=K2vyVjyAVLHdXlYfRMhZ4avGWV L+Duci17bVATdtmax4FcqChXQg4UFuYDyd4bFx2MxAoWxyVkllUixBsMBHYx/B1oKRNSEKEEuMiq4 0sKr+2AxpvMLt3D0DYRbqEFAhedzfEYhKpMzQcFJVuoYK+zp4CnPKQ+BhQmYwtUf469M=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, philmd@linaro.org, marcel.apfelbaum@gmail.com, wangyanan55@huawei.com Subject: [PATCH v2 03/12] target: Widen pc/cs_base in cpu_get_tb_cpu_state Date: Fri, 5 May 2023 16:13:54 +0200 Message-Id: <20230505141403.25735-4-anjo@rev.ng> In-Reply-To: <20230505141403.25735-1-anjo@rev.ng> References: <20230505141403.25735-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683296192148100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- accel/tcg/cpu-exec.c | 9 ++++++--- accel/tcg/translate-all.c | 3 ++- target/alpha/cpu.h | 4 ++-- target/arm/cpu.h | 4 ++-- target/arm/helper.c | 4 ++-- target/avr/cpu.h | 4 ++-- target/cris/cpu.h | 4 ++-- target/hexagon/cpu.h | 4 ++-- target/hppa/cpu.h | 5 ++--- target/i386/cpu.h | 4 ++-- target/loongarch/cpu.h | 6 ++---- target/m68k/cpu.h | 4 ++-- target/microblaze/cpu.h | 4 ++-- target/mips/cpu.h | 4 ++-- target/nios2/cpu.h | 4 ++-- target/openrisc/cpu.h | 5 ++--- target/ppc/cpu.h | 8 ++++---- target/ppc/helper_regs.c | 4 ++-- target/riscv/cpu.h | 4 ++-- target/riscv/cpu_helper.c | 4 ++-- target/rx/cpu.h | 4 ++-- target/s390x/cpu.h | 4 ++-- target/sh4/cpu.h | 4 ++-- target/sparc/cpu.h | 4 ++-- target/tricore/cpu.h | 4 ++-- target/xtensa/cpu.h | 4 ++-- 26 files changed, 58 insertions(+), 58 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index f1eae7b8e5..47fbbcb16d 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -410,7 +410,8 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) { CPUState *cpu =3D env_cpu(env); TranslationBlock *tb; - target_ulong cs_base, pc; + vaddr pc; + uint64_t cs_base; uint32_t flags, cflags; =20 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); @@ -531,7 +532,8 @@ void cpu_exec_step_atomic(CPUState *cpu) { CPUArchState *env =3D cpu->env_ptr; TranslationBlock *tb; - target_ulong cs_base, pc; + vaddr pc; + uint64_t cs_base; uint32_t flags, cflags; int tb_exit; =20 @@ -944,7 +946,8 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) =20 while (!cpu_handle_interrupt(cpu, &last_tb)) { TranslationBlock *tb; - target_ulong cs_base, pc; + vaddr pc; + uint64_t cs_base; uint32_t flags, cflags; =20 cpu_get_tb_cpu_state(cpu->env_ptr, &pc, &cs_base, &flags); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 6a40bb83be..5b2c8aba42 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -583,7 +583,8 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t retad= dr) /* The exception probably happened in a helper. The CPU state sho= uld have been saved before calling it. Fetch the PC from there. */ CPUArchState *env =3D cpu->env_ptr; - target_ulong pc, cs_base; + vaddr pc; + uint64_t cs_base; tb_page_addr_t addr; uint32_t flags; =20 diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 5e67304d81..fcd20bfd3a 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -462,8 +462,8 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, MemTxResult response, uintptr_t retad= dr); #endif =20 -static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *= pc, - target_ulong *cs_base, uint32_t *p= flags) +static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflag= s) { *pc =3D env->pc; *cs_base =3D 0; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d469a2637b..3b495f9bc8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3123,8 +3123,8 @@ static inline bool arm_cpu_bswap_data(CPUARMState *en= v) } #endif =20 -void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *flags); +void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags); =20 enum { QEMU_PSCI_CONDUIT_DISABLED =3D 0, diff --git a/target/arm/helper.c b/target/arm/helper.c index 2297626bfb..549a0b4678 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11838,8 +11838,8 @@ static bool mve_no_pred(CPUARMState *env) return true; } =20 -void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *pflags) +void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) { CPUARMTBFlags flags; =20 diff --git a/target/avr/cpu.h b/target/avr/cpu.h index f19dd72926..7225174668 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -190,8 +190,8 @@ enum { TB_FLAGS_SKIP =3D 2, }; =20 -static inline void cpu_get_tb_cpu_state(CPUAVRState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *p= flags) +static inline void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflag= s) { uint32_t flags =3D 0; =20 diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 71fa1f96e0..8e37c6e50d 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -266,8 +266,8 @@ static inline int cpu_mmu_index (CPUCRISState *env, boo= l ifetch) =20 #include "exec/cpu-all.h" =20 -static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *p= c, - target_ulong *cs_base, uint32_t *f= lags) +static inline void cpu_get_tb_cpu_state(CPUCRISState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) { *pc =3D env->pc; *cs_base =3D 0; diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 81b663ecfb..d60b2d6949 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -152,8 +152,8 @@ struct ArchCPU { =20 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) =20 -static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, target_ulong= *pc, - target_ulong *cs_base, uint32_t *f= lags) +static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) { uint32_t hex_flags =3D 0; *pc =3D env->gpr[HEX_REG_PC]; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index b595ef25a9..7373177b55 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -268,9 +268,8 @@ static inline target_ulong hppa_form_gva(CPUHPPAState *= env, uint64_t spc, #define TB_FLAG_PRIV_SHIFT 8 #define TB_FLAG_UNALIGN 0x400 =20 -static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *p= c, - target_ulong *cs_base, - uint32_t *pflags) +static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflag= s) { uint32_t flags =3D env->psw_n * PSW_N; =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8504aaac68..e6ffb870a6 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2257,8 +2257,8 @@ static inline int cpu_mmu_index_kernel(CPUX86State *e= nv) #include "hw/i386/apic.h" #endif =20 -static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *f= lags) +static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) { *cs_base =3D env->segs[R_CS].base; *pc =3D *cs_base + env->eip; diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index e11c875188..d9ff94e74d 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -401,10 +401,8 @@ static inline int cpu_mmu_index(CPULoongArchState *env= , bool ifetch) #define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */ #define HW_FLAGS_EUEN_FPE 0x04 =20 -static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, - target_ulong *pc, - target_ulong *cs_base, - uint32_t *flags) +static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) { *pc =3D env->pc; *cs_base =3D 0; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 048d5aae2b..cf70282717 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -601,8 +601,8 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr p= hysaddr, vaddr addr, #define TB_FLAGS_TRACE 16 #define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE) =20 -static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *p= c, - target_ulong *cs_base, uint32_t *f= lags) +static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) { *pc =3D env->pc; *cs_base =3D 0; diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 88324d0bc1..3525de144c 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -401,8 +401,8 @@ void mb_tcg_init(void); /* Ensure there is no overlap between the two masks. */ QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK); =20 -static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *f= lags) +static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) { *pc =3D env->pc; *flags =3D (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 142c55af47..a3bc646976 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1313,8 +1313,8 @@ void itc_reconfigure(struct MIPSITUState *tag); /* helper.c */ target_ulong exception_resume_pc(CPUMIPSState *env); =20 -static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *p= c, - target_ulong *cs_base, uint32_t *f= lags) +static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) { *pc =3D env->active_tc.PC; *cs_base =3D 0; diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 20042c4332..477a3161fd 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -302,8 +302,8 @@ FIELD(TBFLAGS, CRS0, 0, 1) /* Set if CRS =3D=3D 0. */ FIELD(TBFLAGS, U, 1, 1) /* Overlaps CR_STATUS_U */ FIELD(TBFLAGS, R0_0, 2, 1) /* Set if R0 =3D=3D 0. */ =20 -static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *= pc, - target_ulong *cs_base, uint32_t *f= lags) +static inline void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) { unsigned crs =3D FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS); =20 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index f16e8b3274..92c38f54c2 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -367,9 +367,8 @@ static inline void cpu_set_gpr(CPUOpenRISCState *env, i= nt i, uint32_t val) env->shadow_gpr[0][i] =3D val; } =20 -static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, - target_ulong *pc, - target_ulong *cs_base, uint32_t *f= lags) +static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) { *pc =3D env->pc; *cs_base =3D 0; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 395b1c1cdf..ab4becfb3d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2502,11 +2502,11 @@ void cpu_write_xer(CPUPPCState *env, target_ulong x= er); #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B)) =20 #ifdef CONFIG_DEBUG_TCG -void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *flags); +void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags); #else -static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *f= lags) +static inline void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) { *pc =3D env->nip; *cs_base =3D 0; diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 779e7db513..cb0c36d81c 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -181,8 +181,8 @@ void hreg_compute_hflags(CPUPPCState *env) } =20 #ifdef CONFIG_DEBUG_TCG -void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *flags) +void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) { uint32_t hflags_current =3D env->hflags; uint32_t hflags_rebuilt; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 638e47c75a..d6eee2a90e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -739,8 +739,8 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, ta= rget_ulong vtype) return cpu->cfg.vlen >> (sew + 3 - lmul); } =20 -void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *pflags); +void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags); =20 void riscv_cpu_update_mask(CPURISCVState *env); =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 7b9744be1e..ff61908542 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -41,8 +41,8 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #endif } =20 -void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *pflags) +void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) { CPUState *cs =3D env_cpu(env); RISCVCPU *cpu =3D RISCV_CPU(cs); diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 555d230f24..7f03ffcfed 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -143,8 +143,8 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, i= nt rte); #define RX_CPU_IRQ 0 #define RX_CPU_FIR 1 =20 -static inline void cpu_get_tb_cpu_state(CPURXState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *f= lags) +static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) { *pc =3D env->pc; *cs_base =3D 0; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index c47e7adcb1..23ed2c058e 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -381,8 +381,8 @@ static inline int cpu_mmu_index(CPUS390XState *env, boo= l ifetch) #endif } =20 -static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *= pc, - target_ulong *cs_base, uint32_t *f= lags) +static inline void cpu_get_tb_cpu_state(CPUS390XState* env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) { if (env->psw.addr & 1) { /* diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 02bfd612ea..1399d3840f 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -368,8 +368,8 @@ static inline void cpu_write_sr(CPUSH4State *env, targe= t_ulong sr) env->sr =3D sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); } =20 -static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *f= lags) +static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) { *pc =3D env->pc; /* For a gUSA region, notice the end of the region. */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 3d090e8278..95d2d0da71 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -762,8 +762,8 @@ trap_state* cpu_tsptr(CPUSPARCState* env); #define TB_FLAG_HYPER (1 << 7) #define TB_FLAG_ASI_SHIFT 24 =20 -static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *= pc, - target_ulong *cs_base, uint32_t *p= flags) +static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflag= s) { uint32_t flags; *pc =3D env->pc; diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 47d0ffb745..6071186319 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -363,8 +363,8 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, b= ool ifetch) void cpu_state_reset(CPUTriCoreState *s); void tricore_tcg_init(void); =20 -static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong= *pc, - target_ulong *cs_base, uint32_t *f= lags) +static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) { *pc =3D env->PC; *cs_base =3D 0; diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index b7a54711a6..87fe992ba6 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -727,8 +727,8 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bo= ol ifetch) =20 #include "exec/cpu-all.h" =20 -static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong = *pc, - target_ulong *cs_base, uint32_t *flags) +static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) { *pc =3D env->pc; *cs_base =3D 0; --=20 2.39.1 From nobody Sat May 18 12:12:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=V5ffV9SSPwFx62K4rO9fNvLrDiYFOpxdwGg3FwtMzwA=; b=EEUc7WltXdDr72wsTpuwx2EMVL D3n6hX7knDLTFTDszl5o9SK8p+iHsOpi7o+3bs7im86//y54svOFZAk/sC4p9FNzhw5FDKK+I5rtm KEQyZc6pQxli/48kleMZ2M6S8Dw9rALA7Jl3m1hfSAbiPIRTXPJnq6GmutsZz/9/H82Q=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, philmd@linaro.org, marcel.apfelbaum@gmail.com, wangyanan55@huawei.com Subject: [PATCH v2 04/12] accel/tcg/cputlb.c: Widen CPUTLBEntry access functions Date: Fri, 5 May 2023 16:13:55 +0200 Message-Id: <20230505141403.25735-5-anjo@rev.ng> In-Reply-To: <20230505141403.25735-1-anjo@rev.ng> References: <20230505141403.25735-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683296146786100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- accel/tcg/cputlb.c | 8 ++++---- include/exec/cpu_ldst.h | 10 +++++----- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 4807f1836d..38c2edb19a 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1453,7 +1453,7 @@ static bool victim_tlb_hit(CPUArchState *env, size_t = mmu_idx, size_t index, assert_cpu_is_self(env_cpu(env)); for (vidx =3D 0; vidx < CPU_VTLB_SIZE; ++vidx) { CPUTLBEntry *vtlb =3D &env_tlb(env)->d[mmu_idx].vtable[vidx]; - target_ulong cmp =3D tlb_read_idx(vtlb, access_type); + uint64_t cmp =3D tlb_read_idx(vtlb, access_type); =20 if (cmp =3D=3D page) { /* Found entry in victim tlb, swap tlb and iotlb. */ @@ -1507,7 +1507,7 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, { uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr =3D tlb_read_idx(entry, access_type); + uint64_t tlb_addr =3D tlb_read_idx(entry, access_type); target_ulong page_addr =3D addr & TARGET_PAGE_MASK; int flags =3D TLB_FLAGS_MASK; =20 @@ -1694,7 +1694,7 @@ bool tlb_plugin_lookup(CPUState *cpu, vaddr addr, int= mmu_idx, CPUArchState *env =3D cpu->env_ptr; CPUTLBEntry *tlbe =3D tlb_entry(env, mmu_idx, addr); uintptr_t index =3D tlb_index(env, mmu_idx, addr); - vaddr tlb_addr =3D is_store ? tlb_addr_write(tlbe) : tlbe->addr_read; + uint64_t tlb_addr =3D is_store ? tlb_addr_write(tlbe) : tlbe->addr_rea= d; =20 if (likely(tlb_hit(tlb_addr, addr))) { /* We must have an iotlb entry for MMIO */ @@ -1759,7 +1759,7 @@ static bool mmu_lookup1(CPUArchState *env, MMULookupP= ageData *data, target_ulong addr =3D data->addr; uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); - target_ulong tlb_addr =3D tlb_read_idx(entry, access_type); + uint64_t tlb_addr =3D tlb_read_idx(entry, access_type); bool maybe_resized =3D false; =20 /* If the TLB entry is for a different page, reload and try again. */ diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 59abab7421..7b23790b2c 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -359,8 +359,8 @@ static inline void clear_helper_retaddr(void) =20 #include "tcg/oversized-guest.h" =20 -static inline target_ulong tlb_read_idx(const CPUTLBEntry *entry, - MMUAccessType access_type) +static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry, + MMUAccessType access_type) { /* Do not rearrange the CPUTLBEntry structure members. */ QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_read) !=3D @@ -386,14 +386,14 @@ static inline target_ulong tlb_read_idx(const CPUTLBE= ntry *entry, #endif } =20 -static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry) +static inline uint64_t tlb_addr_write(const CPUTLBEntry *entry) { return tlb_read_idx(entry, MMU_DATA_STORE); } =20 /* Find the TLB index corresponding to the mmu_idx + address pair. */ static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx, - target_ulong addr) + vaddr addr) { uintptr_t size_mask =3D env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY= _BITS; =20 @@ -402,7 +402,7 @@ static inline uintptr_t tlb_index(CPUArchState *env, ui= ntptr_t mmu_idx, =20 /* Find the TLB entry corresponding to the mmu_idx + address pair. */ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, - target_ulong addr) + vaddr addr) { return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)]; } --=20 2.39.1 From nobody Sat May 18 12:12:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1683296223; 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bh=Jl+9uIHBuoQ94iJWD2OfDbohcMB+30msieRSc5sJsZI=; b=eH+9gxp5NH5fF+TWY62KKnzW2K 3ADhXzrqCeib10GEhNRd+latk+Cm0L6+k2MlU/fk3DTcncDgV/J+ONt/CenwITtVa9jV7NvdaRoGJ Wl67dLW2dy0HmCSwmbPAVWacFBiTMHIxByA2mr3nJxoxu4lVbF0Ylh7cAdciWwuQNbIc=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, philmd@linaro.org, marcel.apfelbaum@gmail.com, wangyanan55@huawei.com Subject: [PATCH v2 05/12] accel/tcg/cputlb.c: Widen addr in MMULookupPageData Date: Fri, 5 May 2023 16:13:56 +0200 Message-Id: <20230505141403.25735-6-anjo@rev.ng> In-Reply-To: <20230505141403.25735-1-anjo@rev.ng> References: <20230505141403.25735-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683296224132100001 Content-Type: text/plain; charset="utf-8" Functions accessing MMULookupPageData are also updated. Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- accel/tcg/cputlb.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 38c2edb19a..d6f8bed9f0 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1729,7 +1729,7 @@ bool tlb_plugin_lookup(CPUState *cpu, vaddr addr, int= mmu_idx, typedef struct MMULookupPageData { CPUTLBEntryFull *full; void *haddr; - target_ulong addr; + vaddr addr; int flags; int size; } MMULookupPageData; @@ -1756,7 +1756,7 @@ typedef struct MMULookupLocals { static bool mmu_lookup1(CPUArchState *env, MMULookupPageData *data, int mmu_idx, MMUAccessType access_type, uintptr_t = ra) { - target_ulong addr =3D data->addr; + vaddr addr =3D data->addr; uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); uint64_t tlb_addr =3D tlb_read_idx(entry, access_type); @@ -1796,7 +1796,7 @@ static void mmu_watch_or_dirty(CPUArchState *env, MMU= LookupPageData *data, MMUAccessType access_type, uintptr_t ra) { CPUTLBEntryFull *full =3D data->full; - target_ulong addr =3D data->addr; + vaddr addr =3D data->addr; int flags =3D data->flags; int size =3D data->size; =20 @@ -1826,7 +1826,7 @@ static void mmu_watch_or_dirty(CPUArchState *env, MMU= LookupPageData *data, * Resolve the translation for the page(s) beginning at @addr, for MemOp.s= ize * bytes. Return true if the lookup crosses a page boundary. */ -static bool mmu_lookup(CPUArchState *env, target_ulong addr, MemOpIdx oi, +static bool mmu_lookup(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType type, MMULookupLocals *= l) { unsigned a_bits; @@ -2046,7 +2046,7 @@ static uint64_t do_ld_mmio_beN(CPUArchState *env, MMU= LookupPageData *p, MMUAccessType type, uintptr_t ra) { CPUTLBEntryFull *full =3D p->full; - target_ulong addr =3D p->addr; + vaddr addr =3D p->addr; int i, size =3D p->size; =20 QEMU_IOTHREAD_LOCK_GUARD(); @@ -2346,7 +2346,7 @@ static uint64_t do_ld_8(CPUArchState *env, MMULookupP= ageData *p, int mmu_idx, return ret; } =20 -static uint8_t do_ld1_mmu(CPUArchState *env, target_ulong addr, MemOpIdx o= i, +static uint8_t do_ld1_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType access_type) { MMULookupLocals l; @@ -2365,7 +2365,7 @@ tcg_target_ulong helper_ldub_mmu(CPUArchState *env, u= int64_t addr, return do_ld1_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); } =20 -static uint16_t do_ld2_mmu(CPUArchState *env, target_ulong addr, MemOpIdx = oi, +static uint16_t do_ld2_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType access_type) { MMULookupLocals l; @@ -2396,7 +2396,7 @@ tcg_target_ulong helper_lduw_mmu(CPUArchState *env, u= int64_t addr, return do_ld2_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); } =20 -static uint32_t do_ld4_mmu(CPUArchState *env, target_ulong addr, MemOpIdx = oi, +static uint32_t do_ld4_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType access_type) { MMULookupLocals l; @@ -2423,7 +2423,7 @@ tcg_target_ulong helper_ldul_mmu(CPUArchState *env, u= int64_t addr, return do_ld4_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); } =20 -static uint64_t do_ld8_mmu(CPUArchState *env, target_ulong addr, MemOpIdx = oi, +static uint64_t do_ld8_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType access_type) { MMULookupLocals l; @@ -2473,7 +2473,7 @@ tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, u= int64_t addr, return (int32_t)helper_ldul_mmu(env, addr, oi, retaddr); } =20 -static Int128 do_ld16_mmu(CPUArchState *env, target_ulong addr, +static Int128 do_ld16_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra) { MMULookupLocals l; @@ -2674,7 +2674,7 @@ static uint64_t do_st_mmio_leN(CPUArchState *env, MMU= LookupPageData *p, uint64_t val_le, int mmu_idx, uintptr_t ra) { CPUTLBEntryFull *full =3D p->full; - target_ulong addr =3D p->addr; + vaddr addr =3D p->addr; int i, size =3D p->size; =20 QEMU_IOTHREAD_LOCK_GUARD(); @@ -2856,7 +2856,7 @@ void helper_stb_mmu(CPUArchState *env, uint64_t addr,= uint32_t val, do_st_1(env, &l.page[0], val, l.mmu_idx, ra); } =20 -static void do_st2_mmu(CPUArchState *env, target_ulong addr, uint16_t val, +static void do_st2_mmu(CPUArchState *env, vaddr addr, uint16_t val, MemOpIdx oi, uintptr_t ra) { MMULookupLocals l; @@ -2885,7 +2885,7 @@ void helper_stw_mmu(CPUArchState *env, uint64_t addr,= uint32_t val, do_st2_mmu(env, addr, val, oi, retaddr); } =20 -static void do_st4_mmu(CPUArchState *env, target_ulong addr, uint32_t val, +static void do_st4_mmu(CPUArchState *env, vaddr addr, uint32_t val, MemOpIdx oi, uintptr_t ra) { MMULookupLocals l; @@ -2912,7 +2912,7 @@ void helper_stl_mmu(CPUArchState *env, uint64_t addr,= uint32_t val, do_st4_mmu(env, addr, val, oi, retaddr); } =20 -static void do_st8_mmu(CPUArchState *env, target_ulong addr, uint64_t val, +static void do_st8_mmu(CPUArchState *env, vaddr addr, uint64_t val, MemOpIdx oi, uintptr_t ra) { MMULookupLocals l; @@ -2939,7 +2939,7 @@ void helper_stq_mmu(CPUArchState *env, uint64_t addr,= uint64_t val, do_st8_mmu(env, addr, val, oi, retaddr); } =20 -static void do_st16_mmu(CPUArchState *env, target_ulong addr, Int128 val, +static void do_st16_mmu(CPUArchState *env, vaddr addr, Int128 val, MemOpIdx oi, uintptr_t ra) { MMULookupLocals l; --=20 2.39.1 From nobody Sat May 18 12:12:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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Fri, 5 May 2023 07:16:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1puwCU-0004tW-Pz; Fri, 05 May 2023 10:14:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1puwCS-0004sQ-WC for qemu-devel@nongnu.org; Fri, 05 May 2023 10:14:21 -0400 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1puwCO-0000yM-AD for qemu-devel@nongnu.org; Fri, 05 May 2023 10:14:20 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=kjKy7U6kLgNK8+tOqUmnfQR2wq8lZPq3Y3fztA+Rsow=; b=tADV7+LAJGrhDdxLmfFnJkSaM4 +UlOI59DYVCanyObmYW1dFGCScH4BlGX9g3mbuRC9J9FqUYLoeOZNO5ZLaq1xlW35g774shdsvUUE NwykiSfjZ2vzu0a6VCOR0R6DTyI7izzXh1yfqX8PA0XVTN/zPey04Pe7pUqqkQhvoi8c=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, philmd@linaro.org, marcel.apfelbaum@gmail.com, wangyanan55@huawei.com Subject: [PATCH v2 06/12] accel/tcg/cpu-exec.c: Widen pc to vaddr Date: Fri, 5 May 2023 16:13:57 +0200 Message-Id: <20230505141403.25735-7-anjo@rev.ng> In-Reply-To: <20230505141403.25735-1-anjo@rev.ng> References: <20230505141403.25735-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683296218139100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- accel/tcg/cpu-exec.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 47fbbcb16d..4c56924711 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -169,8 +169,8 @@ uint32_t curr_cflags(CPUState *cpu) } =20 struct tb_desc { - target_ulong pc; - target_ulong cs_base; + vaddr pc; + uint64_t cs_base; CPUArchState *env; tb_page_addr_t page_addr0; uint32_t flags; @@ -195,7 +195,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) return true; } else { tb_page_addr_t phys_page1; - target_ulong virt_page1; + vaddr virt_page1; =20 /* * We know that the first page matched, and an otherwise valid= TB @@ -216,8 +216,8 @@ static bool tb_lookup_cmp(const void *p, const void *d) return false; } =20 -static TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, - target_ulong cs_base, uint32_t f= lags, +static TranslationBlock *tb_htable_lookup(CPUState *cpu, vaddr pc, + uint64_t cs_base, uint32_t flags, uint32_t cflags) { tb_page_addr_t phys_pc; @@ -241,9 +241,9 @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu= , target_ulong pc, } =20 /* Might cause an exception, so have a longjmp destination ready */ -static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc, - target_ulong cs_base, - uint32_t flags, uint32_t cflags) +static inline TranslationBlock *tb_lookup(CPUState *cpu, vaddr pc, + uint64_t cs_base, uint32_t flags, + uint32_t cflags) { TranslationBlock *tb; CPUJumpCache *jc; @@ -297,13 +297,13 @@ static inline TranslationBlock *tb_lookup(CPUState *c= pu, target_ulong pc, return tb; } =20 -static void log_cpu_exec(target_ulong pc, CPUState *cpu, +static void log_cpu_exec(vaddr pc, CPUState *cpu, const TranslationBlock *tb) { if (qemu_log_in_addr_range(pc)) { qemu_log_mask(CPU_LOG_EXEC, "Trace %d: %p [%08" PRIx64 - "/" TARGET_FMT_lx "/%08x/%08x] %s\n", + "/%" VADDR_PRIx "/%08x/%08x] %s\n", cpu->cpu_index, tb->tc.ptr, tb->cs_base, pc, tb->flags, tb->cflags, lookup_symbol(pc)); =20 @@ -325,7 +325,7 @@ static void log_cpu_exec(target_ulong pc, CPUState *cpu, } } =20 -static bool check_for_breakpoints_slow(CPUState *cpu, target_ulong pc, +static bool check_for_breakpoints_slow(CPUState *cpu, vaddr pc, uint32_t *cflags) { CPUBreakpoint *bp; @@ -391,7 +391,7 @@ static bool check_for_breakpoints_slow(CPUState *cpu, t= arget_ulong pc, return false; } =20 -static inline bool check_for_breakpoints(CPUState *cpu, target_ulong pc, +static inline bool check_for_breakpoints(CPUState *cpu, vaddr pc, uint32_t *cflags) { return unlikely(!QTAILQ_EMPTY(&cpu->breakpoints)) && @@ -487,10 +487,10 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int= *tb_exit) cc->set_pc(cpu, last_tb->pc); } if (qemu_loglevel_mask(CPU_LOG_EXEC)) { - target_ulong pc =3D log_pc(cpu, last_tb); + vaddr pc =3D log_pc(cpu, last_tb); if (qemu_log_in_addr_range(pc)) { - qemu_log("Stopped execution of TB chain before %p [" - TARGET_FMT_lx "] %s\n", + qemu_log("Stopped execution of TB chain before %p [%" + VADDR_PRIx "] %s\n", last_tb->tc.ptr, pc, lookup_symbol(pc)); } } @@ -884,8 +884,8 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, } =20 static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, - target_ulong pc, - TranslationBlock **last_tb, int *tb_ex= it) + vaddr pc, TranslationBlock **last_tb, + int *tb_exit) { int32_t insns_left; =20 --=20 2.39.1 From nobody Sat May 18 12:12:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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Fri, 5 May 2023 07:15:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1puwCZ-0004ur-IK; Fri, 05 May 2023 10:14:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1puwCU-0004tO-BA for qemu-devel@nongnu.org; Fri, 05 May 2023 10:14:22 -0400 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1puwCO-0000yU-JQ for qemu-devel@nongnu.org; Fri, 05 May 2023 10:14:22 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=+htCIQ7w4aGVM7u95J+OASj5h6/N/fkJHboFXJOqH4Y=; b=oI4X37NSCFM3+lGzKtaNTBQWOr 6lq8QYwqmi4H7sJvaWFxYVEcwOq/JbfYAqLdD7mb6X5H+AyRfEjZ8iNABrWFe8L76yNSM2KF8MSzi Baq7GSy9xf58pbY4nJ2PJNztkIdtBrvJrpZgHVo2crHWBdrfqew1Fx4K/xFtlXr8qz2A=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, philmd@linaro.org, marcel.apfelbaum@gmail.com, wangyanan55@huawei.com Subject: [PATCH v2 07/12] accel/tcg: Widen pc to vaddr in CPUJumpCache Date: Fri, 5 May 2023 16:13:58 +0200 Message-Id: <20230505141403.25735-8-anjo@rev.ng> In-Reply-To: <20230505141403.25735-1-anjo@rev.ng> References: <20230505141403.25735-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683296147961100011 Content-Type: text/plain; charset="utf-8" Related functions dealing with the jump cache are also updated. Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- accel/tcg/cputlb.c | 2 +- accel/tcg/tb-hash.h | 12 ++++++------ accel/tcg/tb-jmp-cache.h | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d6f8bed9f0..3a400cb0cd 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -99,7 +99,7 @@ static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns, desc->window_max_entries =3D max_entries; } =20 -static void tb_jmp_cache_clear_page(CPUState *cpu, target_ulong page_addr) +static void tb_jmp_cache_clear_page(CPUState *cpu, vaddr page_addr) { CPUJumpCache *jc =3D cpu->tb_jmp_cache; int i, i0; diff --git a/accel/tcg/tb-hash.h b/accel/tcg/tb-hash.h index 83dc610e4c..f560d3b0bb 100644 --- a/accel/tcg/tb-hash.h +++ b/accel/tcg/tb-hash.h @@ -35,16 +35,16 @@ #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1) #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE) =20 -static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) +static inline unsigned int tb_jmp_cache_hash_page(vaddr pc) { - target_ulong tmp; + vaddr tmp; tmp =3D pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MA= SK; } =20 -static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) +static inline unsigned int tb_jmp_cache_hash_func(vaddr pc) { - target_ulong tmp; + vaddr tmp; tmp =3D pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_= MASK) | (tmp & TB_JMP_ADDR_MASK)); @@ -53,7 +53,7 @@ static inline unsigned int tb_jmp_cache_hash_func(target_= ulong pc) #else =20 /* In user-mode we can get better hashing because we do not have a TLB */ -static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) +static inline unsigned int tb_jmp_cache_hash_func(vaddr pc) { return (pc ^ (pc >> TB_JMP_CACHE_BITS)) & (TB_JMP_CACHE_SIZE - 1); } @@ -61,7 +61,7 @@ static inline unsigned int tb_jmp_cache_hash_func(target_= ulong pc) #endif /* CONFIG_SOFTMMU */ =20 static inline -uint32_t tb_hash_func(tb_page_addr_t phys_pc, target_ulong pc, uint32_t fl= ags, +uint32_t tb_hash_func(tb_page_addr_t phys_pc, vaddr pc, uint32_t flags, uint32_t cf_mask, uint32_t trace_vcpu_dstate) { return qemu_xxhash7(phys_pc, pc, flags, cf_mask, trace_vcpu_dstate); diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h index bee87eb840..bb424c8a05 100644 --- a/accel/tcg/tb-jmp-cache.h +++ b/accel/tcg/tb-jmp-cache.h @@ -21,7 +21,7 @@ struct CPUJumpCache { struct rcu_head rcu; struct { TranslationBlock *tb; - target_ulong pc; + vaddr pc; } array[TB_JMP_CACHE_SIZE]; }; =20 --=20 2.39.1 From nobody Sat May 18 12:12:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1683296154; cv=none; d=zohomail.com; s=zohoarc; b=MBsmzHPkPnGMx0F7TVkBXsRVcmc5RmmRdCIS1yB/Yguwufmz6TvqgH8QyzGDX/1o/nmqCdN7OUjPETjrEHy3xDvkj/+EU890fYbqFp2xlvv2v8OMYEuiYojuXJFGppFQC2pQtyWsHbFU2y8HOn34YDr+ob7XfVxCexk8tjLOY3M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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Fri, 05 May 2023 10:14:23 -0400 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1puwCP-0000yy-Ac for qemu-devel@nongnu.org; Fri, 05 May 2023 10:14:23 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=yNgS/NxH41+8C8c5+7zGjFAgCr6ogmUoNJwym7KRdZk=; b=Wk/81xMHoMFSeqTkJoH0vf3jRP XEBJjsvwaRBEUGvLuobkZKGPpj5c0gtobRwtl5gS2DgK/lWjNRyJsz11T28fl4hHHL4izdkOafL09 Hjr7QNI+HLhHG7wDBpzfpZeV8HZrody6QEa9jk42bgGXerZp8oyeWdO2JAILm4mzu4ZI=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, philmd@linaro.org, marcel.apfelbaum@gmail.com, wangyanan55@huawei.com Subject: [PATCH v2 08/12] accel: Replace target_ulong with vaddr in probe_*() Date: Fri, 5 May 2023 16:13:59 +0200 Message-Id: <20230505141403.25735-9-anjo@rev.ng> In-Reply-To: <20230505141403.25735-1-anjo@rev.ng> References: <20230505141403.25735-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683296154536100001 Content-Type: text/plain; charset="utf-8" Functions for probing memory accesses (and functions that call these) are updated to take a vaddr for guest virtual addresses over target_ulong. Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- accel/stubs/tcg-stub.c | 4 ++-- accel/tcg/cputlb.c | 12 ++++++------ accel/tcg/user-exec.c | 8 ++++---- include/exec/exec-all.h | 14 +++++++------- 4 files changed, 19 insertions(+), 19 deletions(-) diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c index 0998e601ad..a9e7a2d5b4 100644 --- a/accel/stubs/tcg-stub.c +++ b/accel/stubs/tcg-stub.c @@ -26,14 +26,14 @@ void tcg_flush_jmp_cache(CPUState *cpu) { } =20 -int probe_access_flags(CPUArchState *env, target_ulong addr, int size, +int probe_access_flags(CPUArchState *env, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr) { g_assert_not_reached(); } =20 -void *probe_access(CPUArchState *env, target_ulong addr, int size, +void *probe_access(CPUArchState *env, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retad= dr) { /* Handled by hardware accelerator. */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 3a400cb0cd..138ce7e697 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1499,7 +1499,7 @@ static void notdirty_write(CPUState *cpu, vaddr mem_v= addr, unsigned size, } } =20 -static int probe_access_internal(CPUArchState *env, target_ulong addr, +static int probe_access_internal(CPUArchState *env, vaddr addr, int fault_size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, CPUTLBEntryFull **pfull, @@ -1508,7 +1508,7 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); uint64_t tlb_addr =3D tlb_read_idx(entry, access_type); - target_ulong page_addr =3D addr & TARGET_PAGE_MASK; + vaddr page_addr =3D addr & TARGET_PAGE_MASK; int flags =3D TLB_FLAGS_MASK; =20 if (!tlb_hit_page(tlb_addr, page_addr)) { @@ -1551,7 +1551,7 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, return flags; } =20 -int probe_access_full(CPUArchState *env, target_ulong addr, int size, +int probe_access_full(CPUArchState *env, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, CPUTLBEntryFull **pfull, uintptr_t retaddr) @@ -1568,7 +1568,7 @@ int probe_access_full(CPUArchState *env, target_ulong= addr, int size, return flags; } =20 -int probe_access_flags(CPUArchState *env, target_ulong addr, int size, +int probe_access_flags(CPUArchState *env, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr) { @@ -1589,7 +1589,7 @@ int probe_access_flags(CPUArchState *env, target_ulon= g addr, int size, return flags; } =20 -void *probe_access(CPUArchState *env, target_ulong addr, int size, +void *probe_access(CPUArchState *env, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retad= dr) { CPUTLBEntryFull *full; @@ -1648,7 +1648,7 @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr ad= dr, * NOTE: This function will trigger an exception if the page is * not executable. */ -tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong ad= dr, +tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, vaddr addr, void **hostp) { CPUTLBEntryFull *full; diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 36ad8284a5..3b92432df9 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -721,7 +721,7 @@ int page_unprotect(target_ulong address, uintptr_t pc) return current_tb_invalidated ? 2 : 1; } =20 -static int probe_access_internal(CPUArchState *env, target_ulong addr, +static int probe_access_internal(CPUArchState *env, vaddr addr, int fault_size, MMUAccessType access_type, bool nonfault, uintptr_t ra) { @@ -759,7 +759,7 @@ static int probe_access_internal(CPUArchState *env, tar= get_ulong addr, cpu_loop_exit_sigsegv(env_cpu(env), addr, access_type, maperr, ra); } =20 -int probe_access_flags(CPUArchState *env, target_ulong addr, int size, +int probe_access_flags(CPUArchState *env, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t ra) { @@ -771,7 +771,7 @@ int probe_access_flags(CPUArchState *env, target_ulong = addr, int size, return flags; } =20 -void *probe_access(CPUArchState *env, target_ulong addr, int size, +void *probe_access(CPUArchState *env, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t ra) { int flags; @@ -783,7 +783,7 @@ void *probe_access(CPUArchState *env, target_ulong addr= , int size, return size ? g2h(env_cpu(env), addr) : NULL; } =20 -tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong ad= dr, +tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, vaddr addr, void **hostp) { int flags; diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f5508e242b..cc1c3556f6 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -413,16 +413,16 @@ static inline void tlb_flush_range_by_mmuidx_all_cpus= _synced(CPUState *cpu, * Finally, return the host address for a page that is backed by RAM, * or NULL if the page requires I/O. */ -void *probe_access(CPUArchState *env, target_ulong addr, int size, +void *probe_access(CPUArchState *env, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, uintptr_t retad= dr); =20 -static inline void *probe_write(CPUArchState *env, target_ulong addr, int = size, +static inline void *probe_write(CPUArchState *env, vaddr addr, int size, int mmu_idx, uintptr_t retaddr) { return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); } =20 -static inline void *probe_read(CPUArchState *env, target_ulong addr, int s= ize, +static inline void *probe_read(CPUArchState *env, vaddr addr, int size, int mmu_idx, uintptr_t retaddr) { return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); @@ -447,7 +447,7 @@ static inline void *probe_read(CPUArchState *env, targe= t_ulong addr, int size, * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags. * For simplicity, all "mmio-like" flags are folded to TLB_MMIO. */ -int probe_access_flags(CPUArchState *env, target_ulong addr, int size, +int probe_access_flags(CPUArchState *env, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, uintptr_t retaddr); =20 @@ -460,7 +460,7 @@ int probe_access_flags(CPUArchState *env, target_ulong = addr, int size, * and must be consumed or copied immediately, before any further * access or changes to TLB @mmu_idx. */ -int probe_access_full(CPUArchState *env, target_ulong addr, int size, +int probe_access_full(CPUArchState *env, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, CPUTLBEntryFull **pfull, uintptr_t retaddr); @@ -581,7 +581,7 @@ struct MemoryRegionSection *iotlb_to_section(CPUState *= cpu, * * Note: this function can trigger an exception. */ -tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong ad= dr, +tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, vaddr addr, void **hostp); =20 /** @@ -596,7 +596,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *e= nv, target_ulong addr, * Note: this function can trigger an exception. */ static inline tb_page_addr_t get_page_addr_code(CPUArchState *env, - target_ulong addr) + vaddr addr) { return get_page_addr_code_hostp(env, addr, NULL); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683296146467100005 Content-Type: text/plain; charset="utf-8" Update atomic_mmu_lookup() and cpu_mmu_lookup() to take the guest virtual address as a vaddr instead of a target_ulong. Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- accel/tcg/cputlb.c | 4 ++-- accel/tcg/user-exec.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 138ce7e697..fb97786dac 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1899,7 +1899,7 @@ static bool mmu_lookup(CPUArchState *env, vaddr addr,= MemOpIdx oi, * * @prot may be PAGE_READ, PAGE_WRITE, or PAGE_READ|PAGE_WRITE. */ -static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, +static void *atomic_mmu_lookup(CPUArchState *env, vaddr addr, MemOpIdx oi, int size, int prot, uintptr_t retaddr) { @@ -1908,7 +1908,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, int a_bits =3D get_alignment_bits(mop); uintptr_t index; CPUTLBEntry *tlbe; - target_ulong tlb_addr; + vaddr tlb_addr; void *hostaddr; CPUTLBEntryFull *full; =20 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 3b92432df9..929f1a4f43 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -889,7 +889,7 @@ void page_reset_target_data(target_ulong start, target_= ulong last) { } =20 /* The softmmu versions of these helpers are in cputlb.c. */ =20 -static void *cpu_mmu_lookup(CPUArchState *env, abi_ptr addr, +static void *cpu_mmu_lookup(CPUArchState *env, vaddr addr, MemOp mop, uintptr_t ra, MMUAccessType type) { int a_bits =3D get_alignment_bits(mop); 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To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, philmd@linaro.org, marcel.apfelbaum@gmail.com, wangyanan55@huawei.com Subject: [PATCH v2 10/12] accel/tcg: Replace target_ulong with vaddr in translator_*() Date: Fri, 5 May 2023 16:14:01 +0200 Message-Id: <20230505141403.25735-11-anjo@rev.ng> In-Reply-To: <20230505141403.25735-1-anjo@rev.ng> References: <20230505141403.25735-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683296156221100005 Content-Type: text/plain; charset="utf-8" Use vaddr for guest virtual address in translator_use_goto_tb() and translator_loop(). Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- accel/tcg/translator.c | 10 +++++----- include/exec/translator.h | 6 +++--- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 918a455e73..0fd9efceba 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -117,7 +117,7 @@ static void gen_tb_end(const TranslationBlock *tb, uint= 32_t cflags, } } =20 -bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest) +bool translator_use_goto_tb(DisasContextBase *db, vaddr dest) { /* Suppress goto_tb if requested. */ if (tb_cflags(db->tb) & CF_NO_GOTO_TB) { @@ -129,8 +129,8 @@ bool translator_use_goto_tb(DisasContextBase *db, targe= t_ulong dest) } =20 void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc, - const TranslatorOps *ops, DisasContextBase *db) + vaddr pc, void *host_pc, const TranslatorOps *ops, + DisasContextBase *db) { uint32_t cflags =3D tb_cflags(tb); TCGOp *icount_start_insn; @@ -235,10 +235,10 @@ void translator_loop(CPUState *cpu, TranslationBlock = *tb, int *max_insns, } =20 static void *translator_access(CPUArchState *env, DisasContextBase *db, - target_ulong pc, size_t len) + vaddr pc, size_t len) { void *host; - target_ulong base, end; + vaddr base, end; TranslationBlock *tb; =20 tb =3D db->tb; diff --git a/include/exec/translator.h b/include/exec/translator.h index 224ae14aa7..a53d3243d4 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -142,8 +142,8 @@ typedef struct TranslatorOps { * - When too many instructions have been translated. */ void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc, - const TranslatorOps *ops, DisasContextBase *db); + vaddr pc, void *host_pc, const TranslatorOps *ops, + DisasContextBase *db); =20 /** * translator_use_goto_tb @@ -153,7 +153,7 @@ void translator_loop(CPUState *cpu, TranslationBlock *t= b, int *max_insns, * Return true if goto_tb is allowed between the current TB * and the destination PC. */ -bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest); +bool translator_use_goto_tb(DisasContextBase *db, vaddr dest); =20 /** * translator_io_start --=20 2.39.1 From nobody Sat May 18 12:12:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1683296225; cv=none; d=zohomail.com; s=zohoarc; b=gbDDnY0ZvPsD+Resfp+/GJ++otcDO/9ya1OtGHBX0gELpVJWRSpILzvuBBG3WKVfAmGmZUZQ5mgTBMYjKTHJUWclCf1kiTW7WKKlp4RFK0JaX9aVCNZaZM6q3deTy77yY8QqwuEtkydtAUafgIfVq4GmbdsLX6ete8Z+YNDMaco= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683296225; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=KmmB2+qkXOef6UkE18/YVECwrR7Ove13nzv5ZIouuRY=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683296226448100009 Content-Type: text/plain; charset="utf-8" Use vaddr for guest virtual addresses for functions dealing with page flags. Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- accel/tcg/user-exec.c | 44 +++++++++++++++++------------------- include/exec/cpu-all.h | 10 ++++---- include/exec/translate-all.h | 2 +- 3 files changed, 27 insertions(+), 29 deletions(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 929f1a4f43..ae2ff4d223 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -144,7 +144,7 @@ typedef struct PageFlagsNode { =20 static IntervalTreeRoot pageflags_root; =20 -static PageFlagsNode *pageflags_find(target_ulong start, target_long last) +static PageFlagsNode *pageflags_find(vaddr start, vaddr last) { IntervalTreeNode *n; =20 @@ -152,8 +152,7 @@ static PageFlagsNode *pageflags_find(target_ulong start= , target_long last) return n ? container_of(n, PageFlagsNode, itree) : NULL; } =20 -static PageFlagsNode *pageflags_next(PageFlagsNode *p, target_ulong start, - target_long last) +static PageFlagsNode *pageflags_next(PageFlagsNode *p, vaddr start, vaddr = last) { IntervalTreeNode *n; =20 @@ -205,7 +204,7 @@ void page_dump(FILE *f) walk_memory_regions(f, dump_region); } =20 -int page_get_flags(target_ulong address) +int page_get_flags(vaddr address) { PageFlagsNode *p =3D pageflags_find(address, address); =20 @@ -228,7 +227,7 @@ int page_get_flags(target_ulong address) } =20 /* A subroutine of page_set_flags: insert a new node for [start,last]. */ -static void pageflags_create(target_ulong start, target_ulong last, int fl= ags) +static void pageflags_create(vaddr start, vaddr last, int flags) { PageFlagsNode *p =3D g_new(PageFlagsNode, 1); =20 @@ -239,13 +238,13 @@ static void pageflags_create(target_ulong start, targ= et_ulong last, int flags) } =20 /* A subroutine of page_set_flags: remove everything in [start,last]. */ -static bool pageflags_unset(target_ulong start, target_ulong last) +static bool pageflags_unset(vaddr start, vaddr last) { bool inval_tb =3D false; =20 while (true) { PageFlagsNode *p =3D pageflags_find(start, last); - target_ulong p_last; + vaddr p_last; =20 if (!p) { break; @@ -284,8 +283,7 @@ static bool pageflags_unset(target_ulong start, target_= ulong last) * A subroutine of page_set_flags: nothing overlaps [start,last], * but check adjacent mappings and maybe merge into a single range. */ -static void pageflags_create_merge(target_ulong start, target_ulong last, - int flags) +static void pageflags_create_merge(vaddr start, vaddr last, int flags) { PageFlagsNode *next =3D NULL, *prev =3D NULL; =20 @@ -336,11 +334,11 @@ static void pageflags_create_merge(target_ulong start= , target_ulong last, #define PAGE_STICKY (PAGE_ANON | PAGE_PASSTHROUGH | PAGE_TARGET_STICKY) =20 /* A subroutine of page_set_flags: add flags to [start,last]. */ -static bool pageflags_set_clear(target_ulong start, target_ulong last, +static bool pageflags_set_clear(vaddr start, vaddr last, int set_flags, int clear_flags) { PageFlagsNode *p; - target_ulong p_start, p_last; + vaddr p_start, p_last; int p_flags, merge_flags; bool inval_tb =3D false; =20 @@ -480,7 +478,7 @@ static bool pageflags_set_clear(target_ulong start, tar= get_ulong last, * The flag PAGE_WRITE_ORG is positioned automatically depending * on PAGE_WRITE. The mmap_lock should already be held. */ -void page_set_flags(target_ulong start, target_ulong last, int flags) +void page_set_flags(vaddr start, vaddr last, int flags) { bool reset =3D false; bool inval_tb =3D false; @@ -520,9 +518,9 @@ void page_set_flags(target_ulong start, target_ulong la= st, int flags) } } =20 -int page_check_range(target_ulong start, target_ulong len, int flags) +int page_check_range(vaddr start, vaddr len, int flags) { - target_ulong last; + vaddr last; int locked; /* tri-state: =3D0: unlocked, +1: global, -1: local */ int ret; =20 @@ -601,7 +599,7 @@ int page_check_range(target_ulong start, target_ulong l= en, int flags) void page_protect(tb_page_addr_t address) { PageFlagsNode *p; - target_ulong start, last; + vaddr start, last; int prot; =20 assert_memory_lock(); @@ -642,7 +640,7 @@ void page_protect(tb_page_addr_t address) * immediately exited. (We can only return 2 if the 'pc' argument is * non-zero.) */ -int page_unprotect(target_ulong address, uintptr_t pc) +int page_unprotect(vaddr address, uintptr_t pc) { PageFlagsNode *p; bool current_tb_invalidated; @@ -676,7 +674,7 @@ int page_unprotect(target_ulong address, uintptr_t pc) } #endif } else { - target_ulong start, len, i; + vaddr start, len, i; int prot; =20 if (qemu_host_page_size <=3D TARGET_PAGE_SIZE) { @@ -691,7 +689,7 @@ int page_unprotect(target_ulong address, uintptr_t pc) prot =3D 0; =20 for (i =3D 0; i < len; i +=3D TARGET_PAGE_SIZE) { - target_ulong addr =3D start + i; + vaddr addr =3D start + i; =20 p =3D pageflags_find(addr, addr); if (p) { @@ -814,7 +812,7 @@ typedef struct TargetPageDataNode { =20 static IntervalTreeRoot targetdata_root; =20 -void page_reset_target_data(target_ulong start, target_ulong last) +void page_reset_target_data(vaddr start, vaddr last) { IntervalTreeNode *n, *next; =20 @@ -828,7 +826,7 @@ void page_reset_target_data(target_ulong start, target_= ulong last) n !=3D NULL; n =3D next, next =3D next ? interval_tree_iter_next(n, start, last) : NULL) { - target_ulong n_start, n_last, p_ofs, p_len; + vaddr n_start, n_last, p_ofs, p_len; TargetPageDataNode *t =3D container_of(n, TargetPageDataNode, itre= e); =20 if (n->start >=3D start && n->last <=3D last) { @@ -851,11 +849,11 @@ void page_reset_target_data(target_ulong start, targe= t_ulong last) } } =20 -void *page_get_target_data(target_ulong address) +void *page_get_target_data(vaddr address) { IntervalTreeNode *n; TargetPageDataNode *t; - target_ulong page, region; + vaddr page, region; =20 page =3D address & TARGET_PAGE_MASK; region =3D address & TBD_MASK; @@ -884,7 +882,7 @@ void *page_get_target_data(target_ulong address) return t->data[(page - region) >> TARGET_PAGE_BITS]; } #else -void page_reset_target_data(target_ulong start, target_ulong last) { } +void page_reset_target_data(vaddr start, vaddr last) { } #endif /* TARGET_PAGE_DATA_SIZE */ =20 /* The softmmu versions of these helpers are in cputlb.c. */ diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 09bf4c0cc6..97be7c2c3c 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -219,10 +219,10 @@ typedef int (*walk_memory_regions_fn)(void *, target_= ulong, target_ulong, unsigned long); int walk_memory_regions(void *, walk_memory_regions_fn); =20 -int page_get_flags(target_ulong address); -void page_set_flags(target_ulong start, target_ulong last, int flags); -void page_reset_target_data(target_ulong start, target_ulong last); -int page_check_range(target_ulong start, target_ulong len, int flags); +int page_get_flags(vaddr address); +void page_set_flags(vaddr start, vaddr last, int flags); +void page_reset_target_data(vaddr start, vaddr last); +int page_check_range(vaddr start, vaddr len, int flags); =20 /** * page_get_target_data(address) @@ -235,7 +235,7 @@ int page_check_range(target_ulong start, target_ulong l= en, int flags); * The memory will be freed when the guest page is deallocated, * e.g. with the munmap system call. */ -void *page_get_target_data(target_ulong address) +void *page_get_target_data(vaddr address) __attribute__((returns_nonnull)); #endif =20 diff --git a/include/exec/translate-all.h b/include/exec/translate-all.h index 88602ae8d8..0b9d2e3b32 100644 --- a/include/exec/translate-all.h +++ b/include/exec/translate-all.h @@ -28,7 +28,7 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr= ); =20 #ifdef CONFIG_USER_ONLY void page_protect(tb_page_addr_t page_addr); -int page_unprotect(target_ulong address, uintptr_t pc); +int page_unprotect(vaddr address, uintptr_t pc); #endif =20 #endif /* TRANSLATE_ALL_H */ --=20 2.39.1 From nobody Sat May 18 12:12:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1683296223; cv=none; d=zohomail.com; s=zohoarc; b=TRQFIVGvNCDEEsf8Io7kHeGYi5aZpMZ8Y1vj5HQM7ErKY1YlWHUyvB65yqyO3dX71aRvpcN1V9163nlNJ6slFQP7zbaw6kFK9k3txDtgRaek/evRI9nmnGT/FUmM9nH76xz9X44D07+pJuOJ9ydxm4OcABq9RVhmXNujAl/u/jY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683296223; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; 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Fri, 05 May 2023 10:14:36 -0400 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1puwCb-00010g-BO for qemu-devel@nongnu.org; Fri, 05 May 2023 10:14:35 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=dlpRQ2jRDGOdUkvKHivyblICDZNlUWBs4xQwg4Ks3rA=; b=OUOHpU723EQFl5lG7wKbB00wrg +8yp7/YE21PpXw5VAao6HvasvafgDIvcQxV0naH32DIHvp9BpI2CcXpwTtOAZz9mmiPIdRhhbMe8F 3Cu8T2jYq1lyHiH7Zj9sQkPXccW2idm0BOch2m9MgGQyRyHOsAaDqgaIFqwFAOfF3KSw=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, philmd@linaro.org, marcel.apfelbaum@gmail.com, wangyanan55@huawei.com Subject: [PATCH v2 12/12] cpu: Replace target_ulong with hwaddr in tb_invalidate_phys_addr() Date: Fri, 5 May 2023 16:14:03 +0200 Message-Id: <20230505141403.25735-13-anjo@rev.ng> In-Reply-To: <20230505141403.25735-1-anjo@rev.ng> References: <20230505141403.25735-1-anjo@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683296224731100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Anton Johansson Reviewed-by: Richard Henderson --- cpu.c | 2 +- include/exec/exec-all.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu.c b/cpu.c index 9105c85404..41150a6136 100644 --- a/cpu.c +++ b/cpu.c @@ -293,7 +293,7 @@ void list_cpus(void) } =20 #if defined(CONFIG_USER_ONLY) -void tb_invalidate_phys_addr(target_ulong addr) +void tb_invalidate_phys_addr(hwaddr addr) { mmap_lock(); tb_invalidate_phys_page(addr); diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index cc1c3556f6..200c27eadf 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -526,7 +526,7 @@ uint32_t curr_cflags(CPUState *cpu); =20 /* TranslationBlock invalidate API */ #if defined(CONFIG_USER_ONLY) -void tb_invalidate_phys_addr(target_ulong addr); +void tb_invalidate_phys_addr(hwaddr addr); #else void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs att= rs); #endif --=20 2.39.1