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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.03.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:03:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248599; x=1685840599; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cRmIoFl2e8CRrWTPkl6Y/zweMYKh21Ri0y8chZO7848=; b=bl5+m1JZk67/dyNQIUlEAervOpEQw36Xg3QHhLi0pA6ZCN8l3+65Urk5ifKpZQdFmn e/+EdPrDInlXh5mxAOyVlhoBtI13pZcC5uOWvKKxmXDWlTILmWSd10wG9b8kMOBUnvtT 2I8cc85v6faxeQnJ1X9DiOb1vqtzY+48wSB7QBqcu+xGdoUn0nirImnlAP0vWsvLochQ aEEg1OF/t1iD/japa6q4UkRiEkS3RHTAijyIk7XvjKFdtDyr9T1SOO90cgS/TgRMsjaI lISUkFBQvMrDtSAFctElgoQhRGL0EmFVUY9nX0TOu3eePq3cqTZy34Jp/6mRrcB57UlK P5Uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248599; x=1685840599; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cRmIoFl2e8CRrWTPkl6Y/zweMYKh21Ri0y8chZO7848=; b=BUWvOx1qBE+zwMuDnyLphFHtEk2EFegIP0263R8ufiMY9a34/F6heMPTw0sv+xmUPY dDmbOkFVc4C2GVq0DSLLwO7RGk+IUG+kabrDCH4N91ZOfzQubAfYf7Cmf9Slj3cjX+FS tu2gLgJk1fTlaMgENrc/H4ZLT6r7wQVoKt6RjZovhz7BPp3l2lmSvLUm+Fl8Fe9YqW8Q fCpglGw/8Ej1HC5T1j8YZ55sNlHHrf1s7Yiec9DtRUlRw/YSH8E4Xs66AsXiqxzj70Gm aGE4INBO3yEAE9dM+fUMPphQVO/ty7RbTDw0C7FlUR0oCOdLMyFvVrC3PrTnDmvjFgzy fgRg== X-Gm-Message-State: AC+VfDwMGpxMFtKmaWmDYXGm51UF0i0Kj9+iXiEa9sL9VfpMmWKJzYRD ARTGY/0eSv3pwvAboSbUd/Gq8h0gX1d0Vw== X-Google-Smtp-Source: ACHHUZ6wHzX3uEv1YaEkJSG6CnGoi08dhd6ix4kI6+arf2vcVEkieWAbKqtbpMuMW3QUSpzO+pZLPA== X-Received: by 2002:a17:903:41c6:b0:1aa:e739:4097 with SMTP id u6-20020a17090341c600b001aae7394097mr6466656ple.5.1683248598990; Thu, 04 May 2023 18:03:18 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Alistair Francis , Daniel Henrique Barboza Subject: [PULL 01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig Date: Fri, 5 May 2023 11:01:13 +1000 Message-Id: <20230505010241.21812-2-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=alistair23@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248630584100007 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Use riscv_cpu_cfg(env) instead of env_archcpu().cfg. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-Id: <20230309071329.45932-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 9 ++++----- target/riscv/csr.c | 40 ++++++++++++--------------------------- target/riscv/gdbstub.c | 4 ++-- 3 files changed, 18 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f88c503cf4..e677255f87 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -314,7 +314,6 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env, int extirq, unsigned int extirq_def_pr= io, uint64_t pending, uint8_t *iprio) { - RISCVCPU *cpu =3D env_archcpu(env); int irq, best_irq =3D RISCV_EXCP_NONE; unsigned int prio, best_prio =3D UINT_MAX; =20 @@ -323,7 +322,8 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env, } =20 irq =3D ctz64(pending); - if (!((extirq =3D=3D IRQ_M_EXT) ? cpu->cfg.ext_smaia : cpu->cfg.ext_ss= aia)) { + if (!((extirq =3D=3D IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : + riscv_cpu_cfg(env)->ext_ssaia)) { return irq; } =20 @@ -765,7 +765,6 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, int mode =3D mmu_idx & TB_FLAGS_PRIV_MMU_MASK; bool use_background =3D false; hwaddr ppn; - RISCVCPU *cpu =3D env_archcpu(env); int napot_bits =3D 0; target_ulong napot_mask; =20 @@ -946,7 +945,7 @@ restart: =20 if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { ppn =3D pte >> PTE_PPN_SHIFT; - } else if (pbmte || cpu->cfg.ext_svnapot) { + } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) { ppn =3D (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; } else { ppn =3D pte >> PTE_PPN_SHIFT; @@ -1043,7 +1042,7 @@ restart: benefit. */ target_ulong vpn =3D addr >> PGSHIFT; =20 - if (cpu->cfg.ext_svnapot && (pte & PTE_N)) { + if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { napot_bits =3D ctzl(ppn) + 1; if ((i !=3D (levels - 1)) || (napot_bits !=3D 4)) { return TRANSLATE_FAIL; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d522efc0b6..70468572fe 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -89,9 +89,7 @@ static RISCVException fs(CPURISCVState *env, int csrno) =20 static RISCVException vs(CPURISCVState *env, int csrno) { - RISCVCPU *cpu =3D env_archcpu(env); - - if (cpu->cfg.ext_zve32f) { + if (riscv_cpu_cfg(env)->ext_zve32f) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_vector_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; @@ -194,9 +192,7 @@ static RISCVException mctr32(CPURISCVState *env, int cs= rno) =20 static RISCVException sscofpmf(CPURISCVState *env, int csrno) { - RISCVCPU *cpu =3D env_archcpu(env); - - if (!cpu->cfg.ext_sscofpmf) { + if (!riscv_cpu_cfg(env)->ext_sscofpmf) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -311,9 +307,7 @@ static RISCVException umode32(CPURISCVState *env, int c= srno) =20 static RISCVException mstateen(CPURISCVState *env, int csrno) { - RISCVCPU *cpu =3D env_archcpu(env); - - if (!cpu->cfg.ext_smstateen) { + if (!riscv_cpu_cfg(env)->ext_smstateen) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -322,9 +316,7 @@ static RISCVException mstateen(CPURISCVState *env, int = csrno) =20 static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int bas= e) { - RISCVCPU *cpu =3D env_archcpu(env); - - if (!cpu->cfg.ext_smstateen) { + if (!riscv_cpu_cfg(env)->ext_smstateen) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -391,10 +383,9 @@ static RISCVException sstateen(CPURISCVState *env, int= csrno) =20 static RISCVException sstc(CPURISCVState *env, int csrno) { - RISCVCPU *cpu =3D env_archcpu(env); bool hmode_check =3D false; =20 - if (!cpu->cfg.ext_sstc || !env->rdtime_fn) { + if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -1171,27 +1162,21 @@ static RISCVException write_ignore(CPURISCVState *e= nv, int csrno, static RISCVException read_mvendorid(CPURISCVState *env, int csrno, target_ulong *val) { - RISCVCPU *cpu =3D env_archcpu(env); - - *val =3D cpu->cfg.mvendorid; + *val =3D riscv_cpu_cfg(env)->mvendorid; return RISCV_EXCP_NONE; } =20 static RISCVException read_marchid(CPURISCVState *env, int csrno, target_ulong *val) { - RISCVCPU *cpu =3D env_archcpu(env); - - *val =3D cpu->cfg.marchid; + *val =3D riscv_cpu_cfg(env)->marchid; return RISCV_EXCP_NONE; } =20 static RISCVException read_mimpid(CPURISCVState *env, int csrno, target_ulong *val) { - RISCVCPU *cpu =3D env_archcpu(env); - - *val =3D cpu->cfg.mimpid; + *val =3D riscv_cpu_cfg(env)->mimpid; return RISCV_EXCP_NONE; } =20 @@ -1233,9 +1218,8 @@ static RISCVException read_mstatus(CPURISCVState *env= , int csrno, =20 static bool validate_vm(CPURISCVState *env, target_ulong vm) { - RISCVCPU *cpu =3D RISCV_CPU(env_cpu(env)); - - return (vm & 0xf) <=3D satp_mode_max_from_map(cpu->cfg.satp_mode.map); + return (vm & 0xf) <=3D + satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map); } =20 static RISCVException write_mstatus(CPURISCVState *env, int csrno, @@ -1898,7 +1882,7 @@ static RISCVException read_menvcfg(CPURISCVState *env= , int csrno, static RISCVException write_menvcfg(CPURISCVState *env, int csrno, target_ulong val) { - RISCVCPUConfig *cfg =3D &env_archcpu(env)->cfg; + const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); uint64_t mask =3D MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCF= G_CBZE; =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { @@ -1921,7 +1905,7 @@ static RISCVException read_menvcfgh(CPURISCVState *en= v, int csrno, static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, target_ulong val) { - RISCVCPUConfig *cfg =3D &env_archcpu(env)->cfg; + const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); uint64_t mask =3D (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | (cfg->ext_svadu ? MENVCFG_HADE : 0); diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 840d1ec5c6..692bbb64f6 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -130,7 +130,7 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_= t *mem_buf, int n) =20 static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n) { - uint16_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; + uint16_t vlenb =3D riscv_cpu_cfg(env)->vlen >> 3; if (n < 32) { int i; int cnt =3D 0; @@ -146,7 +146,7 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GBy= teArray *buf, int n) =20 static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int = n) { - uint16_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; + uint16_t vlenb =3D riscv_cpu_cfg(env)->vlen >> 3; if (n < 32) { int i; for (i =3D 0; i < vlenb; i +=3D 8) { --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248645; cv=none; d=zohomail.com; s=zohoarc; b=F3CUZ+g81gTakzvd2Yb1M97SVMm8jiExl+rVkbNd/RgUyUClxA21H/oEBeyqphfpFVv/yW74AN28n+xiWYNsu3Oi+SGSsvupM7SfEEU6cs/ei2liS+hdsKUoTxzXaogQf/xM4PpgPWB/wgUKLMaS2JWbGpz9IhWXbb5/RSIno24= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248645; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VUdrhXPjbgTbybk94uAMNTrh0ZDyzc4ZvWsfq2o302w=; b=TtACZBcqyWsz4rCfRpItCnDToEq/pGXLllt2OYF287mANKxVzlCgO3dQQyTVBboE2B6cPGXx/ScNf41sAWGFJ4LmZ/8e3MFGYdIfrCv2OMokCIhoGrYDEIFW/gjnfIUqqX2CfNUdlaUI9TlgJUK4fgrSdDSWqn9TjEPa+eAzYuQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683248645691754.6298421129331; Thu, 4 May 2023 18:04:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujr6-0007w9-2H; Thu, 04 May 2023 21:03:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujr4-0007vf-Qh for qemu-devel@nongnu.org; Thu, 04 May 2023 21:03:27 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujr3-0006qI-63 for qemu-devel@nongnu.org; Thu, 04 May 2023 21:03:26 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-6439d505274so193179b3a.0 for ; Thu, 04 May 2023 18:03:24 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.03.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:03:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248602; x=1685840602; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VUdrhXPjbgTbybk94uAMNTrh0ZDyzc4ZvWsfq2o302w=; b=AabQLGG08cVe4ubBD2irYFjXj3/n6OLdzSOGzyCm/A5pgvfU47XEcO1mc5B456QTIB kLiauCE2rZ8lFm4vtWnPd/jpclNJVXFQ6SKApiKigQro5Bxq3B3tM+z0YW8PhT/9TRck PitgLj4/CqJOzA5kMnRnc+eD6PLMkN+9VU9v8hC67ayiG2wRhEJeuZ/0GTPtlVL3F5PU Ov2riEW2sBco1yZ9uQxHX/2ApIf48k6SK6VIVy8D/ndRnPjGWgdZCwyPAVjG2dMkcu7q v5thEp5bESrZJvt/38gbldOOtwmCGxFIHmCI0QPRy4PtHORN9PuR6NXtJzOqEg3Y2m77 6dfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248602; x=1685840602; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VUdrhXPjbgTbybk94uAMNTrh0ZDyzc4ZvWsfq2o302w=; b=drB7zIHjZ+Mp7n5h7qRlkG8PTuJjumPiR1Sqzw+BLoU4VY9tAFYTrj0Av1qsVPwKg8 ybwznRDRk/beU2Hc8evLJHgT8DF86tvmA3U5usQNwQTPdyVCBdEjea3Ut4frTgTokVyQ Iq+0QQzQeV7xbIjByCm2VY+pr/Vf5DcjC2R1YZS7iaxc5C/ynxat+zYedmEFnuQjQfZQ R1xDGJ79QbGE8o/Wj7myLbO2NtmfBJD81+5MRdt7cTnvTiUCIcrjg7JjZfxyyN5LxMY7 cmguQj1fbHzQiKTaq56IA5XR+XWAyxl1u3X6i1535EEUpBe0xEpQeJEoWBJ1wzWiihWQ nx2A== X-Gm-Message-State: AC+VfDwDdF9PY9sKH9Ls4fLmXCFm0REmuCnnlt86pgisYoewR5xLZNdH jdHHm2TnCHY8GkpTF1PYb7CNlADCgFvr0A== X-Google-Smtp-Source: ACHHUZ5s5cH9HER7NS7BC4h/0TyiP84C1F5KSjDjyHRMdopFTAn0/6MuxrgkmCnwpbAw/DhpaCecdw== X-Received: by 2002:a05:6a20:a688:b0:f2:afd5:e52e with SMTP id ba8-20020a056a20a68800b000f2afd5e52emr4172364pzb.33.1683248602518; Thu, 04 May 2023 18:03:22 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, LIU Zhiwei , Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 02/89] target/riscv: Fix priv version dependency for vector and zfh Date: Fri, 5 May 2023 11:01:14 +1000 Message-Id: <20230505010241.21812-3-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=alistair23@gmail.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248647564100003 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei Vector implicitly enables zve64d, zve64f, zve32f sub extensions. As vector only requires PRIV_1_10_0, these sub extensions should not require priv ver= sion higher than that. The same for Zfh. Signed-off-by: LIU Zhiwei Reviewed-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Message-Id: <20230321043415.754-1-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e97473af2..eaf75a00a6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -84,7 +84,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintp= ause), ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh), - ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), + ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_11_0, ext_zfhmin), ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), @@ -104,9 +104,9 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), - ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), - ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), - ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_12_0, ext_zve64d), + ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_10_0, ext_zve32f), + ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_10_0, ext_zve64f), + ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_10_0, ext_zve64d), ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh), ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248640; cv=none; d=zohomail.com; s=zohoarc; b=kyRFv8BbA08rPGiSMlhEinzP6FZvfnfWih3IrfePM1ygQFJaYVIz9XOJxeoqZu661yCXHEu0hOM0SmAcXZ0zdEVdAy3Bx9390jKUJLcwliGbjwBHoa60dZYMV94pzJsGBSgHGBNzEgIyyP6Xe08a94w0V5NA5Of0D4j8a+ZNNrE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248640; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YPIznLJlFld2/pzlq8rqnzqjocmMSn/cjAgHK7fzxjI=; b=PPSQF6f0/uhzxUDcKcOS/qxYdkJBUTxChZt9Wbb61DmKT9ojhsN+oMQ/gt1DqDYs0bSFV5c1L7UB8bPjBLSLaqPY5scU0N6MS8TET2ypiW1fLH1ieEQo4fLLD+xTtfQiHzyzqbLOjGm+hA+7DKDq1hAFIBtaYXYmLSaqgevPNOk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683248640043486.16206810918607; Thu, 4 May 2023 18:04:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujr9-0007wk-V2; Thu, 04 May 2023 21:03:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujr7-0007wT-TI for qemu-devel@nongnu.org; Thu, 04 May 2023 21:03:29 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujr6-0006qw-6p for qemu-devel@nongnu.org; Thu, 04 May 2023 21:03:29 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1ab01bf474aso8549495ad.1 for ; Thu, 04 May 2023 18:03:27 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.03.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:03:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248606; x=1685840606; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YPIznLJlFld2/pzlq8rqnzqjocmMSn/cjAgHK7fzxjI=; b=OnGVxOQqdO9w6IA0BLy9bXAzeLrJUwDoIYS6tkqNwzfRK9sVboTaDT2JJSpiN+rR0I tu16lDNxuBKCbDM7eimwOPUn0zgm/I1bRCs7INVV4vYVf1hL8TDaNbiEsP50MCRk7CvD YatVeTuJdfFIT68lr4JBB7ORcMxSg0ZhvakfyiwHHKa6lRMaUf22mD0iAHuo/GCEII4E KZblelGiI/W/dNM6SR5dIzUIszPXR/Ts6oNgdFpYkRes5lVT3MXKFxmrKWzkWw47Huz3 Dws2v7GLS/gybiqK/xkR99qaEa5bLfYwxBppuwy3OR5FfOs22RDPbjKlaUjQ+t4wg/AZ XerA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248606; x=1685840606; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YPIznLJlFld2/pzlq8rqnzqjocmMSn/cjAgHK7fzxjI=; b=GRmW34RAMun4qqrlTdfFdCAGwEz2IXzjnAgifT61zLY9K28xlb/5hfHbAm4ivtVtCg OuU2Gl844ZZKT7cIeXJzYhhdWgUL/Xt5wC/TprvNNQtj621YUeu+pX/59oerWoc1mHQn nr+hICwHX4BVSHWzwzvKoNbSC63poLyECcM5M9FwUta35hjF9q5L6laCCbZNt9pDVSJj ixcuoQfvQI8CjqJaBCgX/vVG3v6zFIVtDBYipUlMf5N37EhFdTS43jXatdUAWefK1gmU NipldU39MqQUuJEV+TlvhQVfuZBiC99Z2AN3BMTGek+q4Dn31CsJJHmATb3abnowPwG2 WUSw== X-Gm-Message-State: AC+VfDxXIyitXtQ0DPaGyny4fJb/wRUuBsvN/MrPwI5XvMWIxNQvXLZe aVbt9+CEV5sfFBorzjGIvb+DmomZCqyW3w== X-Google-Smtp-Source: ACHHUZ5AcJx8EoSADQDuMdRRAyIvnRNLacQXlFfGUNK8+pIwNhcRhyIUBfkiJ6zKGti2OArua8HYSg== X-Received: by 2002:a17:903:258a:b0:1ab:19db:f2b with SMTP id jb10-20020a170903258a00b001ab19db0f2bmr6257527plb.36.1683248606463; Thu, 04 May 2023 18:03:26 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Alistair Francis , Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 03/89] target/riscv: Simplify getting RISCVCPU pointer from env Date: Fri, 5 May 2023 11:01:15 +1000 Message-Id: <20230505010241.21812-4-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=alistair23@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248641663100003 From: Weiwei Li Use env_archcpu() to get RISCVCPU pointer from env directly. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20230309071329.45932-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/pmu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index b8e56d2b7b..a200741083 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -223,7 +223,7 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *= env, return true; } =20 - cpu =3D RISCV_CPU(env_cpu(env)); + cpu =3D env_archcpu(env); if (!cpu->pmu_event_ctr_map) { return false; } @@ -249,7 +249,7 @@ bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, u= int32_t target_ctr) return true; } =20 - cpu =3D RISCV_CPU(env_cpu(env)); + cpu =3D env_archcpu(env); if (!cpu->pmu_event_ctr_map) { return false; } @@ -289,7 +289,7 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uint= 64_t value, uint32_t ctr_idx) { uint32_t event_idx; - RISCVCPU *cpu =3D RISCV_CPU(env_cpu(env)); + RISCVCPU *cpu =3D env_archcpu(env); =20 if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map)= { return -1; @@ -390,7 +390,7 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t = value, uint32_t ctr_idx) { uint64_t overflow_delta, overflow_at; int64_t overflow_ns, overflow_left =3D 0; - RISCVCPU *cpu =3D RISCV_CPU(env_cpu(env)); + RISCVCPU *cpu =3D env_archcpu(env); PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; =20 if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscofpmf) { --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248685; cv=none; d=zohomail.com; s=zohoarc; b=IfNnR5/uIoartNOgY3YyrfHpQwUaFbRge4rMqt3Moske5pBR2gZeSfFyXLrIFUs8wTKX6hcX54fGCN6akcP7RTF9undi3Cy4HWWBj//N2vgNH0mbUd0OTFQP3U4BRSDWuVR9WE5WieQe8T/EDuCAaRwwbpr7J3jNtS9s19TXEkk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248685; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=APTyY3hc2vM0RicVRK0p1IL56eRDbDC/MUZ7Ub4+IDE=; b=eyK0PaEHdNfH8g4V09k586jqZY6umnkZ6CtGTn3L7oF/B5DXOqiGd/11odCXXc4n14Bhk+OivPxqcdczVBz+irnbugHf1JzPdP1Ag8RdB/Lgcfl2DINrzPIKc0MtYgkEUwXNXrDqvGbfjqF5pxKGOCvPJeApKZmAZ8Rw6a+jf7Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683248685007252.78838599838878; Thu, 4 May 2023 18:04:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujrF-0007xZ-8K; Thu, 04 May 2023 21:03:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujrC-0007xA-2a for qemu-devel@nongnu.org; Thu, 04 May 2023 21:03:34 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujr9-0006rI-SO for qemu-devel@nongnu.org; Thu, 04 May 2023 21:03:33 -0400 Received: by mail-pg1-x534.google.com with SMTP id 41be03b00d2f7-51fcf5d1e44so998372a12.3 for ; Thu, 04 May 2023 18:03:31 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.03.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:03:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248610; x=1685840610; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=APTyY3hc2vM0RicVRK0p1IL56eRDbDC/MUZ7Ub4+IDE=; b=mwyf1sdvN/jAoLa4eFYb751oltYMLX8tYzQP5cSv1OSv9Nv4tTs6pDzC1ljqryppXJ P9e79NeKCwc0/KOnhwLNeuFGqAlASqZbFl6JrwjRgU6FphY4vBFJd7ZjgjtpL4Snsh+J Zr3H9aTq8eF/XATbnBFHClMGaAPGUQ/sVktf4vZPfZosL+UJ4uaHA6uwWegt+aqWI2Sk pv/bsEBcG4o1O+ZPTaqSyZfXYx8qBdSGomnBFmsUOQyHhLcaikdag+ndlELi2SGECt/3 fkhpwx4fc3zhAkjbNm6N4+vk4ID+ugCq6mJ9ZbPW3oAoNDCVKRNfmj9aFg4PnEb0+aal Wulg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248610; x=1685840610; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=APTyY3hc2vM0RicVRK0p1IL56eRDbDC/MUZ7Ub4+IDE=; b=GAsKqik9yO35unrc47KF172ra32KUf7jyJy8zq1qxB/KX/v8c2cV6TSwITVsvckzJd XpkXb9Vmsa+8htfISnCetRna7bUx+DnDYamfPoNzwIBPirgSw0Vq0v6XM23Af2KmJYgZ ezoOC0fboiWwDnbsdAj36wmq4C9MqddFXgQPRmWX9L79QB4vWdewUEgfADaLEDdvVCqz UMQ3t4nse+Tu1Q1+jlqvKIYocz15UMITgvLYRFbe0lO0w59lWNdXXMOffm7/UYzIVi2/ C8nSn31vt6710uPwuYHqZCt99K5u3z5KZ7e7GOogy+O4hUYsCGtcdxnXKpmzYZqsnQmF 47TA== X-Gm-Message-State: AC+VfDzpSncYaaCQ8vDdgcPhYzpHi08WkaQ9Hp2Ho9uVTngiZPjtedIA sfuHaLGLLGZLo2aSNRDh1N4V2hunTm+tng== X-Google-Smtp-Source: ACHHUZ4Fzy+HbNVhWT0V5bSjjFNG64mb5PxOuG3EH3q3jYSsO1kN1hsWIrSnm/YlrzTTe6jU45REBg== X-Received: by 2002:a17:902:f7cc:b0:1ab:1c09:2df8 with SMTP id h12-20020a170902f7cc00b001ab1c092df8mr4895047plw.50.1683248610101; Thu, 04 May 2023 18:03:30 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Alistair Francis , Daniel Henrique Barboza Subject: [PULL 04/89] target/riscv: Simplify type conversion for CPURISCVState Date: Fri, 5 May 2023 11:01:16 +1000 Message-Id: <20230505010241.21812-5-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=alistair23@gmail.com; helo=mail-pg1-x534.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248685620100003 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Use CPURISCVState as argument directly in riscv_cpu_update_mip and riscv_timer_write_timecmp, since type converts from CPURISCVState to RISCVCPU in many caller of them and then back to CPURISCVState in them. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-Id: <20230309071329.45932-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 ++- target/riscv/time_helper.h | 2 +- target/riscv/cpu.c | 6 +++--- target/riscv/cpu_helper.c | 8 ++++---- target/riscv/csr.c | 35 +++++++++++------------------------ target/riscv/pmu.c | 6 +++--- target/riscv/time_helper.c | 15 +++++++-------- 7 files changed, 31 insertions(+), 44 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 638e47c75a..5adefe4ab5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -602,7 +602,8 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vad= dr addr); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); -uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value= ); +uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, + uint64_t value); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), void *arg); diff --git a/target/riscv/time_helper.h b/target/riscv/time_helper.h index 7b3cdcc350..cacd79b80c 100644 --- a/target/riscv/time_helper.h +++ b/target/riscv/time_helper.h @@ -22,7 +22,7 @@ #include "cpu.h" #include "qemu/timer.h" =20 -void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer, +void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer, uint64_t timecmp, uint64_t delta, uint32_t timer_irq); void riscv_timer_init(RISCVCPU *cpu); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index eaf75a00a6..cea0d3cbdd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1302,7 +1302,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, = int level) if (kvm_enabled()) { kvm_riscv_set_irq(cpu, irq, level); } else { - riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); + riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level)); } break; case IRQ_S_EXT: @@ -1310,7 +1310,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, = int level) kvm_riscv_set_irq(cpu, irq, level); } else { env->external_seip =3D level; - riscv_cpu_update_mip(cpu, 1 << irq, + riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level | env->software_se= ip)); } break; @@ -1336,7 +1336,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, = int level) } =20 /* Update mip.SGEIP bit */ - riscv_cpu_update_mip(cpu, MIP_SGEIP, + riscv_cpu_update_mip(env, MIP_SGEIP, BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); } else { g_assert_not_reached(); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e677255f87..824f0cbd92 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -590,7 +590,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, boo= l enable) * * To solve this, we check and inject interrupt after setting V=3D= 1. */ - riscv_cpu_update_mip(env_archcpu(env), 0, 0); + riscv_cpu_update_mip(env, 0, 0); } } =20 @@ -610,10 +610,10 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_= t interrupts) } } =20 -uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value) +uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, + uint64_t value) { - CPURISCVState *env =3D &cpu->env; - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); uint64_t gein, vsgein =3D 0, vstip =3D 0, old =3D env->mip; =20 if (riscv_cpu_virt_enabled(env)) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 70468572fe..a7d0157d33 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -991,15 +991,13 @@ static RISCVException read_vstimecmph(CPURISCVState *= env, int csrno, static RISCVException write_vstimecmp(CPURISCVState *env, int csrno, target_ulong val) { - RISCVCPU *cpu =3D env_archcpu(env); - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { env->vstimecmp =3D deposit64(env->vstimecmp, 0, 32, (uint64_t)val); } else { env->vstimecmp =3D val; } =20 - riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp, + riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, env->htimedelta, MIP_VSTIP); =20 return RISCV_EXCP_NONE; @@ -1008,10 +1006,8 @@ static RISCVException write_vstimecmp(CPURISCVState = *env, int csrno, static RISCVException write_vstimecmph(CPURISCVState *env, int csrno, target_ulong val) { - RISCVCPU *cpu =3D env_archcpu(env); - env->vstimecmp =3D deposit64(env->vstimecmp, 32, 32, (uint64_t)val); - riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp, + riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, env->htimedelta, MIP_VSTIP); =20 return RISCV_EXCP_NONE; @@ -1044,8 +1040,6 @@ static RISCVException read_stimecmph(CPURISCVState *e= nv, int csrno, static RISCVException write_stimecmp(CPURISCVState *env, int csrno, target_ulong val) { - RISCVCPU *cpu =3D env_archcpu(env); - if (riscv_cpu_virt_enabled(env)) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; @@ -1059,7 +1053,7 @@ static RISCVException write_stimecmp(CPURISCVState *e= nv, int csrno, env->stimecmp =3D val; } =20 - riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP= ); + riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP= ); =20 return RISCV_EXCP_NONE; } @@ -1067,8 +1061,6 @@ static RISCVException write_stimecmp(CPURISCVState *e= nv, int csrno, static RISCVException write_stimecmph(CPURISCVState *env, int csrno, target_ulong val) { - RISCVCPU *cpu =3D env_archcpu(env); - if (riscv_cpu_virt_enabled(env)) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; @@ -1077,7 +1069,7 @@ static RISCVException write_stimecmph(CPURISCVState *= env, int csrno, } =20 env->stimecmp =3D deposit64(env->stimecmp, 32, 32, (uint64_t)val); - riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP= ); + riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP= ); =20 return RISCV_EXCP_NONE; } @@ -2212,7 +2204,6 @@ static RISCVException rmw_mip64(CPURISCVState *env, i= nt csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) { - RISCVCPU *cpu =3D env_archcpu(env); uint64_t old_mip, mask =3D wr_mask & delegable_ints; uint32_t gin; =20 @@ -2221,14 +2212,14 @@ static RISCVException rmw_mip64(CPURISCVState *env,= int csrno, new_val |=3D env->external_seip * MIP_SEIP; } =20 - if (cpu->cfg.ext_sstc && (env->priv =3D=3D PRV_M) && + if (riscv_cpu_cfg(env)->ext_sstc && (env->priv =3D=3D PRV_M) && get_field(env->menvcfg, MENVCFG_STCE)) { /* sstc extension forbids STIP & VSTIP to be writeable in mip */ mask =3D mask & ~(MIP_STIP | MIP_VSTIP); } =20 if (mask) { - old_mip =3D riscv_cpu_update_mip(cpu, mask, (new_val & mask)); + old_mip =3D riscv_cpu_update_mip(env, mask, (new_val & mask)); } else { old_mip =3D env->mip; } @@ -2988,7 +2979,7 @@ static RISCVException write_hgeie(CPURISCVState *env,= int csrno, val &=3D ((((target_ulong)1) << env->geilen) - 1) << 1; env->hgeie =3D val; /* Update mip.SGEIP bit */ - riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP, + riscv_cpu_update_mip(env, MIP_SGEIP, BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); return RISCV_EXCP_NONE; } @@ -3057,8 +3048,6 @@ static RISCVException read_htimedelta(CPURISCVState *= env, int csrno, static RISCVException write_htimedelta(CPURISCVState *env, int csrno, target_ulong val) { - RISCVCPU *cpu =3D env_archcpu(env); - if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; } @@ -3069,8 +3058,8 @@ static RISCVException write_htimedelta(CPURISCVState = *env, int csrno, env->htimedelta =3D val; } =20 - if (cpu->cfg.ext_sstc && env->rdtime_fn) { - riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp, + if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) { + riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, env->htimedelta, MIP_VSTIP); } =20 @@ -3091,16 +3080,14 @@ static RISCVException read_htimedeltah(CPURISCVStat= e *env, int csrno, static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val) { - RISCVCPU *cpu =3D env_archcpu(env); - if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; } =20 env->htimedelta =3D deposit64(env->htimedelta, 32, 32, (uint64_t)val); =20 - if (cpu->cfg.ext_sstc && env->rdtime_fn) { - riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp, + if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) { + riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, env->htimedelta, MIP_VSTIP); } =20 diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index a200741083..22e2283c76 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -133,7 +133,7 @@ static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint3= 2_t ctr_idx) /* Generate interrupt only if OF bit is clear */ if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) { env->mhpmeventh_val[ctr_idx] |=3D MHPMEVENTH_BIT_OF; - riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1)); + riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); } } else { counter->mhpmcounterh_val++; @@ -172,7 +172,7 @@ static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint3= 2_t ctr_idx) /* Generate interrupt only if OF bit is clear */ if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) { env->mhpmevent_val[ctr_idx] |=3D MHPMEVENT_BIT_OF; - riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1)); + riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); } } else { counter->mhpmcounter_val++; @@ -371,7 +371,7 @@ static void pmu_timer_trigger_irq(RISCVCPU *cpu, /* Generate interrupt only if OF bit is clear */ if (!(*mhpmevent_val & of_bit_mask)) { *mhpmevent_val |=3D of_bit_mask; - riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1)); + riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); } } } diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index b654f91af9..8d245bed3a 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -27,25 +27,24 @@ static void riscv_vstimer_cb(void *opaque) RISCVCPU *cpu =3D opaque; CPURISCVState *env =3D &cpu->env; env->vstime_irq =3D 1; - riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1)); + riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1)); } =20 static void riscv_stimer_cb(void *opaque) { RISCVCPU *cpu =3D opaque; - riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1)); + riscv_cpu_update_mip(&cpu->env, MIP_STIP, BOOL_TO_MASK(1)); } =20 /* * Called when timecmp is written to update the QEMU timer or immediately * trigger timer interrupt if mtimecmp <=3D current timer value. */ -void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer, +void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer, uint64_t timecmp, uint64_t delta, uint32_t timer_irq) { uint64_t diff, ns_diff, next; - CPURISCVState *env =3D &cpu->env; RISCVAclintMTimerState *mtimer =3D env->rdtime_fn_arg; uint32_t timebase_freq =3D mtimer->timebase_freq; uint64_t rtc_r =3D env->rdtime_fn(env->rdtime_fn_arg) + delta; @@ -57,9 +56,9 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *= timer, */ if (timer_irq =3D=3D MIP_VSTIP) { env->vstime_irq =3D 1; - riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1)); + riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1)); } else { - riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1)); + riscv_cpu_update_mip(env, MIP_STIP, BOOL_TO_MASK(1)); } return; } @@ -67,9 +66,9 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *= timer, /* Clear the [VS|S]TIP bit in mip */ if (timer_irq =3D=3D MIP_VSTIP) { env->vstime_irq =3D 0; - riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(0)); + riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(0)); } else { - riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); + riscv_cpu_update_mip(env, timer_irq, BOOL_TO_MASK(0)); } =20 /* --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248746; cv=none; d=zohomail.com; s=zohoarc; b=RcUtl8pR3+hHLB1G9tw+Qh0jEEaKCiJfzngx0tGs3ZZYvefS+dgwivYj+AXaji6c0wStONCJZJJdpLGHdi8ysE7PXi+FLmXN6A/ozk9oEZmsFAUqwUMx8DFs7xAtMtVRlkS665Qv3N4jHbB0aM5QN2iFWWRRV88pOoLhmFoGK40= ARC-Message-Signature: i=1; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.03.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:03:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248614; x=1685840614; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sslaewbTbiBH8XQ1gp6B49Xbcv0jBClrDRjZFrx/k4k=; b=okTasPgpUCcYczJZKJgxnR5fydDVZ5OrjxEnpQ1La4BSmL2KUxgLXmDdiYdZK6f63f pX2hAHjIq2ctVzaSBsHMqKkKemB+GVvLUMoWCAFufMmE0/3/J+j9cL2v12tmMSGPudOP 7lrJu3NPzdAZ6rUb1Nl5HTTClqBCotqaay/vgtZY4UYT7///zULkec+736/CRrJME+ey leww9ulGyXPulP1R2SBsX3ZCTCGr9Vbm+YE1Mq2pOWu1lUTE6pCPohWiuC2vx7OXfaxH P9Lq+ZX4j+cMSsLA+5KZ5+xGoeDGuJw/2L5iP+HWVdn80RFq6LGwgf5uc57nBmJghvaY ksTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248614; x=1685840614; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sslaewbTbiBH8XQ1gp6B49Xbcv0jBClrDRjZFrx/k4k=; b=VDcxE6cEON5+1Rk82YCfb+/PaTy4ySNayp/3HSySuaWjUJ7VSDR2hSvJyHnH6D7VAG x5OtZBZwXBIf+UZGDH4NDJVYI4Mf2Nv6cC8ElraqfnTCz36MXBtfj8Xk+bsmUVMd2hmv sH76CzE5MyMpcJ2/fAc3Snz5f1OH9Lk8X2tTPSSGIJnAtNLTEoqrulj1vf1jsoV1I18B B4828Y6PUwbK6JfxbQV+o1a3fvy1iahlAo2D7hLaxfkOQ8ezMdEXYj9ODqIt2CKU/djq ja8keMJUrUgtXx+4pSKGaSpXKUZkx6E7860dPz4mu7T8IcsX2f0ojGh/hWImhXk+Vswg HLiQ== X-Gm-Message-State: AC+VfDx8SoczXTIps6adwWpxnatykvKTU5XPImtUb/9tSeIJeS72kb/V /dPdPp+zt4OEkXjmSsANwtD2u0+VurIExw== X-Google-Smtp-Source: ACHHUZ4kRGXyFKzwTcRsH0+/jSsNfQRNgl2Ejx4qeMnON5Ri4ry+3Y9e/e3KEMbGktJVzB2vpO4mow== X-Received: by 2002:a17:902:aa02:b0:1a0:50bd:31a8 with SMTP id be2-20020a170902aa0200b001a050bd31a8mr4967283plb.26.1683248613962; Thu, 04 May 2023 18:03:33 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Alistair Francis , Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 05/89] target/riscv: Simplify arguments for riscv_csrrw_check Date: Fri, 5 May 2023 11:01:17 +1000 Message-Id: <20230505010241.21812-6-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=alistair23@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248747194100006 From: Weiwei Li Remove RISCVCPU argument, and get cfg infomation from CPURISCVState directly. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20230309071329.45932-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a7d0157d33..8f4d5eb13f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3756,15 +3756,14 @@ static RISCVException rmw_seed(CPURISCVState *env, = int csrno, =20 static inline RISCVException riscv_csrrw_check(CPURISCVState *env, int csrno, - bool write_mask, - RISCVCPU *cpu) + bool write_mask) { /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails = */ bool read_only =3D get_field(csrno, 0xC00) =3D=3D 3; int csr_min_priv =3D csr_ops[csrno].min_priv_ver; =20 /* ensure the CSR extension is enabled */ - if (!cpu->cfg.ext_icsr) { + if (!riscv_cpu_cfg(env)->ext_icsr) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -3860,9 +3859,7 @@ RISCVException riscv_csrrw(CPURISCVState *env, int cs= rno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { - RISCVCPU *cpu =3D env_archcpu(env); - - RISCVException ret =3D riscv_csrrw_check(env, csrno, write_mask, cpu); + RISCVException ret =3D riscv_csrrw_check(env, csrno, write_mask); if (ret !=3D RISCV_EXCP_NONE) { return ret; } @@ -3915,9 +3912,8 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, i= nt csrno, Int128 new_value, Int128 write_mask) { RISCVException ret; - RISCVCPU *cpu =3D env_archcpu(env); =20 - ret =3D riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu); + ret =3D riscv_csrrw_check(env, csrno, int128_nz(write_mask)); if (ret !=3D RISCV_EXCP_NONE) { return ret; } --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248774; cv=none; d=zohomail.com; s=zohoarc; b=LYy3QcQsYKIBt2G+r6q0P4oB2D37xwlZ07q1gWwNR5RkBycLUbo/HNheDG3GxdNLNFGgE6rA3miRRmnSGQZjM13njUgsQRcHgh7Pt7EV6j2w8aSQdL5uBptdmMxT/jfieSG2QggMIP0fJtm6qM69xhIKAhCFuATRbNreF5acqhw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248774; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=T4aY8YM6365clacuLSclfItYOK7GtpdOeg6+yztwDiQ=; b=cilKoesDcTK61zzk67+bs1u/RSRn0wX4UjA4dwS+TgYdDmGLqNxVfMUqmgQ5fHNCUJHYDyzBkPR7rfEhKUaPHqI1lco5amW9rc4KtGeJmZ5BTvry9k5XAOkZXO2zIun3TVDVfPc/pvt2cM6P83JuLwXH83tGXWZvNObMVzu+o8M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683248774773670.9989961597851; Thu, 4 May 2023 18:06:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujrK-0007ya-3j; Thu, 04 May 2023 21:03:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujrI-0007yP-KX for qemu-devel@nongnu.org; Thu, 04 May 2023 21:03:40 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujrH-0006sM-09 for qemu-devel@nongnu.org; Thu, 04 May 2023 21:03:40 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-64115e652eeso16410845b3a.0 for ; Thu, 04 May 2023 18:03:38 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.03.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:03:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248617; x=1685840617; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T4aY8YM6365clacuLSclfItYOK7GtpdOeg6+yztwDiQ=; b=I9vaWfCw1+l53EJyvYjlAbS6HqxlhdjXoKaQUkNBnz8yTvq/Vlswkvmhg320jdMON3 muQ+G6ctRCycLh81uRN38j0c3t4nDowQZE/7NibUnTOGfNVsf3dZx0pVOzeQWPyCh1HP kyQZ6HayyaKUEN4OAibpsgl3Wn3EQ1itcV2Zkj5WGq1QznqIku/DCyP+jJFKo/1j/Yxw clF+qoBr32sgZX6HnpdoEqKU6nihqK7CJBK7h9gAP8W1gUJNoNEe5rYriIPj/tHeYMOl jiyTAuoFSjG4wr+/CRxCGtCVokBQGjOLfLU9EK7/w506ZLPtvJHTa9xe164QrV9Fonu8 D6sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248617; x=1685840617; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T4aY8YM6365clacuLSclfItYOK7GtpdOeg6+yztwDiQ=; b=YgsHkRiJx55KCNpxvcxEfI57T00by1EaYrzQ8F6mdhScndvIGfsKEyRyQ6IkYE0Irg V2jT9Tqw2bOPxobj92fFteWcFGuU9iS/OjjlUXdCYnFpscu6qrqczwvK+IH3v6fVdmWX y1Y2uy57AFl/j8XZjfYVeyDRwT5sC3KcFnH3eLBoC5rbeP0c5NujstTlTAuymviyWP7h 8COJamySEUoUrT//KQ9cA6gWdC0sJnS4Tbq9MCnQGGW3IUcPaoAd2ABMIEeaOEP/Qf2n GrE8pvcWe3E+HNsFI9JiVBD2Z4D1y1Ph8JeT6r4pLGUUSRoXK+q9Bb6B37lKUtf9rKcQ GOEw== X-Gm-Message-State: AC+VfDx4/u8BVnfQMhaVp3KLqaWqh35+9SyWOlw6g1CbnCTE8YHauAnC HK/ZbOv3HBZOmbQ5ziNC1dA8YjTIuzXrDA== X-Google-Smtp-Source: ACHHUZ68gkrxpTfCdu30NGdd60equh36hn0eRXNB8besKs03V8urFJVPKgrQIDklfIL3VtXDhwbp9w== X-Received: by 2002:a17:903:1cd:b0:1a9:581b:fbb1 with SMTP id e13-20020a17090301cd00b001a9581bfbb1mr6173188plh.32.1683248617335; Thu, 04 May 2023 18:03:37 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Philipp Tomsich , Richard Henderson , Alistair Francis Subject: [PULL 06/89] target/riscv: refactor Zicond support Date: Fri, 5 May 2023 11:01:18 +1000 Message-Id: <20230505010241.21812-7-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=alistair23@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248776032100010 Content-Type: text/plain; charset="utf-8" From: Philipp Tomsich After the original Zicond support was stuck/fell through the cracks on the mailing list at v3 (and a different implementation was merged in the meanwhile), we need to refactor Zicond to prepare it to be reused by XVentanaCondOps. This commit lifts the common logic out into gen_czero and uses this via gen_logic and 2 helper functions (effectively partial closures). Reviewed-by: Richard Henderson Signed-off-by: Philipp Tomsich Acked-by: Alistair Francis Message-Id: <20230307180708.302867-2-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvzicond.c.inc | 36 ++++++++++++-------- 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvzicond.c.inc b/target/riscv/in= sn_trans/trans_rvzicond.c.inc index 645260164e..c8e43fa325 100644 --- a/target/riscv/insn_trans/trans_rvzicond.c.inc +++ b/target/riscv/insn_trans/trans_rvzicond.c.inc @@ -2,6 +2,7 @@ * RISC-V translation routines for the Zicond Standard Extension. * * Copyright (c) 2020-2023 PLCT Lab + * Copyright (c) 2022 VRULL GmbH. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -22,28 +23,33 @@ } \ } while (0) =20 -static bool trans_czero_eqz(DisasContext *ctx, arg_czero_eqz *a) +/* Emits "$rd =3D ($rs2 $zero) ? $zero : $rs1" */ +static void gen_czero(TCGv dest, TCGv src1, TCGv src2, TCGCond cond) { - REQUIRE_ZICOND(ctx); + TCGv zero =3D tcg_constant_tl(0); + tcg_gen_movcond_tl(cond, dest, src2, zero, zero, src1); +} =20 - TCGv dest =3D dest_gpr(ctx, a->rd); - TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_NONE); - TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); +static void gen_czero_eqz(TCGv dest, TCGv src1, TCGv src2) +{ + gen_czero(dest, src1, src2, TCG_COND_EQ); +} =20 - tcg_gen_movcond_tl(TCG_COND_EQ, dest, src2, ctx->zero, ctx->zero, src1= ); - gen_set_gpr(ctx, a->rd, dest); - return true; +static void gen_czero_nez(TCGv dest, TCGv src1, TCGv src2) +{ + gen_czero(dest, src1, src2, TCG_COND_NE); } =20 -static bool trans_czero_nez(DisasContext *ctx, arg_czero_nez *a) +static bool trans_czero_eqz(DisasContext *ctx, arg_r *a) { REQUIRE_ZICOND(ctx); =20 - TCGv dest =3D dest_gpr(ctx, a->rd); - TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_NONE); - TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); + return gen_logic(ctx, a, gen_czero_eqz); +} + +static bool trans_czero_nez(DisasContext *ctx, arg_r *a) +{ + REQUIRE_ZICOND(ctx); =20 - tcg_gen_movcond_tl(TCG_COND_NE, dest, src2, ctx->zero, ctx->zero, src1= ); - gen_set_gpr(ctx, a->rd, dest); - return true; + return gen_logic(ctx, a, gen_czero_nez); } --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248709; cv=none; d=zohomail.com; s=zohoarc; b=aGPdw/jWLVT+Fhw8hZ95hEVAxAw6BBLspwzkL70mdPrGdgx6ku/mN3+d51O0U4iC4wh7LOd/SuIj2XkuY/kfwyXa0tD7wDflqdgslLxy7FTfw3MxSAE4pILKzLB88d5moMXMihFy3eyoCb7fSofBFciGUhcWSN8iklbHW00VDms= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248709; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gzoJE78iVJN0femplDxvF1wc7FoDyCByCqci+Nuw7LQ=; b=Y+Ey3uV3TYOTHh2I5fk6EfAbYrG4TYNehVHt/PiaGmYKPMQGLKxhG2LjwVt88H/+suzxplmvGb222RafgEvqihA4h0aN5mg4gCLtZ+WFA8737x/I5zE3MVHZErdwoWngSsTFGwTX0IfoG/Pd+gNi6TIar6QrHKGs/c2mdA82kS8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683248709312624.0361520296073; Thu, 4 May 2023 18:05:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujrN-0007z3-Pi; Thu, 04 May 2023 21:03:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujrM-0007yq-5U for qemu-devel@nongnu.org; Thu, 04 May 2023 21:03:44 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujrK-0006sg-Dd for qemu-devel@nongnu.org; Thu, 04 May 2023 21:03:43 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-64115eef620so16294962b3a.1 for ; Thu, 04 May 2023 18:03:42 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.03.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:03:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248621; x=1685840621; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gzoJE78iVJN0femplDxvF1wc7FoDyCByCqci+Nuw7LQ=; b=gCdw6nUHIo1/1kCdBfIgxgFSX5s9S64q0vKikLMVQ1dlDL98gcXwOe9Q1Ro9QO8Qx/ bAZdpJCog3N0i/7pPG2aWVm5xbLWMytkAjBAE4BcmJvVDtXc58GpdQadQQTq2/1oezXG XRf8m8ff91slvD8uFeusk1iU9Kavo7AoIWpdV7A39yML4CAoNubKUHKDyP9BqYpikVkY dexdVTawDu4vnzHE0ujt7hImYDDjqVxQasLxDm0DgDIadgwdEh+LKL8/D8HBZq6YJ7xG PTxaNjjp7j0YxKUI4LQDlJ2OcBjmGCSdOppzlpJBCErUCDEjiwIn9fYqO25b2+c1v7H8 e0xA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248621; x=1685840621; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gzoJE78iVJN0femplDxvF1wc7FoDyCByCqci+Nuw7LQ=; b=gH/YPJ05+lO/JG9gIggSNRkB/F2z/XrCzpgrWwzPuPG36cDVmR3XAMKSwf3Y7altHC nqQB8E+ay+3gUZvXuz6Mb3CyfHQu6ImyQX8ipcg0idEiidnxoU7tAPA13YJ9Vr/CXfPO 5w2Gbp1xfxXz3pRfKTR0D3zkFns/dz5fojvUhtfaIycDaGU7lldm2Th8YRv3XlyQOwQH Fu7y/uN7VRY5wv+1+B8LPXdG06xmhupU+LMK7HDJgONicBVmRru+NsosricWUGSvnqHU r/TSnGJ6/B0090JWqAofVIEgFjimu/iMp/iVYnYNqmFM1+k9BvH79GXuvfVHY8xbBROQ l19g== X-Gm-Message-State: AC+VfDw4USok5Lyqpwnn26dXVtHP1IpBmtvJE6apetYD+Rp+v9faamIz mSSOjWJ1t68dQPA95cC62gtXdxcpUgPmzQ== X-Google-Smtp-Source: ACHHUZ5mHnFCnj/Y8xcC9K5tf/rVUmSp9ryFsjYIkvtsuu9syabjZg88EOQbPOXaEIzMKSiV/UFIrg== X-Received: by 2002:a17:903:2303:b0:1aa:d4ba:de2 with SMTP id d3-20020a170903230300b001aad4ba0de2mr6449125plh.18.1683248620594; Thu, 04 May 2023 18:03:40 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Philipp Tomsich , Richard Henderson , Alistair Francis Subject: [PULL 07/89] target/riscv: redirect XVentanaCondOps to use the Zicond functions Date: Fri, 5 May 2023 11:01:19 +1000 Message-Id: <20230505010241.21812-8-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=alistair23@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248709989100001 Content-Type: text/plain; charset="utf-8" From: Philipp Tomsich The Zicond standard extension implements the same instruction semantics as XVentanaCondOps, although using different mnemonics and opcodes. Point XVentanaCondOps to the (newly implemented) Zicond implementation to reduce the future maintenance burden. Also updating MAINTAINERS as trans_xventanacondops.c.inc. Reviewed-by: Richard Henderson Signed-off-by: Philipp Tomsich Acked-by: Alistair Francis Message-Id: <20230307180708.302867-3-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis --- MAINTAINERS | 2 +- .../insn_trans/trans_xventanacondops.c.inc | 18 +++--------------- 2 files changed, 4 insertions(+), 16 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index b22b85bc3a..431556c217 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -328,7 +328,7 @@ F: target/riscv/xthead*.decode RISC-V XVentanaCondOps extension M: Philipp Tomsich L: qemu-riscv@nongnu.org -S: Supported +S: Maintained F: target/riscv/XVentanaCondOps.decode F: target/riscv/insn_trans/trans_xventanacondops.c.inc =20 diff --git a/target/riscv/insn_trans/trans_xventanacondops.c.inc b/target/r= iscv/insn_trans/trans_xventanacondops.c.inc index 16849e6d4e..38c15f2825 100644 --- a/target/riscv/insn_trans/trans_xventanacondops.c.inc +++ b/target/riscv/insn_trans/trans_xventanacondops.c.inc @@ -1,7 +1,7 @@ /* * RISC-V translation routines for the XVentanaCondOps extension. * - * Copyright (c) 2021-2022 VRULL GmbH. + * Copyright (c) 2021-2023 VRULL GmbH. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,24 +16,12 @@ * this program. If not, see . */ =20 -static bool gen_vt_condmask(DisasContext *ctx, arg_r *a, TCGCond cond) -{ - TCGv dest =3D dest_gpr(ctx, a->rd); - TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_NONE); - TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); - - tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, ctx->zero); - - gen_set_gpr(ctx, a->rd, dest); - return true; -} - static bool trans_vt_maskc(DisasContext *ctx, arg_r *a) { - return gen_vt_condmask(ctx, a, TCG_COND_NE); + return gen_logic(ctx, a, gen_czero_eqz); } =20 static bool trans_vt_maskcn(DisasContext *ctx, arg_r *a) { - return gen_vt_condmask(ctx, a, TCG_COND_EQ); + return gen_logic(ctx, a, gen_czero_nez); } --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168324872174396.74322912802018; Thu, 4 May 2023 18:05:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujrQ-000848-Uq; Thu, 04 May 2023 21:03:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujrP-0007zK-4x for qemu-devel@nongnu.org; Thu, 04 May 2023 21:03:47 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujrN-0006t5-LD for qemu-devel@nongnu.org; Thu, 04 May 2023 21:03:46 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1aad5245632so8430105ad.3 for ; Thu, 04 May 2023 18:03:45 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.03.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:03:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248624; x=1685840624; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=faGYL4VJj7cZEOd1ZUz2qNV6mXJyIvHtFi+9mAQJHcc=; b=NTOUn65pVMNpbErR0Fz9oX2kkV8uuyH8WN0NytEDn/zVjaPaM6wUZBwK8jjTNZGDYS mvDRo2bV12XlVtqAYxwQGyk7Lbxp/XO2sxTEPYbhChazXWM1pxNnsX2dB/Qw4hPdVprC QiPZME9sa6zh9s0Uba9N+UkxKoCChW0Hq1wmyQd9oYpy74QKIstL0lHpD45l47ZtkBAH jPg4r6focRC76zyHVfMkB55UpydoyINi2zlqzPZvM+is+dhRyANKw4xtEfqi4HdOJ7b6 Kro0DYMw1bkNnVSe37Sd7PH3L5SOOxYlup1/8FH0UOeZcNT44vFL8KyG6ERXNK9DVYU8 03Iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248624; x=1685840624; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=faGYL4VJj7cZEOd1ZUz2qNV6mXJyIvHtFi+9mAQJHcc=; b=Mh+sERemOqx4lMEQbiKntdjepmaGxMbgXH/4ihBi2x1jaBskPuk6aimcQy/AtLEi1L DmXB0EPxCoN+dN80n5y/L2BlyMyZgqJGn5cFbxCecGUcSyXgiL+hSXFrdWxJvQt22ia5 /aAiaXt5Nd3pamnRDRqr53/XWVBOYqCa6RabybAGINBJ2j/LEHpKAUOaZpHm/yFkumUd Jvkd+la1ouzUUhX95ebwAs3dtBlP+Pt1lDxtGOv/O8SAxNkTTnhah1vfClgZUvlB9NBl PGrRD1wS5JcP+/xwKGbQlYyfmnmwNaoovEC9tkqMkVQuDQ6mMUlzZh2ToUaO+rjL58i2 M6Pw== X-Gm-Message-State: AC+VfDyQt5N28JUGetLJo8OJkejzDlgxgsqKhTGQ//kuMNBFx5WzeLun BaFz2WHgS2lPf1p5KkKpn8ajuYQKYwQRsw== X-Google-Smtp-Source: ACHHUZ60Uv6zpz29QyTlac0W6H0fNgqa82oSHVJ9h8De7BOQatxymd1/bIe9jIXwb4JjT7PLCTVUoQ== X-Received: by 2002:a17:902:db08:b0:1ac:3103:c555 with SMTP id m8-20020a170902db0800b001ac3103c555mr3919596plx.58.1683248623851; Thu, 04 May 2023 18:03:43 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Conor Dooley , Alistair Francis Subject: [PULL 08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entry Date: Fri, 5 May 2023 11:01:20 +1000 Message-Id: <20230505010241.21812-9-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1683248723436100001 Content-Type: text/plain; charset="utf-8" From: Conor Dooley dt-validate complains: > soc: pmu: {'riscv,event-to-mhpmcounters': > [[1, 1, 524281], [2, 2, 524284], [65561, 65561, 524280], > [65563, 65563, 524280], [65569, 65569, 524280], [0, 0, 0], [0, 0]], > pmu: riscv,event-to-mhpmcounters:6: [0, 0] is too short There are bogus 0 entries added at the end, of which one is of insufficient length. This happens because only 15 of fdt_event_ctr_map[]'s 20 elements are populated & qemu_fdt_setprop() is called using the size of the array. Reduce the array to 15 elements to make the error go away. Signed-off-by: Conor Dooley Reviewed-by: Alistair Francis Message-Id: <20230404173333.35179-1-conor@kernel.org> Signed-off-by: Alistair Francis --- target/riscv/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 22e2283c76..96ce2dbe49 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -35,7 +35,7 @@ */ void riscv_pmu_generate_fdt_node(void *fdt, int num_ctrs, char *pmu_name) { - uint32_t fdt_event_ctr_map[20] =3D {}; + uint32_t fdt_event_ctr_map[15] =3D {}; uint32_t cmask; =20 /* All the programmable counters can map to any event */ --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248773; cv=none; d=zohomail.com; s=zohoarc; b=VqPBy2Hu56QIW9DgVMDzfGVVB9wjIuy33rPdR6zZyEPokuMSFSTUgir7M+Tm1wJg+k9Gr+odPNwZqrxQP3GHPOHrb7tn01hcCjxK5YQBfugPlbtqfI06WJPq/MgF/T5jKCl738XSHuJNFKoZ5vC/gorOKo16tdvnsG8Yd6qlvO8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248773; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eSrZR2FEgMCsszLbeTj2jVznuk5gFjIpd0QGja6u5o4=; b=LFGK2m3YnM6zmiZtb1XzFKnUoxIcknZQ/aPKSL+k99vWfTWTWwpUOd0YYWbmE/FluvAZCFNShW7Qa6Tb1JD0Tonp/+YboxZIDVPMWCzNwke336qLj1eDHh2CuZW9a2xbN4k+agD9YMasBu0oA6hZyLdbzvGRRTyg4AEbzTC+z50= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16832487735151003.9461044265632; Thu, 4 May 2023 18:06:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujrV-000876-AW; Thu, 04 May 2023 21:03:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujrT-00086g-Ju for qemu-devel@nongnu.org; Thu, 04 May 2023 21:03:51 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujrS-0006tU-2X for qemu-devel@nongnu.org; Thu, 04 May 2023 21:03:51 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1aaebed5bd6so8160455ad.1 for ; Thu, 04 May 2023 18:03:48 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.03.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:03:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248627; x=1685840627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eSrZR2FEgMCsszLbeTj2jVznuk5gFjIpd0QGja6u5o4=; b=OqHMPqN2baAfIHwCqKAsMhYx4WAnShdAh66sOy6rBixdMZdbukMEW3puDo80azEA6a Xqp4dYwuEXW4dfniUSx5SvvmDb/4FEHo95oAWdpfIKkao2hCJ5OtVfpsyTHk6caTdGe9 pQHTbYd97Rv6RDt7/rLGucb4Dvqta4guj1fmdce6GyL8G2Ze0J7a8epgZxMALiFIE6Sv NBxgu/7lVizgBdFj2e4unBVR+0E5LYVdEB3WDH3QFFBBcGlu3nzDu5UAn+h2xPyPGf7M E1fJoFHwybRv7PZQiLrUxy5HIsgXyCYvSucncmJdW8saJ99Noox3G/sJfmvkXfftbchR E/vQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248627; x=1685840627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eSrZR2FEgMCsszLbeTj2jVznuk5gFjIpd0QGja6u5o4=; b=HmFcO/EL6IvXHu6xGJETbtJivmAPp9k6CKaylPtIrcaoOKdGUb2fSLI5d1bdkQ6A93 9S2kpL8oQbGpE9GhuoBC+B1W88JpJ4NRky0j2b3cc2r1Z+H6UaToar000rids0tWWPD1 HLJ3afwRQCPCcAl6ol8CoL6QvgmzEWqAsoklOcjpwoFpUXcYqMre1YuslnIKDMwcMn4y hjfU6K4+boHssl9MReVaJv2rPSzHNvkL+M3ysNbcC4uatgGCQHThDo0A6h4O/TXoQDZx 0TG9WQ4IY1BABXS0Vo7B3edSeNsHGqMT7S5+mGpfzIn9L9J2SMb10fPjIkUFdwz5Ffxj EJ5Q== X-Gm-Message-State: AC+VfDzM5CweBIvHeHGsgv8z+iKvSarKQrZBs/yXCp+DcLIMYWQq2o2I UmNyAdH4eiijTFiqghG1EUtMPiAAt2Q5Cw== X-Google-Smtp-Source: ACHHUZ4v10kTb5GIV4uQpjG0+7Hf+8R4fMEWPFzrXN3uZtT6YoWbDMTtqKfktiC8J8SS/W2lveKWgw== X-Received: by 2002:a17:902:b904:b0:1ac:34fe:d040 with SMTP id bf4-20020a170902b90400b001ac34fed040mr2778146plb.50.1683248627332; Thu, 04 May 2023 18:03:47 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Richard Henderson , Alistair Francis Subject: [PULL 09/89] target/riscv: add cfg properties for Zc* extension Date: Fri, 5 May 2023 11:01:21 +1000 Message-Id: <20230505010241.21812-10-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=alistair23@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248775658100004 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension. Add check for these properties. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20230307081403.61950-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 6 ++++++ target/riscv/cpu.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5adefe4ab5..e5f7c860d1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -438,6 +438,12 @@ struct RISCVCPUConfig { bool ext_zbkc; bool ext_zbkx; bool ext_zbs; + bool ext_zca; + bool ext_zcb; + bool ext_zcd; + bool ext_zcf; + bool ext_zcmp; + bool ext_zcmt; bool ext_zk; bool ext_zkn; bool ext_zknd; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cea0d3cbdd..97b0a77d8e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -939,6 +939,49 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU= *cpu, Error **errp) } } =20 + if (cpu->cfg.ext_c) { + cpu->cfg.ext_zca =3D true; + if (cpu->cfg.ext_f && env->misa_mxl_max =3D=3D MXL_RV32) { + cpu->cfg.ext_zcf =3D true; + } + if (cpu->cfg.ext_d) { + cpu->cfg.ext_zcd =3D true; + } + } + + if (env->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { + error_setg(errp, "Zcf extension is only relevant to RV32"); + return; + } + + if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) { + error_setg(errp, "Zcf extension requires F extension"); + return; + } + + if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) { + error_setg(errp, "Zcd extension requires D extension"); + return; + } + + if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || + cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { + error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " + "extension"); + return; + } + + if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { + error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " + "Zcd extension"); + return; + } + + if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { + error_setg(errp, "Zcmt extension requires Zicsr extension"); + return; + } + if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn =3D true; cpu->cfg.ext_zkr =3D true; --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249239; cv=none; d=zohomail.com; s=zohoarc; b=gWDlHlV5klDwa92T3TQpEvV5B+fZK8TkZthGKTTjbEmzv++Ywb+piZL4e8UFAjSp2lmpLq70/qKcIpCqWnYywLaQrHFQMX3V8QH4VZiJ7nNBrvmvql3xADIqVt1si8F6afgWUH9mq0RezC0moCllyOwFWyFoqG8DzTL+fYSmkHc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249239; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TItCTzTkSU2louEtCfJ4UF91sjN6WTuYpCMNNVreXeY=; b=D0rUMo9j8waiWiYflV/RNgHR0M0MZXy7rd5mrlm95bMed6W4L/3Xyc4Anu72z9cAX3taUPJzrnlk46z94DPeJiCgpb4tQ8Zsd/NSJZyPfphHPVHqXHkBcscMc3qb09iSAgdFU+ggfSrmmY4WFDuw7LH2CF7egLnkhFr2jRJoKbM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249239887132.35674291734483; Thu, 4 May 2023 18:13:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujrX-00087e-Ii; Thu, 04 May 2023 21:03:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujrW-00087M-8I for qemu-devel@nongnu.org; Thu, 04 May 2023 21:03:54 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujrU-0006uc-N6 for qemu-devel@nongnu.org; Thu, 04 May 2023 21:03:54 -0400 Received: by mail-pg1-x536.google.com with SMTP id 41be03b00d2f7-51f1b6e8179so747440a12.3 for ; Thu, 04 May 2023 18:03:52 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.03.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:03:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248631; x=1685840631; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TItCTzTkSU2louEtCfJ4UF91sjN6WTuYpCMNNVreXeY=; b=Xc3uxRdmeBBefQU+gSp21Xr2HA0k5bqPSfeOB7jw2XAOdz36vLF63T97FurN6ESpBN sIEBFlQOg87W2XfrEYAslKCg5wfss5ZzUQww1HKhqf6Jr+sC6nKtOVJ+Lvhmu4jZoOqX W0Om+bonIQrbZdDqFeSKza5vWP5bdNzbjbZGxn6dHsua32M7GMSVm/OMNATmlxxVeA9z 4mBwnEVuGYwfGiWismChc4PT29Xhs7odTAFh85lSWPJE6hZZY4w68z46vNwnDgEZUKbn 3Vx37IYirpthl+sIh8eUIsSFyoLpcqYJa19n9wr4AwP7beSoJLNDbhdee/U4Nx+jbtmX KyYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248631; x=1685840631; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TItCTzTkSU2louEtCfJ4UF91sjN6WTuYpCMNNVreXeY=; b=fKpE1m3Z5r0lQFwa6UoQN98+C573Cr1BM2mabNqMoVFOpZXMQ0RUefbPkWTd1ozhWl A9B+5r+NQa4+R4hdoY6UJIiRLsFSTVGQdDZJJtNhRxl1jTa+PIbuQUX/qzHocCfTvP5F H+L8CjGkN1xWZNk4Ktg6HbIdo4NcQe7KJCKDpgv23sTa8+4krnBb50enqBTLQi48Bq4P Jejz4FkkeBN7VhZ6MFDov0WfnED8qPY75MoVN522OIpQtd8y5TUV4/PPhPT5xEqvHsSC K7wIAaYv/nJM+6jGVZM2e9Ea4hq7QSGqT5PDLJ1Mk9UT9P6IrdmcUes5A/78Hs+N0K5J hFzQ== X-Gm-Message-State: AC+VfDyHj8uZ6OHRqZv31vpl2fZ5s8357IUL8XlAdd93cUfIQ2AixRGX aQux8w5aerVn3GnK6tNKEqkJQLGLZqGwWQ== X-Google-Smtp-Source: ACHHUZ4lXVcFBeiP6rkISz0F0PRStFyCMD9cFlwIgBpmmr6IMmWKtAmCHBqK6SagVFhxpsOr1vf0Qg== X-Received: by 2002:a17:903:11c8:b0:1ab:fb6:1e72 with SMTP id q8-20020a17090311c800b001ab0fb61e72mr6762060plh.42.1683248630976; Thu, 04 May 2023 18:03:50 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Richard Henderson , Alistair Francis , Wilfred Mallawa Subject: [PULL 10/89] target/riscv: add support for Zca extension Date: Fri, 5 May 2023 11:01:22 +1000 Message-Id: <20230505010241.21812-11-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=alistair23@gmail.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249240712100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Modify the check for C extension to Zca (C implies Zca). Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Wilfred Mallawa Message-Id: <20230307081403.61950-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/translate.c | 8 ++++++-- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0ee8ee147d..d1fdd0c2d7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -549,7 +549,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_u= long imm) =20 /* check misaligned: */ next_pc =3D ctx->base.pc_next + imm; - if (!has_ext(ctx, RVC)) { + if (!ctx->cfg_ptr->ext_zca) { if ((next_pc & 0x3) !=3D 0) { gen_exception_inst_addr_mis(ctx); return; @@ -1122,7 +1122,11 @@ static void decode_opc(CPURISCVState *env, DisasCont= ext *ctx, uint16_t opcode) if (insn_len(opcode) =3D=3D 2) { ctx->opcode =3D opcode; ctx->pc_succ_insn =3D ctx->base.pc_next + 2; - if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) { + /* + * The Zca extension is added as way to refer to instructions in t= he C + * extension that do not include the floating-point loads and stor= es + */ + if (ctx->cfg_ptr->ext_zca && decode_insn16(ctx, opcode)) { return; } } else { diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 4ad54e8a49..c70c495fc5 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -56,7 +56,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2); =20 gen_set_pc(ctx, cpu_pc); - if (!has_ext(ctx, RVC)) { + if (!ctx->cfg_ptr->ext_zca) { TCGv t0 =3D tcg_temp_new(); =20 misaligned =3D gen_new_label(); @@ -169,7 +169,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCG= Cond cond) =20 gen_set_label(l); /* branch taken */ =20 - if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) { + if (!ctx->cfg_ptr->ext_zca && ((ctx->base.pc_next + a->imm) & 0x3)) { /* misaligned */ gen_exception_inst_addr_mis(ctx); } else { --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248732; cv=none; d=zohomail.com; s=zohoarc; b=hc7aIHJ34nNkVccvCavlASPQXjNpMYQCW2gTUVLsXRLXAYZVbZkwBnAhctGXDlPGC2k7ldj3//E6rBgxnLueBw5QqLJg9YFaKtNVbSzNqk8W0MhlFiJfIVeL2FyqUjzFnNG87wz+ma2NjMGygwJNeAJoXfKXupIaZU3BNvBPduU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248732; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QJhWbDbpcQGhaaiXOe2fwIjhXa0Xx1aUHvNDUSvtTzY=; b=R5VKmpDmUu+QnNsREjAXpNkqZ0UJwDmwW/AZ7Nt29/aHiasygY4DwDjumIlT97FbkFeMxRlTnVyRVvO3Eg5n+rVBISB/RoWJOfL6NfoUM8W3hJkGtVohbJkA5l5OWSUinFALqiztIf0MdoN529egdA9Ax1O24CCkrLzZ3H9OAI8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168324873228988.6685973479457; Thu, 4 May 2023 18:05:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujrd-0008C0-NQ; Thu, 04 May 2023 21:04:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujrc-0008BW-Io for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:00 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujrY-0006vJ-Vw for qemu-devel@nongnu.org; Thu, 04 May 2023 21:03:59 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1aae46e62e9so8418235ad.2 for ; Thu, 04 May 2023 18:03:55 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.03.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:03:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248634; x=1685840634; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QJhWbDbpcQGhaaiXOe2fwIjhXa0Xx1aUHvNDUSvtTzY=; b=BuV+55DPQM5coPPC3fCgqiwtQa3pkf3pd1yu/kGULSVSdajTERmEVL1q4Q91cpH+BC y7pfmT+YGs1aILAcd0GAuJHo2eFOU4MNF8eFWp5uaCRh5yJsa7pBUwYJCPMlXM9W6amy Fep6uyHqjSVzXPPam1h6Blrf3CBNAL1hJv3rM0DZdb6ily2YXDIiZHMzX4FrkevWd/0h bKANEteJEDmCJTNY9fcCQbowkmXe/MmJHrGfHWY6Cp0Bu459ZuLZF1RgmvfabQaET3jA qKIH9LHGgzqGZWhU6pQniGavbbRryA7OPGj/n2Ugd8sPXfVgVlrdl0DMp1F+oLvw+jXJ CB2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248634; x=1685840634; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QJhWbDbpcQGhaaiXOe2fwIjhXa0Xx1aUHvNDUSvtTzY=; b=jfpT7lkHncPFOk8JqODA7V/bw6i8wY93483GG5DSukm7gXzU5YeJjFSdwZeIkfNuEb N4IZJBZrMJExcsrTDMu+IjStD+IkXYWev4xB08moqVBFjebNJnZh8bkdZbkUQKKWQONU f8Lp91sXV3OZeaG7SkvxTOld83Z5i4oTu49UGtxDN1k0r3WLiXH8k7RiUWZF8oW03/Cl L6j3BzxcOhiJ5WDHhFRKodj6EBlq4szEK7dFbW+8SZroWIZAwFj10jjihnwJpFQKNOTI noTC0FtEjmK48UnHhIIiFcFyXplhl+FxoSLq23OH9buxu//cmpzoFMaURUBfExjfXLkH Sdew== X-Gm-Message-State: AC+VfDzrQLpTcGz2Ls179J9zXIGCJfgNwN0hkUgSZN0TFiP1HH9lynCJ pL/0vTL7zrIMwgagZOWCwtLnJZqVaXoc5w== X-Google-Smtp-Source: ACHHUZ6sc2/s8xV6tlljITyNdRiHVJS8yLfkuBjU4pDj7s7H/1DrLdvxGM/WvjPIfoPPLpIkZ1hgLA== X-Received: by 2002:a17:902:8ec5:b0:1a9:b91f:63fc with SMTP id x5-20020a1709028ec500b001a9b91f63fcmr5095888plo.12.1683248634335; Thu, 04 May 2023 18:03:54 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Richard Henderson , Alistair Francis Subject: [PULL 11/89] target/riscv: add support for Zcf extension Date: Fri, 5 May 2023 11:01:23 +1000 Message-Id: <20230505010241.21812-12-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=alistair23@gmail.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248733534100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20230307081403.61950-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/insn16.decode | 8 ++++---- target/riscv/insn_trans/trans_rvf.c.inc | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index ccfe59f294..f3ea650325 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -109,11 +109,11 @@ sw 110 ... ... .. ... 00 @cs_w # *** RV32C and RV64C specific Standard Extension (Quadrant 0) *** { ld 011 ... ... .. ... 00 @cl_d - flw 011 ... ... .. ... 00 @cl_w + c_flw 011 ... ... .. ... 00 @cl_w } { sd 111 ... ... .. ... 00 @cs_d - fsw 111 ... ... .. ... 00 @cs_w + c_fsw 111 ... ... .. ... 00 @cs_w } =20 # *** RV32/64C Standard Extension (Quadrant 1) *** @@ -174,9 +174,9 @@ sw 110 . ..... ..... 10 @c_swsp { c64_illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=3D0 ld 011 . ..... ..... 10 @c_ldsp - flw 011 . ..... ..... 10 @c_lwsp + c_flw 011 . ..... ..... 10 @c_lwsp } { sd 111 . ..... ..... 10 @c_sdsp - fsw 111 . ..... ..... 10 @c_swsp + c_fsw 111 . ..... ..... 10 @c_swsp } diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index 052408f45c..9e9fa2087a 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -30,6 +30,12 @@ } \ } while (0) =20 +#define REQUIRE_ZCF(ctx) do { \ + if (!ctx->cfg_ptr->ext_zcf) { \ + return false; \ + } \ +} while (0) + static bool trans_flw(DisasContext *ctx, arg_flw *a) { TCGv_i64 dest; @@ -61,6 +67,18 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) return true; } =20 +static bool trans_c_flw(DisasContext *ctx, arg_flw *a) +{ + REQUIRE_ZCF(ctx); + return trans_flw(ctx, a); +} + +static bool trans_c_fsw(DisasContext *ctx, arg_fsw *a) +{ + REQUIRE_ZCF(ctx); + return trans_fsw(ctx, a); +} + static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a) { REQUIRE_FPU; --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248785; cv=none; d=zohomail.com; s=zohoarc; b=IIBjQ3hhnE4LpwDrsl8zu382kS+FTgEShFNh7Kb7mWALbP5wbBRbED9a7/XJfhdQ/AoqvMv3SYoRNXT1MPYPey9prMtlKQ5D5qy86MCpmpwY66WMbLYugkwpXDvhK1ICWm6ewCFr1IFmyreFJlbBSUUUEFDWlFIjMXAb6L9l+Qc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248785; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=F7kq4l6FRbNL5l8a5fEkXlr9K/vWT8JmBZha0iGGH9o=; b=KrgsIgjIKfl4KDO26GWtKxruIulRyPDR0chja4V/rp67k5ivKDhMpNH2xWSnpO5hwgxHyaBlJDMPVCuUdB8yqZoXJq0KQyFDb7lXEQhcB+JwVB4VPdlICtb6IBJksu8FZS3IHsQOZilJTJU1/8blfq2Jq5DVCzC7OoSUenXsRwc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683248785731592.9133504513006; Thu, 4 May 2023 18:06:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujrg-0008D1-6j; Thu, 04 May 2023 21:04:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujre-0008C3-9g for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:02 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujrc-0006vu-9G for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:01 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1a516fb6523so10658375ad.3 for ; Thu, 04 May 2023 18:03:59 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.03.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:03:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248637; x=1685840637; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F7kq4l6FRbNL5l8a5fEkXlr9K/vWT8JmBZha0iGGH9o=; b=C9XVBtm1WHir4UqSD2FkwOuBKaMcZuYQXl3XUwrnTvmHjJF335KpOtihfJjkQeuODB aJSMQaPTomlv38abXgDObDJgzK/H2tNF+hue5gMII7vgtdy98CRND1MRt9m9vIuqjA41 eEy0eqWcAW1L8Go1HgBbBLEwIZlS1PAFCtcbV1qxiqXfZduZY4CSv5cPeXKxHHd71+ne AZtOdN+GKAM5t7TvcpTRYR3OpWOcW555tcnqDkQIFmLf8+tyXJ9Z/ePSSDlJcqQSrWI8 BucL81NPUd5a9NmHgX9CzPSZRcpZtpYfxemlfI9Tmd10Sszw2ZDus46EIUNWa9ZzYxmf l1nA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248637; x=1685840637; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F7kq4l6FRbNL5l8a5fEkXlr9K/vWT8JmBZha0iGGH9o=; b=EZVDvrbVd8EBPCPEZ0qFMVndFbEUvcsESP1gfjEnt/5k5yQNhv+CMfdizJhUsApq47 P2nffRJfP6Jd93INCFjqL/QX2MfH3Vcs+HYwKOcbbo14jik/nkmHtTxMDBD5X+pvBa9C azGCdM4ywZgyZeuBwXCKeG8r+HYqrzAVK9Cqf+HLekPRq+sKRGlNFus6Zn5XHHpnnj4o +d8ON5t+SnszF1EgvGrQajscZUiMhjXXhFyhFUYgLSBKekchh14B99jMav8FxNhqPxVM 7dkqo78KzMrJRqVtfRKCZcYfSbwNrxCSy2ZBx79Zh2wMh0fx2aJehS6LnVJvoYShqH1P gqCQ== X-Gm-Message-State: AC+VfDy2zmF9kbybazWxUIsQjM987weFqizlqZ+gcWxxYNAxTYph+zXI UYpRoJRKoXqzK10FORLwOW6scY++Km+LqQ== X-Google-Smtp-Source: ACHHUZ5GwJvEP/ORSZhYPqQtIHBdFRoTIfoipticGnyNiEQpkvc58/tpqOEaZA0LdQaMrrHQ5tDULg== X-Received: by 2002:a17:902:d50b:b0:1a0:57dd:b340 with SMTP id b11-20020a170902d50b00b001a057ddb340mr5969137plg.64.1683248637636; Thu, 04 May 2023 18:03:57 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Richard Henderson , Alistair Francis Subject: [PULL 12/89] target/riscv: add support for Zcd extension Date: Fri, 5 May 2023 11:01:24 +1000 Message-Id: <20230505010241.21812-13-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=alistair23@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248786100100006 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Separate c_fld/c_fsd from fld/fsd to add additional check for c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse their encodings. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20230307081403.61950-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/insn16.decode | 8 ++++---- target/riscv/insn_trans/trans_rvd.c.inc | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index f3ea650325..b62664b6af 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -97,12 +97,12 @@ } { lq 001 ... ... .. ... 00 @cl_q - fld 001 ... ... .. ... 00 @cl_d + c_fld 001 ... ... .. ... 00 @cl_d } lw 010 ... ... .. ... 00 @cl_w { sq 101 ... ... .. ... 00 @cs_q - fsd 101 ... ... .. ... 00 @cs_d + c_fsd 101 ... ... .. ... 00 @cs_d } sw 110 ... ... .. ... 00 @cs_w =20 @@ -148,7 +148,7 @@ addw 100 1 11 ... 01 ... 01 @cs_2 slli 000 . ..... ..... 10 @c_shift2 { lq 001 ... ... .. ... 10 @c_lqsp - fld 001 . ..... ..... 10 @c_ldsp + c_fld 001 . ..... ..... 10 @c_ldsp } { illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=3D0 @@ -166,7 +166,7 @@ slli 000 . ..... ..... 10 @c_shift2 } { sq 101 ... ... .. ... 10 @c_sqsp - fsd 101 ...... ..... 10 @c_sdsp + c_fsd 101 ...... ..... 10 @c_sdsp } sw 110 . ..... ..... 10 @c_swsp =20 diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 1597bf31d8..2c51e01c40 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -31,6 +31,12 @@ } \ } while (0) =20 +#define REQUIRE_ZCD(ctx) do { \ + if (!ctx->cfg_ptr->ext_zcd) { \ + return false; \ + } \ +} while (0) + static bool trans_fld(DisasContext *ctx, arg_fld *a) { TCGv addr; @@ -59,6 +65,18 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) return true; } =20 +static bool trans_c_fld(DisasContext *ctx, arg_fld *a) +{ + REQUIRE_ZCD(ctx); + return trans_fld(ctx, a); +} + +static bool trans_c_fsd(DisasContext *ctx, arg_fsd *a) +{ + REQUIRE_ZCD(ctx); + return trans_fsd(ctx, a); +} + static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a) { REQUIRE_FPU; --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248759; cv=none; d=zohomail.com; s=zohoarc; b=XugEgDJyCn5iNPIOYnAZ98ReLB8ucPTEJuePtWLgAgBlAnzlSRL94OaYakhDYikh3HGYDENQbdcdL2FcBt9+jmud+dPmAXMkAnL/wSwS1ZoHiufEwkCs89SI929Qyc7y3uoJ4o1hnTFs70ozffX0gyYHvENth7RrNPrRvJtORiQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248759; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ATqXAaRyTP9goBurtZyxqTGUYDE3bm5yuJr3IsVaVdU=; b=gN5lkkqcW+1JxdCWZw/9gc+tVp+jAvxwCIfZ1lyhay88EFjEzAUoTxAlTgYgHpiMoVBB/TBXy38Wn20EoVe3vrzB1X6zA1UK1U44RUrA66YDicpTLbu2xzEw1rHiRVxhZj+Al3AHWF9JQud8uziihEBaVihAyGVE1D256j7waG0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683248759898356.3262891724323; Thu, 4 May 2023 18:05:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujro-0008HP-NF; Thu, 04 May 2023 21:04:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujri-0008FY-1l for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:06 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujrg-0006ww-07 for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:05 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1a50cb65c92so8230985ad.0 for ; Thu, 04 May 2023 18:04:02 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.03.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:04:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248641; x=1685840641; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ATqXAaRyTP9goBurtZyxqTGUYDE3bm5yuJr3IsVaVdU=; b=k5fTjFh5dFZe8rrAXTZnszJC0tOu92tnOpmUAPUNoOw0pR/cz0driziuxm3dDijBtx 5iObV0ZRY9Ly11Vn9YNYLt+kMaL+0Md8NvaDhiT7NHZ9AvD9bmL1fp/LX/BZVWdSpAnW 7o5bAAgHVisCFS+sywLZ9k8u9lH5DriTbGeF9wzbRqsiSM9vVnQypjw5ojCMhjdgQV+M VrfUi2Ztar/qEbyNAXR9EFdMz+EzpLcPRAR2js2pekZcaRj6GhnbR2NHYmVL8o1oqoMu OZ/miyAdCTp7vdjqEPQ/D/K+GBFwd5bm+46fDDH/HWeoe50cl3MUwFEeTzGkxlE5nU4u ZI1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248641; x=1685840641; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ATqXAaRyTP9goBurtZyxqTGUYDE3bm5yuJr3IsVaVdU=; b=IKI7rdOoXlac5vi8yXkxoDnGMGqO40D+nfMm4AWt3xEAFBeDehMhXmtqB3QNCjx7yv ybiHeEVpBx9ymdvE9AG8+ehGmV+tDB4RZTGoKSsvnUJDXnnDhw0kTg7J1pcO0shUX37I gMNXe5vdOw7DnAQwuYc57KaVR8RbWFofgcuJMWPKytqUhpCMHALGI/ZvNhUmMVop+E/9 oiNcxcIVGXldo1WL86F6EIPDroHwg6LmWbJW8lmDxs6NNlWfkFI/uvRQQS2RYaJjEz2L 4i3rzQNItGeTeuVf9nwSeUFkilQSDSDN4nxr6j/BwFTr/kPkNI9ql7EzR8PPukYxE+O0 R95A== X-Gm-Message-State: AC+VfDx4sRuUgILx1Nj3xlS9TfB8Qed9U6lWvUyKfQ8yV6uXynRKZItv QWM+ygyg6jOg+xhUVsTSzupcKPR/9gsL5g== X-Google-Smtp-Source: ACHHUZ67svsbDh/ZidQgN9466GseP6NWV7PgwslqYNeYh39DB2YG564EItqdxyiS22jSJpnm4Oy0LQ== X-Received: by 2002:a17:902:ceca:b0:1a9:b977:81c7 with SMTP id d10-20020a170902ceca00b001a9b97781c7mr6107777plg.62.1683248641146; Thu, 04 May 2023 18:04:01 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Richard Henderson , Alistair Francis Subject: [PULL 13/89] target/riscv: add support for Zcb extension Date: Fri, 5 May 2023 11:01:25 +1000 Message-Id: <20230505010241.21812-14-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=alistair23@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248761498100003 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Add encode and trans* functions support for Zcb instructions. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20230307081403.61950-6-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/insn16.decode | 23 +++++ target/riscv/translate.c | 2 + target/riscv/insn_trans/trans_rvzce.c.inc | 100 ++++++++++++++++++++++ 3 files changed, 125 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index b62664b6af..ab780fa46a 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -43,6 +43,8 @@ %imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=3Dex_shift_4 %imm_lui 12:s1 2:5 !function=3Dex_shift_12 =20 +%uimm_cl_b 5:1 6:1 +%uimm_cl_h 5:1 !function=3Dex_shift_1 =20 # Argument sets imported from insn32.decode: &empty !extern @@ -53,6 +55,7 @@ &b imm rs2 rs1 !extern &u imm rd !extern &shift shamt rs1 rd !extern +&r2 rd rs1 !extern =20 =20 # Formats 16: @@ -89,6 +92,12 @@ =20 @c_andi ... . .. ... ..... .. &i imm=3D%imm_ci rs1=3D%rs1_3 rd=3D%= rs1_3 =20 +@cu ... ... ... .. ... .. &r2 rs1=3D%rs1_3 rd= =3D%rs1_3 +@cl_b ... . .. ... .. ... .. &i imm=3D%uimm_cl_b rs1=3D%rs1_3 r= d=3D%rs2_3 +@cl_h ... . .. ... .. ... .. &i imm=3D%uimm_cl_h rs1=3D%rs1_3 r= d=3D%rs2_3 +@cs_b ... . .. ... .. ... .. &s imm=3D%uimm_cl_b rs1=3D%rs1_3 r= s2=3D%rs2_3 +@cs_h ... . .. ... .. ... .. &s imm=3D%uimm_cl_h rs1=3D%rs1_3 r= s2=3D%rs2_3 + # *** RV32/64C Standard Extension (Quadrant 0) *** { # Opcode of all zeros is illegal; rd !=3D 0, nzuimm =3D=3D 0 is reserved. @@ -180,3 +189,17 @@ sw 110 . ..... ..... 10 @c_swsp sd 111 . ..... ..... 10 @c_sdsp c_fsw 111 . ..... ..... 10 @c_swsp } + +# *** RV64 and RV32 Zcb Extension *** +c_zext_b 100 111 ... 11 000 01 @cu +c_sext_b 100 111 ... 11 001 01 @cu +c_zext_h 100 111 ... 11 010 01 @cu +c_sext_h 100 111 ... 11 011 01 @cu +c_zext_w 100 111 ... 11 100 01 @cu +c_not 100 111 ... 11 101 01 @cu +c_mul 100 111 ... 10 ... 01 @cs_2 +c_lbu 100 000 ... .. ... 00 @cl_b +c_lhu 100 001 ... 0. ... 00 @cl_h +c_lh 100 001 ... 1. ... 00 @cl_h +c_sb 100 010 ... .. ... 00 @cs_b +c_sh 100 011 ... 0. ... 00 @cs_h diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d1fdd0c2d7..3634137d85 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1091,6 +1091,8 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) =20 /* Include the auto-generated decoder for 16 bit insn */ #include "decode-insn16.c.inc" +#include "insn_trans/trans_rvzce.c.inc" + /* Include decoders for factored-out extensions */ #include "decode-XVentanaCondOps.c.inc" =20 diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_= trans/trans_rvzce.c.inc new file mode 100644 index 0000000000..de96c4afaf --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -0,0 +1,100 @@ +/* + * RISC-V translation routines for the Zcb Standard Extension. + * + * Copyright (c) 2021-2022 PLCT Lab + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#define REQUIRE_ZCB(ctx) do { \ + if (!ctx->cfg_ptr->ext_zcb) \ + return false; \ +} while (0) + +static bool trans_c_zext_b(DisasContext *ctx, arg_c_zext_b *a) +{ + REQUIRE_ZCB(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8u_tl); +} + +static bool trans_c_zext_h(DisasContext *ctx, arg_c_zext_h *a) +{ + REQUIRE_ZCB(ctx); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl); +} + +static bool trans_c_sext_b(DisasContext *ctx, arg_c_sext_b *a) +{ + REQUIRE_ZCB(ctx); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl); +} + +static bool trans_c_sext_h(DisasContext *ctx, arg_c_sext_h *a) +{ + REQUIRE_ZCB(ctx); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl); +} + +static bool trans_c_zext_w(DisasContext *ctx, arg_c_zext_w *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_ZCB(ctx); + REQUIRE_ZBA(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext32u_tl); +} + +static bool trans_c_not(DisasContext *ctx, arg_c_not *a) +{ + REQUIRE_ZCB(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_not_tl); +} + +static bool trans_c_mul(DisasContext *ctx, arg_c_mul *a) +{ + REQUIRE_ZCB(ctx); + REQUIRE_M_OR_ZMMUL(ctx); + return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl, NULL); +} + +static bool trans_c_lbu(DisasContext *ctx, arg_c_lbu *a) +{ + REQUIRE_ZCB(ctx); + return gen_load(ctx, a, MO_UB); +} + +static bool trans_c_lhu(DisasContext *ctx, arg_c_lhu *a) +{ + REQUIRE_ZCB(ctx); + return gen_load(ctx, a, MO_UW); +} + +static bool trans_c_lh(DisasContext *ctx, arg_c_lh *a) +{ + REQUIRE_ZCB(ctx); + return gen_load(ctx, a, MO_SW); +} + +static bool trans_c_sb(DisasContext *ctx, arg_c_sb *a) +{ + REQUIRE_ZCB(ctx); + return gen_store(ctx, a, MO_UB); +} + +static bool trans_c_sh(DisasContext *ctx, arg_c_sh *a) +{ + REQUIRE_ZCB(ctx); + return gen_store(ctx, a, MO_UW); +} --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248745; cv=none; d=zohomail.com; s=zohoarc; b=fXm1jCOaoRBFY/VpU10CrPv9Kbx8A8wpQV8qNCxHInWmdaYsyHe46LnY5QqifZFy1KgXxwoYyNY/znd38bQOvb2k+gJteaUIIUKYiafS3r/t/ayr/j6wx8eN7/o3kHC9eyEw/87wjq0BaVOEVfLBfUOnic8yZKb+X+124zK2dFM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248745; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9MYKoZRgqijJtTAATIS/Z9PJuep3yN5xuWDKdqT5dlQ=; b=g7hfYXXe/hWWlEgkEoMnUA8pR1uMQnLsNvBgIK/qVle7xMfoLTAy5XidJL2E7HWGRDtzlR5PZ1q1Bh5dvaJ2v3KQtNjRsxWanc8+jJsFYTF54KnYuUR9zbRU4po8eNu/uqlI7RrEjgQh6WnlNXYiRuTkVvpFijaxnzLPQR+vxYM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683248745282683.8760302672215; Thu, 4 May 2023 18:05:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujrp-0008Hs-8d; Thu, 04 May 2023 21:04:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujrk-0008Go-HX for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:09 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujri-0006xs-IU for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:08 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1a50cb65c92so8231235ad.0 for ; Thu, 04 May 2023 18:04:06 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.04.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:04:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248645; x=1685840645; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9MYKoZRgqijJtTAATIS/Z9PJuep3yN5xuWDKdqT5dlQ=; b=oq+Wr9q/HG4FDuAbKE0Si98DnfZ6X2MB9oaBbIjQ6bSikH4lPdGF1oJb8v/pH7Ejix riogKS263oeNMr3CPLn6xoRrzbz/XkH900c9ipdhoPyFux36Ddq5LZ7Y6pONx1wdi5el s/Gl9FgzI8+rc8Nu0HUFxdo6Fhc1VqVxiqSch4WFFYvfBPf7j4OvA1B+M4hT0nAbbNWF 79axN7TUEbWhS3/5uUZy6NqNMJpQZl/ZvqgmaIxVFLwY3x8c3TwNss1yv73IUVVZV6UN 1lHuL7vtmntPB1NckS3WfFUhh53uYe4yrpMVyMFmKkwfUhNHTXPS01poqMyG4c9GtTwZ vwFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248645; x=1685840645; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9MYKoZRgqijJtTAATIS/Z9PJuep3yN5xuWDKdqT5dlQ=; b=hHVWGElgzXYvuuHLvFcE/v2QJR8Yk2Vtqgw5PBV19zDABaxC3LE9svK1bhjVzrdqkq jqcfn0TcpqPlSVPgIfPTf0YYCvXS6ORQWfKDDjadJAsnb6ndIfC2jXGF3CA+SIhjKPwS w4CR2QNWKbm4lynrHk6/HKxeQvVpLc1Q0x/7ZHd8JRolvqBNo4gGokJw1Z5qUC1lLnYW g2bHNeKBHJJ/vlbsKpjYMx5nAbsO78X5SpQCFKPG9IGzDnL5xJDSsjzqYm3GuWGOtUeR p0K9+glGfH9R6iQtY+0Z2FAn8ZrwqjBT4Z9EyFLzp5c6XJ+MTLCSRReCOqFF7eKGfHCC gHUw== X-Gm-Message-State: AC+VfDxIKhmo5r3GWVpXcqyH48VKv0PB4WepIyyTvt1gxidTGrn9+ocB gU1jqh8Wbu9dkv3PfikF0U7JMsMGJe7hAA== X-Google-Smtp-Source: ACHHUZ4cI0Dk3HG2zJ4hRfLe2U3tK0ObMa5s2n/lTCedKyR7TIUvoIDrAKbWKEABQ6rGmeJ2HPWA1A== X-Received: by 2002:a17:903:1108:b0:1ab:624:38cb with SMTP id n8-20020a170903110800b001ab062438cbmr6165679plh.14.1683248644738; Thu, 04 May 2023 18:04:04 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Richard Henderson , Alistair Francis Subject: [PULL 14/89] target/riscv: add support for Zcmp extension Date: Fri, 5 May 2023 11:01:26 +1000 Message-Id: <20230505010241.21812-15-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=alistair23@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248745571100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Add encode, trans* functions for Zcmp instructions. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20230307081403.61950-7-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/insn16.decode | 18 +++ target/riscv/translate.c | 5 + target/riscv/insn_trans/trans_rvzce.c.inc | 187 +++++++++++++++++++++- 3 files changed, 209 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index ab780fa46a..55c9574299 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -21,6 +21,8 @@ %rs1_3 7:3 !function=3Dex_rvc_register %rs2_3 2:3 !function=3Dex_rvc_register %rs2_5 2:5 +%r1s 7:3 !function=3Dex_sreg_register +%r2s 2:3 !function=3Dex_sreg_register =20 # Immediates: %imm_ci 12:s1 2:5 @@ -45,6 +47,8 @@ =20 %uimm_cl_b 5:1 6:1 %uimm_cl_h 5:1 !function=3Dex_shift_1 +%spimm 2:2 !function=3Dex_shift_4 +%urlist 4:4 =20 # Argument sets imported from insn32.decode: &empty !extern @@ -56,7 +60,9 @@ &u imm rd !extern &shift shamt rs1 rd !extern &r2 rd rs1 !extern +&r2_s rs1 rs2 !extern =20 +&cmpp urlist spimm =20 # Formats 16: @cr .... ..... ..... .. &r rs2=3D%rs2_5 rs1=3D%rd = %rd @@ -97,6 +103,8 @@ @cl_h ... . .. ... .. ... .. &i imm=3D%uimm_cl_h rs1=3D%rs1_3 r= d=3D%rs2_3 @cs_b ... . .. ... .. ... .. &s imm=3D%uimm_cl_b rs1=3D%rs1_3 r= s2=3D%rs2_3 @cs_h ... . .. ... .. ... .. &s imm=3D%uimm_cl_h rs1=3D%rs1_3 r= s2=3D%rs2_3 +@cm_pp ... ... ........ .. &cmpp %urlist %spimm +@cm_mv ... ... ... .. ... .. &r2_s rs2=3D%r2s rs1=3D%r1s =20 # *** RV32/64C Standard Extension (Quadrant 0) *** { @@ -176,6 +184,16 @@ slli 000 . ..... ..... 10 @c_shift2 { sq 101 ... ... .. ... 10 @c_sqsp c_fsd 101 ...... ..... 10 @c_sdsp + + # *** RV64 and RV32 Zcmp Extension *** + [ + cm_push 101 11000 .... .. 10 @cm_pp + cm_pop 101 11010 .... .. 10 @cm_pp + cm_popret 101 11110 .... .. 10 @cm_pp + cm_popretz 101 11100 .... .. 10 @cm_pp + cm_mva01s 101 011 ... 11 ... 10 @cm_mv + cm_mvsa01 101 011 ... 01 ... 10 @cm_mv + ] } sw 110 . ..... ..... 10 @c_swsp =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3634137d85..6872d17fb9 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -757,6 +757,11 @@ static int ex_rvc_register(DisasContext *ctx, int reg) return 8 + reg; } =20 +static int ex_sreg_register(DisasContext *ctx, int reg) +{ + return reg < 2 ? reg + 8 : reg + 16; +} + static int ex_rvc_shiftli(DisasContext *ctx, int imm) { /* For RV128 a shamt of 0 means a shift by 64. */ diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_= trans/trans_rvzce.c.inc index de96c4afaf..a47959eb67 100644 --- a/target/riscv/insn_trans/trans_rvzce.c.inc +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -1,5 +1,5 @@ /* - * RISC-V translation routines for the Zcb Standard Extension. + * RISC-V translation routines for the Zc[b,mp] Standard Extensions. * * Copyright (c) 2021-2022 PLCT Lab * @@ -21,6 +21,11 @@ return false; \ } while (0) =20 +#define REQUIRE_ZCMP(ctx) do { \ + if (!ctx->cfg_ptr->ext_zcmp) \ + return false; \ +} while (0) + static bool trans_c_zext_b(DisasContext *ctx, arg_c_zext_b *a) { REQUIRE_ZCB(ctx); @@ -98,3 +103,183 @@ static bool trans_c_sh(DisasContext *ctx, arg_c_sh *a) REQUIRE_ZCB(ctx); return gen_store(ctx, a, MO_UW); } + +#define X_S0 8 +#define X_S1 9 +#define X_Sn 16 + +static uint32_t decode_push_pop_list(DisasContext *ctx, target_ulong rlist) +{ + uint32_t reg_bitmap =3D 0; + + if (ctx->cfg_ptr->ext_e && rlist > 6) { + return 0; + } + + switch (rlist) { + case 15: + reg_bitmap |=3D 1 << (X_Sn + 11) ; + reg_bitmap |=3D 1 << (X_Sn + 10) ; + /* FALL THROUGH */ + case 14: + reg_bitmap |=3D 1 << (X_Sn + 9) ; + /* FALL THROUGH */ + case 13: + reg_bitmap |=3D 1 << (X_Sn + 8) ; + /* FALL THROUGH */ + case 12: + reg_bitmap |=3D 1 << (X_Sn + 7) ; + /* FALL THROUGH */ + case 11: + reg_bitmap |=3D 1 << (X_Sn + 6) ; + /* FALL THROUGH */ + case 10: + reg_bitmap |=3D 1 << (X_Sn + 5) ; + /* FALL THROUGH */ + case 9: + reg_bitmap |=3D 1 << (X_Sn + 4) ; + /* FALL THROUGH */ + case 8: + reg_bitmap |=3D 1 << (X_Sn + 3) ; + /* FALL THROUGH */ + case 7: + reg_bitmap |=3D 1 << (X_Sn + 2) ; + /* FALL THROUGH */ + case 6: + reg_bitmap |=3D 1 << X_S1 ; + /* FALL THROUGH */ + case 5: + reg_bitmap |=3D 1 << X_S0; + /* FALL THROUGH */ + case 4: + reg_bitmap |=3D 1 << xRA; + break; + default: + break; + } + + return reg_bitmap; +} + +static bool gen_pop(DisasContext *ctx, arg_cmpp *a, bool ret, bool ret_val) +{ + REQUIRE_ZCMP(ctx); + + uint32_t reg_bitmap =3D decode_push_pop_list(ctx, a->urlist); + if (reg_bitmap =3D=3D 0) { + return false; + } + + MemOp memop =3D get_ol(ctx) =3D=3D MXL_RV32 ? MO_TEUL : MO_TEUQ; + int reg_size =3D memop_size(memop); + target_ulong stack_adj =3D ROUND_UP(ctpop32(reg_bitmap) * reg_size, 16= ) + + a->spimm; + TCGv sp =3D dest_gpr(ctx, xSP); + TCGv addr =3D tcg_temp_new(); + int i; + + tcg_gen_addi_tl(addr, sp, stack_adj - reg_size); + + for (i =3D X_Sn + 11; i >=3D 0; i--) { + if (reg_bitmap & (1 << i)) { + TCGv dest =3D dest_gpr(ctx, i); + tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop); + gen_set_gpr(ctx, i, dest); + tcg_gen_subi_tl(addr, addr, reg_size); + } + } + + tcg_gen_addi_tl(sp, sp, stack_adj); + gen_set_gpr(ctx, xSP, sp); + + if (ret_val) { + gen_set_gpr(ctx, xA0, ctx->zero); + } + + if (ret) { + TCGv ret_addr =3D get_gpr(ctx, xRA, EXT_NONE); + gen_set_pc(ctx, ret_addr); + tcg_gen_lookup_and_goto_ptr(); + ctx->base.is_jmp =3D DISAS_NORETURN; + } + + return true; +} + +static bool trans_cm_push(DisasContext *ctx, arg_cm_push *a) +{ + REQUIRE_ZCMP(ctx); + + uint32_t reg_bitmap =3D decode_push_pop_list(ctx, a->urlist); + if (reg_bitmap =3D=3D 0) { + return false; + } + + MemOp memop =3D get_ol(ctx) =3D=3D MXL_RV32 ? MO_TEUL : MO_TEUQ; + int reg_size =3D memop_size(memop); + target_ulong stack_adj =3D ROUND_UP(ctpop32(reg_bitmap) * reg_size, 16= ) + + a->spimm; + TCGv sp =3D dest_gpr(ctx, xSP); + TCGv addr =3D tcg_temp_new(); + int i; + + tcg_gen_subi_tl(addr, sp, reg_size); + + for (i =3D X_Sn + 11; i >=3D 0; i--) { + if (reg_bitmap & (1 << i)) { + TCGv val =3D get_gpr(ctx, i, EXT_NONE); + tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, memop); + tcg_gen_subi_tl(addr, addr, reg_size); + } + } + + tcg_gen_subi_tl(sp, sp, stack_adj); + gen_set_gpr(ctx, xSP, sp); + + return true; +} + +static bool trans_cm_pop(DisasContext *ctx, arg_cm_pop *a) +{ + return gen_pop(ctx, a, false, false); +} + +static bool trans_cm_popret(DisasContext *ctx, arg_cm_popret *a) +{ + return gen_pop(ctx, a, true, false); +} + +static bool trans_cm_popretz(DisasContext *ctx, arg_cm_popret *a) +{ + return gen_pop(ctx, a, true, true); +} + +static bool trans_cm_mva01s(DisasContext *ctx, arg_cm_mva01s *a) +{ + REQUIRE_ZCMP(ctx); + + TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); + + gen_set_gpr(ctx, xA0, src1); + gen_set_gpr(ctx, xA1, src2); + + return true; +} + +static bool trans_cm_mvsa01(DisasContext *ctx, arg_cm_mvsa01 *a) +{ + REQUIRE_ZCMP(ctx); + + if (a->rs1 =3D=3D a->rs2) { + return false; + } + + TCGv a0 =3D get_gpr(ctx, xA0, EXT_NONE); + TCGv a1 =3D get_gpr(ctx, xA1, EXT_NONE); + + gen_set_gpr(ctx, a->rs1, a0); + gen_set_gpr(ctx, a->rs2, a1); + + return true; +} --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249561; cv=none; d=zohomail.com; s=zohoarc; b=HBH5NT8UAjMLxuWRu1sGrDCpLBGYS5OzDkGdNQjpj828kHCmgACi9U3Ivx+p7IKj5jhDmqMoutpekJOen1ghFvdQV0FkfNq8l9dkKE/UqeNOeLYJGb4dLtD09gv1szdGrYGw9+bKbsmKJr41V9GmPkM5z6vJYr6Utqef3/JMvNE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249561; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GSrByuyf+Wr8vm0cbqDXr0XzyjlqN/trYJTbY/9Zt6c=; b=jh4WSN7IFaGFts7XK7YWOp8xFRlrfV1ol1SMB2kifZs4g6Xe5cgcHMt0a+230+c0ObdVXFpt7HVtcuh3fJ9bh50iLgg83+nlJd8iT0vBqLdNji2qDtwGS8LPIrVaXrbo49sBuAhy1S9o5h+3kZpZSsasj74FwonI4aQ9k5BNsws= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249561258367.23069201977785; Thu, 4 May 2023 18:19:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujrr-0008Oq-E9; Thu, 04 May 2023 21:04:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujro-0008HW-EA for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:12 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujrm-0006yv-2y for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:12 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1ab0c697c2bso10723165ad.1 for ; Thu, 04 May 2023 18:04:09 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. 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Add support for jvt csr. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20230307081403.61950-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 4 ++ target/riscv/cpu_bits.h | 7 +++ target/riscv/helper.h | 3 ++ target/riscv/insn16.decode | 7 ++- target/riscv/csr.c | 36 ++++++++++++++- target/riscv/machine.c | 19 ++++++++ target/riscv/zce_helper.c | 55 +++++++++++++++++++++++ target/riscv/insn_trans/trans_rvzce.c.inc | 28 +++++++++++- target/riscv/meson.build | 3 +- 9 files changed, 157 insertions(+), 5 deletions(-) create mode 100644 target/riscv/zce_helper.c diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e5f7c860d1..8d66365f60 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -176,6 +176,8 @@ struct CPUArchState { /* 128-bit helpers upper part return value */ target_ulong retxh; =20 + target_ulong jvt; + #ifdef CONFIG_USER_ONLY uint32_t elf_flags; #endif @@ -620,6 +622,8 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, = uint32_t priv, target_ulong new_val, target_ulong write_mask), void *rmw_fn_arg); + +RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bi= t); #endif void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); =20 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index fca7ef0cef..a92313a06f 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -319,6 +319,7 @@ #define SMSTATEEN_MAX_COUNT 4 #define SMSTATEEN0_CS (1ULL << 0) #define SMSTATEEN0_FCSR (1ULL << 1) +#define SMSTATEEN0_JVT (1ULL << 2) #define SMSTATEEN0_HSCONTXT (1ULL << 57) #define SMSTATEEN0_IMSIC (1ULL << 58) #define SMSTATEEN0_AIA (1ULL << 59) @@ -523,6 +524,9 @@ /* Crypto Extension */ #define CSR_SEED 0x015 =20 +/* Zcmt Extension */ +#define CSR_JVT 0x017 + /* mstatus CSR bits */ #define MSTATUS_UIE 0x00000001 #define MSTATUS_SIE 0x00000002 @@ -898,4 +902,7 @@ typedef enum RISCVException { #define MHPMEVENT_IDX_MASK 0xFFFFF #define MHPMEVENT_SSCOF_RESVD 16 =20 +/* JVT CSR bits */ +#define JVT_MODE 0x3F +#define JVT_BASE (~0x3F) #endif diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 37b54e0991..1880e95c50 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1142,3 +1142,6 @@ DEF_HELPER_FLAGS_1(aes64im, TCG_CALL_NO_RWG_SE, tl, t= l) =20 DEF_HELPER_FLAGS_3(sm4ed, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) + +/* Zce helper */ +DEF_HELPER_FLAGS_2(cm_jalt, TCG_CALL_NO_WG, tl, env, i32) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 55c9574299..b96c534e73 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -49,6 +49,7 @@ %uimm_cl_h 5:1 !function=3Dex_shift_1 %spimm 2:2 !function=3Dex_shift_4 %urlist 4:4 +%index 2:8 =20 # Argument sets imported from insn32.decode: &empty !extern @@ -63,6 +64,7 @@ &r2_s rs1 rs2 !extern =20 &cmpp urlist spimm +&cmjt index =20 # Formats 16: @cr .... ..... ..... .. &r rs2=3D%rs2_5 rs1=3D%rd = %rd @@ -105,6 +107,7 @@ @cs_h ... . .. ... .. ... .. &s imm=3D%uimm_cl_h rs1=3D%rs1_3 r= s2=3D%rs2_3 @cm_pp ... ... ........ .. &cmpp %urlist %spimm @cm_mv ... ... ... .. ... .. &r2_s rs2=3D%r2s rs1=3D%r1s +@cm_jt ... ... ........ .. &cmjt %index =20 # *** RV32/64C Standard Extension (Quadrant 0) *** { @@ -185,7 +188,7 @@ slli 000 . ..... ..... 10 @c_shift2 sq 101 ... ... .. ... 10 @c_sqsp c_fsd 101 ...... ..... 10 @c_sdsp =20 - # *** RV64 and RV32 Zcmp Extension *** + # *** RV64 and RV32 Zcmp/Zcmt Extension *** [ cm_push 101 11000 .... .. 10 @cm_pp cm_pop 101 11010 .... .. 10 @cm_pp @@ -193,6 +196,8 @@ slli 000 . ..... ..... 10 @c_shift2 cm_popretz 101 11100 .... .. 10 @cm_pp cm_mva01s 101 011 ... 11 ... 10 @cm_mv cm_mvsa01 101 011 ... 01 ... 10 @cm_mv + + cm_jalt 101 000 ........ 10 @cm_jt ] } sw 110 . ..... ..... 10 @c_swsp diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 8f4d5eb13f..777d7fbac0 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -43,8 +43,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *o= ps) =20 /* Predicates */ #if !defined(CONFIG_USER_ONLY) -static RISCVException smstateen_acc_ok(CPURISCVState *env, int index, - uint64_t bit) +RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bi= t) { bool virt =3D riscv_cpu_virt_enabled(env); =20 @@ -161,6 +160,22 @@ static RISCVException ctr32(CPURISCVState *env, int cs= rno) return ctr(env, csrno); } =20 +static RISCVException zcmt(CPURISCVState *env, int csrno) +{ + if (!riscv_cpu_cfg(env)->ext_zcmt) { + return RISCV_EXCP_ILLEGAL_INST; + } + +#if !defined(CONFIG_USER_ONLY) + RISCVException ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_JVT); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } +#endif + + return RISCV_EXCP_NONE; +} + #if !defined(CONFIG_USER_ONLY) static RISCVException mctr(CPURISCVState *env, int csrno) { @@ -3958,6 +3973,20 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env,= int csrno, return ret; } =20 +static RISCVException read_jvt(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->jvt; + return RISCV_EXCP_NONE; +} + +static RISCVException write_jvt(CPURISCVState *env, int csrno, + target_ulong val) +{ + env->jvt =3D val; + return RISCV_EXCP_NONE; +} + /* Control and Status Register function table */ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* User Floating-Point CSRs */ @@ -3988,6 +4017,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* Crypto Extension */ [CSR_SEED] =3D { "seed", seed, NULL, NULL, rmw_seed }, =20 + /* Zcmt Extension */ + [CSR_JVT] =3D {"jvt", zcmt, read_jvt, write_jvt}, + #if !defined(CONFIG_USER_ONLY) /* Machine Timers and Counters */ [CSR_MCYCLE] =3D { "mcycle", any, read_hpmcounter, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 9c455931d8..27f430ad74 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -329,6 +329,24 @@ static const VMStateDescription vmstate_pmu_ctr_state = =3D { } }; =20 +static bool jvt_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + + return cpu->cfg.ext_zcmt; +} + +static const VMStateDescription vmstate_jvt =3D { + .name =3D "cpu/jvt", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D jvt_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINTTL(env.jvt, RISCVCPU), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", .version_id =3D 7, @@ -395,6 +413,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { &vmstate_envcfg, &vmstate_debug, &vmstate_smstateen, + &vmstate_jvt, NULL } }; diff --git a/target/riscv/zce_helper.c b/target/riscv/zce_helper.c new file mode 100644 index 0000000000..b433bda16d --- /dev/null +++ b/target/riscv/zce_helper.c @@ -0,0 +1,55 @@ +/* + * RISC-V Zcmt Extension Helper for QEMU. + * + * Copyright (c) 2021-2022 PLCT Lab + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "exec/cpu_ldst.h" + +target_ulong HELPER(cm_jalt)(CPURISCVState *env, uint32_t index) +{ + +#if !defined(CONFIG_USER_ONLY) + RISCVException ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_JVT); + if (ret !=3D RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, 0); + } +#endif + + target_ulong target; + target_ulong val =3D env->jvt; + int xlen =3D riscv_cpu_xlen(env); + uint8_t mode =3D get_field(val, JVT_MODE); + target_ulong base =3D val & JVT_BASE; + target_ulong t0; + + if (mode !=3D 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, 0); + } + + if (xlen =3D=3D 32) { + t0 =3D base + (index << 2); + target =3D cpu_ldl_code(env, t0); + } else { + t0 =3D base + (index << 3); + target =3D cpu_ldq_code(env, t0); + } + + return target & ~0x1; +} diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_= trans/trans_rvzce.c.inc index a47959eb67..d75acbc4a6 100644 --- a/target/riscv/insn_trans/trans_rvzce.c.inc +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -1,5 +1,5 @@ /* - * RISC-V translation routines for the Zc[b,mp] Standard Extensions. + * RISC-V translation routines for the Zc[b,mp,mt] Standard Extensions. * * Copyright (c) 2021-2022 PLCT Lab * @@ -26,6 +26,11 @@ return false; \ } while (0) =20 +#define REQUIRE_ZCMT(ctx) do { \ + if (!ctx->cfg_ptr->ext_zcmt) \ + return false; \ +} while (0) + static bool trans_c_zext_b(DisasContext *ctx, arg_c_zext_b *a) { REQUIRE_ZCB(ctx); @@ -283,3 +288,24 @@ static bool trans_cm_mvsa01(DisasContext *ctx, arg_cm_= mvsa01 *a) =20 return true; } + +static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a) +{ + REQUIRE_ZCMT(ctx); + + /* + * Update pc to current for the non-unwinding exception + * that might come from cpu_ld*_code() in the helper. + */ + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + gen_helper_cm_jalt(cpu_pc, cpu_env, tcg_constant_i32(a->index)); + + /* c.jt vs c.jalt depends on the index. */ + if (a->index >=3D 32) { + gen_set_gpri(ctx, xRA, ctx->pc_succ_insn); + } + + tcg_gen_lookup_and_goto_ptr(); + ctx->base.is_jmp =3D DISAS_NORETURN; + return true; +} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 5dee37a242..5b7f813a3e 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -19,7 +19,8 @@ riscv_ss.add(files( 'bitmanip_helper.c', 'translate.c', 'm128_helper.c', - 'crypto_helper.c' + 'crypto_helper.c', + 'zce_helper.c' )) riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files(= 'kvm-stub.c')) =20 --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.04.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:04:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248651; x=1685840651; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qm7H0VopL6pYa5B3koINncB8EyaAHKhgvY10lBiE+6I=; b=W4cNZD1671eztUuONkYxurdPHfNbkYPzUOxYeuCr98ogfRdDHMLe/Znijnni97L3Sg uvHpUuJ7d5IHTZBO5MRpi+TYddR29SUonrPP3Us8ZmdRwsE8i53E5kLBnibqUGXhroYo FCQrmoqEX3Gu6pOoJS5ISNuF0xg0DTdX/+MFoDtYTv9YWwPbBedVWBl4fRUbjZXO+ecT QalPsNbAcu5Jan74Cs4dWOGtwivH6BIcwCOcYPxm9DkSd4cUEVMGCDq1JuW7T1iKfqmL vGPFYGjJvKV6fOmLsOSzUj7GHzgFaAf7nHsyg77JWPoZKaFBrdknMyPZ1PNL8JFq7/IV CkGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248651; x=1685840651; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qm7H0VopL6pYa5B3koINncB8EyaAHKhgvY10lBiE+6I=; b=J95bvxkCa8LyoYX2fnauhdCcUfMb+BsMZdmMvRFhS7Qle48II2/38Qpeld9TMH5Uz7 8ipKZ5VmMgJEo4IXQR4lmciy7hXIiLttTFQX5lS2+CuaTCnb1SCVtkFW7C+JwpSxvYwW ihOTN/3zWnQqQWLKw40pYQd89pdHKGALSJ1IHRssXxLvveLfu1+gNnSr+J/L0TbSappN V7DnanXsVxNYBNLg3vFeuQqZujtN0TliweRRdYmBMaQHVXZ2yC9JtAebeIEpyAyjYRpJ YU1OJnxiTc6bYhdChDqB400/ddOb8TkRqDKsDohNOp6DHifBtF6lP90NRgcjF7wO5Gg3 g4vQ== X-Gm-Message-State: AC+VfDxpS/nAvmZ5+fQNBJrKjIWIqAaaI/g9yh49dh0/UV6gHvCwGLxB MIb71f0UDoPzU5AEyrbhgye0dd0z5B5Nmg== X-Google-Smtp-Source: ACHHUZ7YUj/YQ5tufZw9dGFejl/0iNdakQUoSuq1yl2pWFx8Yk8lUUQqeO+BjAPNPArGIcZzZuFtug== X-Received: by 2002:a17:902:a716:b0:1a9:80a0:47fc with SMTP id w22-20020a170902a71600b001a980a047fcmr4859135plq.17.1683248651391; Thu, 04 May 2023 18:04:11 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Alistair Francis Subject: [PULL 16/89] target/riscv: expose properties for Zc* extension Date: Fri, 5 May 2023 11:01:28 +1000 Message-Id: <20230505010241.21812-17-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=alistair23@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249577129100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Expose zca,zcb,zcf,zcd,zcmp,zcmt properties. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Message-Id: <20230307081403.61950-9-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 97b0a77d8e..ed8dc61d10 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -87,6 +87,12 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_11_0, ext_zfhmin), ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), + ISA_EXT_DATA_ENTRY(zca, true, PRIV_VERSION_1_12_0, ext_zca), + ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb), + ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf), + ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd), + ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp), + ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt), ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), @@ -1491,6 +1497,14 @@ static Property riscv_cpu_extensions[] =3D { /* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), + + DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), + DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), + DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false), + DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false), + DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false), + DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), + /* ePMP 0.9.3 */ DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249333; cv=none; d=zohomail.com; s=zohoarc; b=cNRnJmZxzWKw3NOkyNdYzXo/dMWwWUZHa5Aj/ViaabZGYUaWq5++qkt0QYEDNVMmY80j/gw1vqusaSFgc0A5N2tjcLYoMEmkZJYcFfADajQ5zArGrAEJnJz0pzL4dHPaJVqBxRli46JgHLOmo7iHf5Y2m9CKM/FHANYDy5qtKoA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249333; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DBiMHpEPdnTcenWskCHjcg196WEb91leQf83xrs3KaQ=; b=UIihPfV0Hn1K3vRj+Y2RyLpUR27ng5qsqkFV+urIJeLzstNHmtnE/31j5v9H8HzDPBmAfmc3PztDNDHgl55Mf1BeZoJ9KFlLeITVZxpk+oEnS6WHUKWiK1q7qyZfH8z8OFbMWOeYJycI4LStYKwnI6sMCAm9kmxsKEaR2SecPZo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249333385740.834187899492; Thu, 4 May 2023 18:15:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujs1-0000At-GL; Thu, 04 May 2023 21:04:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujrw-000060-42 for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:22 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujrt-0006zu-6t for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:19 -0400 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-64115e652eeso16412912b3a.0 for ; Thu, 04 May 2023 18:04:16 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.04.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:04:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248655; x=1685840655; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DBiMHpEPdnTcenWskCHjcg196WEb91leQf83xrs3KaQ=; b=F/fULkHhquHG5XHnv4nqfP+O8/TVFENQCx6mI0wSTFDLuxNXlx84ICDpeiguFkal7C gC6W2bgvv00E45eGa1KUbfuAfsC20aNYPUDXAoUuE7azeSZ0p+mvRdMJZpll3/GCRRjb upzHVYIYtMg5ChY7Rkb7dn6QtvBY8gdAlOWQq8oryDw4KParUaBOm76AhnuUCOGHslf5 Z/8AqkgttzSDkyV6VyTl1TrreZrkv8awtwS7kX5Ge5/WfLnUc2Bgy3x9umhSxC5G/ExH WVtbaARyjXt8KAFbPtKkJWgbZH+DsG855paqEkFPTYh5uMwyamRvzwG+2PNkgzUZaozN +ADQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248655; x=1685840655; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DBiMHpEPdnTcenWskCHjcg196WEb91leQf83xrs3KaQ=; b=gsACgqgJajXK7Vkqkba8oO5TDMjHCIeF4oD1qHz4TaSsmstaVJcDe9Gcc64cznjecb /awVCacruk5ft/eiBdILRvkjhrQkT2/aldov4DfITTgI2VM0Z2yZjTOulDyT5bAR9XMe 3q7HlPM9ks7zxVtRU4TJIt3D4E6zKt3EOVJ7chpcgGoLUbHpeEkyqwHIRu5qpYSLP8hK vg0HPEGXr+CxBowpKDB/umSpKQHI4yeR8zWChfY8OCe1ZDl0tdMGgR2PtJyz4/1U9VK4 n48v2JGcJ9EzEEbWEOqUZhrJluwuSHddZvkW3ePUVpS5s/rNdBxqo5cw2Tp57UrgzoXe Swrg== X-Gm-Message-State: AC+VfDwKpURI3Yn7gHyhjOCrYAUMmXqtGrQKz5o2n3+sI0ks+fSLIrdd /V1ELHsG99nsh1VvUSp4reIkoUY2kfpslg== X-Google-Smtp-Source: ACHHUZ7JEvIK9Nld2A4ZhM8GNdst3Im08K9Mkmy5DKCPf+vG3Imz47GWCWtTE5vj43wCKz0YtDV4bQ== X-Received: by 2002:a17:902:f68c:b0:1ac:2bd0:1d9d with SMTP id l12-20020a170902f68c00b001ac2bd01d9dmr4938623plg.1.1683248654641; Thu, 04 May 2023 18:04:14 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Alistair Francis Subject: [PULL 17/89] disas/riscv.c: add disasm support for Zc* Date: Fri, 5 May 2023 11:01:29 +1000 Message-Id: <20230505010241.21812-18-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=alistair23@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249334305100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd* instructions currently. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis Message-Id: <20230307081403.61950-10-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- disas/riscv.c | 228 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 227 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/riscv.c index d6b0fbe5e8..e61bda5674 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -163,6 +163,13 @@ typedef enum { rv_codec_v_i, rv_codec_vsetvli, rv_codec_vsetivli, + rv_codec_zcb_ext, + rv_codec_zcb_mul, + rv_codec_zcb_lb, + rv_codec_zcb_lh, + rv_codec_zcmp_cm_pushpop, + rv_codec_zcmp_cm_mv, + rv_codec_zcmt_jt, } rv_codec; =20 typedef enum { @@ -935,6 +942,26 @@ typedef enum { rv_op_vsetvli =3D 766, rv_op_vsetivli =3D 767, rv_op_vsetvl =3D 768, + rv_op_c_zext_b =3D 769, + rv_op_c_sext_b =3D 770, + rv_op_c_zext_h =3D 771, + rv_op_c_sext_h =3D 772, + rv_op_c_zext_w =3D 773, + rv_op_c_not =3D 774, + rv_op_c_mul =3D 775, + rv_op_c_lbu =3D 776, + rv_op_c_lhu =3D 777, + rv_op_c_lh =3D 778, + rv_op_c_sb =3D 779, + rv_op_c_sh =3D 780, + rv_op_cm_push =3D 781, + rv_op_cm_pop =3D 782, + rv_op_cm_popret =3D 783, + rv_op_cm_popretz =3D 784, + rv_op_cm_mva01s =3D 785, + rv_op_cm_mvsa01 =3D 786, + rv_op_cm_jt =3D 787, + rv_op_cm_jalt =3D 788, } rv_op; =20 /* structures */ @@ -958,6 +985,7 @@ typedef struct { uint8_t rnum; uint8_t vm; uint32_t vzimm; + uint8_t rlist; } rv_decode; =20 typedef struct { @@ -1071,6 +1099,10 @@ static const char rv_vreg_name_sym[32][4] =3D { #define rv_fmt_vd_vm "O\tDm" #define rv_fmt_vsetvli "O\t0,1,v" #define rv_fmt_vsetivli "O\t0,u,v" +#define rv_fmt_rs1_rs2_zce_ldst "O\t2,i(1)" +#define rv_fmt_push_rlist "O\tx,-i" +#define rv_fmt_pop_rlist "O\tx,i" +#define rv_fmt_zcmt_index "O\ti" =20 /* pseudo-instruction constraints */ =20 @@ -2066,7 +2098,27 @@ const rv_opcode_data opcode_data[] =3D { { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf8, = rv_op_vsext_vf8, 0 }, { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, rv_op_vsetvli, rv= _op_vsetvli, 0 }, { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, rv_op_vsetivli= , rv_op_vsetivli, 0 }, - { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_v= setvl, 0 } + { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_v= setvl, 0 }, + { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, + { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, + { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, + { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, + { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, + { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, + { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 }, + { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, + { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, + { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, + { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, + { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, + { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 }, + { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, + { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0,= 0 }, + { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0= }, + { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, + { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, + { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, + { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, }; =20 /* CSR names */ @@ -2085,6 +2137,7 @@ static const char *csr_name(int csrno) case 0x000a: return "vxrm"; case 0x000f: return "vcsr"; case 0x0015: return "seed"; + case 0x0017: return "jvt"; case 0x0040: return "uscratch"; case 0x0041: return "uepc"; case 0x0042: return "ucause"; @@ -2307,6 +2360,24 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) op =3D rv_op_c_ld; } break; + case 4: + switch ((inst >> 10) & 0b111) { + case 0: op =3D rv_op_c_lbu; break; + case 1: + if (((inst >> 6) & 1) =3D=3D 0) { + op =3D rv_op_c_lhu; + } else { + op =3D rv_op_c_lh; + } + break; + case 2: op =3D rv_op_c_sb; break; + case 3: + if (((inst >> 6) & 1) =3D=3D 0) { + op =3D rv_op_c_sh; + } + break; + } + break; case 5: if (isa =3D=3D rv128) { op =3D rv_op_c_sq; @@ -2363,6 +2434,17 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) case 3: op =3D rv_op_c_and; break; case 4: op =3D rv_op_c_subw; break; case 5: op =3D rv_op_c_addw; break; + case 6: op =3D rv_op_c_mul; break; + case 7: + switch ((inst >> 2) & 0b111) { + case 0: op =3D rv_op_c_zext_b; break; + case 1: op =3D rv_op_c_sext_b; break; + case 2: op =3D rv_op_c_zext_h; break; + case 3: op =3D rv_op_c_sext_h; break; + case 4: op =3D rv_op_c_zext_w; break; + case 5: op =3D rv_op_c_not; break; + } + break; } break; } @@ -2418,6 +2500,46 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) op =3D rv_op_c_sqsp; } else { op =3D rv_op_c_fsdsp; + if (((inst >> 12) & 0b01)) { + switch ((inst >> 8) & 0b01111) { + case 8: + if (((inst >> 4) & 0b01111) >=3D 4) { + op =3D rv_op_cm_push; + } + break; + case 10: + if (((inst >> 4) & 0b01111) >=3D 4) { + op =3D rv_op_cm_pop; + } + break; + case 12: + if (((inst >> 4) & 0b01111) >=3D 4) { + op =3D rv_op_cm_popretz; + } + break; + case 14: + if (((inst >> 4) & 0b01111) >=3D 4) { + op =3D rv_op_cm_popret; + } + break; + } + } else { + switch ((inst >> 10) & 0b011) { + case 0: + if (((inst >> 2) & 0xFF) >=3D 32) { + op =3D rv_op_cm_jalt; + } else { + op =3D rv_op_cm_jt; + } + break; + case 3: + switch ((inst >> 5) & 0b011) { + case 1: op =3D rv_op_cm_mvsa01; break; + case 3: op =3D rv_op_cm_mva01s; break; + } + break; + } + } } break; case 6: op =3D rv_op_c_swsp; break; @@ -3662,6 +3784,21 @@ static uint32_t operand_crs2q(rv_inst inst) return (inst << 59) >> 61; } =20 +static uint32_t calculate_xreg(uint32_t sreg) +{ + return sreg < 2 ? sreg + 8 : sreg + 16; +} + +static uint32_t operand_sreg1(rv_inst inst) +{ + return calculate_xreg((inst << 54) >> 61); +} + +static uint32_t operand_sreg2(rv_inst inst) +{ + return calculate_xreg((inst << 59) >> 61); +} + static uint32_t operand_crd(rv_inst inst) { return (inst << 52) >> 59; @@ -3884,6 +4021,46 @@ static uint32_t operand_vm(rv_inst inst) return (inst << 38) >> 63; } =20 +static uint32_t operand_uimm_c_lb(rv_inst inst) +{ + return (((inst << 58) >> 63) << 1) | + ((inst << 57) >> 63); +} + +static uint32_t operand_uimm_c_lh(rv_inst inst) +{ + return (((inst << 58) >> 63) << 1); +} + +static uint32_t operand_zcmp_spimm(rv_inst inst) +{ + return ((inst << 60) >> 62) << 4; +} + +static uint32_t operand_zcmp_rlist(rv_inst inst) +{ + return ((inst << 56) >> 60); +} + +static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t s= pimm) +{ + int xlen_bytes_log2 =3D isa =3D=3D rv64 ? 3 : 2; + int regs =3D rlist =3D=3D 15 ? 13 : rlist - 3; + uint32_t stack_adj_base =3D ROUND_UP(regs << xlen_bytes_log2, 16); + return stack_adj_base + spimm; +} + +static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa) +{ + return calculate_stack_adj(isa, operand_zcmp_rlist(inst), + operand_zcmp_spimm(inst)); +} + +static uint32_t operand_tbl_index(rv_inst inst) +{ + return ((inst << 54) >> 56); +} + /* decode operands */ =20 static void decode_inst_operands(rv_decode *dec, rv_isa isa) @@ -4200,6 +4377,34 @@ static void decode_inst_operands(rv_decode *dec, rv_= isa isa) dec->imm =3D operand_vimm(inst); dec->vzimm =3D operand_vzimm10(inst); break; + case rv_codec_zcb_lb: + dec->rs1 =3D operand_crs1q(inst) + 8; + dec->rs2 =3D operand_crs2q(inst) + 8; + dec->imm =3D operand_uimm_c_lb(inst); + break; + case rv_codec_zcb_lh: + dec->rs1 =3D operand_crs1q(inst) + 8; + dec->rs2 =3D operand_crs2q(inst) + 8; + dec->imm =3D operand_uimm_c_lh(inst); + break; + case rv_codec_zcb_ext: + dec->rd =3D operand_crs1q(inst) + 8; + break; + case rv_codec_zcb_mul: + dec->rd =3D operand_crs1rdq(inst) + 8; + dec->rs2 =3D operand_crs2q(inst) + 8; + break; + case rv_codec_zcmp_cm_pushpop: + dec->imm =3D operand_zcmp_stack_adj(inst, isa); + dec->rlist =3D operand_zcmp_rlist(inst); + break; + case rv_codec_zcmp_cm_mv: + dec->rd =3D operand_sreg1(inst); + dec->rs2 =3D operand_sreg2(inst); + break; + case rv_codec_zcmt_jt: + dec->imm =3D operand_tbl_index(inst); + break; }; } =20 @@ -4359,6 +4564,9 @@ static void format_inst(char *buf, size_t buflen, siz= e_t tab, rv_decode *dec) case ')': append(buf, ")", buflen); break; + case '-': + append(buf, "-", buflen); + break; case 'b': snprintf(tmp, sizeof(tmp), "%d", dec->bs); append(buf, tmp, buflen); @@ -4542,6 +4750,24 @@ static void format_inst(char *buf, size_t buflen, si= ze_t tab, rv_decode *dec) append(buf, vma, buflen); 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.04.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:04:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248658; x=1685840658; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=o7BRB0VvCbUWARshHRUihAqCFtRb6NdUeQ4X2RByb3U=; b=Nr88YLii+qa8+NZIRknUzHOIsV04zQnxHbEbggfmEEBJl0Wv7+SPS4y9moJST09MdB m2d6ZVCeNWdkWDx03vtoPTcqVdPfetB6wzo2MyT1azvQIMAH97ErUJ8lqXWB/r347yyY 1oB6AllM7vAvIKIvkHOM/zldk/pbYj6MzxFaI1SQ5GFDtx8EZlgfq9U2LBhCit6u2VdX fAWuV/5qAWTnU0MSJ+X36US71c2j70Rw0LSzOv9NrnKV0+iOL/xrZXHbwfNlGIwBmsxT 9sI7J/gTM3JXTmRrHvUbnVW3GdOWWHCN7zu138drwJ0v0lRbbFPMHCtfU+X+tQv5LLt9 FSkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248658; x=1685840658; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=o7BRB0VvCbUWARshHRUihAqCFtRb6NdUeQ4X2RByb3U=; b=Yrb3BUHf9o28cCuCZqUs21/UH8tU9k0bw3VvkbXqLgxRq2BLCiKBd+PlkDtYO5NqN4 9tX+1XsdjCCsiCvRRts0DVNzlYN4hhL6e1WsAh3EV9n/YvjQm4eoZ8NycQWjuGvy7yF8 qd9Q7iGjwwlJ8uzYl0k0c/bstBe3pyDu0uE5abkAvEhUddlRe/wW9jI1qNGX/lRrRTMd DJCYzgKfO1Ac+Ieop6CY+WNSi9S9CaX5ICiL8rNGnUG43bO96fZOPL8m93cmR0N5lqzi rHHWJrcCeMV0VuHA/kmTfQr9AZIlfiBBi+VwJHWbXj0uhdtMBtX30OwitAoI1qKgyiqh 1gUw== X-Gm-Message-State: AC+VfDyvsCd/7wzC8ghKUo2AAQAoYUwTpFiMhFCfhVyf8UJw1OQ0FuOA VZhJDLxOWnW43aKRYyLLO1MzAsip83tvPA== X-Google-Smtp-Source: ACHHUZ4wH1vySHr5v8pz05ATU9WwkJCCjrNgyRqLSA6nggYJO07wsYn8uOP4gROpJwpL57BoFoETjg== X-Received: by 2002:a17:90b:289:b0:24e:39d2:ab80 with SMTP id az9-20020a17090b028900b0024e39d2ab80mr4187689pjb.4.1683248657792; Thu, 04 May 2023 18:04:17 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Alistair Francis Subject: [PULL 18/89] target/riscv: Add support for Zce Date: Fri, 5 May 2023 11:01:30 +1000 Message-Id: <20230505010241.21812-19-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1036.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248874627100007 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Add and expose property for Zce: * Specifying Zce without F includes Zca, Zcb, Zcmp, Zcmt. * Specifying Zce with F includes Zca, Zcb, Zcmp, Zcmt and Zcf. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Message-Id: <20230307081403.61950-11-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 12 ++++++++++++ 2 files changed, 13 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8d66365f60..5f38b0adc0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -443,6 +443,7 @@ struct RISCVCPUConfig { bool ext_zca; bool ext_zcb; bool ext_zcd; + bool ext_zce; bool ext_zcf; bool ext_zcmp; bool ext_zcmt; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ed8dc61d10..cd9e7bdce6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -91,6 +91,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb), ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf), ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd), + ISA_EXT_DATA_ENTRY(zce, true, PRIV_VERSION_1_12_0, ext_zce), ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp), ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt), ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), @@ -945,6 +946,16 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU= *cpu, Error **errp) } } =20 + if (cpu->cfg.ext_zce) { + cpu->cfg.ext_zca =3D true; + cpu->cfg.ext_zcb =3D true; + cpu->cfg.ext_zcmp =3D true; + cpu->cfg.ext_zcmt =3D true; + if (cpu->cfg.ext_f && env->misa_mxl_max =3D=3D MXL_RV32) { + cpu->cfg.ext_zcf =3D true; + } + } + if (cpu->cfg.ext_c) { cpu->cfg.ext_zca =3D true; if (cpu->cfg.ext_f && env->misa_mxl_max =3D=3D MXL_RV32) { @@ -1501,6 +1512,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false), + DEFINE_PROP_BOOL("x-zce", RISCVCPU, cfg.ext_zce, false), DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false), DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false), DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249345; cv=none; d=zohomail.com; s=zohoarc; b=KYUHAoLr1mOoa4zMb4IKV8+H86OirInHcQ6UnsGW4gX9Hp5TLC204skriSOWRc+kuDho++ZbEUzHFCwVXruCbYKAOxOvggOG+b9tv5Cw/rNWmkEV26Jbds7i3X/y/OV0YY8Un6mIvAal4gxsUSYBS6kLMxS/L/H99alkmgNvXKg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249345; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mEzcRbLfJm5D5Qt3BEMThpbyDkKnvKMH/BrAOrVTgag=; b=cHjLJGbYvnb3V4+H1+dbw3nrZHimNA5Kd36TbyeBwsUaI26I90YgbntUt62rv4OG/ZXkEqQ8+fnYGdvxaud5FslXXl2Y7FbfHxM+oj0QLgvOYq5Z5cbQ6jd85Bx2CJhbW8A052nzcBAsf1tOlrv2KDvkPTvrmg2OzMnquenSe6o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168324934598198.67448197230044; Thu, 4 May 2023 18:15:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujs5-0000RR-74; Thu, 04 May 2023 21:04:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujs0-0000Au-Ad for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:25 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujry-00070g-Om for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:24 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1aaf2ede38fso11257525ad.2 for ; Thu, 04 May 2023 18:04:22 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.04.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:04:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248661; x=1685840661; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mEzcRbLfJm5D5Qt3BEMThpbyDkKnvKMH/BrAOrVTgag=; b=DLALL8JRvAnhQmG2L234aS2lLAJB9yv+1gq4+0dZGpzqFYJMKeIrc0p2rAvjDEhFgn Slyq43kQXAkNQuXWsCDT2qF+aQNr/MSg1K6/IAZrWJQnm764XOogokMKD+Hb538xB2bI ohHSrdU8nlW6AY6AFMXGDg3V3TaIe6O2TcePBWOKqaHB69g+mhm3TTHJHqIlH+pVlbNQ spse99Yv/2D54dictSKvNVb2OYx2GugOJ4vS+ct2yIP3j0oXI4v0FwsXi8dyd0rqfVhb G3PgP2pl9UvJYjLxNxxIMHOnj7YolKqIR7xbPwtC5sLg7seV5IL1iy1U1HUNkmFMnH3L lUyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248661; x=1685840661; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mEzcRbLfJm5D5Qt3BEMThpbyDkKnvKMH/BrAOrVTgag=; b=Jo9DMD+/Ph2CLJ4NBy7A/k1hQk0lTXVTB6xbH0zd0lApW27Yz6mXOH/m85l0CBcB+7 1sJYVJ0U8X081OoUpq1NE0CP9TzCUywkrFbq6JyPNetsP4LKYrryDz6OL9iZugMPkkM2 g0N+AfVkZHq1qkbK7am3ePgPDdkBwtmeCoPvXHkbQbw+tGlHsbgvBb6HlssuvnH/eEzp 3T6Vtv4lSupNIxyoNcmD2jPV2ozgj85n0DdMVGwJLvzsMH37cHvBq8haKDMY49v2VNOV btQv9Y/IQ0WnO57vo+TN+kNaawkG+ezKZhJ5RS6kXTlfB5uE2f64Zz4iO2EzopIkA0y0 VS1A== X-Gm-Message-State: AC+VfDwNOQjcqwo6TJpyrZOsh+V5ex1BJ2Dkmp+GPd/ABTV57Ev9fIpA of+x2dBZTy33a1RaWI7//VbMneuvkl9JtA== X-Google-Smtp-Source: ACHHUZ5+os7302pbUyGaZGC0YxnlSyzvGnKXazllmosAUGY0wRFcsvQQrRDQF2BVTSsKl3dmclLn6w== X-Received: by 2002:a17:902:82c5:b0:1a9:826c:8f44 with SMTP id u5-20020a17090282c500b001a9826c8f44mr5959921plz.32.1683248661320; Thu, 04 May 2023 18:04:21 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, LIU Zhiwei , Weiwei Li , Alistair Francis Subject: [PULL 19/89] target/riscv: Fix itrigger when icount is used Date: Fri, 5 May 2023 11:01:31 +1000 Message-Id: <20230505010241.21812-20-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=alistair23@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249346805100003 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei When I boot a ubuntu image, QEMU output a "Bad icount read" message and exi= t. The reason is that when execute helper_mret or helper_sret, it will cause a call to icount_get_raw_locked (), which needs set can_do_io flag on cpustate. Thus we setting this flag when execute these two instructions. Signed-off-by: LIU Zhiwei Reviewed-by: Weiwei Li Acked-by: Alistair Francis Message-Id: <20230324064011.976-1-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_privileged.c.inc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index 59501b2780..e3bee971c6 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -77,6 +77,9 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) #ifndef CONFIG_USER_ONLY if (has_ext(ctx, RVS)) { decode_save_opc(ctx); + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_sret(cpu_pc, cpu_env); exit_tb(ctx); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; @@ -93,6 +96,9 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY decode_save_opc(ctx); + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_mret(cpu_pc, cpu_env); exit_tb(ctx); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248750; cv=none; d=zohomail.com; s=zohoarc; b=Ve0hTYzNJAj954dXV8FZVR12otAQxyFUyrlPoM0vjOJSrrDjiNpMyw2phuRj+RPicHHDvUyaQrN8tocQuIqg6Q/cai/IGq7AVo3PeIebBm9D2vFN71uAJ5MoNL6pUy04/mgy9I9tnZmPuWlrGxkVMzlKN6G1Z7RdqQQjM4jXH+8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248750; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9xDxBR/PUFexvpCP/tmv2vmExxBV4so69CnlLNO4rLM=; b=PVF8M57me4x1tI6JOwY6OS4QACRHeQUnDXRX/cnr4gt+Zt0eWHfQDM0is8WJ7R4JUlGmmZVtUBxRdfE5cWmJyppywnLCB6EVjjoYUstl+L4WeHaGhn9/GzvJ1ATMyHN8/zYP1VWqW4+Kq8hklQhTJTwIffJ6Mh/PJQx9tPV/zTQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683248750773384.8697032019692; Thu, 4 May 2023 18:05:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujs6-0000gS-NW; Thu, 04 May 2023 21:04:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujs4-0000UX-DU for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:29 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujs2-00072n-Qq for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:28 -0400 Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-52079a12451so801931a12.3 for ; Thu, 04 May 2023 18:04:26 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.04.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:04:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248665; x=1685840665; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9xDxBR/PUFexvpCP/tmv2vmExxBV4so69CnlLNO4rLM=; b=sf5F9KLPe7bQEBXsw1ELgNj21Ec4Y1N7DkfH+SvWEG9mhDw/UdS3+0qMeJRdr04ezd ZPuOEMcjxwXcbVKmDhMqjT8omoJgRzcCuNsJ/9zwhGjojopPVKBFyD1TEKujJ5zaiXzx xxWlo2Ee7xACffFgvGbI/77LYugO9TT1ss5bAFl/djfdgKt95KWP8DAP+nbtRjPcaBwr LOTpVWG/8/d1ASJs+YbpyxgiEJ8izBpvv65phgx2E6jMP91xZp0bt8YUpUxaye6QHizE t2GE43sYqcj3GswaskrcHAHrYx/M0sF4vIvXD4UFKUvFrnMTuFKNVgL00f6aGs5Hm6Lm goeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248665; x=1685840665; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9xDxBR/PUFexvpCP/tmv2vmExxBV4so69CnlLNO4rLM=; b=R0iyJIDt2iaztHRaOui2rR8OEIKoa3d0pN0CvjX75s1/nDTbRke+x0lXfV8gsiFS+u hld3ZybTblu4xRHnLejbpuLuuWLezXnmDCYRPBln9+Ubq++zmpsp3/pIqikZyeyLJ0PW Ob7E3H6wR18vnQtHbjp2XM6ws9Q3BogjfB7sN5dznwwPqLTwDAXlF0+qgzhodlnRpiMR e+qJ5u+sCl1kCH/cmUHiuAw7Hl56UFWWCYwTjF+cFsqYXri4id3pQRL+Z5Vj3EzM3gZ8 yLAJeC5ctYSqaDgCXflyQHaZyymzp3/T0i6dtOCz2m0NhIESO8G9PrhKlkE141OvwlkT faNw== X-Gm-Message-State: AC+VfDxEpQ/WmBdInM+YVVUZQ/3+Jov32F3K42frcfCQ2DS3Ql021eoC fA3AKQfz6YTZXKky1qUVUZ7vIxvVeFc37g== X-Google-Smtp-Source: ACHHUZ5h3v1DaNDxg8AzxjPvwyvu2QJ1aRs68B4N2N3qwtknmedsKvWM8X3EsKZSoLJORSzipHSuMw== X-Received: by 2002:a17:902:b40f:b0:19e:839e:49d8 with SMTP id x15-20020a170902b40f00b0019e839e49d8mr4991363plr.59.1683248664998; Thu, 04 May 2023 18:04:24 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Richard Henderson , LIU Zhiwei , Alistair Francis Subject: [PULL 20/89] target/riscv: Remove redundant call to riscv_cpu_virt_enabled Date: Fri, 5 May 2023 11:01:32 +1000 Message-Id: <20230505010241.21812-21-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248751932100023 Content-Type: text/plain; charset="utf-8" From: Weiwei Li The assignment is done under the condition riscv_cpu_virt_enabled()=3Dtrue. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-Id: <20230327080858.39703-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 824f0cbd92..e140d6a8d0 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1706,9 +1706,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_swap_hypervisor_regs(env); env->hstatus =3D set_field(env->hstatus, HSTATUS_SPVP, env->priv); - env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, - riscv_cpu_virt_enabled(env)); - + env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, true= ); =20 htval =3D env->guest_phys_fault_addr; =20 --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248852; cv=none; d=zohomail.com; s=zohoarc; b=eghMA9/jAM2g2oVtu5Hs+wbVdbNabmj/ExKbUdRzB3U+dBDYNoSwVcrw4mzsx88/L3LwzfJBVbcqfhnteaUC/77Z27x8V82Rs08rJ6oSCUOq3Ne1bu7R/qy5F0rUHhE5xUN9hoxRmU3tGX9p9oRU+VpWCelANkTruf3vN8MzmEE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248852; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RBxSXudG5zQ++9UGGLr3DqQBdQ9CGYyS1kJRqGjUyQg=; b=ehVsICziHddokUxLOsfqM8CLSzM1meLAoZAGkC85mLfRBdBgkFVCQp3Tey56zChIeILhppDh0TY0B8JLE3jzhMmIDD5C4/7RsM9p+y//EDCAk02TSEQWxJnIW/OUUehS2rexA7ivrMiJDcamNdQ3P5QvfB5jMXcyFueF8cb2AYc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683248852876737.652966031456; Thu, 4 May 2023 18:07:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujsA-0001Dn-MD; Thu, 04 May 2023 21:04:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujs8-0000xF-Jy for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:32 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujs6-00073U-Bs for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:32 -0400 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-64115eef620so16297693b3a.1 for ; Thu, 04 May 2023 18:04:29 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.04.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:04:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248668; x=1685840668; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RBxSXudG5zQ++9UGGLr3DqQBdQ9CGYyS1kJRqGjUyQg=; b=KOnVwhKNTJvV3kF/1Gumf+NnSbRWpzFejnCkSDwj5I7pZJJHYgGSQ8aQgL33gjFlV0 Vezu8vNNe16ygErvtBwbEtkDqev+ouwbKCuMOfLDkfz07dfVJ8TvSy6fMfInq62OJwi3 gEXXyuawU5FXRC0DHVDCb1Lckq4qMjgvGvzmWDtCgRtL7rBZKG3kNN7Gq7mgB5tVSlWo ZcoO84ycu5gAnavxS08MxOFrP52DfyFWGHQZcJvn2LMXS+WgMduqlJ6eZZdfg7l2dmOz AFAVk+xMu6/AfmK3Xx4cQaBGlnmSzzQtXzX7Ddsk/l17OHNZSMfGLwjQGFGSq41VEPZh /8zA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248668; x=1685840668; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RBxSXudG5zQ++9UGGLr3DqQBdQ9CGYyS1kJRqGjUyQg=; b=ex7MOelk/qOL5Zd3Oyt4qdQ2GIa0DZ2Kd5NQty8Eg1TikKam1HaxLeqUJcQvW7BJ8A stm5NM3x8xSSMW8CLiwudVrSWaAHREK8btA/7pKuPuV3vDh1pjNgzkSRtgbur7S17JdK LlW5GBdNX4CCgF8PVOwySPFcgSWQ5SwEE6BVGfXHrwIlGNUkQ6p0Z7yweT8vtvUS76a2 Gf657nuZV9y/wVRnSwLm5Ov6x28xHf2isz4XyNFOXsaJteMkbZH8kiXyKu0rs5GNCnwG /Y4EEtdG/sCkfCVpXcJ0a2+qntlM9xkrl4u/mmwZjAVmaPN8AXUa0TVWxOYOPUSUUoZZ /1dg== X-Gm-Message-State: AC+VfDyNT/GBaHhXs16mycwyrKE0g3Gj8vEU7KPn3cji0MOLwdWIAq1k ohJxttug4pnlmjh6zxYnEeZCKnhEyTJvsA== X-Google-Smtp-Source: ACHHUZ5toR7TSvlH4tg9PQudTfDErpcRSKXDRmSB0MX3MgMfQaBfYRt6L0n35foz9NXNsMN8y0peTA== X-Received: by 2002:a17:902:db08:b0:1a6:7b71:e64b with SMTP id m8-20020a170902db0800b001a67b71e64bmr6708918plx.15.1683248668585; Thu, 04 May 2023 18:04:28 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Richard Henderson , LIU Zhiwei , Alistair Francis Subject: [PULL 21/89] target/riscv: Remove redundant check on RVH Date: Fri, 5 May 2023 11:01:33 +1000 Message-Id: <20230505010241.21812-22-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=alistair23@gmail.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248854112100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Check on riscv_cpu_virt_enabled contains the check on RVH. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-Id: <20230327080858.39703-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/op_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 84ee018f7d..1eecae9547 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -278,8 +278,7 @@ target_ulong helper_sret(CPURISCVState *env) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } =20 - if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_VTSR)) { + if (riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_VTS= R)) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } =20 --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248710; cv=none; d=zohomail.com; s=zohoarc; b=Hu5wfIMQqY+nR9EFVUf1CmKdy1NaQQ8X4Sfz0T3X+WaiqnVl7WzwMhmv9cmKPK+kAgveSRyZvU/DaLoixLoEq/tY6PppHYIV0FYJX7eue0KH64tUboUmOiTK85EuQEDEkxiv3F5Oi+uKd+gc3lliZZUBJC1AOHd63zYQGGryhUQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248710; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BIu+1DjWI3CsiFnOxaA3b+UpyBWG0H0jnr/0F2pEbU4=; b=EO+x4V27OX/lzH20Wfe45bGmnW6VScmFrE6ECjt++uWiPiXX/VPBXQvQSobsOdYUqE3PhBr7bHrCtnZebMn0acQprwlk2BBYudex72+rlqOOc3QzzD7cZofXZduuLrvrttuHYf/naZwLnrJ95gkXKaJaino9lxHmP5cMsnbj6mo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683248710872758.1505255299754; Thu, 4 May 2023 18:05:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujsD-0001ds-NT; Thu, 04 May 2023 21:04:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujsB-0001Ps-TK for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:35 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujsA-00074J-04 for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:35 -0400 Received: by mail-pj1-x102c.google.com with SMTP id 98e67ed59e1d1-24e1d272b09so932073a91.1 for ; Thu, 04 May 2023 18:04:33 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.04.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:04:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248672; x=1685840672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BIu+1DjWI3CsiFnOxaA3b+UpyBWG0H0jnr/0F2pEbU4=; b=idqG9pyl0Ay/Zj+OXiE20yOSkXj0KaaoSNN7T3AuXLiq3Y78HFzJlD/lIKHPfQ0fAb jfVOwTShfHVns+l8AsIf0D2lMjjgieoABPInJT3KEI2HbcBd66AqJlo/Rz4xNdRVwN3C HEGKuB+Z4l+wRVHfcwcf7ehKYFbdIgzVNtV1WjSyEPqQpoNoRXEWzCps3XURcCpPnEwV KDdvvtnoog/VW+1+VjbVfrBs++gQJGxUBJ/GJjbnfAhvQhSKLc8CBXOY7jltk5s7Tj+q vGUQKxmm6Oy/xXQMoxeQJtQYykcd6TZRuioPenRXS+cZOsqo2W/Hjp0tDX/NPZiyjdk/ FcKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248672; x=1685840672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BIu+1DjWI3CsiFnOxaA3b+UpyBWG0H0jnr/0F2pEbU4=; b=AalZflTw4LCsargGvgE/hQSkslMqwzmP5rWpCaU1Wfv8XcoozAnadTDQRJmjDcUvWv GwhIjIctxsCCM5GL5NqzXFSiemz5IVUtpt7sg9SLatodb5JdetVk3xD2featkzaKW5PX 5TahwHxycYCH2sSBf4TtnwPx33TkfSsymmNRFZBUQZouiuSYBUfv/1k7bZ/KHhSsYqMu s44BSul6ZnDb5MgQnBIE7zHxRdBnhI064u5dQtirxKpLRjMJT1LLd19YTH6nyjK/pQY6 XfFLdkc6WTUMIm/HX+jFwzpoi0b19drJX2xvcddpv0OpYRaNEjnYZcZLibfClKR6kTlZ 5b7A== X-Gm-Message-State: AC+VfDxZ72L+E8HXNcg/O0sBWHgDSSs0u1GbeullPtE8XRc5we8xnsKF xNUfaVgURSLTrOSBtuqXuoXFWHr7mx0u0A== X-Google-Smtp-Source: ACHHUZ5VIhKitPY+sllVQvpZi4pRG2M52Zt2JSJWnIfBBym2NK2ABjQwKYTGsBWqklba+hOlSz/dWw== X-Received: by 2002:a17:90b:3685:b0:24e:2248:31c with SMTP id mj5-20020a17090b368500b0024e2248031cmr4153589pjb.22.1683248672187; Thu, 04 May 2023 18:04:32 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Richard Henderson , LIU Zhiwei , Alistair Francis Subject: [PULL 22/89] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled Date: Fri, 5 May 2023 11:01:34 +1000 Message-Id: <20230505010241.21812-23-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248711726100003 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Since env->virt.VIRT_ONOFF is initialized as false, and will not be set to true when RVH is disabled, so we can just return this bit(false) when RVH is not disabled. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-Id: <20230327080858.39703-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e140d6a8d0..62fd2c90f1 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -560,10 +560,6 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_u= long geilen) =20 bool riscv_cpu_virt_enabled(CPURISCVState *env) { - if (!riscv_has_ext(env, RVH)) { - return false; - } - return get_field(env->virt, VIRT_ONOFF); } =20 --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248763; cv=none; d=zohomail.com; s=zohoarc; b=FEVbbU6lLiVMhMQUkAnR5MdJgdLdGpmhL6Rrx9P9R+sSFmy36fE8hL3ML9gxuFWeR3FBxSGmPTUM2uT6Rv4DW+JLqd3H7R1VP/8PKMoCgMe7z40iydlROgBZfIkkcRF3D6W1qQI/hTthznVdwLa/1NUQYTJUe8k0rizuVscNF6Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248763; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PjjcvaCoss6g2C9XP+Va16VVgd05AoBG7zQPBN7oS/g=; b=dDxnfknpMFlcgP72eYS+IBX082gw3cyG2vBMDcZRetjXuZGzeV6v0g9qf2iI9QTh429bQhknMW4wzcb9a8hOnysMRbgceVn6yfYO1w2O5j0iWnZXQggX+v5I9XpI++NcetpmN/3+hdVhmMhNLq/jVIU/OudCKM+ZulKSTvGJILw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683248763645345.62117929159297; Thu, 4 May 2023 18:06:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujsG-00025d-CF; Thu, 04 May 2023 21:04:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujsF-0001wb-Ce for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:39 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujsD-00075A-Lq for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:39 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1ab13da70a3so11258645ad.1 for ; Thu, 04 May 2023 18:04:37 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.04.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:04:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248676; x=1685840676; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PjjcvaCoss6g2C9XP+Va16VVgd05AoBG7zQPBN7oS/g=; b=XX7xMqzWtmb4dPB9Kq2amVx0nXiZ5Hofz84mqlhoW1scvoCJg7+VoBKCJ9TCEeaEId r5r8ui875zABFQYKb6X8LjBNkAgzC7COxNB6egHyTjd7Ra52rT29KlPCZ+XV3WPuX4To LiH29d7H4IzR7iJsT9+SfraI3eqC7M19eiXRKi017141kCc52cUzk0t74KnzOInUxrP2 1rLbeLKI2TRupUQVi4J/wJRzttVnrBYu9KvdycYp7VY3GL1CuGcnDKkK1adcZpDa1jdH v5eV2JQNDubIGDHrRCU6IebGlgolJqoPMCEpDedQy/VmF0wdbZRcfVTUYsusRoizIXn2 E3Ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248676; x=1685840676; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PjjcvaCoss6g2C9XP+Va16VVgd05AoBG7zQPBN7oS/g=; b=dchF9gVtg2JhQwmjDsO+JZ8gt+BLW6lj9BNXwNDjUfRcEp3h8UDg2cEP8ShzL4ofhK jTvjf6AGJALMgzw+GWuOtDbywXBODMG4Jw5tp00Mb/PpqYSlqhULse3gTuVsRSWybEKc zdb15k/OwLrnhDuMhCRW693iy8xNW7yit7vQaUTAObx/dTqo+PjWNWD53pf9PaGCtPoD FCvan7HsWXkL9Ujx+2hbikOfo2niHuby657T2nrBZwMMSx0YmWsiZHwgBVrU07gShfyK ccibuhMhjdM1d5ag8wsW9CLq6q5MAgrmVceEe2VV2n74RfEb7qDMq8HwqVaQJ+mZemoB JQew== X-Gm-Message-State: AC+VfDyoAdmBvPQ7+aVSV5OR4lvneqhLCXOFBxCrjYss+sFCz8Vv3VvY OUZXrmZWOkr22phwP36tRUIfyTDrB8K+BQ== X-Google-Smtp-Source: ACHHUZ6jGuN/x6qkyqCpe1V93KMXPRu8DLZ+SCAiUb0HjR1X6VAf5Pzjg1ScSigxNa1418yEzRP7Ug== X-Received: by 2002:a17:902:da90:b0:19a:a520:b203 with SMTP id j16-20020a170902da9000b0019aa520b203mr6357637plx.25.1683248676134; Thu, 04 May 2023 18:04:36 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Richard Henderson , LIU Zhiwei , Alistair Francis Subject: [PULL 23/89] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled Date: Fri, 5 May 2023 11:01:35 +1000 Message-Id: <20230505010241.21812-24-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248764134100003 Content-Type: text/plain; charset="utf-8" From: Weiwei Li In current implementation, riscv_cpu_set_virt_enabled is only called when RVH is enabled. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-Id: <20230327080858.39703-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 62fd2c90f1..b286118a6b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -563,12 +563,9 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env) return get_field(env->virt, VIRT_ONOFF); } =20 +/* This function can only be called to set virt when RVH is enabled */ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) { - if (!riscv_has_ext(env, RVH)) { - return; - } - /* Flush the TLB on all virt mode changes. */ if (get_field(env->virt, VIRT_ONOFF) !=3D enable) { tlb_flush(env_cpu(env)); --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248977; cv=none; d=zohomail.com; s=zohoarc; b=PFZN5Gmo7xaAxiWiyRlYinjreMM+kYP0gIh1skUe7Z/tEGV5RYIeGdH9tlvOTLY20OeLTIX04YlT2RLOpCSMOt0ipNfI7j0Upiq7V8vky6SkxNaTnSiitmHQvweqRcZFo0A5R7z3adphqS9CscIlbFoWlUHQ+kYP3qh7LBs5/mg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248977; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FFi9k6FVuhmjeEuDvSU0Hvy8dG/Qgn75vXEPkKyXHjg=; b=XHOKBkBgH9Z7fiXXV0gHeRulI6feYNEgXRFmcG8K68YvH5uWbxGBK14gZAaDySVPFuHZyeJFGZ9pnYVLRrPF4ELSKhj3bQ5NjlXQLUyhrQrdBvx9uowfO1MWO/GzNOQ8v9/rBv6ZjBcl49xGGapCxHP6JxyzbPDFmsB5E7y4DaQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168324897739466.25970421697957; Thu, 4 May 2023 18:09:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujsK-0002af-NC; Thu, 04 May 2023 21:04:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujsI-0002UX-QD for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:42 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujsH-00075p-0b for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:42 -0400 Received: by mail-pg1-x532.google.com with SMTP id 41be03b00d2f7-52c62a71541so802135a12.3 for ; Thu, 04 May 2023 18:04:40 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.04.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:04:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248679; x=1685840679; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FFi9k6FVuhmjeEuDvSU0Hvy8dG/Qgn75vXEPkKyXHjg=; b=C5oMeKP0tnxh/plRDlP5bRmlKpjm/Nl6vqs7Vm+UbUHjwWGfTL5zrFm4WaKOE2B+Aj jWUyIzc5dUsCBt/FD6XkUTO8efBrWpaScOkoNIxatElNyiCOys9NNjpGTdJp9Tm+qQxD 8a2itbJyTCDOjOFHj7Zwmzr2A/k0N+l/TywQVPaWuvpp1TMVgXcl3i5xHJPi6VDPDmRJ xXc8Z2PLsKRNsQNNTpHP/Ef66P3+nXd12CC7Q8Y03rMT06KXaevzd57aT0+qkAXDnqz9 xAAFMmiILCmnpsL+vEqw1+L+vTkDSpzlw2tu8sshygZaJ9OYKmX81jOsDeitvD7/IvfY P+bQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248679; x=1685840679; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FFi9k6FVuhmjeEuDvSU0Hvy8dG/Qgn75vXEPkKyXHjg=; b=g+APBZuxZRwi1ofTLbHkZOlnsaTylIxE6nL5L7tvKGHvrRtb0uFtSacWlCD04Yg6GX vhIcCYTVnGz/Q4MIVCptctRjvd6IRHRj/VZcDKEsF6WOeq1d0OR9rVjP6SBh+muVQQ03 VPYV67Hh5U2CGtrCxr7xawIwnLnK6NU7QjPL8wQXIf/pQofd/ufej1JUdpHIKgUeMafO DHKTyeUvxquCIUcwbgu6pz6ONM4JOLrZ8k97wzASdnorCnnneMxBuBAlKYWzGjzG4EyO Io4VqDlDnLhu6Hny/79u4kgbzzDnULMnXgHyM3sVlh0iLHgm1X0cmlE1hSRk2DaDm9Ps hsLw== X-Gm-Message-State: AC+VfDwlC7xq3p74Ld7IGJYdZh3B2LnKXVB8nuL4Fz3K9kh/B0YsB6gK 22b2Hpes3vhGGbrmuwe9AuSZkt4SQ4NNvw== X-Google-Smtp-Source: ACHHUZ596UsvMGmbLYLInDifOvQLMBlnrEgw5hp/Zpu0ixdxXvxADORdA/nRGnguxYM8oG0GUrcxvA== X-Received: by 2002:a17:903:190:b0:1ab:397:9748 with SMTP id z16-20020a170903019000b001ab03979748mr6864977plg.21.1683248679405; Thu, 04 May 2023 18:04:39 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, LIU Zhiwei , Weiwei Li , Alistair Francis , Richard Henderson Subject: [PULL 24/89] target/riscv: Convert env->virt to a bool env->virt_enabled Date: Fri, 5 May 2023 11:01:36 +1000 Message-Id: <20230505010241.21812-25-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=alistair23@gmail.com; helo=mail-pg1-x532.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248979053100003 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei Currently we only use the env->virt to encode the virtual mode enabled status. Let's make it a bool type. Signed-off-by: LIU Zhiwei Reviewed-by: Weiwei Li Message-ID: <20230325145348.1208-1-zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-Id: <20230327080858.39703-6-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/cpu_bits.h | 3 --- target/riscv/cpu_helper.c | 6 +++--- target/riscv/machine.c | 6 +++--- target/riscv/translate.c | 4 ++-- 5 files changed, 9 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5f38b0adc0..ff6b3c6720 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -185,7 +185,7 @@ struct CPUArchState { #ifndef CONFIG_USER_ONLY target_ulong priv; /* This contains QEMU specific information about the virt state. */ - target_ulong virt; + bool virt_enabled; target_ulong geilen; uint64_t resetvec; =20 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index a92313a06f..190e517862 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -611,9 +611,6 @@ typedef enum { #define PRV_H 2 /* Reserved */ #define PRV_M 3 =20 -/* Virtulisation Register Fields */ -#define VIRT_ONOFF 1 - /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 #define SATP32_ASID 0x7fc00000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b286118a6b..c7bc3fc553 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -560,18 +560,18 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_= ulong geilen) =20 bool riscv_cpu_virt_enabled(CPURISCVState *env) { - return get_field(env->virt, VIRT_ONOFF); + return env->virt_enabled; } =20 /* This function can only be called to set virt when RVH is enabled */ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) { /* Flush the TLB on all virt mode changes. */ - if (get_field(env->virt, VIRT_ONOFF) !=3D enable) { + if (env->virt_enabled !=3D enable) { tlb_flush(env_cpu(env)); } =20 - env->virt =3D set_field(env->virt, VIRT_ONOFF, enable); + env->virt_enabled =3D enable; =20 if (enable) { /* diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 27f430ad74..8869346089 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -349,8 +349,8 @@ static const VMStateDescription vmstate_jvt =3D { =20 const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", - .version_id =3D 7, - .minimum_version_id =3D 7, + .version_id =3D 8, + .minimum_version_id =3D 8, .post_load =3D riscv_cpu_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), @@ -370,7 +370,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU), VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), VMSTATE_UINTTL(env.priv, RISCVCPU), - VMSTATE_UINTTL(env.virt, RISCVCPU), + VMSTATE_BOOL(env.virt_enabled, RISCVCPU), VMSTATE_UINT64(env.resetvec, RISCVCPU), VMSTATE_UINTTL(env.mhartid, RISCVCPU), VMSTATE_UINT64(env.mstatus, RISCVCPU), diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6872d17fb9..5dddac44bc 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1266,8 +1266,8 @@ static void riscv_tr_disas_log(const DisasContextBase= *dcbase, =20 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 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Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-Id: <20230327080858.39703-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c7bc3fc553..9e2be29c45 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1051,7 +1051,7 @@ restart: if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { *prot |=3D PAGE_READ; } - if ((pte & PTE_X)) { + if (pte & PTE_X) { *prot |=3D PAGE_EXEC; } /* add write permission on stores or if the page is already di= rty, --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248746; cv=none; d=zohomail.com; s=zohoarc; b=Wq+qQ8Uua3mB+uamBBZl6bHMmRUZtiMVtHvRUB89hSwVUWcGR2HfaJUdEPI6FspT8keGzSPjGfXtLkgCxDFqiGzlwaszsdclYHAsxiDlztXQoj50UDEMY1oGLO7KLp9+cBgWuigUGhf8yGV0bbfGH0Lfahat1/Q6naVcAPBtSng= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248746; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ByUOlk1RB4HTBv9euthcrclHSXtsLV8170svpbksmdk=; b=P2byf0Od3B+zG9rjzYhaA4H13/cbr0AmcUotvXB/mPXPjxhEo5cJpfaA/3ttzwrkUALykYPf4cvU3sL7WatixyhTE+lTGFw76jhOkyapVSLrtMn2YUAwKTIOPqQ9Xvg9XMnnanQjwrDL8uFFS9Li7652emt1u4uga4yQPIfkhX0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683248746148384.9701980097368; Thu, 4 May 2023 18:05:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujsQ-0003Vn-SC; Thu, 04 May 2023 21:04:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujsP-0003IV-JW for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:49 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujsN-00076S-L8 for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:49 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1aad5245571so8028165ad.1 for ; Thu, 04 May 2023 18:04:47 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.04.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:04:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248686; x=1685840686; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ByUOlk1RB4HTBv9euthcrclHSXtsLV8170svpbksmdk=; b=Xg84NQPP1qUkTklL10h9QNXHgC2GqrLoIG4IAGhmnd7Ks6b86RlQoM3r7c0gR7mC93 iSPJ9UBGcTDtykb24389FPBjP0rEGgFfV15YBmEkAKBxIYMx6HnZNMOPFvl83FWdyOFe /q6xT8w0DzR4JCOGey9dW3OwISIMkUdRPeQbvYfCXHCN97QJ9et31IEwWsCYDU8rHyBj Fpk7o/yRMZ3JYw6XioxpT9Pmn1MhIBG8F4d9xJSe98+5lFviH1ziTY+dUOjAqk35BDbH BxJKSgBerNZhDN3Y4kV6f3IbTAWfVUhMNtxgnnRGirjAnfj/wkND1yQEyrGubyxBa6zr te9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248686; x=1685840686; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ByUOlk1RB4HTBv9euthcrclHSXtsLV8170svpbksmdk=; b=JLVZ6X/gzhiL2MVu32VyKsz9XryoJrTA8oRqb6txRGY1wOLfC4oNTVHpd+s3mZMVYV ASQridaLVTiWWVbJR8WCP25djanKhasXGRHNep94PZUZOM/1LSpoFdsgfQLsTbEICqYp g/qkbp0zYqwufrZGTvtTf6o15N+GM0eD7SdyD8sbuTwQZGL/5J4haBXI/pkYpPJLyJ+K TVZQsyF1hoQwNfEgHhdIXX2vtl8Uj3cADs+rZX8oD2tzhePeOqODQqu5XV8PYybViZSM sg0VammYGlZd30hDyhWlTXwAqbYk7sRyQIH8Pq2jILY/G4sllhp+u8oAtBeMpy5LKOzU j3Zw== X-Gm-Message-State: AC+VfDx+aCGj64j6C3zle4gIN8GjbfiL7U84i4opxwHgbU9Bt9SseguC C6wFeWSUhkL0bY+0ZBx5l9gPYBMohZ0n7w== X-Google-Smtp-Source: ACHHUZ66L5BFzDRNocpKNqh2Jf/5olN3+9jb6LrXQ9QcwK2LAHPqmFANE24mHXO539MJAR+ByX0A/Q== X-Received: by 2002:a17:902:c948:b0:1a9:6d25:b2d2 with SMTP id i8-20020a170902c94800b001a96d25b2d2mr6195005pla.67.1683248686584; Thu, 04 May 2023 18:04:46 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Alistair Francis , Richard Henderson Subject: [PULL 26/89] target/riscv: Fix addr type for get_physical_address Date: Fri, 5 May 2023 11:01:38 +1000 Message-Id: <20230505010241.21812-27-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=alistair23@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248748095100011 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Function get_physical_address() translates both virtual address and guest physical address, and the latter is 34-bits for Sv32x4. So we should use vaddr type for 'addr' parameter. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-Id: <20230329101928.83856-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9e2be29c45..b0e094a933 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -732,7 +732,7 @@ static int get_physical_address_pmp(CPURISCVState *env,= int *prot, * @env: CPURISCVState * @physical: This will be set to the calculated physical address * @prot: The returned protection attributes - * @addr: The virtual address to be translated + * @addr: The virtual address or guest physical address to be translated * @fault_pte_addr: If not NULL, this will be set to fault pte address * when a error occurs on pte address translation. * This will already be shifted to match htval. @@ -744,7 +744,7 @@ static int get_physical_address_pmp(CPURISCVState *env,= int *prot, * @is_debug: Is this access from a debugger or the monitor? */ static int get_physical_address(CPURISCVState *env, hwaddr *physical, - int *prot, target_ulong addr, + int *prot, vaddr addr, target_ulong *fault_pte_addr, int access_type, int mmu_idx, bool first_stage, bool two_stage, --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249147; cv=none; d=zohomail.com; s=zohoarc; b=OzxaXYV6ook7+BGREmVKKYHx32QTjYPQUhj8h6LTVrm2tdBHBFuS4tclV5gbanMZ0oKzjpMeoqU7ujavg94/kdZyQoy4Z8FoyidD++TGpiDbiwKDBmtNBg84E5mYpuA3IntzqLuCMJUj+XRXd9U337EsUgag099mXFLVqzFjFrQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249147; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UkMty94oAbLIxhqFblM8E1A1z94sOK+vVkAnvNy/KwI=; b=ZxnUvetG3352FkOBxFTC5jUZ+/sbGyZ0RW58coI8hcY9OUaaUr9ta4oDdB0Rh9Pb9pGnY+d4dI0OLe1vl/q2oD0Z5r2dmlBhnGGWzFC2GHe9mav1iavw9pCQJ8fNtJkSwfG9Td8Zv/G7lVDC/JZJz6G8etVGDkj2K/M1H2Ew/Dg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249147147845.3621719330989; Thu, 4 May 2023 18:12:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujsV-0004II-Pp; Thu, 04 May 2023 21:04:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujsT-00042F-LN for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:54 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujsR-00077J-PQ for qemu-devel@nongnu.org; Thu, 04 May 2023 21:04:53 -0400 Received: by mail-pg1-x532.google.com with SMTP id 41be03b00d2f7-51b661097bfso813075a12.0 for ; Thu, 04 May 2023 18:04:51 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.04.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:04:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248690; x=1685840690; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UkMty94oAbLIxhqFblM8E1A1z94sOK+vVkAnvNy/KwI=; b=moR80q+omiN3nkg9EaOAAT3oJTDHftZ4IDOnoEHPLBWdY1VHW3J6QTVuonAMNsyf55 rUr2mfA9Q/xFzhYmgApFJS+wWVg5w6KUwiOsq6bxU3zk5JL/RWgBY93ev+fR+l5xm7EG VE4m1T1gV+X1uEX7jwMgFTZVQiwF9+cD6wrduP//mSTshs4AYBRiz1sv3VYJYhhmvCqc I+D+fVgHeInst9c5WXX+DtGT9/hx4iO4wScnfMCKENPZfOv1KhuffCXsYW94N+ooo4gK vbtq1lXZ8ygO5luP6aTLVzj5p+jnu36aP2LGxkzoU2hbB+TUus3++vepZxcZ/l3zjPy4 rebg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248690; x=1685840690; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UkMty94oAbLIxhqFblM8E1A1z94sOK+vVkAnvNy/KwI=; b=Hnqwd+W5Pm0SxXCHhoNsz1/lG6m96r6ReQVqOTe4pW4EMKf9N6EYx3/+X9Xm99XmdP AnffdLnWHaD4Y2/uStA6evLcFi0hsV8j6djjHv5VCBMk3W436siCVGw7Fdo9tPEjYg4z xf7cIxU3+wrZodINhNY917v5dYDAJJE7Bfwrtmgnz7X+xQFmaBDePgKkKgQrZOElqxUn wXBCPAwE0bfkYoinLFEWIkyOvdfJZx4e8aORwQegeJw2Xm7MES5yh5Yrn2O5Aq28Whho xViAc+31R2SHzBC+1xSe9nwSnMiZxRAU6wH2zRR3SiGOlA6gkEPTsmAqeFhBtxN4K/hS 8cJA== X-Gm-Message-State: AC+VfDz6e6Gfk849NTi4klS4949tygaskK12BFBBZ+KW6US1/gRlXK/Q 05kHvya0wkOJMLzkSzQzI+JeunEDFI0DwA== X-Google-Smtp-Source: ACHHUZ6fNO2K08hRTTZ7euXj4VRjNxPv+fTj0O2CF4cSd82SJH2zq3wDwHjso5l07Q7FZP9YsHbNng== X-Received: by 2002:a17:902:7048:b0:1ab:1bdd:b307 with SMTP id h8-20020a170902704800b001ab1bddb307mr4896710plt.51.1683248689898; Thu, 04 May 2023 18:04:49 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 27/89] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault Date: Fri, 5 May 2023 11:01:39 +1000 Message-Id: <20230505010241.21812-28-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=alistair23@gmail.com; helo=mail-pg1-x532.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249147600100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li decode_save_opc() will not work for generate_exception(), since 0 is passed to riscv_raise_exception() as pc in helper_raise_exception(), and bins will not be restored in this case. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-Id: <20230330034636.44585-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvh.c.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index 9248b48c36..4b730cd492 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -20,6 +20,8 @@ static bool check_access(DisasContext *ctx) { if (!ctx->hlsx) { + tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, + offsetof(CPURISCVState, bins)); if (ctx->virt_enabled) { generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); } else { --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248749; cv=none; d=zohomail.com; s=zohoarc; b=g19TcY6MycXofW69iDTAd7Ie4dd/FFUP47p32Ui/z9IQrd+Vm/UYWtZ+OYBoEpvpHYFExsGL8JDEaw8Zf39BIubDNmW2Hx8Olybbvc/aBboCepCvVjbE9BfNR2iHSLNw8RoRwlbvNTzTm6t+57g6VzbYz7f6WCqJONzoQS4u5mI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248749; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=COPdmPGTsakgWsYch7yYN18znxXDMdJHEbnCGEjq5WM=; b=PN8L0WhzsAMeJzcKIRsXxWX6WQPXfCjlq9iwqKE+ssVIKc1sIUg6Yu8ZnUOVay7zz8MmXTtEnXigtG9OhxjpgJa9k4N7S4lherf9t6y2pkBpfca0iehA8/qmHu005uurqWeHhjZNy9xZcBcHP5WBd5ALcySGeGPczHa0tKKchDo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683248749612811.8380237245284; Thu, 4 May 2023 18:05:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujsd-0005Jr-6X; Thu, 04 May 2023 21:05:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujsb-0005A0-BS for qemu-devel@nongnu.org; Thu, 04 May 2023 21:05:01 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujsV-00077q-QI for qemu-devel@nongnu.org; Thu, 04 May 2023 21:05:00 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1ab01bf474aso8555865ad.1 for ; Thu, 04 May 2023 18:04:55 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.04.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:04:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248694; x=1685840694; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=COPdmPGTsakgWsYch7yYN18znxXDMdJHEbnCGEjq5WM=; b=EDLh3MVMLIy/CmCzuNitFyNaIw+S6PiBS95vmM+wXmFw08qsWANhlxgIjEsKHN+NYt pTq4vN9O3qdSiydVYax+O/d2dJWR13kqjFdmXOrCLM06CohriWhfhRtjzACg7Odc1+d1 eooUQJ982JxPyKCTLY3/VNZ4k6ZGWsKG3Zf0xFc2mMaQcKlY3CCp3DKeGHT6FMyelwn6 exxoYQC9OFANcnOlWj7btI/WRylTX2ZXOa7t/E+LHgjJ+ArL0Oks5F4PCvZb7eDwB5wu tvlRHSCaJUwfRJD11QA2dRwxU77Yg/RH2G7+G5elCK4hRNR5EnlB8zNpQgNtJJ+ayct+ JeqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248694; x=1685840694; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=COPdmPGTsakgWsYch7yYN18znxXDMdJHEbnCGEjq5WM=; b=A8xrVBO+94FQD715o20i5O9c0/qD6xVqx/tObMN+/ZMYcetZn0TFZEtsewvTD230Iy yZXgDG2N6qH5KoXrLr9o4x4iv4VdQHWBZDG1b0+Sn5GczXnlpR0rbQa4rulaU653DfqC aSgrEIkt/RFd77S7bWfSln1F6Xt535SVsGKQUAYTdKv/WZRYxGGR16hn1lZy32gPAZ0t CuHiGXqA0ymYLbHepnS2AIchCDYph4FruYvFtQCvFd/zKL15wSKYD9RsXQHKg5XsKAok SpjCGCRTy3jmkMWj+XUUrT1eLkJ4iS8OvXc7HywLa+qOxNtl7ujuYPQkqoyZI7KGp+rd ULDw== X-Gm-Message-State: AC+VfDzsyXkqDAzvlRKkArdggUI3nEoUF8XuUJHkAxdKGW+1k8I8BIZp vSum1uurr/7IFD6Jjb8+lff7hXcxNVnmBQ== X-Google-Smtp-Source: ACHHUZ7mSteBsfPL9fhhQiR7cBOmVnTe8ed3bPiaoUlTDKuY0vE50YH59vklGukUhTiK0jScKqmV/w== X-Received: by 2002:a17:902:8b83:b0:1a1:bfe8:4fae with SMTP id ay3-20020a1709028b8300b001a1bfe84faemr5646716plb.43.1683248693817; Thu, 04 May 2023 18:04:53 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , LIU Zhiwei , Junqiang Wang , Richard Henderson , Alistair Francis , Daniel Henrique Barboza Subject: [PULL 28/89] target/riscv: Remove riscv_cpu_virt_enabled() Date: Fri, 5 May 2023 11:01:40 +1000 Message-Id: <20230505010241.21812-29-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248750123100017 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Directly use env->virt_enabled instead. Suggested-by: LIU Zhiwei Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-Id: <20230405085813.40643-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 51 ++++++++++++++++++--------------------- target/riscv/csr.c | 46 +++++++++++++++++------------------ target/riscv/debug.c | 10 ++++---- target/riscv/op_helper.c | 18 +++++++------- target/riscv/pmu.c | 4 +-- target/riscv/translate.c | 2 +- 8 files changed, 64 insertions(+), 70 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ff6b3c6720..995192757a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -585,7 +585,6 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env); target_ulong riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); -bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cd9e7bdce6..c304deabd7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -556,7 +556,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,= int flags) =20 #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s %d\n", "V =3D ", riscv_cpu_virt_enabled= (env)); + qemu_fprintf(f, " %s %d\n", "V =3D ", env->virt_enabled); } #endif qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b0e094a933..fbcdec3c06 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -93,8 +93,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulon= g *pc, =20 if (riscv_has_ext(env, RVH)) { if (env->priv =3D=3D PRV_M || - (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && + (env->priv =3D=3D PRV_S && !env->virt_enabled) || + (env->priv =3D=3D PRV_U && !env->virt_enabled && get_field(env->hstatus, HSTATUS_HU))) { flags =3D FIELD_DP32(flags, TB_FLAGS, HLSX, 1); } @@ -391,7 +391,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *e= nv) uint64_t irqs, pending, mie, hsie, vsie; =20 /* Determine interrupt enable state of all privilege modes */ - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { mie =3D 1; hsie =3D 1; vsie =3D (env->priv < PRV_S) || @@ -452,7 +452,7 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) bool riscv_cpu_fp_enabled(CPURISCVState *env) { if (env->mstatus & MSTATUS_FS) { - if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)= ) { + if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) { return false; } return true; @@ -465,7 +465,7 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) bool riscv_cpu_vector_enabled(CPURISCVState *env) { if (env->mstatus & MSTATUS_VS) { - if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)= ) { + if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) { return false; } return true; @@ -483,7 +483,7 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) if (riscv_has_ext(env, RVF)) { mstatus_mask |=3D MSTATUS_FS; } - bool current_virt =3D riscv_cpu_virt_enabled(env); + bool current_virt =3D env->virt_enabled; =20 g_assert(riscv_has_ext(env, RVH)); =20 @@ -558,11 +558,6 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_u= long geilen) env->geilen =3D geilen; } =20 -bool riscv_cpu_virt_enabled(CPURISCVState *env) -{ - return env->virt_enabled; -} - /* This function can only be called to set virt when RVH is enabled */ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) { @@ -609,7 +604,7 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint6= 4_t mask, CPUState *cs =3D env_cpu(env); uint64_t gein, vsgein =3D 0, vstip =3D 0, old =3D env->mip; =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { gein =3D get_field(env->hstatus, HSTATUS_VGEIN); vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; } @@ -768,7 +763,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, * was called. Background registers will be used if the guest has * forced a two stage translation to be on (in HS or M mode). */ - if (!riscv_cpu_virt_enabled(env) && two_stage) { + if (!env->virt_enabled && two_stage) { use_background =3D true; } =20 @@ -931,7 +926,7 @@ restart: bool pbmte =3D env->menvcfg & MENVCFG_PBMTE; bool hade =3D env->menvcfg & MENVCFG_HADE; =20 - if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) { + if (first_stage && two_stage && env->virt_enabled) { pbmte =3D pbmte && (env->henvcfg & HENVCFG_PBMTE); hade =3D hade && (env->henvcfg & HENVCFG_HADE); } @@ -1091,7 +1086,7 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, =20 switch (access_type) { case MMU_INST_FETCH: - if (riscv_cpu_virt_enabled(env) && !first_stage) { + if (env->virt_enabled && !first_stage) { cs->exception_index =3D RISCV_EXCP_INST_GUEST_PAGE_FAULT; } else { cs->exception_index =3D page_fault_exceptions ? @@ -1131,11 +1126,11 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, = vaddr addr) int mmu_idx =3D cpu_mmu_index(&cpu->env, false); =20 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_id= x, - true, riscv_cpu_virt_enabled(env), true)) { + true, env->virt_enabled, true)) { return -1; } =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 0, mmu_idx, false, true, true)) { return -1; @@ -1163,7 +1158,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hw= addr physaddr, } =20 env->badaddr =3D addr; - env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || + env->two_stage_lookup =3D env->virt_enabled || riscv_cpu_two_stage_lookup(mmu_idx); env->two_stage_indirect_lookup =3D false; cpu_loop_exit_restore(cs, retaddr); @@ -1189,7 +1184,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, g_assert_not_reached(); } env->badaddr =3D addr; - env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || + env->two_stage_lookup =3D env->virt_enabled || riscv_cpu_two_stage_lookup(mmu_idx); env->two_stage_indirect_lookup =3D false; cpu_loop_exit_restore(cs, retaddr); @@ -1253,7 +1248,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, } =20 pmu_tlb_fill_incr_ctr(cpu, access_type); - if (riscv_cpu_virt_enabled(env) || + if (env->virt_enabled || ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && access_type !=3D MMU_INST_FETCH)) { /* Two stage lookup */ @@ -1351,7 +1346,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, } else { raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error, - riscv_cpu_virt_enabled(env) || + env->virt_enabled || riscv_cpu_two_stage_lookup(mmu_idx), two_stage_indirect_error); cpu_loop_exit_restore(cs, retaddr); @@ -1658,9 +1653,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) =20 if (env->priv =3D=3D PRV_M) { cause =3D RISCV_EXCP_M_ECALL; - } else if (env->priv =3D=3D PRV_S && riscv_cpu_virt_enabled(en= v)) { + } else if (env->priv =3D=3D PRV_S && env->virt_enabled) { cause =3D RISCV_EXCP_VS_ECALL; - } else if (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(e= nv)) { + } else if (env->priv =3D=3D PRV_S && !env->virt_enabled) { cause =3D RISCV_EXCP_S_ECALL; } else if (env->priv =3D=3D PRV_U) { cause =3D RISCV_EXCP_U_ECALL; @@ -1683,7 +1678,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_has_ext(env, RVH)) { uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; =20 - if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { + if (env->virt_enabled && ((hdeleg >> cause) & 1)) { /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode inte= rrupt @@ -1694,7 +1689,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) cause =3D cause - 1; } write_gva =3D false; - } else if (riscv_cpu_virt_enabled(env)) { + } else if (env->virt_enabled) { /* Trap into HS mode, from virt */ riscv_cpu_swap_hypervisor_regs(env); env->hstatus =3D set_field(env->hstatus, HSTATUS_SPVP, @@ -1728,12 +1723,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) } else { /* handle the trap in M-mode */ if (riscv_has_ext(env, RVH)) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { riscv_cpu_swap_hypervisor_regs(env); } env->mstatus =3D set_field(env->mstatus, MSTATUS_MPV, - riscv_cpu_virt_enabled(env)); - if (riscv_cpu_virt_enabled(env) && tval) { + env->virt_enabled); + if (env->virt_enabled && tval) { env->mstatus =3D set_field(env->mstatus, MSTATUS_GVA, 1); } =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 777d7fbac0..41e56012d5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -45,7 +45,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *o= ps) #if !defined(CONFIG_USER_ONLY) RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bi= t) { - bool virt =3D riscv_cpu_virt_enabled(env); + bool virt =3D env->virt_enabled; =20 if (env->priv =3D=3D PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) { return RISCV_EXCP_NONE; @@ -135,7 +135,7 @@ skip_ext_pmu_check: return RISCV_EXCP_ILLEGAL_INST; } =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (!get_field(env->hcounteren, ctr_mask) || (env->priv =3D=3D PRV_U && !get_field(env->scounteren, ctr_mas= k))) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; @@ -365,7 +365,7 @@ static RISCVException hstateenh(CPURISCVState *env, int= csrno) =20 static RISCVException sstateen(CPURISCVState *env, int csrno) { - bool virt =3D riscv_cpu_virt_enabled(env); + bool virt =3D env->virt_enabled; int index =3D csrno - CSR_SSTATEEN0; =20 if (!riscv_cpu_cfg(env)->ext_smstateen) { @@ -430,7 +430,7 @@ static RISCVException sstc(CPURISCVState *env, int csrn= o) return RISCV_EXCP_ILLEGAL_INST; } =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (!(get_field(env->hcounteren, COUNTEREN_TM) && get_field(env->henvcfg, HENVCFG_STCE))) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; @@ -536,7 +536,7 @@ static RISCVException seed(CPURISCVState *env, int csrn= o) */ if (env->priv =3D=3D PRV_M) { return RISCV_EXCP_NONE; - } else if (riscv_cpu_virt_enabled(env)) { + } else if (env->virt_enabled) { if (env->mseccfg & MSECCFG_SSEED) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } else { @@ -964,7 +964,7 @@ static int read_scountovf(CPURISCVState *env, int csrno= , target_ulong *val) static RISCVException read_time(CPURISCVState *env, int csrno, target_ulong *val) { - uint64_t delta =3D riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; + uint64_t delta =3D env->virt_enabled ? env->htimedelta : 0; =20 if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; @@ -977,7 +977,7 @@ static RISCVException read_time(CPURISCVState *env, int= csrno, static RISCVException read_timeh(CPURISCVState *env, int csrno, target_ulong *val) { - uint64_t delta =3D riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; + uint64_t delta =3D env->virt_enabled ? env->htimedelta : 0; =20 if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; @@ -1031,7 +1031,7 @@ static RISCVException write_vstimecmph(CPURISCVState = *env, int csrno, static RISCVException read_stimecmp(CPURISCVState *env, int csrno, target_ulong *val) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { *val =3D env->vstimecmp; } else { *val =3D env->stimecmp; @@ -1043,7 +1043,7 @@ static RISCVException read_stimecmp(CPURISCVState *en= v, int csrno, static RISCVException read_stimecmph(CPURISCVState *env, int csrno, target_ulong *val) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { *val =3D env->vstimecmp >> 32; } else { *val =3D env->stimecmp >> 32; @@ -1055,7 +1055,7 @@ static RISCVException read_stimecmph(CPURISCVState *e= nv, int csrno, static RISCVException write_stimecmp(CPURISCVState *env, int csrno, target_ulong val) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } @@ -1076,7 +1076,7 @@ static RISCVException write_stimecmp(CPURISCVState *e= nv, int csrno, static RISCVException write_stimecmph(CPURISCVState *env, int csrno, target_ulong val) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } @@ -1530,7 +1530,7 @@ static int read_mtopi(CPURISCVState *env, int csrno, = target_ulong *val) =20 static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno) { - if (!riscv_cpu_virt_enabled(env)) { + if (!env->virt_enabled) { return csrno; } =20 @@ -1687,7 +1687,7 @@ static int rmw_xireg(CPURISCVState *env, int csrno, t= arget_ulong *val, =20 done: if (ret) { - return (riscv_cpu_virt_enabled(env) && virt) ? + return (env->virt_enabled && virt) ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; } return RISCV_EXCP_NONE; @@ -1741,7 +1741,7 @@ static int rmw_xtopei(CPURISCVState *env, int csrno, = target_ulong *val, =20 done: if (ret) { - return (riscv_cpu_virt_enabled(env) && virt) ? + return (env->virt_enabled && virt) ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; } return RISCV_EXCP_NONE; @@ -2171,7 +2171,7 @@ static RISCVException write_hstateenh_1_3(CPURISCVSta= te *env, int csrno, static RISCVException read_sstateen(CPURISCVState *env, int csrno, target_ulong *val) { - bool virt =3D riscv_cpu_virt_enabled(env); + bool virt =3D env->virt_enabled; int index =3D csrno - CSR_SSTATEEN0; =20 *val =3D env->sstateen[index] & env->mstateen[index]; @@ -2185,7 +2185,7 @@ static RISCVException read_sstateen(CPURISCVState *en= v, int csrno, static RISCVException write_sstateen(CPURISCVState *env, int csrno, uint64_t mask, target_ulong new_val) { - bool virt =3D riscv_cpu_virt_enabled(env); + bool virt =3D env->virt_enabled; int index =3D csrno - CSR_SSTATEEN0; uint64_t wr_mask; uint64_t *reg; @@ -2380,7 +2380,7 @@ static RISCVException rmw_sie64(CPURISCVState *env, i= nt csrno, RISCVException ret; uint64_t mask =3D env->mideleg & S_MODE_INTERRUPTS; =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } @@ -2590,7 +2590,7 @@ static RISCVException rmw_sip64(CPURISCVState *env, i= nt csrno, RISCVException ret; uint64_t mask =3D env->mideleg & sip_writable_mask; =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } @@ -2783,7 +2783,7 @@ static int read_stopi(CPURISCVState *env, int csrno, = target_ulong *val) int irq; uint8_t iprio; =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { return read_vstopi(env, CSR_VSTOPI, val); } =20 @@ -3128,7 +3128,7 @@ static int read_hvipriox(CPURISCVState *env, int firs= t_index, =20 /* First index has to be a multiple of number of irqs per register */ if (first_index % num_irqs) { - return (riscv_cpu_virt_enabled(env)) ? + return (env->virt_enabled) ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; } =20 @@ -3154,7 +3154,7 @@ static int write_hvipriox(CPURISCVState *env, int fir= st_index, =20 /* First index has to be a multiple of number of irqs per register */ if (first_index % num_irqs) { - return (riscv_cpu_virt_enabled(env)) ? + return (env->virt_enabled) ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; } =20 @@ -3809,7 +3809,7 @@ static inline RISCVException riscv_csrrw_check(CPURIS= CVState *env, int csr_priv, effective_priv =3D env->priv; =20 if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_S && - !riscv_cpu_virt_enabled(env)) { + !env->virt_enabled) { /* * We are in HS mode. Add 1 to the effective privledge level to * allow us to access the Hypervisor CSRs. @@ -3819,7 +3819,7 @@ static inline RISCVException riscv_csrrw_check(CPURIS= CVState *env, =20 csr_priv =3D get_field(csrno, 0x300); if (!env->debugger && (effective_priv < csr_priv)) { - if (csr_priv =3D=3D (PRV_S + 1) && riscv_cpu_virt_enabled(env)) { + if (csr_priv =3D=3D (PRV_S + 1) && env->virt_enabled) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } return RISCV_EXCP_ILLEGAL_INST; diff --git a/target/riscv/debug.c b/target/riscv/debug.c index b091293069..1f7aed23c9 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -515,7 +515,7 @@ itrigger_set_count(CPURISCVState *env, int index, int v= alue) static bool check_itrigger_priv(CPURISCVState *env, int index) { target_ulong tdata1 =3D env->tdata1[index]; - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { /* check VU/VS bit against current privilege level */ return (get_field(tdata1, ITRIGGER_VS) =3D=3D env->priv) || (get_field(tdata1, ITRIGGER_VU) =3D=3D env->priv); @@ -787,7 +787,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) switch (trigger_type) { case TRIGGER_TYPE_AD_MATCH: /* type 2 trigger cannot be fired in VU/VS mode */ - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { return false; } =20 @@ -806,7 +806,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) pc =3D env->tdata2[i]; =20 if ((ctrl & TYPE6_EXEC) && (bp->pc =3D=3D pc)) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { /* check VU/VS bit against current privilege level= */ if ((ctrl >> 23) & BIT(env->priv)) { return true; @@ -845,7 +845,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPU= Watchpoint *wp) switch (trigger_type) { case TRIGGER_TYPE_AD_MATCH: /* type 2 trigger cannot be fired in VU/VS mode */ - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { return false; } =20 @@ -880,7 +880,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPU= Watchpoint *wp) } =20 if ((wp->flags & flags) && (wp->vaddr =3D=3D addr)) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { /* check VU/VS bit against current privilege level */ if ((ctrl >> 23) & BIT(env->priv)) { return true; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 1eecae9547..c0c4ced7f0 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -140,7 +140,7 @@ static void check_zicbo_envcfg(CPURISCVState *env, targ= et_ulong envbits, riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } =20 - if (riscv_cpu_virt_enabled(env) && + if (env->virt_enabled && (((env->priv < PRV_H) && !get_field(env->henvcfg, envbits)) || ((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)))) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra); @@ -278,7 +278,7 @@ target_ulong helper_sret(CPURISCVState *env) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } =20 - if (riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_VTS= R)) { + if (env->virt_enabled && get_field(env->hstatus, HSTATUS_VTSR)) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } =20 @@ -293,7 +293,7 @@ target_ulong helper_sret(CPURISCVState *env) } env->mstatus =3D mstatus; =20 - if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { + if (riscv_has_ext(env, RVH) && !env->virt_enabled) { /* We support Hypervisor extensions and virtulisation is disabled = */ target_ulong hstatus =3D env->hstatus; =20 @@ -365,9 +365,9 @@ void helper_wfi(CPURISCVState *env) bool prv_s =3D env->priv =3D=3D PRV_S; =20 if (((prv_s || (!rvs && prv_u)) && get_field(env->mstatus, MSTATUS_TW)= ) || - (rvs && prv_u && !riscv_cpu_virt_enabled(env))) { + (rvs && prv_u && !env->virt_enabled)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } else if (riscv_cpu_virt_enabled(env) && (prv_u || + } else if (env->virt_enabled && (prv_u || (prv_s && get_field(env->hstatus, HSTATUS_VTW)))) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } else { @@ -384,7 +384,7 @@ void helper_tlb_flush(CPURISCVState *env) (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM))) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } else if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) && + } else if (riscv_has_ext(env, RVH) && env->virt_enabled && get_field(env->hstatus, HSTATUS_VTVM)) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } else { @@ -402,12 +402,12 @@ void helper_hyp_tlb_flush(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); =20 - if (env->priv =3D=3D PRV_S && riscv_cpu_virt_enabled(env)) { + if (env->priv =3D=3D PRV_S && env->virt_enabled) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } =20 if (env->priv =3D=3D PRV_M || - (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env))) { + (env->priv =3D=3D PRV_S && !env->virt_enabled)) { tlb_flush(cs); return; } @@ -417,7 +417,7 @@ void helper_hyp_tlb_flush(CPURISCVState *env) =20 void helper_hyp_gvma_tlb_flush(CPURISCVState *env) { - if (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env) && + if (env->priv =3D=3D PRV_S && !env->virt_enabled && get_field(env->mstatus, MSTATUS_TVM)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 96ce2dbe49..48ad60be2b 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -109,7 +109,7 @@ static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint3= 2_t ctr_idx) CPURISCVState *env =3D &cpu->env; target_ulong max_val =3D UINT32_MAX; PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; - bool virt_on =3D riscv_cpu_virt_enabled(env); + bool virt_on =3D env->virt_enabled; =20 /* Privilege mode filtering */ if ((env->priv =3D=3D PRV_M && @@ -150,7 +150,7 @@ static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint3= 2_t ctr_idx) CPURISCVState *env =3D &cpu->env; PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; uint64_t max_val =3D UINT64_MAX; - bool virt_on =3D riscv_cpu_virt_enabled(env); + bool virt_on =3D env->virt_enabled; =20 /* Privilege mode filtering */ if ((env->priv =3D=3D PRV_M && diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5dddac44bc..03748f72e6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1169,7 +1169,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->priv_ver =3D env->priv_ver; #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVH)) { - ctx->virt_enabled =3D riscv_cpu_virt_enabled(env); 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Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-Id: <20230405085813.40643-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/pmp.h | 9 +- target/riscv/arch_dump.c | 4 +- target/riscv/cpu.c | 40 +++--- target/riscv/cpu_helper.c | 163 ++++++++++++------------ target/riscv/fpu_helper.c | 24 ++-- target/riscv/m128_helper.c | 16 +-- target/riscv/machine.c | 18 +-- target/riscv/op_helper.c | 4 +- target/riscv/pmp.c | 19 +-- target/riscv/translate.c | 4 +- target/riscv/vector_helper.c | 159 +++++++++++------------ target/riscv/insn_trans/trans_rvv.c.inc | 28 ++-- 12 files changed, 247 insertions(+), 241 deletions(-) diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index da32c61c85..b296ea1fc6 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -63,18 +63,19 @@ typedef struct { } pmp_table_t; =20 void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, - target_ulong val); + target_ulong val); target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index); =20 void mseccfg_csr_write(CPURISCVState *env, target_ulong val); target_ulong mseccfg_csr_read(CPURISCVState *env); =20 void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, - target_ulong val); + target_ulong val); target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index); int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, - target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs, - target_ulong mode); + target_ulong size, pmp_priv_t privs, + pmp_priv_t *allowed_privs, + target_ulong mode); target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index, target_ulong tlb_sa, target_ulong tlb_ea); void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index); diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c index 736a232956..573587810e 100644 --- a/target/riscv/arch_dump.c +++ b/target/riscv/arch_dump.c @@ -180,8 +180,8 @@ int cpu_get_dump_info(ArchDumpInfo *info, info->d_class =3D ELFCLASS32; #endif =20 - info->d_endian =3D (env->mstatus & MSTATUS_UBE) !=3D 0 - ? ELFDATA2MSB : ELFDATA2LSB; + info->d_endian =3D (env->mstatus & MSTATUS_UBE) !=3D 0 ? + ELFDATA2MSB : ELFDATA2LSB; =20 return 0; } diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c304deabd7..8ed8601399 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -54,7 +54,7 @@ struct isa_ext_data { }; =20 #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ -{#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} + {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} =20 /** * Here are the ordering rules of extension naming defined by RISC-V @@ -157,29 +157,29 @@ static void isa_ext_update_enabled(RISCVCPU *cpu, } =20 const char * const riscv_int_regnames[] =3D { - "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", - "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", - "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", - "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", - "x28/t3", "x29/t4", "x30/t5", "x31/t6" + "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", + "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", + "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", + "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11= ", + "x28/t3", "x29/t4", "x30/t5", "x31/t6" }; =20 const char * const riscv_int_regnamesh[] =3D { - "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", - "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h= ", - "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h= ", - "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h= ", - "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h= ", - "x30h/t5h", "x31h/t6h" + "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0= h", + "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a= 1h", + "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a= 7h", + "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s= 7h", + "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t= 4h", + "x30h/t5h", "x31h/t6h" }; =20 const char * const riscv_fpr_regnames[] =3D { - "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", - "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", - "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", - "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", - "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", - "f30/ft10", "f31/ft11" + "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", + "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", + "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", + "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", + "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", + "f30/ft10", "f31/ft11" }; =20 static const char * const riscv_excp_names[] =3D { @@ -351,8 +351,8 @@ static void riscv_any_cpu_init(Object *obj) =20 #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), - riscv_cpu_mxl(&RISCV_CPU(obj)->env) =3D=3D MXL_RV32 ? - VM_1_10_SV32 : VM_1_10_SV57); + riscv_cpu_mxl(&RISCV_CPU(obj)->env) =3D=3D MXL_RV32 ? + VM_1_10_SV32 : VM_1_10_SV57); #endif =20 set_priv_version(env, PRIV_VERSION_1_12_0); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index fbcdec3c06..8d2547a164 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -68,12 +68,12 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ul= ong *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, sew); flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, - FIELD_EX64(env->vtype, VTYPE, VLMUL)); + FIELD_EX64(env->vtype, VTYPE, VLMUL)); flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); flags =3D FIELD_DP32(flags, TB_FLAGS, VTA, - FIELD_EX64(env->vtype, VTYPE, VTA)); + FIELD_EX64(env->vtype, VTYPE, VTA)); flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, - FIELD_EX64(env->vtype, VTYPE, VMA)); + FIELD_EX64(env->vtype, VTYPE, VMA)); } else { flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); } @@ -95,7 +95,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulon= g *pc, if (env->priv =3D=3D PRV_M || (env->priv =3D=3D PRV_S && !env->virt_enabled) || (env->priv =3D=3D PRV_U && !env->virt_enabled && - get_field(env->hstatus, HSTATUS_HU))) { + get_field(env->hstatus, HSTATUS_HU))) { flags =3D FIELD_DP32(flags, TB_FLAGS, HLSX, 1); } =20 @@ -230,75 +230,75 @@ int riscv_cpu_hviprio_index2irq(int index, int *out_i= rq, int *out_rdzero) * ---------------------------------------------------------------- */ static const uint8_t default_iprio[64] =3D { - /* Custom interrupts 48 to 63 */ - [63] =3D IPRIO_MMAXIPRIO, - [62] =3D IPRIO_MMAXIPRIO, - [61] =3D IPRIO_MMAXIPRIO, - [60] =3D IPRIO_MMAXIPRIO, - [59] =3D IPRIO_MMAXIPRIO, - [58] =3D IPRIO_MMAXIPRIO, - [57] =3D IPRIO_MMAXIPRIO, - [56] =3D IPRIO_MMAXIPRIO, - [55] =3D IPRIO_MMAXIPRIO, - [54] =3D IPRIO_MMAXIPRIO, - [53] =3D IPRIO_MMAXIPRIO, - [52] =3D IPRIO_MMAXIPRIO, - [51] =3D IPRIO_MMAXIPRIO, - [50] =3D IPRIO_MMAXIPRIO, - [49] =3D IPRIO_MMAXIPRIO, - [48] =3D IPRIO_MMAXIPRIO, - - /* Custom interrupts 24 to 31 */ - [31] =3D IPRIO_MMAXIPRIO, - [30] =3D IPRIO_MMAXIPRIO, - [29] =3D IPRIO_MMAXIPRIO, - [28] =3D IPRIO_MMAXIPRIO, - [27] =3D IPRIO_MMAXIPRIO, - [26] =3D IPRIO_MMAXIPRIO, - [25] =3D IPRIO_MMAXIPRIO, - [24] =3D IPRIO_MMAXIPRIO, - - [47] =3D IPRIO_DEFAULT_UPPER, - [23] =3D IPRIO_DEFAULT_UPPER + 1, - [46] =3D IPRIO_DEFAULT_UPPER + 2, - [45] =3D IPRIO_DEFAULT_UPPER + 3, - [22] =3D IPRIO_DEFAULT_UPPER + 4, - [44] =3D IPRIO_DEFAULT_UPPER + 5, - - [43] =3D IPRIO_DEFAULT_UPPER + 6, - [21] =3D IPRIO_DEFAULT_UPPER + 7, - [42] =3D IPRIO_DEFAULT_UPPER + 8, - [41] =3D IPRIO_DEFAULT_UPPER + 9, - [20] =3D IPRIO_DEFAULT_UPPER + 10, - [40] =3D IPRIO_DEFAULT_UPPER + 11, - - [11] =3D IPRIO_DEFAULT_M, - [3] =3D IPRIO_DEFAULT_M + 1, - [7] =3D IPRIO_DEFAULT_M + 2, - - [9] =3D IPRIO_DEFAULT_S, - [1] =3D IPRIO_DEFAULT_S + 1, - [5] =3D IPRIO_DEFAULT_S + 2, - - [12] =3D IPRIO_DEFAULT_SGEXT, - - [10] =3D IPRIO_DEFAULT_VS, - [2] =3D IPRIO_DEFAULT_VS + 1, - [6] =3D IPRIO_DEFAULT_VS + 2, - - [39] =3D IPRIO_DEFAULT_LOWER, - [19] =3D IPRIO_DEFAULT_LOWER + 1, - [38] =3D IPRIO_DEFAULT_LOWER + 2, - [37] =3D IPRIO_DEFAULT_LOWER + 3, - [18] =3D IPRIO_DEFAULT_LOWER + 4, - [36] =3D IPRIO_DEFAULT_LOWER + 5, - - [35] =3D IPRIO_DEFAULT_LOWER + 6, - [17] =3D IPRIO_DEFAULT_LOWER + 7, - [34] =3D IPRIO_DEFAULT_LOWER + 8, - [33] =3D IPRIO_DEFAULT_LOWER + 9, - [16] =3D IPRIO_DEFAULT_LOWER + 10, - [32] =3D IPRIO_DEFAULT_LOWER + 11, + /* Custom interrupts 48 to 63 */ + [63] =3D IPRIO_MMAXIPRIO, + [62] =3D IPRIO_MMAXIPRIO, + [61] =3D IPRIO_MMAXIPRIO, + [60] =3D IPRIO_MMAXIPRIO, + [59] =3D IPRIO_MMAXIPRIO, + [58] =3D IPRIO_MMAXIPRIO, + [57] =3D IPRIO_MMAXIPRIO, + [56] =3D IPRIO_MMAXIPRIO, + [55] =3D IPRIO_MMAXIPRIO, + [54] =3D IPRIO_MMAXIPRIO, + [53] =3D IPRIO_MMAXIPRIO, + [52] =3D IPRIO_MMAXIPRIO, + [51] =3D IPRIO_MMAXIPRIO, + [50] =3D IPRIO_MMAXIPRIO, + [49] =3D IPRIO_MMAXIPRIO, + [48] =3D IPRIO_MMAXIPRIO, + + /* Custom interrupts 24 to 31 */ + [31] =3D IPRIO_MMAXIPRIO, + [30] =3D IPRIO_MMAXIPRIO, + [29] =3D IPRIO_MMAXIPRIO, + [28] =3D IPRIO_MMAXIPRIO, + [27] =3D IPRIO_MMAXIPRIO, + [26] =3D IPRIO_MMAXIPRIO, + [25] =3D IPRIO_MMAXIPRIO, + [24] =3D IPRIO_MMAXIPRIO, + + [47] =3D IPRIO_DEFAULT_UPPER, + [23] =3D IPRIO_DEFAULT_UPPER + 1, + [46] =3D IPRIO_DEFAULT_UPPER + 2, + [45] =3D IPRIO_DEFAULT_UPPER + 3, + [22] =3D IPRIO_DEFAULT_UPPER + 4, + [44] =3D IPRIO_DEFAULT_UPPER + 5, + + [43] =3D IPRIO_DEFAULT_UPPER + 6, + [21] =3D IPRIO_DEFAULT_UPPER + 7, + [42] =3D IPRIO_DEFAULT_UPPER + 8, + [41] =3D IPRIO_DEFAULT_UPPER + 9, + [20] =3D IPRIO_DEFAULT_UPPER + 10, + [40] =3D IPRIO_DEFAULT_UPPER + 11, + + [11] =3D IPRIO_DEFAULT_M, + [3] =3D IPRIO_DEFAULT_M + 1, + [7] =3D IPRIO_DEFAULT_M + 2, + + [9] =3D IPRIO_DEFAULT_S, + [1] =3D IPRIO_DEFAULT_S + 1, + [5] =3D IPRIO_DEFAULT_S + 2, + + [12] =3D IPRIO_DEFAULT_SGEXT, + + [10] =3D IPRIO_DEFAULT_VS, + [2] =3D IPRIO_DEFAULT_VS + 1, + [6] =3D IPRIO_DEFAULT_VS + 2, + + [39] =3D IPRIO_DEFAULT_LOWER, + [19] =3D IPRIO_DEFAULT_LOWER + 1, + [38] =3D IPRIO_DEFAULT_LOWER + 2, + [37] =3D IPRIO_DEFAULT_LOWER + 3, + [18] =3D IPRIO_DEFAULT_LOWER + 4, + [36] =3D IPRIO_DEFAULT_LOWER + 5, + + [35] =3D IPRIO_DEFAULT_LOWER + 6, + [17] =3D IPRIO_DEFAULT_LOWER + 7, + [34] =3D IPRIO_DEFAULT_LOWER + 8, + [33] =3D IPRIO_DEFAULT_LOWER + 9, + [16] =3D IPRIO_DEFAULT_LOWER + 10, + [32] =3D IPRIO_DEFAULT_LOWER + 11, }; =20 uint8_t riscv_cpu_default_priority(int irq) @@ -1001,8 +1001,8 @@ restart: */ MemoryRegion *mr; hwaddr l =3D sizeof(target_ulong), addr1; - mr =3D address_space_translate(cs->as, pte_addr, - &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); + mr =3D address_space_translate(cs->as, pte_addr, &addr1, &= l, + false, MEMTXATTRS_UNSPECIFIED= ); if (memory_region_is_ram(mr)) { target_ulong *pte_pa =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -1052,7 +1052,7 @@ restart: /* add write permission on stores or if the page is already di= rty, so that we TLB miss on later writes to update the dirty bit= */ if ((pte & PTE_W) && - (access_type =3D=3D MMU_DATA_STORE || (pte & PTE_D))) { + (access_type =3D=3D MMU_DATA_STORE || (pte & PTE_D))) { *prot |=3D PAGE_WRITE; } return TRANSLATE_SUCCESS; @@ -1281,9 +1281,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,= int size, false); =20 qemu_log_mask(CPU_LOG_MMU, - "%s 2nd-stage address=3D%" VADDR_PRIx " ret %d physica= l " - HWADDR_FMT_plx " prot %d\n", - __func__, im_address, ret, pa, prot2); + "%s 2nd-stage address=3D%" VADDR_PRIx + " ret %d physical " + HWADDR_FMT_plx " prot %d\n", + __func__, im_address, ret, pa, prot2); =20 prot &=3D prot2; =20 @@ -1718,7 +1719,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->htval =3D htval; env->htinst =3D tinst; env->pc =3D (env->stvec >> 2 << 2) + - ((async && (env->stvec & 3) =3D=3D 1) ? cause * 4 : 0); + ((async && (env->stvec & 3) =3D=3D 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_S); } else { /* handle the trap in M-mode */ @@ -1749,7 +1750,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mtval2 =3D mtval2; env->mtinst =3D tinst; env->pc =3D (env->mtvec >> 2 << 2) + - ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); + ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_M); } =20 diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 449d236df6..5dd14d8390 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -248,8 +248,8 @@ uint64_t helper_fmin_s(CPURISCVState *env, uint64_t rs1= , uint64_t rs2) float32 frs1 =3D check_nanbox_s(env, rs1); float32 frs2 =3D check_nanbox_s(env, rs2); return nanbox_s(env, env->priv_ver < PRIV_VERSION_1_11_0 ? - float32_minnum(frs1, frs2, &env->fp_status) : - float32_minimum_number(frs1, frs2, &env->fp_status)); + float32_minnum(frs1, frs2, &env->fp_status) : + float32_minimum_number(frs1, frs2, &env->fp_statu= s)); } =20 uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) @@ -257,8 +257,8 @@ uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1= , uint64_t rs2) float32 frs1 =3D check_nanbox_s(env, rs1); float32 frs2 =3D check_nanbox_s(env, rs2); return nanbox_s(env, env->priv_ver < PRIV_VERSION_1_11_0 ? - float32_maxnum(frs1, frs2, &env->fp_status) : - float32_maximum_number(frs1, frs2, &env->fp_status)); + float32_maxnum(frs1, frs2, &env->fp_status) : + float32_maximum_number(frs1, frs2, &env->fp_statu= s)); } =20 uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1) @@ -361,15 +361,15 @@ uint64_t helper_fdiv_d(CPURISCVState *env, uint64_t f= rs1, uint64_t frs2) uint64_t helper_fmin_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) { return env->priv_ver < PRIV_VERSION_1_11_0 ? - float64_minnum(frs1, frs2, &env->fp_status) : - float64_minimum_number(frs1, frs2, &env->fp_status); + float64_minnum(frs1, frs2, &env->fp_status) : + float64_minimum_number(frs1, frs2, &env->fp_status); } =20 uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) { return env->priv_ver < PRIV_VERSION_1_11_0 ? - float64_maxnum(frs1, frs2, &env->fp_status) : - float64_maximum_number(frs1, frs2, &env->fp_status); + float64_maxnum(frs1, frs2, &env->fp_status) : + float64_maximum_number(frs1, frs2, &env->fp_status); } =20 uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1) @@ -481,8 +481,8 @@ uint64_t helper_fmin_h(CPURISCVState *env, uint64_t rs1= , uint64_t rs2) float16 frs1 =3D check_nanbox_h(env, rs1); float16 frs2 =3D check_nanbox_h(env, rs2); return nanbox_h(env, env->priv_ver < PRIV_VERSION_1_11_0 ? - float16_minnum(frs1, frs2, &env->fp_status) : - float16_minimum_number(frs1, frs2, &env->fp_status)); + float16_minnum(frs1, frs2, &env->fp_status) : + float16_minimum_number(frs1, frs2, &env->fp_statu= s)); } =20 uint64_t helper_fmax_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) @@ -490,8 +490,8 @@ uint64_t helper_fmax_h(CPURISCVState *env, uint64_t rs1= , uint64_t rs2) float16 frs1 =3D check_nanbox_h(env, rs1); float16 frs2 =3D check_nanbox_h(env, rs2); return nanbox_h(env, env->priv_ver < PRIV_VERSION_1_11_0 ? - float16_maxnum(frs1, frs2, &env->fp_status) : - float16_maximum_number(frs1, frs2, &env->fp_status)); + float16_maxnum(frs1, frs2, &env->fp_status) : + float16_maximum_number(frs1, frs2, &env->fp_statu= s)); } =20 uint64_t helper_fsqrt_h(CPURISCVState *env, uint64_t rs1) diff --git a/target/riscv/m128_helper.c b/target/riscv/m128_helper.c index 7bf115b85e..e6a4f6120a 100644 --- a/target/riscv/m128_helper.c +++ b/target/riscv/m128_helper.c @@ -24,8 +24,8 @@ #include "exec/helper-proto.h" =20 target_ulong HELPER(divu_i128)(CPURISCVState *env, - target_ulong ul, target_ulong uh, - target_ulong vl, target_ulong vh) + target_ulong ul, target_ulong uh, + target_ulong vl, target_ulong vh) { target_ulong ql, qh; Int128 q; @@ -44,8 +44,8 @@ target_ulong HELPER(divu_i128)(CPURISCVState *env, } =20 target_ulong HELPER(remu_i128)(CPURISCVState *env, - target_ulong ul, target_ulong uh, - target_ulong vl, target_ulong vh) + target_ulong ul, target_ulong uh, + target_ulong vl, target_ulong vh) { target_ulong rl, rh; Int128 r; @@ -64,8 +64,8 @@ target_ulong HELPER(remu_i128)(CPURISCVState *env, } =20 target_ulong HELPER(divs_i128)(CPURISCVState *env, - target_ulong ul, target_ulong uh, - target_ulong vl, target_ulong vh) + target_ulong ul, target_ulong uh, + target_ulong vl, target_ulong vh) { target_ulong qh, ql; Int128 q; @@ -89,8 +89,8 @@ target_ulong HELPER(divs_i128)(CPURISCVState *env, } =20 target_ulong HELPER(rems_i128)(CPURISCVState *env, - target_ulong ul, target_ulong uh, - target_ulong vl, target_ulong vh) + target_ulong ul, target_ulong uh, + target_ulong vl, target_ulong vh) { target_ulong rh, rl; Int128 r; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 8869346089..3ce2970785 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -136,15 +136,15 @@ static const VMStateDescription vmstate_vector =3D { .minimum_version_id =3D 2, .needed =3D vector_needed, .fields =3D (VMStateField[]) { - VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64= ), - VMSTATE_UINTTL(env.vxrm, RISCVCPU), - VMSTATE_UINTTL(env.vxsat, RISCVCPU), - VMSTATE_UINTTL(env.vl, RISCVCPU), - VMSTATE_UINTTL(env.vstart, RISCVCPU), - VMSTATE_UINTTL(env.vtype, RISCVCPU), - VMSTATE_BOOL(env.vill, RISCVCPU), - VMSTATE_END_OF_LIST() - } + VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64), + VMSTATE_UINTTL(env.vxrm, RISCVCPU), + VMSTATE_UINTTL(env.vxsat, RISCVCPU), + VMSTATE_UINTTL(env.vl, RISCVCPU), + VMSTATE_UINTTL(env.vstart, RISCVCPU), + VMSTATE_UINTTL(env.vtype, RISCVCPU), + VMSTATE_BOOL(env.vill, RISCVCPU), + VMSTATE_END_OF_LIST() + } }; =20 static bool pointermasking_needed(void *opaque) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index c0c4ced7f0..ec9a384772 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -367,8 +367,8 @@ void helper_wfi(CPURISCVState *env) if (((prv_s || (!rvs && prv_u)) && get_field(env->mstatus, MSTATUS_TW)= ) || (rvs && prv_u && !env->virt_enabled)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } else if (env->virt_enabled && (prv_u || - (prv_s && get_field(env->hstatus, HSTATUS_VTW)))) { + } else if (env->virt_enabled && + (prv_u || (prv_s && get_field(env->hstatus, HSTATUS_VTW))))= { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } else { cs->halted =3D 1; diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index a08cd95658..3943b0f2e3 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -27,7 +27,7 @@ #include "exec/exec-all.h" =20 static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, - uint8_t val); + uint8_t val); static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index); static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index); =20 @@ -220,8 +220,8 @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_= index, target_ulong addr) { int result =3D 0; =20 - if ((addr >=3D env->pmp_state.addr[pmp_index].sa) - && (addr <=3D env->pmp_state.addr[pmp_index].ea)) { + if ((addr >=3D env->pmp_state.addr[pmp_index].sa) && + (addr <=3D env->pmp_state.addr[pmp_index].ea)) { result =3D 1; } else { result =3D 0; @@ -234,8 +234,9 @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_= index, target_ulong addr) * Check if the address has required RWX privs when no PMP entry is matche= d. */ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong ad= dr, - target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs, - target_ulong mode) + target_ulong size, pmp_priv_t privs, + pmp_priv_t *allowed_privs, + target_ulong mode) { bool ret; =20 @@ -297,8 +298,8 @@ static bool pmp_hart_has_privs_default(CPURISCVState *e= nv, target_ulong addr, * Return negtive value if no match */ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, - target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs, - target_ulong mode) + target_ulong size, pmp_priv_t privs, + pmp_priv_t *allowed_privs, target_ulong mode) { int i =3D 0; int ret =3D -1; @@ -466,7 +467,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong= addr, * Handle a write to a pmpcfg CSR */ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, - target_ulong val) + target_ulong val) { int i; uint8_t cfg_val; @@ -508,7 +509,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32= _t reg_index) * Handle a write to a pmpaddr CSR */ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, - target_ulong val) + target_ulong val) { trace_pmpaddr_csr_write(env->mhartid, addr_index, val); =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 03748f72e6..3613aca28d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -746,8 +746,8 @@ EX_SH(12) } while (0) =20 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ - if (!ctx->cfg_ptr->ext_##A && \ - !ctx->cfg_ptr->ext_##B) { \ + if (!ctx->cfg_ptr->ext_##A && \ + !ctx->cfg_ptr->ext_##B) { \ return false; \ } \ } while (0) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 2423affe37..6067b5cfc7 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -50,10 +50,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_u= long s1, } } =20 - if ((sew > cpu->cfg.elen) - || vill - || (ediv !=3D 0) - || (reserved !=3D 0)) { + if ((sew > cpu->cfg.elen) || vill || (ediv !=3D 0) || (reserved !=3D 0= )) { /* only set vill bit. */ env->vill =3D 1; env->vtype =3D 0; @@ -1116,7 +1113,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ \ *((ETYPE *)vd + H(i)) =3D DO_OP(s2, (ETYPE)(target_long)s1, carry)= ;\ } \ - env->vstart =3D 0; \ + env->vstart =3D 0; = \ /* set tail elements to 1s */ \ vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } @@ -1308,7 +1305,8 @@ GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H= 8, DO_SRL, 0x3f) /* generate the helpers for shift instructions with one vector and one sca= lar */ #define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ - void *vs2, CPURISCVState *env, uint32_t desc) \ + void *vs2, CPURISCVState *env, \ + uint32_t desc) \ { \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ @@ -1735,9 +1733,9 @@ GEN_VEXT_VX(vmulhsu_vx_d, 8) /* Vector Integer Divide Instructions */ #define DO_DIVU(N, M) (unlikely(M =3D=3D 0) ? (__typeof(N))(-1) : N / M) #define DO_REMU(N, M) (unlikely(M =3D=3D 0) ? N : N % M) -#define DO_DIV(N, M) (unlikely(M =3D=3D 0) ? (__typeof(N))(-1) :\ +#define DO_DIV(N, M) (unlikely(M =3D=3D 0) ? (__typeof(N))(-1) : \ unlikely((N =3D=3D -N) && (M =3D=3D (__typeof(N))(-1))) ? N : N / = M) -#define DO_REM(N, M) (unlikely(M =3D=3D 0) ? N :\ +#define DO_REM(N, M) (unlikely(M =3D=3D 0) ? N : \ unlikely((N =3D=3D -N) && (M =3D=3D (__typeof(N))(-1))) ? 0 : N % = M) =20 RVVCALL(OPIVV2, vdivu_vv_b, OP_UUU_B, H1, H1, H1, DO_DIVU) @@ -1846,7 +1844,7 @@ GEN_VEXT_VX(vwmulsu_vx_h, 4) GEN_VEXT_VX(vwmulsu_vx_w, 8) =20 /* Vector Single-Width Integer Multiply-Add Instructions */ -#define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ +#define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ { \ TX1 s1 =3D *((T1 *)vs1 + HS1(i)); \ @@ -2277,7 +2275,8 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void= *vs2, /* generate helpers for fixed point instructions with OPIVX format */ #define GEN_VEXT_VX_RM(NAME, ESZ) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ - void *vs2, CPURISCVState *env, uint32_t desc) \ + void *vs2, CPURISCVState *env, \ + uint32_t desc) \ { \ vext_vx_rm_2(vd, v0, s1, vs2, env, desc, \ do_##NAME, ESZ); \ @@ -2651,7 +2650,7 @@ static inline int8_t vsmul8(CPURISCVState *env, int v= xrm, int8_t a, int8_t b) =20 res =3D (int16_t)a * (int16_t)b; round =3D get_round(vxrm, res, 7); - res =3D (res >> 7) + round; + res =3D (res >> 7) + round; =20 if (res > INT8_MAX) { env->vxsat =3D 0x1; @@ -2671,7 +2670,7 @@ static int16_t vsmul16(CPURISCVState *env, int vxrm, = int16_t a, int16_t b) =20 res =3D (int32_t)a * (int32_t)b; round =3D get_round(vxrm, res, 15); - res =3D (res >> 15) + round; + res =3D (res >> 15) + round; =20 if (res > INT16_MAX) { env->vxsat =3D 0x1; @@ -2691,7 +2690,7 @@ static int32_t vsmul32(CPURISCVState *env, int vxrm, = int32_t a, int32_t b) =20 res =3D (int64_t)a * (int64_t)b; round =3D get_round(vxrm, res, 31); - res =3D (res >> 31) + round; + res =3D (res >> 31) + round; =20 if (res > INT32_MAX) { env->vxsat =3D 0x1; @@ -2758,7 +2757,7 @@ vssrl8(CPURISCVState *env, int vxrm, uint8_t a, uint8= _t b) uint8_t res; =20 round =3D get_round(vxrm, a, shift); - res =3D (a >> shift) + round; + res =3D (a >> shift) + round; return res; } static inline uint16_t @@ -2862,7 +2861,7 @@ vnclip8(CPURISCVState *env, int vxrm, int16_t a, int8= _t b) int16_t res; =20 round =3D get_round(vxrm, a, shift); - res =3D (a >> shift) + round; + res =3D (a >> shift) + round; if (res > INT8_MAX) { env->vxsat =3D 0x1; return INT8_MAX; @@ -2881,7 +2880,7 @@ vnclip16(CPURISCVState *env, int vxrm, int32_t a, int= 16_t b) int32_t res; =20 round =3D get_round(vxrm, a, shift); - res =3D (a >> shift) + round; + res =3D (a >> shift) + round; if (res > INT16_MAX) { env->vxsat =3D 0x1; return INT16_MAX; @@ -2900,7 +2899,7 @@ vnclip32(CPURISCVState *env, int vxrm, int64_t a, int= 32_t b) int64_t res; =20 round =3D get_round(vxrm, a, shift); - res =3D (a >> shift) + round; + res =3D (a >> shift) + round; if (res > INT32_MAX) { env->vxsat =3D 0x1; return INT32_MAX; @@ -2933,7 +2932,7 @@ vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, ui= nt8_t b) uint16_t res; =20 round =3D get_round(vxrm, a, shift); - res =3D (a >> shift) + round; + res =3D (a >> shift) + round; if (res > UINT8_MAX) { env->vxsat =3D 0x1; return UINT8_MAX; @@ -2949,7 +2948,7 @@ vnclipu16(CPURISCVState *env, int vxrm, uint32_t a, u= int16_t b) uint32_t res; =20 round =3D get_round(vxrm, a, shift); - res =3D (a >> shift) + round; + res =3D (a >> shift) + round; if (res > UINT16_MAX) { env->vxsat =3D 0x1; return UINT16_MAX; @@ -2965,7 +2964,7 @@ vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, u= int32_t b) uint64_t res; =20 round =3D get_round(vxrm, a, shift); - res =3D (a >> shift) + round; + res =3D (a >> shift) + round; if (res > UINT32_MAX) { env->vxsat =3D 0x1; return UINT32_MAX; @@ -3052,7 +3051,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, = \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ uint32_t total_elems =3D \ - vext_get_total_elems(env, desc, ESZ); \ + vext_get_total_elems(env, desc, ESZ); \ uint32_t vta =3D vext_vta(desc); \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ @@ -3118,13 +3117,13 @@ GEN_VEXT_VF(vfrsub_vf_d, 8) static uint32_t vfwadd16(uint16_t a, uint16_t b, float_status *s) { return float32_add(float16_to_float32(a, true, s), - float16_to_float32(b, true, s), s); + float16_to_float32(b, true, s), s); } =20 static uint64_t vfwadd32(uint32_t a, uint32_t b, float_status *s) { return float64_add(float32_to_float64(a, s), - float32_to_float64(b, s), s); + float32_to_float64(b, s), s); =20 } =20 @@ -3140,13 +3139,13 @@ GEN_VEXT_VF(vfwadd_vf_w, 8) static uint32_t vfwsub16(uint16_t a, uint16_t b, float_status *s) { return float32_sub(float16_to_float32(a, true, s), - float16_to_float32(b, true, s), s); + float16_to_float32(b, true, s), s); } =20 static uint64_t vfwsub32(uint32_t a, uint32_t b, float_status *s) { return float64_sub(float32_to_float64(a, s), - float32_to_float64(b, s), s); + float32_to_float64(b, s), s); =20 } =20 @@ -3250,13 +3249,13 @@ GEN_VEXT_VF(vfrdiv_vf_d, 8) static uint32_t vfwmul16(uint16_t a, uint16_t b, float_status *s) { return float32_mul(float16_to_float32(a, true, s), - float16_to_float32(b, true, s), s); + float16_to_float32(b, true, s), s); } =20 static uint64_t vfwmul32(uint32_t a, uint32_t b, float_status *s) { return float64_mul(float32_to_float64(a, s), - float32_to_float64(b, s), s); + float32_to_float64(b, s), s); =20 } RVVCALL(OPFVV2, vfwmul_vv_h, WOP_UUU_H, H4, H2, H2, vfwmul16) @@ -3271,7 +3270,7 @@ GEN_VEXT_VF(vfwmul_vf_w, 8) /* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */ #define OPFVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \ - CPURISCVState *env) \ + CPURISCVState *env) \ { \ TX1 s1 =3D *((T1 *)vs1 + HS1(i)); \ TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ @@ -3303,7 +3302,7 @@ GEN_VEXT_VV_ENV(vfmacc_vv_d, 8) =20 #define OPFVF3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \ - CPURISCVState *env) \ + CPURISCVState *env) \ { \ TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ TD d =3D *((TD *)vd + HD(i)); \ @@ -3319,20 +3318,20 @@ GEN_VEXT_VF(vfmacc_vf_d, 8) =20 static uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status = *s) { - return float16_muladd(a, b, d, - float_muladd_negate_c | float_muladd_negate_product, s); + return float16_muladd(a, b, d, float_muladd_negate_c | + float_muladd_negate_product, s); } =20 static uint32_t fnmacc32(uint32_t a, uint32_t b, uint32_t d, float_status = *s) { - return float32_muladd(a, b, d, - float_muladd_negate_c | float_muladd_negate_product, s); + return float32_muladd(a, b, d, float_muladd_negate_c | + float_muladd_negate_product, s); } =20 static uint64_t fnmacc64(uint64_t a, uint64_t b, uint64_t d, float_status = *s) { - return float64_muladd(a, b, d, - float_muladd_negate_c | float_muladd_negate_product, s); + return float64_muladd(a, b, d, float_muladd_negate_c | + float_muladd_negate_product, s); } =20 RVVCALL(OPFVV3, vfnmacc_vv_h, OP_UUU_H, H2, H2, H2, fnmacc16) @@ -3434,20 +3433,20 @@ GEN_VEXT_VF(vfmadd_vf_d, 8) =20 static uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status = *s) { - return float16_muladd(d, b, a, - float_muladd_negate_c | float_muladd_negate_product, s); + return float16_muladd(d, b, a, float_muladd_negate_c | + float_muladd_negate_product, s); } =20 static uint32_t fnmadd32(uint32_t a, uint32_t b, uint32_t d, float_status = *s) { - return float32_muladd(d, b, a, - float_muladd_negate_c | float_muladd_negate_product, s); + return float32_muladd(d, b, a, float_muladd_negate_c | + float_muladd_negate_product, s); } =20 static uint64_t fnmadd64(uint64_t a, uint64_t b, uint64_t d, float_status = *s) { - return float64_muladd(d, b, a, - float_muladd_negate_c | float_muladd_negate_product, s); + return float64_muladd(d, b, a, float_muladd_negate_c | + float_muladd_negate_product, s); } =20 RVVCALL(OPFVV3, vfnmadd_vv_h, OP_UUU_H, H2, H2, H2, fnmadd16) @@ -3523,13 +3522,13 @@ GEN_VEXT_VF(vfnmsub_vf_d, 8) static uint32_t fwmacc16(uint16_t a, uint16_t b, uint32_t d, float_status = *s) { return float32_muladd(float16_to_float32(a, true, s), - float16_to_float32(b, true, s), d, 0, s); + float16_to_float32(b, true, s), d, 0, s); } =20 static uint64_t fwmacc32(uint32_t a, uint32_t b, uint64_t d, float_status = *s) { return float64_muladd(float32_to_float64(a, s), - float32_to_float64(b, s), d, 0, s); + float32_to_float64(b, s), d, 0, s); } =20 RVVCALL(OPFVV3, vfwmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwmacc16) @@ -3544,15 +3543,16 @@ GEN_VEXT_VF(vfwmacc_vf_w, 8) static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status= *s) { return float32_muladd(float16_to_float32(a, true, s), - float16_to_float32(b, true, s), d, - float_muladd_negate_c | float_muladd_negate_produc= t, s); + float16_to_float32(b, true, s), d, + float_muladd_negate_c | float_muladd_negate_prod= uct, + s); } =20 static uint64_t fwnmacc32(uint32_t a, uint32_t b, uint64_t d, float_status= *s) { - return float64_muladd(float32_to_float64(a, s), - float32_to_float64(b, s), d, - float_muladd_negate_c | float_muladd_negate_produc= t, s); + return float64_muladd(float32_to_float64(a, s), float32_to_float64(b, = s), + d, float_muladd_negate_c | + float_muladd_negate_product, s); } =20 RVVCALL(OPFVV3, vfwnmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwnmacc16) @@ -3567,15 +3567,15 @@ GEN_VEXT_VF(vfwnmacc_vf_w, 8) static uint32_t fwmsac16(uint16_t a, uint16_t b, uint32_t d, float_status = *s) { return float32_muladd(float16_to_float32(a, true, s), - float16_to_float32(b, true, s), d, - float_muladd_negate_c, s); + float16_to_float32(b, true, s), d, + float_muladd_negate_c, s); } =20 static uint64_t fwmsac32(uint32_t a, uint32_t b, uint64_t d, float_status = *s) { return float64_muladd(float32_to_float64(a, s), - float32_to_float64(b, s), d, - float_muladd_negate_c, s); + float32_to_float64(b, s), d, + float_muladd_negate_c, s); } =20 RVVCALL(OPFVV3, vfwmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwmsac16) @@ -3590,15 +3590,15 @@ GEN_VEXT_VF(vfwmsac_vf_w, 8) static uint32_t fwnmsac16(uint16_t a, uint16_t b, uint32_t d, float_status= *s) { return float32_muladd(float16_to_float32(a, true, s), - float16_to_float32(b, true, s), d, - float_muladd_negate_product, s); + float16_to_float32(b, true, s), d, + float_muladd_negate_product, s); } =20 static uint64_t fwnmsac32(uint32_t a, uint32_t b, uint64_t d, float_status= *s) { return float64_muladd(float32_to_float64(a, s), - float32_to_float64(b, s), d, - float_muladd_negate_product, s); + float32_to_float64(b, s), d, + float_muladd_negate_product, s); } =20 RVVCALL(OPFVV3, vfwnmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwnmsac16) @@ -3616,9 +3616,9 @@ GEN_VEXT_VF(vfwnmsac_vf_w, 8) #define OP_UU_W uint32_t, uint32_t, uint32_t #define OP_UU_D uint64_t, uint64_t, uint64_t =20 -#define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ +#define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ static void do_##NAME(void *vd, void *vs2, int i, \ - CPURISCVState *env) \ + CPURISCVState *env) \ { \ TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ *((TD *)vd + HD(i)) =3D OP(s2, &env->fp_status); \ @@ -3626,7 +3626,7 @@ static void do_##NAME(void *vd, void *vs2, int i, = \ =20 #define GEN_VEXT_V_ENV(NAME, ESZ) \ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ - CPURISCVState *env, uint32_t desc) \ + CPURISCVState *env, uint32_t desc) \ { \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ @@ -3703,9 +3703,9 @@ static uint64_t frsqrt7(uint64_t f, int exp_size, int= frac_size) } =20 int idx =3D ((exp & 1) << (precision - 1)) | - (frac >> (frac_size - precision + 1)); + (frac >> (frac_size - precision + 1)); uint64_t out_frac =3D (uint64_t)(lookup_table[idx]) << - (frac_size - precision); + (frac_size - precision); uint64_t out_exp =3D (3 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp) / 2; =20 uint64_t val =3D 0; @@ -3727,9 +3727,9 @@ static float16 frsqrt7_h(float16 f, float_status *s) * frsqrt7(-subnormal) =3D canonical NaN */ if (float16_is_signaling_nan(f, s) || - (float16_is_infinity(f) && sign) || - (float16_is_normal(f) && sign) || - (float16_is_zero_or_denormal(f) && !float16_is_zero(f) && sign= )) { + (float16_is_infinity(f) && sign) || + (float16_is_normal(f) && sign) || + (float16_is_zero_or_denormal(f) && !float16_is_zero(f) && sign)) { s->float_exception_flags |=3D float_flag_invalid; return float16_default_nan(s); } @@ -3767,9 +3767,9 @@ static float32 frsqrt7_s(float32 f, float_status *s) * frsqrt7(-subnormal) =3D canonical NaN */ if (float32_is_signaling_nan(f, s) || - (float32_is_infinity(f) && sign) || - (float32_is_normal(f) && sign) || - (float32_is_zero_or_denormal(f) && !float32_is_zero(f) && sign= )) { + (float32_is_infinity(f) && sign) || + (float32_is_normal(f) && sign) || + (float32_is_zero_or_denormal(f) && !float32_is_zero(f) && sign)) { s->float_exception_flags |=3D float_flag_invalid; return float32_default_nan(s); } @@ -3807,9 +3807,9 @@ static float64 frsqrt7_d(float64 f, float_status *s) * frsqrt7(-subnormal) =3D canonical NaN */ if (float64_is_signaling_nan(f, s) || - (float64_is_infinity(f) && sign) || - (float64_is_normal(f) && sign) || - (float64_is_zero_or_denormal(f) && !float64_is_zero(f) && sign= )) { + (float64_is_infinity(f) && sign) || + (float64_is_normal(f) && sign) || + (float64_is_zero_or_denormal(f) && !float64_is_zero(f) && sign)) { s->float_exception_flags |=3D float_flag_invalid; return float64_default_nan(s); } @@ -3897,18 +3897,18 @@ static uint64_t frec7(uint64_t f, int exp_size, int= frac_size, ((s->float_rounding_mode =3D=3D float_round_up) && sign)) { /* Return greatest/negative finite value. */ return (sign << (exp_size + frac_size)) | - (MAKE_64BIT_MASK(frac_size, exp_size) - 1); + (MAKE_64BIT_MASK(frac_size, exp_size) - 1); } else { /* Return +-inf. */ return (sign << (exp_size + frac_size)) | - MAKE_64BIT_MASK(frac_size, exp_size); + MAKE_64BIT_MASK(frac_size, exp_size); } } } =20 int idx =3D frac >> (frac_size - precision); uint64_t out_frac =3D (uint64_t)(lookup_table[idx]) << - (frac_size - precision); + (frac_size - precision); uint64_t out_exp =3D 2 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp; =20 if (out_exp =3D=3D 0 || out_exp =3D=3D UINT64_MAX) { @@ -4422,8 +4422,8 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, vo= id *vs2, \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ - *((ETYPE *)vd + H(i)) \ - =3D (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \ + *((ETYPE *)vd + H(i)) =3D \ + (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \ } \ env->vstart =3D 0; \ /* set tail elements to 1s */ \ @@ -4564,7 +4564,8 @@ GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4) /* Vector Single-Width Integer Reduction Instructions */ #define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ - void *vs2, CPURISCVState *env, uint32_t desc) \ + void *vs2, CPURISCVState *env, \ + uint32_t desc) \ { \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ @@ -5013,7 +5014,8 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8) =20 #define GEN_VEXT_VSLIE1UP(BITWIDTH, H) = \ static void vslide1up_##BITWIDTH(void *vd, void *v0, uint64_t s1, = \ - void *vs2, CPURISCVState *env, uint32_t desc) = \ + void *vs2, CPURISCVState *env, = \ + uint32_t desc) = \ { = \ typedef uint##BITWIDTH##_t ETYPE; = \ uint32_t vm =3D vext_vm(desc); = \ @@ -5061,7 +5063,8 @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64) =20 #define GEN_VEXT_VSLIDE1DOWN(BITWIDTH, H) = \ static void vslide1down_##BITWIDTH(void *vd, void *v0, uint64_t s1, = \ - void *vs2, CPURISCVState *env, uint32_t desc) = \ + void *vs2, CPURISCVState *env, = \ + uint32_t desc) = \ { = \ typedef uint##BITWIDTH##_t ETYPE; = \ uint32_t vm =3D vext_vm(desc); = \ diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index f2e3d38515..8e43bfc07c 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -238,8 +238,8 @@ static bool vext_check_store(DisasContext *s, int vd, i= nt nf, uint8_t eew) { int8_t emul =3D eew - s->sew + s->lmul; return (emul >=3D -3 && emul <=3D 3) && - require_align(vd, emul) && - require_nf(vd, nf, emul); + require_align(vd, emul) && + require_nf(vd, nf, emul); } =20 /* @@ -315,7 +315,7 @@ static bool vext_check_ld_index(DisasContext *s, int vd= , int vs2, int8_t seg_vd; int8_t emul =3D eew - s->sew + s->lmul; bool ret =3D vext_check_st_index(s, vd, vs2, nf, eew) && - require_vm(vm, vd); + require_vm(vm, vd); =20 /* Each segment register group has to follow overlap rules. */ for (int i =3D 0; i < nf; ++i) { @@ -345,8 +345,8 @@ static bool vext_check_ld_index(DisasContext *s, int vd= , int vs2, static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm) { return require_vm(vm, vd) && - require_align(vd, s->lmul) && - require_align(vs, s->lmul); + require_align(vd, s->lmul) && + require_align(vs, s->lmul); } =20 /* @@ -365,7 +365,7 @@ static bool vext_check_ss(DisasContext *s, int vd, int = vs, int vm) static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int = vm) { return vext_check_ss(s, vd, vs2, vm) && - require_align(vs1, s->lmul); + require_align(vs1, s->lmul); } =20 static bool vext_check_ms(DisasContext *s, int vd, int vs) @@ -396,7 +396,7 @@ static bool vext_check_ms(DisasContext *s, int vd, int = vs) static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2) { bool ret =3D vext_check_ms(s, vd, vs2) && - require_align(vs1, s->lmul); + require_align(vs1, s->lmul); if (vd !=3D vs1) { ret &=3D require_noover(vd, 0, vs1, s->lmul); } @@ -460,14 +460,14 @@ static bool vext_narrow_check_common(DisasContext *s,= int vd, int vs2, static bool vext_check_ds(DisasContext *s, int vd, int vs, int vm) { return vext_wide_check_common(s, vd, vm) && - require_align(vs, s->lmul) && - require_noover(vd, s->lmul + 1, vs, s->lmul); + require_align(vs, s->lmul) && + require_noover(vd, s->lmul + 1, vs, s->lmul); } =20 static bool vext_check_dd(DisasContext *s, int vd, int vs, int vm) { return vext_wide_check_common(s, vd, vm) && - require_align(vs, s->lmul + 1); + require_align(vs, s->lmul + 1); } =20 /* @@ -485,8 +485,8 @@ static bool vext_check_dd(DisasContext *s, int vd, int = vs, int vm) static bool vext_check_dss(DisasContext *s, int vd, int vs1, int vs2, int = vm) { return vext_check_ds(s, vd, vs2, vm) && - require_align(vs1, s->lmul) && - require_noover(vd, s->lmul + 1, vs1, s->lmul); + require_align(vs1, s->lmul) && + require_noover(vd, s->lmul + 1, vs1, s->lmul); } =20 /* @@ -507,7 +507,7 @@ static bool vext_check_dss(DisasContext *s, int vd, int= vs1, int vs2, int vm) static bool vext_check_dds(DisasContext *s, int vd, int vs1, int vs2, int = vm) { return vext_check_ds(s, vd, vs1, vm) && - require_align(vs2, s->lmul + 1); + require_align(vs2, s->lmul + 1); } =20 static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm) @@ -535,7 +535,7 @@ static bool vext_check_sd(DisasContext *s, int vd, int = vs, int vm) static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, int = vm) { return vext_check_sd(s, vd, vs2, vm) && - require_align(vs1, s->lmul); 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Add spaces around single line comments(after "/*" and before "*/"). Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-Id: <20230405085813.40643-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 26 ++++---- target/riscv/cpu_bits.h | 2 +- target/riscv/sbi_ecall_interface.h | 8 +-- target/riscv/arch_dump.c | 3 +- target/riscv/cpu.c | 2 +- target/riscv/cpu_helper.c | 57 +++++++++++------ target/riscv/csr.c | 6 +- target/riscv/pmp.c | 41 +++++++------ target/riscv/translate.c | 20 +++--- target/riscv/vector_helper.c | 82 +++++++++++++++---------- target/riscv/insn_trans/trans_rvv.c.inc | 8 ++- 11 files changed, 151 insertions(+), 104 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 995192757a..5018a3b1b2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -124,7 +124,7 @@ FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 1= 1) typedef struct PMUCTRState { /* Current value of a counter */ target_ulong mhpmcounter_val; - /* Current value of a counter in RV32*/ + /* Current value of a counter in RV32 */ target_ulong mhpmcounterh_val; /* Snapshot values of counter */ target_ulong mhpmcounter_prev; @@ -280,8 +280,10 @@ struct CPUArchState { target_ulong satp_hs; uint64_t mstatus_hs; =20 - /* Signals whether the current exception occurred with two-stage addre= ss - translation active. */ + /* + * Signals whether the current exception occurred with two-stage addre= ss + * translation active. + */ bool two_stage_lookup; /* * Signals whether the current exception occurred while doing two-stage @@ -297,10 +299,10 @@ struct CPUArchState { /* PMU counter state */ PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; =20 - /* PMU event selector configured values. First three are unused*/ + /* PMU event selector configured values. First three are unused */ target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; =20 - /* PMU event selector configured values for RV32*/ + /* PMU event selector configured values for RV32 */ target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; =20 target_ulong sscratch; @@ -389,7 +391,7 @@ struct CPUArchState { =20 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) =20 -/** +/* * RISCVCPUClass: * @parent_realize: The parent class' realize handler. * @parent_phases: The parent class' reset phase handlers. @@ -397,9 +399,9 @@ OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_= CPU) * A RISCV CPU model. */ struct RISCVCPUClass { - /*< private >*/ + /* < private > */ CPUClass parent_class; - /*< public >*/ + /* < public > */ DeviceRealize parent_realize; ResettablePhases parent_phases; }; @@ -530,16 +532,16 @@ struct RISCVCPUConfig { =20 typedef struct RISCVCPUConfig RISCVCPUConfig; =20 -/** +/* * RISCVCPU: * @env: #CPURISCVState * * A RISCV CPU. */ struct ArchCPU { - /*< private >*/ + /* < private > */ CPUState parent_obj; - /*< public >*/ + /* < public > */ CPUNegativeOffsetState neg; CPURISCVState env; =20 @@ -813,7 +815,7 @@ enum { CSR_TABLE_SIZE =3D 0x1000 }; =20 -/** +/* * The event id are encoded based on the encoding specified in the * SBI specification v0.3 */ diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 190e517862..101702cb4a 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -731,7 +731,7 @@ typedef enum RISCVException { #define MIE_SSIE (1 << IRQ_S_SOFT) #define MIE_USIE (1 << IRQ_U_SOFT) =20 -/* General PointerMasking CSR bits*/ +/* General PointerMasking CSR bits */ #define PM_ENABLE 0x00000001ULL #define PM_CURRENT 0x00000002ULL #define PM_INSN 0x00000004ULL diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_in= terface.h index 77574ed4cb..43899d08f6 100644 --- a/target/riscv/sbi_ecall_interface.h +++ b/target/riscv/sbi_ecall_interface.h @@ -28,7 +28,7 @@ #define SBI_EXT_RFENCE 0x52464E43 #define SBI_EXT_HSM 0x48534D =20 -/* SBI function IDs for BASE extension*/ +/* SBI function IDs for BASE extension */ #define SBI_EXT_BASE_GET_SPEC_VERSION 0x0 #define SBI_EXT_BASE_GET_IMP_ID 0x1 #define SBI_EXT_BASE_GET_IMP_VERSION 0x2 @@ -37,13 +37,13 @@ #define SBI_EXT_BASE_GET_MARCHID 0x5 #define SBI_EXT_BASE_GET_MIMPID 0x6 =20 -/* SBI function IDs for TIME extension*/ +/* SBI function IDs for TIME extension */ #define SBI_EXT_TIME_SET_TIMER 0x0 =20 -/* SBI function IDs for IPI extension*/ +/* SBI function IDs for IPI extension */ #define SBI_EXT_IPI_SEND_IPI 0x0 =20 -/* SBI function IDs for RFENCE extension*/ +/* SBI function IDs for RFENCE extension */ #define SBI_EXT_RFENCE_REMOTE_FENCE_I 0x0 #define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA 0x1 #define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID 0x2 diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c index 573587810e..434c8a3dbb 100644 --- a/target/riscv/arch_dump.c +++ b/target/riscv/arch_dump.c @@ -1,4 +1,5 @@ -/* Support for writing ELF notes for RISC-V architectures +/* + * Support for writing ELF notes for RISC-V architectures * * Copyright (C) 2021 Huawei Technologies Co., Ltd * diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8ed8601399..2e45b1f076 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -56,7 +56,7 @@ struct isa_ext_data { #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} =20 -/** +/* * Here are the ordering rules of extension naming defined by RISC-V * specification : * 1. All extensions should be separated from other multi-letter extensions diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8d2547a164..445ffe691a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -717,7 +717,8 @@ static int get_physical_address_pmp(CPURISCVState *env,= int *prot, return TRANSLATE_SUCCESS; } =20 -/* get_physical_address - get the physical address for this virtual address +/* + * get_physical_address - get the physical address for this virtual address * * Do a page table walk to obtain the physical address corresponding to a * virtual address. Returns 0 if the translation was successful @@ -745,9 +746,11 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, bool first_stage, bool two_stage, bool is_debug) { - /* NOTE: the env->pc value visible here will not be + /* + * NOTE: the env->pc value visible here will not be * correct, but the value visible to the exception handler - * (riscv_cpu_do_interrupt) is correct */ + * (riscv_cpu_do_interrupt) is correct + */ MemTxResult res; MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; int mode =3D mmu_idx & TB_FLAGS_PRIV_MMU_MASK; @@ -767,8 +770,10 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, use_background =3D true; } =20 - /* MPRV does not affect the virtual-machine load/store - instructions, HLV, HLVX, and HSV. */ + /* + * MPRV does not affect the virtual-machine load/store + * instructions, HLV, HLVX, and HSV. + */ if (riscv_cpu_two_stage_lookup(mmu_idx)) { mode =3D get_field(env->hstatus, HSTATUS_SPVP); } else if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { @@ -778,8 +783,10 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, } =20 if (first_stage =3D=3D false) { - /* We are in stage 2 translation, this is similar to stage 1. */ - /* Stage 2 is always taken as U-mode */ + /* + * We are in stage 2 translation, this is similar to stage 1. + * Stage 2 is always taken as U-mode + */ mode =3D PRV_U; } =20 @@ -1007,8 +1014,10 @@ restart: target_ulong *pte_pa =3D qemu_map_ram_ptr(mr->ram_block, addr1); #if TCG_OVERSIZED_GUEST - /* MTTCG is not enabled on oversized TCG guests so - * page table updates do not need to be atomic */ + /* + * MTTCG is not enabled on oversized TCG guests so + * page table updates do not need to be atomic + */ *pte_pa =3D pte =3D updated_pte; #else target_ulong old_pte =3D @@ -1020,14 +1029,18 @@ restart: } #endif } else { - /* misconfigured PTE in ROM (AD bits are not preset) or - * PTE is in IO space and can't be updated atomically = */ + /* + * misconfigured PTE in ROM (AD bits are not preset) or + * PTE is in IO space and can't be updated atomically + */ return TRANSLATE_FAIL; } } =20 - /* for superpage mappings, make a fake leaf PTE for the TLB's - benefit. */ + /* + * for superpage mappings, make a fake leaf PTE for the TLB's + * benefit. + */ target_ulong vpn =3D addr >> PGSHIFT; =20 if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { @@ -1049,8 +1062,10 @@ restart: if (pte & PTE_X) { *prot |=3D PAGE_EXEC; } - /* add write permission on stores or if the page is already di= rty, - so that we TLB miss on later writes to update the dirty bit= */ + /* + * add write permission on stores or if the page is already di= rty, + * so that we TLB miss on later writes to update the dirty bit + */ if ((pte & PTE_W) && (access_type =3D=3D MMU_DATA_STORE || (pte & PTE_D))) { *prot |=3D PAGE_WRITE; @@ -1235,8 +1250,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,= int size, qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); =20 - /* MPRV does not affect the virtual-machine load/store - instructions, HLV, HLVX, and HSV. */ + /* + * MPRV does not affect the virtual-machine load/store + * instructions, HLV, HLVX, and HSV. + */ if (riscv_cpu_two_stage_lookup(mmu_idx)) { mode =3D get_field(env->hstatus, HSTATUS_SPVP); } else if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH && @@ -1577,7 +1594,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool write_gva =3D false; uint64_t s; =20 - /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide + /* + * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide * so we mask off the MSB and separate into trap type and cause. */ bool async =3D !!(cs->exception_index & RISCV_EXCP_INT_FLAG); @@ -1754,7 +1772,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_set_mode(env, PRV_M); } =20 - /* NOTE: it is not necessary to yield load reservations here. It is on= ly + /* + * NOTE: it is not necessary to yield load reservations here. It is on= ly * necessary for an SC from "another hart" to cause a load reservation * to be yielded. Refer to the memory consistency model section of the * RISC-V ISA Specification. diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 41e56012d5..76755ee128 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -189,7 +189,7 @@ static RISCVException mctr(CPURISCVState *env, int csrn= o) } ctr_index =3D csrno - base_csrno; if (!pmu_num || ctr_index >=3D pmu_num) { - /* The PMU is not enabled or counter is out of range*/ + /* The PMU is not enabled or counter is out of range */ return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -877,7 +877,7 @@ static RISCVException riscv_pmu_read_ctr(CPURISCVState = *env, target_ulong *val, counter.mhpmcounter_val; =20 if (get_field(env->mcountinhibit, BIT(ctr_idx))) { - /** + /* * Counter should not increment if inhibit bit is set. We can't re= ally * stop the icount counting. Just return the counter value written= by * the supervisor to indicate that counter was not incremented. @@ -891,7 +891,7 @@ static RISCVException riscv_pmu_read_ctr(CPURISCVState = *env, target_ulong *val, } } =20 - /** + /* * The kernel computes the perf delta by subtracting the current value= from * the value it initialized previously (ctr_val). */ diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 3943b0f2e3..6ab2ae81c7 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -132,15 +132,15 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_= t pmp_index, uint8_t val) static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulon= g *ea) { /* - aaaa...aaa0 8-byte NAPOT range - aaaa...aa01 16-byte NAPOT range - aaaa...a011 32-byte NAPOT range - ... - aa01...1111 2^XLEN-byte NAPOT range - a011...1111 2^(XLEN+1)-byte NAPOT range - 0111...1111 2^(XLEN+2)-byte NAPOT range - 1111...1111 Reserved - */ + * aaaa...aaa0 8-byte NAPOT range + * aaaa...aa01 16-byte NAPOT range + * aaaa...a011 32-byte NAPOT range + * ... + * aa01...1111 2^XLEN-byte NAPOT range + * a011...1111 2^(XLEN+1)-byte NAPOT range + * 0111...1111 2^(XLEN+2)-byte NAPOT range + * 1111...1111 Reserved + */ a =3D (a << 2) | 0x3; *sa =3D a & (a + 1); *ea =3D a | (a + 1); @@ -205,7 +205,8 @@ void pmp_update_rule_nums(CPURISCVState *env) } } =20 -/* Convert cfg/addr reg values here into simple 'sa' --> start address and= 'ea' +/* + * Convert cfg/addr reg values here into simple 'sa' --> start address and= 'ea' * end address values. * This function is called relatively infrequently whereas the check that * an address is within a pmp rule is called often, so optimise that one @@ -329,8 +330,10 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulon= g addr, pmp_size =3D size; } =20 - /* 1.10 draft priv spec states there is an implicit order - from low to high */ + /* + * 1.10 draft priv spec states there is an implicit order + * from low to high + */ for (i =3D 0; i < MAX_RISCV_PMPS; i++) { s =3D pmp_is_in_range(env, i, addr); e =3D pmp_is_in_range(env, i, addr + pmp_size - 1); @@ -609,13 +612,13 @@ target_ulong pmp_get_tlb_size(CPURISCVState *env, int= pmp_index, return TARGET_PAGE_SIZE; } else { /* - * At this point we have a tlb_size that is the smallest possible s= ize - * That fits within a TARGET_PAGE_SIZE and the PMP region. - * - * If the size is less then TARGET_PAGE_SIZE we drop the size to 1. - * This means the result isn't cached in the TLB and is only used f= or - * a single translation. - */ + * At this point we have a tlb_size that is the smallest possible = size + * That fits within a TARGET_PAGE_SIZE and the PMP region. + * + * If the size is less then TARGET_PAGE_SIZE we drop the size to 1. + * This means the result isn't cached in the TLB and is only used = for + * a single translation. + */ return 1; } } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3613aca28d..d0094922b6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -69,11 +69,13 @@ typedef struct DisasContext { uint32_t mstatus_hs_fs; uint32_t mstatus_hs_vs; uint32_t mem_idx; - /* Remember the rounding mode encoded in the previous fp instruction, - which we have already installed into env->fp_status. Or -1 for - no previous fp instruction. Note that we exit the TB when writing - to any system register, which includes CSR_FRM, so we do not have - to reset this known value. */ + /* + * Remember the rounding mode encoded in the previous fp instruction, + * which we have already installed into env->fp_status. Or -1 for + * no previous fp instruction. Note that we exit the TB when writing + * to any system register, which includes CSR_FRM, so we do not have + * to reset this known value. + */ int frm; RISCVMXL ol; bool virt_inst_excp; @@ -491,7 +493,7 @@ static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) } } =20 -/* assume t is nanboxing (for normal) or sign-extended (for zfinx) */ +/* assume it is nanboxing (for normal) or sign-extended (for zfinx) */ static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) { if (!ctx->cfg_ptr->ext_zfinx) { @@ -598,7 +600,8 @@ static TCGv get_address_indexed(DisasContext *ctx, int = rs1, TCGv offs) } =20 #ifndef CONFIG_USER_ONLY -/* The states of mstatus_fs are: +/* + * The states of mstatus_fs are: * 0 =3D disabled, 1 =3D initial, 2 =3D clean, 3 =3D dirty * We will have already diagnosed disabled state, * and need to turn initial/clean into dirty. @@ -636,7 +639,8 @@ static inline void mark_fs_dirty(DisasContext *ctx) { } #endif =20 #ifndef CONFIG_USER_ONLY -/* The states of mstatus_vs are: +/* + * The states of mstatus_vs are: * 0 =3D disabled, 1 =3D initial, 2 =3D clean, 3 =3D dirty * We will have already diagnosed disabled state, * and need to turn initial/clean into dirty. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 6067b5cfc7..81ac85b7d5 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -287,7 +287,7 @@ static void vext_set_tail_elems_1s(CPURISCVState *env, = target_ulong vl, } =20 /* - *** stride: access vector element from strided memory + * stride: access vector element from strided memory */ static void vext_ldst_stride(void *vd, void *v0, target_ulong base, @@ -353,10 +353,10 @@ GEN_VEXT_ST_STRIDE(vsse32_v, int32_t, ste_w) GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d) =20 /* - *** unit-stride: access elements stored contiguously in memory + * unit-stride: access elements stored contiguously in memory */ =20 -/* unmasked unit-stride load and store operation*/ +/* unmasked unit-stride load and store operation */ static void vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t des= c, vext_ldst_elem_fn *ldst_elem, uint32_t log2_esz, uint32_t evl, @@ -429,7 +429,7 @@ GEN_VEXT_ST_US(vse32_v, int32_t, ste_w) GEN_VEXT_ST_US(vse64_v, int64_t, ste_d) =20 /* - *** unit stride mask load and store, EEW =3D 1 + * unit stride mask load and store, EEW =3D 1 */ void HELPER(vlm_v)(void *vd, void *v0, target_ulong base, CPURISCVState *env, uint32_t desc) @@ -450,7 +450,7 @@ void HELPER(vsm_v)(void *vd, void *v0, target_ulong bas= e, } =20 /* - *** index: access vector element from indexed memory + * index: access vector element from indexed memory */ typedef target_ulong vext_get_index_addr(target_ulong base, uint32_t idx, void *vs2); @@ -554,7 +554,7 @@ GEN_VEXT_ST_INDEX(vsxei64_32_v, int32_t, idx_d, ste_w) GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d) =20 /* - *** unit-stride fault-only-fisrt load instructions + * unit-stride fault-only-fisrt load instructions */ static inline void vext_ldff(void *vd, void *v0, target_ulong base, @@ -571,7 +571,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, uint32_t vma =3D vext_vma(desc); target_ulong addr, offset, remain; =20 - /* probe every access*/ + /* probe every access */ for (i =3D env->vstart; i < env->vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { continue; @@ -660,7 +660,7 @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d) #define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M) =20 /* - *** load and store whole register instructions + * load and store whole register instructions */ static void vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t = desc, @@ -733,7 +733,7 @@ GEN_VEXT_ST_WHOLE(vs4r_v, int8_t, ste_b) GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) =20 /* - *** Vector Integer Arithmetic Instructions + * Vector Integer Arithmetic Instructions */ =20 /* expand macro args before macro */ @@ -1149,8 +1149,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, voi= d *vs2, \ vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \ } \ env->vstart =3D 0; \ - /* mask destination register are always tail-agnostic */ \ - /* set tail elements to 1s */ \ + /* + * mask destination register are always tail-agnostic + * set tail elements to 1s + */ \ if (vta_all_1s) { \ for (; i < total_elems; i++) { \ vext_set_elem_mask(vd, i, 1); \ @@ -1185,8 +1187,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s= 1, \ DO_OP(s2, (ETYPE)(target_long)s1, carry)); \ } \ env->vstart =3D 0; \ - /* mask destination register are always tail-agnostic */ \ - /* set tail elements to 1s */ \ + /* + * mask destination register are always tail-agnostic + * set tail elements to 1s + */ \ if (vta_all_1s) { \ for (; i < total_elems; i++) { \ vext_set_elem_mask(vd, i, 1); \ @@ -1392,8 +1396,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, voi= d *vs2, \ vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \ } \ env->vstart =3D 0; \ - /* mask destination register are always tail-agnostic */ \ - /* set tail elements to 1s */ \ + /* + * mask destination register are always tail-agnostic + * set tail elements to 1s + */ \ if (vta_all_1s) { \ for (; i < total_elems; i++) { \ vext_set_elem_mask(vd, i, 1); \ @@ -1455,8 +1461,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s= 1, void *vs2, \ DO_OP(s2, (ETYPE)(target_long)s1)); \ } \ env->vstart =3D 0; \ - /* mask destination register are always tail-agnostic */ \ - /* set tail elements to 1s */ \ + /* + * mask destination register are always tail-agnostic + * set tail elements to 1s + */ \ if (vta_all_1s) { \ for (; i < total_elems; i++) { \ vext_set_elem_mask(vd, i, 1); \ @@ -2075,7 +2083,7 @@ GEN_VEXT_VMERGE_VX(vmerge_vxm_w, int32_t, H4) GEN_VEXT_VMERGE_VX(vmerge_vxm_d, int64_t, H8) =20 /* - *** Vector Fixed-Point Arithmetic Instructions + * Vector Fixed-Point Arithmetic Instructions */ =20 /* Vector Single-Width Saturating Add and Subtract */ @@ -2988,7 +2996,7 @@ GEN_VEXT_VX_RM(vnclipu_wx_h, 2) GEN_VEXT_VX_RM(vnclipu_wx_w, 4) =20 /* - *** Vector Float Point Arithmetic Instructions + * Vector Float Point Arithmetic Instructions */ /* Vector Single-Width Floating-Point Add/Subtract Instructions */ #define OPFVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ @@ -4171,8 +4179,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, voi= d *vs2, \ DO_OP(s2, s1, &env->fp_status)); \ } \ env->vstart =3D 0; \ - /* mask destination register are always tail-agnostic */ \ - /* set tail elements to 1s */ \ + /* + * mask destination register are always tail-agnostic + * set tail elements to 1s + */ \ if (vta_all_1s) { \ for (; i < total_elems; i++) { \ vext_set_elem_mask(vd, i, 1); \ @@ -4208,8 +4218,10 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, v= oid *vs2, \ DO_OP(s2, (ETYPE)s1, &env->fp_status)); \ } \ env->vstart =3D 0; \ - /* mask destination register are always tail-agnostic */ \ - /* set tail elements to 1s */ \ + /* + * mask destination register are always tail-agnostic + * set tail elements to 1s + */ \ if (vta_all_1s) { \ for (; i < total_elems; i++) { \ vext_set_elem_mask(vd, i, 1); \ @@ -4472,7 +4484,9 @@ GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8) #define WOP_UU_B uint16_t, uint8_t, uint8_t #define WOP_UU_H uint32_t, uint16_t, uint16_t #define WOP_UU_W uint64_t, uint32_t, uint32_t -/* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned inte= ger.*/ +/* + * vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned inte= ger. + */ RVVCALL(OPFVV1, vfwcvt_xu_f_v_h, WOP_UU_H, H4, H2, float16_to_uint32) RVVCALL(OPFVV1, vfwcvt_xu_f_v_w, WOP_UU_W, H8, H4, float32_to_uint64) GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h, 4) @@ -4559,7 +4573,7 @@ GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2) GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4) =20 /* - *** Vector Reduction Operations + * Vector Reduction Operations */ /* Vector Single-Width Integer Reduction Instructions */ #define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP) \ @@ -4713,7 +4727,7 @@ GEN_VEXT_FRED(vfwredosum_vs_h, uint32_t, uint16_t, H4= , H2, fwadd16) GEN_VEXT_FRED(vfwredosum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32) =20 /* - *** Vector Mask Operations + * Vector Mask Operations */ /* Vector Mask-Register Logical Instructions */ #define GEN_VEXT_MASK_VV(NAME, OP) \ @@ -4733,10 +4747,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ vext_set_elem_mask(vd, i, OP(b, a)); \ } \ env->vstart =3D 0; \ - /* mask destination register are always tail- \ - * agnostic \ + /* + * mask destination register are always tail-agnostic + * set tail elements to 1s */ \ - /* set tail elements to 1s */ \ if (vta_all_1s) { \ for (; i < total_elems; i++) { \ vext_set_elem_mask(vd, i, 1); \ @@ -4779,7 +4793,7 @@ target_ulong HELPER(vcpop_m)(void *v0, void *vs2, CPU= RISCVState *env, return cnt; } =20 -/* vfirst find-first-set mask bit*/ +/* vfirst find-first-set mask bit */ target_ulong HELPER(vfirst_m)(void *v0, void *vs2, CPURISCVState *env, uint32_t desc) { @@ -4844,8 +4858,10 @@ static void vmsetm(void *vd, void *v0, void *vs2, CP= URISCVState *env, } } env->vstart =3D 0; - /* mask destination register are always tail-agnostic */ - /* set tail elements to 1s */ + /* + * mask destination register are always tail-agnostic + * set tail elements to 1s + */ if (vta_all_1s) { for (; i < total_elems; i++) { vext_set_elem_mask(vd, i, 1); @@ -4937,7 +4953,7 @@ GEN_VEXT_VID_V(vid_v_w, uint32_t, H4) GEN_VEXT_VID_V(vid_v_d, uint64_t, H8) =20 /* - *** Vector Permutation Instructions + * Vector Permutation Instructions */ =20 /* Vector Slide Instructions */ diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 8e43bfc07c..ca3c4c1a3d 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3136,9 +3136,11 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr = *a) return false; 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Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-Id: <20230405085813.40643-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 4 +- target/riscv/cpu.c | 3 +- target/riscv/cpu_helper.c | 3 +- target/riscv/csr.c | 38 ++++++++++-------- target/riscv/debug.c | 11 +++--- target/riscv/gdbstub.c | 3 +- target/riscv/pmp.c | 6 ++- target/riscv/pmu.c | 3 +- target/riscv/vector_helper.c | 76 ++++++++++++++++++++++++------------ 9 files changed, 91 insertions(+), 56 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5018a3b1b2..cbf3de2708 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -591,8 +591,8 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, boo= l enable); bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, = int mmu_idx, - uintptr_t retaddr); + MMUAccessType access_type, + int mmu_idx, uintptr_t reta= ddr); bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2e45b1f076..cb68916fce 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1700,7 +1700,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) device_class_set_props(dc, riscv_cpu_properties); } =20 -static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_st= r_len) +static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, + int max_str_len) { char *old =3D *isa_str; char *new =3D *isa_str; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 445ffe691a..2310c7905f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1121,7 +1121,8 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, cs->exception_index =3D RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAUL= T; } else { cs->exception_index =3D page_fault_exceptions ? - RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_= FAULT; + RISCV_EXCP_STORE_PAGE_FAULT : + RISCV_EXCP_STORE_AMO_ACCESS_FAULT; } break; default: diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 76755ee128..e0b871f6dc 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1137,7 +1137,8 @@ static const target_ulong sstatus_v1_10_mask =3D SSTA= TUS_SIE | SSTATUS_SPIE | static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MIP_= UEIP | SIP_LCOFIP; static const target_ulong hip_writable_mask =3D MIP_VSSIP; -static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | M= IP_VSEIP; +static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | + MIP_VSEIP; static const target_ulong vsip_writable_mask =3D MIP_VSSIP; =20 const bool valid_vm_1_10_32[16] =3D { @@ -1298,7 +1299,8 @@ static RISCVException write_mstatush(CPURISCVState *e= nv, int csrno, static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno, Int128 *val) { - *val =3D int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->ms= tatus)); + *val =3D int128_make128(env->mstatus, add_status_sd(MXL_RV128, + env->mstatus)); return RISCV_EXCP_NONE; } =20 @@ -2823,7 +2825,8 @@ static RISCVException write_hstatus(CPURISCVState *en= v, int csrno, { env->hstatus =3D val; if (riscv_cpu_mxl(env) !=3D MXL_RV32 && get_field(val, HSTATUS_VSXL) != =3D 2) { - qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN optio= ns."); + qemu_log_mask(LOG_UNIMP, + "QEMU does not support mixed HSXLEN options."); } if (get_field(val, HSTATUS_VSBE) !=3D 0) { qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.= "); @@ -3490,9 +3493,9 @@ static RISCVException write_mmte(CPURISCVState *env, = int csrno, target_ulong wpri_val =3D val & MMTE_MASK; =20 if (val !=3D wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT= _lx "\n", - "MMTE: WPRI violation written 0x", val, - "vs expected 0x", wpri_val); + qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" + TARGET_FMT_lx "\n", "MMTE: WPRI violation written 0x= ", + val, "vs expected 0x", wpri_val); } /* for machine mode pm.current is hardwired to 1 */ wpri_val |=3D MMTE_M_PM_CURRENT; @@ -3521,9 +3524,9 @@ static RISCVException write_smte(CPURISCVState *env, = int csrno, target_ulong wpri_val =3D val & SMTE_MASK; =20 if (val !=3D wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT= _lx "\n", - "SMTE: WPRI violation written 0x", val, - "vs expected 0x", wpri_val); + qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" + TARGET_FMT_lx "\n", "SMTE: WPRI violation written 0x= ", + val, "vs expected 0x", wpri_val); } =20 /* if pm.current=3D=3D0 we can't modify current PM CSRs */ @@ -3549,9 +3552,9 @@ static RISCVException write_umte(CPURISCVState *env, = int csrno, target_ulong wpri_val =3D val & UMTE_MASK; =20 if (val !=3D wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT= _lx "\n", - "UMTE: WPRI violation written 0x", val, - "vs expected 0x", wpri_val); + qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" + TARGET_FMT_lx "\n", "UMTE: WPRI violation written 0x= ", + val, "vs expected 0x", wpri_val); } =20 if (check_pm_current_disabled(env, csrno)) { @@ -3941,7 +3944,8 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, i= nt csrno, * Fall back to 64-bit version for now, if the 128-bit alternative isn= 't * at all defined. * Note, some CSRs don't need to extend to MXLEN (64 upper bits non - * significant), for those, this fallback is correctly handling the ac= cesses + * significant), for those, this fallback is correctly handling the + * accesses */ target_ulong old_value; ret =3D riscv_csrrw_do64(env, csrno, &old_value, @@ -4154,11 +4158,11 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =20 /* Supervisor Trap Setup */ [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus, - NULL, read_sstatus_i128 = }, - [CSR_SIE] =3D { "sie", smode, NULL, NULL, rmw_sie = }, - [CSR_STVEC] =3D { "stvec", smode, read_stvec, write_stv= ec }, + NULL, read_sstatus_i128 = }, + [CSR_SIE] =3D { "sie", smode, NULL, NULL, rmw_sie = }, + [CSR_STVEC] =3D { "stvec", smode, read_stvec, write_stv= ec }, [CSR_SCOUNTEREN] =3D { "scounteren", smode, read_scounteren, - write_scounteren = }, + write_scounteren = }, =20 /* Supervisor Trap Handling */ [CSR_SSCRATCH] =3D { "sscratch", smode, read_sscratch, write_sscratch, diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 1f7aed23c9..75ee1c4971 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -282,8 +282,8 @@ static target_ulong type2_mcontrol_validate(CPURISCVSta= te *env, /* validate size encoding */ size =3D type2_breakpoint_size(env, ctrl); if (access_size[size] =3D=3D -1) { - qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using S= IZE_ANY\n", - size); + qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using " + "SIZE_ANY\n", size); } else { val |=3D (ctrl & TYPE2_SIZELO); if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { @@ -411,8 +411,8 @@ static target_ulong type6_mcontrol6_validate(CPURISCVSt= ate *env, /* validate size encoding */ size =3D extract32(ctrl, 16, 4); if (access_size[size] =3D=3D -1) { - qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using S= IZE_ANY\n", - size); + qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using " + "SIZE_ANY\n", size); } else { val |=3D (ctrl & TYPE6_SIZE); } @@ -696,7 +696,8 @@ target_ulong tdata_csr_read(CPURISCVState *env, int tda= ta_index) int trigger_type; switch (tdata_index) { case TDATA1: - trigger_type =3D extract_trigger_type(env, env->tdata1[env->trigge= r_cur]); + trigger_type =3D extract_trigger_type(env, + env->tdata1[env->trigger_cur]); if ((trigger_type =3D=3D TRIGGER_TYPE_INST_CNT) && icount_enabled(= )) { return deposit64(env->tdata1[env->trigger_cur], 10, 14, itrigger_get_adjust_count(env)); diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 692bbb64f6..fa537aed74 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -321,7 +321,8 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs) } if (env->misa_ext & RVV) { int base_reg =3D cs->gdb_num_regs; - gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_v= ector, + gdb_register_coprocessor(cs, riscv_gdb_get_vector, + riscv_gdb_set_vector, ricsv_gen_dynamic_vector_xml(cs, base_reg= ), "riscv-vector.xml", 0); } diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 6ab2ae81c7..1f5aca42e8 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -129,7 +129,8 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t = pmp_index, uint8_t val) } } =20 -static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulon= g *ea) +static void pmp_decode_napot(target_ulong a, target_ulong *sa, + target_ulong *ea) { /* * aaaa...aaa0 8-byte NAPOT range @@ -217,7 +218,8 @@ static void pmp_update_rule(CPURISCVState *env, uint32_= t pmp_index) pmp_update_rule_nums(env); } =20 -static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong= addr) +static int pmp_is_in_range(CPURISCVState *env, int pmp_index, + target_ulong addr) { int result =3D 0; =20 diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 48ad60be2b..db06b3882f 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -419,7 +419,8 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t = value, uint32_t ctr_idx) } else { return -1; } - overflow_at =3D (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + over= flow_ns; + overflow_at =3D (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + overflow_ns; =20 if (overflow_at > INT64_MAX) { overflow_left +=3D overflow_at - INT64_MAX; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 81ac85b7d5..f4d0438988 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -382,8 +382,8 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState= *env, uint32_t desc, } =20 /* - * masked unit-stride load and store operation will be a special case of s= tride, - * stride =3D NF * sizeof (MTYPE) + * masked unit-stride load and store operation will be a special case of + * stride, stride =3D NF * sizeof (MTYPE) */ =20 #define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN) \ @@ -678,7 +678,8 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVSt= ate *env, uint32_t desc, /* load/store rest of elements of current segment pointed by vstar= t */ for (pos =3D off; pos < max_elems; pos++, env->vstart++) { target_ulong addr =3D base + ((pos + k * max_elems) << log2_es= z); - ldst_elem(env, adjust_addr(env, addr), pos + k * max_elems, vd= , ra); + ldst_elem(env, adjust_addr(env, addr), pos + k * max_elems, vd, + ra); } k++; } @@ -1306,7 +1307,9 @@ GEN_VEXT_SHIFT_VV(vsra_vv_h, uint16_t, int16_t, H2, H= 2, DO_SRL, 0xf) GEN_VEXT_SHIFT_VV(vsra_vv_w, uint32_t, int32_t, H4, H4, DO_SRL, 0x1f) GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f) =20 -/* generate the helpers for shift instructions with one vector and one sca= lar */ +/* + * generate the helpers for shift instructions with one vector and one sca= lar + */ #define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ void *vs2, CPURISCVState *env, \ @@ -2165,7 +2168,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ do_##NAME, ESZ); \ } =20 -static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a, uint= 8_t b) +static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a, + uint8_t b) { uint8_t res =3D a + b; if (res < a) { @@ -2309,7 +2313,8 @@ static inline int8_t sadd8(CPURISCVState *env, int vx= rm, int8_t a, int8_t b) return res; } =20 -static inline int16_t sadd16(CPURISCVState *env, int vxrm, int16_t a, int1= 6_t b) +static inline int16_t sadd16(CPURISCVState *env, int vxrm, int16_t a, + int16_t b) { int16_t res =3D a + b; if ((res ^ a) & (res ^ b) & INT16_MIN) { @@ -2319,7 +2324,8 @@ static inline int16_t sadd16(CPURISCVState *env, int = vxrm, int16_t a, int16_t b) return res; } =20 -static inline int32_t sadd32(CPURISCVState *env, int vxrm, int32_t a, int3= 2_t b) +static inline int32_t sadd32(CPURISCVState *env, int vxrm, int32_t a, + int32_t b) { int32_t res =3D a + b; if ((res ^ a) & (res ^ b) & INT32_MIN) { @@ -2329,7 +2335,8 @@ static inline int32_t sadd32(CPURISCVState *env, int = vxrm, int32_t a, int32_t b) return res; } =20 -static inline int64_t sadd64(CPURISCVState *env, int vxrm, int64_t a, int6= 4_t b) +static inline int64_t sadd64(CPURISCVState *env, int vxrm, int64_t a, + int64_t b) { int64_t res =3D a + b; if ((res ^ a) & (res ^ b) & INT64_MIN) { @@ -2357,7 +2364,8 @@ GEN_VEXT_VX_RM(vsadd_vx_h, 2) GEN_VEXT_VX_RM(vsadd_vx_w, 4) GEN_VEXT_VX_RM(vsadd_vx_d, 8) =20 -static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, uint= 8_t b) +static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, + uint8_t b) { uint8_t res =3D a - b; if (res > a) { @@ -2428,7 +2436,8 @@ static inline int8_t ssub8(CPURISCVState *env, int vx= rm, int8_t a, int8_t b) return res; } =20 -static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, int1= 6_t b) +static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, + int16_t b) { int16_t res =3D a - b; if ((res ^ a) & (a ^ b) & INT16_MIN) { @@ -2438,7 +2447,8 @@ static inline int16_t ssub16(CPURISCVState *env, int = vxrm, int16_t a, int16_t b) return res; } =20 -static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, int3= 2_t b) +static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, + int32_t b) { int32_t res =3D a - b; if ((res ^ a) & (a ^ b) & INT32_MIN) { @@ -2448,7 +2458,8 @@ static inline int32_t ssub32(CPURISCVState *env, int = vxrm, int32_t a, int32_t b) return res; } =20 -static inline int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a, int6= 4_t b) +static inline int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a, + int64_t b) { int64_t res =3D a - b; if ((res ^ a) & (a ^ b) & INT64_MIN) { @@ -2504,7 +2515,8 @@ static inline uint8_t get_round(int vxrm, uint64_t v,= uint8_t shift) return 0; /* round-down (truncate) */ } =20 -static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a, int3= 2_t b) +static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a, + int32_t b) { int64_t res =3D (int64_t)a + b; uint8_t round =3D get_round(vxrm, res, 1); @@ -2512,7 +2524,8 @@ static inline int32_t aadd32(CPURISCVState *env, int = vxrm, int32_t a, int32_t b) return (res >> 1) + round; } =20 -static inline int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a, int6= 4_t b) +static inline int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a, + int64_t b) { int64_t res =3D a + b; uint8_t round =3D get_round(vxrm, res, 1); @@ -2577,7 +2590,8 @@ GEN_VEXT_VX_RM(vaaddu_vx_h, 2) GEN_VEXT_VX_RM(vaaddu_vx_w, 4) GEN_VEXT_VX_RM(vaaddu_vx_d, 8) =20 -static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int3= 2_t b) +static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, + int32_t b) { int64_t res =3D (int64_t)a - b; uint8_t round =3D get_round(vxrm, res, 1); @@ -2585,7 +2599,8 @@ static inline int32_t asub32(CPURISCVState *env, int = vxrm, int32_t a, int32_t b) return (res >> 1) + round; } =20 -static inline int64_t asub64(CPURISCVState *env, int vxrm, int64_t a, int6= 4_t b) +static inline int64_t asub64(CPURISCVState *env, int vxrm, int64_t a, + int64_t b) { int64_t res =3D (int64_t)a - b; uint8_t round =3D get_round(vxrm, res, 1); @@ -4498,7 +4513,9 @@ RVVCALL(OPFVV1, vfwcvt_x_f_v_w, WOP_UU_W, H8, H4, flo= at32_to_int64) GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 4) GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 8) =20 -/* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width fl= oat */ +/* + * vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width fl= oat. + */ RVVCALL(OPFVV1, vfwcvt_f_xu_v_b, WOP_UU_B, H2, H1, uint8_to_float16) RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32) RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64) @@ -4515,8 +4532,7 @@ GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 4) GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 8) =20 /* - * vfwcvt.f.f.v vd, vs2, vm - * Convert single-width float to double-width float. + * vfwcvt.f.f.v vd, vs2, vm # Convert single-width float to double-width f= loat. */ static uint32_t vfwcvtffv16(uint16_t a, float_status *s) { @@ -4549,7 +4565,9 @@ GEN_VEXT_V_ENV(vfncvt_x_f_w_b, 1) GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2) GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4) =20 -/* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to fl= oat */ +/* + * vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to fl= oat. + */ RVVCALL(OPFVV1, vfncvt_f_xu_w_h, NOP_UU_H, H2, H4, uint32_to_float16) RVVCALL(OPFVV1, vfncvt_f_xu_w_w, NOP_UU_W, H4, H8, uint64_to_float32) GEN_VEXT_V_ENV(vfncvt_f_xu_w_h, 2) @@ -4699,14 +4717,20 @@ GEN_VEXT_FRED(vfredosum_vs_w, uint32_t, uint32_t, H= 4, H4, float32_add) GEN_VEXT_FRED(vfredosum_vs_d, uint64_t, uint64_t, H8, H8, float64_add) =20 /* Maximum value */ -GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maximum_n= umber) -GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maximum_n= umber) -GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maximum_n= umber) +GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, + float16_maximum_number) +GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, + float32_maximum_number) +GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, + float64_maximum_number) =20 /* Minimum value */ -GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minimum_n= umber) -GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minimum_n= umber) -GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minimum_n= umber) +GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, + float16_minimum_number) +GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, + float32_minimum_number) +GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, + float64_minimum_number) =20 /* Vector Widening Floating-Point Add Instructions */ static uint32_t fwadd16(uint32_t a, uint16_t b, float_status *s) --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Recgonize the signature section between begin_signature and end_signature s= ymbols when loading elf of ACT tests. Then dump signature data in signature sectio= n just before the ACT tests exit. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-Id: <20230405095720.75848-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- include/hw/char/riscv_htif.h | 3 +++ hw/char/riscv_htif.c | 44 +++++++++++++++++++++++++++++++++++- hw/riscv/spike.c | 13 +++++++++++ 3 files changed, 59 insertions(+), 1 deletion(-) diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h index 5958c5b986..df493fdf6b 100644 --- a/include/hw/char/riscv_htif.h +++ b/include/hw/char/riscv_htif.h @@ -40,6 +40,9 @@ typedef struct HTIFState { uint64_t pending_read; } HTIFState; =20 +extern const char *sig_file; +extern uint8_t line_size; + /* HTIF symbol callback */ void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_va= lue, uint64_t st_size); diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index 098de50e35..37d3ccc76b 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -29,6 +29,8 @@ #include "chardev/char-fe.h" #include "qemu/timer.h" #include "qemu/error-report.h" +#include "exec/address-spaces.h" +#include "sysemu/dma.h" =20 #define RISCV_DEBUG_HTIF 0 #define HTIF_DEBUG(fmt, ...) = \ @@ -51,7 +53,10 @@ /* PK system call number */ #define PK_SYS_WRITE 64 =20 -static uint64_t fromhost_addr, tohost_addr; +const char *sig_file; +uint8_t line_size =3D 16; + +static uint64_t fromhost_addr, tohost_addr, begin_sig_addr, end_sig_addr; =20 void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_va= lue, uint64_t st_size) @@ -68,6 +73,10 @@ void htif_symbol_callback(const char *st_name, int st_in= fo, uint64_t st_value, error_report("HTIF tohost must be 8 bytes"); exit(1); } + } else if (strcmp("begin_signature", st_name) =3D=3D 0) { + begin_sig_addr =3D st_value; + } else if (strcmp("end_signature", st_name) =3D=3D 0) { + end_sig_addr =3D st_value; } } =20 @@ -163,6 +172,39 @@ static void htif_handle_tohost_write(HTIFState *s, uin= t64_t val_written) if (payload & 0x1) { /* exit code */ int exit_code =3D payload >> 1; + + /* + * Dump signature data if sig_file is specified and + * begin/end_signature symbols exist. + */ + if (sig_file && begin_sig_addr && end_sig_addr) { + uint64_t sig_len =3D end_sig_addr - begin_sig_addr; + char *sig_data =3D g_malloc(sig_len); + dma_memory_read(&address_space_memory, begin_sig_addr, + sig_data, sig_len, MEMTXATTRS_UNSPECIF= IED); + FILE *signature =3D fopen(sig_file, "w"); + if (signature =3D=3D NULL) { + error_report("Unable to open %s with error %s", + sig_file, strerror(errno)); + exit(1); + } + + for (int i =3D 0; i < sig_len; i +=3D line_size) { + for (int j =3D line_size; j > 0; j--) { + if (i + j <=3D sig_len) { + fprintf(signature, "%02x", + sig_data[i + j - 1] & 0xff); + } else { + fprintf(signature, "%02x", 0); + } + } + fprintf(signature, "\n"); + } + + fclose(signature); + g_free(sig_data); + } + exit(exit_code); } else { uint64_t syscall[8]; diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index a584d5b3a2..2c5546560a 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -332,6 +332,11 @@ static void spike_board_init(MachineState *machine) htif_custom_base); } =20 +static void spike_set_signature(Object *obj, const char *val, Error **errp) +{ + sig_file =3D g_strdup(val); +} + static void spike_machine_instance_init(Object *obj) { } @@ -350,6 +355,14 @@ static void spike_machine_class_init(ObjectClass *oc, = void *data) mc->get_default_cpu_node_id =3D riscv_numa_get_default_cpu_node_id; mc->numa_mem_supported =3D true; mc->default_ram_id =3D "riscv.spike.ram"; + object_class_property_add_str(oc, "signature", NULL, spike_set_signatu= re); + object_class_property_set_description(oc, "signature", + "File to write ACT test signatur= e"); + object_class_property_add_uint8_ptr(oc, "signature-granularity", + &line_size, OBJ_PROP_FLAG_WRITE); + object_class_property_set_description(oc, "signature-granularity", + "Size of each line in ACT signat= ure " + "file"); } =20 static const TypeInfo spike_machine_typeinfo =3D { --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249475; cv=none; d=zohomail.com; s=zohoarc; b=QF8qlqT6c0Z509gwjNbgCUTBkUI0Rg95lSAIKpw6R8dLzTNFDj9IqyVOw9ElE+LbMW8pobxCtK1JFCd94yCfojHOf432Pn0GyRMP4hQCrkFmTLRy9O5maVwEUyHwZ7XASZkRxSS6o1gg1qcX78LzLC/Wm+5muCSpCrYwZeqQNrs= ARC-Message-Signature: i=1; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.05.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:05:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248712; x=1685840712; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8kYPc3zJuRBU7p7Cv5AbI6Y/Hrunw54E5HI30VRK+2Y=; b=IF++k7cogYoTl11CLghfOkYPYUT1ws71FfU/YDWieSTsW/pDsf9mzkDDoinuS2uMfK 4Fpx/oyYGJZMRpZ3Ty+VfaYXHOrUCxzR3eyMuE8TQ1GJ1f+ku3cVd817ivKGUgnsrxjK eN1XLDqAVcp3ioQTDvX4UvQOW6oCx01gd6oycLmRuhzJcaQuCZ4rmx/ZLnT20RHQYs6r Nbdphz6snpiJJSGzd1VvzRuX01c3EvEtvq+UjMNngS6biZyyKHjx9MhawEvesbcR6no8 FlSVKUUekGsBieLaSZd68OCRoJtR+tCMzx/W3ksQ6XfGywMpWW4hiJNSaNfmI45Xjhbf SibA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248712; x=1685840712; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8kYPc3zJuRBU7p7Cv5AbI6Y/Hrunw54E5HI30VRK+2Y=; b=d+BNPpv+g2Pc2jbiFKzmTejVM+VyCYZ2IBlBmSmwHBTrCMeAVF1zRjB0HRu8WVAhrm 4IBjEIHxVzLjF6kRMPQGCsW47/std1Jeoehx5i7JLSJtvFzWhe2nl7Ad2qiJvfCbHMFv gnZHJXLWdmutShW4rEydTka9/Q/bKKg60EXmp3Osto0YJtf5ilyXzCWD3/2w/ngakdsw C0YgqEqWf5wZfppFRhROPSIpLvkb86W3EUUUWjbkIiL4tdSZI5H7eHL4vvrj7yyR2Myt Sv3gjQWFCfWOLO/yfK5iIPR8tebVkNwsjKaKPSzhJVbJe7rNQxL23v7Vnq64yma+Gh9c nICg== X-Gm-Message-State: AC+VfDxdF3Tqey6xZ0ozi5ELHlDIlTZbB46MBodIFnqLUvGcNIdOaqao e6SUlqqiRbojZFHNQm1M5AGp0rcspcjDlw== X-Google-Smtp-Source: ACHHUZ5MNwzSaAzROaKXzn8/h85Izgwju2j57NElKFZ4bYPY1ErB/xQEeCJzY/4s4dKioQ3H/ablZQ== X-Received: by 2002:a17:902:b706:b0:1a8:1c9a:f68 with SMTP id d6-20020a170902b70600b001a81c9a0f68mr5511480pls.36.1683248712523; Thu, 04 May 2023 18:05:12 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 33/89] target/riscv: sync env->misa_ext* with cpu->cfg in realize() Date: Fri, 5 May 2023 11:01:45 +1000 Message-Id: <20230505010241.21812-34-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249476790100004 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza When riscv_cpu_realize() starts we're guaranteed to have cpu->cfg.ext_N properties updated. The same can't be said about env->misa_ext*, since the user might enable/disable MISA extensions in the command line, and env->misa_ext* won't caught these changes. The current solution is to sync everything at the end of validate_set_extensions(), checking every cpu->cfg.ext_N value to do a set_misa() in the end. The last change we're making in the MISA cfg flags are in the G extension logic, enabling IMAFG if cpu->cfg_ext.g is enabled. Otherwise we're not making any changes in MISA bits ever since realize() starts. There's no reason to postpone misa_ext updates until the end of the validation. Let's do it earlier, during realize(), in a new helper called riscv_cpu_sync_misa_cfg(). If cpu->cfg.ext_g is enabled, do it again by updating env->misa_ext* directly. This is a pre-requisite to allow riscv_cpu_validate_set_extensions() to use riscv_has_ext() instead of cpu->cfg.ext_N to validate the MISA extensions, which is our end goal here. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 94 +++++++++++++++++++++++++++------------------- 1 file changed, 56 insertions(+), 38 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cb68916fce..66de3bb33f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -811,12 +811,11 @@ static void riscv_cpu_disas_set_info(CPUState *s, dis= assemble_info *info) =20 /* * Check consistency between chosen extensions while setting - * cpu->cfg accordingly, doing a set_misa() in the end. + * cpu->cfg accordingly. */ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; - uint32_t ext =3D 0; =20 /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && @@ -831,6 +830,9 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) cpu->cfg.ext_d =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; + + env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; + env->misa_ext_mask =3D env->misa_ext; } =20 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { @@ -1022,39 +1024,8 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) cpu->cfg.ext_zksh =3D true; } =20 - if (cpu->cfg.ext_i) { - ext |=3D RVI; - } - if (cpu->cfg.ext_e) { - ext |=3D RVE; - } - if (cpu->cfg.ext_m) { - ext |=3D RVM; - } - if (cpu->cfg.ext_a) { - ext |=3D RVA; - } - if (cpu->cfg.ext_f) { - ext |=3D RVF; - } - if (cpu->cfg.ext_d) { - ext |=3D RVD; - } - if (cpu->cfg.ext_c) { - ext |=3D RVC; - } - if (cpu->cfg.ext_s) { - ext |=3D RVS; - } - if (cpu->cfg.ext_u) { - ext |=3D RVU; - } - if (cpu->cfg.ext_h) { - ext |=3D RVH; - } if (cpu->cfg.ext_v) { int vext_version =3D VEXT_VERSION_1_00_0; - ext |=3D RVV; if (!is_power_of_2(cpu->cfg.vlen)) { error_setg(errp, "Vector extension VLEN must be power of 2"); @@ -1092,11 +1063,6 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) } set_vext_version(env, vext_version); } - if (cpu->cfg.ext_j) { - ext |=3D RVJ; - } - - set_misa(env, env->misa_mxl, ext); } =20 #ifndef CONFIG_USER_ONLY @@ -1181,6 +1147,50 @@ static void riscv_cpu_finalize_features(RISCVCPU *cp= u, Error **errp) #endif } =20 +static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) +{ + uint32_t ext =3D 0; + + if (riscv_cpu_cfg(env)->ext_i) { + ext |=3D RVI; + } + if (riscv_cpu_cfg(env)->ext_e) { + ext |=3D RVE; + } + if (riscv_cpu_cfg(env)->ext_m) { + ext |=3D RVM; + } + if (riscv_cpu_cfg(env)->ext_a) { + ext |=3D RVA; + } + if (riscv_cpu_cfg(env)->ext_f) { + ext |=3D RVF; + } + if (riscv_cpu_cfg(env)->ext_d) { + ext |=3D RVD; + } + if (riscv_cpu_cfg(env)->ext_c) { + ext |=3D RVC; + } + if (riscv_cpu_cfg(env)->ext_s) { + ext |=3D RVS; + } + if (riscv_cpu_cfg(env)->ext_u) { + ext |=3D RVU; + } + if (riscv_cpu_cfg(env)->ext_h) { + ext |=3D RVH; + } + if (riscv_cpu_cfg(env)->ext_v) { + ext |=3D RVV; + } + if (riscv_cpu_cfg(env)->ext_j) { + ext |=3D RVJ; + } + + env->misa_ext =3D env->misa_ext_mask =3D ext; +} + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -1216,6 +1226,14 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) set_priv_version(env, priv_version); } =20 + /* + * We can't be sure of whether we set defaults during cpu_init() + * or whether the user enabled/disabled some bits via cpu->cfg + * flags. Sync env->misa_ext with cpu->cfg now to allow us to + * use just env->misa_ext later. + */ + riscv_cpu_sync_misa_cfg(env); + /* Force disable extensions if priv spec version does not match */ for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248773; cv=none; d=zohomail.com; s=zohoarc; b=Q0Fl+F84+o3psl/naOlP/UxycAob9FXJBL82UkFcf/RGrm3btxEUNCrvu3KLypzaslRs07R5FtwIUOXGekPEtIjwAW6QCnCZGcy1qF1QNmdn7Iy5jpLF0/VvyThldvu1380HuWoUwJmld/hIaBmBcZG5KbcTHbmxfraEks7TXr0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248773; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8zwoHgB2wM+/422ctK/G+FfLoKTWp+g/CF36MrgNQJk=; b=FKDqQ2gUozorkiNU6d1GBappwKopdb5uNUzNweZdS8dLm0Qz+NVwaKQRVyvYS3k2Qm9L6JJf1L3XcN1E/vyC5dIcF1vi94GZNzFictWR3RpIzrd2+fBntlclu9UNEXBDta3H+90qFdrdgvp7n3ZXlKA6E97CCnOslDP0ptcx70M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683248773812917.2874804204104; Thu, 4 May 2023 18:06:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujsw-00079x-A1; Thu, 04 May 2023 21:05:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujsu-0006xT-IA for qemu-devel@nongnu.org; Thu, 04 May 2023 21:05:20 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujsr-0007N5-NK for qemu-devel@nongnu.org; Thu, 04 May 2023 21:05:20 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1aaebed5bd6so8166305ad.1 for ; Thu, 04 May 2023 18:05:17 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.05.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:05:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248716; x=1685840716; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8zwoHgB2wM+/422ctK/G+FfLoKTWp+g/CF36MrgNQJk=; b=EOlv1h0FSZwtb2D7+ZagN/LmISs7OszpTOXSpi4ROaeh6euy5h78TmT2TtDeOHEBJp CyuSM2YFwTUdBMuXq/efC0PkLdGW16OIAWFQE/6UtmkkKPjBCNF2hWN7He4vDDS7GLzZ Ie9++owDRkNuEcPYXzy0lk6TNfFy18vFAq1JwWXgLaNLiuCjNMl+i8Wg/lsP7z85k5zg fJjugp4iYE6fQWzbbFheMUloyrGVS72h5Pl4u9qBx2GvlH3BDCSl0r0LPaksjjZN5s0J 1AXG1pERQ9FNxqqtHAxnpyA8w+efRyYDx9HQr9VYwq2nf3h8+FDzA5AX2zwXMOL/WadX q2WA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248716; x=1685840716; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8zwoHgB2wM+/422ctK/G+FfLoKTWp+g/CF36MrgNQJk=; b=Wf7do0n/g1n1n2uKTBHaCYCXWrbIzE4+ncB+HBcfjtyHfr1sAnP0E1L/njIjcJuJQX t6z3FkuPFnPmTHhRh1+0aHgzsTCGa/LFFD9Kyrbno8S4HoAT2bSFncu3mfDdKb7Irvmb WMon66dwkSOCcbngUK8M+jSBoXXQ2lcb7eklX5Efej1y1hyAoFnv49e0QlJ0eT+5KiRM cy9Pc+MKB+WcjTJC9cOPASRe8C5Yxic6OnJQYd6uq2LjmhEMTskxd8N7i+1alqDf1/bj JMKrafUTmPX/l/ienhbvTYnWo3/Q0fHdWHVdQsl5vFfQIucXrlK10YjWKk97kwEc4/WN bORw== X-Gm-Message-State: AC+VfDwzKcNGgoMonX0eMdBzkSXbjq720oOvXo4Qpod+U1ImwLmcP9zu qRPu3E3v6hDm27dOU6sZ9s+FWNXrcZ8eiQ== X-Google-Smtp-Source: ACHHUZ4T9ypiAT119p9avCg5GIuxn3b++tdd8AU3yEkqMyKmuw1J4qFeHbkJ89g6Db7fpWTHbSw6HQ== X-Received: by 2002:a17:902:a716:b0:1a9:80a0:47fc with SMTP id w22-20020a170902a71600b001a980a047fcmr4861751plq.17.1683248715952; Thu, 04 May 2023 18:05:15 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 34/89] target/riscv: remove MISA properties from isa_edata_arr[] Date: Fri, 5 May 2023 11:01:46 +1000 Message-Id: <20230505010241.21812-35-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248774036100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza The code that disables extensions if there's a priv version mismatch uses cpu->cfg.ext_N properties to do its job. We're aiming to not rely on cpu->cfg.ext_N props for MISA bits. Split the MISA related verifications in a new function, removing it from isa_edata_arr[]. We're also erroring it out instead of disabling, making the cpu_init() function responsible for running an adequate priv spec for the MISA extensions it wants to use. Note that the RVV verification is being ignored since we're always have at least PRIV_VERSION_1_10_0. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 66de3bb33f..ed8f36c649 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -72,10 +72,11 @@ struct isa_ext_data { * 4. Non-standard extensions (starts with 'X') must be listed after all * standard extensions. They must be separated from other multi-letter * extensions by an underscore. + * + * Single letter extensions are checked in riscv_cpu_validate_misa_priv() + * instead. */ static const struct isa_ext_data isa_edata_arr[] =3D { - ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), - ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v), ISA_EXT_DATA_ENTRY(zicbom, true, PRIV_VERSION_1_12_0, ext_icbom), ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz), ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond), @@ -1191,6 +1192,14 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *e= nv) env->misa_ext =3D env->misa_ext_mask =3D ext; } =20 +static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) +{ + if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { + error_setg(errp, "H extension requires priv spec 1.12.0"); + return; + } +} + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -1234,6 +1243,12 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) */ riscv_cpu_sync_misa_cfg(env); =20 + riscv_cpu_validate_misa_priv(env, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + /* Force disable extensions if priv spec version does not match */ for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248816; cv=none; d=zohomail.com; s=zohoarc; b=Gaw1jMnvNmTG38lrBnVuKr8waVHPxVizXBIe8GDiVtgvrt6vMKm7tDTkKgMM6cn45XU6M6KB2R9m6+zKMQI+dAdw1AWdfcavhnXhB1zKYFGZI8iPl/leOlce9NpXsSMN7nt/06064btS5v+P+zecdtSWZVtq3BTvc6IxecXWqCQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248816; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=duqrjjIQV/MCrH+vSirPVU02qGF+Zve4B4fYCslucG8=; b=YGpv9ut3HSCYRYMhoCazsWME+Fla1sVZ3+0kDAMxtj7E6FbPWHqpb8oinIjz8upUYQJDQGS3BQ4Op2+8d5RSzLiVzRzu4NT93mi1W2kG1bBmATOf1iLjmRyYcbf3zQ1p+BhD8DCfKPMSsYpUdvrQcynKgcH5xGgrcrNMkN/oYJc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683248816683120.6579826388969; Thu, 4 May 2023 18:06:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujt0-0007YR-Ok; Thu, 04 May 2023 21:05:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujsy-0007Od-EM for qemu-devel@nongnu.org; Thu, 04 May 2023 21:05:24 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujsv-0007Qz-32 for qemu-devel@nongnu.org; Thu, 04 May 2023 21:05:24 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1ab0c697c2bso10730945ad.1 for ; Thu, 04 May 2023 18:05:20 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.05.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:05:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248719; x=1685840719; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=duqrjjIQV/MCrH+vSirPVU02qGF+Zve4B4fYCslucG8=; b=DIUY9Wq2lBrtUsqJ997YWxcMddyfePWs/gWg3XG69QOFixEsyCdC2SNbs5TbwhxTbX M7gSN5KCcM59vu3uXA4+sdSCsOO5cpRFZ3TEJ5n3njVnb3iZRbL4aQFZFluiDGCzmhhr FjK4qmfRhri6AbY6QH2r34PP89DpX7z/zoZTiH6yGTv++F/zRulJZGeD7uwB6rLqFsMw U8dTrHuEd0KG+joEoyAsrx6ThbaMnMYdAwpD8S6UOREGR+EQrHHfHDHp6KkD7GCdqpbQ 1u7gZWl5KMz+Bc+n+BiNuWqASduKZJRTtEljyOHfiaQbLpHimEHLQ/wDG/5hx+Dhbhj+ EipQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248719; x=1685840719; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=duqrjjIQV/MCrH+vSirPVU02qGF+Zve4B4fYCslucG8=; b=MIuLJYRrQ0trzY3FPZETTTIMTev24iLQ2anuWVj5Xf9nc2DboEpNDcrFf291ZeElgC E07v5o0BQFc7iwBNw+itViK1JjC6xz8LUNaE6lXlAiNcWaIUuXvTIlB93xLh7VNebfOB x5nOiZqBcPWb0zeUYQZC3L9SRcV2SFsNPTKfTJDNnrXXoM5PWFGosUaWrkYV9C7a1Ace HVOGv+FX+SQRMOyDJuDw40Xqf8kjrXxSPBfLgaNvpUnx99XQVebj/eEbmN0hr+Q98g/e GO15J2ZKSMXXb/wroESHUiuwYcW2NcnOBn5K9dET/OqiPDgkWtfoxu41rcEYtDzAcYke ve9Q== X-Gm-Message-State: AC+VfDwq9TtUMGPi/B5Q247kNBczSAYvUaum2RrkFNwRSpsbac2UjjBx ZcDXkXTWaNzuVvPPRWUIPq9ppH3dtuiFzQ== X-Google-Smtp-Source: ACHHUZ5pASjEWprqu9IltUTBgBBFwA0yj3ZfJENh7UkfzRAlH7PHL2inpJzSAK+01uo+9lYfb/Ee2w== X-Received: by 2002:a17:902:d315:b0:1ab:13bd:5f96 with SMTP id b21-20020a170902d31500b001ab13bd5f96mr5593529plc.4.1683248719245; Thu, 04 May 2023 18:05:19 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 35/89] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data Date: Fri, 5 May 2023 11:01:47 +1000 Message-Id: <20230505010241.21812-36-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248818470100005 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza We don't have MISA extensions in isa_edata_arr[] anymore. Remove the redundant 'multi_letter' field from isa_ext_data. Suggested-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 132 ++++++++++++++++++++++----------------------- 1 file changed, 65 insertions(+), 67 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ed8f36c649..fbf612292a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -48,13 +48,12 @@ static const char riscv_single_letter_exts[] =3D "IEMAF= DQCPVH"; =20 struct isa_ext_data { const char *name; - bool multi_letter; int min_version; int ext_enable_offset; }; =20 -#define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ - {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} +#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ + {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} =20 /* * Here are the ordering rules of extension naming defined by RISC-V @@ -77,68 +76,68 @@ struct isa_ext_data { * instead. */ static const struct isa_ext_data isa_edata_arr[] =3D { - ISA_EXT_DATA_ENTRY(zicbom, true, PRIV_VERSION_1_12_0, ext_icbom), - ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz), - ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond), - ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), - ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), - ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintp= ause), - ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), - ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh), - ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_11_0, ext_zfhmin), - ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), - ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), - ISA_EXT_DATA_ENTRY(zca, true, PRIV_VERSION_1_12_0, ext_zca), - ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb), - ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf), - ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd), - ISA_EXT_DATA_ENTRY(zce, true, PRIV_VERSION_1_12_0, ext_zce), - ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp), - ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt), - ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), - ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), - ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), - ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), - ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), - ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), - ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), - ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), - ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), - ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), - ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), - ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), - ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), - ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), - ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), - ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), - ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), - ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_10_0, ext_zve32f), - ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_10_0, ext_zve64f), - ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_10_0, ext_zve64d), - ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh), - ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin), - ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), - ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), - ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), - ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), - ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), - ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), - ISA_EXT_DATA_ENTRY(svadu, true, PRIV_VERSION_1_12_0, ext_svadu), - ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), - ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), - ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), - ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), - ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), - ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), - ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo= ), - ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xthea= dcondmov), - ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xthea= dfmemidx), - ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv= ), - ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac= ), - ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xthead= memidx), - ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xthea= dmempair), - ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsy= nc), - ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVe= ntanaCondOps), + ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), + ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), + ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), + ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), + ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), + ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), + ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), + ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh), + ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin), + ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx), + ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx), + ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca), + ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb), + ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf), + ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd), + ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce), + ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp), + ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt), + ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba), + ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb), + ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc), + ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb), + ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc), + ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx), + ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs), + ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk), + ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn), + ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd), + ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne), + ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh), + ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr), + ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks), + ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), + ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), + ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), + ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), + ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), + ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), + ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), + ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), + ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), + ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), + ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), + ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), + ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), + ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), + ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), + ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), + ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), + ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), + ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), + ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo), + ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondm= ov), + ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemi= dx), + ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv), + ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac), + ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx= ), + ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempa= ir), + ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), + ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaC= ondOps), }; =20 static bool isa_ext_is_enabled(RISCVCPU *cpu, @@ -1741,8 +1740,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char = **isa_str, int i; =20 for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_edata_arr[i].multi_letter && - isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { + if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { new =3D g_strconcat(old, "_", isa_edata_arr[i].name, NULL); g_free(old); old =3D new; --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249321; cv=none; d=zohomail.com; s=zohoarc; b=hDxr6CyrgZQTWcmTCcrv/fzQ50s2xNmkiOz15HidfT5xzq7KjTUVjODmH6Y6OH5jT04Rs4oHtw8ehSeFYJumgUhLdnyPI9YcxZLZixWOv/1zuxkII5MQ4WHrOPDEhqOq9sL3P4+gRwNLaxGa+plhkg0NTjEqv9AJRg5LclCBKnQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249321; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0VlDUG5xdx4tfhItsi+rq/GyyGDu6Bi+jvi5OOLM7AE=; b=UbKAUtcUv7kUeNU4BZSzKchUIDCKy62cEzoVHgr758j18+ZZNlVYCPOZNa1iXQq0ZdYuRZKmFVFO3HnesN5bhzCDvdPNgwqbThnmfJFDPbRvjAPahaPRLmKFxCEhRkyWYRDXWx03t7xl8Ep8s/yLSDva69ldIihkC19GQb9zcjA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249321687336.14836908333746; Thu, 4 May 2023 18:15:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujt1-0007dQ-S2; Thu, 04 May 2023 21:05:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujt0-0007Wb-6I for qemu-devel@nongnu.org; Thu, 04 May 2023 21:05:26 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujsy-0007TK-5R for qemu-devel@nongnu.org; Thu, 04 May 2023 21:05:25 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1aad5245571so8030815ad.1 for ; Thu, 04 May 2023 18:05:23 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. 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User settings are reflected in the cpu->cfg object for later use. These properties are used in the target/riscv/cpu.c code, most notably in riscv_cpu_validate_set_extensions(), where most of our realize time validations are made. And then there's env->misa_ext, the field where the MISA extensions are set, that is read everywhere else. We need to keep env->misa_ext updated with cpu->cfg settings, since our validations rely on it, forcing us to make register_cpu_props() write cpu->cfg.ext_N flags to cover for named CPUs that aren't used named properties but also needs to go through the same validation steps. Failing to so will make those name CPUs fail validation (see c66ffcd5358b for more info). Not only that, but we also need to sync env->misa_ext with cpu->cfg again during realize() time to catch any change the user might have done, since the rest of the code relies on that. Making cpu->cfg.ext_N and env->misa_ext reflect each other is not needed. What we want is a way for users to enable/disable MISA extensions, and there's nothing stopping us from letting the user write env->misa_ext directly. Here are the artifacts that will enable us to do that: - RISCVCPUMisaExtConfig will declare each MISA property; - cpu_set_misa_ext_cfg() is the setter for each property. We'll write env->misa_ext and env->misa_ext_mask with the appropriate misa_bit; cutting off cpu->cfg.ext_N from the logic; - cpu_get_misa_ext_cfg() is a getter that will retrieve the current val of the property based on env->misa_ext; - riscv_cpu_add_misa_properties() will be called in register_cpu_props() to init all MISA properties from the misa_ext_cfgs[] array. With this infrastructure we'll start to get rid of each cpu->cfg.ext_N attribute in the next patches. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fbf612292a..3b234a03d0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1453,6 +1453,69 @@ static void riscv_cpu_init(Object *obj) #endif /* CONFIG_USER_ONLY */ } =20 +typedef struct RISCVCPUMisaExtConfig { + const char *name; + const char *description; + target_ulong misa_bit; + bool enabled; +} RISCVCPUMisaExtConfig; + +static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + const RISCVCPUMisaExtConfig *misa_ext_cfg =3D opaque; + target_ulong misa_bit =3D misa_ext_cfg->misa_bit; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + if (value) { + env->misa_ext |=3D misa_bit; + env->misa_ext_mask |=3D misa_bit; + } else { + env->misa_ext &=3D ~misa_bit; + env->misa_ext_mask &=3D ~misa_bit; + } +} + +static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + const RISCVCPUMisaExtConfig *misa_ext_cfg =3D opaque; + target_ulong misa_bit =3D misa_ext_cfg->misa_bit; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + bool value; + + value =3D env->misa_ext & misa_bit; + + visit_type_bool(v, name, &value, errp); +} + +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D {}; + +static void riscv_cpu_add_misa_properties(Object *cpu_obj) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { + const RISCVCPUMisaExtConfig *misa_cfg =3D &misa_ext_cfgs[i]; + + object_property_add(cpu_obj, misa_cfg->name, "bool", + cpu_get_misa_ext_cfg, + cpu_set_misa_ext_cfg, + NULL, (void *)misa_cfg); + object_property_set_description(cpu_obj, misa_cfg->name, + misa_cfg->description); + object_property_set_bool(cpu_obj, misa_cfg->name, + misa_cfg->enabled, NULL); + } +} + static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), @@ -1599,6 +1662,8 @@ static void register_cpu_props(Object *obj) return; } =20 + riscv_cpu_add_misa_properties(obj); + for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248966; cv=none; d=zohomail.com; s=zohoarc; b=d1XVULV9zEW2eeM2zeEH9yPyirXi9IPQASj5MHyF6xoLN0NHFhsXbYB78Nrdw5ubiqRWyjpflbKPaK9k6LMLFBLFAD4mPr7v1JVtall+qkWE6nbnag+iVaplcpyRuGdu3VcDT9EOncqAr4xRdPpT0+JsM83CnzAoRKRdsLwqE/E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248966; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Z5RXQf6FLVdL4O5TT8cjEinnW5z+LWUcUu0nx1MkXws=; b=GD4HfJvSl7NcmG0Pw0b0p/V9b+eJSUXTBI5fDSh6YoNZbptz3D8Rp0aqewTUFlLJeB74ZQhKPNKMEosjSExX2a0E08MYnBZLJ+p9F+m8wabPDfoyzuqVedlZyHQERInl/YOzDhinUGjkI8xCMNj3DcstsShn+HsNzkib8tlxCKc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683248966803717.429973464969; Thu, 4 May 2023 18:09:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujtG-0000zb-Tg; Thu, 04 May 2023 21:05:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujtF-0000o5-LB for qemu-devel@nongnu.org; Thu, 04 May 2023 21:05:41 -0400 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujt2-0007Uv-0A for qemu-devel@nongnu.org; Thu, 04 May 2023 21:05:41 -0400 Received: by mail-pg1-x531.google.com with SMTP id 41be03b00d2f7-51fcf5d1e44so999638a12.3 for ; Thu, 04 May 2023 18:05:27 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.05.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:05:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248726; x=1685840726; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z5RXQf6FLVdL4O5TT8cjEinnW5z+LWUcUu0nx1MkXws=; b=YY14b86GGAZtXdHUY+iSmn3qT9aT9/QcQW1xhRCLBWe/Ts9ab9dul/DelgQYt+OR0f ixPfc7xXZJG9u8WF8JsMOOn3PDwLGYAZdViby1JwEG1IasA8mmMMuGbNgyCdrZyOHZj4 Jht09bY2Blf4kLOlfsnzJ8OCt3tKHKiBLX0BHcY+PeCppXSw66jKbNbA8KoCIe29n9DK B6MHuw6vN31N4YCbMrhA1s0LuFno6/J8IXsAuNQw9+9wfbDYdSvDOci4Wf8Ecpw0u+B/ 5qLBx9cjZHCgkzCIDQcc2NFE4/6BVgoyONytxVwS6Sm4gJGaIQAXRDJPyASjHJ+51lTl 07sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248726; x=1685840726; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z5RXQf6FLVdL4O5TT8cjEinnW5z+LWUcUu0nx1MkXws=; b=O24cwBNOhiRd4jvfNWpuHo2WqBQ+k19RGIld9K854rz3WJdSgUsUxnSEZj0U6nX6ot KfUaGsJ3sJYVOpcEMNAHJQXLXHI2wmTAZxq+bCA+qUKahM1UID1SrXO/9ATN/PeO5mJ5 L/HJ7opoHalqRy5kiGjfCYRJf3tkXK4Gldq16Jsx3pDqKdzyeV+vC63oxjgNibqY4+ED ocpvsoDiOj+TnEDAB/rMkorcz17s9ZRWUdbNJTjSOMn77Hoqy+zj/uh9XY4Ia7fMVZ4s sdapKtIOT56uVmfTiEZ2+AD7zbD6U62dh4XXT/opKen9d2kE23OqeEr0swlawQP9RH3f yAWg== X-Gm-Message-State: AC+VfDyrDPTObff4Pe+hPEAF6sY0P7ftc1xivgEc4F6KrvHNk2yryzxU pNocc1aGRyeTaMEicuawugrUQKftggC0+g== X-Google-Smtp-Source: ACHHUZ6C+7RR3wFIWBKHubxSvzaPVLHrHQ2EJ0BQaPZUFL+pBlFPHRu7BPcZGTxJIdlGPdn9ULkEqQ== X-Received: by 2002:a17:902:d50b:b0:1ab:723:1acc with SMTP id b11-20020a170902d50b00b001ab07231accmr5982015plg.35.1683248725646; Thu, 04 May 2023 18:05:25 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 37/89] target/riscv: remove cpu->cfg.ext_a Date: Fri, 5 May 2023 11:01:49 +1000 Message-Id: <20230505010241.21812-38-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=alistair23@gmail.com; helo=mail-pg1-x531.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248967081100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Create a new "a" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVA. Instances of cpu->cfg.ext_a and similar are replaced with riscv_has_ext(env, RVA). Remove the old "a" property and 'ext_a' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/cpu.c | 16 ++++++++-------- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cbf3de2708..1d1a17d85b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -426,7 +426,6 @@ struct RISCVCPUConfig { bool ext_e; bool ext_g; bool ext_m; - bool ext_a; bool ext_f; bool ext_d; bool ext_c; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3b234a03d0..3770fd4f6f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -819,13 +819,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) =20 /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && - cpu->cfg.ext_a && cpu->cfg.ext_f && - cpu->cfg.ext_d && + riscv_has_ext(env, RVA) && + cpu->cfg.ext_f && cpu->cfg.ext_d && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); cpu->cfg.ext_i =3D true; cpu->cfg.ext_m =3D true; - cpu->cfg.ext_a =3D true; cpu->cfg.ext_f =3D true; cpu->cfg.ext_d =3D true; cpu->cfg.ext_icsr =3D true; @@ -869,7 +868,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { + if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { error_setg(errp, "Zawrs extension requires A extension"); return; } @@ -1160,7 +1159,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_cpu_cfg(env)->ext_m) { ext |=3D RVM; } - if (riscv_cpu_cfg(env)->ext_a) { + if (riscv_has_ext(env, RVA)) { ext |=3D RVA; } if (riscv_cpu_cfg(env)->ext_f) { @@ -1496,7 +1495,10 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visito= r *v, const char *name, visit_type_bool(v, name, &value, errp); } =20 -static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D {}; +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { + {.name =3D "a", .description =3D "Atomic instructions", + .misa_bit =3D RVA, .enabled =3D true}, +}; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) { @@ -1522,7 +1524,6 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), - DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), @@ -1645,7 +1646,6 @@ static void register_cpu_props(Object *obj) cpu->cfg.ext_i =3D misa_ext & RVI; cpu->cfg.ext_e =3D misa_ext & RVE; cpu->cfg.ext_m =3D misa_ext & RVM; - cpu->cfg.ext_a =3D misa_ext & RVA; cpu->cfg.ext_f =3D misa_ext & RVF; cpu->cfg.ext_d =3D misa_ext & RVD; cpu->cfg.ext_v =3D misa_ext & RVV; --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.05.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:05:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248729; x=1685840729; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dTRKBCm4ghHrHqbde39ICtG5ruW14LMud4XOBjlLFVU=; b=Q1pCt1a04ohjTCoNlbZfbHu9+8qFOIy7D7K4CDZae5kBM5wBydHYOsDWJDWxI4ryBU RClhNiK9YcuyKv/pZ4dgnaMh+Yhg/OYFObf5rR34Mlvc3IyfHM4G1RfcmogeZXZyEjjI lzN9tAFBTwae75t1tGfF069llAG+FcbkAO7/jHuyr6qeF0qML7CuVFvTDqXKXQCf/TlL IdToiT5CNgva5YxFVL12BTEDp+DOiEY9OtnIE+dwc53OZsLFgZ2Czf/1lazKxv1MeMVE 3fRAAzw9S912VQKmcJDirHFMVULo8wz+w2NckABZvWHUXohH9ofB6+i9XrzON5C7HpWf OBRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248729; x=1685840729; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dTRKBCm4ghHrHqbde39ICtG5ruW14LMud4XOBjlLFVU=; b=OSElZhxAL1l+65duK1iVCk3tQtRECOmuDpmzdZxP5C+2rghoHgd9DeS1CupLfoP9Nd U0P/89Bg3yqgxFwopQ2U+y3sIoH1t/PeF3nXEClBU2jAMIXvhMrqvkH+HMHsi09pnocf Q28dqgO5D3EQLnSXmuuVB8shUoIxw6eqpPtqQbtm3cSrIQDCup2KGNPmxtTxwWxsjvlk jHREtdwKezs2RnW2mFOrhp4pyEXeVqYHwTJP+rZFytCqFrZ3Im9ZOdBZ6JtEvWp/jzof Lc3q/g4RQLMrL7hsUAzHPZmSv3JAR68qRl/t34c1l4vJV7KhotNcHw2ipH2QY1cid1M8 2IjA== X-Gm-Message-State: AC+VfDyrUT2PUuX62g+IASIwKCG1RJHOmbBspeDsTb9++zOlzMuYXx8N 6T97FQz1BoxOgHImUZ9eWPZooiu6L/gT2g== X-Google-Smtp-Source: ACHHUZ6wm/6GTRoiMCl2HHLNPG69xFQibSgTiOliDr1Vhfhri46pEOR/Fnkvf0kgqKw2OiJ0s7Ebbg== X-Received: by 2002:a17:903:503:b0:1a9:765c:77ac with SMTP id jn3-20020a170903050300b001a9765c77acmr5332494plb.7.1683248729159; Thu, 04 May 2023 18:05:29 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 38/89] target/riscv: remove cpu->cfg.ext_c Date: Fri, 5 May 2023 11:01:50 +1000 Message-Id: <20230505010241.21812-39-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=alistair23@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248786091100005 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Create a new "c" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVC. Instances of cpu->cfg.ext_c and similar are replaced with riscv_has_ext(env, RVC). Remove the old "c" property and 'ext_c' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/cpu.c | 9 ++++----- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1d1a17d85b..9a3847329c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -428,7 +428,6 @@ struct RISCVCPUConfig { bool ext_m; bool ext_f; bool ext_d; - bool ext_c; bool ext_s; bool ext_u; bool ext_h; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3770fd4f6f..2e00b8f20a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -407,7 +407,6 @@ static void rv64_thead_c906_cpu_init(Object *obj) set_priv_version(env, PRIV_VERSION_1_11_0); =20 cpu->cfg.ext_g =3D true; - cpu->cfg.ext_c =3D true; cpu->cfg.ext_u =3D true; cpu->cfg.ext_s =3D true; cpu->cfg.ext_icsr =3D true; @@ -957,7 +956,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) } } =20 - if (cpu->cfg.ext_c) { + if (riscv_has_ext(env, RVC)) { cpu->cfg.ext_zca =3D true; if (cpu->cfg.ext_f && env->misa_mxl_max =3D=3D MXL_RV32) { cpu->cfg.ext_zcf =3D true; @@ -1168,7 +1167,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_cpu_cfg(env)->ext_d) { ext |=3D RVD; } - if (riscv_cpu_cfg(env)->ext_c) { + if (riscv_has_ext(env, RVC)) { ext |=3D RVC; } if (riscv_cpu_cfg(env)->ext_s) { @@ -1498,6 +1497,8 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor= *v, const char *name, static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { {.name =3D "a", .description =3D "Atomic instructions", .misa_bit =3D RVA, .enabled =3D true}, + {.name =3D "c", .description =3D "Compressed instructions", + .misa_bit =3D RVC, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1526,7 +1527,6 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), - DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), @@ -1649,7 +1649,6 @@ static void register_cpu_props(Object *obj) cpu->cfg.ext_f =3D misa_ext & RVF; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.05.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:05:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248732; x=1685840732; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vgul8x4Qi/Uxz9Qmr5Jz3geBJliOPBQT6thdE7BzeNQ=; b=NJA2xJ4m7mTqB9Zpcl3dEIz2XDoBB7sdXTxfVQRCCxZEMLieNGjd8LaUGygdvdA2Co VXu9LqVQEuyAnJDbLa4E9L4ZkKMu2uaCF915WCmlgJEvpxNc4eFNZy4HQw2tP/lDXGHe wWa51CeVmZVHjDFiigvoUuK6rTE7WMldgJKW2BWzWG02XXD9Uzo8z2sYxQsXI88CDBYX QkXXB+CxNfTIq684POjt8TuO1LUXTb93Mv9oaVm7t1dEKRGpZFsWjRuPfPX71u5oyKzS PLUhXHG3nTlhSU2knVZIxiLd45x8J8nlUopt0J8+pmu2sslmTZC1zIaOuI4Sm96r6MzS jTRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248732; x=1685840732; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vgul8x4Qi/Uxz9Qmr5Jz3geBJliOPBQT6thdE7BzeNQ=; b=D0x83FT0/EcVWa/wqa6hDjxJjtiXLMJB6ZyI15D1Nb8BVbQgD5+3J7BuUqn8MD7Ima RfVQvX7NTgMKfaP8iMTCb1g0es/JYARjHOBf7Hz7x/xEDxdOA/qUAYsGC9aNSqO1hWru St3CVNIlCVWOqHUJhU4ITPzntzOz1HRgPgT2Ll8W5c4TWhvboJyJENBSlfXJq2rHa+Uv PZI3QCvQ+oooYreSOCgv+0Co7s/XXW8HwheG+yJsm1GkU71j+DghrSBij8SUekGTPqlV Om+U0LzfZVNBQ6h8/wSy6GYiBVKPcNrjxx5jcBpwxNoAlEVfwYAQbnpOYOdA8OCFzQ+h KbTw== X-Gm-Message-State: AC+VfDzlTUKZfmuuBe5twT0Zl2VNWicIcwhFe+hI0cqxSQ+gHFYNyTXB MK2VLchL/5MUqdVbfwGqWuMdC8sYGHk4rQ== X-Google-Smtp-Source: ACHHUZ7Ye6eMhcfU8XrSywibWPB3iG1yWTXAb4TDVoXprsZfjVbCyy1sAzQtt6SHSLHOtph3vlcGEA== X-Received: by 2002:a17:903:1208:b0:1a9:7912:850e with SMTP id l8-20020a170903120800b001a97912850emr5850883plh.10.1683248732297; Thu, 04 May 2023 18:05:32 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 39/89] target/riscv: remove cpu->cfg.ext_d Date: Fri, 5 May 2023 11:01:51 +1000 Message-Id: <20230505010241.21812-40-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248750071100015 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Create a new "d" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVD. Instances of cpu->cfg.ext_d and similar are replaced with riscv_has_ext(env, RVD). Remove the old "d" property and 'ext_d' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/cpu.c | 17 ++++++++--------- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9a3847329c..fba5e9a33c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -427,7 +427,6 @@ struct RISCVCPUConfig { bool ext_g; bool ext_m; bool ext_f; - bool ext_d; bool ext_s; bool ext_u; bool ext_h; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2e00b8f20a..5bb03e2ee5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -819,13 +819,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && riscv_has_ext(env, RVA) && - cpu->cfg.ext_f && cpu->cfg.ext_d && + cpu->cfg.ext_f && riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); cpu->cfg.ext_i =3D true; cpu->cfg.ext_m =3D true; cpu->cfg.ext_f =3D true; - cpu->cfg.ext_d =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; =20 @@ -881,7 +880,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { + if (riscv_has_ext(env, RVD) && !cpu->cfg.ext_f) { error_setg(errp, "D extension requires F extension"); return; } @@ -901,7 +900,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) cpu->cfg.ext_zve32f =3D true; } =20 - if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) { + if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { error_setg(errp, "Zve64d/V extensions require D extension"); return; } @@ -961,7 +960,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) if (cpu->cfg.ext_f && env->misa_mxl_max =3D=3D MXL_RV32) { cpu->cfg.ext_zcf =3D true; } - if (cpu->cfg.ext_d) { + if (riscv_has_ext(env, RVD)) { cpu->cfg.ext_zcd =3D true; } } @@ -976,7 +975,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) { + if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { error_setg(errp, "Zcd extension requires D extension"); return; } @@ -1164,7 +1163,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_cpu_cfg(env)->ext_f) { ext |=3D RVF; } - if (riscv_cpu_cfg(env)->ext_d) { + if (riscv_has_ext(env, RVD)) { ext |=3D RVD; } if (riscv_has_ext(env, RVC)) { @@ -1499,6 +1498,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVA, .enabled =3D true}, {.name =3D "c", .description =3D "Compressed instructions", .misa_bit =3D RVC, .enabled =3D true}, + {.name =3D "d", .description =3D "Double-precision float point", + .misa_bit =3D RVD, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1526,7 +1527,6 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), - DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), @@ -1647,7 +1647,6 @@ static void register_cpu_props(Object *obj) cpu->cfg.ext_e =3D misa_ext & RVE; cpu->cfg.ext_m =3D misa_ext & RVM; cpu->cfg.ext_f =3D misa_ext & RVF; - cpu->cfg.ext_d =3D misa_ext & RVD; cpu->cfg.ext_v =3D misa_ext & RVV; cpu->cfg.ext_s =3D misa_ext & RVS; cpu->cfg.ext_u =3D misa_ext & RVU; --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249045; cv=none; d=zohomail.com; s=zohoarc; b=UbURWY3DiSeiyd6emadCm/SIjw8X111Es2+VAiW89zdRefqbvgnTSDj/ez1KGpUmozSjjyLcyZUD6ff+qNwtgxV3gBdhsohG9nJm+1f9m95AMh1jEUqTy/COFtOuHL8Via1mYEvxHrLO/1rcJh+dY8QCYpeuvqgQ5y3YMNt8kj0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249045; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Instances of cpu->cfg.ext_f and similar are replaced with riscv_has_ext(env, RVF). Remove the old "f" property and 'ext_f' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-9-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/cpu.c | 26 +++++++++++++------------- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index fba5e9a33c..e5680b0709 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -426,7 +426,6 @@ struct RISCVCPUConfig { bool ext_e; bool ext_g; bool ext_m; - bool ext_f; bool ext_s; bool ext_u; bool ext_h; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5bb03e2ee5..715cbca1b3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -819,12 +819,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && riscv_has_ext(env, RVA) && - cpu->cfg.ext_f && riscv_has_ext(env, RVD) && + riscv_has_ext(env, RVF) && + riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); cpu->cfg.ext_i =3D true; cpu->cfg.ext_m =3D true; - cpu->cfg.ext_f =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; =20 @@ -861,7 +861,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { + if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) { error_setg(errp, "F extension requires Zicsr"); return; } @@ -875,12 +875,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) cpu->cfg.ext_zfhmin =3D true; } =20 - if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) { + if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { error_setg(errp, "Zfh/Zfhmin extensions require F extension"); return; } =20 - if (riscv_has_ext(env, RVD) && !cpu->cfg.ext_f) { + if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { error_setg(errp, "D extension requires F extension"); return; } @@ -905,7 +905,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) { + if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { error_setg(errp, "Zve32f/Zve64f extensions require F extension"); return; } @@ -938,7 +938,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) error_setg(errp, "Zfinx extension requires Zicsr"); return; } - if (cpu->cfg.ext_f) { + if (riscv_has_ext(env, RVF)) { error_setg(errp, "Zfinx cannot be supported together with F extensio= n"); return; @@ -950,14 +950,14 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) cpu->cfg.ext_zcb =3D true; cpu->cfg.ext_zcmp =3D true; cpu->cfg.ext_zcmt =3D true; - if (cpu->cfg.ext_f && env->misa_mxl_max =3D=3D MXL_RV32) { + if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { cpu->cfg.ext_zcf =3D true; } } =20 if (riscv_has_ext(env, RVC)) { cpu->cfg.ext_zca =3D true; - if (cpu->cfg.ext_f && env->misa_mxl_max =3D=3D MXL_RV32) { + if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { cpu->cfg.ext_zcf =3D true; } if (riscv_has_ext(env, RVD)) { @@ -970,7 +970,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) { + if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { error_setg(errp, "Zcf extension requires F extension"); return; } @@ -1160,7 +1160,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVA)) { ext |=3D RVA; } - if (riscv_cpu_cfg(env)->ext_f) { + if (riscv_has_ext(env, RVF)) { ext |=3D RVF; } if (riscv_has_ext(env, RVD)) { @@ -1500,6 +1500,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVC, .enabled =3D true}, {.name =3D "d", .description =3D "Double-precision float point", .misa_bit =3D RVD, .enabled =3D true}, + {.name =3D "f", .description =3D "Single-precision float point", + .misa_bit =3D RVF, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1526,7 +1528,6 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), - DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), @@ -1646,7 +1647,6 @@ static void register_cpu_props(Object *obj) cpu->cfg.ext_i =3D misa_ext & RVI; cpu->cfg.ext_e =3D misa_ext & RVE; cpu->cfg.ext_m =3D misa_ext & RVM; - cpu->cfg.ext_f =3D misa_ext & RVF; cpu->cfg.ext_v =3D misa_ext & RVV; cpu->cfg.ext_s =3D misa_ext & RVS; cpu->cfg.ext_u =3D misa_ext & RVU; --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249390; cv=none; d=zohomail.com; s=zohoarc; b=NKVKmYPp0l7o6ReJoRC2gdDeikza2cLiuwPIhDAmGF16yj/CFKEZyvOpNZ+Nf3uNVhnXp4EZKuhagz3AB+eDKC6v8jK20WVSTb8aJXUrJEY+D0AlOntgMCZ5xHrIlxa3OqcS0itxSMotC4inKSG4tGQXPiiG/VpXZgfN3aKUMwU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249390; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.05.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:05:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248739; x=1685840739; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mjm7hy5NUkBT/uOHj61PYQmyww7/dxN5VdhuTdeHgcQ=; b=OO2xFhKALJxSFSDTj3Znq4OHXZe9gKAMiZHCzDnYRCcob6DELJdre1OCTSDa0NpCvr FwCM8jk/Z0klgYk5L8ZfQnHUZQaJrbDaqM3XQ25tBGkP7Z6ABWEc89tmcfBOIbqCyupX GeTvNfGHSuzKQs6gj5d9VNWeAAYBwI4QmQLb9K8q1DEqc7lRenztgUdSCqXhhVz4CZno G4gPFgTs0HzD/QVpoMI4M84jgK/NQL4egzlY9SF+3WxnV+er17e8WfpOjvNFsoGXREOG brOEcHCJmI8go5Eogq/k1DxQ8+rH6rWI7Aadmp/1Z9lgVtzBqt8RlJqb4woRBIJu5OJG Wm3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248739; x=1685840739; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mjm7hy5NUkBT/uOHj61PYQmyww7/dxN5VdhuTdeHgcQ=; b=VgTqci5OieUt5jECk025Rgo/aKSWPFcUvZQ4NINp6u+7BlVav+LyRXC5Sbd3Sb0BZ5 qsFRt9WDg5VPeXqLD9cS036gbRgXF73hJ/tfTQdGM0yQXGtpKA1Iwu2bMJ94vRmwQrlP aNIyqxV/5sifB8p1l4yWrpYu/89Cxr1G0x0SQc7AvgQT64P9+40pFtsiv1cRyubqyudg rEHojUU36L8sUeMB9Yr//Mb+u00kGz+UY53UfUbqPyFWPywfB3RSQE8kMOpiCHkhWcX+ dxUURWNypsutF04ctmsgEmVeNi1QWYcEk2t8GedVj5qLAe5q9ElIKR8Uq/TpwekjQpOW /Cow== X-Gm-Message-State: AC+VfDyLRm1fftv4AHOXBdH0iFllRGHBBQ2lt7va8DN798CZQyN3LQ6j BcRVjs0Y/Pj4NZYOcy/bzd24eke1Jb9JUQ== X-Google-Smtp-Source: ACHHUZ5wEqRllom/5RNcMvQfYdDfo2xiExxLtPVyFyaOdapz2+SOMNhBJz6JSsv/4E0xKbx5bwEB6g== X-Received: by 2002:a17:90b:198f:b0:246:5787:6f5d with SMTP id mv15-20020a17090b198f00b0024657876f5dmr4649097pjb.10.1683248738646; Thu, 04 May 2023 18:05:38 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 41/89] target/riscv: remove cpu->cfg.ext_i Date: Fri, 5 May 2023 11:01:53 +1000 Message-Id: <20230505010241.21812-42-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=alistair23@gmail.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249391141100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Create a new "i" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVI. Instances of cpu->cfg.ext_i and similar are replaced with riscv_has_ext(env, RVI). Remove the old "i" property and 'ext_i' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-10-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/cpu.c | 15 +++++++-------- 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e5680b0709..479b654d54 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -422,7 +422,6 @@ typedef struct { } RISCVSATPMap; =20 struct RISCVCPUConfig { - bool ext_i; bool ext_e; bool ext_g; bool ext_m; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 715cbca1b3..f082748569 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -817,13 +817,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) CPURISCVState *env =3D &cpu->env; =20 /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && + if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m && riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_i =3D true; cpu->cfg.ext_m =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; @@ -832,13 +831,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) env->misa_ext_mask =3D env->misa_ext; } =20 - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { + if (riscv_has_ext(env, RVI) && cpu->cfg.ext_e) { error_setg(errp, "I and E extensions are incompatible"); return; } =20 - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { + if (!riscv_has_ext(env, RVI) && !cpu->cfg.ext_e) { error_setg(errp, "Either I or E extension must be set"); return; @@ -850,7 +849,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { + if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) { error_setg(errp, "H depends on an I base integer ISA with 32 x registers= "); return; @@ -1148,7 +1147,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) { uint32_t ext =3D 0; =20 - if (riscv_cpu_cfg(env)->ext_i) { + if (riscv_has_ext(env, RVI)) { ext |=3D RVI; } if (riscv_cpu_cfg(env)->ext_e) { @@ -1502,6 +1501,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVD, .enabled =3D true}, {.name =3D "f", .description =3D "Single-precision float point", .misa_bit =3D RVF, .enabled =3D true}, + {.name =3D "i", .description =3D "Base integer instruction set", + .misa_bit =3D RVI, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1524,7 +1525,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) =20 static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ - DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), @@ -1644,7 +1644,6 @@ static void register_cpu_props(Object *obj) * later on. */ if (cpu->env.misa_ext !=3D 0) { - cpu->cfg.ext_i =3D misa_ext & RVI; cpu->cfg.ext_e =3D misa_ext & RVE; cpu->cfg.ext_m =3D misa_ext & RVM; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.05.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:05:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248742; x=1685840742; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ITG8jjVwNOI0oWDo4I+IRi2yCELVv5S7qO6nRFbXJq4=; b=RC06wX60HSApaqrKDxJJ72bo4Fj+NyRyBrxHWNoUICyUVcS0XbHpQluTUnUZJw2x4T 83A2KglSKtgZ3Kkeqm9hrLtM41CxHkzWKg+tQMfECfvKMoJv+jGbC4XhBtRT5HZRtSIP LKcw0j+bDSQ4VnA7TOYJY22Rw44v9uTUOfEaCEjrPXl0ocrjHPRNCxyMQvCFXR1XZU5G FitjqFMhjwJNEdKCfpBMvondeESSielVJCjxf2jYDhVc03kh6GUz8ab5iMlFHIRO+a4l yCFp2yWq58mZOM0No6qwdyeSFbLaM4Jyz/+eQ16m41533OfBe3olp7wSGlJjsnjieE1l 6fRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248742; x=1685840742; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ITG8jjVwNOI0oWDo4I+IRi2yCELVv5S7qO6nRFbXJq4=; b=es2KUKYP1yyPhzwwGEBysgZOja2Q1O4EGL1I+jaK2hHjbyHvyDOBRrRPR6uS/xyDym iwRnhWTztKPEEvZYW3f3iTTXiLludYZcQuFMBI+eoWALYONVvxMsSSgakbNiNjeM139I tYuFJBS4w5iB+4iOFJpKIc5EyUkO6qL6lVh8KBqDH0UAM/xXcQ5O0YfWlVUR/8vr7Vhw ZCHt7XEptFiyUov54fuWc4OT9pP8A0CBck1xZ02rc4mXmzIa2RW9z3ArkTte1bVXWIYu b9UnGIcbpRcsLyU29H68MFA3MqiiBsTggjpH7M/RkwJfGW4/73HtRT+rkqKDUqj53sWW ymfg== X-Gm-Message-State: AC+VfDyjoX5KYZKMGr346cS7R1vqnCE2swf2tz/NxeUUpHNJihNFGTl/ KJuZllujCCEbB69mPTs3HXE6sxFFy1iZKA== X-Google-Smtp-Source: ACHHUZ7cR/TIOMisjtlBU0LLh/A96WjKcan57NPmmRhMlZyT0o92wD/MRvhQLxIy5XpCk+a7C4HD1w== X-Received: by 2002:a17:903:41d2:b0:1aa:d545:462e with SMTP id u18-20020a17090341d200b001aad545462emr7576350ple.13.1683248741952; Thu, 04 May 2023 18:05:41 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 42/89] target/riscv: remove cpu->cfg.ext_e Date: Fri, 5 May 2023 11:01:54 +1000 Message-Id: <20230505010241.21812-43-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=alistair23@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248787737100009 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Create a new "e" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVE. Instances of cpu->cfg.ext_e and similar are replaced with riscv_has_ext(env, RVE). Remove the old "e" property and 'ext_e' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-11-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/cpu.c | 10 +++++----- target/riscv/insn_trans/trans_rvzce.c.inc | 2 +- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 479b654d54..2b42de60b1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -422,7 +422,6 @@ typedef struct { } RISCVSATPMap; =20 struct RISCVCPUConfig { - bool ext_e; bool ext_g; bool ext_m; bool ext_s; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f082748569..33db4fa4b2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -831,13 +831,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) env->misa_ext_mask =3D env->misa_ext; } =20 - if (riscv_has_ext(env, RVI) && cpu->cfg.ext_e) { + if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { error_setg(errp, "I and E extensions are incompatible"); return; } =20 - if (!riscv_has_ext(env, RVI) && !cpu->cfg.ext_e) { + if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { error_setg(errp, "Either I or E extension must be set"); return; @@ -1150,7 +1150,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVI)) { ext |=3D RVI; } - if (riscv_cpu_cfg(env)->ext_e) { + if (riscv_has_ext(env, RVE)) { ext |=3D RVE; } if (riscv_cpu_cfg(env)->ext_m) { @@ -1503,6 +1503,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVF, .enabled =3D true}, {.name =3D "i", .description =3D "Base integer instruction set", .misa_bit =3D RVI, .enabled =3D true}, + {.name =3D "e", .description =3D "Base integer instruction set (embedd= ed)", + .misa_bit =3D RVE, .enabled =3D false}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1525,7 +1527,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) =20 static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ - DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), @@ -1644,7 +1645,6 @@ static void register_cpu_props(Object *obj) * later on. */ if (cpu->env.misa_ext !=3D 0) { - cpu->cfg.ext_e =3D misa_ext & RVE; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.05.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:05:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248745; x=1685840745; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BFpSyKFezOrBsvTABEY4MyulP+rbedB6ASbtbkYsot0=; b=WA8TM3O12/8c82mvux4/LTVUbemDMeMKkcP7XYtXbSqrsYZMRqm5Ftl0jxLikX4cXj 5yPlzJlSkuoikDRmDD/FUl5NXs2ValGFn9N52ktFcChh9GxZ8tV0+7T7m9KVp+jICBbs RjBEgR8U/dQDhUncoLcbzXh7mzTWxVC5uOpxkNgA6xSWSHDYr2lvPfLt2BGLLzbwvorv c1y82/XvZepzRxmiTSkOSjQX2XKQQbFh31qMM6PcqPzhd8QmpCVf0RY+acpxbmJEWZwQ WT78dRClCwky9SwZ52QnMbN3ySnX6pNPqrr+92Jif2RYsA9P/XI1kfrpwLL8WD0J+K3q 1ovg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248745; x=1685840745; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BFpSyKFezOrBsvTABEY4MyulP+rbedB6ASbtbkYsot0=; b=PdtJL+GcqMN+ELZFcD6d+oUOTNkMKo8ZMEB5CumwaowHmsqDpqZikBU7EsrS8p4Lxi v/K9Y5X4P4oGKLMxnjeTYz8bMb9/8eyc7MnDNkIEnyfQbxqLK7vOf0Y/ibhy9DgUcvVf j4B58VMmCYMv7UkDyNlK74fMjHFoFZKqiyZr/nK5W4wCOOgvtVuLPMdLYu5xBqA94yOK kY7Y7MK6v+nRd1ZKg+DmJwgfH3zq6QDoN2fq3jgY9WmLgrqhg06MrpTde010igK0GjQl vapGmdH/3T3XDa9qtNvxKBsWkxGuLb08FUHz3OOxsrigfD9rTV3rFWbVl5rXDT6MD7d/ XdUA== X-Gm-Message-State: AC+VfDwytJfW8NrPpiZEKcs23kWxqmWOUnsHLyWvsOkpN09U/XqexypT k/489s5YJz/2UA3OtIEe5k28gZPJFsvIGA== X-Google-Smtp-Source: ACHHUZ5OOi2620XGxjW80vJxDsiSBFQGwy2dhCwp5YT5acONdoJRkxxHdVwBijmrRBOFJ6UwbBRscg== X-Received: by 2002:a17:902:ce8f:b0:1aa:ebcc:dd5e with SMTP id f15-20020a170902ce8f00b001aaebccdd5emr6464508plg.65.1683248745355; Thu, 04 May 2023 18:05:45 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 43/89] target/riscv: remove cpu->cfg.ext_m Date: Fri, 5 May 2023 11:01:55 +1000 Message-Id: <20230505010241.21812-44-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=alistair23@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249136081100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Create a new "m" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVM. Instances of cpu->cfg.ext_m and similar are replaced with riscv_has_ext(env, RVM). Remove the old "m" property and 'ext_m' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-12-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/cpu.c | 10 +++++----- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2b42de60b1..71540a33ec 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -423,7 +423,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_m; bool ext_s; bool ext_u; bool ext_h; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 33db4fa4b2..24640450c7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -817,13 +817,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) CPURISCVState *env =3D &cpu->env; =20 /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m && + if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && + riscv_has_ext(env, RVM) && riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_m =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; =20 @@ -1153,7 +1153,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVE)) { ext |=3D RVE; } - if (riscv_cpu_cfg(env)->ext_m) { + if (riscv_has_ext(env, RVM)) { ext |=3D RVM; } if (riscv_has_ext(env, RVA)) { @@ -1505,6 +1505,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVI, .enabled =3D true}, {.name =3D "e", .description =3D "Base integer instruction set (embedd= ed)", .misa_bit =3D RVE, .enabled =3D false}, + {.name =3D "m", .description =3D "Integer multiplication and division", + .misa_bit =3D RVM, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1528,7 +1530,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), - DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), @@ -1645,7 +1646,6 @@ static void register_cpu_props(Object *obj) * later on. */ if (cpu->env.misa_ext !=3D 0) { - cpu->cfg.ext_m =3D misa_ext & RVM; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.05.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:05:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248748; x=1685840748; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r0HMGYLkLLW+NmuP1q5Nflfs6qIETz2UQ27v4mEd4VY=; b=pGYiOViH7Im0RBDJUEYEUG/LpwEfs3RFYt9UIzSP6zzURczE6m5PL6zHAIQbsFAdSa L/G2FRu/cl/y6PokaddDKhvK2NkVnQhdXXXqYOxqIYzl0FdLQd2WtJglhhk/j9c9UaeX nRogcxIvdwnXQ6GrhD6UKFw0Ho3sonRcG4OFM5k30tHd1pmpSF4WiX/jBNkorGEVkgQf eMhiZ2irJyWJvaaE8OJU8s8kC0/KMTia5fYqnd5MGcAO+eaVKCuhKNQQ5OMhEZACDy3G mc9SlVEZwV7sduRU/987lwW5Bb/qx0Sh1KoFxHFKqu2O/LdVqy6W65T2jxCq6FyKUBrq LMvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248748; x=1685840748; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r0HMGYLkLLW+NmuP1q5Nflfs6qIETz2UQ27v4mEd4VY=; b=E2mYegBSMWAZVNzNHapksSmXrUacKOShYFhuDt6k5UyNidC8RDCrZyaV4h6xme6RBq EjdB+2HcUlw35TPWnBW+8wai7dBH9LAwp0NN8QbHVRQV4yinoiMjHpMJCK8cqAFklQ+I JISXHU/WtlaDcfytWrD4VTF5Xg3Ol+OxfFVcqilZJ93m1SYEnTskXvCFKcvHV4ufXSU9 LohX7ESeJ7vRH0CWkE7dL7Qh++oo381UHRZpJosMbxP2NjZhKAjPpWiyinAkGfkjjk+5 FaltWmHnKCuxUL5BcspVX4u/8idKclLrde51137jrRRo37aHg2yLBFF6h1R+XReh783b BmiQ== X-Gm-Message-State: AC+VfDzmZynDOQw5b4hRgaq7rCtxO9g3KqffeSD3hhC4ek57ZszKdesy oZHYZkRc85yZQT+YT46NULys85QgEmtAWw== X-Google-Smtp-Source: ACHHUZ7+Hhyk3tbcZEI9rmd8jezX7yjiN43ZeP4HPE1QDatAY+Inp43//sEoi4vnK+0xZhMt3gCgFw== X-Received: by 2002:a17:902:7c17:b0:1a6:5487:3f97 with SMTP id x23-20020a1709027c1700b001a654873f97mr5057482pll.64.1683248748703; Thu, 04 May 2023 18:05:48 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 44/89] target/riscv: remove cpu->cfg.ext_s Date: Fri, 5 May 2023 11:01:56 +1000 Message-Id: <20230505010241.21812-45-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249313248100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Create a new "s" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVS. Instances of cpu->cfg.ext_s and similar are replaced with riscv_has_ext(env, RVS). Remove the old "s" property and 'ext_s' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-13-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/cpu.c | 11 +++++------ 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 71540a33ec..8b8e541e5f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -423,7 +423,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_s; bool ext_u; bool ext_h; bool ext_j; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 24640450c7..cded82ac7a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -408,7 +408,6 @@ static void rv64_thead_c906_cpu_init(Object *obj) =20 cpu->cfg.ext_g =3D true; cpu->cfg.ext_u =3D true; - cpu->cfg.ext_s =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_zfh =3D true; cpu->cfg.mmu =3D true; @@ -843,7 +842,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { + if (riscv_has_ext(env, RVS) && !cpu->cfg.ext_u) { error_setg(errp, "Setting S extension without U extension is illegal"); return; @@ -855,7 +854,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { + if (cpu->cfg.ext_h && !riscv_has_ext(env, RVS)) { error_setg(errp, "H extension implicitly requires S-mode"); return; } @@ -1168,7 +1167,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVC)) { ext |=3D RVC; } - if (riscv_cpu_cfg(env)->ext_s) { + if (riscv_has_ext(env, RVS)) { ext |=3D RVS; } if (riscv_cpu_cfg(env)->ext_u) { @@ -1507,6 +1506,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVE, .enabled =3D false}, {.name =3D "m", .description =3D "Integer multiplication and division", .misa_bit =3D RVM, .enabled =3D true}, + {.name =3D "s", .description =3D "Supervisor-level instructions", + .misa_bit =3D RVS, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1530,7 +1531,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), - DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), @@ -1647,7 +1647,6 @@ static void register_cpu_props(Object *obj) */ if (cpu->env.misa_ext !=3D 0) { cpu->cfg.ext_v =3D misa_ext & RVV; - cpu->cfg.ext_s =3D misa_ext & RVS; cpu->cfg.ext_u =3D misa_ext & RVU; cpu->cfg.ext_h =3D misa_ext & RVH; cpu->cfg.ext_j =3D misa_ext & RVJ; --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.05.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:05:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248752; x=1685840752; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cDlZ4Zbd9WcpiDWF+eyHE4GUnPL/j5qqsryflmQ1crU=; b=luQt+STFKqVAZfcqt5cri+iT61UIzah4GfqSQUkcwAOrxjZ9lQSCyf1QAhva+K5KNq cKxsujNKIDPF4dR/E1StOQ7xfpe0nuOf/G5ZpwRTW75CQMO7aZDjeQKDjaslOvK5QxUD bEzP/1rXH0DQ3ybMQiKZ4Fi5/ym/sL3/FRwH+1FCx3y7LsXyq2RyXezg86jgcHoOk1yu V4zgfCs1jOmrN+JS/OsE7F6guVfTEzwPaUFe/gnfmsalOJ9uX+D0t4k5N8gjTc9Jm0D2 pd46JHHLfThYMvh6pSWKyB8JaqYTWnb2D+jY2AQOZZO3ZCdPS5OZ4T4Hm06TfQY1hAnG SLNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248752; x=1685840752; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cDlZ4Zbd9WcpiDWF+eyHE4GUnPL/j5qqsryflmQ1crU=; b=gc/VLbALlWrs2x5Ijl8pQ63tHC9nbLB1lHwdpm4XvT7GvQ2N16/g+swwv4QwJsoR5Z LG+Dja7irAbqQJOPUzmZJXJlkTHIUg/1ZGduF5nEkwSB0/U7MHWadCLt6r8bXAHQwbko DJPdRBYjuOxC2tTBBQ3FLaixodDrg4e/olRlMuSW0CdTQQ2fQUqA81q0dKq4mw08P5Py aBIR9dSDyAC6h9ENMnmWKS/oI2iFem/QGv0ofqfyG3axcUDEOmBC0vzDmiw3KZpO9KUd DfkhbV9KgjVg66VDsOp2XcPlItVDtfDok8JtuVykTB9vXK688bU1UONmbCKK7lWeKKNV 2V7Q== X-Gm-Message-State: AC+VfDyLQqbzHgMIiDIPV7y5EJRRNL8jHH/g19Fj7nNslv4+GpA99T5j nDzH4WY1Fkx8QSZ/NEwHe2tFD9HGEYou7Q== X-Google-Smtp-Source: ACHHUZ4TFzczx87uAJi8dbngnzLLcqcw6EfGyppgFyh5hAo4euflEH1DMXzS5SNJyLW3tiU5ADwKsg== X-Received: by 2002:a17:902:d2c2:b0:1ab:581:839e with SMTP id n2-20020a170902d2c200b001ab0581839emr6703330plc.65.1683248751755; Thu, 04 May 2023 18:05:51 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 45/89] target/riscv: remove cpu->cfg.ext_u Date: Fri, 5 May 2023 11:01:57 +1000 Message-Id: <20230505010241.21812-46-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=alistair23@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248779615100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Create a new "u" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVU. Instances of cpu->cfg.ext_u and similar are replaced with riscv_has_ext(env, RVU). Remove the old "u" property and 'ext_u' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-14-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/cpu.c | 9 ++++----- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8b8e541e5f..486061589e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -423,7 +423,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_u; bool ext_h; bool ext_j; bool ext_v; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cded82ac7a..9565495839 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -407,7 +407,6 @@ static void rv64_thead_c906_cpu_init(Object *obj) set_priv_version(env, PRIV_VERSION_1_11_0); =20 cpu->cfg.ext_g =3D true; - cpu->cfg.ext_u =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_zfh =3D true; cpu->cfg.mmu =3D true; @@ -842,7 +841,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (riscv_has_ext(env, RVS) && !cpu->cfg.ext_u) { + if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { error_setg(errp, "Setting S extension without U extension is illegal"); return; @@ -1170,7 +1169,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVS)) { ext |=3D RVS; } - if (riscv_cpu_cfg(env)->ext_u) { + if (riscv_has_ext(env, RVU)) { ext |=3D RVU; } if (riscv_cpu_cfg(env)->ext_h) { @@ -1508,6 +1507,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVM, .enabled =3D true}, {.name =3D "s", .description =3D "Supervisor-level instructions", .misa_bit =3D RVS, .enabled =3D true}, + {.name =3D "u", .description =3D "User-level instructions", + .misa_bit =3D RVU, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1531,7 +1532,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), - DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), @@ -1647,7 +1647,6 @@ static void register_cpu_props(Object *obj) */ if (cpu->env.misa_ext !=3D 0) { cpu->cfg.ext_v =3D misa_ext & RVV; - cpu->cfg.ext_u =3D misa_ext & RVU; cpu->cfg.ext_h =3D misa_ext & RVH; cpu->cfg.ext_j =3D misa_ext & RVJ; =20 --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249260; cv=none; d=zohomail.com; s=zohoarc; b=Mf3yZ32ATyCC84rfj8pCNQTefT+BhdLWLG7CNqCdciC/OvzZGp3jXKp6/jS/izdG9Jx1efDObv/coCkn+rOKzyP7Wh4GlMp4IuMDCx31QNCEKA3n3UKMkCAZrAH0ri7H3P1l/hLzckLnNfPT3E2zSo8j4v41sr2Fwigt89YgaOE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249260; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fXtZPf1E6h+vYd9nupqfDNnVJU62rsNJUjgqDNMmw/U=; b=j7Bq+DDK6t7MhHPwnI3xCD8pfnAQFRhh1d4MvNnuCHpuhBezriSqpfxy8xbxh7THzHhB3ly3lbDKoKX1JteXXUiTH1PgBQ+pzAtkXsCNm5pg2iR8ixeMeUljTIrm0lU31ujeN4N8hib5U7BqWBqffsUVkgk8UNh0i1agv/bcmyg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249260158601.836607174189; Thu, 4 May 2023 18:14:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujtf-0002q3-UC; Thu, 04 May 2023 21:06:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujtW-0002Ck-BB for qemu-devel@nongnu.org; Thu, 04 May 2023 21:05:59 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujtU-0007cg-G7 for qemu-devel@nongnu.org; Thu, 04 May 2023 21:05:58 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1aaff9c93a5so8146655ad.2 for ; Thu, 04 May 2023 18:05:56 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.05.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:05:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248755; x=1685840755; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fXtZPf1E6h+vYd9nupqfDNnVJU62rsNJUjgqDNMmw/U=; b=AUQvFCk/lGwaa2XQzvOGs4gRAiGI80G4JdoW//BmGbKdok/45ww2jzwopGK5bGfdEW h6RsywY0jH9+fVkZmLAn4jqEclKBv6xC6KWV6RgIgjCZgiJdX/tjRCxh6SUNli7WxLvw mXmKW/gHTYLTSizBsZW6WDvDiHsWhFzIoJmXUI4PjsbUNo8hGpJDFlc9PvTbpPe3tKIZ b78mebhREKbF6JMK8U05CzVk4dSPQLOIEVedDldJZ1dbg7zAijEKPMPU/k+U3dUS+NFo lBrlKHWbrFWBt1knqNNkqPqr/hHwMdWqn2byqJSsNtpIvEpBRLpz25CABNYJUXfHZ4+L 6+tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248755; x=1685840755; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fXtZPf1E6h+vYd9nupqfDNnVJU62rsNJUjgqDNMmw/U=; b=lKxD9186r3AAETmePI4T+0hbzOXh7d40pKRvAYDYA+/O2Kqp1fKkq15aqPqLwebsaC zuT6vs6yLE7r8KJ40K9B642k9tu5x7wklpMsPkcy2uK+ykekUB3hQp+1ekCRuALQz2aF 4XIKwwfZPVwEnyNM7pXM4y8E9XucoBIuOHW8x7Q+HedoBBXBhtL6xXVAjeDvVKPS4G/u iVXJ3gyZjx5LE/1AFofC8DrAUwvIWygCDtEG5n4UT3lHFuzSgreDUbrW70Utp9JrsyUL dAptJOInrHAIOxL1pzP1skihKH+HafwxCIkT/Nf91RW/MMjZAqm1uPlpmCU1D+9e6OJF wp5w== X-Gm-Message-State: AC+VfDy3sCapsy4j6NqBlhKRFNLnt/+MCxifTVHchJ68nUQeJ0XG61Dz VEFBPdOvgQtL2nQMYMDZw7EXmJ8EBqLThg== X-Google-Smtp-Source: ACHHUZ494u5Y61Rrdo1pPCEfzOlZGMRpTLGW+xBMhOYFvYQfBeifcXGM8JU2NFO8scrafk+IHy6yug== X-Received: by 2002:a17:902:8f97:b0:1a9:2c70:e1eb with SMTP id z23-20020a1709028f9700b001a92c70e1ebmr5229366plo.36.1683248755039; Thu, 04 May 2023 18:05:55 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 46/89] target/riscv: remove cpu->cfg.ext_h Date: Fri, 5 May 2023 11:01:58 +1000 Message-Id: <20230505010241.21812-47-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=alistair23@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249260798100002 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Create a new "h" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVH. Instances of cpu->cfg.ext_h and similar are replaced with riscv_has_ext(env, RVH). Remove the old "h" property and 'ext_h' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-15-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/cpu.c | 10 +++++----- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 486061589e..823be82239 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -423,7 +423,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_h; bool ext_j; bool ext_v; bool ext_zba; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9565495839..6291224905 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -847,13 +847,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) { + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { error_setg(errp, "H depends on an I base integer ISA with 32 x registers= "); return; } =20 - if (cpu->cfg.ext_h && !riscv_has_ext(env, RVS)) { + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { error_setg(errp, "H extension implicitly requires S-mode"); return; } @@ -1172,7 +1172,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVU)) { ext |=3D RVU; } - if (riscv_cpu_cfg(env)->ext_h) { + if (riscv_has_ext(env, RVH)) { ext |=3D RVH; } if (riscv_cpu_cfg(env)->ext_v) { @@ -1509,6 +1509,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVS, .enabled =3D true}, {.name =3D "u", .description =3D "User-level instructions", .misa_bit =3D RVU, .enabled =3D true}, + {.name =3D "h", .description =3D "Hypervisor", + .misa_bit =3D RVH, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1533,7 +1535,6 @@ static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), - DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), @@ -1647,7 +1648,6 @@ static void register_cpu_props(Object *obj) */ if (cpu->env.misa_ext !=3D 0) { cpu->cfg.ext_v =3D misa_ext & RVV; - cpu->cfg.ext_h =3D misa_ext & RVH; cpu->cfg.ext_j =3D misa_ext & RVJ; =20 /* --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248915; cv=none; d=zohomail.com; s=zohoarc; b=WF3QwkAE7fXVK6uA4eEEnSFGOUPnWk0mS1R+sakIDfScdTdEgjbmIU9o+cE0Cku4afY4iwy1gcqLQW0LCvmdKnVzqv1nwEV/Nyd54KGjXkSsD3CH5jcgkE0wyUFnM17LP4g83mI/9gh0Pn3uS2P0jsOHb83wdNl46l3wwfpqVlU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248915; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=d5PHm+/0fHo5woJCY6EqmLZmNlnAPjLAIx4jrfLf5nI=; b=FbDP3TXGvEOKcJyHss5vDzW4nxS5V62zBnjchJc9q226UZzwEm55X8aP6GXQF7zwv4Q90RskaIaT5EAwbaqTMZoPx4WvcRocFzU8QNDVHtpDdutDkfv+IjmpW00hfcCeGPSNQNj/ASaK1jutn/QtOdioz0cYplvbcXeOgLzu8dg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168324891577197.33163730050308; Thu, 4 May 2023 18:08:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujtk-0003UW-31; Thu, 04 May 2023 21:06:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujth-0003CM-UH for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:10 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujtY-0007dV-4X for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:09 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1aad5245571so8033315ad.1 for ; Thu, 04 May 2023 18:05:59 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.05.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:05:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248758; x=1685840758; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d5PHm+/0fHo5woJCY6EqmLZmNlnAPjLAIx4jrfLf5nI=; b=boIiUE1KBvoAkfwTXKXmkZzE6ONoXcnQEJERd14G3I9YjNh97aoSj2kD5asDZrJrSX GuitXYvoi9LWWNz5DCwxmYkSKvrJg6H+x7GJGhzOfM2u9fUETqmd6qGRaNg96Fq8CtAj T59RAoU0tGBF3DvnFKd2rQr8kbbgOfzBOgng2fFZPqWesi/nNye7SGTQmXY7DS78Wggg bGw6Q6LyR53ak6VqvIg/UT8UqgRnhSbOz36rI9Z96eCAQLj4FmHSSi5xgTzcDO09gsg5 /anp0N5KxZVraaJUPzfbOvymt2eBjemUEmekSQDY4kJFpH1S370HYbcFDmrPOyvvGe8V fsFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248758; x=1685840758; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d5PHm+/0fHo5woJCY6EqmLZmNlnAPjLAIx4jrfLf5nI=; b=SI4Sxz0AAfkPXsTTbhgKUN+TfnXTEa4rDgzskZr7CFMtpNBH24TnPbxuanhtk2G6gY zXTyDZi7h/pxZQMyfZQwEZQKUVSs1NoWt2etfFlko1EPezs65tgfJnvzhC1qtVuMSj+U XEHS+5iDJdL6s+f5ITJmDrWOxi/WJoc/V2DMuOtb+Mrf2IX5Y5v0azAv4yVwQ+D9HmNP BrKUPi0EMyG/VvkgMv2Yu3VGxiWOA0Dc9PJHNnAfxqTfdSU9yOlQLcUdFvaZ9iCPdbO3 Q6i91WOk0IB0U45lsdFqSRGnk0LcriFBqZxvJDI7WV8yUY+L4iILedHM3K3VdiVrxHM3 FQlg== X-Gm-Message-State: AC+VfDwPACciW++obBfSwar9vfc3xBj30k1pkcYvfmeNA+aUxowMbsSm 5cocAOprQAc/Q2rwPYE0HdNMFGhrVc5++g== X-Google-Smtp-Source: ACHHUZ76Smpne7P0I1CkVRiOW4OLYbtq19bYeimOK9L3a6Qp4kebte8ABc28pSuzWtQtTOWeRbFZaw== X-Received: by 2002:a17:902:f691:b0:1ac:2cc6:296d with SMTP id l17-20020a170902f69100b001ac2cc6296dmr4450855plg.34.1683248758661; Thu, 04 May 2023 18:05:58 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 47/89] target/riscv: remove cpu->cfg.ext_j Date: Fri, 5 May 2023 11:01:59 +1000 Message-Id: <20230505010241.21812-48-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=alistair23@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248916519100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Create a new "j" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are replaced with riscv_has_ext(env, RVJ). Remove the old "j" property and 'ext_j' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-16-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/cpu.c | 6 +++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 823be82239..1aff93ba91 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -423,7 +423,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_j; bool ext_v; bool ext_zba; bool ext_zbb; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6291224905..3bdd6875a8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1178,7 +1178,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_cpu_cfg(env)->ext_v) { ext |=3D RVV; } - if (riscv_cpu_cfg(env)->ext_j) { + if (riscv_has_ext(env, RVJ)) { ext |=3D RVJ; } =20 @@ -1511,6 +1511,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVU, .enabled =3D true}, {.name =3D "h", .description =3D "Hypervisor", .misa_bit =3D RVH, .enabled =3D true}, + {.name =3D "x-j", .description =3D "Dynamic translated languages", + .misa_bit =3D RVJ, .enabled =3D false}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1607,7 +1609,6 @@ static Property riscv_cpu_extensions[] =3D { =20 /* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), - DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), =20 DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), @@ -1648,7 +1649,6 @@ static void register_cpu_props(Object *obj) */ if (cpu->env.misa_ext !=3D 0) { cpu->cfg.ext_v =3D misa_ext & RVV; - cpu->cfg.ext_j =3D misa_ext & RVJ; =20 /* * We don't want to set the default riscv_cpu_extensions --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249553; cv=none; d=zohomail.com; s=zohoarc; b=IfoYo0IwtFc+ZnCs40VKJkWAJ3TjLD+xD9cLmFEhJZy+hIT4uem6R5UI3KFCCW8s7c43IcatZVNVurDkk90tJL6A8Ui2UxM8PgfhTCGC7PM+omplduUiizHXAfg/qbcb6U3OAgpODQWLPMi4lC96lHf6J6jHgW/jkJlGiYOI2pU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249553; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uGV9M7Q3fySnRT5Y8OU1Bm9pFj5qXHNKBUX8c4QcSuQ=; b=bcrUOJ7tWU22+zoRGm9I4i6bMVGTZUlNsSxSLprlqIEFq9raCcSZlM1jraW3aQ3r5GaOShCYgzbll6gYwiM/T1BgSazsQPknmGYeSxXyvoQtko5cqxyDvkrslOy/wDwv9xMaudXzn/dgTTN+Lbp2SkWIO344qLdDkHcKOddA6lQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249553799573.5302732888343; Thu, 4 May 2023 18:19:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujth-00036y-Dy; Thu, 04 May 2023 21:06:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujtd-0002Zu-VH for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:05 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujtc-0007e0-01 for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:05 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1aae5c2423dso11257675ad.3 for ; Thu, 04 May 2023 18:06:02 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.05.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:06:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248762; x=1685840762; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uGV9M7Q3fySnRT5Y8OU1Bm9pFj5qXHNKBUX8c4QcSuQ=; b=qQhRSYf4EiFyDRjq9TSbVH84i0fvA7mnA7asxXpEop679Y43vgT8HUGmsevpBeqJOt ZUrMD4sj5sntbZBM5o8dZr++6W4EMcLwZnsNy6AG6UdlNvh81QMAEKCDMPv6xmaby+kG e+32lD0B5lLfR2gAqu+mirBvUK1C5D0n6r4NklDJ9F12+fD3AX9HBBCvuEOrUcvUNlU0 Mjknf1r3rMi7rCnrLfgp0olCb10mHfISH9AKJlRA+YMe6txGIBaVg8nL7rN56pzdyT8D X5KMQsngfUiMTbQeYMZ+DQpsej5wLL73pfwupCYLeeDjZVEqB0MHL/FO2g9qTkSvvHUh N3VQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248762; x=1685840762; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uGV9M7Q3fySnRT5Y8OU1Bm9pFj5qXHNKBUX8c4QcSuQ=; b=YI9yLqX7h94YnvwwlT0fjqFYGgQ/nbrq/j/A9MLQNrD+CHh0ezeeGcWJ0IG7/78kUA BhUQRuRBS8Jt/agfil55K4ajXsEGOSqfzKsaL1I0Z4HVY2Y865R3waQvU2t7GGOKtJTh XV7vglEE2F2QfwZWPfaQfE2vZvmGs1tflHucoCJT3uaXJBbUVo2SVzHlur/bNXmzrCVf R5QSWD1c5kLg8DtHbRcpWaM8uxyRg5wgki3KT9dVWeYzR4VH5TGOsPQq7mEX1kKGPk9C FBXinvll5oTksMZwG6nIqf64JJvUouWZ+mTRhjpHvw1WUfIaJDVvQqGc+PyixNqg9kce iXyA== X-Gm-Message-State: AC+VfDxr/4frA6ErwmqEHi7VzoF89EyIMNy8uO02SqXqX22QFU9IBSYf UWsfu/hOMCa4CTKViE4ZH/+4ktvQiKnZ4w== X-Google-Smtp-Source: ACHHUZ5EOD1wYl80wWEvaBLliljsH2NNdVCpgP7cjsbRqs0vfBtLxTLeO2VDRO7x7/RepCDC9up9Fg== X-Received: by 2002:a17:903:22c1:b0:1a6:82ac:f277 with SMTP id y1-20020a17090322c100b001a682acf277mr6509208plg.14.1683248761694; Thu, 04 May 2023 18:06:01 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 48/89] target/riscv: remove cpu->cfg.ext_v Date: Fri, 5 May 2023 11:02:00 +1000 Message-Id: <20230505010241.21812-49-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=alistair23@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249554587100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Create a new "v" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVV. Instances of cpu->cfg.ext_v and similar are replaced with riscv_has_ext(env, RVV). Remove the old "v" property and 'ext_v' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-17-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/cpu.c | 12 +++++------- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1aff93ba91..e011cf6ca4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -423,7 +423,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_v; bool ext_zba; bool ext_zbb; bool ext_zbc; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3bdd6875a8..13ff37250e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -883,7 +883,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) } =20 /* The V vector extension depends on the Zve64d extension */ - if (cpu->cfg.ext_v) { + if (riscv_has_ext(env, RVV)) { cpu->cfg.ext_zve64d =3D true; } =20 @@ -1018,7 +1018,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) cpu->cfg.ext_zksh =3D true; } =20 - if (cpu->cfg.ext_v) { + if (riscv_has_ext(env, RVV)) { int vext_version =3D VEXT_VERSION_1_00_0; if (!is_power_of_2(cpu->cfg.vlen)) { error_setg(errp, @@ -1175,7 +1175,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVH)) { ext |=3D RVH; } - if (riscv_cpu_cfg(env)->ext_v) { + if (riscv_has_ext(env, RVV)) { ext |=3D RVV; } if (riscv_has_ext(env, RVJ)) { @@ -1513,6 +1513,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVH, .enabled =3D true}, {.name =3D "x-j", .description =3D "Dynamic translated languages", .misa_bit =3D RVJ, .enabled =3D false}, + {.name =3D "v", .description =3D "Vector operations", + .misa_bit =3D RVV, .enabled =3D false}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1536,7 +1538,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), - DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), @@ -1638,7 +1639,6 @@ static Property riscv_cpu_extensions[] =3D { static void register_cpu_props(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); - uint32_t misa_ext =3D cpu->env.misa_ext; Property *prop; DeviceState *dev =3D DEVICE(obj); =20 @@ -1648,8 +1648,6 @@ static void register_cpu_props(Object *obj) * later on. */ if (cpu->env.misa_ext !=3D 0) { - cpu->cfg.ext_v =3D misa_ext & RVV; - /* * We don't want to set the default riscv_cpu_extensions * in this case. --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249392; cv=none; d=zohomail.com; s=zohoarc; b=G3h+wYFDlpqxiV1kxV+OPOcc8wxMlGK0l0BCXGYAJqBZBCPLePmtxh3LH0maECFs0UHISev4U073Cv4u59meUJTOuY1oxxj0nIVNIlqQcR9wgVMnqjNjwkln+9hJo+sXq5c717g7m0X0ieSN25cmCkk+qN2fdKo1Yr+KHbjBY/A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:06:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248765; x=1685840765; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j0qdCGr5H/dXi5GZTnoaSiKG2ZdRv1O4vEZjYe7CLHE=; b=cFO9e48jajhGg8KVjk2iedPjaw20Fzq5tKRO0qLdEzcontK7B3NpD498m4CAo8/OeB On8EJS28b/ea+qpACoVsBxIzWHojAY+HPJWk0TxCIWYXxvl/oCDBvKZRDutZP/ra3GdB ebg737vJzMsBnuDJz0wY2+e7PrbbAwmgW7i3b72gSX1ad14Omgjpp9vGGO+lzSv92zi9 dsAuyCFmFOxbVa0qgMBxMQzAZ5uhWs4IZ+WREoWjmTT+f1KTOVb2f97GQTKJjqDkryP6 +1xw3H15VtvPTuuLnIzEcoAMF9A/hVCfuSyNOhcKp0SN+gsJ89/MP0+az3ftywt/Ezru 1RJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248765; x=1685840765; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j0qdCGr5H/dXi5GZTnoaSiKG2ZdRv1O4vEZjYe7CLHE=; b=JwiBvuCYuxv79fyv/C9GMzHl2853wt65yUn+j/p9AuK/Wo57lByXRAJII3nWErrOO9 ArtlprZuGX2au+HDgd/opK27/aC60FmchxLHJ9rtV4I/O6hDDHEmG7ZRxRK3hLTGKOhO +3aHr7kdl7QXt+9UbWKJjgAlwBMiGt8XFt7VxMCKN8xsQr5vnDSNErQVa56CN9K4GV+K SdQ0E+A1aFuXXF0S/bBmRFBZXNznzsWfS6vT8KNQkgLE+ERmFp0SlR6+8qL0F2cUkNLy s8bw2FBxYH989ECVtUuKRF8SP2xPvOPZw1qROE+GwyMLrgyCH2LricrXvZN69vlOrsGC Z2gA== X-Gm-Message-State: AC+VfDxNjAlg6gMmhN+wTvciboUHMCXZyxXad25tGYsb6z9c9zBLlGQ2 /lSUMGsVLuBrlqLypQRBymoor1cghtQL6Q== X-Google-Smtp-Source: ACHHUZ7XSfKzqvHa0j/ucS/pAnDOV5zUEZxCTfo8UwZ1Xj8N5vwL04dWfBoYbDocMXwqWOc8oBsxqQ== X-Received: by 2002:a17:903:187:b0:1a8:1320:133 with SMTP id z7-20020a170903018700b001a813200133mr6530699plg.51.1683248764870; Thu, 04 May 2023 18:06:04 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 49/89] target/riscv: remove riscv_cpu_sync_misa_cfg() Date: Fri, 5 May 2023 11:02:01 +1000 Message-Id: <20230505010241.21812-50-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249393410100007 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza This function was created to move the sync between cpu->cfg.ext_N bit changes to env->misa_ext* from the validation step to an ealier step, giving us a guarantee that we could use either cpu->cfg.ext_N or riscv_has_ext(env,N) in the validation. We don't have any cpu->cfg.ext_N left that has an existing MISA bit (cfg.ext_g will be handled shortly). The function is now a no-op, simply copying the existing values of misa_ext* back to misa_ext*. Remove it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-18-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 52 ---------------------------------------------- 1 file changed, 52 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 13ff37250e..1ecb82bb5d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1141,50 +1141,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cp= u, Error **errp) #endif } =20 -static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) -{ - uint32_t ext =3D 0; - - if (riscv_has_ext(env, RVI)) { - ext |=3D RVI; - } - if (riscv_has_ext(env, RVE)) { - ext |=3D RVE; - } - if (riscv_has_ext(env, RVM)) { - ext |=3D RVM; - } - if (riscv_has_ext(env, RVA)) { - ext |=3D RVA; - } - if (riscv_has_ext(env, RVF)) { - ext |=3D RVF; - } - if (riscv_has_ext(env, RVD)) { - ext |=3D RVD; - } - if (riscv_has_ext(env, RVC)) { - ext |=3D RVC; - } - if (riscv_has_ext(env, RVS)) { - ext |=3D RVS; - } - if (riscv_has_ext(env, RVU)) { - ext |=3D RVU; - } - if (riscv_has_ext(env, RVH)) { - ext |=3D RVH; - } - if (riscv_has_ext(env, RVV)) { - ext |=3D RVV; - } - if (riscv_has_ext(env, RVJ)) { - ext |=3D RVJ; - } - - env->misa_ext =3D env->misa_ext_mask =3D ext; -} - static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) { if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { @@ -1228,14 +1184,6 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) set_priv_version(env, priv_version); } =20 - /* - * We can't be sure of whether we set defaults during cpu_init() - * or whether the user enabled/disabled some bits via cpu->cfg - * flags. Sync env->misa_ext with cpu->cfg now to allow us to - * use just env->misa_ext later. - */ - riscv_cpu_sync_misa_cfg(env); - riscv_cpu_validate_misa_priv(env, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249335; cv=none; d=zohomail.com; s=zohoarc; b=Z7W0FU1u27XqrUFeL0eaYGyPyMSH5fnmaQ0sBb+mKWfBAhfOmaOyGRnCwF08vEbOGFsqG/Gr1ht6McGAK/hs8pacZYqJbyKuVKWhdnFo9ha9QL2tMR0tIHjppWzHygrOtOXoM2jAff/MNoV8DzzkyjpeAd8oU4OKuvrQoR9ZI04= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249335; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0X8g131CVFq/pjT+ErsV8dyrgFnoRBEg/6IUxaJk6ls=; b=doiA2hwZIyBkXYasS6ZdehHb0IpdVhcFiy7ngzqB7Vo5/sjteegErJkH1UDHPK7xUxfWlgh544r+yLqD+wj9cHhHyE+Ov/6mUmbBoi38scE95n8VyIDf7BlXqYHn0MYGs+5ksCKO3jtj+L05hkMljYvb3AXHlcwkLuK8uNoOsJA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249335360251.29049678431738; Thu, 4 May 2023 18:15:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujtv-00059J-1g; Thu, 04 May 2023 21:06:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujts-0004oV-P5 for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:20 -0400 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujti-0007fb-8t for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:20 -0400 Received: by mail-pg1-x531.google.com with SMTP id 41be03b00d2f7-517ab9a4a13so960522a12.1 for ; Thu, 04 May 2023 18:06:09 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:06:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248768; x=1685840768; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0X8g131CVFq/pjT+ErsV8dyrgFnoRBEg/6IUxaJk6ls=; b=ORB76+x5Oes4m/e49uVa1Zrh82qgY1We3nN223kVEAdrwARfWhNaBoYevGAWkpe/5C oYLQX3eQRu3xbpdItiajTb2EWAPrBk1IT6qA1rD/+/K118Fj8J/+6crkvqcH2yZgIn0x zgJjS+d3oBseWUk9NFk2/j0Q5iWyfUz5nuqsU8Z9twy/QdXScu0GkFs7VH/3uIkjB/6W s5dxVFvv39ZQKpXK8I5kahOkrirX6nr+9BFJkNoi4/DP/Km8sCgNpx5MuccTMH6BenDN LU4gevYP3O2aPEmxKA5439HLeNqFiGsfCgWEqWGfptgRkQKaJMwcneKNG/2wldaW5U4z M/6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248768; x=1685840768; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0X8g131CVFq/pjT+ErsV8dyrgFnoRBEg/6IUxaJk6ls=; b=lzD1rkoI2I6bFO2wbDPPMxrdYmIHRYsrLy92WflQytzbMo2Pf7VVtWvPC0eNFJ2sBx Ig7BVZaKnSEvYLzJpNBDNxM4KlXs1ecyo6y/E0385j7Pu8xURMtiOroRHXPPiLTti7Oy tFrews3ASzaMXztK5w6ZHLdJbGQvdX632ZLEYndAcRwfOZgwU70sUBvOzXFtSKjUDIBs DIvlnCUq1UJX17YdvH0nX8G6yrWpbQR2Nuvh2MVrrspAbVwEjoeqK5ThF8NLrBEo4pGl rmySCeJ8ZGQCtcY03UgQx5MTBYdzqv01S828sigxvm1BICA+l+gbXS8lsoC6ur2QWWj6 aJEg== X-Gm-Message-State: AC+VfDzesTafR4fKhYOe6Yprp2KYdteBn9Zzt87WCXu5AKVbzdSpVtXy SJqt/sd8rO6MUJ6SZWCccUT/DJr7SvB2Tg== X-Google-Smtp-Source: ACHHUZ5ldR+D09E5oU+fwo8dL2+8v91uPEPfzqRqA9K7JTQaDJPKailCIp9R6mwk9aueSPNewg3ikw== X-Received: by 2002:a17:902:ab83:b0:1aa:fdab:24a5 with SMTP id f3-20020a170902ab8300b001aafdab24a5mr4776539plr.10.1683248768100; Thu, 04 May 2023 18:06:08 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 50/89] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init() Date: Fri, 5 May 2023 11:02:02 +1000 Message-Id: <20230505010241.21812-51-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=alistair23@gmail.com; helo=mail-pg1-x531.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249337362100007 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza This CPU is enabling G via cfg.ext_g and, at the same time, setting IMAFD in set_misa() and cfg.ext_icsr. riscv_cpu_validate_set_extensions() is already doing that, so there's no need for cpu_init() setups to worry about setting G and its extensions. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-19-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1ecb82bb5d..b005bcb786 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -403,11 +403,10 @@ static void rv64_thead_c906_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_misa(env, MXL_RV64, RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_11_0); =20 cpu->cfg.ext_g =3D true; - cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_zfh =3D true; cpu->cfg.mmu =3D true; cpu->cfg.ext_xtheadba =3D true; --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683248973; cv=none; d=zohomail.com; s=zohoarc; b=n0Fu3Er6+5xpUR5k0T59qonGUppx8WVvqyXZzlg+LTGgIrEEr5jzHUFkoQK00iAL0VeLJTbOiHxXh/8UkMto7Pw1NlCWx0O2NAYIksyMc6emvZauKIQoVdtHLIcTEuMi+Mr+Pc2wSffZiL6Aktie75ZyQf8fNoEDx5Xaxk0aWW4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683248973; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=r7PYDlMmen8qFAQjWPuusLTWBhWo0OdwyZiWfqo+jQs=; b=jt8c8tdFH4ds5KeAWhge4emSJ+69bJ0kbl+dBF7gmltNl+DN+tAr8kmBFFBVeBFEGbIgSM12WTFl3H6yChCZ4uUEgMpAcOA4jc4xxjYeOm1I3JfVBcDXC2gU+94ipmsQ7ymo4125fAvOBhMk1J5OzwTugw6TLapzzwcf7PFFWaQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683248973468384.5313663250813; Thu, 4 May 2023 18:09:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujto-00042n-DH; Thu, 04 May 2023 21:06:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujtm-0003qc-Qx for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:14 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujtk-0007gH-QF for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:14 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1aaf7067647so8240185ad.0 for ; Thu, 04 May 2023 18:06:12 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:06:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248771; x=1685840771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r7PYDlMmen8qFAQjWPuusLTWBhWo0OdwyZiWfqo+jQs=; b=BI11k2ETIbJpayY+dAGdcOVkaPTrTfQFi01OK6ZcKqXvXN2rtCPm0usVEgZFzujpCL 0naYr7bMhIw0YCBbTN07iLSvk1YuP8OWkGOqs5s2wmVyu6zpRmVhdIMGikfivTfFaHg+ rfEj2LpyM9iG1CQQYni9cVC+WKrn6Qy3f6eYn/EiC82/VhLC4wamZ3WXXbSXTI7NhWGl 2fL/BGeQmbPSXY/SymTFXEC+IfVgHxYyUOm2Tag6CBtWzNrr0JA1o8uKTDTnE4ljsYHR afWXaCtHgacNWHSsXcrWOQY+7T9mbI0rNoYnOZ98hdmkpUhRkK3Q757r6ogNlvMxXWMw BXww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248771; x=1685840771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r7PYDlMmen8qFAQjWPuusLTWBhWo0OdwyZiWfqo+jQs=; b=fRLUHNUtgBrrg7Li15kbw+CEbtMU6amBInfBJkB8ISEbj6kTqnaEMecGJAc2+HF4Lx u68aeykwj64mFrYfaHBekLa4U3c7SNS++ilJbNmN6WQSN4Mf6pU73Spi/txK3NE7dwjl mxIog6caoSjd39rc5jCWOUE/hwNd6CXlP7Mfqz+vF3+YwvpxMJl7V9bdukkwR9DXSf8I Lme39J21d/WRshDXkbzeUr+AFQBbD3ZBTf9rmvgVnvpxl/H7Skjnx1oplPiRcZUzBnk8 fNWx6efcpk/X0mm09J47Z4zkSiWtoV2gKxHDlU8ERzKPAPqbz0kLMuyfn6+0b2WvURoi TGBg== X-Gm-Message-State: AC+VfDxlg/K3l8HYCVWVHrQfvxzXLJiErqbTnng1CwKr2NDPSQ9ie6G/ K/UJrDqpvOCxyzmLL6V8e2Iilk5eoeUOoQ== X-Google-Smtp-Source: ACHHUZ6GBiT86EWHjXmQqjLjsSoiWH+i8aM9M3vqVub5ZKOA0nS+jojTHfDBt9lQ4EQJ38a6xdr4VA== X-Received: by 2002:a17:903:4d2:b0:1a6:b1a2:5f21 with SMTP id jm18-20020a17090304d200b001a6b1a25f21mr5374000plb.8.1683248771252; Thu, 04 May 2023 18:06:11 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 51/89] target/riscv: add RVG and remove cpu->cfg.ext_g Date: Fri, 5 May 2023 11:02:03 +1000 Message-Id: <20230505010241.21812-52-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=alistair23@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683248974812100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza We're still have one RISCVCPUConfig MISA flag, 'ext_g'. We'll remove it the same way we did with the others: create a "g" RISCVCPUMisaExtConfig property, remove the old "g" property, remove all instances of 'cfg.ext_g' and use riscv_has_ext(env, RVG). The caveat is that we don't have RVG, so add it. RVG will be used right off the bat in set_misa() of rv64_thead_c906_cpu_init() because the CPU is enabling G via the now removed 'ext_g' flag. After this patch, there are no more MISA extensions represented by flags in RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-20-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/cpu.c | 17 ++++++++--------- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e011cf6ca4..070547234b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -81,6 +81,7 @@ #define RVU RV('U') #define RVH RV('H') #define RVJ RV('J') +#define RVG RV('G') =20 =20 /* Privileged specification version */ @@ -422,7 +423,6 @@ typedef struct { } RISCVSATPMap; =20 struct RISCVCPUConfig { - bool ext_g; bool ext_zba; bool ext_zbb; bool ext_zbc; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b005bcb786..143079a8df 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -403,10 +403,9 @@ static void rv64_thead_c906_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV64, RVC | RVS | RVU); + set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_11_0); =20 - cpu->cfg.ext_g =3D true; cpu->cfg.ext_zfh =3D true; cpu->cfg.mmu =3D true; cpu->cfg.ext_xtheadba =3D true; @@ -814,12 +813,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) CPURISCVState *env =3D &cpu->env; =20 /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && - riscv_has_ext(env, RVM) && - riscv_has_ext(env, RVA) && - riscv_has_ext(env, RVF) && - riscv_has_ext(env, RVD) && - cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { + if (riscv_has_ext(env, RVG) && + !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && + riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && + riscv_has_ext(env, RVD) && + cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; @@ -1462,6 +1460,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVJ, .enabled =3D false}, {.name =3D "v", .description =3D "Vector operations", .misa_bit =3D RVV, .enabled =3D false}, + {.name =3D "g", .description =3D "General purpose (IMAFD_Zicsr_Zifence= i)", + .misa_bit =3D RVG, .enabled =3D false}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1484,7 +1484,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) =20 static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ - DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249559; cv=none; d=zohomail.com; s=zohoarc; b=VbftHg+X8lw60f7UMpc8T5qLiwoJPnoFI/rlSa5ScZfIOE3lon+iWyycUQ7+VOfSlAio0dOrTowcRxjIlXMwcqi6pGo0JbaMgwNdfGmOloHFBbvcPa+wAtnOQzLuh+GxxTDVuyPvOkYSk/IuoJ2qYgpabk2WoAZINViFY2CLwck= ARC-Message-Signature: i=1; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:06:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248775; x=1685840775; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HTfWHY5TryJq8HJkmtFzq6CI0tu47ICZjv1qVc4hQog=; b=sGjNI978PxN+oW0dnMasX8RVDMicL/nmuMMEVgoPIsXj6TDgqKYop8sb7fF7ONXaOK ovL2Oo0W8kznnkx71DFiSYU6DImvjKNrNsYCMPrdaWFv4whnMmi5Tmq4jq8jTtKqwvNz MywrB75Un289MVaeCIsmpMaqV6OQNHig/vFkSNUr7opFZFjEfuDJaipPcjEKutzgoXjo ifQdp1pdwQPMjGzEFd1iq8pL+R/bQMeQlfxsAJKAB46a79IIeT/zFKqMfZZo/2SSPT6a fJYpSVVML7bP+UlUYarK9z0SDV/SbLktbOxZ0Wun5FJmnBmivQIWdGb/FWTwCnYVCu0k x9pQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248775; x=1685840775; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HTfWHY5TryJq8HJkmtFzq6CI0tu47ICZjv1qVc4hQog=; b=DEUoxrrphu7Bueh94GpYnCJbXZut1YBnw7KplKoSQVvgXESlr9KoMZrPP5ruCCZ4HM DWA02LtCrbM0yiYC/JXkeF6RAbH5bCzThDXlsrAHtTGgMIofefMiCFTIAr+dTYsUl+Rp iSj9WHVy+kCkGsBSC/+Oz/q9cUW7/jAvKwMkz6/0PEiCzpWDrmYZk8iOgE2KkQqTpeKU NyVPKuIs8CmooCaZPLRMPhe3mHblqfCfJT93TbQkd0XLV4sBJf0nutMhc4T0FiznyiP3 GAbByoA0OUan9YRJlVOIkLtymJe/EX5yKtBzVuFtCaTiFsMJk82a3lsI6xz3/3fxFeV+ W2yw== X-Gm-Message-State: AC+VfDwbcOq4BtX2m3f5hrFP+4sGiw2or0+q3Eid45CBW2zzyLsQ+8Cq RmJOmIeWLbwd7EF4SuCt4pdvsfCiSYTuKA== X-Google-Smtp-Source: ACHHUZ6L8Pcmquin163JySIBIWg28kr778Iwpwo03QEhW2fNZapr3Sc2W46W1SRguC2QDo+8bxEYhw== X-Received: by 2002:a17:902:c40b:b0:1ab:28ec:bf10 with SMTP id k11-20020a170902c40b00b001ab28ecbf10mr7263927plk.51.1683248774662; Thu, 04 May 2023 18:06:14 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL 52/89] target/riscv/cpu.c: redesign register_cpu_props() Date: Fri, 5 May 2023 11:02:04 +1000 Message-Id: <20230505010241.21812-53-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=alistair23@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249561054100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza The function is now a no-op for all cpu_init() callers that are setting a non-zero misa value in set_misa(), since it's no longer used to sync cpu->cfg props with env->misa_ext bits. Remove it in those cases. While we're at it, rename the function to match what it's actually doing: create user properties to set/remove CPU extensions. Make a note that it will overwrite env->misa_ext with the defaults set by each user property. Update the MISA bits comment in cpu.h as well. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230406180351.570807-21-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 5 +---- target/riscv/cpu.c | 41 ++++++++++------------------------------- 2 files changed, 11 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 070547234b..f47c3fc139 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -65,10 +65,7 @@ =20 #define RV(x) ((target_ulong)1 << (x - 'A')) =20 -/* - * Consider updating register_cpu_props() when adding - * new MISA bits here. - */ +/* Consider updating misa_ext_cfgs[] when adding new MISA bits here */ #define RVI RV('I') #define RVE RV('E') /* E and I are mutually exclusive */ #define RVM RV('M') diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 143079a8df..d1769fd218 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -228,7 +228,7 @@ static const char * const riscv_intr_names[] =3D { "reserved" }; =20 -static void register_cpu_props(Object *obj); +static void riscv_cpu_add_user_properties(Object *obj); =20 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { @@ -356,7 +356,6 @@ static void riscv_any_cpu_init(Object *obj) #endif =20 set_priv_version(env, PRIV_VERSION_1_12_0); - register_cpu_props(obj); } =20 #if defined(TARGET_RISCV64) @@ -365,7 +364,7 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); - register_cpu_props(obj); + riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); #ifndef CONFIG_USER_ONLY @@ -377,7 +376,6 @@ static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); @@ -390,7 +388,6 @@ static void rv64_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY @@ -436,7 +433,7 @@ static void rv128_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); - register_cpu_props(obj); + riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); #ifndef CONFIG_USER_ONLY @@ -449,7 +446,7 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); - register_cpu_props(obj); + riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); #ifndef CONFIG_USER_ONLY @@ -461,7 +458,6 @@ static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); @@ -474,7 +470,6 @@ static void rv32_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY @@ -488,7 +483,6 @@ static void rv32_ibex_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY @@ -503,7 +497,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY @@ -521,7 +514,7 @@ static void riscv_host_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, 0); #endif - register_cpu_props(obj); + riscv_cpu_add_user_properties(obj); } #endif =20 @@ -1577,30 +1570,16 @@ static Property riscv_cpu_extensions[] =3D { }; =20 /* - * Register CPU props based on env.misa_ext. If a non-zero - * value was set, register only the required cpu->cfg.ext_* - * properties and leave. env.misa_ext =3D 0 means that we want - * all the default properties to be registered. + * Add CPU properties with user-facing flags. + * + * This will overwrite existing env->misa_ext values with the + * defaults set via riscv_cpu_add_misa_properties(). */ -static void register_cpu_props(Object *obj) +static void riscv_cpu_add_user_properties(Object *obj) { - RISCVCPU *cpu =3D RISCV_CPU(obj); Property *prop; DeviceState *dev =3D DEVICE(obj); =20 - /* - * If misa_ext is not zero, set cfg properties now to - * allow them to be read during riscv_cpu_realize() - * later on. - */ - if (cpu->env.misa_ext !=3D 0) { - /* - * We don't want to set the default riscv_cpu_extensions - * in this case. - */ - return; - } - riscv_cpu_add_misa_properties(obj); =20 for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249513; cv=none; d=zohomail.com; s=zohoarc; b=cSw2rvNwnFhAbbzgKih3S/Am+SOobSjLcyI27iK0TFhRa/ec6pr3IUaXzk+99LIV2K8hjFSKL1lkMQ4D/xANHsMYBcQTeT8R4Dx3+m2oC5uDwMbQoV0uJa6hv3WrGE3CTli8X2WZCloXpndeCn9ztyIEDPdNyboQihJGklQoaVA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249513; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nGEnLprJBACbjqSpRTZ1KffttqllnbujSuQyuZ/EBCA=; b=YjRjXlSojlAXDzZ7b3FECORpXNhQKzPg8wshKT5ATT9veOofk7jV2eh4p0sBqzq7eYL4O7zthpYH7IA/DQayD3YGQyGCoX8h2tVMdhwdpV5VlMoe05Xl8IpHMt10p6nB8etyNUrr2ByWPJMHwTA53vGgdXFijhpbur3yT+Gm2NU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249513024996.0168935236094; Thu, 4 May 2023 18:18:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujty-0005pD-0D; Thu, 04 May 2023 21:06:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujtu-00055c-7c for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:22 -0400 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujtr-0007hY-9F for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:21 -0400 Received: by mail-pg1-x52e.google.com with SMTP id 41be03b00d2f7-52867360efcso750932a12.2 for ; Thu, 04 May 2023 18:06:18 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:06:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248778; x=1685840778; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nGEnLprJBACbjqSpRTZ1KffttqllnbujSuQyuZ/EBCA=; b=QAj6yw0zuWVDsd8HTqSaYqjpDP1fYsRCAB/trSd3nNyRb+ou6HlRHXoPJhTz9s3pMu wFQ6OynUYDNrohBeKcNHqc8dypcEIn5Y19bieFZjdDTuaUPqk7el3rJxItPXsjIxTDiV xG6WZNl4GYwqprTsljClq1lXnQIHzXHhOYyXGVC7mcKiUZGZV/CoAon9kBPsp9UPRtcq SXitMor4wK2JkXcD3lri/4VTNo2wJPpc548OR3k0Q17XwAVgSc2RqpuqmNp7TOPwEFzI klIgUwQG/PNGBwHER2lzouhfusCtPjt3ezVCmys3fH1X/PbE7L7vbU2eib5Dka/tjT/m DAvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248778; x=1685840778; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nGEnLprJBACbjqSpRTZ1KffttqllnbujSuQyuZ/EBCA=; b=gxBef2IujZAE6VAg0CAyxctcaw+DF8ByGZu+y5e7cHIcswn8gNR9H4gWkLh3FVOFrT dPjz5qHI1MNS2ypUUo6kmgjNFNrFBCIatCNMFt7e6CczKNevxcTfFD+YTLjbMejn1Fl1 wGfsUmP+BVhJKNWJSytbNDV9Ejz/oxiFY5xPLomtJbg/JsHYk7z7i2rz6tsdqDsyPPFG 3fhJ5tQXEhGzFpKzUq+yZQ25u/keCTw2RxmKHTpu6/u5y14/jH88ATJFwnw7XGsqsJmH RSXoqtg8xMTshpIDA7OD5hKOu6Eqqjce/KhN9GgXLMXlble8+ZBJjM+43B2pPnME5Fkg YBow== X-Gm-Message-State: AC+VfDyMjr5CiZWqmRrWpd9KR48QaZUhac/OY/gMLb+icHDFMA+ejWA0 2zq8drMY/I1VFeovMptgND2E+gejPpkDnQ== X-Google-Smtp-Source: ACHHUZ7k5ofpdPr0lZs+ogP9BYIo2Ktyc2lTvkSwe4XvMkJirc+v/MIRhLKswAhg+Za2HNQwlg6vnA== X-Received: by 2002:a17:902:e5c8:b0:1a9:465c:6800 with SMTP id u8-20020a170902e5c800b001a9465c6800mr6670392plf.12.1683248777743; Thu, 04 May 2023 18:06:17 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Alistair Francis Subject: [PULL 53/89] target/riscv: Fix the mstatus.MPP value after executing MRET Date: Fri, 5 May 2023 11:02:05 +1000 Message-Id: <20230505010241.21812-54-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249514931100003 Content-Type: text/plain; charset="utf-8" From: Weiwei Li The MPP will be set to the least-privileged supported mode (U if U-mode is implemented, else M). Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Message-Id: <20230407014743.18779-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/op_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index ec9a384772..b8a03afebb 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -338,7 +338,8 @@ target_ulong helper_mret(CPURISCVState *env) mstatus =3D set_field(mstatus, MSTATUS_MIE, get_field(mstatus, MSTATUS_MPIE)); mstatus =3D set_field(mstatus, MSTATUS_MPIE, 1); - mstatus =3D set_field(mstatus, MSTATUS_MPP, PRV_U); + mstatus =3D set_field(mstatus, MSTATUS_MPP, + riscv_has_ext(env, RVU) ? PRV_U : PRV_M); mstatus =3D set_field(mstatus, MSTATUS_MPV, 0); if ((env->priv_ver >=3D PRIV_VERSION_1_12_0) && (prev_priv !=3D PRV_M)= ) { mstatus =3D set_field(mstatus, MSTATUS_MPRV, 0); --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249561; cv=none; d=zohomail.com; s=zohoarc; b=m95d28QC7zEj7B25OPFTiWA2DZEKZ3UEr43vfpFmJA0ztHyf04nnIT3Uzlj3uJJhAJlIX/A7aRDikBroelVq1lcthROibEpXymNuoq3vfkTUCMOoFCj67ErP0GwgmWwohuHHu4td+6eVsgz6K0cAQGb+MzUBrNUBQY9iq6QZYPg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249561; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xZGjFNLoqqGuNOvjc//J6vmOrtdne6dPztqTW31lhQM=; b=QYqIpvi0UOXwzsHTGhp5l8MOjmNdUztsIWQEsLX0jRjLWap7JcqpzEC1NHzmeioBpjUiUnZxZiAl5oSUw60eDUDN/jtjViG9omQlsfpIG+PciY4zucOVNFNbJzq9Q9qdiGGm26IdBlS5pIblbiUDZ9XJn6FxvJ9oAChHbdm+ktw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249561227751.3187071515633; Thu, 4 May 2023 18:19:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujty-0005z2-Ua; Thu, 04 May 2023 21:06:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujtx-0005jX-9Y for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:25 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujtv-0007i3-1o for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:24 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1aad5245632so8442635ad.3 for ; Thu, 04 May 2023 18:06:22 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:06:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248781; x=1685840781; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xZGjFNLoqqGuNOvjc//J6vmOrtdne6dPztqTW31lhQM=; b=hJ8flvXhg7JJ+3jwRbPXw1pR73KPPs+h8A+GpcjmledHZnsCeN0JTr+9skMxRxJwRt VJLrXWOij2Opegxxq7bRrq5I5yST8k+HzuWQ8OPNbannggKtoxYKSyFFonmRFHiM/G6E 1vMvWrgeFFlUJJPgVUu0xiaUeLtYw8OQyb2+rEBJJmRAyhXSev3MSy7Stq5ciH2ymCEK hXPmE9k4ycNwQBTy29JpD+qbMCJUHxwBKoXHbkSF5GoxQg5cB7GAbgFrq5R5sXr7gEw7 Yy0l/GEghFCy5Gnvv4TM9yWAD8MVK8IiU3w58XJ0gbkIdKz7EMwqkTQDBYgadFnI764Q J9CQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248781; x=1685840781; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xZGjFNLoqqGuNOvjc//J6vmOrtdne6dPztqTW31lhQM=; b=KuHRMJKdGTK59TGtVS2FYjE5ddh/W+Iq/QKQjy+whjgdK9bEbp1OxrjHnvej5T2Zom x+qghnU+v91m6KzRUrUVzR2C6tk/Vk4YzBR0/VQW42bTPqqzy6Rn6VgLCHAg5yZkTewT rwDq89itQUUKcrrvTX38l8Gisr68tXA+vfE9RHO6gUSkyNKBqdzIrw69OyyGwPuOvCVZ vOktxhCW8fQB6kBPsQMp35xLg/JXFUe9HCja4UIzmQKvXHg/VUQprLn9/Vfh2KzQCxZI L2I9F3Glv3dqw1nQ/evgV94DzhAjkN+dEiOq/Rcvodj6jgIyJw5y5Ihu3zI2aAjFi4Lp myTQ== X-Gm-Message-State: AC+VfDzC4YmuBS0FWXJC8yiB33OrYktpvPD21lHrVPMlS2AwxmFtJh1Y twigJdG2A+PTvppqW9yOEhdcvL0t5Jcbyg== X-Google-Smtp-Source: ACHHUZ7h1lHB73p6NiP01pregwc/pVVlAshbHy7j49dViNhMrLxU3K5MmqEdVdKvpmFP6tuNMczQyQ== X-Received: by 2002:a17:902:db08:b0:1ac:3103:c555 with SMTP id m8-20020a170902db0800b001ac3103c555mr3929044plx.58.1683248781336; Thu, 04 May 2023 18:06:21 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Alistair Francis , Richard Henderson Subject: [PULL 54/89] target/riscv: Use PRV_RESERVED instead of PRV_H Date: Fri, 5 May 2023 11:02:06 +1000 Message-Id: <20230505010241.21812-55-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249562001100005 Content-Type: text/plain; charset="utf-8" From: Weiwei Li PRV_H has no real meaning, but just a reserved privilege mode currently. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-Id: <20230407014743.18779-3-liweiwei@iscas.ac.cn> [ Changes by AF: - Convert one missing use of PRV_H ] Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/cpu_bits.h | 2 +- target/riscv/cpu_helper.c | 2 +- target/riscv/gdbstub.c | 2 +- target/riscv/op_helper.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f47c3fc139..86e08d10da 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -684,7 +684,7 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *= env) case PRV_U: xl =3D get_field(env->mstatus, MSTATUS64_UXL); break; - default: /* PRV_S | PRV_H */ + default: /* PRV_S */ xl =3D get_field(env->mstatus, MSTATUS64_SXL); break; } diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 101702cb4a..a16bfaf43f 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -608,7 +608,7 @@ typedef enum { /* Privilege modes */ #define PRV_U 0 #define PRV_S 1 -#define PRV_H 2 /* Reserved */ +#define PRV_RESERVED 2 #define PRV_M 3 =20 /* RV32 satp CSR field masks */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 2310c7905f..29ac7956f7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -650,7 +650,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulon= g newpriv) if (newpriv > PRV_M) { g_assert_not_reached(); } - if (newpriv =3D=3D PRV_H) { + if (newpriv =3D=3D PRV_RESERVED) { newpriv =3D PRV_U; } if (icount_enabled() && newpriv !=3D env->priv) { diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index fa537aed74..524bede865 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -203,7 +203,7 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uin= t8_t *mem_buf, int n) if (n =3D=3D 0) { #ifndef CONFIG_USER_ONLY cs->priv =3D ldtul_p(mem_buf) & 0x3; - if (cs->priv =3D=3D PRV_H) { + if (cs->priv =3D=3D PRV_RESERVED) { cs->priv =3D PRV_S; } #endif diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index b8a03afebb..bd21c6eeef 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -141,7 +141,7 @@ static void check_zicbo_envcfg(CPURISCVState *env, targ= et_ulong envbits, } =20 if (env->virt_enabled && - (((env->priv < PRV_H) && !get_field(env->henvcfg, envbits)) || + (((env->priv <=3D PRV_S) && !get_field(env->henvcfg, envbits)) || ((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)))) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra); 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:06:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248785; x=1685840785; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cKRtGtYIgef1clEK0i7kNVfzqDvagT7FZvB4yYdMQ/Y=; b=IS81Nq4qotlTFQf1bapWJ72rm4zd9ESpbv/6ZCxZEi3Zl3gsYhXnowAOsZvLWsAZ2/ ACcobbBLuvHSTg6jJcb/lxWhLeVPp8KR1SWvrrW77CQdEUpXu9TQg6opQkMUCFpHQHMe 97jEgW2/PFTUdnQ/iH9xkbMPqyhlFAf26/XtmHAnkQ0NCpRi952W4XG5hJGm4mDla51q FrMkirJC1wa1nEVhVheMUbcAvVXlVhdt8SI3y1OPRwC6vvYwXNK1gwT+k7YeQImeHLM8 oUp7OnMdu0vMYGNKLiLXWyZB29a0wSaAZcigrc3mIc327qbKbCT7Tpo0Q4TqBDqjNZ2O xntA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248785; x=1685840785; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cKRtGtYIgef1clEK0i7kNVfzqDvagT7FZvB4yYdMQ/Y=; b=hhmMOKXCi0Bgr9IP44nOalQd3nXN4A5IIK3VndoDFnHRYKzPSP7WAPxXgExdgnFs9b nKafm7c6mWXq54qxwB99yQsReEcuEW1KGG491A2uuVQrhn0vz2K0Y+8obUvraL+ETnHT 7/d1LsbYvStIqg2F6XJxQ8nd9p63UhOP8WG2RGbUdYHCiNXGGNpSEudvp/tQuO7J33D3 9cdGba/KlwwgY0wUHWnyED2HygixFToUI1EfWNdDQt+ZWf+v1W57Bzq+UiAidKZw9o3E CbIr7hqA973BMzuR20i3VkghK3jP13qRzFioV9Ocp+tiIAUNruTfBsydPEb23Lha6U+D g9DQ== X-Gm-Message-State: AC+VfDylKQHmUbM4lC3HkEQ1uXZpzO6eizdYPJhptQVX5eAdEHWyWKaN QtoG/kvKtDHI72XGsCk0bk8mvuSTveYhVA== X-Google-Smtp-Source: ACHHUZ6xfXNn9XJ+7Ou6tuJ1Hdu506psOmeTzmHcsP0H0VcxoZLLlJJanmYaJpCAskjOrSCw7MClFg== X-Received: by 2002:a17:90b:3696:b0:250:5f4:5652 with SMTP id mj22-20020a17090b369600b0025005f45652mr3536721pjb.39.1683248784729; Thu, 04 May 2023 18:06:24 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Alistair Francis , Richard Henderson Subject: [PULL 55/89] target/riscv: Legalize MPP value in write_mstatus Date: Fri, 5 May 2023 11:02:07 +1000 Message-Id: <20230505010241.21812-56-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249586750100003 Content-Type: text/plain; charset="utf-8" From: Weiwei Li mstatus.MPP field is a WARL field since priv version 1.11, so we remain it unchanged if an invalid value is written into it. And after this, RVH shouldn't be passed to riscv_cpu_set_mode(). Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-Id: <20230407014743.18779-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 8 ++------ target/riscv/csr.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 29ac7956f7..433ea529b0 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -647,12 +647,8 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env,= uint32_t priv, =20 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) { - if (newpriv > PRV_M) { - g_assert_not_reached(); - } - if (newpriv =3D=3D PRV_RESERVED) { - newpriv =3D PRV_U; - } + g_assert(newpriv <=3D PRV_M && newpriv !=3D PRV_RESERVED); + if (icount_enabled() && newpriv !=3D env->priv) { riscv_itrigger_update_priv(env); } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e0b871f6dc..f4d2dcfdc8 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1230,6 +1230,32 @@ static bool validate_vm(CPURISCVState *env, target_u= long vm) satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map); } =20 +static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp, + target_ulong val) +{ + bool valid =3D false; + target_ulong new_mpp =3D get_field(val, MSTATUS_MPP); + + switch (new_mpp) { + case PRV_M: + valid =3D true; + break; + case PRV_S: + valid =3D riscv_has_ext(env, RVS); + break; + case PRV_U: + valid =3D riscv_has_ext(env, RVU); + break; + } + + /* Remain field unchanged if new_mpp value is invalid */ + if (!valid) { + val =3D set_field(val, MSTATUS_MPP, old_mpp); + } + + return val; +} + static RISCVException write_mstatus(CPURISCVState *env, int csrno, target_ulong val) { @@ -1237,6 +1263,12 @@ static RISCVException write_mstatus(CPURISCVState *e= nv, int csrno, uint64_t mask =3D 0; RISCVMXL xl =3D riscv_cpu_mxl(env); =20 + /* + * MPP field have been made WARL since priv version 1.11. However, + * legalization for it will not break any software running on 1.10. + */ + val =3D legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val); + /* flush tlb on mstatus fields that affect VM */ if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | MSTATUS_MPRV | MSTATUS_SUM)) { --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249043; cv=none; d=zohomail.com; s=zohoarc; b=OGgJ21LtqNZb4t38XHZ4HiasumvGWh1E0gPyD/rRGmMD6nzFcM8qMo8DSZUJ1LjbjiY/ZyUya/ofz+JSk9+Bow10zYD3KVYJbtJPpcCLBL5v5HPbwgKBdK9qCF/lLqcspewzP3cfT92ywmqqN4qU75a6kzfYaSCuqcZ7407aJN0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249043; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kfBR1l/PXU4/Q6yJtXXce9Y0KTY53G4yiiDVUTCQE3g=; b=EUkLTfBr5joSDzv4hSkj19RTRDSvNaNgtxQ9SAcd/3hlq4BDeOQTugRi64j/N4fsUkftE83N20P8U4BizVNifVxF8PrJF/emoUH1/qnp+Hvmr2kAFyyyNEwSBgll7M3VvcF45DUEASwdNddkIUX4R/2qTWyM4KFXKC0SqTnAIZM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249043545899.1980263308291; Thu, 4 May 2023 18:10:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujuO-0006vi-Ak; Thu, 04 May 2023 21:06:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1puju6-0006ne-8X for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:36 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1puju2-0007lG-TF for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:33 -0400 Received: by mail-pj1-x1031.google.com with SMTP id 98e67ed59e1d1-24e01ba9e03so867972a91.1 for ; Thu, 04 May 2023 18:06:28 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:06:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248788; x=1685840788; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kfBR1l/PXU4/Q6yJtXXce9Y0KTY53G4yiiDVUTCQE3g=; b=jfZZ7xnBfzijqPsuj3Fj02RyZ3+0ow59iT2Je1Qg+bF4AYeTNk3ZUSG+g4H9OIAyzT suMM4Wa+wee3RBONfnUG/Q1Yt39ed+55tHB/dNGbzoEzQX//89BPPOB7ZGvd2+BKPfPk DTVthYLOOSnSj6cUCsvloqFeBxRHk48Uu9+95ITdhBMqO1Kuc/q98MzndmsaBs9HZVuT NWpN0KfI6LoQ6xyATaSWAbanIQDyH91OwcUPBFG+ynQyUSLfmS7nc6kbOpVZPfhbo414 BvlMONBkgOXpXjburLX/eqGRD06ix2jl58chG+tZWLJnlo0llsPynpmrcaUxv3SAOoj9 cEiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248788; x=1685840788; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kfBR1l/PXU4/Q6yJtXXce9Y0KTY53G4yiiDVUTCQE3g=; b=L+LEDVzZ1W97tsHN7XuKm6rOxC87budbb8MfStUEIxf6J8h/2k3TzhrM3Ta1S8p17+ Qsqy/ex1LzU3c1VOImQ2iqm+hR9beptTL2oGQKGnGT9OzNxRkfTym5YFlBVgNI/QM/F1 p+SFmCO2wrPGPw6lBqfmqsSbYOXvG6wQPaTKoC1xAc4BCE5fa9JZeAqlYITqaYKSRga+ FozRQ6qwpCwlVEaVAmnVKatsnGOUREw7CIV2eC/0m/Ef5b4Zra7mcgdbgMaAAY6ZHbnM lLQaHjF/t9qbqDgcZe7ltpt1ZPPSVYRa7PiNP/DSstocbJ/8+T6/554pijvowsa3rYvK cAeA== X-Gm-Message-State: AC+VfDxW3mInEPOUS/gn0psEG6lJuJfwDz5VFb6mnVDmraD1N5LbQtOs EejGo7U3oeobbx3TYtWCeX98alCZjygXsA== X-Google-Smtp-Source: ACHHUZ7Q+m8je07754uF9vYVXmDo+DwaG7znWw2qz4gxCrXS7O96+OjB54Oc1Gf3ChQJuDMf/Pua3Q== X-Received: by 2002:a17:90b:2290:b0:24e:f37:a6a2 with SMTP id kx16-20020a17090b229000b0024e0f37a6a2mr3916614pjb.21.1683248787762; Thu, 04 May 2023 18:06:27 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Alistair Francis Subject: [PULL 56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx Date: Fri, 5 May 2023 11:02:08 +1000 Message-Id: <20230505010241.21812-57-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249045408100003 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Zdinx/Zhinx{min} require Zfinx. And require relationship is usually done by check currently. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis Message-Id: <20230408135908.25269-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d1769fd218..fab38859ec 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -916,8 +916,9 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) cpu->cfg.ext_zhinxmin =3D true; } =20 - if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) { - cpu->cfg.ext_zfinx =3D true; + if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfi= nx) { + error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); + return; } =20 if (cpu->cfg.ext_zfinx) { --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249382; cv=none; d=zohomail.com; s=zohoarc; b=jOCXb67XgCmnEuLZe599X348Qd8BO61L21Q375kVQpneTRZz9eUA46Ef4Mf3J5/sxIwlO9UGSH7mblLhS82/IrzjyoKkjQKZ5+Ty/mfwVA5mER0ZVDg8Oo3gC93wdcmDGsvCRUrJV+Tr7a/jVyVbz3GxbZtKKCiPMbB6qkRMHbI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249382; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QXiRfA1lCxh93roVIvQPkq79XyZvB0MaIu5Q6xvGzsE=; b=BCN4CyfrWpGbkHDd0fwazm+uWzv/qT+G9R+4yM9vBVdWwqiNsEqsmsqQKy7Cibahqi+qSBKub60lo84HSgfRpJlVMEb7O52WD5sJ6xj5jD5lvYKWwQ4MwWNX0A9n3AMrFzKawFn0RXuHHT/DbdNIcgWkjPs+ELbCfJSqsGkIq+k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249382605355.53233679687264; Thu, 4 May 2023 18:16:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujuQ-00074q-Q5; Thu, 04 May 2023 21:06:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujuA-0006r1-33 for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:47 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1puju6-0007lb-0m for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:36 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-64115eef620so16304697b3a.1 for ; Thu, 04 May 2023 18:06:33 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:06:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248791; x=1685840791; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QXiRfA1lCxh93roVIvQPkq79XyZvB0MaIu5Q6xvGzsE=; b=ppZW1pOixIx29J7mn7yjJybyaYczUrmMHc1zI7WTMzabGCIWGU183yV4VzEnKYLPMY NULd87NFI7jNHFwI+S5snpGJbswae9Sq20tXX6LywQgIli+lZgDtB32JATU4XkJ5u2JT eCL4MpTcg851TYxmSEwxAnkdhAngBygZ5xFDQpYsZEp03lheU2MmWyaP6z1KsMlCogFs 6KDihBLP5lJ6KYuHVMk11/l87rsNk3+r7j2sszstANnuiV+zXakio95FMyHQmkxw0BRv cC9xylNFJY0+PirZKhycm9eqpuH7VG4BLOkENKTer7ETCgWqvX/IbjtssS4fu+a8hZjV VG2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248791; x=1685840791; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QXiRfA1lCxh93roVIvQPkq79XyZvB0MaIu5Q6xvGzsE=; b=j0/Tdy8OfPPTAIeNZXqu965StazeeMIE7S1EC5e9loqnpjckewCodaBEQrGNoDowjM HDRMsoCVLgmwVUael2abJGjRWPm9u/UJTpd/97yJA8xHsmkujvZgoha5sgHr376+q1TS +Vjxp8Ox1rQ3dmn0r3CW7ZekRusU3ddIOEEIEHBSeR4Z+P4P6h+jEKYofvFW4sqjtLWJ f42t+0hmq6FayUh6Be7lRR52NRu9hTFcxixjD7Fk/JRoizBmu671u+06O0cWMl34PQG5 Etiv+Q19AKEKcJDHqpW5AzU1wjhOXIdhb/eE+A2EW5SH6FCyL4xDNGNwptXP2idQgyBF 2Dnw== X-Gm-Message-State: AC+VfDxJAHYDjarXmL4JHLqJMgG46pjczfDFGouCz+Rsqg+YoJivAeph PQJF3TLDqAyGWswh5EPnYrN7lEwsjTIznA== X-Google-Smtp-Source: ACHHUZ40lrafRaG4jlQiCPvkBd+7wk6+NB7tzU87UQM4zFyCEY9aIv4u+V9+qvggurXLobe0ANCPJw== X-Received: by 2002:a17:902:e5c5:b0:1aa:f818:7a24 with SMTP id u5-20020a170902e5c500b001aaf8187a24mr6499844plf.1.1683248791167; Thu, 04 May 2023 18:06:31 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Yi Chen , Weiwei Li , LIU Zhiwei , Alistair Francis Subject: [PULL 57/89] target/riscv: fix H extension TVM trap Date: Fri, 5 May 2023 11:02:09 +1000 Message-Id: <20230505010241.21812-58-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=alistair23@gmail.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249383920100009 Content-Type: text/plain; charset="utf-8" From: Yi Chen - Trap satp/hgatp accesses from HS-mode when MSTATUS.TVM is enabled. - Trap satp accesses from VS-mode when HSTATUS.VTVM is enabled. - Raise RISCV_EXCP_ILLEGAL_INST when U-mode executes SFENCE.VMA/SINVAL.VMA. - Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-mode executes SFENCE.VMA/SINVAL.VMA or VS-mode executes SFENCE.VMA/SINVAL.VMA with HSTATUS.VTVM enabled. - Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-mode executes HFENCE.GVMA/HFENCE.VVMA/HINVAL.GVMA/HINVAL.VVMA. Signed-off-by: Yi Chen Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-Id: <20230406101559.39632-1-chenyi2000@zju.edu.cn> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 56 +++++++++++++++++++++++++--------------- target/riscv/op_helper.c | 12 ++++----- 2 files changed, 41 insertions(+), 27 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f4d2dcfdc8..d2271da137 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -449,6 +449,30 @@ static RISCVException sstc_32(CPURISCVState *env, int = csrno) return sstc(env, csrno); } =20 +static RISCVException satp(CPURISCVState *env, int csrno) +{ + if (env->priv =3D=3D PRV_S && !env->virt_enabled && + get_field(env->mstatus, MSTATUS_TVM)) { + return RISCV_EXCP_ILLEGAL_INST; + } + if (env->priv =3D=3D PRV_S && env->virt_enabled && + get_field(env->hstatus, HSTATUS_VTVM)) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + + return smode(env, csrno); +} + +static RISCVException hgatp(CPURISCVState *env, int csrno) +{ + if (env->priv =3D=3D PRV_S && !env->virt_enabled && + get_field(env->mstatus, MSTATUS_TVM)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return hmode(env, csrno); +} + /* Checks if PointerMasking registers could be accessed */ static RISCVException pointer_masking(CPURISCVState *env, int csrno) { @@ -2679,13 +2703,7 @@ static RISCVException read_satp(CPURISCVState *env, = int csrno, *val =3D 0; return RISCV_EXCP_NONE; } - - if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { - return RISCV_EXCP_ILLEGAL_INST; - } else { - *val =3D env->satp; - } - + *val =3D env->satp; return RISCV_EXCP_NONE; } =20 @@ -2708,18 +2726,14 @@ static RISCVException write_satp(CPURISCVState *env= , int csrno, } =20 if (vm && mask) { - if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { - return RISCV_EXCP_ILLEGAL_INST; - } else { - /* - * The ISA defines SATP.MODE=3DBare as "no translation", but w= e still - * pass these through QEMU's TLB emulation as it improves - * performance. Flushing the TLB on SATP writes with paging - * enabled avoids leaking those invalid cached mappings. - */ - tlb_flush(env_cpu(env)); - env->satp =3D val; - } + /* + * The ISA defines SATP.MODE=3DBare as "no translation", but we st= ill + * pass these through QEMU's TLB emulation as it improves + * performance. Flushing the TLB on SATP writes with paging + * enabled avoids leaking those invalid cached mappings. + */ + tlb_flush(env_cpu(env)); + env->satp =3D val; } return RISCV_EXCP_NONE; } @@ -4215,7 +4229,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { .min_priv_ver =3D PRIV_VERSION_1_12_0 }, =20 /* Supervisor Protection and Translation */ - [CSR_SATP] =3D { "satp", smode, read_satp, write_satp = }, + [CSR_SATP] =3D { "satp", satp, read_satp, write_satp }, =20 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ [CSR_SISELECT] =3D { "siselect", aia_smode, NULL, NULL, rmw_xisele= ct }, @@ -4252,7 +4266,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_HGEIP] =3D { "hgeip", hmode, read_hgeip, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, - [CSR_HGATP] =3D { "hgatp", hmode, read_hgatp, write_hg= atp, + [CSR_HGATP] =3D { "hgatp", hgatp, read_hgatp, write_hg= atp, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_HTIMEDELTA] =3D { "htimedelta", hmode, read_htimedelta, write_htimedelta, diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index bd21c6eeef..0c10dd7a78 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -381,12 +381,12 @@ void helper_wfi(CPURISCVState *env) void helper_tlb_flush(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); - if (!(env->priv >=3D PRV_S) || - (env->priv =3D=3D PRV_S && - get_field(env->mstatus, MSTATUS_TVM))) { + if (!env->virt_enabled && + (env->priv =3D=3D PRV_U || + (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)))= ) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } else if (riscv_has_ext(env, RVH) && env->virt_enabled && - get_field(env->hstatus, HSTATUS_VTVM)) { + } else if (env->virt_enabled && + (env->priv =3D=3D PRV_U || get_field(env->hstatus, HSTATUS_= VTVM))) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } else { tlb_flush(cs); @@ -403,7 +403,7 @@ void helper_hyp_tlb_flush(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); =20 - if (env->priv =3D=3D PRV_S && env->virt_enabled) { + if (env->virt_enabled) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } =20 --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249563; cv=none; d=zohomail.com; s=zohoarc; b=MAGEhk62CVj+ig2+jf/TCClcC024Xg09lZO21PD0bfFjQcmrWm/Mis+wE1QXIcnutsroW19Ac0KlpG3Fu5qAl7ptXT01HL+2lnJ0sAFCX+6ye6DS2498kXLSE2spLyPXuZOSz/kd9GaYnCSKCyoe2LgfSa9DxCjbQG2asKV1klI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249563; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=43SGISdmrbl+ksWlytg3Bw5IaTqyK3kj2xiFSyap57I=; b=OrpogHsiy6CBYpf0N6d9zkuXxoiGjH6OsQTAuO77ytxWAIxN/OitvhfyRGLHU3UQqS21+PKh3aPjqwNgrLfICAbDdgddA3l/xv/3EWw6D8rCaWwWwhKWZDOXy5O3CPsrRYoTV6uROqR4nszLs4Y9ffIZWkOA5AWqJm5hqjRQ6yE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249563677198.69910785687125; Thu, 4 May 2023 18:19:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujuR-0007AL-5k; Thu, 04 May 2023 21:06:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujuB-0006rn-Nx for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:48 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1puju9-0007ph-Rw for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:39 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-64115e652eeso16420775b3a.0 for ; Thu, 04 May 2023 18:06:36 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:06:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248795; x=1685840795; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=43SGISdmrbl+ksWlytg3Bw5IaTqyK3kj2xiFSyap57I=; b=J4ydM6RZvX3i4ddaJy3egeCGy7Yfqa6eU/vZ8KR0s50dh+Z+B/wZyJtaD0RLL4P7Cp YsynbBCrJpQNyGlmaY4c+HQzQCr88q3E/CMLxC4mqolY67tN3EWix/agOK0RkoV/nG00 CRhkPKK7iZOMVloShkWn3b1ElxmT0Wz/PCpa2EnsBz6Ycn0JOnvKuI4i4V56qYfLxwhO sNzfT7Xq29dX0oEx44YSVsOcIhJshmQZkp7CviPfEK/4hNMz/8ph22kIeGi0U7MoHzcs U3DQDBWBKBMNItPCifDBN7rE078UHKMEZvh+LnU6m3utY5tKdOC/wZ1MQInebWz8qXgG fGOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248795; x=1685840795; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=43SGISdmrbl+ksWlytg3Bw5IaTqyK3kj2xiFSyap57I=; b=EJmqb0ZkVPcDhCkFgFrxrGkut26H2c2ub8uAxJgHVIIeQYZiCrrDMYLZc01EZEfAgw AZiQbWw2AJiRVkC8RchWzy2eaKcX1AEnuv0RlffYScFJEIFo405+sgJuQotrR2U6zH28 yp0PKvOdB/cyGMgk9LC1xEdJO5U6EOWjulW/lg43hP0/fGfWo03FcZVFibF4ab/8ARKp POqaJODQkp1aJc16qla9UXHtThc2/QdOZJGmgr6zs2XYQDb5O+TqvAbTsup14F12wEyk jS/YkpOjZzTrQ2SeBOap81fOUAQQ255p5MUX6QW039pdsGXopILvgc6hzGII/rY9Nq+M lV/g== X-Gm-Message-State: AC+VfDxffL1dtidxAPUO2aRPooDv6pNJl+Mp3QX/Sd3An67iPHKokXr3 MQ3vLcu/ArRubprFFt3PoR0MdFhxagCk/w== X-Google-Smtp-Source: ACHHUZ5wgGuQoqe8pz7qR4Tb000uxi0tsUYReCZMRCwXjBx+aTs5Y+BvOpCxsJ3BHlk//t0Qxp4RKQ== X-Received: by 2002:a17:902:9044:b0:1a6:7ea8:9f4f with SMTP id w4-20020a170902904400b001a67ea89f4fmr4777832plz.26.1683248794910; Thu, 04 May 2023 18:06:34 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, LIU Zhiwei , Richard Henderson , Weiwei Li , Alistair Francis , Daniel Henrique Barboza Subject: [PULL 58/89] target/riscv: Extract virt enabled state from tb flags Date: Fri, 5 May 2023 11:02:10 +1000 Message-Id: <20230505010241.21812-59-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249564434100013 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei Virt enabled state is not a constant, so we should put it into tb flags. Thus we can use it like a constant condition at translation phase. Reported-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: LIU Zhiwei Reviewed-by: Weiwei Li Message-Id: <20230324143031.1093-2-zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-2-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-2-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 1 + target/riscv/translate.c | 10 +--------- 3 files changed, 4 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 86e08d10da..aa53d0e256 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -648,6 +648,8 @@ FIELD(TB_FLAGS, VTA, 24, 1) FIELD(TB_FLAGS, VMA, 25, 1) /* Native debug itrigger */ FIELD(TB_FLAGS, ITRIGGER, 26, 1) +/* Virtual mode enabled */ +FIELD(TB_FLAGS, VIRT_ENABLED, 27, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 433ea529b0..1d90977d46 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -104,6 +104,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ul= ong *pc, =20 flags =3D FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, get_field(env->mstatus_hs, MSTATUS_VS)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, env->virt_enab= led); } if (cpu->cfg.debug && !icount_enabled()) { flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d0094922b6..ebd00529ff 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1171,15 +1171,7 @@ static void riscv_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) ctx->mstatus_fs =3D tb_flags & TB_FLAGS_MSTATUS_FS; ctx->mstatus_vs =3D tb_flags & TB_FLAGS_MSTATUS_VS; ctx->priv_ver =3D env->priv_ver; -#if !defined(CONFIG_USER_ONLY) - if (riscv_has_ext(env, RVH)) { - ctx->virt_enabled =3D env->virt_enabled; - } else { - ctx->virt_enabled =3D false; - } -#else - ctx->virt_enabled =3D false; -#endif + ctx->virt_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); ctx->misa_ext =3D env->misa_ext; ctx->frm =3D -1; /* unknown rounding mode */ ctx->cfg_ptr =3D &(cpu->cfg); --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249261; cv=none; d=zohomail.com; s=zohoarc; b=CxkGKsbkdCYnHsJvy8fSRfs4Ec6jvZFoNtgAYVX+TC0+PpUWiD6IjNNwx6NkR5VLCQIc4Ijtcv8WoqXBhGXOgraIx57BfqXCXpcVLYR7mmhFJcEJvuRacU/gewt7Rn+UTMqMNmfJbQ5gwqhBI9UJJkBoqTmvfzq0NRlbHLw6ylk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249261; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8+fk9boX5qCCAYEaNmLumPg5ElbWwbOh4WqzIoOmRZQ=; b=fDhfzD/GFyALmE2jfZOUmJarA8e9PQl8CSGY7PADscjXdYdHU9Xk9cgYt2MixN+0IQbKdAr3L8TykQFp7UoKM7pvwlehn9wDEF2cZ7Tk7S1P4E0VCm6bLf/APbVAbldNt0IaghnRTXLQVwUd1naV/EHO6dkYyiaHstWAYuHEPrk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249261702659.2995318065576; Thu, 4 May 2023 18:14:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujuY-0007PI-Rv; Thu, 04 May 2023 21:07:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujuJ-0006rw-DT for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:49 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujuD-0007rG-LR for qemu-devel@nongnu.org; Thu, 04 May 2023 21:06:45 -0400 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-24df161f84bso867584a91.3 for ; Thu, 04 May 2023 18:06:39 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. 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The vector or float extension uses the status in an indirect way. Replace the pointer masking extension special status fields with the general status. Reviewed-by: Richard Henderson Signed-off-by: LIU Zhiwei Message-Id: <20230324143031.1093-3-zhiwei_liu@linux.alibaba.com> [rth: Add a typedef for the enum] Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-3-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-3-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 8 ++++++++ target/riscv/cpu_bits.h | 12 ++++-------- target/riscv/cpu.c | 2 +- target/riscv/csr.c | 14 +++++++------- 4 files changed, 20 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index aa53d0e256..ba11279716 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -97,6 +97,14 @@ enum { TRANSLATE_G_STAGE_FAIL }; =20 +/* Extension context status */ +typedef enum { + EXT_STATUS_DISABLED =3D 0, + EXT_STATUS_INITIAL, + EXT_STATUS_CLEAN, + EXT_STATUS_DIRTY, +} RISCVExtStatus; + #define MMU_USER_IDX 3 =20 #define MAX_RISCV_PMPS (16) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index a16bfaf43f..fb63b8e125 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -9,6 +9,9 @@ (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \ (uint64_t)(mask))) =20 +/* Extension context status mask */ +#define EXT_STATUS_MASK 0x3ULL + /* Floating point round mode */ #define FSR_RD_SHIFT 5 #define FSR_RD (0x7 << FSR_RD_SHIFT) @@ -735,13 +738,6 @@ typedef enum RISCVException { #define PM_ENABLE 0x00000001ULL #define PM_CURRENT 0x00000002ULL #define PM_INSN 0x00000004ULL -#define PM_XS_MASK 0x00000003ULL - -/* PointerMasking XS bits values */ -#define PM_EXT_DISABLE 0x00000000ULL -#define PM_EXT_INITIAL 0x00000001ULL -#define PM_EXT_CLEAN 0x00000002ULL -#define PM_EXT_DIRTY 0x00000003ULL =20 /* Execution enviornment configuration bits */ #define MENVCFG_FIOM BIT(0) @@ -781,7 +777,7 @@ typedef enum RISCVException { #define S_OFFSET 5ULL #define M_OFFSET 8ULL =20 -#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET) +#define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET) #define U_PM_ENABLE (PM_ENABLE << U_OFFSET) #define U_PM_CURRENT (PM_CURRENT << U_OFFSET) #define U_PM_INSN (PM_INSN << U_OFFSET) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fab38859ec..32c04214a1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -759,7 +759,7 @@ static void riscv_cpu_reset_hold(Object *obj) i++; } /* mmte is supposed to have pm.current hardwired to 1 */ - env->mmte |=3D (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); + env->mmte |=3D (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT); #endif env->xl =3D riscv_cpu_mxl(env); riscv_cpu_update_mask(env); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d2271da137..92ad54411b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3548,7 +3548,7 @@ static RISCVException write_mmte(CPURISCVState *env, = int csrno, =20 /* hardwiring pm.instruction bit to 0, since it's not supported yet */ wpri_val &=3D ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); - env->mmte =3D wpri_val | PM_EXT_DIRTY; + env->mmte =3D wpri_val | EXT_STATUS_DIRTY; riscv_cpu_update_mask(env); =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -3628,7 +3628,7 @@ static RISCVException write_mpmmask(CPURISCVState *en= v, int csrno, if ((env->priv =3D=3D PRV_M) && (env->mmte & M_PM_ENABLE)) { env->cur_pmmask =3D val; } - env->mmte |=3D PM_EXT_DIRTY; + env->mmte |=3D EXT_STATUS_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ mstatus =3D env->mstatus | MSTATUS_XS; @@ -3656,7 +3656,7 @@ static RISCVException write_spmmask(CPURISCVState *en= v, int csrno, if ((env->priv =3D=3D PRV_S) && (env->mmte & S_PM_ENABLE)) { env->cur_pmmask =3D val; } - env->mmte |=3D PM_EXT_DIRTY; + env->mmte |=3D EXT_STATUS_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ mstatus =3D env->mstatus | MSTATUS_XS; @@ -3684,7 +3684,7 @@ static RISCVException write_upmmask(CPURISCVState *en= v, int csrno, if ((env->priv =3D=3D PRV_U) && (env->mmte & U_PM_ENABLE)) { env->cur_pmmask =3D val; } - env->mmte |=3D PM_EXT_DIRTY; + env->mmte |=3D EXT_STATUS_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ mstatus =3D env->mstatus | MSTATUS_XS; @@ -3708,7 +3708,7 @@ static RISCVException write_mpmbase(CPURISCVState *en= v, int csrno, if ((env->priv =3D=3D PRV_M) && (env->mmte & M_PM_ENABLE)) { env->cur_pmbase =3D val; } - env->mmte |=3D PM_EXT_DIRTY; + env->mmte |=3D EXT_STATUS_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ mstatus =3D env->mstatus | MSTATUS_XS; @@ -3736,7 +3736,7 @@ static RISCVException write_spmbase(CPURISCVState *en= v, int csrno, if ((env->priv =3D=3D PRV_S) && (env->mmte & S_PM_ENABLE)) { env->cur_pmbase =3D val; } - env->mmte |=3D PM_EXT_DIRTY; + env->mmte |=3D EXT_STATUS_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ mstatus =3D env->mstatus | MSTATUS_XS; @@ -3764,7 +3764,7 @@ static RISCVException write_upmbase(CPURISCVState *en= v, int csrno, if ((env->priv =3D=3D PRV_U) && (env->mmte & U_PM_ENABLE)) { env->cur_pmbase =3D val; } - env->mmte |=3D PM_EXT_DIRTY; + env->mmte |=3D EXT_STATUS_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ mstatus =3D env->mstatus | MSTATUS_XS; --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:06:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248802; x=1685840802; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aFpeSydLToeDkFGGhok1argALURBxwBUe50hDHY5hQY=; b=ZfhlxbRSukWRjjhDU0n+Y1CUiASy1rIfoMW/W6zcz5eBjPgDtB5sGulPx5X8b58cK0 TVgo9JLHHk1aq+M0n3XfXingM43RmpbJNtajLNSTbePrQGZJuOZD+xLvJJ54i9ZlXtkL tb7RUZZJY6PoOXQP3ZxK4XM59vyNE9QT0uHVSxC7AR/t0nxkC5UBPyDrP5IESe6yov3Z QZXQm15vWE/bOCCEnx41E9OYZ9xWkBUUIIVUvtaYzpwHWd6IgjhkSpdQTVipezf/hEyg SGgrVt7ywaGxiC1cwB+w8sywL2t1qbLMBE92S+mouAHF2h/SqCS3RalaYBdUiyzzcK2b +PuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248802; x=1685840802; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aFpeSydLToeDkFGGhok1argALURBxwBUe50hDHY5hQY=; b=XOfLm24cvJcBfn1GMsstWok1GUzws29gBKTC/Op7TWVMWy0mcoX5r7SfRyHeLadE6E Ae9wVL9uTic86ICOnNvij4GIeAOY806S3LL4NioTSsLIfz8pPUz0uyJOElsSqW6kfHCb emcsLnHFTMWzZYgtHLJzZVl1Br5pL0huTOG4qnXJprjYhIja4OyUmQq2lI+SOG1Dp5jT /hvkmUjxnDUwdKlVIgb9R3s5fvv00jVfnWcu8AVs0YKr9kfV8LI+h+5m/ixOM2v2R8wG sbJYCBO55cH3St1/rZ64k4aAi1c8gITrfoO7DRZCFJ3aWEkKKj0xvP6F0K2R9S06AX4u XFWQ== X-Gm-Message-State: AC+VfDyV2fW1g/6fO2qYScNgsxpkW3MPvPmM5JxqmU/8vXjBZhKjQ5ob dSLPaoIb8ecIVwwIRh4br2dgQkD0phf7pw== X-Google-Smtp-Source: ACHHUZ467P5cRxilfPTmVDzaSweCng+v3hYPAJQ+78ogkquIhDdht5+BnB33CK88PLRsfYlnRqr10A== X-Received: by 2002:a17:902:ec8c:b0:1aa:f3c4:7582 with SMTP id x12-20020a170902ec8c00b001aaf3c47582mr7720516plg.31.1683248802624; Thu, 04 May 2023 18:06:42 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, LIU Zhiwei , Richard Henderson , Weiwei Li , Alistair Francis , Daniel Henrique Barboza Subject: [PULL 60/89] target/riscv: Encode the FS and VS on a normal way for tb flags Date: Fri, 5 May 2023 11:02:12 +1000 Message-Id: <20230505010241.21812-61-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=alistair23@gmail.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249574907100003 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei Reuse the MSTATUS_FS and MSTATUS_VS for the tb flags positions is not a normal way. It will make it hard to change the tb flags layout. And even worse, if we want to keep tb flags for a same extension togather without a hole. Reviewed-by: Richard Henderson Signed-off-by: LIU Zhiwei Reviewed-by: Weiwei Li Message-Id: <20230324143031.1093-4-zhiwei_liu@linux.alibaba.com> [rth: Adjust trans_rvf.c.inc as well; use the typedef] Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-4-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-4-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 15 ++++++------ target/riscv/cpu_helper.c | 11 +++++---- target/riscv/translate.c | 32 +++++++++++-------------- target/riscv/insn_trans/trans_rvf.c.inc | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 8 +++---- 5 files changed, 32 insertions(+), 36 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ba11279716..51d39687fe 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -631,18 +631,17 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_= ulong); =20 #define TB_FLAGS_PRIV_MMU_MASK 3 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) -#define TB_FLAGS_MSTATUS_FS MSTATUS_FS -#define TB_FLAGS_MSTATUS_VS MSTATUS_VS =20 #include "exec/cpu-all.h" =20 FIELD(TB_FLAGS, MEM_IDX, 0, 3) -FIELD(TB_FLAGS, LMUL, 3, 3) -FIELD(TB_FLAGS, SEW, 6, 3) -/* Skip MSTATUS_VS (0x600) bits */ -FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) -FIELD(TB_FLAGS, VILL, 12, 1) -/* Skip MSTATUS_FS (0x6000) bits */ +FIELD(TB_FLAGS, FS, 3, 2) +/* Vector flags */ +FIELD(TB_FLAGS, VS, 5, 2) +FIELD(TB_FLAGS, LMUL, 7, 3) +FIELD(TB_FLAGS, SEW, 10, 3) +FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) +FIELD(TB_FLAGS, VILL, 14, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 15, 1) FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1d90977d46..8412ef26ee 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -79,16 +79,17 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ul= ong *pc, } =20 #ifdef CONFIG_USER_ONLY - flags |=3D TB_FLAGS_MSTATUS_FS; - flags |=3D TB_FLAGS_MSTATUS_VS; + flags =3D FIELD_DP32(flags, TB_FLAGS, FS, EXT_STATUS_DIRTY); + flags =3D FIELD_DP32(flags, TB_FLAGS, VS, EXT_STATUS_DIRTY); #else flags |=3D cpu_mmu_index(env, 0); if (riscv_cpu_fp_enabled(env)) { - flags |=3D env->mstatus & MSTATUS_FS; + flags =3D FIELD_DP32(flags, TB_FLAGS, FS, + get_field(env->mstatus, MSTATUS_FS)); } - if (riscv_cpu_vector_enabled(env)) { - flags |=3D env->mstatus & MSTATUS_VS; + flags =3D FIELD_DP32(flags, TB_FLAGS, VS, + get_field(env->mstatus, MSTATUS_VS)); } =20 if (riscv_has_ext(env, RVH)) { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ebd00529ff..411e771e6f 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -64,10 +64,10 @@ typedef struct DisasContext { RISCVMXL xl; uint32_t misa_ext; uint32_t opcode; - uint32_t mstatus_fs; - uint32_t mstatus_vs; - uint32_t mstatus_hs_fs; - uint32_t mstatus_hs_vs; + RISCVExtStatus mstatus_fs; + RISCVExtStatus mstatus_vs; + RISCVExtStatus mstatus_hs_fs; + RISCVExtStatus mstatus_hs_vs; uint32_t mem_idx; /* * Remember the rounding mode encoded in the previous fp instruction, @@ -601,8 +601,6 @@ static TCGv get_address_indexed(DisasContext *ctx, int = rs1, TCGv offs) =20 #ifndef CONFIG_USER_ONLY /* - * The states of mstatus_fs are: - * 0 =3D disabled, 1 =3D initial, 2 =3D clean, 3 =3D dirty * We will have already diagnosed disabled state, * and need to turn initial/clean into dirty. */ @@ -614,9 +612,9 @@ static void mark_fs_dirty(DisasContext *ctx) return; } =20 - if (ctx->mstatus_fs !=3D MSTATUS_FS) { + if (ctx->mstatus_fs !=3D EXT_STATUS_DIRTY) { /* Remember the state change for the rest of the TB. */ - ctx->mstatus_fs =3D MSTATUS_FS; + ctx->mstatus_fs =3D EXT_STATUS_DIRTY; =20 tmp =3D tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); @@ -624,9 +622,9 @@ static void mark_fs_dirty(DisasContext *ctx) tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); } =20 - if (ctx->virt_enabled && ctx->mstatus_hs_fs !=3D MSTATUS_FS) { + if (ctx->virt_enabled && ctx->mstatus_hs_fs !=3D EXT_STATUS_DIRTY) { /* Remember the stage change for the rest of the TB. */ - ctx->mstatus_hs_fs =3D MSTATUS_FS; + ctx->mstatus_hs_fs =3D EXT_STATUS_DIRTY; =20 tmp =3D tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); @@ -640,8 +638,6 @@ static inline void mark_fs_dirty(DisasContext *ctx) { } =20 #ifndef CONFIG_USER_ONLY /* - * The states of mstatus_vs are: - * 0 =3D disabled, 1 =3D initial, 2 =3D clean, 3 =3D dirty * We will have already diagnosed disabled state, * and need to turn initial/clean into dirty. */ @@ -649,9 +645,9 @@ static void mark_vs_dirty(DisasContext *ctx) { TCGv tmp; =20 - if (ctx->mstatus_vs !=3D MSTATUS_VS) { + if (ctx->mstatus_vs !=3D EXT_STATUS_DIRTY) { /* Remember the state change for the rest of the TB. */ - ctx->mstatus_vs =3D MSTATUS_VS; + ctx->mstatus_vs =3D EXT_STATUS_DIRTY; =20 tmp =3D tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); @@ -659,9 +655,9 @@ static void mark_vs_dirty(DisasContext *ctx) tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); } =20 - if (ctx->virt_enabled && ctx->mstatus_hs_vs !=3D MSTATUS_VS) { + if (ctx->virt_enabled && ctx->mstatus_hs_vs !=3D EXT_STATUS_DIRTY) { /* Remember the stage change for the rest of the TB. */ - ctx->mstatus_hs_vs =3D MSTATUS_VS; + ctx->mstatus_hs_vs =3D EXT_STATUS_DIRTY; =20 tmp =3D tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); @@ -1168,8 +1164,8 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) =20 ctx->pc_succ_insn =3D ctx->base.pc_first; ctx->mem_idx =3D FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); - ctx->mstatus_fs =3D tb_flags & TB_FLAGS_MSTATUS_FS; - ctx->mstatus_vs =3D tb_flags & TB_FLAGS_MSTATUS_VS; + ctx->mstatus_fs =3D FIELD_EX32(tb_flags, TB_FLAGS, FS); + ctx->mstatus_vs =3D FIELD_EX32(tb_flags, TB_FLAGS, VS); ctx->priv_ver =3D env->priv_ver; ctx->virt_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); ctx->misa_ext =3D env->misa_ext; diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index 9e9fa2087a..b2de4fcf3f 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -19,7 +19,7 @@ */ =20 #define REQUIRE_FPU do {\ - if (ctx->mstatus_fs =3D=3D 0) \ + if (ctx->mstatus_fs =3D=3D EXT_STATUS_DISABLED) \ if (!ctx->cfg_ptr->ext_zfinx) \ return false; \ } while (0) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index ca3c4c1a3d..ecbdf1b3d7 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -29,12 +29,12 @@ static inline bool is_overlapped(const int8_t astart, i= nt8_t asize, =20 static bool require_rvv(DisasContext *s) { - return s->mstatus_vs !=3D 0; + return s->mstatus_vs !=3D EXT_STATUS_DISABLED; } =20 static bool require_rvf(DisasContext *s) { - if (s->mstatus_fs =3D=3D 0) { + if (s->mstatus_fs =3D=3D EXT_STATUS_DISABLED) { return false; } =20 @@ -52,7 +52,7 @@ static bool require_rvf(DisasContext *s) =20 static bool require_scale_rvf(DisasContext *s) { - if (s->mstatus_fs =3D=3D 0) { + if (s->mstatus_fs =3D=3D EXT_STATUS_DISABLED) { return false; } =20 @@ -70,7 +70,7 @@ static bool require_scale_rvf(DisasContext *s) =20 static bool require_scale_rvfmin(DisasContext *s) { - if (s->mstatus_fs =3D=3D 0) { + if (s->mstatus_fs =3D=3D EXT_STATUS_DISABLED) { return false; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:06:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248806; x=1685840806; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uhmk5Jx0OAmTzZeJbqXjEcRvnQOSauhU+b8PthDHgjA=; b=ZZW0S70Wl7rVk7eQH+/HLNWYSfKADjFGIE20xvz/wodgy/suckgNidXrjxRTmG9+07 1qKlRuYIOxPirmFWwHeFmcOSNUZLZKbNR7LXKxIGncgl9MlARw30EOmZGsTfXtPLrQ44 Tfc6fhXuorqBiZEoZME1tbIu2/nu3dLKldCs11ysYjryp9d+C2mGlVW74+P5BS07drEb s/bsLsT/34sJckp3DRrDwU3gZjXbHuK/y7nuEKY5QLaszvcBaZs7AUui7VTFlyJtn7IO dKHimmhBoTUBholpku2Vt49CJ98oVtWcIdWtgECzMkrUuueW6ECpShsbP3WXtjQ5Zdip wghQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248806; x=1685840806; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uhmk5Jx0OAmTzZeJbqXjEcRvnQOSauhU+b8PthDHgjA=; b=J+u+hFwCosHvt8oaWxzaVn6v721hBfRcSE/vMOnYRNrrhgvyoGfDenL5oBohBGhLu+ dPagtzQL+g71XgymA5dti/yNGDtUZlyH5YN9wBkqydtlzWqqeJqciSguSxuBbsR88HCV XzJ4huL5t681sjaqzVMEeFOVSGGzHEbdHvaVms1ptuoJed+9qBhXIDLSp/jtna1yF8kH z+9Xo9QExb64lZrP8D0IQ7X1tPghSaYvam04biXiI6tREZidyGdoQasLFkFTwCVAfBwK 1+qVPiIfp6ahKvRggXBUOGyOK+20TCOMdjR75bIF0CCxwVcnGTTu4AdyUyjMV3//LHTn bopw== X-Gm-Message-State: AC+VfDxx6JVE6UIgNyXXk7nHRLTS0GtQLmJ6oCfu2dhW7YbCwvXsNX8K 4sZ9dqhFIiXgZxR4CEvu1yFDE5PYhkrsuQ== X-Google-Smtp-Source: ACHHUZ6kNyGXBZO88G2XdWuaso+JBcLYP08ZvQ6oSDwAFKMCx5xNvbdyhxspThDS37ek11dBhx+5aQ== X-Received: by 2002:a17:903:120a:b0:1a6:a988:b858 with SMTP id l10-20020a170903120a00b001a6a988b858mr6327474plh.58.1683248806515; Thu, 04 May 2023 18:06:46 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , LIU Zhiwei , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags Date: Fri, 5 May 2023 11:02:13 +1000 Message-Id: <20230505010241.21812-62-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=alistair23@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249582756100002 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Merge with mstatus_{fs,vs}. We might perform a redundant assignment to one or the other field, but it's a trivial and saves 4 bits from TB_FLAGS. Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-5-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-5-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 16 +++++++--------- target/riscv/cpu_helper.c | 33 ++++++++++++++++----------------- target/riscv/translate.c | 32 ++++++++++---------------------- 3 files changed, 33 insertions(+), 48 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 51d39687fe..ab64d5f92d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -644,19 +644,17 @@ FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) FIELD(TB_FLAGS, VILL, 14, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 15, 1) -FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) -FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ -FIELD(TB_FLAGS, XL, 20, 2) +FIELD(TB_FLAGS, XL, 16, 2) /* If PointerMasking should be applied */ -FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) -FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) -FIELD(TB_FLAGS, VTA, 24, 1) -FIELD(TB_FLAGS, VMA, 25, 1) +FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) +FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) +FIELD(TB_FLAGS, VTA, 20, 1) +FIELD(TB_FLAGS, VMA, 21, 1) /* Native debug itrigger */ -FIELD(TB_FLAGS, ITRIGGER, 26, 1) +FIELD(TB_FLAGS, ITRIGGER, 22, 1) /* Virtual mode enabled */ -FIELD(TB_FLAGS, VIRT_ENABLED, 27, 1) +FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8412ef26ee..e3e620137b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -45,7 +45,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulon= g *pc, { CPUState *cs =3D env_cpu(env); RISCVCPU *cpu =3D RISCV_CPU(cs); - + RISCVExtStatus fs, vs; uint32_t flags =3D 0; =20 *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; @@ -79,18 +79,12 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ul= ong *pc, } =20 #ifdef CONFIG_USER_ONLY - flags =3D FIELD_DP32(flags, TB_FLAGS, FS, EXT_STATUS_DIRTY); - flags =3D FIELD_DP32(flags, TB_FLAGS, VS, EXT_STATUS_DIRTY); + fs =3D EXT_STATUS_DIRTY; + vs =3D EXT_STATUS_DIRTY; #else flags |=3D cpu_mmu_index(env, 0); - if (riscv_cpu_fp_enabled(env)) { - flags =3D FIELD_DP32(flags, TB_FLAGS, FS, - get_field(env->mstatus, MSTATUS_FS)); - } - if (riscv_cpu_vector_enabled(env)) { - flags =3D FIELD_DP32(flags, TB_FLAGS, VS, - get_field(env->mstatus, MSTATUS_VS)); - } + fs =3D get_field(env->mstatus, MSTATUS_FS); + vs =3D get_field(env->mstatus, MSTATUS_VS); =20 if (riscv_has_ext(env, RVH)) { if (env->priv =3D=3D PRV_M || @@ -100,18 +94,23 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_u= long *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, HLSX, 1); } =20 - flags =3D FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, - get_field(env->mstatus_hs, MSTATUS_FS)); - - flags =3D FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, - get_field(env->mstatus_hs, MSTATUS_VS)); - flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, env->virt_enab= led); + if (env->virt_enabled) { + flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); + /* + * Merge DISABLED and !DIRTY states using MIN. + * We will set both fields when dirtying. + */ + fs =3D MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); + vs =3D MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); + } } if (cpu->cfg.debug && !icount_enabled()) { flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); } #endif =20 + flags =3D FIELD_DP32(flags, TB_FLAGS, FS, fs); + flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); if (env->cur_pmmask < (env->xl =3D=3D MXL_RV32 ? UINT32_MAX : UINT64_M= AX)) { flags =3D FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 411e771e6f..3092c942ab 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -66,8 +66,6 @@ typedef struct DisasContext { uint32_t opcode; RISCVExtStatus mstatus_fs; RISCVExtStatus mstatus_vs; - RISCVExtStatus mstatus_hs_fs; - RISCVExtStatus mstatus_hs_vs; uint32_t mem_idx; /* * Remember the rounding mode encoded in the previous fp instruction, @@ -620,16 +618,12 @@ static void mark_fs_dirty(DisasContext *ctx) tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); - } - - if (ctx->virt_enabled && ctx->mstatus_hs_fs !=3D EXT_STATUS_DIRTY) { - /* Remember the stage change for the rest of the TB. */ - ctx->mstatus_hs_fs =3D EXT_STATUS_DIRTY; =20 - tmp =3D tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); - tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + if (ctx->virt_enabled) { + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs= )); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs= )); + } } } #else @@ -653,16 +647,12 @@ static void mark_vs_dirty(DisasContext *ctx) tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); - } - - if (ctx->virt_enabled && ctx->mstatus_hs_vs !=3D EXT_STATUS_DIRTY) { - /* Remember the stage change for the rest of the TB. */ - ctx->mstatus_hs_vs =3D EXT_STATUS_DIRTY; =20 - tmp =3D tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); - tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + if (ctx->virt_enabled) { + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs= )); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs= )); + } } } #else @@ -1171,8 +1161,6 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->misa_ext =3D env->misa_ext; ctx->frm =3D -1; /* unknown rounding mode */ ctx->cfg_ptr =3D &(cpu->cfg); - ctx->mstatus_hs_fs =3D FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); - ctx->mstatus_hs_vs =3D FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); ctx->hlsx =3D FIELD_EX32(tb_flags, TB_FLAGS, HLSX); ctx->vill =3D FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew =3D FIELD_EX32(tb_flags, TB_FLAGS, SEW); --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:06:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248810; x=1685840810; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/1DiLPivEPqQjktvYFeG5k60WWY9PrwUsIUMOZUW7Jw=; b=WoY5WoT8ORYzcqyd/uDPqYmK7HHoqUenQTa1yb27sXUYVGzZnr06O/i2SXMKxXA0r2 HSuscHJxbLbS1C5EN6ScfRzxqkcbj6MJ0iOimpW99u6pWrziu19OgutWyf7HoyAw5CsA wLHY1zHRVHc/NtXH7slFyjq9W4N3vwak5wGnqQ6k1mX9BIks2wRPkCiZk+FskMbP0eot IjTvA6TKzaeTWqlZf49/sJbPqj1QqmSugorKPzg50arfReRVNIBCOwHKW48qaoWsM3pE rs0Z2XQ1BX1ERdzQlO5CKOc+yp5AEJhBIunV3N4oGD/M4Cm1VJtil+Bwj/HzuaVlX6/9 QgVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248810; x=1685840810; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/1DiLPivEPqQjktvYFeG5k60WWY9PrwUsIUMOZUW7Jw=; b=eYGRmvXk6fjRqkyKrMqBdO+Rb7dCta8iuSoNZvuCtiATbHbmo65uKPEZKN7zyM5DrW DNRIg7SPBexwUEv1hE5cF0XBMccNCd1nNEH+VAgwSQWJuv+WeC53XlX2CwnmQYvfK6Qp omvr3TGGmAwPla31uIyKmGv9LqXDm9dzSI3zq0X00phBXuBpFb9Lvp6jRARyZRGiiV8M BUolxnN+lh8tHaMOcBSIy2Gj+vH+1SQoPrKz84dv+v8jER1BL2e3Qy1CpX0c9iA5YiFE vlyUXoLFLwRx+8Zj3ZIhFVy5fMt8Vsn4Ph63JnU2Us74Mm2KU6dYK35Fx8ZGjd0ZbI9y l0/w== X-Gm-Message-State: AC+VfDxs9y8yp4XSjy28ibU5qBe7L2fVyW3tpu2bckXhYAUcCz26Sdui FvwFokS3oRsulV8fE9sc5K66n8C4rAiH2Q== X-Google-Smtp-Source: ACHHUZ4Y51PavqVG1Z9+Y5gc3H5TTyJ8X+ADPt0vAfsiW0mDmx1pq0+YM3AOUKdskjzt4PfzlRrSFg== X-Received: by 2002:a17:902:9a03:b0:1ab:2b41:613 with SMTP id v3-20020a1709029a0300b001ab2b410613mr5325985plp.32.1683248810216; Thu, 04 May 2023 18:06:50 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, LIU Zhiwei , Richard Henderson , Weiwei Li , Alistair Francis , Daniel Henrique Barboza Subject: [PULL 62/89] target/riscv: Add a tb flags field for vstart Date: Fri, 5 May 2023 11:02:14 +1000 Message-Id: <20230505010241.21812-63-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=alistair23@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249350987100001 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei Once we mistook the vstart directly from the env->vstart. As env->vstart is= not a constant, we should record it in the tb flags if we want to use it in translation. Reported-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: LIU Zhiwei Reviewed-by: Weiwei Li Message-Id: <20230324143031.1093-5-zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-6-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-6-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 1 + target/riscv/translate.c | 4 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 14 +++++++------- 4 files changed, 11 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ab64d5f92d..786ad047ee 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -655,6 +655,7 @@ FIELD(TB_FLAGS, VMA, 21, 1) FIELD(TB_FLAGS, ITRIGGER, 22, 1) /* Virtual mode enabled */ FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) +FIELD(TB_FLAGS, VSTART_EQ_ZERO, 24, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e3e620137b..7579e83c3d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -74,6 +74,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulon= g *pc, FIELD_EX64(env->vtype, VTYPE, VTA)); flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, FIELD_EX64(env->vtype, VTYPE, VMA)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart = =3D=3D 0); } else { flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3092c942ab..3ab8a9999e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -99,7 +99,7 @@ typedef struct DisasContext { uint8_t vta; uint8_t vma; bool cfg_vta_all_1s; - target_ulong vstart; + bool vstart_eq_zero; bool vl_eq_vlmax; CPUState *cs; TCGv zero; @@ -1168,7 +1168,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->vta =3D FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_al= l_1s; ctx->vma =3D FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_al= l_1s; ctx->cfg_vta_all_1s =3D cpu->cfg.rvv_ta_all_1s; - ctx->vstart =3D env->vstart; + ctx->vstart_eq_zero =3D FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->misa_mxl_max =3D env->misa_mxl_max; ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index ecbdf1b3d7..6c07eebc52 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -547,7 +547,7 @@ static bool vext_check_sds(DisasContext *s, int vd, int= vs1, int vs2, int vm) */ static bool vext_check_reduction(DisasContext *s, int vs2) { - return require_align(vs2, s->lmul) && (s->vstart =3D=3D 0); + return require_align(vs2, s->lmul) && s->vstart_eq_zero; } =20 /* @@ -3083,7 +3083,7 @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *a) { if (require_rvv(s) && vext_check_isa_ill(s) && - s->vstart =3D=3D 0) { + s->vstart_eq_zero) { TCGv_ptr src2, mask; TCGv dst; TCGv_i32 desc; @@ -3112,7 +3112,7 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *= a) { if (require_rvv(s) && vext_check_isa_ill(s) && - s->vstart =3D=3D 0) { + s->vstart_eq_zero) { TCGv_ptr src2, mask; TCGv dst; TCGv_i32 desc; @@ -3148,7 +3148,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ vext_check_isa_ill(s) && \ require_vm(a->vm, a->rd) && \ (a->rd !=3D a->rs2) && \ - (s->vstart =3D=3D 0)) { \ + s->vstart_eq_zero) { \ uint32_t data =3D 0; \ gen_helper_gvec_3_ptr *fn =3D gen_helper_##NAME; \ TCGLabel *over =3D gen_new_label(); \ @@ -3189,7 +3189,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_= m *a) !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) && require_vm(a->vm, a->rd) && require_align(a->rd, s->lmul) && - (s->vstart =3D=3D 0)) { + s->vstart_eq_zero) { uint32_t data =3D 0; TCGLabel *over =3D gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); @@ -3638,7 +3638,7 @@ static bool vcompress_vm_check(DisasContext *s, arg_r= *a) require_align(a->rs2, s->lmul) && (a->rd !=3D a->rs2) && !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs1, 1) && - (s->vstart =3D=3D 0); + s->vstart_eq_zero; } =20 static bool trans_vcompress_vm(DisasContext *s, arg_r *a) @@ -3677,7 +3677,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME = * a) \ QEMU_IS_ALIGNED(a->rd, LEN) && \ QEMU_IS_ALIGNED(a->rs2, LEN)) { \ uint32_t maxsz =3D (s->cfg_ptr->vlen >> 3) * LEN; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:06:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248814; x=1685840814; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8F3Sjh0q82oloWl6cV86F6NpqB0/qVOCdqaCJ4JeI3s=; b=C54y8DjQrZk/C950cf8E2E6tGH8hDsgvzwuZzijzjQA+MX5vHcrRh7/zcpg4OJbeGI dSbynyliiX914wHGGSYbwar6qlcMmt6BMBZ06d49JtnQcaXOOLdaeKzgnZQ0OkqUQbNk j8EDxM5Hjx+dqkKKfo8jS+1I6YXFW0wlW3JCPPw6nXHffx7RTaxbxqhnVb9vE6mTr2D0 vot1bhX8o1sSphxVr1TwQXW/69KGmjCJpNukZSyryuYiZNuvfmeh7z7H/N3O7Q69Qbya iEuOz3DSJFaGiR6CDHLNWPZG8q7CwDmhU3eVjfmHl25mEl5KExXP7ZXPuc/C2KUNzG5V 58hA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248814; x=1685840814; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8F3Sjh0q82oloWl6cV86F6NpqB0/qVOCdqaCJ4JeI3s=; b=dTNlS5RBdKK39qm+Zix39qpAOru/AWc0qKKf9myX+ZI+NbS+o0FbvbwG1nCZ9+1eEe 8x+rqLVQRBHY/VVJ0WY92rdiAJuJ3zRvwm4P97x2KBCnEj6wR7x5p9vRTHljEnxAbQ+m NK2RAACJJXnY5AfYojDNbZp31qXcoYLGMmxPdABfRHuDzvix5KeSEX99DZhmaNAi/zb/ WwIoL3HF8TIry177ux1IeR6Vv6bc3vtKadsB1jzmhIj2Pb3+TQhpK8IVV8rZoPpr+E3a oJJBUVpm+u7Vyd/RwgZKqeVLbJw7uRTE5iX4HKNH5ZHVPFSprZtZF+TXXSrcCkLSXiW4 F99A== X-Gm-Message-State: AC+VfDxiHN04FMQQLiSrMoxQgi4/NtFg0uWqXFI7LIfU6mcDpEn6J/9A lytOjswFbn+8xzON15w6YjMb3Rp4w0oAPA== X-Google-Smtp-Source: ACHHUZ6uvpbNk7U/gO04zg6Hr91A7/I9NXVo02k8w+s4TQwgIMDPNWoixtFWf+AfEN+ywINpPyBwMA== X-Received: by 2002:a17:902:d490:b0:1ab:d2c:a1a6 with SMTP id c16-20020a170902d49000b001ab0d2ca1a6mr6349822plg.69.1683248814342; Thu, 04 May 2023 18:06:54 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Fei Wu , Richard Henderson , LIU Zhiwei , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 63/89] target/riscv: Separate priv from mmu_idx Date: Fri, 5 May 2023 11:02:15 +1000 Message-Id: <20230505010241.21812-64-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249480145100017 Content-Type: text/plain; charset="utf-8" From: Fei Wu Currently it's assumed the 2 low bits of mmu_idx map to privilege mode, this assumption won't last as we are about to add more mmu_idx. Here an individual priv field is added into TB_FLAGS. Reviewed-by: Richard Henderson Signed-off-by: Fei Wu Message-Id: <20230324054154.414846-2-fei2.wu@intel.com> Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-7-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-7-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/cpu_helper.c | 4 +++- target/riscv/translate.c | 2 ++ target/riscv/insn_trans/trans_privileged.c.inc | 2 +- target/riscv/insn_trans/trans_xthead.c.inc | 14 +------------- 5 files changed, 8 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 786ad047ee..9b971ee1b0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -629,7 +629,6 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *en= v, target_ulong riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); =20 -#define TB_FLAGS_PRIV_MMU_MASK 3 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) =20 #include "exec/cpu-all.h" @@ -656,6 +655,7 @@ FIELD(TB_FLAGS, ITRIGGER, 22, 1) /* Virtual mode enabled */ FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) FIELD(TB_FLAGS, VSTART_EQ_ZERO, 24, 1) +FIELD(TB_FLAGS, PRIV, 25, 2) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 7579e83c3d..36d6e422d7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -83,6 +83,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulon= g *pc, fs =3D EXT_STATUS_DIRTY; vs =3D EXT_STATUS_DIRTY; #else + flags =3D FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); + flags |=3D cpu_mmu_index(env, 0); fs =3D get_field(env->mstatus, MSTATUS_FS); vs =3D get_field(env->mstatus, MSTATUS_VS); @@ -751,7 +753,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, */ MemTxResult res; MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; - int mode =3D mmu_idx & TB_FLAGS_PRIV_MMU_MASK; + int mode =3D env->priv; bool use_background =3D false; hwaddr ppn; int napot_bits =3D 0; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3ab8a9999e..6d59348f0c 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -67,6 +67,7 @@ typedef struct DisasContext { RISCVExtStatus mstatus_fs; RISCVExtStatus mstatus_vs; uint32_t mem_idx; + uint32_t priv; /* * Remember the rounding mode encoded in the previous fp instruction, * which we have already installed into env->fp_status. Or -1 for @@ -1153,6 +1154,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) uint32_t tb_flags =3D ctx->base.tb->flags; =20 ctx->pc_succ_insn =3D ctx->base.pc_first; + ctx->priv =3D FIELD_EX32(tb_flags, TB_FLAGS, PRIV); ctx->mem_idx =3D FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); ctx->mstatus_fs =3D FIELD_EX32(tb_flags, TB_FLAGS, FS); ctx->mstatus_vs =3D FIELD_EX32(tb_flags, TB_FLAGS, VS); diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index e3bee971c6..7c2837194c 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -52,7 +52,7 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) * that no exception will be raised when fetching them. */ =20 - if (semihosting_enabled(ctx->mem_idx < PRV_S) && + if (semihosting_enabled(ctx->priv =3D=3D PRV_U) && (pre_addr & TARGET_PAGE_MASK) =3D=3D (post_addr & TARGET_PAGE_MASK= )) { pre =3D opcode_at(&ctx->base, pre_addr); ebreak =3D opcode_at(&ctx->base, ebreak_addr); diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index df504c3f2c..3e13b1d74d 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -263,25 +263,13 @@ static bool trans_th_tst(DisasContext *ctx, arg_th_ts= t *a) =20 /* XTheadCmo */ =20 -static inline int priv_level(DisasContext *ctx) -{ -#ifdef CONFIG_USER_ONLY - return PRV_U; -#else - /* Priv level is part of mem_idx. */ - return ctx->mem_idx & TB_FLAGS_PRIV_MMU_MASK; -#endif -} - /* Test if priv level is M, S, or U (cannot fail). */ #define REQUIRE_PRIV_MSU(ctx) =20 /* Test if priv level is M or S. */ #define REQUIRE_PRIV_MS(ctx) \ do { \ - int priv =3D priv_level(ctx); \ - if (!(priv =3D=3D PRV_M || \ - priv =3D=3D PRV_S)) { \ + if (ctx->priv =3D=3D PRV_U) { \ return false; \ } \ } while (0) --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249475; cv=none; d=zohomail.com; s=zohoarc; b=M7M20XfKXZ3S47Nwz0wCzQ57sEvCyjNqkgfFRuMi/eRWqDZq0njcYkrJQ+ruR/HxapKEpN9fTOvp+tkFQ9V+rya3SK7lmItUpGwP08Mnk4lmpcX2s83Nsu0v+jBigbh41ZdtqScfL1I8DujnKgwqYqSyIn2EMffj8zpAh9O5hDk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249475; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JbBMk9JLIxgutGnQaDrHlYakr8/72eeE7gqabzbXCvE=; b=fXhTAF4krRpklz7Mz/QmIZZxp61vB4gUcgN55Uywm/3inoYH8Iwq704ym+cr2P2m5rb6H9TuQ1r6RblfKsUEVwV+miN6nrwf2NoHB0nwfGM9lIIWz61yeakLmLBTGEkgWuxGXM5BhfTiNY3IVyP61BSxiPnmalFaIhP44hcxCR8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249475689838.9050345873093; Thu, 4 May 2023 18:17:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujut-0000AP-Ob; Thu, 04 May 2023 21:07:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujuZ-0008Fa-Np for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:05 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujuV-0007vW-Vq for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:01 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1aaef97652fso8106825ad.0 for ; Thu, 04 May 2023 18:06:59 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:06:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248818; x=1685840818; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JbBMk9JLIxgutGnQaDrHlYakr8/72eeE7gqabzbXCvE=; b=ZvWqvLt+b49zjU5wt2Vj6sJlfWw7s1Bi7Vki0HGrV2Pi9Q2tdHkt0/UyTODwXOp3jr CTlCp+jiYjnome/nYSVAawnYn3ha+e9Q+hAWYErciYfbqzdzUH2lHFDmmApVo4ZyU7gG jAk95bP3QJrphK6VINqOoErawRnYPXFaUgI/4m72o9KplI6eyNKtqPLGotf8y/A7Mx4i xB4CWZ1XMPGXmAJymPsFVA8B1uMN2mbeEA1rW3S8EHpZntnNN9Rf+rcNi0y1Vhe3VAvP z7EG5eGYm3z0xFXFFlxrsIweorMFXaUIjlvhQJCStO8pMsTzGvhSocX4c9zXWyeskRkv IG1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248818; x=1685840818; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JbBMk9JLIxgutGnQaDrHlYakr8/72eeE7gqabzbXCvE=; b=Mnf7k2CjBUFbBPk2zp9UklTI9YmqiYRknYemSsMXTqDbq2hzropojs2pwllJyWxMzI DWlu9g5zrVkt5vyHsBbuigeu1enktWWQ2R1+0UtMFpGgtE6q/QSA6bmdzpiObIRGxlci Lg2PRYKBzu6R6q5xbO5ZeNQSEwdj0vK0apw5lRhJKBnHXpKQrq+qO8ZO5bTPgbzzOvqY xA9fFSp9nka6HmRNBFu5IEEms293Rs0KPFyx3krGVENCpm7X6swCGRn5kBD2WfzfAyhT 2fxY8XXDUqzSKWNl7bG/FE66bXE9KyQloy+yU20o7ir0Y7c4gTDz6DHZlFKQuznH8fhR n24Q== X-Gm-Message-State: AC+VfDy4GouPWsVa82lc7BJy15Rllz/NcbbcI46PchcDnMlC3qYpImxG zshevipb7y/PMOeVsUIfZmuH6a5nSbUfPQ== X-Google-Smtp-Source: ACHHUZ7ohM+hxpEvIm4j7Nf3NygOFZU8wrBfQ7U3saZf7EGxBSgid2iJqc3seCjSr1Svd1o4YYW9LQ== X-Received: by 2002:a17:902:e808:b0:1a9:8d57:6d6c with SMTP id u8-20020a170902e80800b001a98d576d6cmr6810542plg.24.1683248818432; Thu, 04 May 2023 18:06:58 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Fei Wu , Richard Henderson , LIU Zhiwei , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 64/89] target/riscv: Reduce overhead of MSTATUS_SUM change Date: Fri, 5 May 2023 11:02:16 +1000 Message-Id: <20230505010241.21812-65-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249476291100001 Content-Type: text/plain; charset="utf-8" From: Fei Wu Kernel needs to access user mode memory e.g. during syscalls, the window is usually opened up for a very limited time through MSTATUS.SUM, the overhead is too much if tlb_flush() gets called for every SUM change. This patch creates a separate MMU index for S+SUM, so that it's not necessary to flush tlb anymore when SUM changes. This is similar to how ARM handles Privileged Access Never (PAN). Result of 'pipe 10' from unixbench boosts from 223656 to 1705006. Many other syscalls benefit a lot from this too. Reviewed-by: Richard Henderson Signed-off-by: Fei Wu Message-Id: <20230324054154.414846-3-fei2.wu@intel.com> Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-8-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-8-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 -- target/riscv/internals.h | 14 ++++++++++++++ target/riscv/cpu_helper.c | 17 +++++++++++++++-- target/riscv/csr.c | 3 +-- target/riscv/op_helper.c | 5 +++-- target/riscv/insn_trans/trans_rvh.c.inc | 4 ++-- 6 files changed, 35 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9b971ee1b0..6239c99f4c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -629,8 +629,6 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *en= v, target_ulong riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); =20 -#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) - #include "exec/cpu-all.h" =20 FIELD(TB_FLAGS, MEM_IDX, 0, 3) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 5620fbffb6..b55152a7dc 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -21,6 +21,20 @@ =20 #include "hw/registerfields.h" =20 +/* + * The current MMU Modes are: + * - U 0b000 + * - S 0b001 + * - S+SUM 0b010 + * - M 0b011 + * - HLV/HLVX/HSV adds 0b100 + */ +#define MMUIdx_U 0 +#define MMUIdx_S 1 +#define MMUIdx_S_SUM 2 +#define MMUIdx_M 3 +#define MMU_HYP_ACCESS_BIT (1 << 2) + /* share data between vector helpers and decode code */ FIELD(VDATA, VM, 0, 1) FIELD(VDATA, LMUL, 1, 3) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 36d6e422d7..174a77706b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "qemu/main-loop.h" #include "cpu.h" +#include "internals.h" #include "pmu.h" #include "exec/exec-all.h" #include "instmap.h" @@ -36,7 +37,19 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #ifdef CONFIG_USER_ONLY return 0; #else - return env->priv; + if (ifetch) { + return env->priv; + } + + /* All priv -> mmu_idx mapping are here */ + int mode =3D env->priv; + if (mode =3D=3D PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { + mode =3D get_field(env->mstatus, MSTATUS_MPP); + } + if (mode =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_SUM)) { + return MMUIdx_S_SUM; + } + return mode; #endif } =20 @@ -588,7 +601,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, boo= l enable) =20 bool riscv_cpu_two_stage_lookup(int mmu_idx) { - return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; + return mmu_idx & MMU_HYP_ACCESS_BIT; } =20 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 92ad54411b..4a4d852bd1 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1294,8 +1294,7 @@ static RISCVException write_mstatus(CPURISCVState *en= v, int csrno, val =3D legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val); =20 /* flush tlb on mstatus fields that affect VM */ - if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | - MSTATUS_MPRV | MSTATUS_SUM)) { + if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPV)) { tlb_flush(env_cpu(env)); } mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 0c10dd7a78..0adfd1ca9a 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -20,6 +20,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "internals.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -428,14 +429,14 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) =20 target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address) { - int mmu_idx =3D cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK; + int mmu_idx =3D cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT; =20 return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); } =20 target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address) { - int mmu_idx =3D cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK; + int mmu_idx =3D cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT; =20 return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); } diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index 4b730cd492..ae98b45e5e 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -42,7 +42,7 @@ static bool do_hlv(DisasContext *ctx, arg_r2 *a, MemOp mo= p) if (check_access(ctx)) { TCGv dest =3D dest_gpr(ctx, a->rd); TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - int mem_idx =3D ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK; + int mem_idx =3D ctx->mem_idx | MMU_HYP_ACCESS_BIT; tcg_gen_qemu_ld_tl(dest, addr, mem_idx, mop); gen_set_gpr(ctx, a->rd, dest); } @@ -89,7 +89,7 @@ static bool do_hsv(DisasContext *ctx, arg_r2_s *a, MemOp = mop) if (check_access(ctx)) { TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); - int mem_idx =3D ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK; + int mem_idx =3D ctx->mem_idx | MMU_HYP_ACCESS_BIT; tcg_gen_qemu_st_tl(data, addr, mem_idx, mop); } return true; --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.06.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248822; x=1685840822; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=APvvZooxKzMDjU/SEAU1BSPZSDT4yDNWxKxwghZLWeA=; b=YnSPJFDi2QS3XwmsDUzZdvMgDYea39r/kwJLlxfsNcCTABUx4u2IXjOj6KoVtmG6h9 Y0l3Bb3JBl3RIdvH1MdtW7fWUUVmGLXpnaCE0SsrBQg+Dk2tP85yioM79F3zC9E1qqeX vi77n+0hKqTAbHXkNs4w1z6FD80tk+Soi2odT3NVyzEy5BAazjS0E5v6KcpzV9IQwi/t VoKKK5DZvpS4HvcSNoZ1IRUF34ny1MjZVDPh4WwF2hL3sS1kSWkHAUcwWtE9SepNeonz HSbVhByRBltwbIUdS7XsLbNeaUE/JKYD9RiYGKiRFHY5HrvMzhgfsi7NlxXw2hcBmaU+ qrFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248822; x=1685840822; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=APvvZooxKzMDjU/SEAU1BSPZSDT4yDNWxKxwghZLWeA=; b=gxRP5SGDsKdHI3DMnl/xodGIbgoA06EZyHlWl7C5ouA/ULTpTwujcvGenS6Ag9e18v Cf87uenhnci8yJOAQqJUfnRvS5LkYzJ8rfwkU4rFaQgy+9xMGzjMTdSa3n4hl3mpkQHX tf5HDKvF7AXvi/pjB9VwSUjt5d9Dc1V3ehQ1BoBZ6Q1Q15yqVnJOhdyNEGTJyEkCsAD5 8go4119qTKdf7Il7bDL1g1QVEMFw4CV4+C6yWSZ/BVE3CE8LYZGY8f0t0oLVcTlpp2DB 1ZzHwTO82PX6NyNaRL8EOgSQ1l79VLzkGB6Twf6NCKOANkEhXhe9jjOD0ci9EmscBTSz RTkQ== X-Gm-Message-State: AC+VfDynbLCjSrsFx8HNoiG2SU73Y8rFDbwss3jAYtB7Y20T7COJD4IV Ut+3x7RxkovKPKk4jKqUhTfvfEn5aOlxDg== X-Google-Smtp-Source: ACHHUZ4qL6qH0JeZup0ANp1txO9nR1NLAsFLyYq/M+6icira9o80YYkZH1sgco5PibWjhbbOwDoRYw== X-Received: by 2002:a17:902:f546:b0:1a3:dcc1:307d with SMTP id h6-20020a170902f54600b001a3dcc1307dmr6869053plf.23.1683248821807; Thu, 04 May 2023 18:07:01 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX Date: Fri, 5 May 2023 11:02:17 +1000 Message-Id: <20230505010241.21812-66-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=alistair23@gmail.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249397132100017 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use the new functions to properly check execute permission for the read rather than read permission. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-10-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-10-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/op_helper.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 0adfd1ca9a..49179e7a5a 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -427,18 +427,27 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) helper_hyp_tlb_flush(env); } =20 +/* + * TODO: These implementations are not quite correct. They perform the + * access using execute permission just fine, but the final PMP check + * is supposed to have read permission as well. Without replicating + * a fair fraction of cputlb.c, fixing this requires adding new mmu_idx + * which would imply that exact check in tlb_fill. + */ target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address) { int mmu_idx =3D cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT; + MemOpIdx oi =3D make_memop_idx(MO_TEUW, mmu_idx); =20 - return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); + return cpu_ldw_code_mmu(env, address, oi, GETPC()); } =20 target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address) { int mmu_idx =3D cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT; + MemOpIdx oi =3D make_memop_idx(MO_TEUL, mmu_idx); =20 - return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); + return cpu_ldl_code_mmu(env, address, oi, GETPC()); } =20 #endif /* !CONFIG_USER_ONLY */ --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249509; cv=none; d=zohomail.com; s=zohoarc; b=gtszUyN9afIBJfzKSZKbvTGPXpXANT4ymBeB1VvPUmn1yGhOKo3vPa/BxAj+OIHkIU/3NDZK/bQgxTwINNJIl9KdfmsyHKo/gsi7+mS8535UoO2sCv5sMMRlOpX22lr4zuI/TVvDbpXwJ9kmAfbGpiKgzII6MndS5HibeTgDmSk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249509; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9GsRgbG59YHzRaQ19aeOdQ0BEV/yRG7KWuiP+B9mq64=; b=T26UVYM4eg95/o3mnqmXaIbneDFq0wo6MQF0X9d1yYd4BKBm/uHHaSMNM5EN7oxbiagoJUyHcVNc9hBCekn5wH+Zq2po3lYWwYKCShDaUaiEb42Ipn8vL7g1poeiAfqOOB/bvPlL7pKwiF29/71cG3EqzGoQoT1BJeSvbwrlYfU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249509926764.822559072698; Thu, 4 May 2023 18:18:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujut-000093-3N; Thu, 04 May 2023 21:07:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujui-0008LG-7R for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:13 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujud-0007wU-EZ for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:10 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1ab267e3528so8676475ad.0 for ; Thu, 04 May 2023 18:07:06 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248825; x=1685840825; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9GsRgbG59YHzRaQ19aeOdQ0BEV/yRG7KWuiP+B9mq64=; b=PLb6uwTGWRB35vb7m7/vFcIlZkR1Exz5ScqjMfS2zXq0xyW/yVs9SQaz+piaAOtlfB r8joZP4LmZ1VwIRk69wYng082LEGbvCdjqTunIb4Aq+3Z3/plzoCTTVx6Y5R74pSIBtz PLA87mCSeElON3/5J5JbXgZxDWeeSaEWfPhakv80O6D6tAoSKRMVW9u1d8+OYLvIilal zJ6HIgwsoAhBbR4Q+Z0LoaZm1DsEJXnnULxWvamL3S5ca8tSrMUha+2ogJtdpsdlUukn F0+cZLR/dcrYatxlyGYXNAcRhF+lCGI0PKKoVBLyDY/OFzOEH8pNnC4j9kSQcg3FDtdI Pl4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248825; x=1685840825; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9GsRgbG59YHzRaQ19aeOdQ0BEV/yRG7KWuiP+B9mq64=; b=jxydn7mv06801Y9ZJ7Vgx3LNYC/iqGU8HIxG3UhaH1g3q6oh+Yo5+4lj3zwrjh3SeV JWiQ2WL2zlBLmvqXUcq52HUsWosMAdX6LMDKMpZSVyiqMEyjHdGs1wZAFOyN0HtNgMZ2 FNQeUMnB6tT3pbOPQo54ZSjh7o57/+sdxHOuGxIDaYQRTOQKOYI5/ZCZzDTCvdQ+bZb6 3XEHwdVFAUnxT8PxZqL6ej4Bo0ette/DZy7jkaAuyjA0ljhS8hMXtb3kELRfg6wQJcwp rVBRstLbDo3r37pTAEfA9bodeOezH77YNORRkFaudhfuDHSmQRC3rp5XYqKYm2Re6VrQ Al3g== X-Gm-Message-State: AC+VfDzfxO7nb7BXH/TwPV+PHFdptaEXhxCApAYqgVDyBcqoO5Kh5C8f oQg4nFODtr+Bq51hCJ84kJY7tnWfUZw/SA== X-Google-Smtp-Source: ACHHUZ5ZxSZinE4iRKm2rflVICYI6VEaVyuPU/Cq97KSigrpIgjruU9XVJkgo2L8QtiMWBe4mZ5SRw== X-Received: by 2002:a17:902:e551:b0:1ac:3ddf:2299 with SMTP id n17-20020a170902e55100b001ac3ddf2299mr625042plf.44.1683248825116; Thu, 04 May 2023 18:07:05 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 66/89] target/riscv: Handle HLV, HSV via helpers Date: Fri, 5 May 2023 11:02:18 +1000 Message-Id: <20230505010241.21812-67-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249510944100002 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Implement these instructions via helpers, in expectation of determining the mmu_idx to use at runtime. This allows the permission check to also be moved out of line, which allows HLSX to be removed from TB_FLAGS. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-11-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-11-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 6 +- target/riscv/helper.h | 12 ++- target/riscv/cpu_helper.c | 26 ++--- target/riscv/op_helper.c | 99 ++++++++++++++++-- target/riscv/translate.c | 2 - target/riscv/insn_trans/trans_rvh.c.inc | 129 ++++++++++-------------- 6 files changed, 165 insertions(+), 109 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6239c99f4c..35cf2e2691 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -639,8 +639,7 @@ FIELD(TB_FLAGS, LMUL, 7, 3) FIELD(TB_FLAGS, SEW, 10, 3) FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) FIELD(TB_FLAGS, VILL, 14, 1) -/* Is a Hypervisor instruction load/store allowed? */ -FIELD(TB_FLAGS, HLSX, 15, 1) +FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ FIELD(TB_FLAGS, XL, 16, 2) /* If PointerMasking should be applied */ @@ -652,8 +651,7 @@ FIELD(TB_FLAGS, VMA, 21, 1) FIELD(TB_FLAGS, ITRIGGER, 22, 1) /* Virtual mode enabled */ FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) -FIELD(TB_FLAGS, VSTART_EQ_ZERO, 24, 1) -FIELD(TB_FLAGS, PRIV, 25, 2) +FIELD(TB_FLAGS, PRIV, 24, 2) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 1880e95c50..98e97810fd 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -123,8 +123,16 @@ DEF_HELPER_1(itrigger_match, void, env) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(hyp_tlb_flush, void, env) DEF_HELPER_1(hyp_gvma_tlb_flush, void, env) -DEF_HELPER_2(hyp_hlvx_hu, tl, env, tl) -DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlv_bu, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlv_hu, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlv_wu, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlv_d, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlvx_hu, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlvx_wu, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_3(hyp_hsv_b, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(hyp_hsv_h, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(hyp_hsv_w, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(hyp_hsv_d, TCG_CALL_NO_WG, void, env, tl, tl) #endif =20 /* Vector functions */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 174a77706b..abf275d2c6 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -102,24 +102,16 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_= ulong *pc, fs =3D get_field(env->mstatus, MSTATUS_FS); vs =3D get_field(env->mstatus, MSTATUS_VS); =20 - if (riscv_has_ext(env, RVH)) { - if (env->priv =3D=3D PRV_M || - (env->priv =3D=3D PRV_S && !env->virt_enabled) || - (env->priv =3D=3D PRV_U && !env->virt_enabled && - get_field(env->hstatus, HSTATUS_HU))) { - flags =3D FIELD_DP32(flags, TB_FLAGS, HLSX, 1); - } - - if (env->virt_enabled) { - flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); - /* - * Merge DISABLED and !DIRTY states using MIN. - * We will set both fields when dirtying. - */ - fs =3D MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); - vs =3D MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); - } + if (env->virt_enabled) { + flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); + /* + * Merge DISABLED and !DIRTY states using MIN. + * We will set both fields when dirtying. + */ + fs =3D MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); + vs =3D MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); } + if (cpu->cfg.debug && !icount_enabled()) { flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 49179e7a5a..7f83395370 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -427,6 +427,91 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) helper_hyp_tlb_flush(env); } =20 +static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra) +{ + if (env->priv =3D=3D PRV_M) { + /* always allowed */ + } else if (env->virt_enabled) { + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra); + } else if (env->priv =3D=3D PRV_U && !get_field(env->hstatus, HSTATUS_= HU)) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); + } + + return cpu_mmu_index(env, x) | MMU_HYP_ACCESS_BIT; +} + +target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr) +{ + uintptr_t ra =3D GETPC(); + int mmu_idx =3D check_access_hlsv(env, false, ra); + MemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); + + return cpu_ldb_mmu(env, addr, oi, ra); +} + +target_ulong helper_hyp_hlv_hu(CPURISCVState *env, target_ulong addr) +{ + uintptr_t ra =3D GETPC(); + int mmu_idx =3D check_access_hlsv(env, false, ra); + MemOpIdx oi =3D make_memop_idx(MO_TEUW, mmu_idx); + + return cpu_ldw_mmu(env, addr, oi, ra); +} + +target_ulong helper_hyp_hlv_wu(CPURISCVState *env, target_ulong addr) +{ + uintptr_t ra =3D GETPC(); + int mmu_idx =3D check_access_hlsv(env, false, ra); + MemOpIdx oi =3D make_memop_idx(MO_TEUL, mmu_idx); + + return cpu_ldl_mmu(env, addr, oi, ra); +} + +target_ulong helper_hyp_hlv_d(CPURISCVState *env, target_ulong addr) +{ + uintptr_t ra =3D GETPC(); + int mmu_idx =3D check_access_hlsv(env, false, ra); + MemOpIdx oi =3D make_memop_idx(MO_TEUQ, mmu_idx); + + return cpu_ldq_mmu(env, addr, oi, ra); +} + +void helper_hyp_hsv_b(CPURISCVState *env, target_ulong addr, target_ulong = val) +{ + uintptr_t ra =3D GETPC(); + int mmu_idx =3D check_access_hlsv(env, false, ra); + MemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); + + cpu_stb_mmu(env, addr, val, oi, ra); +} + +void helper_hyp_hsv_h(CPURISCVState *env, target_ulong addr, target_ulong = val) +{ + uintptr_t ra =3D GETPC(); + int mmu_idx =3D check_access_hlsv(env, false, ra); + MemOpIdx oi =3D make_memop_idx(MO_TEUW, mmu_idx); + + cpu_stw_mmu(env, addr, val, oi, ra); +} + +void helper_hyp_hsv_w(CPURISCVState *env, target_ulong addr, target_ulong = val) +{ + uintptr_t ra =3D GETPC(); + int mmu_idx =3D check_access_hlsv(env, false, ra); + MemOpIdx oi =3D make_memop_idx(MO_TEUL, mmu_idx); + + cpu_stl_mmu(env, addr, val, oi, ra); +} + +void helper_hyp_hsv_d(CPURISCVState *env, target_ulong addr, target_ulong = val) +{ + uintptr_t ra =3D GETPC(); + int mmu_idx =3D check_access_hlsv(env, false, ra); + MemOpIdx oi =3D make_memop_idx(MO_TEUQ, mmu_idx); + + cpu_stq_mmu(env, addr, val, oi, ra); +} + /* * TODO: These implementations are not quite correct. They perform the * access using execute permission just fine, but the final PMP check @@ -434,20 +519,22 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) * a fair fraction of cputlb.c, fixing this requires adding new mmu_idx * which would imply that exact check in tlb_fill. */ -target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address) +target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong addr) { - int mmu_idx =3D cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT; + uintptr_t ra =3D GETPC(); + int mmu_idx =3D check_access_hlsv(env, true, ra); MemOpIdx oi =3D make_memop_idx(MO_TEUW, mmu_idx); =20 - return cpu_ldw_code_mmu(env, address, oi, GETPC()); + return cpu_ldw_code_mmu(env, addr, oi, GETPC()); } =20 -target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address) +target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong addr) { - int mmu_idx =3D cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT; + uintptr_t ra =3D GETPC(); + int mmu_idx =3D check_access_hlsv(env, true, ra); MemOpIdx oi =3D make_memop_idx(MO_TEUL, mmu_idx); =20 - return cpu_ldl_code_mmu(env, address, oi, GETPC()); + return cpu_ldl_code_mmu(env, addr, oi, ra); } =20 #endif /* !CONFIG_USER_ONLY */ diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6d59348f0c..928da0d3f0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -80,7 +80,6 @@ typedef struct DisasContext { bool virt_inst_excp; bool virt_enabled; const RISCVCPUConfig *cfg_ptr; - bool hlsx; /* vector extension */ bool vill; /* @@ -1163,7 +1162,6 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->misa_ext =3D env->misa_ext; ctx->frm =3D -1; /* unknown rounding mode */ ctx->cfg_ptr =3D &(cpu->cfg); - ctx->hlsx =3D FIELD_EX32(tb_flags, TB_FLAGS, HLSX); ctx->vill =3D FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew =3D FIELD_EX32(tb_flags, TB_FLAGS, SEW); ctx->lmul =3D sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index ae98b45e5e..3e9322130f 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -16,158 +16,131 @@ * this program. If not, see . */ =20 -#ifndef CONFIG_USER_ONLY -static bool check_access(DisasContext *ctx) -{ - if (!ctx->hlsx) { - tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, - offsetof(CPURISCVState, bins)); - if (ctx->virt_enabled) { - generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); - } else { - generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); - } - return false; - } +#ifdef CONFIG_USER_ONLY +#define do_hlv(ctx, a, func) false +#define do_hsv(ctx, a, func) false +#else +static void gen_helper_hyp_hlv_b(TCGv r, TCGv_env e, TCGv a) +{ + gen_helper_hyp_hlv_bu(r, e, a); + tcg_gen_ext8s_tl(r, r); +} + +static void gen_helper_hyp_hlv_h(TCGv r, TCGv_env e, TCGv a) +{ + gen_helper_hyp_hlv_hu(r, e, a); + tcg_gen_ext16s_tl(r, r); +} + +static void gen_helper_hyp_hlv_w(TCGv r, TCGv_env e, TCGv a) +{ + gen_helper_hyp_hlv_wu(r, e, a); + tcg_gen_ext32s_tl(r, r); +} + +static bool do_hlv(DisasContext *ctx, arg_r2 *a, + void (*func)(TCGv, TCGv_env, TCGv)) +{ + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + + decode_save_opc(ctx); + func(dest, cpu_env, addr); + gen_set_gpr(ctx, a->rd, dest); return true; } -#endif =20 -static bool do_hlv(DisasContext *ctx, arg_r2 *a, MemOp mop) +static bool do_hsv(DisasContext *ctx, arg_r2_s *a, + void (*func)(TCGv_env, TCGv, TCGv)) { -#ifdef CONFIG_USER_ONLY - return false; -#else + TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); + decode_save_opc(ctx); - if (check_access(ctx)) { - TCGv dest =3D dest_gpr(ctx, a->rd); - TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - int mem_idx =3D ctx->mem_idx | MMU_HYP_ACCESS_BIT; - tcg_gen_qemu_ld_tl(dest, addr, mem_idx, mop); - gen_set_gpr(ctx, a->rd, dest); - } + func(cpu_env, addr, data); return true; -#endif } +#endif /* CONFIG_USER_ONLY */ =20 static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a) { REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_SB); + return do_hlv(ctx, a, gen_helper_hyp_hlv_b); } =20 static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a) { REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_TESW); + return do_hlv(ctx, a, gen_helper_hyp_hlv_h); } =20 static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a) { REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_TESL); + return do_hlv(ctx, a, gen_helper_hyp_hlv_w); } =20 static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a) { REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_UB); + return do_hlv(ctx, a, gen_helper_hyp_hlv_bu); } =20 static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a) { REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_TEUW); -} - -static bool do_hsv(DisasContext *ctx, arg_r2_s *a, MemOp mop) -{ -#ifdef CONFIG_USER_ONLY - return false; -#else - decode_save_opc(ctx); - if (check_access(ctx)) { - TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); - int mem_idx =3D ctx->mem_idx | MMU_HYP_ACCESS_BIT; - tcg_gen_qemu_st_tl(data, addr, mem_idx, mop); - } - return true; -#endif + return do_hlv(ctx, a, gen_helper_hyp_hlv_hu); } =20 static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a) { REQUIRE_EXT(ctx, RVH); - return do_hsv(ctx, a, MO_SB); + return do_hsv(ctx, a, gen_helper_hyp_hsv_b); } =20 static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a) { REQUIRE_EXT(ctx, RVH); - return do_hsv(ctx, a, MO_TESW); + return do_hsv(ctx, a, gen_helper_hyp_hsv_h); } =20 static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a) { REQUIRE_EXT(ctx, RVH); - return do_hsv(ctx, a, MO_TESL); + return do_hsv(ctx, a, gen_helper_hyp_hsv_w); } =20 static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_TEUL); + return do_hlv(ctx, a, gen_helper_hyp_hlv_wu); } =20 static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_TEUQ); + return do_hlv(ctx, a, gen_helper_hyp_hlv_d); } =20 static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); - return do_hsv(ctx, a, MO_TEUQ); -} - -#ifndef CONFIG_USER_ONLY -static bool do_hlvx(DisasContext *ctx, arg_r2 *a, - void (*func)(TCGv, TCGv_env, TCGv)) -{ - decode_save_opc(ctx); - if (check_access(ctx)) { - TCGv dest =3D dest_gpr(ctx, a->rd); - TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - func(dest, cpu_env, addr); - gen_set_gpr(ctx, a->rd, dest); - } - return true; + return do_hsv(ctx, a, gen_helper_hyp_hsv_d); } -#endif =20 static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a) { REQUIRE_EXT(ctx, RVH); -#ifndef CONFIG_USER_ONLY - return do_hlvx(ctx, a, gen_helper_hyp_hlvx_hu); -#else - return false; -#endif + return do_hlv(ctx, a, gen_helper_hyp_hlvx_hu); } =20 static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a) { REQUIRE_EXT(ctx, RVH); -#ifndef CONFIG_USER_ONLY - return do_hlvx(ctx, a, gen_helper_hyp_hlvx_wu); -#else - return false; -#endif + return do_hlv(ctx, a, gen_helper_hyp_hlvx_wu); } =20 static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248828; x=1685840828; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+n36tMTZvWq86F1D3ut0hsueUyzrn9pMgnXvfb62RmU=; b=l6u5jAnXFs8NSj//FeueGg4UIy/ZMAwCyR3npYXBSsK0VsxjL4TgRAXGzZ5c+bzQqM rcEAxbHE/JpSEzTPaQ/aT5H+zZo9C2YefO7U+vjCLQrP08mZdomFrpuLs0o3z/Ycda/I tvUecpnoSal4RNrL+7Tz1FEmDrbyoBJL91MblEOdW1LxIJsOAgHsqLQzA+WmdjhMYVfj DTySJQykJgGUVcM7yvzDKeZB7jXo1Q36nO4TlsY1kBfoFXPP4hFypCr7Sb8fycRN1W2G mW/iYBLR8bFfKmwwG1qVe/XnOL7Phkm5cOV7t2wXaHR1FZfp66iek3MDUKuDEt0kGkf/ /Qxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248828; x=1685840828; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+n36tMTZvWq86F1D3ut0hsueUyzrn9pMgnXvfb62RmU=; b=QG87HGY/rWIOtQ3tu+q6BaPihCb3hDxM5DUSEoTYAX7+7N+9wt6m5/EnT/BdPUXb8j l9AUFnO6sXvrWEtXekiI3x6HoWLM5+2QAp8SHPSysBeU+CkuwleYcWAWomLlaGNd4dis PqhO4x1GT4t/L/hO+JJ9eKt5ekMSzTF0DD21zma+jCsOlxThD9uPrFbpkawZXSSxrgTz CuJrqYUuefw8jLHuiGpAin1A9WO+JGK78r7c38N7/SkzT499WAyPf7imYeSc/BVz/rcB GXBiVrKUsHjOaaJeZCLzgwjO3JWvd332e/T6V1YNoTDEF1vX/Dk5xOoLgVTq18/qUnDK 2Quw== X-Gm-Message-State: AC+VfDz6BvzHwnpUcAw2pQJ0233myFaWFZdUg7vU9Hep2+zE82iZxd3F nIKWi+SJ/7SmE3TzQJ96h/Vrql1GQSfcWw== X-Google-Smtp-Source: ACHHUZ5Lc2uWmKl7KCCIBMVTrhNlE7duH3wN7nmDbxUCK/ippT/C/Bc60OYyX2T7ArU5E6z/oFEi0Q== X-Received: by 2002:a17:902:d4d1:b0:1ab:2a77:6f4b with SMTP id o17-20020a170902d4d100b001ab2a776f4bmr6024437plg.26.1683248828444; Thu, 04 May 2023 18:07:08 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT Date: Fri, 5 May 2023 11:02:19 +1000 Message-Id: <20230505010241.21812-68-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=alistair23@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249236693100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson We will enable more uses of this bit in the future. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-12-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-12-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/internals.h | 6 ++++-- target/riscv/cpu_helper.c | 2 +- target/riscv/op_helper.c | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index b55152a7dc..7b63c0f1b6 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -27,13 +27,15 @@ * - S 0b001 * - S+SUM 0b010 * - M 0b011 - * - HLV/HLVX/HSV adds 0b100 + * - U+2STAGE 0b100 + * - S+2STAGE 0b101 + * - S+SUM+2STAGE 0b110 */ #define MMUIdx_U 0 #define MMUIdx_S 1 #define MMUIdx_S_SUM 2 #define MMUIdx_M 3 -#define MMU_HYP_ACCESS_BIT (1 << 2) +#define MMU_2STAGE_BIT (1 << 2) =20 /* share data between vector helpers and decode code */ FIELD(VDATA, VM, 0, 1) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index abf275d2c6..291a1acbf7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -593,7 +593,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, boo= l enable) =20 bool riscv_cpu_two_stage_lookup(int mmu_idx) { - return mmu_idx & MMU_HYP_ACCESS_BIT; + return mmu_idx & MMU_2STAGE_BIT; } =20 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 7f83395370..6122f5fbe5 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -437,7 +437,7 @@ static int check_access_hlsv(CPURISCVState *env, bool x= , uintptr_t ra) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } =20 - return cpu_mmu_index(env, x) | MMU_HYP_ACCESS_BIT; + return cpu_mmu_index(env, x) | MMU_2STAGE_BIT; } =20 target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr) --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249467; cv=none; d=zohomail.com; s=zohoarc; b=iNM0WhKlsG5hob/+x+3WndrURxE7O5u2xCccjy1aG9uqtDh/a2F/awvFGEhdCApnrlKhmS1hOpeDrPmvkGXD12X404vwBLb/nS6DJPb62oWy46fuK89zSPFBQaMHXGjixlYWA1iaMZtpC1O6GXHAhI4c3a70YbpOf8D7hg62ni0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249467; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hnAT6rPeWHhnyQGQh4TsIFOiMxMNe6JrOBOWyeNI6yQ=; b=h4I/sIRuORQKSDkJizQ2pSEpU96CkH0eu6UiZFtw+6BoY5m66TFVruEkPS3R9oZ5ISAoZAvL2n7GeKHIGhKoUPVSU9R/ZlPXGBdkvfEkdgpXwwbfyDV88R/h/cF0wQ9mkJ8bNGXjr7KGUTlgpDeBzj0JebN78c2oEN4YnRFilac= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168324946722171.69500048919417; Thu, 4 May 2023 18:17:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujus-0008Qc-6L; Thu, 04 May 2023 21:07:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujul-0008NJ-Pg for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:17 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujuk-0007xo-6e for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:15 -0400 Received: by mail-pg1-x52b.google.com with SMTP id 41be03b00d2f7-517bfdf55c3so565171a12.2 for ; Thu, 04 May 2023 18:07:13 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248832; x=1685840832; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hnAT6rPeWHhnyQGQh4TsIFOiMxMNe6JrOBOWyeNI6yQ=; b=WBSIhKitK//PtL8Phzk+EE/bAf93oTHQPuBwkZRwmr8E4oLTuPN+iIEXHFP3qaIQLF kwXdAnccbuDRalyQyBSnCivqMc+me+rClhUEH4WSslN7EPcVcVDmGCV3FzbTgZquOA8+ GLpZVMHoTqJJFwVP9xSZrtGeeqHAk9WMVE0ixf22Cm9AES3ZYLEHYXMUxvLWl2ldv7gb SKq1gRiv0Fv5BE0rjuTTcofv+S+R6d01keHSbEP6kZPDqPieTJGYyO3n0NOfwgDVwDfj TWD+hzqFik+EQFt6vtb8h3th7xiq/UVkoW4ifr5GVXkEf6faJuOzTmPdDX5iI+WSPMHS ZPiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248832; x=1685840832; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hnAT6rPeWHhnyQGQh4TsIFOiMxMNe6JrOBOWyeNI6yQ=; b=H0Ymyrr505E+oz16SmNJ4TlAaymmpO3FOJrB3yasiTJy9a4Jn2oHVtYejiyyCY+NLj GT0tdwmQ31RbSUWvH2ZgphNdAxCW2pEuvTlnFGxN3OqEyupYcg4ZElZ5CG5U4b3UgeyT PxcOswLW/NKtiMDWqNZ2VP374Xp8qKGYiSzafokFGzdh/22kLLh0SRpgaSOoq6plW98l gCpLvFIrTzK70B0XOFT10yEgu75xTQT7rMLyRfrGU/4CTppevRZUusQlCAAoQZWuPmst 4rcKzNLlFbxCGGeGkwVNL14gxHkXvxsHrcOjp19vzGHkDaiCloSFiVXSC/nW4aTbymGP MZNw== X-Gm-Message-State: AC+VfDybuuFk/YVimIFA7iPjsk3n9u2jHUuS18RrR8AF3lyeHpFp/K0P qEVac8bSzBZcOnvl5UOfwAYiK2cjgATUkA== X-Google-Smtp-Source: ACHHUZ7oxTyGh7YUgkscT6cTAksdBxXH7llO8sg9GUbHXAQnl7ESWf4OuKejuB9DDqFvdZUb70VoVg== X-Received: by 2002:a17:90b:4a8c:b0:23d:a2a:3ae4 with SMTP id lp12-20020a17090b4a8c00b0023d0a2a3ae4mr3901952pjb.44.1683248831972; Thu, 04 May 2023 18:07:11 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 68/89] target/riscv: Introduce mmuidx_sum Date: Fri, 5 May 2023 11:02:20 +1000 Message-Id: <20230505010241.21812-69-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249468011100005 Content-Type: text/plain; charset="utf-8" From: Richard Henderson In get_physical_address, we should use the setting passed via mmu_idx rather than checking env->mstatus directly. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-13-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-13-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/internals.h | 5 +++++ target/riscv/cpu_helper.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 7b63c0f1b6..0b61f337dd 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -37,6 +37,11 @@ #define MMUIdx_M 3 #define MMU_2STAGE_BIT (1 << 2) =20 +static inline bool mmuidx_sum(int mmu_idx) +{ + return (mmu_idx & 3) =3D=3D MMUIdx_S_SUM; +} + /* share data between vector helpers and decode code */ FIELD(VDATA, VM, 0, 1) FIELD(VDATA, LMUL, 1, 3) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 291a1acbf7..29ee9b1b42 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -842,7 +842,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, widened =3D 2; } /* status.SUM will be ignored if execute on background */ - sum =3D get_field(env->mstatus, MSTATUS_SUM) || use_background || is_d= ebug; + sum =3D mmuidx_sum(mmu_idx) || use_background || is_debug; switch (vm) { case VM_1_10_SV32: levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249464; cv=none; d=zohomail.com; s=zohoarc; b=j6nxRO1yKJ2rcgkxCdEk59uFnC5SzbQUieI+KE6ab03nJgUKxavhD18YJR9zsy0iY9ni5Hn+mfbJDiglxZRgY3qZpu1CaWViZ6XXc27k1EuQ0LigXFtS+eZkFXtLjF8XvSj4plCsvLphBVmuLiL2MOiscRFHem7mKZGp4o86O8U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249464; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RGNIw9bc7Cyb4tZyzwGyzD9oYOSakGAm6uS/tG53Jdc=; b=nP8A+m6Yu+/YVFHd6leftFEFZXugBOsUNBWBIozPu7BQ4vQjLbmncY168hPbU+7Trx/FcaRK3uSggoJ4sXTqG1eZoB/pheSXlvQfSmC8U6JtiSF6w2gdz1wqkIq8vTrQcItFQITVREi1hPId7DKuULIlr4sUTcQnSlvMsJUALeI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16832494648511020.2331832428172; Thu, 4 May 2023 18:17:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujuw-0000IT-Si; Thu, 04 May 2023 21:07:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujup-0008WP-4E for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:21 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujun-0007yG-Di for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:18 -0400 Received: by mail-pg1-x535.google.com with SMTP id 41be03b00d2f7-51452556acdso731164a12.2 for ; Thu, 04 May 2023 18:07:17 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248835; x=1685840835; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RGNIw9bc7Cyb4tZyzwGyzD9oYOSakGAm6uS/tG53Jdc=; b=GXERoG+dZGhszy9tdsnXMJUOH7bukEQCekqeIhXQlwt21wogNNjqVhl/po20QC9X2w 7KQbwEHE7Vy1a/o/97ymvw8euX0bQuDmvLJWXkRYW3cbG8FTy570iM8LMUwU+SqE7GDJ VZlxlscwsPC7U7KYWlE/lSZFgJzSEWyRU8iiyvusxMi2sOPw8Ka/Z5sFK4oTqubCAQtZ 9J5nWZV2Cv0tUKWm/y4cHdrEJ8nQsozkQ4SJCS1dIFrQpd1SReTIWO2foGovOoHfU7/5 o+gH0zdNFOOyvwIAn3XtGTLE49v3a4ujDDhlqtIT2vRFJeCfhkk7OW/XdsAWafr7RTCQ Cyfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248835; x=1685840835; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RGNIw9bc7Cyb4tZyzwGyzD9oYOSakGAm6uS/tG53Jdc=; b=CoHGRedsOPf0fT3XNbqz8GLJXBzeZKMJAGp+C9hB6YfHA50F/Yo4cMoNtt7VEQifsl criHvIkroIxqD85YGQFNWrX6738bMK5WvUHeYDlWxVOHAwYuaPHncim7MLAwgzsM6qRV SsnE6XxB9HoW5irrdiKfUda+TVUyYxo7MyYsG+Y0mu0me6ZQRn0+FLtO8F+vDgmbKWHG hoVOuMIT5jsoNaQ1LIfKYGuofsvOZkuOF/7Tv9NcxvRULrubwDA0hCkk3U6y79JGsini CqDNn+C4HbDz1MD4lXTIb+8TtDEJHxiolYn0gzwzID8fhy2baKl+Xp2MibDgpxmNcgOv 7i+A== X-Gm-Message-State: AC+VfDyb27TBYj1xRdep9YzKIlxaE7mDTj7oBMhIkvF2gMUq399+4LWh OJhPC2lW9p56kNyXQC51p5jXzIP1moFUbg== X-Google-Smtp-Source: ACHHUZ7iyTAvqn6qf26bxjwYWw8EunvKxfCopx0/kDtBbd5gTXP5ypwFYSfsLXo9mKe5zCKGWKb/rg== X-Received: by 2002:a17:903:22c4:b0:19e:4bc3:b1ef with SMTP id y4-20020a17090322c400b0019e4bc3b1efmr6160564plg.64.1683248835607; Thu, 04 May 2023 18:07:15 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 69/89] target/riscv: Introduce mmuidx_priv Date: Fri, 5 May 2023 11:02:21 +1000 Message-Id: <20230505010241.21812-70-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=alistair23@gmail.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249466744100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use the priv level encoded into the mmu_idx, rather than starting from env->priv. We have already checked MPRV+MPP in riscv_cpu_mmu_index -- no need to repeat that. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-14-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-14-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/internals.h | 9 +++++++++ target/riscv/cpu_helper.c | 6 +----- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 0b61f337dd..4aa1cb409f 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -37,6 +37,15 @@ #define MMUIdx_M 3 #define MMU_2STAGE_BIT (1 << 2) =20 +static inline int mmuidx_priv(int mmu_idx) +{ + int ret =3D mmu_idx & 3; + if (ret =3D=3D MMUIdx_S_SUM) { + ret =3D PRV_S; + } + return ret; +} + static inline bool mmuidx_sum(int mmu_idx) { return (mmu_idx & 3) =3D=3D MMUIdx_S_SUM; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 29ee9b1b42..57bb19c76e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -758,7 +758,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, */ MemTxResult res; MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; - int mode =3D env->priv; + int mode =3D mmuidx_priv(mmu_idx); bool use_background =3D false; hwaddr ppn; int napot_bits =3D 0; @@ -781,10 +781,6 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, */ if (riscv_cpu_two_stage_lookup(mmu_idx)) { mode =3D get_field(env->hstatus, HSTATUS_SPVP); - } else if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { - if (get_field(env->mstatus, MSTATUS_MPRV)) { - mode =3D get_field(env->mstatus, MSTATUS_MPP); - } } =20 if (first_stage =3D=3D false) { --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249424; cv=none; d=zohomail.com; s=zohoarc; b=euFLlFRxxinsVC5p0uv5RXoI070C1ii7BeH1cpQZBOQHWHEKv4oHBuyGmpNLyydIWgDC4OoezGydVO3s0L2pXPbZfxEks3ec9YFtV+19SEOIHqUHDs03ULebh4ly+0xNOT5oEp5Isn6q5JVOfwyCJKf32CsI8EC09hL2wlyeeYQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249424; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Wi+1v00zCXgIbo5ZQUE7RzeAN6+AZmd0gp2h5NJhB9o=; b=EuRxd7jLbDQw4fmRQ7/E2cYupZouxTyHUhd9ltZcXIyImr+DcotiACKQBca/bewLCKp8wNF82AKxiIQcLt/XUHyzycgELuwtunclO9siFamkEdFHRAfyFs/2Hc86uY1xXuF9KFRFtNslI3GT0LOaAxRdapYQZZwsC1c3+5rjQhc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249424079516.3142898023783; Thu, 4 May 2023 18:17:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujvH-0000kl-Bk; Thu, 04 May 2023 21:07:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujus-000086-QE for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:22 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujuq-0007yv-S6 for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:22 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1aaff9c93a5so8151745ad.2 for ; Thu, 04 May 2023 18:07:20 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248839; x=1685840839; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Wi+1v00zCXgIbo5ZQUE7RzeAN6+AZmd0gp2h5NJhB9o=; b=Oeo5StD34xN8QRsGMRQCMS+5usi756D1yRQU/u11Tf+NjGCCQRbK7dcO3+kVKoLXSM ylTjGQjAS4VsgG5ntObAEjYMB2Kz8v9u4v/gt2S5KH+sTyTa+6qkmjHrCh+gI8EQHvdN p5Tfok9aWp+PSi7W5uMWvFRhcB/tTv08ZglacewbV9fxdst4BAJQFdsQ2AI8pa2iKjHE vm7zhl4VC5kbIxGeFy6BUB45M5dSR2ssww9YK27dRIrDq72HCuLNQRLqghw5duoQvIMZ 3LpqerrqK4nPM9W0tGEbmgFVa3+mkFIt5dFyLcJ61mDrTPt8E6tGHjBx0avAlZPTz1pU THNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248839; x=1685840839; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Wi+1v00zCXgIbo5ZQUE7RzeAN6+AZmd0gp2h5NJhB9o=; b=L4oCb0fLbwU4d+FQEi8KFZT6axRy3Srh2AKwWep5Wx5rc7m4Hgb1t2YnNksLZ+Vnb+ cAwLlxfMjnycsZNP1SzGUdHRMThBnxHajXMS1TBvylihnf/tMBMNhuBEqbs3k0aLKDDA 6JwqkCPwpSZ1bPXH2UA3+XnNnJLUbOrTyD4SPRHDdTF6qK/e9N1I6v7GYfCrBSQXg8KM Ihj5ruAywJLfxiyY1i2Eop8pEQRwmbGUhPH5ylY9qrCP/hnD2XAmR4f2ld1lVQYo24e3 SEqHXVAkV7g3BK71tp58beCyppX/SzrIGYINTbGSuWFGlGTYRJHMoJufLvdffRda6Sbd hC1w== X-Gm-Message-State: AC+VfDx9L0LwfTRNJvq74KKRg2G5zO0iZxY1PHExMnnW7PKZZndW9pP2 nWrV+3s3mm+AoZ5Ko9Y1Z8AB39oZhahlBg== X-Google-Smtp-Source: ACHHUZ7Mmd8k4NK+P6DFAVH+Si96Rk1jBw7I7a++zIoWbSko729dNY/utY3/TbCWQO94J6E94T4djA== X-Received: by 2002:a17:902:eccf:b0:1a6:f93a:a135 with SMTP id a15-20020a170902eccf00b001a6f93aa135mr6791826plh.61.1683248839389; Thu, 04 May 2023 18:07:19 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 70/89] target/riscv: Introduce mmuidx_2stage Date: Fri, 5 May 2023 11:02:22 +1000 Message-Id: <20230505010241.21812-71-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=alistair23@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249425312100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Move and rename riscv_cpu_two_stage_lookup, to match the other mmuidx_* functions. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-15-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-15-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/internals.h | 5 +++++ target/riscv/cpu_helper.c | 20 ++++++-------------- 3 files changed, 11 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 35cf2e2691..d1f888a790 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -581,7 +581,6 @@ target_ulong riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); -bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 4aa1cb409f..b5f823c7ec 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -51,6 +51,11 @@ static inline bool mmuidx_sum(int mmu_idx) return (mmu_idx & 3) =3D=3D MMUIdx_S_SUM; } =20 +static inline bool mmuidx_2stage(int mmu_idx) +{ + return mmu_idx & MMU_2STAGE_BIT; +} + /* share data between vector helpers and decode code */ FIELD(VDATA, VM, 0, 1) FIELD(VDATA, LMUL, 1, 3) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 57bb19c76e..9dfd1d739b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -591,11 +591,6 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bo= ol enable) } } =20 -bool riscv_cpu_two_stage_lookup(int mmu_idx) -{ - return mmu_idx & MMU_2STAGE_BIT; -} - int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) { CPURISCVState *env =3D &cpu->env; @@ -779,7 +774,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, * MPRV does not affect the virtual-machine load/store * instructions, HLV, HLVX, and HSV. */ - if (riscv_cpu_two_stage_lookup(mmu_idx)) { + if (mmuidx_2stage(mmu_idx)) { mode =3D get_field(env->hstatus, HSTATUS_SPVP); } =20 @@ -1175,8 +1170,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hw= addr physaddr, } =20 env->badaddr =3D addr; - env->two_stage_lookup =3D env->virt_enabled || - riscv_cpu_two_stage_lookup(mmu_idx); + env->two_stage_lookup =3D env->virt_enabled || mmuidx_2stage(mmu_idx); env->two_stage_indirect_lookup =3D false; cpu_loop_exit_restore(cs, retaddr); } @@ -1201,8 +1195,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, g_assert_not_reached(); } env->badaddr =3D addr; - env->two_stage_lookup =3D env->virt_enabled || - riscv_cpu_two_stage_lookup(mmu_idx); + env->two_stage_lookup =3D env->virt_enabled || mmuidx_2stage(mmu_idx); env->two_stage_indirect_lookup =3D false; cpu_loop_exit_restore(cs, retaddr); } @@ -1256,7 +1249,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, * MPRV does not affect the virtual-machine load/store * instructions, HLV, HLVX, and HSV. */ - if (riscv_cpu_two_stage_lookup(mmu_idx)) { + if (mmuidx_2stage(mmu_idx)) { mode =3D get_field(env->hstatus, HSTATUS_SPVP); } else if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH && get_field(env->mstatus, MSTATUS_MPRV)) { @@ -1268,7 +1261,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, =20 pmu_tlb_fill_incr_ctr(cpu, access_type); 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248843; x=1685840843; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0lZiXeB7ApdXEaksXsIhLSnMPRCJzB+5QIy3AM8RHG4=; b=TB8kMYmxMqnXINYyfwqLCwl+2DfOjA++zXtWZajsPhL68XhqOb7gmms3zwn4Ln2gCu 8/rYZzHoE3NXHesVG7P8Nt8l7iZ30ynKKUN5+knS4EtAE2V0S+wcFeCzZmHv6u+jqEZU RVJd5q1Eg8ZOzGdWZFkQCVrky3pjBFGt9/N3SzbguDI+1T8f3ysWkxmD7X07bVwrWfSP JZW8XxD2SbbesGlP0eSLtuCTAYaU7nxb2lw9nJ8u/U6SfsGuo2eAxhCJT3gkiqn3hnYZ ozRy/4+YjvsitA+8in84Xr8f/hZ3PEvnBrGPZcj1OCqdT2VIik35p5LHdmLJeqSRPhmx XF+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248843; x=1685840843; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0lZiXeB7ApdXEaksXsIhLSnMPRCJzB+5QIy3AM8RHG4=; b=J8AO0uf9Lr16RA+Lo84uqRPnrHUtlu9xzA1OIzFtUGU5EO7QHd2FWyClAqRV32nOfu LnqpaUCW2E1H6Mpci7j+EsuvdrcsHqCxLjIvRE2YR+1tM+yZ6ur1n4JrLH6KC1z653uN 8tPS1hT4GE82nI1JfltUkXEKg4ZjjYYkPg81SgYhD96lotaeUvpf9dDKlFUC325eLyhF K0KNtdU8sFCBZw17CcTCv9dHF9y+kQjKqBMV39GYPP+D7lS/CVuvagfpMpIOPQup4vIS hD9Bj07tBMD6KcFqUz2CWtJ9TjbdxAIaxa5HftIZMKs1IfeYW7iYmlizz2TObIdu4LaQ 8/cw== X-Gm-Message-State: AC+VfDw3UC7GvuEnFR3K16Sam0fgCju9cefanqKcGv5/PRXMCcPk5b48 ZRk7J22EoOjTu30tMzWO76muDlW3N4TTKA== X-Google-Smtp-Source: ACHHUZ4ef8lGXaeydsn1VanF9sZ8k4FECP9AmSB6+1iuTeiidYsPhmdHwOgB4l/clX8/ondyNPpIxA== X-Received: by 2002:a17:903:2443:b0:1ab:197c:b510 with SMTP id l3-20020a170903244300b001ab197cb510mr6078789pls.31.1683248842940; Thu, 04 May 2023 18:07:22 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 71/89] target/riscv: Move hstatus.spvp check to check_access_hlsv Date: Fri, 5 May 2023 11:02:23 +1000 Message-Id: <20230505010241.21812-72-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=alistair23@gmail.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249415279100005 Content-Type: text/plain; charset="utf-8" From: Richard Henderson The current cpu_mmu_index value is really irrelevant to the HLV/HSV lookup. Provide the correct priv level directly. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-16-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-16-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 10 +--------- target/riscv/op_helper.c | 2 +- 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9dfd1d739b..ccba3c45e7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -770,14 +770,6 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, use_background =3D true; } =20 - /* - * MPRV does not affect the virtual-machine load/store - * instructions, HLV, HLVX, and HSV. - */ - if (mmuidx_2stage(mmu_idx)) { - mode =3D get_field(env->hstatus, HSTATUS_SPVP); - } - if (first_stage =3D=3D false) { /* * We are in stage 2 translation, this is similar to stage 1. @@ -1250,7 +1242,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, * instructions, HLV, HLVX, and HSV. */ if (mmuidx_2stage(mmu_idx)) { - mode =3D get_field(env->hstatus, HSTATUS_SPVP); + ; } else if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH && get_field(env->mstatus, MSTATUS_MPRV)) { mode =3D get_field(env->mstatus, MSTATUS_MPP); diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 6122f5fbe5..f83f7b5347 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -437,7 +437,7 @@ static int check_access_hlsv(CPURISCVState *env, bool x= , uintptr_t ra) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } =20 - return cpu_mmu_index(env, x) | MMU_2STAGE_BIT; + return get_field(env->hstatus, HSTATUS_SPVP) | MMU_2STAGE_BIT; } =20 target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr) --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249577; cv=none; d=zohomail.com; s=zohoarc; b=Xxy21P00tW9i6KejfVfUumODf1M4sfmjfFLe7yezoO9k2MZ51pY2spQu5dvXo4W69fRL5lfQN9ug9JdpbGPRhj3/h3sLaOj+JJrpalxhEg5UHatCt1+gQjAuxNIRPseOxnvlzojDGOBwpEA52TjIGyjej4wpsRjrocsgYc0he6Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249577; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aFHu1wXGTKi/8OHzVpdxexLxvjVZdWMnanU8CAAQbkg=; b=R/shKpafFaVdmmKVcqD1HkFx3np8bU7n0wmO3majNbqAWB2sV9U40S+QepUgB0houRb6dKGKEUDFzML73NZ9e8u7DW/F6R/51swLXz1FXhdymU+0mdW6qAil13GoGE4fC3MmGUhMiVc/3WbJeXwhufkZ+VRrBemCMgqzqDKK+kc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249577917294.21544578765213; Thu, 4 May 2023 18:19:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujvJ-0000qQ-W9; Thu, 04 May 2023 21:07:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujv0-0000Xo-LS for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:39 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujux-00081X-VB for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:29 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1aad5245571so8039865ad.1 for ; Thu, 04 May 2023 18:07:27 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248846; x=1685840846; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aFHu1wXGTKi/8OHzVpdxexLxvjVZdWMnanU8CAAQbkg=; b=agYuLICf039HPmnNCrJvxh3em8Z20NTbqQE4vcxBVYWbOVE05pl7ae4QesHFJK/xLT wqzie4J/ucdqExX33x8aQBxET7hlF2ILMcYSAi02WEhu/ZzfGexqeDyNyerhRpUPaJ1C I5/rIrKXMkUayh90RUy8n7p1gkcX/TI7fAPBMdfqUKZvQze0mdXDAcnithOBPMs6YNfm 6v9t5qrQIwxK6yibL1Bc+fyg+lI8SKzyHHZXllYSyFrak7G67o3BxwGnPpuW1Z2fibDA fioXfCeAkvT10VKFYrI2NNcWLYR+F5Z+ffphHm8lT+Va2vZlnzS3UW6MLoo2A5lcKYDl FYcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248846; x=1685840846; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aFHu1wXGTKi/8OHzVpdxexLxvjVZdWMnanU8CAAQbkg=; b=l1MAXEuNI0sLcK76jSOxMNky5LdjwE64M93db+SmYI+zITg04SYBmOPkyLqBlxqyVg Cz3VagLEIG7gxn3MOn9GSOJ2zgoe5Hs3bsITJP/siZq9y+LeG9EPFt3nXICo+zaaETxJ 7Ga2UTrdcbkvhY7XvEsM9NsU10TY5TlYcDcpoSu6VSQiBx6CaOhtMYkVNEltw100azcY 7CvnZ3AARIVA0pxk/nKWelut1WwQxK1A5wq/00NrqX3Dk4wlJ8zy4sabHnzqmIJaB/Sd n/7zVPLDq+oe3Lfv4CpdI8hQrfMxK5t+AgWY7KFaJT5Ti49fRsyd84Oyal7CmPcjKzSx 4u1A== X-Gm-Message-State: AC+VfDx6EXs18x0Ck+dcZwfF3cjC0rd+wwz+JRJm6MmP+02kkP3zIOt1 lQLBKrylS+qRt0bW0DzseDKM4aOnIeZviw== X-Google-Smtp-Source: ACHHUZ4NYVQKYQ1i3ZkbqHp9u24K3pBLVHEybnSfh6EOj184GzvJNujCUj+vDkm2FAzLu5hd2hGEzg== X-Received: by 2002:a17:903:32c4:b0:1ac:3605:97ec with SMTP id i4-20020a17090332c400b001ac360597ecmr3436280plr.62.1683248846468; Thu, 04 May 2023 18:07:26 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 72/89] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index Date: Fri, 5 May 2023 11:02:24 +1000 Message-Id: <20230505010241.21812-73-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=alistair23@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249578432100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Incorporate the virt_enabled and MPV checks into the cpu_mmu_index function, so we don't have to keep doing it within tlb_fill and subroutines. This also elides a flush on changes to MPV. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-17-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-17-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 49 ++++++++++++++------------------------- target/riscv/csr.c | 6 +---- 2 files changed, 18 insertions(+), 37 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index ccba3c45e7..baa4b3a1d2 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -37,19 +37,21 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #ifdef CONFIG_USER_ONLY return 0; #else - if (ifetch) { - return env->priv; - } + bool virt =3D env->virt_enabled; + int mode =3D env->priv; =20 /* All priv -> mmu_idx mapping are here */ - int mode =3D env->priv; - if (mode =3D=3D PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { - mode =3D get_field(env->mstatus, MSTATUS_MPP); - } - if (mode =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_SUM)) { - return MMUIdx_S_SUM; + if (!ifetch) { + if (mode =3D=3D PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { + mode =3D get_field(env->mstatus, MSTATUS_MPP); + virt =3D get_field(env->mstatus, MSTATUS_MPV); + } + if (mode =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_SUM)) { + mode =3D MMUIdx_S_SUM; + } } - return mode; + + return mode | (virt ? MMU_2STAGE_BIT : 0); #endif } =20 @@ -1162,7 +1164,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hw= addr physaddr, } =20 env->badaddr =3D addr; - env->two_stage_lookup =3D env->virt_enabled || mmuidx_2stage(mmu_idx); + env->two_stage_lookup =3D mmuidx_2stage(mmu_idx); env->two_stage_indirect_lookup =3D false; cpu_loop_exit_restore(cs, retaddr); } @@ -1187,7 +1189,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, g_assert_not_reached(); } env->badaddr =3D addr; - env->two_stage_lookup =3D env->virt_enabled || mmuidx_2stage(mmu_idx); + env->two_stage_lookup =3D mmuidx_2stage(mmu_idx); env->two_stage_indirect_lookup =3D false; cpu_loop_exit_restore(cs, retaddr); } @@ -1225,7 +1227,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, int prot, prot2, prot_pmp; bool pmp_violation =3D false; bool first_stage_error =3D true; - bool two_stage_lookup =3D false; + bool two_stage_lookup =3D mmuidx_2stage(mmu_idx); bool two_stage_indirect_error =3D false; int ret =3D TRANSLATE_FAIL; int mode =3D mmu_idx; @@ -1237,24 +1239,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,= int size, qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); =20 - /* - * MPRV does not affect the virtual-machine load/store - * instructions, HLV, HLVX, and HSV. - */ - if (mmuidx_2stage(mmu_idx)) { - ; - } else if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH && - get_field(env->mstatus, MSTATUS_MPRV)) { - mode =3D get_field(env->mstatus, MSTATUS_MPP); - if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV= )) { - two_stage_lookup =3D true; - } - } - pmu_tlb_fill_incr_ctr(cpu, access_type); - if (env->virt_enabled || - ((mmuidx_2stage(mmu_idx) || two_stage_lookup) && - access_type !=3D MMU_INST_FETCH)) { + if (two_stage_lookup) { /* Two stage lookup */ ret =3D get_physical_address(env, &pa, &prot, address, &env->guest_phys_fault_addr, access_typ= e, @@ -1350,8 +1336,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, return false; } else { raise_mmu_exception(env, address, access_type, pmp_violation, - first_stage_error, - env->virt_enabled || mmuidx_2stage(mmu_idx), + first_stage_error, two_stage_lookup, two_stage_indirect_error); cpu_loop_exit_restore(cs, retaddr); } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4a4d852bd1..865ee9efda 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1294,7 +1294,7 @@ static RISCVException write_mstatus(CPURISCVState *en= v, int csrno, val =3D legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val); =20 /* flush tlb on mstatus fields that affect VM */ - if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPV)) { + if ((val ^ mstatus) & MSTATUS_MXR) { tlb_flush(env_cpu(env)); } mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | @@ -1342,10 +1342,6 @@ static RISCVException write_mstatush(CPURISCVState *= env, int csrno, uint64_t valh =3D (uint64_t)val << 32; uint64_t mask =3D MSTATUS_MPV | MSTATUS_GVA; =20 - if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { - tlb_flush(env_cpu(env)); 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248850; x=1685840850; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aS4kDtm5851BGcVcD1xdvmRa2zrcDeJrdu60JMY+Uks=; b=Bx905cAHBdM4SkO/YcOa5C4C5nWsLom8NxWh98R+GJcm/vHUEe38gq9jwdCtgk36oB C2rqsl8W/RFcsY1NCu8JMcWOomadxG4IMZdmTMUtL2BXAHQT9WcCxqBxtKXaHUXvnNjX f82fXhuzyuLhkBUuGTWDULBwMkI5uzvrrufHDKysBKbDwnNXzI1CxBribJk1ZE4QItBK cdWUMuiRL5NmUztdU7736T+C6NXohLJDDXNJnyz0lpUJYjhfGL6nPEkECv9t7zAr7Vly QKFZTQ8g2fMRG4VZda9mvU6aLxI0KWxXkzOdNWyxuHxuNOoGYa5mS0izcnGoxHrJUs5R eedQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248850; x=1685840850; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aS4kDtm5851BGcVcD1xdvmRa2zrcDeJrdu60JMY+Uks=; b=l1UCCy4GcvZuQqwxnTbMmikTzMbRScuNRQjsU5+3HKmiOqvAfdgejp3MT/uwROyb3b UhMl3RdgCW8s3m7VQqPLHXAQtvpbSMAqcisTrGWebMMjgyItZKjGGv4p+MQU0FT63p1P 4vZEf2Rmft9a5GFBpjM4B8lRKg7ZuDTuxCRRkvc4nZ6PsY8pF7AOftzHxDE0jBnltiBt t8XaprRM4zTNMse8/k7bZt+Q/dISflaTUYKV92LMgusrWpuVcVw7eg6EGR7/+A5Zns7W LqdYLoEzuf4YF1OheGk51bz8ewIaJxU0fGbItHnRz9db3WCCelQKAiEQqEmyXG325z3I DnyQ== X-Gm-Message-State: AC+VfDyI/uxh7HXhSqOGGd6ZfNs/WW3utTeLVM98XqGh1+jgERyw8Fl2 UqoeirAcpUCAG6qajyEQUJ2hCMQD9ZUgYA== X-Google-Smtp-Source: ACHHUZ4fbRsBECYhRVZib5KbvNO9cg69+zjMLIO1rGUAGw/AKx58QBiMlSW11dpDvT9F1J4kfPztjA== X-Received: by 2002:a17:903:11c6:b0:1ab:16e0:ef5e with SMTP id q6-20020a17090311c600b001ab16e0ef5emr6379214plh.4.1683248850033; Thu, 04 May 2023 18:07:30 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 73/89] target/riscv: Check SUM in the correct register Date: Fri, 5 May 2023 11:02:25 +1000 Message-Id: <20230505010241.21812-74-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=alistair23@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249586325100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Table 9.5 "Effect of MPRV..." specifies that MPV=3D1 uses VS-level vsstatus.SUM instead of HS-level sstatus.SUM. For HLV/HSV instructions, the HS-level register does not apply, but the VS-level register presumably does, though this is not mentioned explicitly in the manual. However, it matches the behavior for MPV. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-18-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-18-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 12 ++++++++---- target/riscv/op_helper.c | 6 +++++- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index baa4b3a1d2..38bd83f66d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -42,11 +42,16 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) =20 /* All priv -> mmu_idx mapping are here */ if (!ifetch) { - if (mode =3D=3D PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { + uint64_t status =3D env->mstatus; + + if (mode =3D=3D PRV_M && get_field(status, MSTATUS_MPRV)) { mode =3D get_field(env->mstatus, MSTATUS_MPP); virt =3D get_field(env->mstatus, MSTATUS_MPV); + if (virt) { + status =3D env->vsstatus; + } } - if (mode =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_SUM)) { + if (mode =3D=3D PRV_S && get_field(status, MSTATUS_SUM)) { mode =3D MMUIdx_S_SUM; } } @@ -826,8 +831,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, } widened =3D 2; } - /* status.SUM will be ignored if execute on background */ - sum =3D mmuidx_sum(mmu_idx) || use_background || is_debug; + sum =3D mmuidx_sum(mmu_idx) || is_debug; switch (vm) { case VM_1_10_SV32: levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index f83f7b5347..f563dc3981 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -437,7 +437,11 @@ static int check_access_hlsv(CPURISCVState *env, bool = x, uintptr_t ra) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } =20 - return get_field(env->hstatus, HSTATUS_SPVP) | MMU_2STAGE_BIT; + int mode =3D get_field(env->hstatus, HSTATUS_SPVP); + if (!x && mode =3D=3D PRV_S && get_field(env->vsstatus, MSTATUS_SUM)) { + mode =3D MMUIdx_S_SUM; + } + return mode | MMU_2STAGE_BIT; } =20 target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr) --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249412; cv=none; d=zohomail.com; s=zohoarc; b=Wx6la/jvx7gmQowfNPjMNPiR6+qgYyhkrjferJsqOMuuUq8aiNXsakq9NRqpfVr8t8RAxJYX71Yaw9wZIxxTwFjipK4VsK7glbPvR0kUQd2Wxg0zsNTJU2Tp5h1wzdRtxHA0W1+Vu9r3ypNDfP4DHJmQ5l0+C85JN5UWnX7fN+g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249412; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rNZtPPrKtoAPNdvExZgKDefGNHGLbWUnU+i+ILhcCsA=; b=chJKFsYP00v6Oa0XG+Zwl6JDl1NG9PJtPgU0wIu5arOljlvxUhRggZpfxvCKMOQN/4U2F/a3bI4I67dkanRTO0NWPuaxS/AyQQTdfG4485bTr+r5dzhCgqP45V84iSsUFrH+MEE/9oAk/9f+krOJr25dhsvWgGxz0SQolDUnDcQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249412097581.8650439159793; Thu, 4 May 2023 18:16:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujvI-0000m1-Au; Thu, 04 May 2023 21:07:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujv9-0000gC-SZ for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:45 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujv5-000839-SP for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:38 -0400 Received: by mail-pg1-x530.google.com with SMTP id 41be03b00d2f7-51fcf5d1e44so1000925a12.3 for ; Thu, 04 May 2023 18:07:34 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248854; x=1685840854; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rNZtPPrKtoAPNdvExZgKDefGNHGLbWUnU+i+ILhcCsA=; b=OpMiUtBRVNBwb394ujoELGOmkuZOjVrE9t5NOB6jiFhD/GSX9CJ0mG46iqg3dxnNYx N+IpK+LrPPKMEkjBbeEZnd+e1Zlw52H5s12a0dZcLbjAs0vpm+28hTtssf85X4IKB0Mm cKM8I4jlaJrYh0jfRxzSwCV8Yg74SPcDIMewyB9XTY800lTZ+1Rz17zchiRiK1Yp6YVE 03gyOAMDTsDzdHj+Lp7dc3owA3TE3yz24mVVntjdjb/K45U3h4pkoUEUImJ6pDg3arrS Kt38CSqqlSHpBax6ygZaDKIj05CPdefVKkawJ/O0iBmjXmkayWb+Wu2ySSolLi7bAl6O Qg4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248854; x=1685840854; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rNZtPPrKtoAPNdvExZgKDefGNHGLbWUnU+i+ILhcCsA=; b=crYamuyjmr04I5tSqkzDpp7LhndcRqjKQuyxCXdPm+l6UQJAcpWpZhDB2sqw4zHChw SR1bH5fpp0G7VTZiWdtJt0nJXUqGPi31+0Lf8AKVJreFfLfIIO1tBc8U4MDv/aE16n6X rFXMcPj+MRlzeL8yYrjvH8BsnLK771wXoOwUDqcyIQ9bO6IJIeeleZPi2Cdh14yX1D2Z gKwnlysMxcd4pYHXS5l9TuGWj9bsrSwR0HtcpfxA1Qp2SatG1sDJyQtbxfDQaKl4Z5ml pxCZeB1r1l5gc3u/HTTwLDyRT4LF7DGdli511gRmPzTxJKxAEbnKlM3Y/V8P/YjMEf3U wCvQ== X-Gm-Message-State: AC+VfDyaAQFYeXDFE5Xq4MxeTmQWVhxusxchoG0XrhI56GHcQ3zJZSJt w3MGDcnFs3D4Ckxx1tdVGujJZfrHllC9wg== X-Google-Smtp-Source: ACHHUZ7LamyBx3HlxEKu4ycJUZICcSEYbNKb0yOfuDpODHvFoDOoyMnYmHI/Gr/vnPyoD3ucJ9Y0wg== X-Received: by 2002:a17:903:2352:b0:1ab:109e:a553 with SMTP id c18-20020a170903235200b001ab109ea553mr6741687plh.62.1683248853667; Thu, 04 May 2023 18:07:33 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 74/89] target/riscv: Hoist second stage mode change to callers Date: Fri, 5 May 2023 11:02:26 +1000 Message-Id: <20230505010241.21812-75-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=alistair23@gmail.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249413676100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Move the check from the top of get_physical_address to the two callers, where passing mmu_idx makes no sense. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-19-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-19-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 38bd83f66d..5753e4e612 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -777,14 +777,6 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, use_background =3D true; } =20 - if (first_stage =3D=3D false) { - /* - * We are in stage 2 translation, this is similar to stage 1. - * Stage 2 is always taken as U-mode - */ - mode =3D PRV_U; - } - if (mode =3D=3D PRV_M || !riscv_cpu_cfg(env)->mmu) { *physical =3D addr; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -890,7 +882,7 @@ restart: /* Do the second stage translation on the base PTE address. */ int vbase_ret =3D get_physical_address(env, &vbase, &vbase_pro= t, base, NULL, MMU_DATA_LOAD, - mmu_idx, false, true, + MMUIdx_U, false, true, is_debug); =20 if (vbase_ret !=3D TRANSLATE_SUCCESS) { @@ -1271,7 +1263,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, im_address =3D pa; =20 ret =3D get_physical_address(env, &pa, &prot2, im_address, NUL= L, - access_type, mmu_idx, false, true, + access_type, MMUIdx_U, false, true, false); =20 qemu_log_mask(CPU_LOG_MMU, --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249321; cv=none; d=zohomail.com; s=zohoarc; b=BONESi7JUNZxDuccHkF22PpAxyeiHV5DIPWwoixM2HDo9TNLvZJr6Q32UXO048Tcs12oj7djcLyv/mQmQHuOT5Cualx8cUQfql6ahi8e+UD1dsDm9qvKtjcOcfNnCmhHZBmUvztt3dVQfySS/UbeMG3xzuVBu+9kM91Ndtj/3S4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249321; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kQOvu3VF8tFauxUlZuL69IHK6L45Rg+xcZox/q0Oz7g=; b=KkLHJRxNvtyFPQ3tN+56AeQCAYL1cc9HV5x7Q+Q3GCHt8zCVbsn6Qy5tB0LY3tI7Y7uFhSskkr8nPubmZWZr62ktksDUFyM66K39BZPRsdntQu/FJ1CDA++ByBJVYua+crEjDxDgN1gY0W+0RXjF7CgkmOxZP7fhOQnGMDUELmM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249321248345.84853617330987; Thu, 4 May 2023 18:15:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujvK-0000s8-Ty; Thu, 04 May 2023 21:07:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujvF-0000gv-Nw for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:45 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujv9-00083m-L6 for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:40 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1aaea43def7so7996285ad.2 for ; Thu, 04 May 2023 18:07:38 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248857; x=1685840857; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kQOvu3VF8tFauxUlZuL69IHK6L45Rg+xcZox/q0Oz7g=; b=AMUerAx9ObDkmsrQRElHEFamW4cbLnfdZNeC2FeFsTZ9cQ0XL2QI3Gm53MmeVZrlM1 GsPQ5fUAzjN7wSbKTPvvuGzEyhWRGwd4eDvaf71EgmVhKm9R5+AjjfNcAfIrDLjpcjCV bZ1h8BKOwPUaitF/QDZv5p+5Y2ywTXEFZ3AsxKVSY9/0zUKKn5i9dgTrbM1J5P9a+iZr RLwRV+xfwuvVSB5tamSAy6UPt48uZTe/zRK2VBrJBfE1yAQd4NsVTB2mJ169AxrAiDDn QmjIuB8uWihOwbxV1sIRx4mYSSlYVSpuG3pMIf4FRrC+0l4edG4KutDx7leQOur1wypb DSfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248857; x=1685840857; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kQOvu3VF8tFauxUlZuL69IHK6L45Rg+xcZox/q0Oz7g=; b=hgFVa7emtJYEOJGOvYCzzhh0SfmeeYL+KxlNuK0eQOoEjUwuPJG8JZaNZPOAd9FosN D3glhl5mMUQiifEhrcnAe0nlSeaqYPkxQDtjYWW++kM+jdmVta0Gee7gbiidlOsPti0d nMeAtEu5ORp9PQG5BMnPI7WaHBCeYOt+UGFz1TG+JM6ZYQbfz7+uvSHwl8g7+5O6fHik dMIURBLfjTs3MXZsJF9RD0kWrVa26elriEC/B0lD9+Hl3hmzX+NlFMj8MtLJfIWF6jg/ 4J2d3MTVP1V5hQ3aM8m0jl/tmReGEsWkHe2us9JSpvVoNFbDJq/wCJHr/T0er7zJ1NUD llSw== X-Gm-Message-State: AC+VfDyVJ9SKKJ0iox22od+9EzQtIevOFO80azDAbvXTMat5pZqJ7gPR 1+HKEeScyYd4XDgsJUtP9bPmbKo/qNtZoQ== X-Google-Smtp-Source: ACHHUZ54fLbMHgbw0G8ehBTppnl5V/wE5p+9WeyKmH3nwmUg/omRfJMs/fp/8raKAcNmMdJOl0rUig== X-Received: by 2002:a17:902:bd86:b0:1ab:ef3:73e5 with SMTP id q6-20020a170902bd8600b001ab0ef373e5mr5279724pls.61.1683248857262; Thu, 04 May 2023 18:07:37 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 75/89] target/riscv: Hoist pbmte and hade out of the level loop Date: Fri, 5 May 2023 11:02:27 +1000 Message-Id: <20230505010241.21812-76-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249322261100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson These values are constant for every level of pte lookup. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-20-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-20-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 5753e4e612..7c9f89d4d3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -856,6 +856,14 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, return TRANSLATE_FAIL; } =20 + bool pbmte =3D env->menvcfg & MENVCFG_PBMTE; + bool hade =3D env->menvcfg & MENVCFG_HADE; + + if (first_stage && two_stage && env->virt_enabled) { + pbmte =3D pbmte && (env->henvcfg & HENVCFG_PBMTE); + hade =3D hade && (env->henvcfg & HENVCFG_HADE); + } + int ptshift =3D (levels - 1) * ptidxbits; int i; =20 @@ -916,14 +924,6 @@ restart: return TRANSLATE_FAIL; } =20 - bool pbmte =3D env->menvcfg & MENVCFG_PBMTE; - bool hade =3D env->menvcfg & MENVCFG_HADE; - - if (first_stage && two_stage && env->virt_enabled) { - pbmte =3D pbmte && (env->henvcfg & HENVCFG_PBMTE); - hade =3D hade && (env->henvcfg & HENVCFG_HADE); - } - if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { ppn =3D pte >> PTE_PPN_SHIFT; } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) { --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249475; cv=none; d=zohomail.com; s=zohoarc; b=JINxUSbMezceNhIPvED+x74jOLFcWHRNaKr/Fpm6Y+YDxi79YCKPfcUP8N7A9ZoZktEwWuyVTnsfleeSx5rvNPsObMJUtGDERYUPU/dA+pw4BH6nEtMGuOr6yuvfNniZ1IHG2/nJsKZC+kj2LaV1GMOe2Lpvswfyz6py1BSTAwE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249475; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1HdwrRbA/OYW6yPcUFcCFbJJAD4gHx1WdvFufjwwivA=; b=PcaWiGDFXiXzsTOzlVEjHjThyq9wobBBeNbHssz+x87QzYXlnCngv1Qra8Cbwwoyp3yA/wDEXOUbwqWbGNk0KWcLJwpFJviK4+tyc87mXPzZLD1aIWQ3UsTMNCat1RyIZqfqwUlLzCpb5Cw2VYU5a5V92KP+vcuZXPAPgKGIx4s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249475925623.0006606790447; Thu, 4 May 2023 18:17:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujvW-00014Y-Ir; Thu, 04 May 2023 21:08:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujvH-0000lc-Nm for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:47 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujvF-00084Z-GF for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:47 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1a50cb65c92so8246185ad.0 for ; Thu, 04 May 2023 18:07:43 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248861; x=1685840861; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1HdwrRbA/OYW6yPcUFcCFbJJAD4gHx1WdvFufjwwivA=; b=Wre2+t5GBaahKwGwCj/Gu6TDOUzoECSP+gNICI3hHmNaLLh2cQH+I1pVZ3LItmFXH6 lhImJspHEoz0tmz46+W/IKFixqb349CFD0GPRRYVopoC9TQrW7PGhwtWMAvDLpKptswC PHHx+x8qwmebU+OI0+qekAj0GRqYjo1imKV2fgZBy082B444ilSlwFh3R/fqS0W7FrU6 6ICKYWSgLE3FjOn/sixdwdt/t00k1c3oo82x8GHtz+NFQvMOqX0PSFqztlz6esHP9YFB vusVqlV4kD8DLgEO/2mvSx4/o2rhi+Aoam0bdm/lDeeF0Cmv7x7b7IMT2fKWn7VJEsku hS3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248861; x=1685840861; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1HdwrRbA/OYW6yPcUFcCFbJJAD4gHx1WdvFufjwwivA=; b=FxLLKKHwD5C2MjqescF7Y/XA4Iw/4wfZCa/NIZapng/6VFziotTbtK1wIwqizJeiiC KPjls1QI8pcxjRf6upP/Mz3UJ9BfUerBJoTGa/WhyL/3kFIHC0/Z60XfzOlKXG5F0xAn 7GXfbMu1xVGJfRV8FxEONnx85sQFjn4ZGCdxqgTyaVEALzbn5QAGIIhhlqbqXSHqj55Q XbiPKIf/kQXqWF++cRnLUT0TFWeY1O0hHeXOURX9n5QRX5UE0+EoDf11cS01/Afau4Kk gIdA7Z+mNVl4xxuuyZ62O0D8knCiCV9a5qYbHxJaDpVKMDl5AR/H917/jzISZo/6gF2w sc+Q== X-Gm-Message-State: AC+VfDz/J72PmioquPF5Aq2at8SnhoyJodcF04VVRz3cVvI2gEWhjye6 WrKApQcgl/B+z68S3QAhs4pTFXU+asz8YQ== X-Google-Smtp-Source: ACHHUZ6qhXwY235+b6iqAUA3f0SVV6GtXaLP8bIr7/yIRaNY23WtPwpd+cEevKLS65Uu0EOa9/P4yQ== X-Received: by 2002:a17:902:a716:b0:1a9:80a0:47fc with SMTP id w22-20020a170902a71600b001a980a047fcmr4868075plq.17.1683248860752; Thu, 04 May 2023 18:07:40 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 76/89] target/riscv: Move leaf pte processing out of level loop Date: Fri, 5 May 2023 11:02:28 +1000 Message-Id: <20230505010241.21812-77-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249477881100009 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Move the code that never loops outside of the loop. Unchain the if-return-else statements. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-21-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-21-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 234 ++++++++++++++++++++------------------ 1 file changed, 123 insertions(+), 111 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 7c9f89d4d3..c2d083f029 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -865,6 +865,8 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, } =20 int ptshift =3D (levels - 1) * ptidxbits; + target_ulong pte; + hwaddr pte_addr; int i; =20 #if !TCG_OVERSIZED_GUEST @@ -881,7 +883,6 @@ restart: } =20 /* check that physical address of PTE is legal */ - hwaddr pte_addr; =20 if (two_stage && first_stage) { int vbase_prot; @@ -913,7 +914,6 @@ restart: return TRANSLATE_PMP_FAIL; } =20 - target_ulong pte; if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { pte =3D address_space_ldl(cs->as, pte_addr, attrs, &res); } else { @@ -938,128 +938,140 @@ restart: if (!(pte & PTE_V)) { /* Invalid PTE */ return TRANSLATE_FAIL; - } else if (!pbmte && (pte & PTE_PBMT)) { - return TRANSLATE_FAIL; - } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { - /* Inner PTE, continue walking */ - if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { - return TRANSLATE_FAIL; - } - base =3D ppn << PGSHIFT; - } else if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D PTE_W) { - /* Reserved leaf PTE flags: PTE_W */ - return TRANSLATE_FAIL; - } else if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D (PTE_W | PTE_X))= { - /* Reserved leaf PTE flags: PTE_W + PTE_X */ - return TRANSLATE_FAIL; - } else if ((pte & PTE_U) && ((mode !=3D PRV_U) && - (!sum || access_type =3D=3D MMU_INST_FETCH))) { - /* User PTE flags when not U mode and mstatus.SUM is not set, - or the access type is an instruction fetch */ - return TRANSLATE_FAIL; - } else if (!(pte & PTE_U) && (mode !=3D PRV_S)) { - /* Supervisor PTE flags when not S mode */ - return TRANSLATE_FAIL; - } else if (ppn & ((1ULL << ptshift) - 1)) { - /* Misaligned PPN */ - return TRANSLATE_FAIL; - } else if (access_type =3D=3D MMU_DATA_LOAD && !((pte & PTE_R) || - ((pte & PTE_X) && mxr))) { - /* Read access check failed */ - return TRANSLATE_FAIL; - } else if (access_type =3D=3D MMU_DATA_STORE && !(pte & PTE_W)) { - /* Write access check failed */ - return TRANSLATE_FAIL; - } else if (access_type =3D=3D MMU_INST_FETCH && !(pte & PTE_X)) { - /* Fetch access check failed */ + } + if (pte & (PTE_R | PTE_W | PTE_X)) { + goto leaf; + } + + /* Inner PTE, continue walking */ + if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { return TRANSLATE_FAIL; - } else { - /* if necessary, set accessed and dirty bits. */ - target_ulong updated_pte =3D pte | PTE_A | + } + base =3D ppn << PGSHIFT; + } + + /* No leaf pte at any translation level. */ + return TRANSLATE_FAIL; + + leaf: + if (ppn & ((1ULL << ptshift) - 1)) { + /* Misaligned PPN */ + return TRANSLATE_FAIL; + } + if (!pbmte && (pte & PTE_PBMT)) { + /* Reserved without Svpbmt. */ + return TRANSLATE_FAIL; + } + if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D PTE_W) { + /* Reserved leaf PTE flags: PTE_W */ + return TRANSLATE_FAIL; + } + if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D (PTE_W | PTE_X)) { + /* Reserved leaf PTE flags: PTE_W + PTE_X */ + return TRANSLATE_FAIL; + } + if ((pte & PTE_U) && + ((mode !=3D PRV_U) && (!sum || access_type =3D=3D MMU_INST_FETCH))= ) { + /* + * User PTE flags when not U mode and mstatus.SUM is not set, + * or the access type is an instruction fetch. + */ + return TRANSLATE_FAIL; + } + if (!(pte & PTE_U) && (mode !=3D PRV_S)) { + /* Supervisor PTE flags when not S mode */ + return TRANSLATE_FAIL; + } + if (access_type =3D=3D MMU_DATA_LOAD && + !((pte & PTE_R) || ((pte & PTE_X) && mxr))) { + /* Read access check failed */ + return TRANSLATE_FAIL; + } + if (access_type =3D=3D MMU_DATA_STORE && !(pte & PTE_W)) { + /* Write access check failed */ + return TRANSLATE_FAIL; + } + if (access_type =3D=3D MMU_INST_FETCH && !(pte & PTE_X)) { + /* Fetch access check failed */ + return TRANSLATE_FAIL; + } + + /* If necessary, set accessed and dirty bits. */ + target_ulong updated_pte =3D pte | PTE_A | (access_type =3D=3D MMU_DATA_STORE ? PTE_D : 0); =20 - /* Page table updates need to be atomic with MTTCG enabled */ - if (updated_pte !=3D pte) { - if (!hade) { - return TRANSLATE_FAIL; - } + /* Page table updates need to be atomic with MTTCG enabled */ + if (updated_pte !=3D pte) { + if (!hade) { + return TRANSLATE_FAIL; + } =20 - /* - * - if accessed or dirty bits need updating, and the PTE = is - * in RAM, then we do so atomically with a compare and s= wap. - * - if the PTE is in IO space or ROM, then it can't be up= dated - * and we return TRANSLATE_FAIL. - * - if the PTE changed by the time we went to update it, = then - * it is no longer valid and we must re-walk the page ta= ble. - */ - MemoryRegion *mr; - hwaddr l =3D sizeof(target_ulong), addr1; - mr =3D address_space_translate(cs->as, pte_addr, &addr1, &= l, - false, MEMTXATTRS_UNSPECIFIED= ); - if (memory_region_is_ram(mr)) { - target_ulong *pte_pa =3D - qemu_map_ram_ptr(mr->ram_block, addr1); + /* + * - if accessed or dirty bits need updating, and the PTE is + * in RAM, then we do so atomically with a compare and swap. + * - if the PTE is in IO space or ROM, then it can't be updated + * and we return TRANSLATE_FAIL. + * - if the PTE changed by the time we went to update it, then + * it is no longer valid and we must re-walk the page table. + */ + MemoryRegion *mr; + hwaddr l =3D sizeof(target_ulong), addr1; + mr =3D address_space_translate(cs->as, pte_addr, &addr1, &l, + false, MEMTXATTRS_UNSPECIFIED); + if (memory_region_is_ram(mr)) { + target_ulong *pte_pa =3D qemu_map_ram_ptr(mr->ram_block, addr1= ); #if TCG_OVERSIZED_GUEST - /* - * MTTCG is not enabled on oversized TCG guests so - * page table updates do not need to be atomic - */ - *pte_pa =3D pte =3D updated_pte; + /* + * MTTCG is not enabled on oversized TCG guests so + * page table updates do not need to be atomic + */ + *pte_pa =3D pte =3D updated_pte; #else - target_ulong old_pte =3D - qatomic_cmpxchg(pte_pa, pte, updated_pte); - if (old_pte !=3D pte) { - goto restart; - } else { - pte =3D updated_pte; - } -#endif - } else { - /* - * misconfigured PTE in ROM (AD bits are not preset) or - * PTE is in IO space and can't be updated atomically - */ - return TRANSLATE_FAIL; - } + target_ulong old_pte =3D qatomic_cmpxchg(pte_pa, pte, updated_= pte); + if (old_pte !=3D pte) { + goto restart; } - + pte =3D updated_pte; +#endif + } else { /* - * for superpage mappings, make a fake leaf PTE for the TLB's - * benefit. + * Misconfigured PTE in ROM (AD bits are not preset) or + * PTE is in IO space and can't be updated atomically. */ - target_ulong vpn =3D addr >> PGSHIFT; - - if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { - napot_bits =3D ctzl(ppn) + 1; - if ((i !=3D (levels - 1)) || (napot_bits !=3D 4)) { - return TRANSLATE_FAIL; - } - } + return TRANSLATE_FAIL; + } + } =20 - napot_mask =3D (1 << napot_bits) - 1; - *physical =3D (((ppn & ~napot_mask) | (vpn & napot_mask) | - (vpn & (((target_ulong)1 << ptshift) - 1)) - ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); + /* For superpage mappings, make a fake leaf PTE for the TLB's benefit.= */ + target_ulong vpn =3D addr >> PGSHIFT; =20 - /* set permissions on the TLB entry */ - if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { - *prot |=3D PAGE_READ; - } - if (pte & PTE_X) { - *prot |=3D PAGE_EXEC; - } - /* - * add write permission on stores or if the page is already di= rty, - * so that we TLB miss on later writes to update the dirty bit - */ - if ((pte & PTE_W) && - (access_type =3D=3D MMU_DATA_STORE || (pte & PTE_D))) { - *prot |=3D PAGE_WRITE; - } - return TRANSLATE_SUCCESS; + if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { + napot_bits =3D ctzl(ppn) + 1; + if ((i !=3D (levels - 1)) || (napot_bits !=3D 4)) { + return TRANSLATE_FAIL; } } - return TRANSLATE_FAIL; + + napot_mask =3D (1 << napot_bits) - 1; + *physical =3D (((ppn & ~napot_mask) | (vpn & napot_mask) | + (vpn & (((target_ulong)1 << ptshift) - 1)) + ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); + + /* set permissions on the TLB entry */ + if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { + *prot |=3D PAGE_READ; + } + if (pte & PTE_X) { + *prot |=3D PAGE_EXEC; + } + /* + * Add write permission on stores or if the page is already dirty, + * so that we TLB miss on later writes to update the dirty bit. + */ + if ((pte & PTE_W) && (access_type =3D=3D MMU_DATA_STORE || (pte & PTE_= D))) { + *prot |=3D PAGE_WRITE; + } + return TRANSLATE_SUCCESS; } =20 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248864; x=1685840864; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ho41lpjeATC7N1pQUPpGcon/1Mo2ide/rqHX/jMW8jQ=; b=NO03irhhD8sXqVu/I+GddYoDrn8/cd4c+L4U9p3WWwTuLih4W6kcd+Ud3mxTyXYbAv Vj5XVf3SW9XrvWUIYzQ6KARHBKyy0jzxlSwW7hchtcsYWm9kx3qGqXzGT+3+YUWdFlEh 6wrRrN7/EFWxz7eyp2EyLFv5B88TktKNHER+z8cZlWg5MgfpfaRd0gz476+SSIT8paPF pgUJJv+Rggirf2eTDj3epoQE5NfLazIgWevWy8YKK3Xrl0zJNZaLF+QQ2yPDkT40vjwp pfn+2jJNzLmXW6KBUopdIXCBcpiRCeENV69C3xvxz3xikJa3AG/FN4dlCWTp69vQkNxU +Wtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248864; x=1685840864; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ho41lpjeATC7N1pQUPpGcon/1Mo2ide/rqHX/jMW8jQ=; b=h+yri8a4CfyiEzBTCu/AUnwF9icZwnMsfngbDaLrwAX59ffTdnFJpqgcGKtLdksKfZ E0qmVkRxn3fOazD+DNicmk1LAupbsVAWUS7xTkeh3vD2I25luQj8MdegSef5SnGH+2Y8 0X8lxnEAUuDOy00hlmsnlKB00bCsn7FvFBjO4Jz3AZsPqZtKJpRgUkU4+tn5CI0XbyeN 60TSAsAeAOBIKFfC/HSMzEda7DyqquRf0YoH+5t4jwpxqXp4v6xkTpzkUFKme0leesKS z9siqu8hQf/0JpEO74ZVEVds04RxjuxzyYc70vun+uRigUnlQJ1JxTIksvLTMAy8RY6A AM3g== X-Gm-Message-State: AC+VfDzNeUcX8B6dMXtYGqn6ci8DT1vQ1CHwmnBbHz6oFeG7IjQSqEKZ lHk0p71wxtw2ypV7Rdk65Fr/ya1+N01u5w== X-Google-Smtp-Source: ACHHUZ7sC1MzFxFEdEvAXV9+qTOHcl5zsOoaCNti8Gk/el0vLarAhPg+q0kaAf322V2gw9zazC+RLg== X-Received: by 2002:a17:90b:811:b0:24e:56e4:9718 with SMTP id bk17-20020a17090b081100b0024e56e49718mr4094559pjb.15.1683248864541; Thu, 04 May 2023 18:07:44 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 77/89] target/riscv: Suppress pte update with is_debug Date: Fri, 5 May 2023 11:02:29 +1000 Message-Id: <20230505010241.21812-78-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=alistair23@gmail.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249220586100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson The debugger should not modify PTE_A or PTE_D. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-22-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-22-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c2d083f029..6dc3fdf594 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1001,7 +1001,7 @@ restart: (access_type =3D=3D MMU_DATA_STORE ? PTE_D : 0); =20 /* Page table updates need to be atomic with MTTCG enabled */ - if (updated_pte !=3D pte) { + if (updated_pte !=3D pte && !is_debug) { if (!hade) { return TRANSLATE_FAIL; } --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249209; cv=none; d=zohomail.com; s=zohoarc; b=QisD9/PeIlTNoO8N+RwUip+VQeo8r38Rk//RAv7VZHlCgSFeHcR7sjMgmWFm/N5R6WieTWZEQ++ODDnZN8bwEemqmP0xWjmAaFUrvwc26xH8YaDYyFbfY2QVv6hOQWEQuuVlS0MU8Wj1Wq1dCK6PF58HRJG9VYJ5Ia34zDQC+W4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249209; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rrHxR+eiZh8W9v/w2e7/d7prgivlc2G2D0PUHvIbg2s=; b=WwWH8ZN4+o3W+PSWIvwbzuTMDFW2WAwoyVD+12wA9bp4U9zDd9XtTyVcTlwU/P/M3erme+1YDzb+3no6z40tFrMh7wGw4C3PrOpBbKkSa8zE4MGuuTkPKbKVeaW+KS96KjRCVUYlgUY4h3H0+IWeDVPQ/jWy6wFCu6auyhldKNc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249209708851.8844424352923; Thu, 4 May 2023 18:13:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujw9-000232-QC; Thu, 04 May 2023 21:08:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujvL-0000uW-Iu for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:51 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujvJ-000860-O3 for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:51 -0400 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-24e015fcf3dso931895a91.3 for ; Thu, 04 May 2023 18:07:49 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248868; x=1685840868; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rrHxR+eiZh8W9v/w2e7/d7prgivlc2G2D0PUHvIbg2s=; b=EtcBpEpMtqmr2taqIeWkwvrRzZZMETzTadrBFIRkxySiJbOOEAQoI8gZZt0N3otq4A p7JlsFO+h+H4dmsIbu+0zMGbssNnnE77beEz1q0eMKVGgnW1smWPBjex9HasmUpazmVZ 8aoi54NXQF7RnjfippmHbpqsJCPMfD6blyMdoxHsxdKmStive80NFNuniUGRrs5acdXx e9AFGB4m5fReBNC4i/KYI2rivBUkYSzh7FX9sk/fa+u+fxE8yHnxyppgeAZtWyGtZHVx R6H5C5suXc2SRmwJL+zyPELbvcdCEYL982ZKmGcd3XrCmdjLeL4ghWVqZgimgDpDhFLX xTog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248868; x=1685840868; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rrHxR+eiZh8W9v/w2e7/d7prgivlc2G2D0PUHvIbg2s=; b=R0lB/ftGY9DNbBwpvyUjFOuxWwFhiVPq33pdlhB6FWj7uwReLiR3K97Nam45zUW8zX 5erGgwWuYDUnHaJ4yfSeVsojHk8T03ZWiMgSbMxdzoEEtmPID1xwXHSgxVGk7IJynRBX U9zrZ/9T0ni5vP4aAe+ll7RbnhjHqD3HlFcn+EctzqgOTiDzmjedg362JQms4n+D/sdR kDAbdGdn0Eh8Zbq6f7dOi+xl5R32ebtNhWlIhfgkr0VWyF9kc1uBxSdRUMgevGw3Hck2 r6wIXu8FdIQ7bfHV32SIG1YAbaTDpUp47rwWyu6dTCVEwVJLyUnV2Z0t4QTSWw+uuyTr F/Ug== X-Gm-Message-State: AC+VfDwOSSmi/bx3C4L5Afw16sbdS8rTgbQK9xt7N9rMqNzDcJw79cAq 2nxzVhSh/kpKcwFBnsW8qk4snCQbq3nuuw== X-Google-Smtp-Source: ACHHUZ4yS/+CUbdeDnA+n0pbgimztEEgD9OYwLgLmQ+bx+f59TySAkBI9o7y1d16T553UOdBsXQ+aQ== X-Received: by 2002:a17:90a:9dc9:b0:24d:fcc0:1949 with SMTP id x9-20020a17090a9dc900b0024dfcc01949mr4503655pjv.12.1683248867979; Thu, 04 May 2023 18:07:47 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 78/89] target/riscv: Don't modify SUM with is_debug Date: Fri, 5 May 2023 11:02:30 +1000 Message-Id: <20230505010241.21812-79-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=alistair23@gmail.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249210153100005 Content-Type: text/plain; charset="utf-8" From: Richard Henderson If we want to give the debugger a greater view of memory than the cpu, we should simply disable the access check entirely, not simply for this one corner case. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-23-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-23-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 6dc3fdf594..9a2b944990 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -823,7 +823,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, } widened =3D 2; } - sum =3D mmuidx_sum(mmu_idx) || is_debug; + sum =3D mmuidx_sum(mmu_idx); switch (vm) { case VM_1_10_SV32: levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249252; cv=none; d=zohomail.com; s=zohoarc; b=hmvRnXOkvjkID7jQvJ2jwTX8obC1v6Af3Yf9H4yrhC+VKroHWHdykWvzgiU+klqRYKIAWBY9pXKDo8T7VSSgOmfAEQ1gSyHsY8LYqzhH4kfqTsx68t9Dy/E21HN541VbZu1acUmPvM1aJtoyJVVYr4xzldRu5FrGWlLfWOEwCNE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249252; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ULqMf+DmHpGYNoo8G2xP3dFFiX1NCkBJ2cATdvrFXCY=; b=LlONe4ihUQZlAD+qLG+eBEAceo4ab+wLiuQOsd02ll73564u6WFjy3W6JHoIAvejW0wqHM01E3SnHwsxuMmEteywLnKUdbAuVm9SgyxwCGRT84Ocf64rd70ijUj76PfQfslf5TCLyfwZyYYHwOvOI+59z2t+0z2CkEG3E4+iiM8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249252731988.8625996963068; Thu, 4 May 2023 18:14:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujva-0001BH-RG; Thu, 04 May 2023 21:08:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujvS-00011C-6S for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:59 -0400 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujvQ-00086q-AK for qemu-devel@nongnu.org; Thu, 04 May 2023 21:07:57 -0400 Received: by mail-pg1-x52e.google.com with SMTP id 41be03b00d2f7-52c6f8ba7e3so1040759a12.3 for ; Thu, 04 May 2023 18:07:52 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249254528100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-24-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-24-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9a2b944990..c7c384bae3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -962,14 +962,14 @@ restart: /* Reserved without Svpbmt. */ return TRANSLATE_FAIL; } - if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D PTE_W) { - /* Reserved leaf PTE flags: PTE_W */ - return TRANSLATE_FAIL; - } - if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D (PTE_W | PTE_X)) { - /* Reserved leaf PTE flags: PTE_W + PTE_X */ + + /* Check for reserved combinations of RWX flags. */ + switch (pte & (PTE_R | PTE_W | PTE_X)) { + case PTE_W: + case PTE_W | PTE_X: return TRANSLATE_FAIL; } + if ((pte & PTE_U) && ((mode !=3D PRV_U) && (!sum || access_type =3D=3D MMU_INST_FETCH))= ) { /* --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249208; cv=none; d=zohomail.com; s=zohoarc; b=c9f/3X72H+um6HP6OxdUnzW29d23t5I7CfM8/439B0DmlO6D1Fl/8dkajLM+6qfL+QTAqW6NlF8rlWyNUJv6zEH8fqKufqkn72kDsLl1A03FFJe7yP6UaW5yWHUUQp79pMh9N1r5XxKhrHr5Gln7exYr/dr+Y3AfPhNIWSxQqUo= ARC-Message-Signature: i=1; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248875; x=1685840875; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X0bxKSCSa5QVRZAElH/ASf7kECM7kPPJ9uPPjJAQxQU=; b=Acozb0kyBipjhCMhrtCO+BYM5SdUNi8qHPnn1w5qr05MbUJ3kAz/V1ZKO0FijJvxeH 3ZGQT3y/Fp/3srsbecWlSLQH0iy/EcToGNm4yzANIBuf/NZnMvPNFO7n6MSmC07MbFJn TKv86JJqL46yTZyV2GrLU7Uax76D0jb71nKbzkoRUW6J5aABo3p3Nqb/H+4kYVWGTjYX w5HDu3wTNpyRNof50I5hXbW3V3BdVdXGVjAkak9bauRx8V1J9aflQteDWuvPwvlpBPVN iCArQessLBOnnhj09+NigXsyKAN7BHI1qa2MjHIa4AcveMsvb04CzkgW1agrGJyV8lls dN+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248875; x=1685840875; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X0bxKSCSa5QVRZAElH/ASf7kECM7kPPJ9uPPjJAQxQU=; b=GSNJlUumpzCYM8Hyo6LhmF+yQ2ZKZQgBsOQ9hv7+xcrfGBrPaiHd5xdO+PpzVR3dgV 8B/+LAx46Rr+JkUNqNenva+xR5Tqz+8SX8zbEhKAkMP3iKOX4HiL9q9rz8Zefs4S39Mi 4f6pRsiH/YkwujcfJjk8VVyDglE3zJx+ahfWDJQFaLx+k/pSPrPitCZ5mV9Q8ouV22wn 6ruI1+wgaT5Sb04jdgXGxI8XHTf7lfXL+rAmfrVn/JBcC1ChM9VIwHovCBuOVlcjX7WY GSoNdLeRtk16Njcn7ZPED3m64naL86LYnmbXtWQuZPYm4qCtj9UmKArn7C7LllLIgxGT Isuw== X-Gm-Message-State: AC+VfDzwJwiNGZJxTSJbrjiuQkzqe7KSHkLoOocI+yrVqWDwWF0+GJL/ Cjk8mseoK45oeNcNfVh+SGqsn80aZbbkEw== X-Google-Smtp-Source: ACHHUZ4tS5bp+ZjAGi0DKQYnJsrsCcvBr17y0eNSPZNuLvA2TR+CjYiNyyHKgvTgoPwpNBr560N/BA== X-Received: by 2002:a17:903:22c9:b0:1aa:cf25:41d0 with SMTP id y9-20020a17090322c900b001aacf2541d0mr7640007plg.33.1683248875096; Thu, 04 May 2023 18:07:55 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 80/89] target/riscv: Reorg access check in get_physical_address Date: Fri, 5 May 2023 11:02:32 +1000 Message-Id: <20230505010241.21812-81-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249208488100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson We were effectively computing the protection bits twice, once while performing access checks and once while returning the valid bits to the caller. Reorg so we do this once. Move the computation of mxr close to its single use. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-25-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-25-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 69 ++++++++++++++++++++------------------- 1 file changed, 36 insertions(+), 33 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c7c384bae3..7849e18554 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -747,7 +747,7 @@ static int get_physical_address_pmp(CPURISCVState *env,= int *prot, * @is_debug: Is this access from a debugger or the monitor? */ static int get_physical_address(CPURISCVState *env, hwaddr *physical, - int *prot, vaddr addr, + int *ret_prot, vaddr addr, target_ulong *fault_pte_addr, int access_type, int mmu_idx, bool first_stage, bool two_stage, @@ -779,20 +779,14 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, =20 if (mode =3D=3D PRV_M || !riscv_cpu_cfg(env)->mmu) { *physical =3D addr; - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + *ret_prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TRANSLATE_SUCCESS; } =20 - *prot =3D 0; + *ret_prot =3D 0; =20 hwaddr base; - int levels, ptidxbits, ptesize, vm, sum, mxr, widened; - - if (first_stage =3D=3D true) { - mxr =3D get_field(env->mstatus, MSTATUS_MXR); - } else { - mxr =3D get_field(env->vsstatus, MSTATUS_MXR); - } + int levels, ptidxbits, ptesize, vm, sum, widened; =20 if (first_stage =3D=3D true) { if (use_background) { @@ -835,7 +829,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, levels =3D 5; ptidxbits =3D 9; ptesize =3D 8; break; case VM_1_10_MBARE: *physical =3D addr; - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + *ret_prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TRANSLATE_SUCCESS; default: g_assert_not_reached(); @@ -970,6 +964,27 @@ restart: return TRANSLATE_FAIL; } =20 + int prot =3D 0; + if (pte & PTE_R) { + prot |=3D PAGE_READ; + } + if (pte & PTE_W) { + prot |=3D PAGE_WRITE; + } + if (pte & PTE_X) { + bool mxr; + + if (first_stage =3D=3D true) { + mxr =3D get_field(env->mstatus, MSTATUS_MXR); + } else { + mxr =3D get_field(env->vsstatus, MSTATUS_MXR); + } + if (mxr) { + prot |=3D PAGE_READ; + } + prot |=3D PAGE_EXEC; + } + if ((pte & PTE_U) && ((mode !=3D PRV_U) && (!sum || access_type =3D=3D MMU_INST_FETCH))= ) { /* @@ -982,17 +997,9 @@ restart: /* Supervisor PTE flags when not S mode */ return TRANSLATE_FAIL; } - if (access_type =3D=3D MMU_DATA_LOAD && - !((pte & PTE_R) || ((pte & PTE_X) && mxr))) { - /* Read access check failed */ - return TRANSLATE_FAIL; - } - if (access_type =3D=3D MMU_DATA_STORE && !(pte & PTE_W)) { - /* Write access check failed */ - return TRANSLATE_FAIL; - } - if (access_type =3D=3D MMU_INST_FETCH && !(pte & PTE_X)) { - /* Fetch access check failed */ + + if (!((prot >> access_type) & 1)) { + /* Access check failed */ return TRANSLATE_FAIL; } =20 @@ -1057,20 +1064,16 @@ restart: (vpn & (((target_ulong)1 << ptshift) - 1)) ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); =20 - /* set permissions on the TLB entry */ - if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { - *prot |=3D PAGE_READ; - } - if (pte & PTE_X) { - *prot |=3D PAGE_EXEC; - } /* - * Add write permission on stores or if the page is already dirty, - * so that we TLB miss on later writes to update the dirty bit. + * Remove write permission unless this is a store, or the page is + * already dirty, so that we TLB miss on later writes to update + * the dirty bit. */ - if ((pte & PTE_W) && (access_type =3D=3D MMU_DATA_STORE || (pte & PTE_= D))) { - *prot |=3D PAGE_WRITE; + if (access_type !=3D MMU_DATA_STORE && !(pte & PTE_D)) { + prot &=3D ~PAGE_WRITE; } + *ret_prot =3D prot; + return TRANSLATE_SUCCESS; } =20 --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248879; x=1685840879; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jWK90p2Eci+LzLUTXl/keL5kSllvMWrMFH8qzWh6iwY=; b=RJZex31dgTh4SmG7V5ceoc0MB41RwRii862/vbRykHAnk7Rxy2vtS/+PnZX0x7ZcSN STcDpc5slZq6/sxFWp3AlZlime31WukCJFoq/fn7/Y9G7TgZPtyhPkAI8z6xrxDsfeUP O9QoXCEPsP8lj2lkceykYVCNxzK4q9WYa2afBRaGQOArWu+1N8LZL0/WrIZfM3O8PJVU sey3PP4ICJDc8gItkNw/wnbTmowmO+m+jvJXG40G0PWYM82jr8gm3XfzBWo++StfAwhR LotKwaklfB3mjQT1XyD9lBuAWfhFCBOu4QBpgP68a6HMspKpj1JkiynYHNGNXeTlDdqn qpyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248879; x=1685840879; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jWK90p2Eci+LzLUTXl/keL5kSllvMWrMFH8qzWh6iwY=; b=PEHXm+bR0wGnOEPzt3VFT9QKpN3Hd7CumZcqH+i1BGY43Dz3Jruz1sPeDPabwe4fr4 cLFZvcYK8ZAwpFISsf+shJvSLj/rpfazfPX0qB9Pubkzzs9iWeJXiDRzfXVBo3+eRbRq 2pFSRcvEdJgKGVh7FFKbgMX/HG/+hIbZ18A0c3pyFy6Xol2vdjKrYQ262s/fvvWpDL7b FaujXQX+7uFIbH4bysgyyDLyF9EHQhVOyV3kBtZxkpkyF9euHkSQa/WT46wBgvWHVzVh pQ2cHjkDILAI2hjev8IHpqsovcFvhoqhKEqi6uUuZ9Cjmfo3Sni+9BEXGzGgNNzMvqNQ OqOA== X-Gm-Message-State: AC+VfDyizwzMoepl7pdAtXOsgRvyACi8wwUUayHkcu3pT6tNVpqofGQ3 fJQIlZnveNXUhyF7kS0tjH+7iTH4sLL0qw== X-Google-Smtp-Source: ACHHUZ4HbeMhPG7ciY5wDZyZCYapkvKHFvhnmaKRnWD4p9EXyvsFvxofPy34tDmHL4tAceLsadZi3Q== X-Received: by 2002:a17:902:dac5:b0:1a9:ba26:6cfa with SMTP id q5-20020a170902dac500b001a9ba266cfamr6943413plx.64.1683248878736; Thu, 04 May 2023 18:07:58 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 81/89] target/riscv: Reorg sum check in get_physical_address Date: Fri, 5 May 2023 11:02:33 +1000 Message-Id: <20230505010241.21812-82-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=alistair23@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249555062100005 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Implement this by adjusting prot, which reduces the set of checks required. This prevents exec to be set for U pages in MMUIdx_S_SUM. While it had been technically incorrect, it did not manifest as a bug, because we will never attempt to execute from MMUIdx_S_SUM. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-26-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-26-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 7849e18554..32a65f8007 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -786,7 +786,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, *ret_prot =3D 0; =20 hwaddr base; - int levels, ptidxbits, ptesize, vm, sum, widened; + int levels, ptidxbits, ptesize, vm, widened; =20 if (first_stage =3D=3D true) { if (use_background) { @@ -817,7 +817,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, } widened =3D 2; } - sum =3D mmuidx_sum(mmu_idx); + switch (vm) { case VM_1_10_SV32: levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; @@ -985,15 +985,15 @@ restart: prot |=3D PAGE_EXEC; } =20 - if ((pte & PTE_U) && - ((mode !=3D PRV_U) && (!sum || access_type =3D=3D MMU_INST_FETCH))= ) { - /* - * User PTE flags when not U mode and mstatus.SUM is not set, - * or the access type is an instruction fetch. - */ - return TRANSLATE_FAIL; - } - if (!(pte & PTE_U) && (mode !=3D PRV_S)) { + if (pte & PTE_U) { + if (mode !=3D PRV_U) { + if (!mmuidx_sum(mmu_idx)) { + return TRANSLATE_FAIL; + } + /* SUM allows only read+write, not execute. */ + prot &=3D PAGE_READ | PAGE_WRITE; + } + } else if (mode !=3D PRV_S) { /* Supervisor PTE flags when not S mode */ return TRANSLATE_FAIL; } --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249479; cv=none; d=zohomail.com; s=zohoarc; b=fwgQDLSW8hC9W4PD342SoJrv0ZMebutDkaR/VLXZaWx3Jrkwlu9hCvk3qJQutPS5JOLtHnnJT3IlA+t0169TeMOfWyqNVJxmseHe7jirs1F5Jw2SIZTb3OwxWyQx28fBTJacVt326uaMMzsf5doo7ukUyEHtOpWW4OXVtIWAH2U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249479; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WqATn5U2LteHkQUhr4ed0Zy0wxeNGC/euNQ0q+PyYgY=; b=agMzGKu0uZ7c0X/KOEG72gFOaXYSmWilE9hPl7Hr/NmoAnu8ssMvMXZoR/5DEx2HCzOidyGPcYL2sVRuxhCywNK4V+gOmI50uT72Dio7s3E9AsAxPlDyTS9RnNVe0MC9Jb/zWM0yrpmtTYWedxwpMgZv6VjbjIW5TN9FCbvYGqQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249479276584.4130109500018; Thu, 4 May 2023 18:17:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujx2-00034F-0U; Thu, 04 May 2023 21:09:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujvZ-0001Ad-Is for qemu-devel@nongnu.org; Thu, 04 May 2023 21:08:06 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujvX-000891-RA for qemu-devel@nongnu.org; Thu, 04 May 2023 21:08:05 -0400 Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-51f597c975fso1057871a12.0 for ; Thu, 04 May 2023 18:08:03 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:08:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248882; x=1685840882; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WqATn5U2LteHkQUhr4ed0Zy0wxeNGC/euNQ0q+PyYgY=; b=mK5OX32FnBkIjJZ/qKrAIjEr84PIlJdkTkuh4jD8+PVM9tAoyhSgKu+Tm7KiQ7WNCX MF6eoSYhxNcgKI5CEezForhJPXSM2UP8/YrVVZ3WbP9z3XJc2iJN3DBwvrg4Js89pz30 zVTSU14m85V/g84GKVjvkWtV9h9/0GaeemiG5cOIdRk2eHyeeWsml0Llqi8Qy/XCn3pw nsE/kJKAEKuY99V5KYqLisQK684rm55Nl7JpJ5LHHTPJu2DCtLeuduDO2K3UPtG6Dsja at+Whs+CQ9o0AlKLa5Vfi7F4TZsuLJVHkeCXuYG6bFIHakF9JG79PlA0mlz42FeEcVox gNWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248882; x=1685840882; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WqATn5U2LteHkQUhr4ed0Zy0wxeNGC/euNQ0q+PyYgY=; b=ECeWjimcrxGjjYPZkuF2hd4dGOWAyIbC5a4qbpE+a/VKN9rm0dfTwutx6/cfV1Pq9+ VNLRs0qG7ezPTHUYL3NzNfoNy40Ms1598jsMESK7+ySKOmNDALxbT9aCzo2dotB9saOL PEUoJoqJOPuEPnZ1przunD8j4Qfka046ShWiplpoQx3XDeWLwBMMETWU+sodZbeZwf5w i0kcvhbaj+QhO4Ou9h6l5n7pt+rF3vsfHv25Q94/7w70eyGMk3QXhMMwn9ouOFLH73Wg hUKPIrE5+MWPr06M3q1cRH3HNpxxWYcjH9oikgfuqhkoV527uJXlfjd8ZdlbmwdstMEn T2BA== X-Gm-Message-State: AC+VfDwH5MveODedsbWAg9DNfYrOuIZLKrxKhlN48QaSVT9tinNM7bUF N2l1Ws3XS0wBMYYmAuJ7mBgSAb1UCUnoMA== X-Google-Smtp-Source: ACHHUZ6bKhWeH5tD1IDZ6ZIJAsHsoN/LcExIcDEXj35S/xS5LGNtat/CvejSpdhyyKZdN7+FeS0bCw== X-Received: by 2002:a17:902:b087:b0:1aa:ebaa:51ce with SMTP id p7-20020a170902b08700b001aaebaa51cemr5100902plr.14.1683248882159; Thu, 04 May 2023 18:08:02 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Ivan Klokov , Alistair Francis , Anup Patel Subject: [PULL 82/89] hw/intc/riscv_aplic: Zero init APLIC internal state Date: Fri, 5 May 2023 11:02:34 +1000 Message-Id: <20230505010241.21812-83-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249480115100015 Content-Type: text/plain; charset="utf-8" From: Ivan Klokov Since g_new is used to initialize the RISCVAPLICState->state structure, in some case we get behavior that is not as expected. This patch changes this to g_new0, which allows to initialize the APLIC in the correct= state. Signed-off-by: Ivan Klokov Reviewed-by: Alistair Francis Reviewed-by: Anup Patel Message-Id: <20230413133432.53771-1-ivan.klokov@syntacore.com> Signed-off-by: Alistair Francis --- hw/intc/riscv_aplic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index cd7efc4ad4..afc5b54dbb 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -803,7 +803,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error= **errp) =20 aplic->bitfield_words =3D (aplic->num_irqs + 31) >> 5; aplic->sourcecfg =3D g_new0(uint32_t, aplic->num_irqs); - aplic->state =3D g_new(uint32_t, aplic->num_irqs); + aplic->state =3D g_new0(uint32_t, aplic->num_irqs); aplic->target =3D g_new0(uint32_t, aplic->num_irqs); if (!aplic->msimode) { for (i =3D 0; i < aplic->num_irqs; i++) { --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249392; cv=none; d=zohomail.com; s=zohoarc; b=R+599gqxsoZYK/Y/V+UX2oc4SZtS9Np5ggTcN//DuwQpmewxRdvAjlmfjclg7QBR6i1wreDo4YPJL3AG4HHmX7nnYhJpQkbsp+YYW1FXJ13rU05h4iijcx+iwWDRNa+2D+l7T9lZ5zntqB6HCxRLLBQy793rGU2VYA4pKr3av6s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249392; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7DEKsMZI/zUfkQT1MmyPbn61GggAQ1+G6neGMUD2jNA=; b=GenW1ChGkuOmqKZzOx6U9rbNlLyfbszLtpu8sG4mztKSDq4RVITW+ChWMpkfFaEA7lwgDdFK5Q5BrS0XaZXz505WEf8xT/vmKZLAfL/icCoXdLjSYDz4IsT9bkkVcBwzExX+7YHo3pBuJekvnkCofuwBjhUFa0K+CUzWHLVrB7s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249392310265.91632973883634; Thu, 4 May 2023 18:16:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujwu-0002lC-Fc; Thu, 04 May 2023 21:09:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujvi-0001RZ-17 for qemu-devel@nongnu.org; Thu, 04 May 2023 21:08:17 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujvc-00089Y-Kz for qemu-devel@nongnu.org; Thu, 04 May 2023 21:08:12 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1aaed87d8bdso8145815ad.3 for ; Thu, 04 May 2023 18:08:06 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.08.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:08:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248885; x=1685840885; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7DEKsMZI/zUfkQT1MmyPbn61GggAQ1+G6neGMUD2jNA=; b=WosXFaqsUulL7thsQXNZjk84RJERejE5L0sGw31PNKIh+6Jy1VxPllSjYJYzQ1RWOV t9UVl0aimiO/ezMgrpHZwzunV9Qbfuvk4rlpV50oZCYfxpS577v24r8+czfDIl+/D4Mi nzYewBAK96s4Hq9CUiNa9KFrHwkVCpoRLjFj/bV+yL7ioutR6/i4vHt9ZPZ/pqTIK4L9 2vavACP060EeEHwujsp6MSl8AajvS2Mo+gOtESZs10WwSbFCJRwGf9Kk6lbIYlNe7iYj L/Depl7BENacVzCjVv6RE69BK4fL3q3FbdSAYXRyDS75YBWlNfuL25c7Qir6cixzzDXt ODMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248885; x=1685840885; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7DEKsMZI/zUfkQT1MmyPbn61GggAQ1+G6neGMUD2jNA=; b=juIggRYTnczwBSOJGWz1/MUlVNkGQiciZSNCLxouY9VyhJO5CpowsUZKbRZg85O5fe b8OlAAz0/uHv6tYN5umVX8T+JEe4ukwl4h9L7Nu1hH15X6RUhyzZ/519HYChxohphsjG CPnEt2bAwKkPISw4Al6jKBancLBNExqGWE2uoECIF7q/uLcYsA/VgqBSxY9NrP88WuBh TG4N/zEMZrseFax0Pb1+WbD5PHAEfuCTx8c9lb+PLo25zNeXdMGwUhjZ1YNSr7bFi2C4 wAaqTknUIWSpIe+r/nkPsk/VRnd9bOD2N/oKgx9aF3m+13Lk68NGDQ7x9whBZvKpGQ0S BgSQ== X-Gm-Message-State: AC+VfDzrcA6O/8RxTmVh6C7wdsZxib1FKmFvju0RRTar/J9Wl2PCTi9I sr7cLifWYXeXUKK73oHZEGS43beuMcvnmg== X-Google-Smtp-Source: ACHHUZ6cmoOVqlPCfXqEBipYh6X0xxUGN7nVmv24JLrSh+GOugIDPEad4E/PQemmcj50N3Q2s+BWgw== X-Received: by 2002:a17:902:ce8f:b0:1aa:ebcc:dd5e with SMTP id f15-20020a170902ce8f00b001aaebccdd5emr6472467plg.65.1683248885507; Thu, 04 May 2023 18:08:05 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Richard Henderson , Alistair Francis Subject: [PULL 83/89] target/riscv: add CPU QOM header Date: Fri, 5 May 2023 11:02:35 +1000 Message-Id: <20230505010241.21812-84-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=alistair23@gmail.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249394480100009 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza QMP CPU commands are usually implemented by a separated file, -qmp-cmds.c, to allow them to be build only for softmmu targets. This file uses a CPU QOM header with basic QOM declarations for the arch. We'll introduce query-cpu-definitions for RISC-V CPUs in the next patch, but first we need a cpu-qom.h header with the definitions of TYPE_RISCV_CPU and RISCVCPUClass declarations. These were moved from cpu.h to the new file, and cpu.h now includes "cpu-qom.h". Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20230411183511.189632-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu-qom.h | 70 ++++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 46 +-------------------------- 2 files changed, 71 insertions(+), 45 deletions(-) create mode 100644 target/riscv/cpu-qom.h diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h new file mode 100644 index 0000000000..b9318e0783 --- /dev/null +++ b/target/riscv/cpu-qom.h @@ -0,0 +1,70 @@ +/* + * QEMU RISC-V CPU QOM header + * + * Copyright (c) 2023 Ventana Micro Systems Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef RISCV_CPU_QOM_H +#define RISCV_CPU_QOM_H + +#include "hw/core/cpu.h" +#include "qom/object.h" + +#define TYPE_RISCV_CPU "riscv-cpu" + +#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU +#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) +#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU + +#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") +#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") +#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") +#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") +#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") +#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") +#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") +#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") +#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") +#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") +#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") +#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") + +#if defined(TARGET_RISCV32) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 +#elif defined(TARGET_RISCV64) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 +#endif + +typedef struct CPUArchState CPURISCVState; + +OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) + +/** + * RISCVCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * + * A RISCV CPU model. + */ +struct RISCVCPUClass { + /*< private >*/ + CPUClass parent_class; + /*< public >*/ + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + +#endif /* RISCV_CPU_QOM_H */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d1f888a790..de7e43126a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -28,6 +28,7 @@ #include "qemu/int128.h" #include "cpu_bits.h" #include "qapi/qapi-types-common.h" +#include "cpu-qom.h" =20 #define TCG_GUEST_DEFAULT_MO 0 =20 @@ -37,32 +38,6 @@ */ #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -#define TYPE_RISCV_CPU "riscv-cpu" - -#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU -#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) -#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU - -#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") -#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") -#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") -#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") -#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") -#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") -#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") -#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") -#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") -#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") -#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") -#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") -#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") - -#if defined(TARGET_RISCV32) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 -#elif defined(TARGET_RISCV64) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 -#endif - #define RV(x) ((target_ulong)1 << (x - 'A')) =20 /* Consider updating misa_ext_cfgs[] when adding new MISA bits here */ @@ -109,8 +84,6 @@ typedef enum { =20 #define MAX_RISCV_PMPS (16) =20 -typedef struct CPUArchState CPURISCVState; - #if !defined(CONFIG_USER_ONLY) #include "pmp.h" #include "debug.h" @@ -395,23 +368,6 @@ struct CPUArchState { uint64_t kvm_timer_frequency; }; =20 -OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) - -/* - * RISCVCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * - * A RISCV CPU model. - */ -struct RISCVCPUClass { - /* < private > */ - CPUClass parent_class; - /* < public > */ - DeviceRealize parent_realize; - ResettablePhases parent_phases; -}; - /* * map is a 16-bit bitmap: the most significant set bit in map is the maxi= mum * satp mode that is supported. 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.08.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:08:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248889; x=1685840889; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=egsz01lxxi53UWnT0C0niRQbknsu91Ea77tB7GLF6c4=; b=XRhvHlxe9VXQmyf824ge1B2KcRbjoLUw2G6QE9X4XyUJPtUPUntwN9iDLuzp4v4H8U XW3kzEUKsY4E0qNyEBe5N9WhV4/7fRRYFxGa+WO7rlH2/mK7uyWnokvIYvJQ8K7BK1sj +7Sti11ikZA1M95iBh9sngoXzMPoPr5JenaeZ77zvL5rQGXqBWBqT2qZgD0penU24xdm tUxbRJ0nh6YNOKCj2S56cqLI5whTg4/pxXV2c7fFRkop9dOGIxMYAZ+lW6d+UZsT2Ug9 dYbRwe4TETfrSwq7rM/gSIqtsG+KKaFh3brKStKqTSy6ME3WzBAyF0reuP6Rrj7BBqXy XZMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248889; x=1685840889; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=egsz01lxxi53UWnT0C0niRQbknsu91Ea77tB7GLF6c4=; b=Qz07pi07Tedw902Myv3Z514VHxhOw9MTXT0InU672YgK10OcGYbBIQf2r5EVjxkeNd /9laH/WFgybD/4Itcw3+oRbmPDjNhAMWY/SJfpse5EoM+23gUfwXFgWS3J4pcqzkaZvi 83iJdkHEvdIFsFcqBN9flPTIzCz7ylq5+NIwOPqAGezaZfY0D8QVNwWAjlLCGi6hUv+6 Uab2y6hs5XvpGQtPLPjzUc5qHxE/xyM3o3JPWzaioE2P6A1xg3OUhzp2BQvkeIqL48o2 wbc+krQIR1OAJcbG7xL8f8FC0LaFS/jovOWGIuGcMsuY9IFLhlDw1e4Zt6LOMhh9wpld z9wQ== X-Gm-Message-State: AC+VfDz91RtvlKT7cJhGgenl7mcUOBonHY9ZW6T3pstWwsdZohMZSmFO NZ29M3xN7kwI/A96DAAdeGSQHx6dLYTq1A== X-Google-Smtp-Source: ACHHUZ4m5JRYWol2o8vzCPIW0LzzIOb+oI1r7hdoe5iAqeXmRMNO192ftedrSCDWumv6tKajhJ7v8Q== X-Received: by 2002:a17:902:b7c8:b0:1a6:db0a:8003 with SMTP id v8-20020a170902b7c800b001a6db0a8003mr5548664plz.23.1683248889178; Thu, 04 May 2023 18:08:09 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Richard Henderson , Alistair Francis Subject: [PULL 84/89] target/riscv: add query-cpy-definitions support Date: Fri, 5 May 2023 11:02:36 +1000 Message-Id: <20230505010241.21812-85-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249501798100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza This command is used by tooling like libvirt to retrieve a list of supported CPUs. Each entry returns a CpuDefinitionInfo object that contains more information about each CPU. This initial support includes only the name of the CPU and its typename. Here's what the command produces for the riscv64 target: $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio {"QMP": {"version": (...)} {"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}} {"return": {}} {"execute": "query-cpu-definitions"} {"return": [ {"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated= ": false}, {"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": false,= "deprecated": false}, {"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated":= false}, {"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "depr= ecated": false}, {"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": false, "de= precated": false}, {"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": false,= "deprecated": false}, {"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": false,= "deprecated": false}] } Next patch will introduce a way to tell whether a given CPU is static or not. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20230411183511.189632-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- qapi/machine-target.json | 6 ++-- target/riscv/riscv-qmp-cmds.c | 53 +++++++++++++++++++++++++++++++++++ target/riscv/meson.build | 3 +- 3 files changed, 59 insertions(+), 3 deletions(-) create mode 100644 target/riscv/riscv-qmp-cmds.c diff --git a/qapi/machine-target.json b/qapi/machine-target.json index b94fbdb65e..afc8c40894 100644 --- a/qapi/machine-target.json +++ b/qapi/machine-target.json @@ -324,7 +324,8 @@ 'TARGET_I386', 'TARGET_S390X', 'TARGET_MIPS', - 'TARGET_LOONGARCH64' ] } } + 'TARGET_LOONGARCH64', + 'TARGET_RISCV' ] } } =20 ## # @query-cpu-definitions: @@ -341,4 +342,5 @@ 'TARGET_I386', 'TARGET_S390X', 'TARGET_MIPS', - 'TARGET_LOONGARCH64' ] } } + 'TARGET_LOONGARCH64', + 'TARGET_RISCV' ] } } diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c new file mode 100644 index 0000000000..128677add9 --- /dev/null +++ b/target/riscv/riscv-qmp-cmds.c @@ -0,0 +1,53 @@ +/* + * QEMU CPU QMP commands for RISC-V + * + * Copyright (c) 2023 Ventana Micro Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" + +#include "qapi/qapi-commands-machine-target.h" +#include "cpu-qom.h" + +static void riscv_cpu_add_definition(gpointer data, gpointer user_data) +{ + ObjectClass *oc =3D data; + CpuDefinitionInfoList **cpu_list =3D user_data; + CpuDefinitionInfo *info =3D g_malloc0(sizeof(*info)); + const char *typename =3D object_class_get_name(oc); + + info->name =3D g_strndup(typename, + strlen(typename) - strlen("-" TYPE_RISCV_CPU)); + info->q_typename =3D g_strdup(typename); + + QAPI_LIST_PREPEND(*cpu_list, info); +} + +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +{ + CpuDefinitionInfoList *cpu_list =3D NULL; + GSList *list =3D object_class_get_list(TYPE_RISCV_CPU, false); + + g_slist_foreach(list, riscv_cpu_add_definition, &cpu_list); + g_slist_free(list); + + return cpu_list; +} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 5b7f813a3e..e1ff6d9b95 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -32,7 +32,8 @@ riscv_softmmu_ss.add(files( 'monitor.c', 'machine.c', 'pmu.c', - 'time_helper.c' + 'time_helper.c', + 'riscv-qmp-cmds.c', )) =20 target_arch +=3D {'riscv': riscv_ss} --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249312; cv=none; d=zohomail.com; s=zohoarc; b=Dj9f+hruLOWDzuw5ZHRJKUpTd0pCElAZ53LDly8hkWpW7IH/4kCR+XKzRVX4MV8FH8PX/X9GtTxti7YHr3ObAN/py2KZEwGxui5UQsHxtszIFngWVa2xqTyX1Y6sfXO4Lbx+IBPFqJwQhSLBjNXwDMJG5UrNbRX9/gUY3elsvIs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249312; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DX46uaUVEZ4Q/jGQoG6en7oJG1cfP+lGPydwFve/Hp0=; b=Vfx1CkQ6rSsjbUOMeqVSaUpooN34p2IR5dqgvcSMnf2xJTnqVFFStPvd6Y3Aub5r5nyRdDbIa45YEo28TDeBm3XVTAjLPdgPlMxakpwy70p+G4Z8BcY/49Fz71bwOwp6cw98BUhNhcu1ZtI29Mxknd/qG+6qf1BIPLxn7eMP91I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249312385126.38416854343075; Thu, 4 May 2023 18:15:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujwx-0002vN-QT; Thu, 04 May 2023 21:09:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujvp-0001i3-Px for qemu-devel@nongnu.org; Thu, 04 May 2023 21:08:31 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujvn-0008Aa-SV for qemu-devel@nongnu.org; Thu, 04 May 2023 21:08:21 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-6439f186366so104921b3a.2 for ; Thu, 04 May 2023 18:08:13 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.08.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:08:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248892; x=1685840892; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DX46uaUVEZ4Q/jGQoG6en7oJG1cfP+lGPydwFve/Hp0=; b=e7LrWxG7Hup42TrP2AN4QCloJ3T4uET+MQwXzTZbgyIx2TE17FGpydKURTx3UatxAd FePk02qkm8seSz/S1PtTtwoulZDCz9Ui3enINl0o9RiIC2vseIlMUmR5xAnxQ2G6thF4 WyIMi2N7NDAhBM1VgPXs8LM1n3ovdeZTjMFRoFwrbLqh10fV6O5Ip3imvwo1LLWfLBhY KtAcoi9VBlctXmxYhaofUZGc/OKSx4HpjM7mqoZUVAuvyy4RP9VFbsckUdCFArRUqmrD SFleZmTf6aSSV4ii+7mpkZtjDF0yjMLobnHUnpeq5jXKA9EIWgyFcQOtdb3J+jlJozEh vAnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248892; x=1685840892; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DX46uaUVEZ4Q/jGQoG6en7oJG1cfP+lGPydwFve/Hp0=; b=bqvKuARpqa/mZoOOUEWysYTQOEd0EOm1H/e8dBN1d1xYr8C1TYVP/feXmC9hMJfYQ0 a8SnsxIsBYyT4e7wHYSW6G+Zo0FPV8AiGgIEaaXLI47gpoPL5n1eXSy+WZGyFSj/ZTp3 CECnU+itsUR+NpqBT9Z3yvjA1wOjvWvBA9HKMad3zq6u7I3pvOxQujlBkUl81iOELZhd vmsOORPuIzikywIqAC3QHaGji1yrriYDsR7BAvAnkcyRVbpGwv3hAwJ7Br5ZLbC4Vg/k SlRyc+A4molzon7fAAhI40mRDvDjxuhaYrS5oF82oiO9xiLtrV33qoNrZvcKrKVJIH9z XE9Q== X-Gm-Message-State: AC+VfDyUcX5/u1mTcjPdMuD04faM92RcOCCAIuEgCGgo83iZFoiO1+Fo OfEiTMAkatBggsy257WXeQb1hNw+3p1/nA== X-Google-Smtp-Source: ACHHUZ6dK6L17vRm4DJa2cmgM5y7tE9ZdU6M8BJUwnuUu7xB5nqFTHF/AHZhQk2tbgEwNzIZfQX3Jw== X-Received: by 2002:a17:902:ecc8:b0:1a6:4127:857 with SMTP id a8-20020a170902ecc800b001a641270857mr6259510plh.5.1683248892223; Thu, 04 May 2023 18:08:12 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Richard Henderson , Alistair Francis Subject: [PULL 85/89] target/riscv: add TYPE_RISCV_DYNAMIC_CPU Date: Fri, 5 May 2023 11:02:37 +1000 Message-Id: <20230505010241.21812-86-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249312713100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza This new abstract type will be used to differentiate between static and non-static CPUs in query-cpu-definitions. All generic CPUs were changed to be of this type. Named CPUs are kept as TYPE_RISCV_CPU and will still be considered static. This is the output of query-cpu-definitions after this change for the riscv64 target: $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio {"QMP": {"version": (...)} {"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}} {"return": {}} {"execute": "query-cpu-definitions"} {"return": [ {"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated= ": false}, {"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": true, = "deprecated": false}, {"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated":= false}, {"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "depr= ecated": false}, {"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": true, "dep= recated": false}, {"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": true, = "deprecated": false}, {"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": true, = "deprecated": false} ]} Suggested-by: Richard Henderson Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Reviewed-by: Richard Henderson Message-Id: <20230411183511.189632-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu-qom.h | 2 +- target/riscv/cpu.c | 20 ++++++++++++++++---- target/riscv/riscv-qmp-cmds.c | 4 ++++ 3 files changed, 21 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index b9318e0783..b29090ad86 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -23,6 +23,7 @@ #include "qom/object.h" =20 #define TYPE_RISCV_CPU "riscv-cpu" +#define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu" =20 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) @@ -66,5 +67,4 @@ struct RISCVCPUClass { DeviceRealize parent_realize; ResettablePhases parent_phases; }; - #endif /* RISCV_CPU_QOM_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 32c04214a1..befa64528f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1788,6 +1788,13 @@ void riscv_cpu_list(void) .instance_init =3D initfn \ } =20 +#define DEFINE_DYNAMIC_CPU(type_name, initfn) \ + { \ + .name =3D type_name, \ + .parent =3D TYPE_RISCV_DYNAMIC_CPU, \ + .instance_init =3D initfn \ + } + static const TypeInfo riscv_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_CPU, @@ -1799,23 +1806,28 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .class_size =3D sizeof(RISCVCPUClass), .class_init =3D riscv_cpu_class_init, }, - DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), + { + .name =3D TYPE_RISCV_DYNAMIC_CPU, + .parent =3D TYPE_RISCV_CPU, + .abstract =3D true, + }, + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), #if defined(CONFIG_KVM) DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), #endif #if defined(TARGET_RISCV32) - DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init= ), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), #elif defined(TARGET_RISCV64) - DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), #endif }; =20 diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c index 128677add9..5ecff1afb3 100644 --- a/target/riscv/riscv-qmp-cmds.c +++ b/target/riscv/riscv-qmp-cmds.c @@ -33,11 +33,15 @@ static void riscv_cpu_add_definition(gpointer data, gpo= inter user_data) CpuDefinitionInfoList **cpu_list =3D user_data; CpuDefinitionInfo *info =3D g_malloc0(sizeof(*info)); const char *typename =3D object_class_get_name(oc); + ObjectClass *dyn_class; =20 info->name =3D g_strndup(typename, strlen(typename) - strlen("-" TYPE_RISCV_CPU)); info->q_typename =3D g_strdup(typename); =20 + dyn_class =3D object_class_dynamic_cast(oc, TYPE_RISCV_DYNAMIC_CPU); + info->q_static =3D dyn_class =3D=3D NULL; + QAPI_LIST_PREPEND(*cpu_list, info); } =20 --=20 2.40.0 From nobody Sat May 18 12:30:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.08.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:08:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248896; x=1685840896; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qnaDtYju5dqRq5XZLlBygStOKuvR4eRJ5p4wSfjTUvM=; b=rGNExJN/yZHKP4GKj+Hs48ry5PeT4g97hqDhL8nmcac06mGlvQDeI3HNpTNHUWrLed Kv0izyGEOommvES7nTqqjb7IXC5OoKRwdm1ifie1qQCS3l1/hq5MHF/fobW+eUR3bZLg 2GE91FUSqEyY2vw4xvoNIzw2pulcqwlkTasj+YT/eGbIB/BnQcHaKWXUCZjfL7jsdLjf 3M3Ufr9STddeCyDGIg/LB+wyYCrxy7Orh4xveaOvm8N5Mm3K/jzEzCwR1Fd8ZjFMpU0g AJF6YYoEDfrt/fHA/g77sKJr8fIpvkAQ99VGGpuN+WeDftcMHbTpHNdsUSsQU0/zXtfF BEPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248896; x=1685840896; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qnaDtYju5dqRq5XZLlBygStOKuvR4eRJ5p4wSfjTUvM=; b=Ga4ldch3szXjP82Nqm3IeNflgJeUziQngPfOxXs7CKtiNKioKMaPDrYVnTM5LqLeMa x2Yra+W86SIxY+AOHAQCvORoCSCabvHfM61x48NpMzplJ+BSR8o54CbRMqESmU+G66C6 Zw0YGuo885L/sfcjix4izdBSsj+m5WzJG9L1LMMKEjz1wJvywgnFqGtW7u7iJh5udIEf W2crp7eCuBe7kBoPZHQxGSqmkGvaa3bx738RmUaD3/RsShehbh3jHY/JaT0Okw94Ew8y yK0qGOPt2Nl0AIvvlnNeW9DoeVR6nvWHKKKY5UeJG+qELZXGcVdk4ogh1wxiVJ9OTmZm 2ANg== X-Gm-Message-State: AC+VfDy/t3B2rW3ikeRDurRYOpff3VCMPRTHPKTWOiEbVM7iHCyh3iXb UiVav87Ur475Ca6BZYGwvu0A+T5Q4Es+wA== X-Google-Smtp-Source: ACHHUZ5y5AMiQk5ddxl8g3qaROfAJv+H64m8mfVR8Ds5IeCwY4BM9JF1icZVLBvXTeLD0D6dznXtLA== X-Received: by 2002:a17:902:c403:b0:1a6:a8e5:9240 with SMTP id k3-20020a170902c40300b001a6a8e59240mr7098291plk.4.1683248896391; Thu, 04 May 2023 18:08:16 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Fei Wu , Daniel Henrique Barboza , Weiwei Li , Alistair Francis , LIU Zhiwei Subject: [PULL 86/89] target/riscv: Restore the predicate() NULL check behavior Date: Fri, 5 May 2023 11:02:38 +1000 Message-Id: <20230505010241.21812-87-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=alistair23@gmail.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249407227100003 Content-Type: text/plain; charset="utf-8" From: Bin Meng When reading a non-existent CSR QEMU should raise illegal instruction exception, but currently it just exits due to the g_assert() check. This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617. Some comments are also added to indicate that predicate() must be provided for an implemented CSR. Reported-by: Fei Wu Signed-off-by: Bin Meng Reviewed-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Message-Id: <20230417043054.3125614-1-bmeng@tinylab.org> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 865ee9efda..4451bd1263 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3826,6 +3826,11 @@ static inline RISCVException riscv_csrrw_check(CPURI= SCVState *env, return RISCV_EXCP_ILLEGAL_INST; } =20 + /* ensure CSR is implemented by checking predicate */ + if (!csr_ops[csrno].predicate) { + return RISCV_EXCP_ILLEGAL_INST; + } + /* privileged spec version check */ if (env->priv_ver < csr_min_priv) { return RISCV_EXCP_ILLEGAL_INST; @@ -3843,7 +3848,6 @@ static inline RISCVException riscv_csrrw_check(CPURIS= CVState *env, * illegal instruction exception should be triggered instead of virtual * instruction exception. Hence this comes after the read / write chec= k. */ - g_assert(csr_ops[csrno].predicate !=3D NULL); RISCVException ret =3D csr_ops[csrno].predicate(env, csrno); if (ret !=3D RISCV_EXCP_NONE) { return ret; @@ -4032,7 +4036,10 @@ static RISCVException write_jvt(CPURISCVState *env, = int csrno, return RISCV_EXCP_NONE; } =20 -/* Control and Status Register function table */ +/* + * Control and Status Register function table + * riscv_csr_operations::predicate() must be provided for an implemented C= SR + */ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* User Floating-Point CSRs */ [CSR_FFLAGS] =3D { "fflags", fs, read_fflags, write_fflags }, --=20 2.40.0 From nobody Sat May 18 12:30:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249380; cv=none; d=zohomail.com; s=zohoarc; b=ahB7d3hiymZK0g46UlS9qiGArUy4E6PSi11W8plqSNmd2PL217xWARu1TerpQbJB3NXbqEvm9ryogTE9tDdymf5KwmAG9ttV2jrx+2RwiipoGHPaQEQWcyIn/9Orzx/1SiST8c4NQrh9+whh63N8RSEb7ZSELAhY3j7hiae/RDA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249380; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Jux+pPZw9jHjtOgyIueCriqpmKTHI9+buEKuL9Hw4r4=; b=V0n4zRaLvmKHTNJx9eH7H/MzNQU5LrNu1xwuR4sVeSA4zA//wkX9A5qOa4R1uJr4uqTHXk0/zDxWPjGa4Uz4bltlP0VUUWNk0/Y2hnNLG0XTm+p4R2134iDamQPvrtXc1xXuSQaHzlUg8zghAlf0ADcCYE/prrOeUNYsthVajcU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249380763263.25863598880596; Thu, 4 May 2023 18:16:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujx5-0003Cj-DA; Thu, 04 May 2023 21:09:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujvr-0001nO-Hg for qemu-devel@nongnu.org; Thu, 04 May 2023 21:08:31 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujvp-0008Bu-Da for qemu-devel@nongnu.org; Thu, 04 May 2023 21:08:23 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1ab05018381so10726245ad.2 for ; Thu, 04 May 2023 18:08:20 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.08.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:08:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248899; x=1685840899; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Jux+pPZw9jHjtOgyIueCriqpmKTHI9+buEKuL9Hw4r4=; b=EhTqNku/2G6FS97roeLBmC54akODI9/uirbhfVSivXVVUt6VLFqQSv9bxibSN/5tBb /eeM4yusxzP2se40baAe+aqBTEoErDj99vOJWNsO577mz9gZ/Scc9KnbwL6lYDH63uqv o+nGWm20ulCFtgC7tZRX3NIm50JoHCGX8jMZhAeTAdTTG4hult74Tj6J5+0pP6q+DpJI PtHIkN2LYYpL4Z+9TO6SoPJDMDuOS+esar/GM3eMhfcd2h0TQSLu2O2KMky3ktVd6h6z 5e7uD17mmzoEmGoAjYilNgkxln6t7wfEucwVbtIdGphl+GnmPl5sB+XZYGED8GnXcZXZ MvNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248899; x=1685840899; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Jux+pPZw9jHjtOgyIueCriqpmKTHI9+buEKuL9Hw4r4=; b=joBfUm709S9mWPoRIxBP/wAHNQnyWTWmdnqzxWBJ5Vkf4Rt3VtbHzplahyiMtSr4Os dTiKjdJF3LBn6YuqOxF7ogEN2wD+NtOXyPHogjLgeb1Fz0PCJrzRD5eqsayCoRMqDMMS wfmlu8jvg2/qeTuZnNglvuq8BEAQ/se6nfFF5PrDa/GhXP1xgFBix13YCg657+iBsnUW zFIsQd+qqLk1V2tvlRsq3SXd6ceJxA8YJ3ej4+mfX3eYD26MSzCEjlPyXweKbj2fGigi kAovdcKlCcBqFZET6pdJhs1RUOBSvnrOtIgsZSBuhWX9JW0SW1dBQAOiKWsu0zgvUfxA k2Bw== X-Gm-Message-State: AC+VfDyKy3H/3YqnISWmDcLjED4fnVwv4X/hNTL2IBP9oS1nygwyuyUn 4oucPEjxhHZvnNL70IDZ/BTpBonW7gWIzQ== X-Google-Smtp-Source: ACHHUZ4wuVtC1Zv2rOyYUfVT6cY6SlFHYseWpJHbHtNQT3eV6cfFmNtWJhXUmPIVSL47X+BT8JrHqg== X-Received: by 2002:a17:902:e5cf:b0:1a9:8ba4:d0e3 with SMTP id u15-20020a170902e5cf00b001a98ba4d0e3mr5864858plf.59.1683248899585; Thu, 04 May 2023 18:08:19 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Irina Ryapolova , Weiwei Li , Alistair Francis Subject: [PULL 87/89] target/riscv: Fix Guest Physical Address Translation Date: Fri, 5 May 2023 11:02:39 +1000 Message-Id: <20230505010241.21812-88-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=alistair23@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249381361100005 From: Irina Ryapolova Before changing the flow check for sv39/48/57. According to specification (for Supervisor mode): Sv39 implementations support a 39-bit virtual address space, divided into 4= KiB pages. Instruction fetch addresses and load and store effective addresses, which a= re 64 bits, must have bits 63=E2=80=9339 all equal to bit 38, or else a page-fault exce= ption will occur. Likewise for Sv48 and Sv57. So the high bits are equal to bit 38 for sv39. According to specification (for Hypervisor mode): For Sv39x4, address bits of the guest physical address 63:41 must all be ze= ros, or else a guest-page-fault exception occurs. Likewise for Sv48x4 and Sv57x4. For Sv48x4 address bits 63:50 must all be zeros, or else a guest-page-fault exception occurs. For Sv57x4 address bits 63:59 must all be zeros, or else a guest-page-fault exception occurs. For example we are trying to access address 0xffff_ffff_ff01_0000 with only G-translation enabled. So expected behavior is to generate exception. But qemu doesn't generate su= ch exception. For the old check, we get va_bits =3D=3D 41, mask =3D=3D (1 << 24) - 1, masked_msbs =3D=3D (0xffff_ff= ff_ff01_0000 >> 40) & mask =3D=3D mask. Accordingly, the condition masked_msbs !=3D 0 && masked_msbs !=3D mask is n= ot fulfilled and the check passes. Signed-off-by: Irina Ryapolova Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230418075423.26217-1-irina.ryapolova@syntacore.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 32a65f8007..b68dcfe7b6 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -837,17 +837,24 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, =20 CPUState *cs =3D env_cpu(env); int va_bits =3D PGSHIFT + levels * ptidxbits + widened; - target_ulong mask, masked_msbs; =20 - if (TARGET_LONG_BITS > (va_bits - 1)) { - mask =3D (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; - } else { - mask =3D 0; - } - masked_msbs =3D (addr >> (va_bits - 1)) & mask; + if (first_stage =3D=3D true) { + target_ulong mask, masked_msbs; =20 - if (masked_msbs !=3D 0 && masked_msbs !=3D mask) { - return TRANSLATE_FAIL; + if (TARGET_LONG_BITS > (va_bits - 1)) { + mask =3D (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; + } else { + mask =3D 0; + } + masked_msbs =3D (addr >> (va_bits - 1)) & mask; + + if (masked_msbs !=3D 0 && masked_msbs !=3D mask) { + return TRANSLATE_FAIL; + } + } else { + if (vm !=3D VM_1_10_SV32 && addr >> va_bits !=3D 0) { + return TRANSLATE_FAIL; + } } =20 bool pbmte =3D env->menvcfg & MENVCFG_PBMTE; --=20 2.40.0 From nobody Sat May 18 12:30:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249395; cv=none; d=zohomail.com; s=zohoarc; b=helPAUiG7W+gnThhcbx6Ilo5IFeoUvgwGE9RJedlikWwfjLonQINtwdz55DEwhF34S795Sg9UlNppWNY0VMRjp9sLoA68PyVuyfWmyvJjpkNNHoOP53EJWF6vEg1fKcLMenSwmMv5mUYMrHyslHmiLX15ZOTJexCpHG48QvjfSU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249395; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dAJxr69P9cXB/f/vPwh/m0VROIZUDkM1KS0tTkeyl0s=; b=LKS/NE7oL2fHpOriVU73dZ8j8yLMlpaiwrFmMBaFm13f7nY30cxKS3S6rIajlxuHwMb4PtfXLWrlr3CdBPn10SS5nEbK3+RGapSlYQbeg2B9XiCWFSRc7lxyDzlWBXmEJk+RRafhL4Qd4Dg259KcAR7CgBdbepUGQqoi75dDjDQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249395307861.4228696066511; Thu, 4 May 2023 18:16:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujx8-0003GO-8O; Thu, 04 May 2023 21:09:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujvz-0001zf-83 for qemu-devel@nongnu.org; Thu, 04 May 2023 21:08:35 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujvs-0008E1-Hv for qemu-devel@nongnu.org; Thu, 04 May 2023 21:08:25 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1ab1ce53ca6so8573315ad.0 for ; Thu, 04 May 2023 18:08:24 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.08.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:08:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248903; x=1685840903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dAJxr69P9cXB/f/vPwh/m0VROIZUDkM1KS0tTkeyl0s=; b=j23oE5NLGc6wUeE6UqsmX3xxxZsD6KXCndmhK+SUYodVQ333OCd+97G8zIfgTdOcRw kXzU85GAZce1GlgoT/ozxtr4NIQqCXR8H/BRNFVixHBiGe25EeccpUpgHg6V04hRWQNd HL7rfmX7SUxxy+fVvq3zgn9OeMDgn5Is6hP1XBrrMZL8Mqi8PV2reOaS/jL23Fq8ghBJ cUx12/wqe90ceFpBq1M33+A3eMTDg9qpUJiAOiQ0I7lT5F6mGIHWa5psGT3+Lba3voE/ YDy7zxQj2sgI9/u6m2zmRVqw+cO3IkpZD9r7BjiTOvN4lgnkXETpL05bRTPTTLts+RLg 726Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248903; x=1685840903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dAJxr69P9cXB/f/vPwh/m0VROIZUDkM1KS0tTkeyl0s=; b=KtzqgOWOl1gy2w3Mq568/YdrG6ujVeQRhO/5wGLQPI33PPi4dJXNK6VDE1N6ukFIma WxwELolasOPiCaiP2kLACsHoh/LuCCy6D7+VU7iInt3PfvvLNAjL8bHFiiRLbg2yvfTY F5Pk91wSd/ZgCBEDKhQVTN98CYQPqXj3wxdMLCBW5MpdGzMYmiEY6/oQRbOgf0p0Nqv+ zc6/tj4mT+bFcyfSNMV+issWFHe25wHbSVoqclZKdPRsWdv8qNpP7VdW0fGuBctkLMK9 tSzIaNKO9VbFXGUoIqZoH5hDdzUcMsi336fE82O2Z8VtaX6aU+kSIXn8pwUxHh8YT6xi 5ptQ== X-Gm-Message-State: AC+VfDxghLD02V7hFqaDnN1EqaUMJ3WXOawhnsWgoW5K0P/a71DbNBjp OVaYFhECL12qZ5XXPxQH5Xqgat5GkYQvnw== X-Google-Smtp-Source: ACHHUZ7dJcEDIafY8xpW2eblia2nIL2Wdh83oHRKDikWUxyen3EP7rcgs8+/eEZQ5bvJ3XxeVbRNyQ== X-Received: by 2002:a17:902:e883:b0:1ab:a30:c89d with SMTP id w3-20020a170902e88300b001ab0a30c89dmr7066860plg.51.1683248902925; Thu, 04 May 2023 18:08:22 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alexandre Ghiti , Andrea Parri , Alistair Francis Subject: [PULL 88/89] riscv: Make sure an exception is raised if a pte is malformed Date: Fri, 5 May 2023 11:02:40 +1000 Message-Id: <20230505010241.21812-89-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=alistair23@gmail.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249396461100015 Content-Type: text/plain; charset="utf-8" From: Alexandre Ghiti As per the specification, in 64-bit, if any of the pte reserved bits 60-54 is set an exception should be triggered (see 4.4.1, "Addressing and Memory Protection"). In addition, we must check the napot/pbmt bits are not set if those extensions are not active. Reported-by: Andrea Parri Signed-off-by: Alexandre Ghiti Reviewed-by: Alistair Francis Message-Id: <20230420150220.60919-1-alexghiti@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 15 +++++++++++---- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index fb63b8e125..59f0ffd9e1 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -644,6 +644,7 @@ typedef enum { #define PTE_SOFT 0x300 /* Reserved for Software */ #define PTE_PBMT 0x6000000000000000ULL /* Page-based memory typ= es */ #define PTE_N 0x8000000000000000ULL /* NAPOT translation */ +#define PTE_RESERVED 0x1FC0000000000000ULL /* Reserved bits */ #define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */ =20 /* Page table PPN shift amount */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b68dcfe7b6..57d04385f1 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -927,13 +927,20 @@ restart: =20 if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { ppn =3D pte >> PTE_PPN_SHIFT; - } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) { - ppn =3D (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; } else { - ppn =3D pte >> PTE_PPN_SHIFT; - if ((pte & ~(target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT) { + if (pte & PTE_RESERVED) { + return TRANSLATE_FAIL; + } + + if (!pbmte && (pte & PTE_PBMT)) { return TRANSLATE_FAIL; } + + if (!riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { + return TRANSLATE_FAIL; + } + + ppn =3D (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; } =20 if (!(pte & PTE_V)) { --=20 2.40.0 From nobody Sat May 18 12:30:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1683249138; cv=none; d=zohomail.com; s=zohoarc; b=m16E3cMv9lWcxHE8epNwaf4pvy4FxlyNeK5HmyF7X6ZIJj6AbniccgyS1Qsk1eleu4Kb0E305NTkDP+fb4G6iS8+JwRSil8fnt3/IRopsj/mgIZMA+c2AysPSeNG9NpczKH6aukxZsac9R5Mu8HkMIqbjp6RnJShhLvRWZHrPqg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1683249138; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WQmY7ILKe0W+JeOW0qS6RjqCim/5IbGU6lDV+NmnA70=; b=RYQ2CqTSfVWKb3x+fcFp6HQN1BIie1thJ8IY9MaXslPFI9kDM+vewoxu3q+Hiec7GBlmK+hZBPJ+KoPzCl0e0smUCy/7ATjBQDBmN4JWN0GDVKfZA187x/4XBUSdL04gNciGQst6Qu7a+J2+Fzdx18I9FYrpTED6trXIxOOgDqI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1683249138929884.8074894331479; Thu, 4 May 2023 18:12:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pujx9-0003S2-Pd; Thu, 04 May 2023 21:09:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pujw3-000222-QO for qemu-devel@nongnu.org; Thu, 04 May 2023 21:08:37 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pujvx-0008EP-9g for qemu-devel@nongnu.org; Thu, 04 May 2023 21:08:32 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1ab1b79d3a7so8013925ad.3 for ; Thu, 04 May 2023 18:08:27 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.08.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:08:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683248906; x=1685840906; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WQmY7ILKe0W+JeOW0qS6RjqCim/5IbGU6lDV+NmnA70=; b=Cw6EAwCCxe07eFeRyAmd5h9t4EzNtFJGRPRSVHIXY3Uq9xeWx6aKtam2pJL/JBcLZw g5R9pgSPQPSEBATzlPV76+qzxT+ZP/S8manW5POJHe6OdxkJLAF8lg163U0PE654dvuA QT4Ks9wljnmkfXKmtL8RI1PJVhBPmzZ10KDF6YOJu1ZJCuOpUbFj9BivOXYkHUTfJJof XqJBMuTys1FjLRJXmmfLCXfrTYoz1Jc6qb9xngH1datUsI5SFYQ8a0nTdKpeu7Fl7zo5 7Chmq709CRQSOxZFLNmdUQkHZaWsJPNLBpsZ2bUznnAe/5XOVZo1/UwPgLcpM5IyxYkA NL7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683248906; x=1685840906; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WQmY7ILKe0W+JeOW0qS6RjqCim/5IbGU6lDV+NmnA70=; b=KQuJp4BKPsFd+OoPzLftk5uSMTsC0COR0Uvos2A1jAA0l1c+oUO+CQlVmwsp2Agluc 7v1VLa9aDVyPiPFJhdxK0fJYOj3aUYu7esni3V2UKYWOdtE/69XugYWsJOc1zgg4gauM I4jNM58j2dM2fAWm/Q05j+Rwg3Qo8eU0P/dZlqut/TI1d53tNPztEfhRexz6TXQuBhJY 1mvm7N429XAFm5zKcSteSa+TSaFBWbqBlfAj0qHxDS0YZXtwmy50qW/ftvKwq904eROK i0tuZVYoPUOwolTNjsLV8LK/uMCg9VxSVumdmbPgdlWJTxPah8D7IQTEoutSz74KoKuY Cotw== X-Gm-Message-State: AC+VfDwSd8Un7R842iGdxTYcQAB1so1ThytEtkIZxHvQeYEPtULi2zIF 5SIbpVVWLvgPoroXK5MmE9pP1BgltYDVwA== X-Google-Smtp-Source: ACHHUZ7HpR6W7n2mR/nax9zpn2WN5RcajnvzV8HQuRvcJP+eYRi1XhOq9t4KNldsSR7b4FLzl2qEHQ== X-Received: by 2002:a17:902:aa06:b0:1a6:7a19:331b with SMTP id be6-20020a170902aa0600b001a67a19331bmr4709536plb.5.1683248906425; Thu, 04 May 2023 18:08:26 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Rahul Pathak , Mayuresh Chitale , Daniel Henrique Barboza , Alistair Francis Subject: [PULL 89/89] target/riscv: add Ventana's Veyron V1 CPU Date: Fri, 5 May 2023 11:02:41 +1000 Message-Id: <20230505010241.21812-90-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=alistair23@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1683249139535100007 Content-Type: text/plain; charset="utf-8" From: Rahul Pathak Add a virtual CPU for Ventana's first CPU named veyron-v1. It runs exclusively for the rv64 target. It's tested with the 'virt' board. CPU specs and general information can be found here: https://www.nextplatform.com/2023/02/02/the-first-risc-v-shot-across-the-da= tacenter-bow/ Signed-off-by: Rahul Pathak Signed-off-by: Mayuresh Chitale Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-Id: <20230418123624.16414-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu_vendorid.h | 4 ++++ target/riscv/cpu.c | 38 +++++++++++++++++++++++++++++++++++++ 3 files changed, 43 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index b29090ad86..04af50983e 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -41,6 +41,7 @@ #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") +#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") =20 #if defined(TARGET_RISCV32) diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h index a5aa249bc9..96b6b9c2cb 100644 --- a/target/riscv/cpu_vendorid.h +++ b/target/riscv/cpu_vendorid.h @@ -3,4 +3,8 @@ =20 #define THEAD_VENDOR_ID 0x5b7 =20 +#define VEYRON_V1_MARCHID 0x8000000000010000 +#define VEYRON_V1_MIMPID 0x111 +#define VEYRON_V1_MVENDORID 0x61f + #endif /* TARGET_RISCV_CPU_VENDORID_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index befa64528f..db0875fb43 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -422,6 +422,43 @@ static void rv64_thead_c906_cpu_init(Object *obj) #endif } =20 +static void rv64_veyron_v1_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + + set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); + env->priv_ver =3D PRIV_VERSION_1_12_0; + + /* Enable ISA extensions */ + cpu->cfg.mmu =3D true; + cpu->cfg.ext_icbom =3D true; + cpu->cfg.cbom_blocksize =3D 64; + cpu->cfg.cboz_blocksize =3D 64; + cpu->cfg.ext_icboz =3D true; + cpu->cfg.ext_smaia =3D true; + cpu->cfg.ext_ssaia =3D true; + cpu->cfg.ext_sscofpmf =3D true; + cpu->cfg.ext_sstc =3D true; + cpu->cfg.ext_svinval =3D true; + cpu->cfg.ext_svnapot =3D true; + cpu->cfg.ext_svpbmt =3D true; + cpu->cfg.ext_smstateen =3D true; + cpu->cfg.ext_zba =3D true; + cpu->cfg.ext_zbb =3D true; + cpu->cfg.ext_zbc =3D true; + cpu->cfg.ext_zbs =3D true; + cpu->cfg.ext_XVentanaCondOps =3D true; + + cpu->cfg.mvendorid =3D VEYRON_V1_MVENDORID; + cpu->cfg.marchid =3D VEYRON_V1_MARCHID; + cpu->cfg.mimpid =3D VEYRON_V1_MIMPID; + +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_SV48); +#endif +} + static void rv128_base_cpu_init(Object *obj) { if (qemu_tcg_mttcg_enabled()) { @@ -1827,6 +1864,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), #endif }; --=20 2.40.0