Hi,
This series adds LoongArch LSX instructions.
About test:
V2 we use RISU test the LoongArch LSX instructions.
QEMU:
https://github.com/loongson/qemu/tree/tcg-old-abi-support-lsx
RISU:
https://github.com/loongson/risu/tree/loongarch-suport-lsx
Build test:
make docker-test-build@fedora-i386-cross
V5:
- R-b and rebase;
- vld/vst{x} Memop = MO_128 | MO_TE.
V4:
- R-b and rebase;
- Migrate the upper half lsx regs;
- Remove tcg_gen_mulus2_*;
- Vsetallnez use !do_match2;
- Use tcg_gen_concat_i64_i128/tcg_gen_extr_i128_i64 to replace
TCGV128_LOW(val)/TCGV128_High(val);
V3:
- R-b;
- Add unsigned data type in vreg;
- Add ctx->vl;
- Use tcg_constant_vec_matching instead of dupi;
- Use __typeof(Vd->E(0)) instead of the output type;
- Tcg integer expansion;
- Use tcg_gen_qemu_ld/st_i128 to implement vld/vst;
- Fix some typos;
- Optimize code based on Richard's comments.
V2:
- Use gvec;
- Fix instructions bugs;
- Add set_fpr()/get_fpr() replace to cpu_fpr.
Song Gao (44):
target/loongarch: Add LSX data type VReg
target/loongarch: meson.build support build LSX
target/loongarch: Add CHECK_SXE maccro for check LSX enable
target/loongarch: Implement vadd/vsub
target/loongarch: Implement vaddi/vsubi
target/loongarch: Implement vneg
target/loongarch: Implement vsadd/vssub
target/loongarch: Implement vhaddw/vhsubw
target/loongarch: Implement vaddw/vsubw
target/loongarch: Implement vavg/vavgr
target/loongarch: Implement vabsd
target/loongarch: Implement vadda
target/loongarch: Implement vmax/vmin
target/loongarch: Implement vmul/vmuh/vmulw{ev/od}
target/loongarch: Implement vmadd/vmsub/vmaddw{ev/od}
target/loongarch: Implement vdiv/vmod
target/loongarch: Implement vsat
target/loongarch: Implement vexth
target/loongarch: Implement vsigncov
target/loongarch: Implement vmskltz/vmskgez/vmsknz
target/loongarch: Implement LSX logic instructions
target/loongarch: Implement vsll vsrl vsra vrotr
target/loongarch: Implement vsllwil vextl
target/loongarch: Implement vsrlr vsrar
target/loongarch: Implement vsrln vsran
target/loongarch: Implement vsrlrn vsrarn
target/loongarch: Implement vssrln vssran
target/loongarch: Implement vssrlrn vssrarn
target/loongarch: Implement vclo vclz
target/loongarch: Implement vpcnt
target/loongarch: Implement vbitclr vbitset vbitrev
target/loongarch: Implement vfrstp
target/loongarch: Implement LSX fpu arith instructions
target/loongarch: Implement LSX fpu fcvt instructions
target/loongarch: Implement vseq vsle vslt
target/loongarch: Implement vfcmp
target/loongarch: Implement vbitsel vset
target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vr
target/loongarch: Implement vreplve vpack vpick
target/loongarch: Implement vilvl vilvh vextrins vshuf
target/loongarch: Implement vld vst
target/loongarch: Implement vldi
target/loongarch: Use {set/get}_gpr replace to cpu_fpr
target/loongarch: CPUCFG support LSX
linux-user/loongarch64/signal.c | 4 +-
target/loongarch/cpu.c | 5 +-
target/loongarch/cpu.h | 27 +-
target/loongarch/disas.c | 911 ++++
target/loongarch/fpu_helper.c | 2 +-
target/loongarch/gdbstub.c | 4 +-
target/loongarch/helper.h | 566 +++
.../loongarch/insn_trans/trans_farith.c.inc | 72 +-
target/loongarch/insn_trans/trans_fcmp.c.inc | 12 +-
.../loongarch/insn_trans/trans_fmemory.c.inc | 37 +-
target/loongarch/insn_trans/trans_fmov.c.inc | 31 +-
target/loongarch/insn_trans/trans_lsx.c.inc | 4400 +++++++++++++++++
target/loongarch/insns.decode | 811 +++
target/loongarch/internals.h | 23 +
target/loongarch/lsx_helper.c | 3004 +++++++++++
target/loongarch/machine.c | 79 +-
target/loongarch/meson.build | 1 +
target/loongarch/translate.c | 55 +-
target/loongarch/translate.h | 1 +
19 files changed, 9988 insertions(+), 57 deletions(-)
create mode 100644 target/loongarch/insn_trans/trans_lsx.c.inc
create mode 100644 target/loongarch/lsx_helper.c
--
2.31.1