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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=richard.purdie@linuxfoundation.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.161, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linuxfoundation.org) X-ZM-MESSAGEID: 1683198224671100001 Content-Type: text/plain; charset="utf-8" The following commits changed the code such that these instructions became = invalid on pre 3.0 ISAs: bf8adfd88b547680aa857c46098f3a1e94373160 - target/ppc: Move mffscrn[i] to= decodetree 394c2e2fda70da722f20fb60412d6c0ca4bfaa03 - target/ppc: Move mffsce to dec= odetree 3e5bce70efe6bd1f684efbb21fd2a316cbf0657e - target/ppc: Move mffsl to deco= detree The hardware will handle them as a MFFS instruction as the code did previou= sly. Restore that behaviour. This means applications that were segfaulting under= qemu when encountering these instructions now operate correctly. The instruction is used in glibc libm functions for example. Signed-off-by: Richard Purdie --- target/ppc/translate/fp-impl.c.inc | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-i= mpl.c.inc index 57d8437851..cb86381c3f 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -584,7 +584,10 @@ static bool trans_MFFSCE(DisasContext *ctx, arg_X_t *a) { TCGv_i64 fpscr; =20 - REQUIRE_INSNS_FLAGS2(ctx, ISA300); + if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { + return trans_MFFS(ctx, a); + } + REQUIRE_FPU(ctx); =20 gen_reset_fpstatus(); @@ -597,7 +600,10 @@ static bool trans_MFFSCRN(DisasContext *ctx, arg_X_tb = *a) { TCGv_i64 t1, fpscr; =20 - REQUIRE_INSNS_FLAGS2(ctx, ISA300); + if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { + return trans_MFFS(ctx, a); + } + REQUIRE_FPU(ctx); =20 t1 =3D tcg_temp_new_i64(); @@ -631,7 +637,10 @@ static bool trans_MFFSCRNI(DisasContext *ctx, arg_X_im= m2 *a) { TCGv_i64 t1, fpscr; =20 - REQUIRE_INSNS_FLAGS2(ctx, ISA300); + if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { + return trans_MFFS(ctx, a); + } + REQUIRE_FPU(ctx); =20 t1 =3D tcg_temp_new_i64(); @@ -661,7 +670,10 @@ static bool trans_MFFSCDRNI(DisasContext *ctx, arg_X_i= mm3 *a) =20 static bool trans_MFFSL(DisasContext *ctx, arg_X_t *a) { - REQUIRE_INSNS_FLAGS2(ctx, ISA300); + if (unlikely(!(ctx->insns_flags2 & PPC2_ISA300))) { + return trans_MFFS(ctx, a); + } + REQUIRE_FPU(ctx); =20 gen_reset_fpstatus();