On 5/3/23 05:56, Richard Henderson wrote:
> Based-on: 20230503070656.1746170-1-richard.henderson@linaro.org
> ("[PATCH v4 00/57] tcg: Improve atomicity support")
>
> I've been vaguely following the __hw_probe syscall progress
> in the upstream kernel. The initial version only handled
> bog standard F+D and C extensions, which everything expects
> to be present anyway, which was disappointing. But at least
> the basis is there for proper extensions.
>
> In the meantime, probe via sigill. Tested with qemu-on-qemu.
> I understand the Ventana core has all of these, if you'd be
> so kind as to test.
I'll run this series with upstream kernel on a real HW as soon as able.
(hopefully this month).
I think this is good to go regardless of HW testing though.
Daniel
>
>
> r~
>
>
> Richard Henderson (11):
> disas/riscv: Decode czero.{eqz,nez}
> tcg/riscv: Probe for Zba, Zbb, Zicond extensions
> tcg/riscv: Support ANDN, ORN, XNOR from Zbb
> tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb
> tcg/riscv: Use ADD.UW for guest address generation
> tcg/riscv: Support rotates from Zbb
> tcg/riscv: Support REV8 from Zbb
> tcg/riscv: Support CPOP from Zbb
> tcg/riscv: Improve setcond expansion
> tcg/riscv: Implement movcond
> tcg/riscv: Support CTZ, CLZ from Zbb
>
> tcg/riscv/tcg-target-con-set.h | 3 +
> tcg/riscv/tcg-target-con-str.h | 1 +
> tcg/riscv/tcg-target.h | 48 +--
> disas/riscv.c | 8 +-
> tcg/riscv/tcg-target.c.inc | 612 +++++++++++++++++++++++++++++----
> 5 files changed, 587 insertions(+), 85 deletions(-)
>