[PATCH v3 0/4] Smstateen FCSR

Mayuresh Chitale posted 4 patches 1 year ago
Failed in applying to current master (apply log)
There is a newer version of this series
target/riscv/cpu.c                        |  3 ++-
target/riscv/cpu_helper.c                 |  9 +++++++
target/riscv/csr.c                        | 15 +++++++++++
target/riscv/insn_trans/trans_rvd.c.inc   | 13 ++++++---
target/riscv/insn_trans/trans_rvf.c.inc   | 24 ++++++++++++++---
target/riscv/insn_trans/trans_rvzfh.c.inc | 32 +++++++++++++++--------
target/riscv/translate.c                  | 12 ++++++++-
7 files changed, 87 insertions(+), 21 deletions(-)
[PATCH v3 0/4] Smstateen FCSR
Posted by Mayuresh Chitale 1 year ago
Patch 4 and 5 of the smstateen series need to be re-submitted with
changes described in the email below.
https://lists.nongnu.org/archive/html/qemu-riscv/2022-11/msg00155.html
Hence splitting the patch 4 of the original series into three and
re-submitting along with the original patch 5.

Changes in v3:
- Reuse TB_FLAGS.FS (instead of TB_FLAGS.HS_FS) for smstateen as HS_FS bits been removed.
- Remove fcsr check for zfh and zfhmin

Changes in v2:
 - Improve patch 1 description
 - Reuse TB_FLAGS.HS_FS for smstateen
 - Convert smstateen_fcsr_check to function
 - Add fcsr check for zdinx

Mayuresh Chitale (4):
  target/riscv: smstateen check for fcsr
  target/riscv: Reuse tb->flags.FS
  target/riscv: check smstateen fcsr flag
  target/riscv: smstateen knobs

 target/riscv/cpu.c                        |  3 ++-
 target/riscv/cpu_helper.c                 |  9 +++++++
 target/riscv/csr.c                        | 15 +++++++++++
 target/riscv/insn_trans/trans_rvd.c.inc   | 13 ++++++---
 target/riscv/insn_trans/trans_rvf.c.inc   | 24 ++++++++++++++---
 target/riscv/insn_trans/trans_rvzfh.c.inc | 32 +++++++++++++++--------
 target/riscv/translate.c                  | 12 ++++++++-
 7 files changed, 87 insertions(+), 21 deletions(-)

-- 
2.34.1