From nobody Sun May 19 21:56:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682350111; cv=none; d=zohomail.com; s=zohoarc; b=YTvNRuUod1fCT0ls/TisbVX2QR8pU7u0n0783JiJqUJc4GxJhjyk3AGg7kWdpDmF3DF/FSRutbm2N4o5t4vG4MRSfAR/a8XYqT/AsJb4QTwDQ+n838PDqDSZiEi0vO9b1YQB+6NJ3Hn/EfUGGK8ZajILN0kAS2Rz89cTM1+HOZw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682350111; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YnTnpb/oRrMNBNJ0ApTxJdoFLFl10qOphFuNP0DCCUU=; b=Z+AgJlaNitDzJFxgjrvjuNxZxss+md/zEmJEEQUnfeVYDw3SOxL5NBsviVjboQP9MFbpnIo9XhHDixPpeyi2ZFuRX+xBJSw4uAJBxREhH4yYqHfZCWHv/Qx3IE7yc+QG79tFf+sCLodyFIZHDwYV9upBAqXlNttJlNllLmbhfoE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682350111080461.7832552256099; Mon, 24 Apr 2023 08:28:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqy6F-0006kl-Qu; Mon, 24 Apr 2023 11:27:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqy6A-0006jR-0T for qemu-devel@nongnu.org; Mon, 24 Apr 2023 11:27:29 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqy65-0006sW-BS for qemu-devel@nongnu.org; Mon, 24 Apr 2023 11:27:25 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-3f1950f5628so33286065e9.3 for ; Mon, 24 Apr 2023 08:27:20 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b1-20020a5d45c1000000b002fdeafcb132sm10971517wrs.107.2023.04.24.08.27.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Apr 2023 08:27:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682350040; x=1684942040; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YnTnpb/oRrMNBNJ0ApTxJdoFLFl10qOphFuNP0DCCUU=; b=f8EpeHyY54VprktfHG/XyBsX5br9tra7f77EMN8mLmSbi5ZWbG9NBzjZFEb0OYPDAD mJp4HxvOSVCGzHu+w6q+hSr7EaICR3bdWz31p0tTnifHwha4sLBNPdqMJs3vJu8xX35c /+IlZBBkyxEGNQjy8IE/1E+XpVZm2uxHlHlTmONPmX/naD2l1Cw8nEUwuLXBy5oZpUD4 WiUyZ4D3ANezM8Ep7vwkXWe5XdfOMthBshY9PJm2EJJj92usOZNUy94gyhLIWF2T7Z7i 4dj2hdRIGfjvrFsG2PgO0RLHWBcQLTibZgdvt/pkgS/vuw3ll7S0UwGH7Dqb//bs8zIK ubLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682350040; x=1684942040; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YnTnpb/oRrMNBNJ0ApTxJdoFLFl10qOphFuNP0DCCUU=; b=AuyYtCw/7+dZpvklyO1d2eIlP5lzGTfxE89H8Jiqlh6/2NTJWDnO84Bc2xFHgqteMo YULzYdCL3kR9kqnbBFOFmslMLLZQ2t7+GIQOM8TSsMxgz9f//VSUA2E0MDvjmrDceAd9 8wxcDrHkKQ6/J3kfFGpo/nSPeXuO0CoG8MKLmkCw4oUXv6CFC4a9LfJsyC6ybPlAob5e Rv5qOwT1JLglOw7YEuuhiOu4ZR8ijRbuK2Whnw6BVpcgAE+f6fVvTQtzSp5Z6Qta52zz EoeUBFy89nXcvBjVzin1Z7qkp5F8r9GmvmWsLqrLrFe6f2F+/TfF+qIdy6gD/cZc/0zg YOGA== X-Gm-Message-State: AAQBX9fyQNoEj6nevMj4tTtQ+raFjpG5jbZufOjpGnomDTtG/QD7GDHC PEASv2NOrAMd9ZsXn0b74atroTIKcG+oQoLZ2DA= X-Google-Smtp-Source: AKy350Z0pfmt9btu/lBi9AxmNX8Fxv6dHOtSGGCdbwKlCRg7htEo/gq2Qu6lS+4KHHwHX0iaGLac6Q== X-Received: by 2002:a1c:7211:0:b0:3da:1f6a:7b36 with SMTP id n17-20020a1c7211000000b003da1f6a7b36mr7761722wmc.0.1682350039748; Mon, 24 Apr 2023 08:27:19 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Jeffery , Joel Stanley , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH 1/3] hw/arm/boot: Make write_bootloader() public as arm_write_bootloader() Date: Mon, 24 Apr 2023 16:27:15 +0100 Message-Id: <20230424152717.1333930-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424152717.1333930-1-peter.maydell@linaro.org> References: <20230424152717.1333930-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682350112289100001 From: C=C3=A9dric Le Goater The arm boot.c code includes a utility function write_bootloader() which assists in writing a boot-code fragment into guest memory, including handling endianness and fixing it up with entry point addresses and similar things. This is useful not just for the boot.c code but also in board model code, so rename it to arm_write_bootloader() and make it globally visible. Since we are making it public, make its API a little neater: move the AddressSpace* argument to be next to the hwaddr argument, and allow the fixupcontext array to be const, since we never modify it in this function. Cc: qemu-stable@nongnu.org Signed-off-by: C=C3=A9dric Le Goater [PMM: Split out from another patch by C=C3=A9dric, added doc comment] Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: C=C3=A9dric Le Goater --- include/hw/arm/boot.h | 49 +++++++++++++++++++++++++++++++++++++++++++ hw/arm/boot.c | 35 +++++++------------------------ 2 files changed, 57 insertions(+), 27 deletions(-) diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h index f18cc3064ff..80c492d7421 100644 --- a/include/hw/arm/boot.h +++ b/include/hw/arm/boot.h @@ -183,4 +183,53 @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cp= u, const struct arm_boot_info *in= fo, hwaddr mvbar_addr); =20 +typedef enum { + FIXUP_NONE =3D 0, /* do nothing */ + FIXUP_TERMINATOR, /* end of insns */ + FIXUP_BOARDID, /* overwrite with board ID number */ + FIXUP_BOARD_SETUP, /* overwrite with board specific setup code addres= s */ + FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */ + FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high hal= f) */ + FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */ + FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) = */ + FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */ + FIXUP_BOOTREG, /* overwrite with boot register address */ + FIXUP_DSB, /* overwrite with correct DSB insn for cpu */ + FIXUP_MAX, +} FixupType; + +typedef struct ARMInsnFixup { + uint32_t insn; + FixupType fixup; +} ARMInsnFixup; + +/** + * arm_write_bootloader - write a bootloader to guest memory + * @name: name of the bootloader blob + * @as: AddressSpace to write the bootloader + * @addr: guest address to write it + * @insns: the blob to be loaded + * @fixupcontext: context to be used for any fixups in @insns + * + * Write a bootloader to guest memory at address @addr in the address + * space @as. @name is the name to use for the resulting ROM blob, so + * it should be unique in the system and reasonably identifiable for debug= ging. + * + * @insns must be an array of ARMInsnFixup structs, each of which has + * one 32-bit value to be written to the guest memory, and a fixup to be + * applied to the value. FIXUP_NONE (do nothing) is value 0, so effectively + * the fixup is optional when writing a struct initializer. + * The final entry in the array must be { 0, FIXUP_TERMINATOR }. + * + * All other supported fixup types have the semantics "ignore insn + * and instead use the value from the array element @fixupcontext[fixup]". + * The caller should therefore provide @fixupcontext as an array of + * size FIXUP_MAX whose elements have been initialized for at least + * the entries that @insns refers to. + */ +void arm_write_bootloader(const char *name, + AddressSpace *as, hwaddr addr, + const ARMInsnFixup *insns, + const uint32_t *fixupcontext); + #endif /* HW_ARM_BOOT_H */ diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 54f6a3e0b3c..720f22531a6 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -60,26 +60,6 @@ AddressSpace *arm_boot_address_space(ARMCPU *cpu, return cpu_get_address_space(cs, asidx); } =20 -typedef enum { - FIXUP_NONE =3D 0, /* do nothing */ - FIXUP_TERMINATOR, /* end of insns */ - FIXUP_BOARDID, /* overwrite with board ID number */ - FIXUP_BOARD_SETUP, /* overwrite with board specific setup code addres= s */ - FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */ - FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high hal= f) */ - FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */ - FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) = */ - FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */ - FIXUP_BOOTREG, /* overwrite with boot register address */ - FIXUP_DSB, /* overwrite with correct DSB insn for cpu */ - FIXUP_MAX, -} FixupType; - -typedef struct ARMInsnFixup { - uint32_t insn; - FixupType fixup; -} ARMInsnFixup; - static const ARMInsnFixup bootloader_aarch64[] =3D { { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */ { 0xaa1f03e1 }, /* mov x1, xzr */ @@ -150,9 +130,10 @@ static const ARMInsnFixup smpboot[] =3D { { 0, FIXUP_TERMINATOR } }; =20 -static void write_bootloader(const char *name, hwaddr addr, - const ARMInsnFixup *insns, uint32_t *fixupcon= text, - AddressSpace *as) +void arm_write_bootloader(const char *name, + AddressSpace *as, hwaddr addr, + const ARMInsnFixup *insns, + const uint32_t *fixupcontext) { /* Fix up the specified bootloader fragment and write it into * guest memory using rom_add_blob_fixed(). fixupcontext is @@ -214,8 +195,8 @@ static void default_write_secondary(ARMCPU *cpu, fixupcontext[FIXUP_DSB] =3D CP15_DSB_INSN; } =20 - write_bootloader("smpboot", info->smp_loader_start, - smpboot, fixupcontext, as); + arm_write_bootloader("smpboot", as, info->smp_loader_start, + smpboot, fixupcontext); } =20 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, @@ -1186,8 +1167,8 @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, fixupcontext[FIXUP_ENTRYPOINT_LO] =3D entry; fixupcontext[FIXUP_ENTRYPOINT_HI] =3D entry >> 32; =20 - write_bootloader("bootloader", info->loader_start, - primary_loader, fixupcontext, as); + arm_write_bootloader("bootloader", as, info->loader_start, + primary_loader, fixupcontext); =20 if (info->write_board_setup) { info->write_board_setup(cpu, info); --=20 2.34.1 From nobody Sun May 19 21:56:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682350138; cv=none; d=zohomail.com; s=zohoarc; b=gqfwe6dqdVIaGzmpG04rLbODSBceiOkYcDZCYx47It4VKRzvyNUB/kSH2h4Gdc00ZVAG6U1KXFciwnhSepKQbfxE9X1CI9QF1kjmmZYBCqUlNgSuf3FiQR79XvqmePFRcl7MrBAmUb6hqSkJ3rD8yHDJgc0IEp6UZ9OMj0wWtNk= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b1-20020a5d45c1000000b002fdeafcb132sm10971517wrs.107.2023.04.24.08.27.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Apr 2023 08:27:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682350040; x=1684942040; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5geIGOhKXTNOnUumAZpLeK5JvkWsmSTZmE66oiXbKTA=; b=qCgxDrzJL3LSqI1wVDFaTIGojdBAyr0bJzIWpUmhDIWkmCI8b3/VQ181bQyGx1O9U3 VItbssMh+OI4giOAbPky5htwDBVF+6D2FTHU1LOqaF5TGC4swGQsoB8QZ6bRcxX0UXnl TqWTxKEHhgIEt48jgvjGox/XdGIc+avTXRUUyVxY8ka/Jm0K7LV1TX2VQNuwAUQ8kOX0 9oJaRVBpPU1GEIuHJkFFSNjmMcHDSkSv5YqPrX6DszAboAdiT/gVsf6VCI9+kTCtl7lu 6QP74g4Hcl+M+lb+0XIebn7/D9QGp1BewotjRNyG+2KrQ60NMmHxhECeY03wVWXPh7Zb VmOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682350040; x=1684942040; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5geIGOhKXTNOnUumAZpLeK5JvkWsmSTZmE66oiXbKTA=; b=KC9m2NjeNG3noCSGhY9lB3GI0VJgOnjk/etZb6EhqASIBhIqGbxMwKyIDFwX/7wyHL 4JsqVf+OQkUNPN3gGBu2XDyiF+6ujTUT7WHBx7QNA/UHKzxGLVTZhlbUV2oRlAhPKRIL 9SlE1KBcXzY1UXhyAZb1RfjNnFVQra4s06Bpo47P3rygbH8QgH3s+KH4nJ43Fbxeo/25 7TcEo/3J1mTvNTiYcC5tTgxQV5Lu4hWtIV3oJ1dEnPUy+9FXz2B6h1vwjIVeCm7Xg4Am Pkq1PexM289wk1rok1aoM/b5eGpIwCootLknyP4w/AeiZQAs3ybCcVOgdIHhdLZIU4rW TAHw== X-Gm-Message-State: AAQBX9frKtRayqa6D2W9JZ0rdEtiFyPv+jOFUclozUqA/34U95jqS/oF CH3R5kkJJWj0OnEWdHb6GYTuyw== X-Google-Smtp-Source: AKy350a5BnB4gNiMYva/UB23u7cWOMKouUVvwveIh3wPFCzNhl+wc+MJxrdN8z0jAPOJXSQwYoVXQw== X-Received: by 2002:adf:fc11:0:b0:2f9:95b4:450a with SMTP id i17-20020adffc11000000b002f995b4450amr9730401wrr.25.1682350040318; Mon, 24 Apr 2023 08:27:20 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Jeffery , Joel Stanley , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH 2/3] hw/arm/aspeed: Use arm_write_bootloader() to write the bootloader Date: Mon, 24 Apr 2023 16:27:16 +0100 Message-Id: <20230424152717.1333930-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424152717.1333930-1-peter.maydell@linaro.org> References: <20230424152717.1333930-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682350139696100007 From: C=C3=A9dric Le Goater When writing the secondary-CPU stub boot loader code to the guest, use arm_write_bootloader() instead of directly calling rom_add_blob_fixed(). This fixes a bug on big-endian hosts, because arm_write_bootloader() will correctly byte-swap the host-byte-order array values into the guest-byte-order to write into the guest memory. Cc: qemu-stable@nongnu.org Signed-off-by: C=C3=A9dric Le Goater [PMM: Moved the "make arm_write_bootloader() function public" part to its own patch; updated commit message to note that this fixes an actual bug; adjust to the API changes noted in previous commit] Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 38 ++++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index c1f2b9cfcab..0b29028fe11 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -200,33 +200,35 @@ struct AspeedMachineState { static void aspeed_write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) { - static const uint32_t poll_mailbox_ready[] =3D { + AddressSpace *as =3D arm_boot_address_space(cpu, info); + static const ARMInsnFixup poll_mailbox_ready[] =3D { /* * r2 =3D per-cpu go sign value * r1 =3D AST_SMP_MBOX_FIELD_ENTRY * r0 =3D AST_SMP_MBOX_FIELD_GOSIGN */ - 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ - 0xe21000ff, /* ands r0, r0, #255 */ - 0xe59f201c, /* ldr r2, [pc, #28] */ - 0xe1822000, /* orr r2, r2, r0 */ + { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5 */ + { 0xe21000ff }, /* ands r0, r0, #255 */ + { 0xe59f201c }, /* ldr r2, [pc, #28] */ + { 0xe1822000 }, /* orr r2, r2, r0 */ =20 - 0xe59f1018, /* ldr r1, [pc, #24] */ - 0xe59f0018, /* ldr r0, [pc, #24] */ + { 0xe59f1018 }, /* ldr r1, [pc, #24] */ + { 0xe59f0018 }, /* ldr r0, [pc, #24] */ =20 - 0xe320f002, /* wfe */ - 0xe5904000, /* ldr r4, [r0] */ - 0xe1520004, /* cmp r2, r4 */ - 0x1afffffb, /* bne */ - 0xe591f000, /* ldr pc, [r1] */ - AST_SMP_MBOX_GOSIGN, - AST_SMP_MBOX_FIELD_ENTRY, - AST_SMP_MBOX_FIELD_GOSIGN, + { 0xe320f002 }, /* wfe */ + { 0xe5904000 }, /* ldr r4, [r0] */ + { 0xe1520004 }, /* cmp r2, r4 */ + { 0x1afffffb }, /* bne */ + { 0xe591f000 }, /* ldr pc, [r1] */ + { AST_SMP_MBOX_GOSIGN }, + { AST_SMP_MBOX_FIELD_ENTRY }, + { AST_SMP_MBOX_FIELD_GOSIGN }, + { 0, FIXUP_TERMINATOR } }; + static const uint32_t fixupcontext[FIXUP_MAX] =3D { 0 }; =20 - rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, - sizeof(poll_mailbox_ready), - info->smp_loader_start); + arm_write_bootloader("aspeed.smpboot", as, info->smp_loader_start, + poll_mailbox_ready, fixupcontext); } =20 static void aspeed_reset_secondary(ARMCPU *cpu, --=20 2.34.1 From nobody Sun May 19 21:56:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682350135; cv=none; d=zohomail.com; s=zohoarc; b=kTtBVS6OEW0UrIL28U8bmLIhVqC8xcHUD6U85tQDp3qzo1C6+rA5YFBdDnE3k5Z7ZDG4dJtxEXXRtOyRbqf8PNlr13Gq233rvuiDJ+naZMo7NqmelgwPQFdpWRFD8yGv/IqlDyQoRtU3zzkgKuEG1KnQGYFHFOaSHfysxFcvLaI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682350135; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZZKjYXHyIeMkg0aKSc0TvN58snmM4oHGc16JhGaHgLU=; b=Lb3iaenp1kTRSyaG5j5CnNHiTInPw6r7rDihx7QI6/PEuXwFMzsDAyPXfKo+awE5ArJ+Fd4XglgCnLjQQIa2/EPL+K6zW5C3wUSNy1SYZn8uLi4Gb8LtmWVuwCfk6crWvfkAxwVQx3/2+d83ZMY56xjhUyffmkgzn55ClgFTwHI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168235013556386.2854027065323; Mon, 24 Apr 2023 08:28:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqy6H-0006lg-ND; Mon, 24 Apr 2023 11:27:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqy6C-0006jW-0r for qemu-devel@nongnu.org; Mon, 24 Apr 2023 11:27:29 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqy66-0006sz-EK for qemu-devel@nongnu.org; Mon, 24 Apr 2023 11:27:27 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-3f178da21b5so30883185e9.3 for ; Mon, 24 Apr 2023 08:27:22 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id b1-20020a5d45c1000000b002fdeafcb132sm10971517wrs.107.2023.04.24.08.27.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Apr 2023 08:27:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682350041; x=1684942041; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZZKjYXHyIeMkg0aKSc0TvN58snmM4oHGc16JhGaHgLU=; b=aESgrZfJrlwqhhiLZA7aRfipgMzYJyYzye0ieW8n3FgJmIFXe4VF0WFI2eXFTLnTBw oDODwCFFs5AnudZ1SulvI+1OcH4dZZciAxI/SjeA9c5jzmwexYuBFrfnv0QKOd3sndtG hsvEwNX+Zr0Z4kYfjkmlGio4oOY9y/1Zy9+I9Z8BJuvs01ntlO9KEodNRjLomgCurxnr rxUJ0DpK50BGrer1UgDMwRNCiLEeGcZN88zv9n6vlCkkw/0UPCv7HZ01vZZwGsruj8OW ipNMJKCg24YalhQCsHAxbLC/9QneiMbLmpvpKZzJ5b76asJ8h+Jl33erygGSi91LJkXw PDxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682350041; x=1684942041; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZZKjYXHyIeMkg0aKSc0TvN58snmM4oHGc16JhGaHgLU=; b=eaUWAS0o987HD78qevAuQ/zmwDE3Jko4l7mIh4vptzMlkFAfYHwE4E44Ep8OagbJGs o45Gx3aJUq0R6S2PzIFVuBiQNbednP/0/ZF6Vk3eZzQ0/HuIETzuA+2LikC8AO0FLUf+ K7WN3b9JVXc+PYiBrKgk9+gLFZW5JTnOuyBsluJVE+pPUaMwD1AknidAay6z8cNnnZu2 3xCFXER5PPZ7SamQEBNGRkTrMEbkJWpL96cGQxlqPvLys7Jvw6DlJ/Ime+sL3KkOL1pB R8XoFjPEyo6V2g6ugTpAI2FE79Srp3BfpygxK2vl4BS8M98eaY9YZwEvHCu5egAQFalZ Jp6A== X-Gm-Message-State: AAQBX9e+WO1GA64a8GRldocu7yoKBBUoA6zfrm6nwqRwkcMrXv5YckJR JJESs0t4iAw9qnFyhZPWhQGLnA== X-Google-Smtp-Source: AKy350YJLDU+R41zAdtSpTfltBnXFKieDIwRiXcKFu0nbMqtxkI4J1U0uU4qXkHG7YAvp7M4D92NFg== X-Received: by 2002:a7b:cb57:0:b0:3f2:507f:25a4 with SMTP id v23-20020a7bcb57000000b003f2507f25a4mr2019118wmj.30.1682350040839; Mon, 24 Apr 2023 08:27:20 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Jeffery , Joel Stanley , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PATCH 3/3] hw/arm/raspi: Use arm_write_bootloader() to write boot code Date: Mon, 24 Apr 2023 16:27:17 +0100 Message-Id: <20230424152717.1333930-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424152717.1333930-1-peter.maydell@linaro.org> References: <20230424152717.1333930-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682350136841100003 Content-Type: text/plain; charset="utf-8" When writing the secondary-CPU stub boot loader code to the guest, use arm_write_bootloader() instead of directly calling rom_add_blob_fixed(). This fixes a bug on big-endian hosts, because arm_write_bootloader() will correctly byte-swap the host-byte-order array values into the guest-byte-order to write into the guest memory. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: C=C3=A9dric Le Goater --- hw/arm/raspi.c | 64 +++++++++++++++++++++++++++----------------------- 1 file changed, 34 insertions(+), 30 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 92d068d1f9d..a7d287b1a8a 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -16,6 +16,7 @@ #include "qemu/units.h" #include "qemu/cutils.h" #include "qapi/error.h" +#include "hw/arm/boot.h" #include "hw/arm/bcm2836.h" #include "hw/registerfields.h" #include "qemu/error-report.h" @@ -124,20 +125,22 @@ static const char *board_type(uint32_t board_rev) =20 static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) { - static const uint32_t smpboot[] =3D { - 0xe1a0e00f, /* mov lr, pc */ - 0xe3a0fe00 + (BOARDSETUP_ADDR >> 4), /* mov pc, BOARDSETUP_ADDR */ - 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5;get core ID */ - 0xe7e10050, /* ubfx r0, r0, #0, #2 ;extract LSB */ - 0xe59f5014, /* ldr r5, =3D0x400000CC ;load mbox base */ - 0xe320f001, /* 1: yield */ - 0xe7953200, /* ldr r3, [r5, r0, lsl #4] ;read mbox for our = core*/ - 0xe3530000, /* cmp r3, #0 ;spin while zero */ - 0x0afffffb, /* beq 1b */ - 0xe7853200, /* str r3, [r5, r0, lsl #4] ;clear mbox */ - 0xe12fff13, /* bx r3 ;jump to target */ - 0x400000cc, /* (constant: mailbox 3 read/clear base) */ + static const ARMInsnFixup smpboot[] =3D { + { 0xe1a0e00f }, /* mov lr, pc */ + { 0xe3a0fe00 + (BOARDSETUP_ADDR >> 4) }, /* mov pc, BOARDSETUP_ADD= R */ + { 0xee100fb0 }, /* mrc p15, 0, r0, c0, c0, 5;get core ID */ + { 0xe7e10050 }, /* ubfx r0, r0, #0, #2 ;extract LSB */ + { 0xe59f5014 }, /* ldr r5, =3D0x400000CC ;load mbox ba= se */ + { 0xe320f001 }, /* 1: yield */ + { 0xe7953200 }, /* ldr r3, [r5, r0, lsl #4] ;read mbox for = our core */ + { 0xe3530000 }, /* cmp r3, #0 ;spin while zer= o */ + { 0x0afffffb }, /* beq 1b */ + { 0xe7853200 }, /* str r3, [r5, r0, lsl #4] ;clear mbox */ + { 0xe12fff13 }, /* bx r3 ;jump to target= */ + { 0x400000cc }, /* (constant: mailbox 3 read/clear base) */ + { 0, FIXUP_TERMINATOR } }; + static const uint32_t fixupcontext[FIXUP_MAX] =3D { 0 }; =20 /* check that we don't overrun board setup vectors */ QEMU_BUILD_BUG_ON(SMPBOOT_ADDR + sizeof(smpboot) > MVBAR_ADDR); @@ -145,9 +148,8 @@ static void write_smpboot(ARMCPU *cpu, const struct arm= _boot_info *info) QEMU_BUILD_BUG_ON((BOARDSETUP_ADDR & 0xf) !=3D 0 || (BOARDSETUP_ADDR >> 4) >=3D 0x100); =20 - rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot), - info->smp_loader_start, - arm_boot_address_space(cpu, info)); + arm_write_bootloader("raspi_smpboot", arm_boot_address_space(cpu, info= ), + info->smp_loader_start, smpboot, fixupcontext); } =20 static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) @@ -161,26 +163,28 @@ static void write_smpboot64(ARMCPU *cpu, const struct= arm_boot_info *info) * the primary CPU goes into the kernel. We put these variables inside * a rom blob, so that the reset for ROM contents zeroes them for us. */ - static const uint32_t smpboot[] =3D { - 0xd2801b05, /* mov x5, 0xd8 */ - 0xd53800a6, /* mrs x6, mpidr_el1 */ - 0x924004c6, /* and x6, x6, #0x3 */ - 0xd503205f, /* spin: wfe */ - 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */ - 0xb4ffffc4, /* cbz x4, spin */ - 0xd2800000, /* mov x0, #0x0 */ - 0xd2800001, /* mov x1, #0x0 */ - 0xd2800002, /* mov x2, #0x0 */ - 0xd2800003, /* mov x3, #0x0 */ - 0xd61f0080, /* br x4 */ + static const ARMInsnFixup smpboot[] =3D { + { 0xd2801b05 }, /* mov x5, 0xd8 */ + { 0xd53800a6 }, /* mrs x6, mpidr_el1 */ + { 0x924004c6 }, /* and x6, x6, #0x3 */ + { 0xd503205f }, /* spin: wfe */ + { 0xf86678a4 }, /* ldr x4, [x5,x6,lsl #3] */ + { 0xb4ffffc4 }, /* cbz x4, spin */ + { 0xd2800000 }, /* mov x0, #0x0 */ + { 0xd2800001 }, /* mov x1, #0x0 */ + { 0xd2800002 }, /* mov x2, #0x0 */ + { 0xd2800003 }, /* mov x3, #0x0 */ + { 0xd61f0080 }, /* br x4 */ + { 0, FIXUP_TERMINATOR } }; + static const uint32_t fixupcontext[FIXUP_MAX] =3D { 0 }; =20 static const uint64_t spintables[] =3D { 0, 0, 0, 0 }; =20 - rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot), - info->smp_loader_start, as); + arm_write_bootloader("raspi_smpboot", as, info->smp_loader_start, + smpboot, fixupcontext); rom_add_blob_fixed_as("raspi_spintables", spintables, sizeof(spintable= s), SPINTABLE_ADDR, as); } --=20 2.34.1