From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315012; cv=none; d=zohomail.com; s=zohoarc; b=Quanry40/kftb5e6Yhts97LM2jHYkDq+AVzsJsW0mlEf5EdaVZuXBYgT+P60CCmFcWB55duVw7LDvI+exOuhYy0EaBpt5PDietQld5MWqit9o6snsqxEig+Ux1d3tliH9Thp92lut94pqaML12tE+z1gMc1ssVEdE5vqocrOXWU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315012; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=B1Nme4PEfXiHQBNXQfkGnrKxGcTYdXe7t9M4qvQh2U4=; b=S8KoB3mJQrspu+DVv6U1wMtD471UOy1hXRvK93FgxGzTYO0RuQAE9+fAs22ZD6M9gSz06T3mL0l9fSjuNrh2iTdpkr6Zc38DfkLtkfdDNM3pRbl+S2E/WIhBuRsid4LnKyfQ2zZg/JV0orBzT13CL2LkfjGFO7MDGxP/OPnB+IU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315012116777.445299589312; Sun, 23 Apr 2023 22:43:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqowy-0005Br-SR; Mon, 24 Apr 2023 01:41:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqowv-00059P-Dz for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:17 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqowp-0004Dx-9k for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:16 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-2f6401ce8f8so2308678f8f.3 for ; Sun, 23 Apr 2023 22:41:08 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314867; x=1684906867; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B1Nme4PEfXiHQBNXQfkGnrKxGcTYdXe7t9M4qvQh2U4=; b=POFyKC8bkGhATjB5yTP/u5UJ96PKN+NTU6yjHTIt/AlayR115/hSgDY9zqqntzHLVX jp1YNS5bYwH51CjCPYbcFFO1IwAYqdkYTFwrCnwOym9tisZ8abm6Me52Gi/MpOo3WWCW JGyOOIjfBTL2D8Sh8ExjLtSMTmeeIQwU5Lvi1v2Bme/k0acq8U4JmzLNFIvoemcFGb/l PV0+GZfUt1bjCNIAqs364no5ND0jLp5YdjTO1WgZCaPxL7pPeadwaWalR/gmHtKMHE8O a9DfAKAO4FX+QQ5QXSmKrlnLoIY57RiniE7Nbcm34ox0C3mbnzcbB1jGYGpgZlLa475I O8GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314867; x=1684906867; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B1Nme4PEfXiHQBNXQfkGnrKxGcTYdXe7t9M4qvQh2U4=; b=f8Tw5g5PufQllbTBbp9tiQVfc5UDjLTNwu8sO5wms7GraUD6kq4Mzd/+Kfhm0y7E0i vpRhlnNOCL4OCcw4nzQltcf3XUvRnARztd+H6WTmCH7FglaklaAWAKjxEHLzBkTlDP2g i+hIv6HSp1Jl5uUG5lTuEtzymD/rBY0ptQP5pvn+IfNbUeeCI33jnNbXCL3pU1vx9sAX xl73xbre27eQRlZmRDsLg/Sj6yUtREZZJr/nDmUXtKWQUKXKwgYkoK2mwT2KmOsHwNZw Z2OYVPyhTDruoOxXpoTdzevMSs5ajbAcNhYh7rOoNTQhY6AfaN6YgM6x2qot8DSCBpJF evtw== X-Gm-Message-State: AAQBX9c01iJQVynsGP36qQ1WZfAY1FCtk8gCJsHeBQygvkPIcDMjrBSA 7Z8mBUjXjueK++Uk1BFpsRysjRx4uRnhw0J/ZwEINg== X-Google-Smtp-Source: AKy350ZBHev0XzwIq8aQkrhGUsIoFiWoYLwiYco2n6TIQoikpW4fyynoiXYgIAtj5Urusj2dbkd0dw== X-Received: by 2002:a5d:40cc:0:b0:2f0:58a:db82 with SMTP id b12-20020a5d40cc000000b002f0058adb82mr7492931wrq.36.1682314867095; Sun, 23 Apr 2023 22:41:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 01/57] tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64 Date: Mon, 24 Apr 2023 06:40:09 +0100 Message-Id: <20230424054105.1579315-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315013932100009 Content-Type: text/plain; charset="utf-8" Since TCG_TYPE_I32 values are kept sign-extended in registers, via ".w" instructions, we need not extend if the register matches. This is already relied upon by comparisons. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/loongarch64/tcg-target.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 21c2fc9e98..0940788c6f 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -463,7 +463,9 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, T= CGReg arg) =20 static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) { - tcg_out_ext32s(s, ret, arg); + if (ret !=3D arg) { + tcg_out_ext32s(s, ret, arg); + } } =20 static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315003; cv=none; d=zohomail.com; s=zohoarc; b=i6rtK9REJVRf2tu0qIqGtZLeJBM0tBs34piMiP82y8TNsfsB3TuPWXOrBLL2iKo0OyNG10q0H4JX9taJyYTzOtOvE1sVBMMugBiBJs/MkPzhE/cAnEx4pOloAZ/6pJCjczOuod83pJBGJBZvX9wZzLac1PdGG/zLPY/GjqThUSg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315003; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0fR1b522KKsIelYZfiuxLUq8SgNfFMeT4gqF0CUIbNU=; b=bE3t7XkVBEj3CrKEZXefuTpIoXfJTYKUWiqQEzQbTHkHQS5DT/GY+fIGlOVCBvA9FXWRpfMEAu0nIRpnDe3KBdeiOzaCbyW4cnnqF9I0gMzdvCRPL2bIlimnfxATz04RErdnDL8yHGk6kGl0Wc4HI/MSoA8EjjWdDNvCF4MR1w8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315003099766.7065060946941; Sun, 23 Apr 2023 22:43:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqox0-0005F9-E2; Mon, 24 Apr 2023 01:41:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqoww-00059j-SU for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:19 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqowp-0004EK-8p for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:17 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3f19c473b9eso30731655e9.0 for ; Sun, 23 Apr 2023 22:41:08 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314867; x=1684906867; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0fR1b522KKsIelYZfiuxLUq8SgNfFMeT4gqF0CUIbNU=; b=RADtIJhDr5EG/Rj6SUP2fKHSeCECGxxk1crSfv3iEca5bbWFmxfcMl/nQUXMwhKIdu ka+YVSa2HOUpX9zyYkaC5AtVBNXpHANRhe6ezTR83p9xp5wWog1xQaPzVAYZabUpeFsB AIaSkriboY4DUwyt27jazZUCrs4Nyx5LjFYx6r0PQ18jJHYBoZ73BFsgShNB0H3hrtL6 aXUONEcIiS/jgjSRSSAu24NBEXp4ryIcteF6Z1qn1FnhMHFpSlPgfMZrV3sjRC7WXn0W z3F+f4JXxPO4DottMedSErUN5HAS8F+VKZBWnyO+1AuuESPkKgO0GBBOJoN+OL370IYF eO6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314867; x=1684906867; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0fR1b522KKsIelYZfiuxLUq8SgNfFMeT4gqF0CUIbNU=; b=TVzh9ojj0rJ53HD4LPATBfInhsQ/q8rsfOqTtA8OWuect2ng+zskJ1JY9pI4in24LC avWfm26/ko3VLxhFjXTaPAri+Fravj7B0AMPWZ6dbJDkZ+oZYX3FcoA7HLrVzY3o0izb 1dyyO7CTyOQCjmNe5HiOy5d0MfjZseZrBZMichMSEMeD1ygqmLL6i1XFcrCeepQzohlz L84/frP9Uhxp9dL7Wp2DxOGfC48I7BTkS9ejoyFJDFL+w54hy8hRVpAYSrxmTljRYqY8 y6hytb4/RU3NNqkbi/bGZQiYvufSuaPm3nchlIyMXS2KoOX+TKR/cBj6GS/2P3BVmvZ3 Ry7g== X-Gm-Message-State: AAQBX9c6q9Il+s5m9+1Ndko+r8GIJeU/nUuVwjze4iRA1IR996xA7TTW XIbuzOfUcH75AL6PhilDQI7TNTBak2d7TIQMSgibYQ== X-Google-Smtp-Source: AKy350a7QZW5dNBt3CrI/Io1SCRyC6vUQ6U4dyvMNaZXhEHOhmHGigSaTByZDRgbx9TG1xnWS9R7vQ== X-Received: by 2002:adf:e711:0:b0:2ef:84c:a4bc with SMTP id c17-20020adfe711000000b002ef084ca4bcmr13177344wrm.19.1682314867709; Sun, 23 Apr 2023 22:41:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 02/57] tcg/mips: Conditionalize tcg_out_exts_i32_i64 Date: Mon, 24 Apr 2023 06:40:10 +0100 Message-Id: <20230424054105.1579315-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315003898100001 Content-Type: text/plain; charset="utf-8" Since TCG_TYPE_I32 values are kept sign-extended in registers, we need not extend if the register matches. This is already relied upon by comparisons. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/mips/tcg-target.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 346c614354..a83ebe8729 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -582,7 +582,9 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TC= GReg rs) =20 static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) { - tcg_out_ext32s(s, rd, rs); + if (rd !=3D rs) { + tcg_out_ext32s(s, rd, rs); + } } =20 static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315009; cv=none; d=zohomail.com; s=zohoarc; b=V9lWg1eKYU3hZVd4x8CNLp7uww0t/ooNp4vpqxcaAAAOgt/4j9vRb3FBK1gFs5F8U3pGZQH3s7XFIdEqoAjCPp3LACLW5CEwClsj0vC2Rgke9SlyXLzQWrn4NYYYrAQP8dOw7OlIRr2zzTIsvvriED3PngjeC+PH5E6pHfHIFNY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315009; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kUxjn8m10fBk8f3TxtdoxukkDWbqJjziW6krAeWvMi0=; b=ORRJ673I9fCemPw47mPGSn9Be21uiM3xslwtXgn1rCsflU1uwQS0DKOv97tEqNin7kOCa6FJLhGQ27NTX3bopbnjqw1DP7J28C3jcB5xzzBSiyS3hUg/ldDCqCGJmX+AwFoxDxBkEVCCLdHMRhbel7fYfwOw5Gu3l7fv9czLfEA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315009533173.08368575891154; Sun, 23 Apr 2023 22:43:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqoxj-0005oK-4d; Mon, 24 Apr 2023 01:42:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqox3-0005Ij-MR for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:26 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqown-0004Ee-R9 for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:25 -0400 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-2f9b9aa9d75so2409700f8f.0 for ; Sun, 23 Apr 2023 22:41:09 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314868; x=1684906868; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kUxjn8m10fBk8f3TxtdoxukkDWbqJjziW6krAeWvMi0=; b=GbNGFaxW0qBKRrcFsI99gICoCIObEvTA/N6Z0GhHXiLFdq5EhV6QOLgapVD+8gWKYX vd+7BPcKsD2L3sak9T2wB3MWoMNjqNCsCdWrH8tnnXbyZalawADaxvIcz/6GMQur9Krw 7sNB6GJCatjyN54U55VK344k24nO80u6NscLRvL7VmlftVotrk33utNtqRoFDwuM0caI 2YIxlpWZzfI1M705+/SzJm+y3LgiV5qCBKv5K9tT9DTamMdg81gIeK2XUgYxykqL53LQ 24Df6j+1ley5sfSfp57+QlSetzKnz8QXWMd8mdH+snxvVn/Lwc1T7ymTeThokTHJWTzD oPCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314868; x=1684906868; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kUxjn8m10fBk8f3TxtdoxukkDWbqJjziW6krAeWvMi0=; b=ddqtCtBVGtPNSv+ckCp+6fkPKDgeQ47XcZuL0zaBxUTIbAYSJs9eBjQnWVjp2haJp9 w6j2NIqCVztehYx3rx7QNu91+z1+eJvlFpBQAFgUvjUrsyCD3imgjwHE8ywTmgSxDG0k R9vXMIquEYFo7Rm/gCBAn+mZ9IpPUo9Rho0kmoAlp+n/NgdxletYV9+ryY22Rg2JwCd/ RISsPOsXEuzn/BihRPULcBOK5/4TRevIbNsMGohZWuefIlQAEQ9qO0IwGx9npyqCJmQi W40SAopxtO6NZp4KjLp65QCb2aSsjj+2Z/55f1uAQyyjwzRGOJS1goh1Ye/SAL3KAJuX AyoQ== X-Gm-Message-State: AAQBX9cXdv6rWi/4OZ11Ao1p+INOU06kl4NGiEFz7NdqKeHuPfauuj4L 05b03JKeU7qvQfOSL/Am6954SYNg1DPDGT3lMzA4MA== X-Google-Smtp-Source: AKy350ZR8jdXSz2UK+NeDe+WuhGMQOgGi+jRMXzhCaNoziGhYYk712ZVjf2xP4yFP38b2JLFCbBktw== X-Received: by 2002:a05:6000:8e:b0:304:6d32:d589 with SMTP id m14-20020a056000008e00b003046d32d589mr3425375wrx.18.1682314868201; Sun, 23 Apr 2023 22:41:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 03/57] tcg/i386: Conditionalize tcg_out_extu_i32_i64 Date: Mon, 24 Apr 2023 06:40:11 +0100 Message-Id: <20230424054105.1579315-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315009916100001 Content-Type: text/plain; charset="utf-8" Since TCG_TYPE_I32 values are kept zero-extended in registers, via omission of the REXW bit, we need not extend if the register matches. This is already relied upon by qemu_{ld,st}. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/i386/tcg-target.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index c8e2bf537f..ce87f8fbc9 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1314,7 +1314,9 @@ static void tcg_out_exts_i32_i64(TCGContext *s, TCGRe= g dest, TCGReg src) =20 static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) { - tcg_out_ext32u(s, dest, src); + if (dest !=3D src) { + tcg_out_ext32u(s, dest, src); + } } =20 static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg dest, TCGReg src) --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315145; cv=none; d=zohomail.com; s=zohoarc; b=iQeQZB6HE7ABBpBG9ByLdr+FQfEkqMnfkiVRQ1uZDcBHb0G5ACYZTfRsI4NuDHsBYdpnVUUJFK+OMOSEBAOxGsdHZpLajjiCQjdY/eou8YO3c+ZllNiuOJNXgo4EIKvsbG3dsfIYkUP0EYD107P/8poUfF9kPO2VrM7SiMq8PVk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315145; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xmZ3Z0VcDD6PgUhrS/B0joODuceToVQhJs8I2eE8Cd0=; b=TD3Ad+Om0uJKcDjw36rV9TTf06WhTq9nbby3w3+iegqHYhaTI9/0mXkq0VFyoliyFAA1Op14PG+hIVke9rsZsrNTEL4gosqvvpZEz3flJUGiB8ymQLE+Zm6nEnGcWpGzZdiIyQHD/5KwXhgHo4A9hNg2h6UEm2npCF1wEZ5qGiE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315145836382.28064631797577; Sun, 23 Apr 2023 22:45:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqox0-0005Ed-3J; Mon, 24 Apr 2023 01:41:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqowv-000598-5q for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:17 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqowp-0004Ez-9d for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:16 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-2f7c281a015so2296673f8f.1 for ; Sun, 23 Apr 2023 22:41:09 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314868; x=1684906868; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xmZ3Z0VcDD6PgUhrS/B0joODuceToVQhJs8I2eE8Cd0=; b=g9F2c1zl7Xz3FzyQtcctbtY8VFDPVAuBWTquyv1x6+7Y7ENn8sVfWONLHrQrsZgL9D JrjShkYdTg3kFxJezUAwomJp9krFdAhzxL8orrz2rYL/6zZGzHxy5asDqhDraCJkgOTD sTilAz/WXbfdo5awiwe0nLcSe/tPFJZrQtf4HwvbhsAyQ2yOcnDYi2S1QgOFpO3kBJ67 NM6G776ZNGs0lc/iHggB9HqyP/Rf4Rh3ISuntP/kHfYj+ObpKUzWZHQVEdhMDp/zYyHn ZLxfULZrgzjhp9b6qXM7q1Kg9gltQ81+mBapoik9P2jMMcFchKfPvRRC7s0iwU9gqB5b Muig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314868; x=1684906868; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xmZ3Z0VcDD6PgUhrS/B0joODuceToVQhJs8I2eE8Cd0=; b=QP6sC48NXFX0WOAMpJEjlWRV2uOcdjooNzR0x2R+LFjmchCIrooZrOJBbSIxb51FjM kyuG3GS/ULDeDV4qOJinqBRApY2e46SCTx1cjaZ9c3ZeC/xdtV2jDpKPpTnf4npDl1aV bfUwfnmmheAD1qS6CdOGLzecH+2o+Yca8j0/O+9XjGeOr91gaVmj2gMqk04gwvi/zEcf POQWPQxALy7mpZYEfSdUjn/UiBA8+eQsNT9pAaDjgjbHCOM2iWqd/GGk0GwP+99E349h cAaQYcfJ6byFwgu9QddrAsAMNYwPlLnOo/ZEqiNU7zLCAa1PfoI2F9ZhYs9vLXJMLKSj W+5Q== X-Gm-Message-State: AAQBX9djCt1rnsUhBdvr8h9XCsjdzA99CibNzrnGwEIK01GlCq8X/QYn aYgQgw5WYzmuK6LyXyyzRVFmEhZuGgRNR8c3Af8dJw== X-Google-Smtp-Source: AKy350bPsbdMVlp2vtA+AEDZasfOhed6GK9CF5g7KUppUYBy8v+uWp+8AhlIeyev1+8fKkuSpObqfA== X-Received: by 2002:a05:6000:1b89:b0:304:6fef:f375 with SMTP id r9-20020a0560001b8900b003046feff375mr3526977wru.70.1682314868660; Sun, 23 Apr 2023 22:41:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 04/57] tcg: Introduce tcg_out_movext2 Date: Mon, 24 Apr 2023 06:40:12 +0100 Message-Id: <20230424054105.1579315-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315147580100003 Content-Type: text/plain; charset="utf-8" This is common code in most qemu_{ld,st} slow paths, moving two registers when there may be overlap between sources and destinations. At present, this is only used by 32-bit hosts for 64-bit data, but will shortly be used for more than that. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg.c | 69 ++++++++++++++++++++++++++++++++++++--- tcg/arm/tcg-target.c.inc | 44 ++++++++++--------------- tcg/i386/tcg-target.c.inc | 19 +++++------ 3 files changed, 90 insertions(+), 42 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index fde5ccc57c..cfd3262a4a 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -115,8 +115,7 @@ static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg = ret, TCGReg arg); static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g); -static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) - __attribute__((unused)); +static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2= ); static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); static void tcg_out_goto_tb(TCGContext *s, int which); static void tcg_out_op(TCGContext *s, TCGOpcode opc, @@ -354,6 +353,14 @@ void tcg_raise_tb_overflow(TCGContext *s) siglongjmp(s->jmp_trans, -2); } =20 +typedef struct TCGMovExtend { + TCGReg dst; + TCGReg src; + TCGType dst_type; + TCGType src_type; + MemOp src_ext; +} TCGMovExtend; + /** * tcg_out_movext -- move and extend * @s: tcg context @@ -365,9 +372,8 @@ void tcg_raise_tb_overflow(TCGContext *s) * * Move or extend @src into @dst, depending on @src_ext and the types. */ -static void __attribute__((unused)) -tcg_out_movext(TCGContext *s, TCGType dst_type, TCGReg dst, - TCGType src_type, MemOp src_ext, TCGReg src) +static void tcg_out_movext(TCGContext *s, TCGType dst_type, TCGReg dst, + TCGType src_type, MemOp src_ext, TCGReg src) { switch (src_ext) { case MO_UB: @@ -417,6 +423,59 @@ tcg_out_movext(TCGContext *s, TCGType dst_type, TCGReg= dst, } } =20 +/* Minor variations on a theme, using a structure. */ +static void tcg_out_movext1_new_src(TCGContext *s, const TCGMovExtend *i, + TCGReg src) +{ + tcg_out_movext(s, i->dst_type, i->dst, i->src_type, i->src_ext, src); +} + +static void tcg_out_movext1(TCGContext *s, const TCGMovExtend *i) +{ + tcg_out_movext1_new_src(s, i, i->src); +} + +/** + * tcg_out_movext2 -- move and extend two pair + * @s: tcg context + * @i1: first move description + * @i2: second move description + * @scratch: temporary register, or -1 for none + * + * As tcg_out_movext, for both @i1 and @i2, caring for overlap + * between the sources and destinations. + */ + +static void __attribute__((unused)) +tcg_out_movext2(TCGContext *s, const TCGMovExtend *i1, + const TCGMovExtend *i2, int scratch) +{ + TCGReg src1 =3D i1->src; + TCGReg src2 =3D i2->src; + + if (i1->dst !=3D src2) { + tcg_out_movext1(s, i1); + tcg_out_movext1(s, i2); + return; + } + if (i2->dst =3D=3D src1) { + TCGType src1_type =3D i1->src_type; + TCGType src2_type =3D i2->src_type; + + if (tcg_out_xchg(s, MAX(src1_type, src2_type), src1, src2)) { + /* The data is now in the correct registers, now extend. */ + src1 =3D i2->src; + src2 =3D i1->src; + } else { + tcg_debug_assert(scratch >=3D 0); + tcg_out_mov(s, src1_type, scratch, src1); + src1 =3D scratch; + } + } + tcg_out_movext1_new_src(s, i2, src2); + tcg_out_movext1_new_src(s, i1, src1); +} + #define C_PFX1(P, A) P##A #define C_PFX2(P, A, B) P##A##_##B #define C_PFX3(P, A, B, C) P##A##_##B##_##C diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 8d769ca0a2..83c818a58b 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1545,7 +1545,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, MemOpIdx oi, =20 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGReg argreg, datalo, datahi; + TCGReg argreg; MemOpIdx oi =3D lb->oi; MemOp opc =3D get_memop(oi); =20 @@ -1565,22 +1565,16 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) /* Use the canonical unsigned helpers and minimize icache usage. */ tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); =20 - datalo =3D lb->datalo_reg; - datahi =3D lb->datahi_reg; if ((opc & MO_SIZE) =3D=3D MO_64) { - if (datalo !=3D TCG_REG_R1) { - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); - tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); - } else if (datahi !=3D TCG_REG_R0) { - tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); - } else { - tcg_out_mov_reg(s, COND_AL, TCG_REG_TMP, TCG_REG_R0); - tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_TMP); - } + TCGMovExtend ext[2] =3D { + { .dst =3D lb->datalo_reg, .dst_type =3D TCG_TYPE_I32, + .src =3D TCG_REG_R0, .src_type =3D TCG_TYPE_I32, .src_ext = =3D MO_UL }, + { .dst =3D lb->datahi_reg, .dst_type =3D TCG_TYPE_I32, + .src =3D TCG_REG_R1, .src_type =3D TCG_TYPE_I32, .src_ext = =3D MO_UL }, + }; + tcg_out_movext2(s, &ext[0], &ext[1], TCG_REG_TMP); } else { - tcg_out_movext(s, TCG_TYPE_I32, datalo, + tcg_out_movext(s, TCG_TYPE_I32, lb->datalo_reg, TCG_TYPE_I32, opc & MO_SSIZE, TCG_REG_R0); } =20 @@ -1663,17 +1657,15 @@ static bool tcg_out_fail_alignment(TCGContext *s, T= CGLabelQemuLdst *l) =20 if (TARGET_LONG_BITS =3D=3D 64) { /* 64-bit target address is aligned into R2:R3. */ - if (l->addrhi_reg !=3D TCG_REG_R2) { - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, l->addrlo_reg); - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, l->addrhi_reg); - } else if (l->addrlo_reg !=3D TCG_REG_R3) { - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, l->addrhi_reg); - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, l->addrlo_reg); - } else { - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R1, TCG_REG_R2); - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, TCG_REG_R3); - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, TCG_REG_R1); - } + TCGMovExtend ext[2] =3D { + { .dst =3D TCG_REG_R2, .dst_type =3D TCG_TYPE_I32, + .src =3D l->addrlo_reg, + .src_type =3D TCG_TYPE_I32, .src_ext =3D MO_UL }, + { .dst =3D TCG_REG_R3, .dst_type =3D TCG_TYPE_I32, + .src =3D l->addrhi_reg, + .src_type =3D TCG_TYPE_I32, .src_ext =3D MO_UL }, + }; + tcg_out_movext2(s, &ext[0], &ext[1], TCG_REG_TMP); } else { tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R1, l->addrlo_reg); } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index ce87f8fbc9..238a75b17e 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1916,7 +1916,6 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) { MemOpIdx oi =3D l->oi; MemOp opc =3D get_memop(oi); - TCGReg data_reg; tcg_insn_unit **label_ptr =3D &l->label_ptr[0]; =20 /* resolve label address */ @@ -1953,18 +1952,16 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) =20 tcg_out_branch(s, 1, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 - data_reg =3D l->datalo_reg; if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { - if (data_reg =3D=3D TCG_REG_EDX) { - /* xchg %edx, %eax */ - tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX, 0, 0, 0); - tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EAX); - } else { - tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); - tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EDX); - } + TCGMovExtend ext[2] =3D { + { .dst =3D l->datalo_reg, .dst_type =3D TCG_TYPE_I32, + .src =3D TCG_REG_EAX, .src_type =3D TCG_TYPE_I32, .src_ext = =3D MO_UL }, + { .dst =3D l->datahi_reg, .dst_type =3D TCG_TYPE_I32, + .src =3D TCG_REG_EDX, .src_type =3D TCG_TYPE_I32, .src_ext = =3D MO_UL }, + }; + tcg_out_movext2(s, &ext[0], &ext[1], -1); } else { - tcg_out_movext(s, l->type, data_reg, + tcg_out_movext(s, l->type, l->datalo_reg, TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_EAX); } =20 --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682314997; cv=none; d=zohomail.com; s=zohoarc; b=I2wJw2YLPWKm4vxK7rfd6MmC36fo3p0ic7vnVVLciCVtM2c99FRFbRhPWl5m6xil1O8Pp3j8NyPodN/wV3LasZ5h+feB/SimAYDyGfCKiY/8xKcFiSeFePgzGZ+R9UQWOs9HXLmBSVuqrbo/nXu72Bj/TIhwH9BqvsuMGtJRak4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682314997; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314869; x=1684906869; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EKDWuG1RsGfawxFgTXNCSIYTsIrz7bejDrOWGz/hlKg=; b=s/GfKfd6eDqIh25T9yrwlpvU6jgRbjZmmZIT8QrD8RxXJMNQ4QLfNSm6CLhACpBovj YlImO0mBmsOtghPuzsGNO3ql2nGMRXMI0g3yq9MnBxuALiap/hbmsRJBwVodkHES6VFK ey61KecPnyuDZyf5hXaXNkqeDKV+BSGgySW7tp4iYvVRELnAkG/N4UdFWr0nKwAAOSA1 tma/aQAprOOuJnGnNF1lU9ObigcYYkYFEa7v/XlTpJ+jaPybqhR3ajcGpK8ETfk/rNf+ GKxmpTObsxBRqtu7JaXywULriUxRnJqP5heV1uFapMfcXM37AwGNcB77II/wYmm88WTY vh8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314869; x=1684906869; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EKDWuG1RsGfawxFgTXNCSIYTsIrz7bejDrOWGz/hlKg=; b=WxVCq/UbjTc8wRpNBxVMs3widk72oDmbvQ1kFEpuivb4vIxI1vQQYnHqBM0XrMf6EO /jelg7bI8mpd98rCwAK1fzNcetKZL06OmafzPvk+Ar+8j8o66WjTlJJQMjv2RUaI5e6N cq3Qu2eSd5PjM+pNNKvDMrPk30UCzJcLHi+4RNW3s8IlkdTcb6V9tHkHfDbmKIpbxzCY E5s8IQZxqyr9NfiUV7WZSY0VKFCkY3yks+K3pLmeqoxVKEKHeF1EzeklTWXU60hfs3xi t0I8U/0Ql4X/+j2DxIMf5a0KwsNq4Ljwm06DTZbHfjXbi3nzyNH1gaymjYQSadI/HMUO 1DFA== X-Gm-Message-State: AAQBX9cfpXimBY8Khd3Tax1799NgJ9Qyly4D37JpD4bqbmzzldiQW5Lv PFAWysobNJdGVWGS6fdk48tW3WPgIKCLrDucqzKxmA== X-Google-Smtp-Source: AKy350b/vQGa7yaeeWFtroAX0jyRdMcQuYhj/XXOs5uPy6ztCYCs/QuUzoYZsIALkaZ18VI/BFaCog== X-Received: by 2002:adf:d08a:0:b0:2f8:3225:2bc1 with SMTP id y10-20020adfd08a000000b002f832252bc1mr8795186wrh.41.1682314869312; Sun, 23 Apr 2023 22:41:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 05/57] tcg/i386: Rationalize args to tcg_out_qemu_{ld,st} Date: Mon, 24 Apr 2023 06:40:13 +0100 Message-Id: <20230424054105.1579315-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682314998583100001 Interpret the variable argument placement in the caller. Pass data_type instead of is64 -- there are several places where we already convert back from bool to type. Clean things up by using type throughout. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 111 +++++++++++++++++--------------------- 1 file changed, 50 insertions(+), 61 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 238a75b17e..b986109d77 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1886,8 +1886,8 @@ static inline void tcg_out_tlb_load(TCGContext *s, TC= GReg addrlo, TCGReg addrhi, * Record the context of a call to the out of line helper code for the slo= w path * for a load or store, so that we can later generate the correct helper c= ode */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64, - MemOpIdx oi, +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, + TCGType type, MemOpIdx oi, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, tcg_insn_unit *raddr, @@ -1897,7 +1897,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, bool is_64, =20 label->is_ld =3D is_ld; label->oi =3D oi; - label->type =3D is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32; + label->type =3D type; label->datalo_reg =3D datalo; label->datahi_reg =3D datahi; label->addrlo_reg =3D addrlo; @@ -2154,11 +2154,10 @@ static inline int setup_guest_base_seg(void) =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, TCGReg base, int index, intptr_t ofs, - int seg, bool is64, MemOp memop) + int seg, TCGType type, MemOp memop) { - TCGType type =3D is64 ? TCG_TYPE_I64 : TCG_TYPE_I32; bool use_movbe =3D false; - int rexw =3D is64 * P_REXW; + int rexw =3D (type =3D=3D TCG_TYPE_I32 ? 0 : P_REXW); int movop =3D OPC_MOVL_GvEv; =20 /* Do big-endian loads with movbe. */ @@ -2248,50 +2247,34 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, } } =20 -/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and - EAX. It will be useful once fixed registers globals are less - common. */ -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) +static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, TCGType data_type) { - TCGReg datalo, datahi, addrlo; - TCGReg addrhi __attribute__((unused)); - MemOpIdx oi; - MemOp opc; + MemOp opc =3D get_memop(oi); + #if defined(CONFIG_SOFTMMU) - int mem_index; tcg_insn_unit *label_ptr[2]; -#else - unsigned a_bits; -#endif =20 - datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); - -#if defined(CONFIG_SOFTMMU) - mem_index =3D get_mmuidx(oi); - - tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, + tcg_out_tlb_load(s, addrlo, addrhi, get_mmuidx(oi), opc, label_ptr, offsetof(CPUTLBEntry, addr_read)); =20 /* TLB Hit. */ - tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, is64, = opc); + tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, + -1, 0, 0, data_type, opc); =20 /* Record the current context of a load into ldst label */ - add_qemu_ldst_label(s, true, is64, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #else - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } =20 tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index, x86_guest_base_offset, x86_guest_base_seg, - is64, opc); + data_type, opc); #endif } =20 @@ -2347,40 +2330,26 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, } } =20 -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) +static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, TCGType data_type) { - TCGReg datalo, datahi, addrlo; - TCGReg addrhi __attribute__((unused)); - MemOpIdx oi; - MemOp opc; + MemOp opc =3D get_memop(oi); + #if defined(CONFIG_SOFTMMU) - int mem_index; tcg_insn_unit *label_ptr[2]; -#else - unsigned a_bits; -#endif =20 - datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); - -#if defined(CONFIG_SOFTMMU) - mem_index =3D get_mmuidx(oi); - - tcg_out_tlb_load(s, addrlo, addrhi, mem_index, opc, + tcg_out_tlb_load(s, addrlo, addrhi, get_mmuidx(oi), opc, label_ptr, offsetof(CPUTLBEntry, addr_write)); =20 /* TLB Hit. */ tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc); =20 /* Record the current context of a store into ldst label */ - add_qemu_ldst_label(s, false, is64, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #else - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); } @@ -2675,17 +2644,37 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, 0); + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I32); + } else { + tcg_out_qemu_ld(s, a0, -1, a1, a2, args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, 1); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_ld(s, a0, -1, a1, -1, a2, TCG_TYPE_I64); + } else if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_ld(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); + } break; case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st8_i32: - tcg_out_qemu_st(s, args, 0); + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I32); + } else { + tcg_out_qemu_st(s, a0, -1, a1, a2, args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, 1); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_st(s, a0, -1, a1, -1, a2, TCG_TYPE_I64); + } else if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_st(s, a0, a1, a2, -1, args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); + } break; =20 OP_32_64(mulu2): --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315009; cv=none; d=zohomail.com; s=zohoarc; b=SCywXWU/VznKp31nwj3y8mDptZEfGBhbRALQQqkY8JHBT/7nokj6sbtp1gKaQEo9Olgl4aKtScFuobyToKD69OshNTQZ76k1UJhvVKNdqlPBOBx/mmD6jLA7HMYcYAxWLL9JLR45fwk4VpyWoOCyVt/aI9g7kTE6eLzejQq9ubk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315009; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eP2UcvTSjxkcvSWlSrM0QTbqla0I8aaMQCx8SFdrxDo=; b=g3jvDZOWyx/RvkoRE49QS5jfaQ2BN17DuNqd7rJNjR5RoYU0cox//CKyEzH0IC6ZAXvFpkdCPkqQWobK5pNmXN6MJQvcDKUSxvkQ76ClsAAUaMFnGbffGlucehCwJzSqV/7biptcHWAKn7/AI1qm8FaJEpIt3SPj+5EyvwONqYY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315009922610.0808952854107; Sun, 23 Apr 2023 22:43:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqoxL-0005Vq-JQ; Mon, 24 Apr 2023 01:41:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqox6-0005Lo-5i for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:28 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqowr-0004Fw-Kn for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:26 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-3f18dacd392so22110645e9.0 for ; Sun, 23 Apr 2023 22:41:11 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314870; x=1684906870; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eP2UcvTSjxkcvSWlSrM0QTbqla0I8aaMQCx8SFdrxDo=; b=IlCNtRwB1/xQU7iLzHM5XbtmCDFsCOjgZJmIipafeiIB9+1OrNeOkGdrqZYeQSwhKt Hy8GuUI4mthHOr1I8q4SjUqNqv59sQuw4X5cqQuPo2F4N3eA1YVEvygVUzz4/XT11iVk T0sMF0/j7IVmdIubK7vkDSuUDEmoYbmzqMPvOAXtboeEesfuFXp8N/NxnYoGVmkuIp5K h5fAbPcPwIoPR0swog010AFsfdl092RuKQlPGLNOtEaIZl/NOCMSKegu2oYJ0rtBbPnE qUWn7rMbyscmsuqGwjOjeatYjYqaampTEwkFqMyty4MypGZOa0AR0Ky7tgSiGexwDtLF PDOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314870; x=1684906870; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eP2UcvTSjxkcvSWlSrM0QTbqla0I8aaMQCx8SFdrxDo=; b=eqEVhVKHnrLNurXFNs7t8VF1ShH3MZw7qGlU6PmSP90lWa0Ul0VaEYqrKhzgbUICdX FqmG9QQuX/luw8mpUwqUMS4pTeRyBKFc7r5ovtgM5Ix0oGXSUIq4LvV25Ysv/XZQQ+Ng eAT/tqWVi+TWKiFc+rPxgnuEnayv2Q1sQCQA7T8eTTjtL1CcrbAIQrI4VfGa6H7Detb0 FnVxIupQ/SvhmuPSFNTPrCfxDyoJnBxzQpyR8105VSe5yCBjlepFXy2w6EWzemRkl5yK trcjB2f2OycgFPf0wSp1jFoKk6e5GOTRjLkQ7XsTP1uzaQXKZtWDwYNJfHQNsGPZH9bp kuUA== X-Gm-Message-State: AAQBX9eUAdHGxy5wM2EczkgGchc/svXrVIxHI4kM8rdgsW4WvCK+wUD9 aKPfKUxMlbnmlHr3F2h4Y40XgkYp21El08fzvjfKmQ== X-Google-Smtp-Source: AKy350bd85CsA+BazkdL6HS42naNU9zdwGzkPGKh6uq1ZYwkBqGm+Q7ZbX1SRdNm2Xdrtq7MlvWmLA== X-Received: by 2002:a5d:6e06:0:b0:2ce:fd37:938c with SMTP id h6-20020a5d6e06000000b002cefd37938cmr8682496wrz.50.1682314869885; Sun, 23 Apr 2023 22:41:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 06/57] tcg/i386: Generalize multi-part load overlap test Date: Mon, 24 Apr 2023 06:40:14 +0100 Message-Id: <20230424054105.1579315-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315012082100007 Content-Type: text/plain; charset="utf-8" Test for both base and index; use datahi as a temporary, overwritten by the final load. Always perform the loads in ascending order, so that any (user-only) fault sees the correct address. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index b986109d77..794d440a9e 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -2223,23 +2223,22 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, base, index, 0, ofs); + break; + } + if (use_movbe) { + TCGReg t =3D datalo; + datalo =3D datahi; + datahi =3D t; + } + if (base =3D=3D datalo || index =3D=3D datalo) { + tcg_out_modrm_sib_offset(s, OPC_LEA, datahi, base, index, 0, o= fs); + tcg_out_modrm_offset(s, movop + seg, datalo, datahi, 0); + tcg_out_modrm_offset(s, movop + seg, datahi, datahi, 4); } else { - if (use_movbe) { - TCGReg t =3D datalo; - datalo =3D datahi; - datahi =3D t; - } - if (base !=3D datalo) { - tcg_out_modrm_sib_offset(s, movop + seg, datalo, - base, index, 0, ofs); - tcg_out_modrm_sib_offset(s, movop + seg, datahi, - base, index, 0, ofs + 4); - } else { - tcg_out_modrm_sib_offset(s, movop + seg, datahi, - base, index, 0, ofs + 4); - tcg_out_modrm_sib_offset(s, movop + seg, datalo, - base, index, 0, ofs); - } + tcg_out_modrm_sib_offset(s, movop + seg, datalo, + base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, movop + seg, datahi, + base, index, 0, ofs + 4); } break; default: --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315563; cv=none; d=zohomail.com; s=zohoarc; b=G4TCuPJF3s3hsNNr4JusAjP5HWSqP38Aoi/LWlKOqSI4UjCthY9vTANiN0uv+sE5iHdj42QvMOOH5ZbRDJ2KrxXuQGfYobRtoPfnpaLY9z7wGdWUWKzwAk+jRrmOWOGN9ehr4o5/MgQKFrhZ8/8/wZixNox1+SmfmX7d0UTCiMk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315563; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YIgckz6VVGA+z4mpJFQpy6mrt/mutSB41Mg7USic7Pg=; b=n3y2U7Fk27BkFAZn9bipphrU3oRqmrFDR70Rg9Mw6FIxhMbe+rTzk7HoouFYaUgMXys5lc1IhjzHN/KN7KnJyBTfXNya9aoP77wJ4SWYqq6TNhdDYjB/fWLuAIWxNjXlopMSbGUSPiouCPFj8dE6SnAOQJF65eZPAasu4X/RJzs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315563299349.9453658015941; Sun, 23 Apr 2023 22:52:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqoya-0006fy-L0; Mon, 24 Apr 2023 01:43:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqoxD-0005Qu-SE for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:38 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqowt-0004GG-5m for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:35 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-2fa0ce30ac2so3625851f8f.3 for ; Sun, 23 Apr 2023 22:41:11 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314870; x=1684906870; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YIgckz6VVGA+z4mpJFQpy6mrt/mutSB41Mg7USic7Pg=; b=ebDrgSRCst0G1+Y66lHpi0pawPt54vZrm+crbLhUBbfLHojBey2TEUIISOrtmg4sVm j8fwsF/4DoAz26v3rJ65h3631iCCLACjDNlITPHoxvNCoOCzcr1Ft5cpAEBhspCAtBf0 nEveodQusmsD8eMhHxC6h1ZpIEmZz076Y9GHBt4/F+pB567gQviT6/vgfXonUKRiYWaZ 5eFDLXNu0FrwtopyjtmLYiPEfH6Yc49ovOUhwkACf8sbXK4EEWN4enlEg2mmT36jdHwF DW0mNnO8Ap3aNIf9+mOA1C9PmbapZlI3zNfbNBBkGBJGSfZAAtcHCWE0lt3VUmmJSNSq pRBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314870; x=1684906870; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YIgckz6VVGA+z4mpJFQpy6mrt/mutSB41Mg7USic7Pg=; b=dv372qUwg9uE7EwNxpYkNt8jHeqevIHo46aJhrCAZ3bh6T4rhOwh0mbijbNvaw7ExK LJPKbcr6sT1BHNcC0neafhVOC5/gsJTKEWRj3kyOp0fzPEZT5OSIhGIW9h6aHm2UflAk ZZP+pYiuArMqwN7PpNAyXIt5M6hDdDh4LLWwIRvOVSLb0ylwhZ7idtDpd7Wvzq/nElJh NpzFSsQzabXUgi36ZOEcWKmyI3gL8oGm+2lmoUo70uUxL2AaEPTJKqOCRoxefMFzkQY1 AhfVtI50MJkt15DR8dzCR8pLREkEulVGTf2snThSolHFsPcbhq28zM7Zz94roHHDu2fC 6nwQ== X-Gm-Message-State: AAQBX9ewZXz4y3FEW1tS9P7KVNfWu4u6ACtQfTtmOCn8P3VFNrt0dCo/ 7THZMUYAEw0Frt7Br37oe5rogefoq+EY9turPZsxwQ== X-Google-Smtp-Source: AKy350Y1BfSeuyAshaQwyewAJX7hIlGmwJ1X2HOqj2Xd8PQiRCfhz7cYdR64lMPDSMjlzt/zFCOCgA== X-Received: by 2002:a5d:40c6:0:b0:2ef:b052:1296 with SMTP id b6-20020a5d40c6000000b002efb0521296mr8954146wrq.22.1682314870486; Sun, 23 Apr 2023 22:41:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 07/57] tcg/i386: Introduce HostAddress Date: Mon, 24 Apr 2023 06:40:15 +0100 Message-Id: <20230424054105.1579315-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315565214100003 Content-Type: text/plain; charset="utf-8" Collect the 4 potential parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st}_direct to use it. Reorg guest_base handling to use it. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/i386/tcg-target.c.inc | 165 +++++++++++++++++++++----------------- 1 file changed, 90 insertions(+), 75 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 794d440a9e..b6750c364a 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1753,6 +1753,13 @@ static void tcg_out_nopn(TCGContext *s, int n) tcg_out8(s, 0x90); } =20 +typedef struct { + TCGReg base; + int index; + int ofs; + int seg; +} HostAddress; + #if defined(CONFIG_SOFTMMU) /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) @@ -2115,17 +2122,13 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) return tcg_out_fail_alignment(s, l); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 -# define x86_guest_base_seg 0 -# define x86_guest_base_index -1 -# define x86_guest_base_offset guest_base -#else -static int x86_guest_base_seg; -static int x86_guest_base_index =3D -1; -static int32_t x86_guest_base_offset; -# if defined(__x86_64__) && defined(__linux__) -# include -# include +static HostAddress x86_guest_base =3D { + .index =3D -1 +}; + +#if defined(__x86_64__) && defined(__linux__) +# include +# include int arch_prctl(int code, unsigned long addr); static inline int setup_guest_base_seg(void) { @@ -2134,8 +2137,9 @@ static inline int setup_guest_base_seg(void) } return 0; } -# elif defined (__FreeBSD__) || defined (__FreeBSD_kernel__) -# include +#elif defined(__x86_64__) && \ + (defined (__FreeBSD__) || defined (__FreeBSD_kernel__)) +# include static inline int setup_guest_base_seg(void) { if (sysarch(AMD64_SET_GSBASE, &guest_base) =3D=3D 0) { @@ -2143,18 +2147,16 @@ static inline int setup_guest_base_seg(void) } return 0; } -# else +#else static inline int setup_guest_base_seg(void) { return 0; } -# endif -#endif +#endif /* setup_guest_base_seg */ #endif /* SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, - TCGReg base, int index, intptr_t ofs, - int seg, TCGType type, MemOp memop) + HostAddress h, TCGType type, MemOp memo= p) { bool use_movbe =3D false; int rexw =3D (type =3D=3D TCG_TYPE_I32 ? 0 : P_REXW); @@ -2169,60 +2171,61 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, =20 switch (memop & MO_SSIZE) { case MO_UB: - tcg_out_modrm_sib_offset(s, OPC_MOVZBL + seg, datalo, - base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVZBL + h.seg, datalo, + h.base, h.index, 0, h.ofs); break; case MO_SB: - tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + seg, datalo, - base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVSBL + rexw + h.seg, datalo, + h.base, h.index, 0, h.ofs); break; case MO_UW: if (use_movbe) { /* There is no extending movbe; only low 16-bits are modified.= */ - if (datalo !=3D base && datalo !=3D index) { + if (datalo !=3D h.base && datalo !=3D h.index) { /* XOR breaks dependency chains. */ tgen_arithr(s, ARITH_XOR, datalo, datalo); - tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + se= g, - datalo, base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.= seg, + datalo, h.base, h.index, 0, h.ofs= ); } else { - tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + se= g, - datalo, base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.= seg, + datalo, h.base, h.index, 0, h.ofs= ); tcg_out_ext16u(s, datalo, datalo); } } else { - tcg_out_modrm_sib_offset(s, OPC_MOVZWL + seg, datalo, - base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVZWL + h.seg, datalo, + h.base, h.index, 0, h.ofs); } break; case MO_SW: if (use_movbe) { - tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, - datalo, base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + h.seg, + datalo, h.base, h.index, 0, h.ofs); tcg_out_ext16s(s, type, datalo, datalo); } else { - tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + seg, - datalo, base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + h.seg, + datalo, h.base, h.index, 0, h.ofs); } break; case MO_UL: - tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, o= fs); + tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, + h.base, h.index, 0, h.ofs); break; #if TCG_TARGET_REG_BITS =3D=3D 64 case MO_SL: if (use_movbe) { - tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + seg, datalo, - base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + h.seg, datalo, + h.base, h.index, 0, h.ofs); tcg_out_ext32s(s, datalo, datalo); } else { - tcg_out_modrm_sib_offset(s, OPC_MOVSLQ + seg, datalo, - base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVSLQ + h.seg, datalo, + h.base, h.index, 0, h.ofs); } break; #endif case MO_UQ: if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, - base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, + h.base, h.index, 0, h.ofs); break; } if (use_movbe) { @@ -2230,15 +2233,16 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, datalo =3D datahi; datahi =3D t; } - if (base =3D=3D datalo || index =3D=3D datalo) { - tcg_out_modrm_sib_offset(s, OPC_LEA, datahi, base, index, 0, o= fs); - tcg_out_modrm_offset(s, movop + seg, datalo, datahi, 0); - tcg_out_modrm_offset(s, movop + seg, datahi, datahi, 4); + if (h.base =3D=3D datalo || h.index =3D=3D datalo) { + tcg_out_modrm_sib_offset(s, OPC_LEA, datahi, + h.base, h.index, 0, h.ofs); + tcg_out_modrm_offset(s, movop + h.seg, datalo, datahi, 0); + tcg_out_modrm_offset(s, movop + h.seg, datahi, datahi, 4); } else { - tcg_out_modrm_sib_offset(s, movop + seg, datalo, - base, index, 0, ofs); - tcg_out_modrm_sib_offset(s, movop + seg, datahi, - base, index, 0, ofs + 4); + tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, + h.base, h.index, 0, h.ofs); + tcg_out_modrm_sib_offset(s, movop + h.seg, datahi, + h.base, h.index, 0, h.ofs + 4); } break; default: @@ -2251,6 +2255,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= alo, TCGReg datahi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); + HostAddress h; =20 #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[2]; @@ -2259,8 +2264,11 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg da= talo, TCGReg datahi, label_ptr, offsetof(CPUTLBEntry, addr_read)); =20 /* TLB Hit. */ - tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, - -1, 0, 0, data_type, opc); + h.base =3D TCG_REG_L1; + h.index =3D -1; + h.ofs =3D 0; + h.seg =3D 0; + tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, opc); =20 /* Record the current context of a load into ldst label */ add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi, @@ -2271,15 +2279,14 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } =20 - tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index, - x86_guest_base_offset, x86_guest_base_seg, - data_type, opc); + h =3D x86_guest_base; + h.base =3D addrlo; + tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, opc); #endif } =20 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, - TCGReg base, int index, intptr_t ofs, - int seg, MemOp memop) + HostAddress h, MemOp memop) { bool use_movbe =3D false; int movop =3D OPC_MOVL_EvGv; @@ -2298,30 +2305,31 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg datalo, TCGReg datahi, case MO_8: /* This is handled with constraints on INDEX_op_qemu_st8_i32. */ tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || datalo < 4); - tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg, - datalo, base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + h.seg, + datalo, h.base, h.index, 0, h.ofs); break; case MO_16: - tcg_out_modrm_sib_offset(s, movop + P_DATA16 + seg, datalo, - base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, movop + P_DATA16 + h.seg, datalo, + h.base, h.index, 0, h.ofs); break; case MO_32: - tcg_out_modrm_sib_offset(s, movop + seg, datalo, base, index, 0, o= fs); + tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, + h.base, h.index, 0, h.ofs); break; case MO_64: if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_modrm_sib_offset(s, movop + P_REXW + seg, datalo, - base, index, 0, ofs); + tcg_out_modrm_sib_offset(s, movop + P_REXW + h.seg, datalo, + h.base, h.index, 0, h.ofs); } else { if (use_movbe) { TCGReg t =3D datalo; datalo =3D datahi; datahi =3D t; } - tcg_out_modrm_sib_offset(s, movop + seg, datalo, - base, index, 0, ofs); - tcg_out_modrm_sib_offset(s, movop + seg, datahi, - base, index, 0, ofs + 4); + tcg_out_modrm_sib_offset(s, movop + h.seg, datalo, + h.base, h.index, 0, h.ofs); + tcg_out_modrm_sib_offset(s, movop + h.seg, datahi, + h.base, h.index, 0, h.ofs + 4); } break; default: @@ -2334,6 +2342,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= alo, TCGReg datahi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); + HostAddress h; =20 #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[2]; @@ -2342,7 +2351,11 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg da= talo, TCGReg datahi, label_ptr, offsetof(CPUTLBEntry, addr_write)); =20 /* TLB Hit. */ - tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc); + h.base =3D TCG_REG_L1; + h.index =3D -1; + h.ofs =3D 0; + h.seg =3D 0; + tcg_out_qemu_st_direct(s, datalo, datahi, h, opc); =20 /* Record the current context of a store into ldst label */ add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi, @@ -2353,8 +2366,10 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg da= talo, TCGReg datahi, tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); } =20 - tcg_out_qemu_st_direct(s, datalo, datahi, addrlo, x86_guest_base_index, - x86_guest_base_offset, x86_guest_base_seg, opc); + h =3D x86_guest_base; + h.base =3D addrlo; + + tcg_out_qemu_st_direct(s, datalo, datahi, h, opc); #endif } =20 @@ -4060,18 +4075,18 @@ static void tcg_target_qemu_prologue(TCGContext *s) (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4 + stack_addend); #else -# if !defined(CONFIG_SOFTMMU) && TCG_TARGET_REG_BITS =3D=3D 64 +# if !defined(CONFIG_SOFTMMU) if (guest_base) { int seg =3D setup_guest_base_seg(); if (seg !=3D 0) { - x86_guest_base_seg =3D seg; + x86_guest_base.seg =3D seg; } else if (guest_base =3D=3D (int32_t)guest_base) { - x86_guest_base_offset =3D guest_base; + x86_guest_base.ofs =3D guest_base; } else { /* Choose R12 because, as a base, it requires a SIB byte. */ - x86_guest_base_index =3D TCG_REG_R12; - tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base_index, guest_base= ); - tcg_regset_set_reg(s->reserved_regs, x86_guest_base_index); + x86_guest_base.index =3D TCG_REG_R12; + tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base.index, guest_base= ); + tcg_regset_set_reg(s->reserved_regs, x86_guest_base.index); } } # endif --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682314998; cv=none; d=zohomail.com; s=zohoarc; b=AXVSpsRuk9+ShExpmgvZv3CuE/Cnp3DCU0l3gd5LqquynjU3x0tmM4UEVaoV6UFhXI2AnX8wOVwsUGD1QCnWgjwhQFcfg+eNqh9IjctOyw56kaertG1IUL89sutNNcmTYZ4cQrU+TYu7KacopIHVCc+2Z89tHl0ZJC09EI3n3uc= ARC-Message-Signature: i=1; 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[46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314871; x=1684906871; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DrJzjH8IZNJFUh651D62ccr1sIbRumHAtxHaJjoHMgY=; b=c85MFEtHFsWLIv+UlVFh5F6GA6w/hwnShW05tlZT+8XoQNQbzuQfASnbbalo83pLAf Ih5tXA4h5ObhOxSZrUXqZFbvEuXn0K6IRcnuOFBfHEThOfRtBFhmQSrytGztXJZGMJ9+ N538PvO/7Bvo2Luldu1epSsRhf1HmPwQhRfTMSb/5MzhzXHYRuZlzE5XwNG2E6T3EdrJ aBkoZn1fIZ0YE+tu1KQMljBMIruZ8iCgLz8vHrnxXc2BrsT68hG8OH8r1fe8A/GPJleP 6qzFgoTGIs4JGjDj78bvyxBvOJP9pBXbxNjbJJuzVGQw2NSYqqAO/7K5haN838iqmeVM BUIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314871; x=1684906871; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DrJzjH8IZNJFUh651D62ccr1sIbRumHAtxHaJjoHMgY=; b=XJmUIYGOY2uRXvSfJfzUbpex0IGOXNTP2G7OoUsGP4i4YQybwequMi9mgTbwwmr9J0 Ne6XOX5oIuxhlpBVgxl8tK9oJNoaPk7Uy8x4qjIsSmgOJ65A38GAjDyPqIDISjmQWmLK KgI/n5pSd38Y4SMnQfXMgbdi3zp/kF4pRkyK9uhxsHT86D/H59swenKOEDMbwltLms3I IKmtx7aJeoF3C2KwZtPJyY0+hfwmY9z+MUPlFwH4qZbvxr7xN/gdw5VB7ZfhCcSih26x 6WOFYmBIZurIo5TXVPgvgIqTuGwFTAECYJmjQzAMZRHFZdKvugnH3yUcFF5gYVYdYWkj lK8w== X-Gm-Message-State: AAQBX9ccU8eVmyH6S+s6diwv/bGCdnyKbuLw2pHlzQTNZxuKwx6/J153 Chr6V1TyAaFiEROzLgFgsCF5gPggaQoVCNW/j1qHVA== X-Google-Smtp-Source: AKy350YZMXeI0pEPtT3uTarD5sW/7JF0wr29PmscpjKwbQCjaYzUfmZ+54BT1v4H1tY4xUcnorqSrw== X-Received: by 2002:a5d:6445:0:b0:2ff:3f47:1e99 with SMTP id d5-20020a5d6445000000b002ff3f471e99mr8412256wrw.41.1682314870982; Sun, 23 Apr 2023 22:41:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 08/57] tcg/i386: Drop r0+r1 local variables from tcg_out_tlb_load Date: Mon, 24 Apr 2023 06:40:16 +0100 Message-Id: <20230424054105.1579315-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682314998988100003 Content-Type: text/plain; charset="utf-8" Use TCG_REG_L[01] constants directly. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/i386/tcg-target.c.inc | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index b6750c364a..7a02f79f1b 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1812,8 +1812,6 @@ static inline void tcg_out_tlb_load(TCGContext *s, TC= GReg addrlo, TCGReg addrhi, int mem_index, MemOp opc, tcg_insn_unit **label_ptr, int which) { - const TCGReg r0 =3D TCG_REG_L0; - const TCGReg r1 =3D TCG_REG_L1; TCGType ttype =3D TCG_TYPE_I32; TCGType tlbtype =3D TCG_TYPE_I32; int trexw =3D 0, hrexw =3D 0, tlbrexw =3D 0; @@ -1837,15 +1835,15 @@ static inline void tcg_out_tlb_load(TCGContext *s, = TCGReg addrlo, TCGReg addrhi, } } =20 - tcg_out_mov(s, tlbtype, r0, addrlo); - tcg_out_shifti(s, SHIFT_SHR + tlbrexw, r0, + tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo); + tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); =20 - tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0, + tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0, TLB_MASK_TABLE_OFS(mem_index) + offsetof(CPUTLBDescFast, mask)); =20 - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0, + tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0, TLB_MASK_TABLE_OFS(mem_index) + offsetof(CPUTLBDescFast, table)); =20 @@ -1853,19 +1851,21 @@ static inline void tcg_out_tlb_load(TCGContext *s, = TCGReg addrlo, TCGReg addrhi, copy the address and mask. For lesser alignments, check that we do= n't cross pages for the complete access. */ if (a_bits >=3D s_bits) { - tcg_out_mov(s, ttype, r1, addrlo); + tcg_out_mov(s, ttype, TCG_REG_L1, addrlo); } else { - tcg_out_modrm_offset(s, OPC_LEA + trexw, r1, addrlo, s_mask - a_ma= sk); + tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1, + addrlo, s_mask - a_mask); } tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; - tgen_arithi(s, ARITH_AND + trexw, r1, tlb_mask, 0); + tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0); =20 - /* cmp 0(r0), r1 */ - tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, r1, r0, which); + /* cmp 0(TCG_REG_L0), TCG_REG_L1 */ + tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, + TCG_REG_L1, TCG_REG_L0, which); =20 /* Prepare for both the fast path add of the tlb addend, and the slow path function argument setup. */ - tcg_out_mov(s, ttype, r1, addrlo); + tcg_out_mov(s, ttype, TCG_REG_L1, addrlo); =20 /* jne slow_path */ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); @@ -1873,8 +1873,8 @@ static inline void tcg_out_tlb_load(TCGContext *s, TC= GReg addrlo, TCGReg addrhi, s->code_ptr +=3D 4; =20 if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - /* cmp 4(r0), addrhi */ - tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, r0, which + 4); + /* cmp 4(TCG_REG_L0), addrhi */ + tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, TCG_REG_L0, which + = 4); =20 /* jne slow_path */ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); @@ -1884,8 +1884,8 @@ static inline void tcg_out_tlb_load(TCGContext *s, TC= GReg addrlo, TCGReg addrhi, =20 /* TLB Hit. */ =20 - /* add addend(r0), r1 */ - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0, + /* add addend(TCG_REG_L0), TCG_REG_L1 */ + tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L1, TCG_REG_L0, offsetof(CPUTLBEntry, addend)); } =20 --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315121; cv=none; d=zohomail.com; s=zohoarc; b=YI/jnP1bKtzZO4I3XJE1rQLY03bO2vVUu5Li127aNwg/P99DeAyH3JKJTQlpX9e6rifTlR+p5PYPwarhuWUiFQG53hES84ms0KqZo/IBxN9kD3yftzXppQ7Rokb3dJ3fWbi9eAkJ233Mt2Fy7sRrPS1Ah9I/KpZY6BlCAXzuL5I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315121; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IJnzORJY4nHB2qHgbe1wyr1FPPmEsXDzn2QzLUICVbI=; b=Z/4oDIawpC14GcFLk3FFqqcHt0oVEIRZRDm73pkmAC26knAxBlrmAYI9MbB/UommWWy4ueIPI9/JRXMgGtLqynj60Mvohdz7XNEW5VPykB9k4jLf0eWGUZ1IrtpWxdXSBt5LyqcFTjG0XXzSLuHBd2fJ/zHN0GXH9fOOcAEb2ks= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315121265848.1842876660467; Sun, 23 Apr 2023 22:45:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqoxL-0005Wd-Qf; Mon, 24 Apr 2023 01:41:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqox6-0005MH-E1 for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:29 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqowt-0004Gs-1c for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:28 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-2f4c431f69cso2315045f8f.0 for ; Sun, 23 Apr 2023 22:41:12 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314871; x=1684906871; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IJnzORJY4nHB2qHgbe1wyr1FPPmEsXDzn2QzLUICVbI=; b=wsrYLo/zEiJ1a2FC+B4pAjorUgO1McKdllwK3A6Rrxz5alsIwaKMGSVQxjZPbSxlrc 1GcnzLeWh2wXA1WCBterba4Bz5K/9jeBG6R0wy+aaegGwV/f/I1Kxz3y53vsBVyY0ZOd YYPJw/urf3rwLn81rTLuO340cBPCkaEXLOoWblgnccdaAOZPvDlnN1S1yc7HHEXpnSvM df6JCt/SYGTueFDS9IMWUmNe/UaXhE6DZwZXhrJ3FW/6f9dUeH3u3nNMoSf+LQUW5Xvc A4hCBcwfpIjKI7/1MCoiUy7QQLN58UX1L+0WquD8vkuk6ppUv/UPh/aTxsOv58vREtZQ 99lQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314871; x=1684906871; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IJnzORJY4nHB2qHgbe1wyr1FPPmEsXDzn2QzLUICVbI=; b=LNjuRBa8v5Q1eEZsUFxuTL/XEnKRK6LnajQHaHUlz2DLswg4iU5B45O6yEcEZZy1ai P77MpZBy/caLQDydPzwBrOnBHTcwOhXX/f87Xf0XL28JklEZta70rvBpx7d9ywUZscB0 h2TT0H4X6XGMytTtY3fMRl7g+w2C7DaYRC6VzRfS3yGyjZrjfZYJp2Z5+nN1MC4rKqn6 2ZG9lQFtVdV0NTaP2Kr3RPrblZ8qXCyW7uAoBHinUTQqmyfAAa4iUXiovxssrBxrNovu hKTOFX9QGojEjoBIQ5/WkE095GEK5ASJF8KdJLW+Lpq0Mi+1FpNMPsDv742BQ+H9VBsq H0EQ== X-Gm-Message-State: AAQBX9dp837jXOYl/91jqbavJe0Rwz7KA4uHzVKZTFoV9Pynx/c7skEM DNop8lOnGak+y24zbgPVi2JmQj9y/L2QtqCyxL0YyA== X-Google-Smtp-Source: AKy350buJEKr5Eebv4vwR1RO40mHBA1DTr3gNjE7iOknmahnJH4s4QirOxIuWNGuc4C+jPmuVqxs4A== X-Received: by 2002:adf:fa85:0:b0:2fa:6929:eb81 with SMTP id h5-20020adffa85000000b002fa6929eb81mr7889175wrr.31.1682314871540; Sun, 23 Apr 2023 22:41:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 09/57] tcg/i386: Introduce tcg_out_testi Date: Mon, 24 Apr 2023 06:40:17 +0100 Message-Id: <20230424054105.1579315-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315121666100001 Split out a helper for choosing testb vs testl. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 7a02f79f1b..19625a7c75 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1753,6 +1753,23 @@ static void tcg_out_nopn(TCGContext *s, int n) tcg_out8(s, 0x90); } =20 +/* Test register R vs immediate bits I, setting Z flag for EQ/NE. */ +static void __attribute__((unused)) +tcg_out_testi(TCGContext *s, TCGReg r, uint32_t i) +{ + /* + * This is used for testing alignment, so we can usually use testb. + * For i686, we have to use testl for %esi/%edi. + */ + if (i <=3D 0xff && (TCG_TARGET_REG_BITS =3D=3D 64 || r < 4)) { + tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, r); + tcg_out8(s, i); + } else { + tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_TESTi, r); + tcg_out32(s, i); + } +} + typedef struct { TCGReg base; int index; @@ -2053,18 +2070,7 @@ static void tcg_out_test_alignment(TCGContext *s, bo= ol is_ld, TCGReg addrlo, unsigned a_mask =3D (1 << a_bits) - 1; TCGLabelQemuLdst *label; =20 - /* - * We are expecting a_bits to max out at 7, so we can usually use test= b. - * For i686, we have to use testl for %esi/%edi. - */ - if (a_mask <=3D 0xff && (TCG_TARGET_REG_BITS =3D=3D 64 || addrlo < 4))= { - tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, addrlo); - tcg_out8(s, a_mask); - } else { - tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_TESTi, addrlo); - tcg_out32(s, a_mask); - } - + tcg_out_testi(s, addrlo, a_mask); /* jne slow_path */ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); =20 --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315660; cv=none; d=zohomail.com; s=zohoarc; b=X7TNH90JelOG80UKVhlrBkSRhDk1zazMcf6oJflYgakYJMmyOA8bU4QYGMFaZcQyL+kw1EflrzbkMpfdnC/n82WEp1hNqd2Yqsk4EWAaDDaOYdu3EFgo0QfoOfqhKT4Gnr2LyclsGe9a5gcdEzjcsxrO1B1hIkijIBz+3slv4Xk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315660; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Pqi/q0sW6VchB17f5UgVVvECaq0I+8SltHFrwPsjgc4=; b=Kl97NroVLbCDwQ9mGWX3FZYeNkjaFqHH9dDmFUtM9EaJiLWigK/KQpylcOxcUYBPTiu0wGTFz2MPldU14nh1dkp7rfsiKVCxdMm4fvfU1cWXWkUBz5IpjrqMWfkiBERB51kjWl2w+GXS3JLnsYOjN42jwgk2TWFzeDkz1GZJ94o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315660791469.2233786766326; Sun, 23 Apr 2023 22:54:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqoxg-0005is-5l; Mon, 24 Apr 2023 01:42:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqox8-0005N9-NL for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:31 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqowt-0004HX-1c for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:30 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3f1763ee8f8so25818195e9.1 for ; Sun, 23 Apr 2023 22:41:13 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314872; x=1684906872; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Pqi/q0sW6VchB17f5UgVVvECaq0I+8SltHFrwPsjgc4=; b=KGUaGmtOweTKlWry5QdKgbHJ0/0PdkXMssNOa8FO9yGsgU2FABhQrU+/ahAf8Zawah hVuus8HFIrc/z7Si+afc82/qniX+2ALms2aT/E1/RpiPb930DKL0znunVGqe+FAz+d83 Ga70oYhe0wvwgU8J3iQtOeDGaNOxB1iG0ecNU4LxLnTLUaIqjHMYumNDpIIpkQlAyfFm 76f5lFQK9TwcPi91wq8zEXD8in6c3uXmYnlnIlmy7u3B2UtJabGupw3mH1Zz0HlpuWcJ RqFl+l0D8YLx0Cq2lfQPYn6/8Kl4yCeSlvSf+6dHtzEF38Eaeqh41yKZkX9TPp0L5Niy qw2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314872; x=1684906872; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Pqi/q0sW6VchB17f5UgVVvECaq0I+8SltHFrwPsjgc4=; b=BnJuiCXKMjywXoCT1mg87//tpivzjfCy8Jt4G+YQZ+hiISTCJTUarPNasr2aYtJfeF RUdmr/XZoOXrkP2NtCn7ySNHKvqJz5RBFWem8tkhg2NfP166eqKM5YQe84buZ4FWeXPq NTLrAN6I9vIOOpgODS2XajxctwgtS7v2cxuPp3ZFtd1cAQhJVhv1d6qajxEiAJmKsYel dYWgvI9fihyIIgBwTSQlCYo5LrMy8oE46gmiA75fohirH8PEUSFujzyQSnKuNXCtYph6 ySj1i7RHMDyVY348fReyL1a01F7d5PwwW0JRdSbitar36m4x/OuR2Z0R6Mji64hm/uR8 9pMA== X-Gm-Message-State: AAQBX9dzQzIIZ6cD7Zvt5N3yBOUZz9ILwJU2x8jFtPmZ6HMIjeMGSyyO FudDxuOLfOsR2mRMX4k+karXJ9y/0XZ27qEZxHRq7w== X-Google-Smtp-Source: AKy350bQ+dMlfGTVscGEKGEPXEODQG1G7QyaheptcdRK2n734LmSIfiaOAyVElGPp32o2OKioYPanw== X-Received: by 2002:a05:600c:214e:b0:3f1:72f8:6a9c with SMTP id v14-20020a05600c214e00b003f172f86a9cmr5966198wml.6.1682314872140; Sun, 23 Apr 2023 22:41:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 10/57] tcg/i386: Introduce prepare_host_addr Date: Mon, 24 Apr 2023 06:40:18 +0100 Message-Id: <20230424054105.1579315-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315663012100003 Content-Type: text/plain; charset="utf-8" Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 344 ++++++++++++++++---------------------- 1 file changed, 143 insertions(+), 201 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 19625a7c75..2da6d87c7d 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1804,135 +1804,6 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_B= SWAP) + 1] =3D { [MO_BEUQ] =3D helper_be_stq_mmu, }; =20 -/* Perform the TLB load and compare. - - Inputs: - ADDRLO and ADDRHI contain the low and high part of the address. - - MEM_INDEX and S_BITS are the memory context and log2 size of the load. - - WHICH is the offset into the CPUTLBEntry structure of the slot to read. - This should be offsetof addr_read or addr_write. - - Outputs: - LABEL_PTRS is filled with 1 (32-bit addresses) or 2 (64-bit addresses) - positions of the displacements of forward jumps to the TLB miss case. - - Second argument register is loaded with the low part of the address. - In the TLB hit case, it has been adjusted as indicated by the TLB - and so is a host address. In the TLB miss case, it continues to - hold a guest address. - - First argument register is clobbered. */ - -static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg a= ddrhi, - int mem_index, MemOp opc, - tcg_insn_unit **label_ptr, int which) -{ - TCGType ttype =3D TCG_TYPE_I32; - TCGType tlbtype =3D TCG_TYPE_I32; - int trexw =3D 0, hrexw =3D 0, tlbrexw =3D 0; - unsigned a_bits =3D get_alignment_bits(opc); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_mask =3D (1 << a_bits) - 1; - unsigned s_mask =3D (1 << s_bits) - 1; - target_ulong tlb_mask; - - if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (TARGET_LONG_BITS =3D=3D 64) { - ttype =3D TCG_TYPE_I64; - trexw =3D P_REXW; - } - if (TCG_TYPE_PTR =3D=3D TCG_TYPE_I64) { - hrexw =3D P_REXW; - if (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32) { - tlbtype =3D TCG_TYPE_I64; - tlbrexw =3D P_REXW; - } - } - } - - tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo); - tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - - tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0, - TLB_MASK_TABLE_OFS(mem_index) + - offsetof(CPUTLBDescFast, mask)); - - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0, - TLB_MASK_TABLE_OFS(mem_index) + - offsetof(CPUTLBDescFast, table)); - - /* If the required alignment is at least as large as the access, simply - copy the address and mask. For lesser alignments, check that we do= n't - cross pages for the complete access. */ - if (a_bits >=3D s_bits) { - tcg_out_mov(s, ttype, TCG_REG_L1, addrlo); - } else { - tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1, - addrlo, s_mask - a_mask); - } - tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; - tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0); - - /* cmp 0(TCG_REG_L0), TCG_REG_L1 */ - tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, - TCG_REG_L1, TCG_REG_L0, which); - - /* Prepare for both the fast path add of the tlb addend, and the slow - path function argument setup. */ - tcg_out_mov(s, ttype, TCG_REG_L1, addrlo); - - /* jne slow_path */ - tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); - label_ptr[0] =3D s->code_ptr; - s->code_ptr +=3D 4; - - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - /* cmp 4(TCG_REG_L0), addrhi */ - tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, TCG_REG_L0, which + = 4); - - /* jne slow_path */ - tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); - label_ptr[1] =3D s->code_ptr; - s->code_ptr +=3D 4; - } - - /* TLB Hit. */ - - /* add addend(TCG_REG_L0), TCG_REG_L1 */ - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L1, TCG_REG_L0, - offsetof(CPUTLBEntry, addend)); -} - -/* - * Record the context of a call to the out of line helper code for the slo= w path - * for a load or store, so that we can later generate the correct helper c= ode - */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, - TCGType type, MemOpIdx oi, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addrhi, - tcg_insn_unit *raddr, - tcg_insn_unit **label_ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D type; - label->datalo_reg =3D datalo; - label->datahi_reg =3D datahi; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr[0]; - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - label->label_ptr[1] =3D label_ptr[1]; - } -} - /* * Generate code for the slow path for a load at the end of block */ @@ -2063,27 +1934,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) return true; } #else - -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrl= o, - TCGReg addrhi, unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *label; - - tcg_out_testi(s, addrlo, a_mask); - /* jne slow_path */ - tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); - - label =3D new_ldst_label(s); - label->is_ld =3D is_ld; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; - label->raddr =3D tcg_splitwx_to_rx(s->code_ptr + 4); - label->label_ptr[0] =3D s->code_ptr; - - s->code_ptr +=3D 4; -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { /* resolve label address */ @@ -2161,6 +2011,133 @@ static inline int setup_guest_base_seg(void) #endif /* setup_guest_base_seg */ #endif /* SOFTMMU */ =20 +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, bool is_ld) +{ + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned a_mask =3D (1 << a_bits) - 1; + +#ifdef CONFIG_SOFTMMU + int cmp_ofs =3D is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write); + TCGType ttype =3D TCG_TYPE_I32; + TCGType tlbtype =3D TCG_TYPE_I32; + int trexw =3D 0, hrexw =3D 0, tlbrexw =3D 0; + unsigned mem_index =3D get_mmuidx(oi); + unsigned s_bits =3D opc & MO_SIZE; + unsigned s_mask =3D (1 << s_bits) - 1; + target_ulong tlb_mask; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + if (TCG_TARGET_REG_BITS =3D=3D 64) { + if (TARGET_LONG_BITS =3D=3D 64) { + ttype =3D TCG_TYPE_I64; + trexw =3D P_REXW; + } + if (TCG_TYPE_PTR =3D=3D TCG_TYPE_I64) { + hrexw =3D P_REXW; + if (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32) { + tlbtype =3D TCG_TYPE_I64; + tlbrexw =3D P_REXW; + } + } + } + + tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo); + tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + + tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0, + TLB_MASK_TABLE_OFS(mem_index) + + offsetof(CPUTLBDescFast, mask)); + + tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0, + TLB_MASK_TABLE_OFS(mem_index) + + offsetof(CPUTLBDescFast, table)); + + /* If the required alignment is at least as large as the access, simply + copy the address and mask. For lesser alignments, check that we do= n't + cross pages for the complete access. */ + if (a_bits >=3D s_bits) { + tcg_out_mov(s, ttype, TCG_REG_L1, addrlo); + } else { + tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1, + addrlo, s_mask - a_mask); + } + tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; + tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0); + + /* cmp 0(TCG_REG_L0), TCG_REG_L1 */ + tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, + TCG_REG_L1, TCG_REG_L0, cmp_ofs); + + /* + * Prepare for both the fast path add of the tlb addend, and the slow + * path function argument setup. + */ + *h =3D (HostAddress) { + .base =3D TCG_REG_L1, + .index =3D -1 + }; + tcg_out_mov(s, ttype, h->base, addrlo); + + /* jne slow_path */ + tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); + ldst->label_ptr[0] =3D s->code_ptr; + s->code_ptr +=3D 4; + + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + /* cmp 4(TCG_REG_L0), addrhi */ + tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, TCG_REG_L0, cmp_ofs = + 4); + + /* jne slow_path */ + tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); + ldst->label_ptr[1] =3D s->code_ptr; + s->code_ptr +=3D 4; + } + + /* TLB Hit. */ + + /* add addend(TCG_REG_L0), TCG_REG_L1 */ + tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, h->base, TCG_REG_L0, + offsetof(CPUTLBEntry, addend)); +#else + if (a_bits) { + ldst =3D new_ldst_label(s); + + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + tcg_out_testi(s, addrlo, a_mask); + /* jne slow_path */ + tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); + ldst->label_ptr[0] =3D s->code_ptr; + s->code_ptr +=3D 4; + } + + *h =3D x86_guest_base; + h->base =3D addrlo; +#endif + + return ldst; +} + static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, HostAddress h, TCGType type, MemOp memo= p) { @@ -2260,35 +2237,18 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[2]; + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, true); + tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, get_memop(oi)); =20 - tcg_out_tlb_load(s, addrlo, addrhi, get_mmuidx(oi), opc, - label_ptr, offsetof(CPUTLBEntry, addr_read)); - - /* TLB Hit. */ - h.base =3D TCG_REG_L1; - h.index =3D -1; - h.ofs =3D 0; - h.seg =3D 0; - tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, opc); - - /* Record the current context of a load into ldst label */ - add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - - h =3D x86_guest_base; - h.base =3D addrlo; - tcg_out_qemu_ld_direct(s, datalo, datahi, h, data_type, opc); -#endif } =20 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, @@ -2347,36 +2307,18 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[2]; + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, false); + tcg_out_qemu_st_direct(s, datalo, datahi, h, get_memop(oi)); =20 - tcg_out_tlb_load(s, addrlo, addrhi, get_mmuidx(oi), opc, - label_ptr, offsetof(CPUTLBEntry, addr_write)); - - /* TLB Hit. */ - h.base =3D TCG_REG_L1; - h.index =3D -1; - h.ofs =3D 0; - h.seg =3D 0; - tcg_out_qemu_st_direct(s, datalo, datahi, h, opc); - - /* Record the current context of a store into ldst label */ - add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - - h =3D x86_guest_base; - h.base =3D addrlo; - - tcg_out_qemu_st_direct(s, datalo, datahi, h, opc); -#endif } =20 static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315116; cv=none; d=zohomail.com; s=zohoarc; b=FTV+mQzmZC9BCPm7xNnmLvY0s5ndIYnx0v8y+AyXCsNDFW0GCv2aon9hFL3u9Zmc597yrZg+li6Xiz8FvZ8c0hBcKXGu1CUR5+CwawbHHJKDPuttnUBqM1UngP2lPoDrXKZf8FL0WwJ/qNzNKE574Sl5qbmHaEzSYmU7gWGT7GU= ARC-Message-Signature: i=1; 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[46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314872; x=1684906872; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fc0ICmGFK3BYN6uzzR7T3sWoQR2opuLU6c9oEemqdsw=; b=dSe09u4ZbZoILZ3YuZJiMrE7CuZ9n5o5k9ddPwTGPA3cD8i7ZN8Jw6mEjqV0Ka0FSH MXppi3m8bKj/uDb4Wnq0WcmLI+DkxPs2GUZLrI4i1wORvrXjwxHu0tj9FYhKsK8+71X5 J0LEktkiYRwFYMkhVvOvuZBQrmMLptLgRv+2Hf5O9dY4dDii6M8/+zLGIjX3k3xmytL4 VcCfj4xMWdhNzvmDQduOqDzo1VUPup8UWOcInqdGEF0Ytb4+1FIzIRYLp+YBX/DG5oCr 4u6xpr9Zg0psiD4WLQtyOTeUbYWZdxJ1STtTg8zRHOk5ppxLoFT++H34C3LY23JVwF5f z6AQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314872; x=1684906872; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fc0ICmGFK3BYN6uzzR7T3sWoQR2opuLU6c9oEemqdsw=; b=I+qEo+FqVQISZTSFjrl6KaHObsqjQm2VqLEMMN6cMdZYgY/NKunVmwKl4sR/7Qg4pv mOF8k3A1RMo4Va8+JteOJ7zeeD1bXKv4FfVlGmvAY+pkEhGZRwZFJJ5/s8ZFxNguwH7o iZeK8k99DixzFH2RG8/gBsuxzZGvOBRgLE0H4sFXPht2vCLEtGCoQEy7vzYmXHm59qBu EXa2BWThxRvVHPX+UJ5Ip7dB+YvAa3zZdDCMSSApCgK9l5A70f/gp4BKtN8PJq0tL37i J9RB3mokPYRlQzeup2dUBpjmX4DVnDHjDWoIOlvQY4w7cxhOHwLc6mZ7Wx4+hsw1iGXw hXdg== X-Gm-Message-State: AC+VfDzxR4ifah7rXh5lwGnF16rX7nqgbXMUt3Vwm1SahqKcSf4iWSmU Yru9jdcy7PvHigmwLcFD7+QaRGQXBPz3u3AbN9t/8g== X-Google-Smtp-Source: ACHHUZ78uHnvVXAGOvD+zdAvQRi2L8nK+UyFGXzqjBGh9P9FUTqK77JZ/ocMAEOnidMK9HABxgetNQ== X-Received: by 2002:a5d:6610:0:b0:304:7bbe:87f7 with SMTP id n16-20020a5d6610000000b003047bbe87f7mr727866wru.58.1682314872656; Sun, 23 Apr 2023 22:41:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 11/57] tcg/i386: Use indexed addressing for softmmu fast path Date: Mon, 24 Apr 2023 06:40:19 +0100 Message-Id: <20230424054105.1579315-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315117499100003 Content-Type: text/plain; charset="utf-8" Since tcg_out_{ld,st}_helper_args, the slow path no longer requires the address argument to be set up by the tlb load sequence. Use a plain load for the addend and indexed addressing with the original input address register. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 2da6d87c7d..fabb03cd74 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1839,7 +1839,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) tcg_out_sti(s, TCG_TYPE_PTR, (uintptr_t)l->raddr, TCG_REG_ESP, ofs= ); } else { tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); - /* The second argument is already loaded with addrlo. */ + tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], + l->addrlo_reg); tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], oi); tcg_out_movi(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[3], (uintptr_t)l->raddr); @@ -1912,7 +1913,8 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, ofs); } else { tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); - /* The second argument is already loaded with addrlo. */ + tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], + l->addrlo_reg); tcg_out_mov(s, (s_bits =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), tcg_target_call_iarg_regs[2], l->datalo_reg); tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], oi); @@ -2085,16 +2087,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContex= t *s, HostAddress *h, tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, TCG_REG_L1, TCG_REG_L0, cmp_ofs); =20 - /* - * Prepare for both the fast path add of the tlb addend, and the slow - * path function argument setup. - */ - *h =3D (HostAddress) { - .base =3D TCG_REG_L1, - .index =3D -1 - }; - tcg_out_mov(s, ttype, h->base, addrlo); - /* jne slow_path */ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); ldst->label_ptr[0] =3D s->code_ptr; @@ -2111,10 +2103,13 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, } =20 /* TLB Hit. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0, + offsetof(CPUTLBEntry, addend)); =20 - /* add addend(TCG_REG_L0), TCG_REG_L1 */ - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, h->base, TCG_REG_L0, - offsetof(CPUTLBEntry, addend)); + *h =3D (HostAddress) { + .base =3D addrlo, + .index =3D TCG_REG_L0, + }; #else if (a_bits) { ldst =3D new_ldst_label(s); --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315645891477.21467145576094; Sun, 23 Apr 2023 22:54:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqozg-0002sN-3n; Mon, 24 Apr 2023 01:44:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqoxL-0005WA-Or for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:43 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqowv-0004IH-4R for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:42 -0400 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-2f625d52275so3800062f8f.3 for ; Sun, 23 Apr 2023 22:41:14 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314873; x=1684906873; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8x8nNgwxVzWwlXkH7TC04g8D23cjiNxwy3VmZPjq5To=; b=cB+RHpr/LDyxIxMlu0TXtnZkfa5eXUHILYMzOPwSYUdcr8pRs/iOvdTrW8F+AiYtX5 ZRraEFd9voWPzLtRjoR0uDv+sNzg6VIRZDv2DVAAHmx96yuy63+PVAuFRomu+mCfIC1+ QDowVhC/cEYGg/e73ZyUe6c6UO22W5F2INWe7rNrL42a8jkVAtgF5vK26NUvEucbgHiN wV4TVDUQ5DhpX/L8rPPZdiMAKiB9lExSd0J5w8YfRQXt0Xzuk/u/sy22NpO9QVzQYxHL 17UQ41j8ezSVMIrRkN4cc9P0qHd+VwY17DJyPs4Lux6j9ePcJEsx8wdZ+U8H0BMHwCQS 3rrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314873; x=1684906873; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8x8nNgwxVzWwlXkH7TC04g8D23cjiNxwy3VmZPjq5To=; b=LGS4Qun8eq0k2pMZYUXWOIpEZGc7s32bHQ5fB39GK8ibwxMorenJPZYb8RJxqTVC28 8zoGTZq09n/zc865huChPHVTUNz0WJaFOvP8SHWjpXCi3X/1eISiNh2kGEtjkT25gKVS HiDv+F8/4E+uomvxVA9eD9odEkpWMw8KDC669drgfT7os/lozZMuYRCrabas/3aAffS7 viX0Y9zKoe0voQkXtviI9kTUe1wBXoQpljxUV5rwifPpeZ75fdBQKsRFjQpSypoKp7f7 io292WFqMqauZ2m8xoidlzdj95RqMmiKpORSbpZRs0nTQjr5nxrABpBKMeukGjBXjhP2 Xbsg== X-Gm-Message-State: AAQBX9dQJk9zSfNN4Fv6RSP825n5mAQ3LnKZopC2XDPhiRE6s54iGUcP IqBXAESUYvkoXiFSsDN4INfkrECtiKpMhyGGhm4TBA== X-Google-Smtp-Source: AKy350Y5kdkvW9AwvK08S+ZJ/REPv9cBaJSsEE/ZMbOgPQEjf9A2Yh6+UVKAioKughLT7WGmwc9Ucg== X-Received: by 2002:adf:f68b:0:b0:2ce:a34b:2b0b with SMTP id v11-20020adff68b000000b002cea34b2b0bmr8473202wrp.28.1682314873260; Sun, 23 Apr 2023 22:41:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 12/57] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld, st} Date: Mon, 24 Apr 2023 06:40:20 +0100 Message-Id: <20230424054105.1579315-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1682315647741100007 Rename the 'ext' parameter 'data_type' to make the use clearer; pass it to tcg_out_qemu_st as well to even out the interfaces. Rename the 'otype' local 'addr_type' to make the use clearer. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 36 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 4ec3cf3172..ecbf6564fc 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1851,22 +1851,21 @@ static void tcg_out_qemu_st_direct(TCGContext *s, M= emOp memop, } =20 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, - MemOpIdx oi, TCGType ext) + MemOpIdx oi, TCGType data_type) { MemOp memop =3D get_memop(oi); - const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; + TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; =20 /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); =20 #ifdef CONFIG_SOFTMMU - unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; =20 - tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1); - tcg_out_qemu_ld_direct(s, memop, ext, data_reg, - TCG_REG_X1, otype, addr_reg); - add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg, + tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 1); + tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, + TCG_REG_X1, addr_type, addr_reg); + add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ unsigned a_bits =3D get_alignment_bits(memop); @@ -1874,33 +1873,32 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, tcg_out_test_alignment(s, true, addr_reg, a_bits); } if (USE_GUEST_BASE) { - tcg_out_qemu_ld_direct(s, memop, ext, data_reg, - TCG_REG_GUEST_BASE, otype, addr_reg); + tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, + TCG_REG_GUEST_BASE, addr_type, addr_reg); } else { - tcg_out_qemu_ld_direct(s, memop, ext, data_reg, + tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, addr_reg, TCG_TYPE_I64, TCG_REG_XZR); } #endif /* CONFIG_SOFTMMU */ } =20 static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, - MemOpIdx oi) + MemOpIdx oi, TCGType data_type) { MemOp memop =3D get_memop(oi); - const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; + TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; =20 /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); =20 #ifdef CONFIG_SOFTMMU - unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; =20 - tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0); + tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 0); tcg_out_qemu_st_direct(s, memop, data_reg, - TCG_REG_X1, otype, addr_reg); - add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)=3D=3D MO_64, - data_reg, addr_reg, s->code_ptr, label_ptr); + TCG_REG_X1, addr_type, addr_reg); + add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, + s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ unsigned a_bits =3D get_alignment_bits(memop); if (a_bits) { @@ -1908,7 +1906,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= a_reg, TCGReg addr_reg, } if (USE_GUEST_BASE) { tcg_out_qemu_st_direct(s, memop, data_reg, - TCG_REG_GUEST_BASE, otype, addr_reg); + TCG_REG_GUEST_BASE, addr_type, addr_reg); } else { tcg_out_qemu_st_direct(s, memop, data_reg, addr_reg, TCG_TYPE_I64, TCG_REG_XZR); @@ -2249,7 +2247,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, REG0(0), a1, a2); + tcg_out_qemu_st(s, REG0(0), a1, a2, ext); break; =20 case INDEX_op_bswap64_i64: --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315654; cv=none; d=zohomail.com; s=zohoarc; b=LRcf6EXgdr25qHx81IKep+MvznHm7gvLaNDmNhyU76PUSg2CtMBZRmIngIsKLPJFontQ95SGUDXmPPE9k0j6BqNO5Wze9gMXaTcXaMakUlIVB3R3iO/AciLNpgAdskjO65Zj1gnN2zeX4y5TV48mWuQiNMVqwL2nv5GmAd+wQL8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315654; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RJ7URx7VME6Yut58cQvnYokrETz9WcC+DTaD3rOQAjQ=; b=DkXTj5yjgXC0FDlEZ91IrwOOs1+vEspHE+Pb3kMYCEyqaEpiaZGgCh3PD8VYhyfs6VwR4tTKK0ye8RPIcrHUIgqsCNmtT4MMrf8PU08pUZsKW1TVNGRNmGO7SEcpZU0XHh2oFTUO+6670+hdnTQ4d7nta4j2husGLmtXaJCjsOE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315654199298.24731612011306; Sun, 23 Apr 2023 22:54:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqoyb-0006mN-9a; Mon, 24 Apr 2023 01:43:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqoxI-0005TZ-VG for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:42 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqowv-0004IT-3x for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:40 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-2f9b9aa9d75so2409725f8f.0 for ; Sun, 23 Apr 2023 22:41:15 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314873; x=1684906873; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RJ7URx7VME6Yut58cQvnYokrETz9WcC+DTaD3rOQAjQ=; b=i1N8/OvPcyq7vmN+JQHWWpVwE1Mhc6tOQFl6DTx/y5ZwxVu2lKGXOdXLUcfzQ9nBoO /+F+fY/aVlXr6OYDQE7bb26zQONJwaOOj78KupozA0zo1vUxHnqth6D/VrMRVrnCyhBF l9JkD9LrYKHBY2NXKVpVYLO9e94AdUr0YF4D5LoDosmzpWBge49mW4tIQJXh5Iva1HrK vjPHPJ30OF5NhdzjVxVjnhMMAe6v5TpLX0JCmbrpr38dtAQpYnjl0WN71dIk2Z9uSsoC 0Y/G3RsJ5b3ZWYMcTmvutKMqaqecJLxwlw13oJw2ex5mCzQrM/HDIJKzKpbUTcYyY9y5 TwKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314873; x=1684906873; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RJ7URx7VME6Yut58cQvnYokrETz9WcC+DTaD3rOQAjQ=; b=Kq1D1WGoYdMNDbxy+XwiGggIsY++r1f1/E8vYYwG7lyS0u0gcUWoFCnbAKQuf26zrC lu3ykrkVPJQuSKMtIcy4EO9xRYLKmSslZ0t2NS2Iqqtz+UcgbVsjBYnVrFu5SrXZ/c8w quchKLkjAwg3nwK5eeOIEoT9fyiW/jJlso6UJ5x6WaPOqXRliV3N6kRSn3OiZB18kLlb PwlcmCEYsuLNZIcGOjPo1mMUqF9sCUADEsUETmRS7c7CjFEzA0M/l1r5esL3M/cHkuSd EUXDOQbweKiFgV1KdGbWz/akQEMVkQwN3cfCHL7wHZa8hJSoJTAnLd8PSlVN0BiWCN8H G1Ig== X-Gm-Message-State: AAQBX9dbQJavomrvT1AYvoRPJqIkZ9ZEMVU/89k4P3MhZGsVjn9fBMOm Hk4f7RANDXKZgjKs24jtXJh271JYtJYlRgPshYiSsA== X-Google-Smtp-Source: AKy350ZPYLYfYJyoFTnI2yNVZHNPv/Ir3D6AOQVIAkS/Nn4XMvjcgHljmhVpy8u/tTg8ZEvYGVwHFA== X-Received: by 2002:adf:dece:0:b0:2d8:47c7:7b52 with SMTP id i14-20020adfdece000000b002d847c77b52mr9052263wrn.9.1682314873801; Sun, 23 Apr 2023 22:41:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 13/57] tcg/aarch64: Introduce HostAddress Date: Mon, 24 Apr 2023 06:40:21 +0100 Message-Id: <20230424054105.1579315-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315654789100001 Content-Type: text/plain; charset="utf-8" Collect the 3 potential parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st}_direct to use it. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/aarch64/tcg-target.c.inc | 86 +++++++++++++++++++++++++----------- 1 file changed, 59 insertions(+), 27 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index ecbf6564fc..d8d464e4a0 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1587,6 +1587,12 @@ static void tcg_out_adr(TCGContext *s, TCGReg rd, co= nst void *target) tcg_out_insn(s, 3406, ADR, rd, offset); } =20 +typedef struct { + TCGReg base; + TCGReg index; + TCGType index_ext; +} HostAddress; + #ifdef CONFIG_SOFTMMU /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * MemOpIdx oi, uintptr_t ra) @@ -1796,32 +1802,31 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) #endif /* CONFIG_SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext, - TCGReg data_r, TCGReg addr_r, - TCGType otype, TCGReg off_r) + TCGReg data_r, HostAddress h) { switch (memop & MO_SSIZE) { case MO_UB: - tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRB, data_r, h.base, h.index_ext, h.index= ); break; case MO_SB: tcg_out_ldst_r(s, ext ? I3312_LDRSBX : I3312_LDRSBW, - data_r, addr_r, otype, off_r); + data_r, h.base, h.index_ext, h.index); break; case MO_UW: - tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRH, data_r, h.base, h.index_ext, h.index= ); break; case MO_SW: tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW), - data_r, addr_r, otype, off_r); + data_r, h.base, h.index_ext, h.index); break; case MO_UL: - tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRW, data_r, h.base, h.index_ext, h.index= ); break; case MO_SL: - tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRSWX, data_r, h.base, h.index_ext, h.ind= ex); break; case MO_UQ: - tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRX, data_r, h.base, h.index_ext, h.index= ); break; default: g_assert_not_reached(); @@ -1829,21 +1834,20 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, M= emOp memop, TCGType ext, } =20 static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop, - TCGReg data_r, TCGReg addr_r, - TCGType otype, TCGReg off_r) + TCGReg data_r, HostAddress h) { switch (memop & MO_SIZE) { case MO_8: - tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_STRB, data_r, h.base, h.index_ext, h.index= ); break; case MO_16: - tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_STRH, data_r, h.base, h.index_ext, h.index= ); break; case MO_32: - tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_STRW, data_r, h.base, h.index_ext, h.index= ); break; case MO_64: - tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_STRX, data_r, h.base, h.index_ext, h.index= ); break; default: g_assert_not_reached(); @@ -1855,6 +1859,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a_reg, TCGReg addr_reg, { MemOp memop =3D get_memop(oi); TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; + HostAddress h; =20 /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); @@ -1863,8 +1868,14 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg da= ta_reg, TCGReg addr_reg, tcg_insn_unit *label_ptr; =20 tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 1); - tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, - TCG_REG_X1, addr_type, addr_reg); + + h =3D (HostAddress){ + .base =3D TCG_REG_X1, + .index =3D addr_reg, + .index_ext =3D addr_type + }; + tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, h); + add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ @@ -1873,12 +1884,19 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, tcg_out_test_alignment(s, true, addr_reg, a_bits); } if (USE_GUEST_BASE) { - tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, - TCG_REG_GUEST_BASE, addr_type, addr_reg); + h =3D (HostAddress){ + .base =3D TCG_REG_GUEST_BASE, + .index =3D addr_reg, + .index_ext =3D addr_type + }; } else { - tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, - addr_reg, TCG_TYPE_I64, TCG_REG_XZR); + h =3D (HostAddress){ + .base =3D addr_reg, + .index =3D TCG_REG_XZR, + .index_ext =3D TCG_TYPE_I64 + }; } + tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, h); #endif /* CONFIG_SOFTMMU */ } =20 @@ -1887,6 +1905,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= a_reg, TCGReg addr_reg, { MemOp memop =3D get_memop(oi); TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; + HostAddress h; =20 /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); @@ -1895,8 +1914,14 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg da= ta_reg, TCGReg addr_reg, tcg_insn_unit *label_ptr; =20 tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 0); - tcg_out_qemu_st_direct(s, memop, data_reg, - TCG_REG_X1, addr_type, addr_reg); + + h =3D (HostAddress){ + .base =3D TCG_REG_X1, + .index =3D addr_reg, + .index_ext =3D addr_type + }; + tcg_out_qemu_st_direct(s, memop, data_reg, h); + add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ @@ -1905,12 +1930,19 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, tcg_out_test_alignment(s, false, addr_reg, a_bits); } if (USE_GUEST_BASE) { - tcg_out_qemu_st_direct(s, memop, data_reg, - TCG_REG_GUEST_BASE, addr_type, addr_reg); + h =3D (HostAddress){ + .base =3D TCG_REG_GUEST_BASE, + .index =3D addr_reg, + .index_ext =3D addr_type + }; } else { - tcg_out_qemu_st_direct(s, memop, data_reg, - addr_reg, TCG_TYPE_I64, TCG_REG_XZR); + h =3D (HostAddress){ + .base =3D addr_reg, + .index =3D TCG_REG_XZR, + .index_ext =3D TCG_TYPE_I64 + }; } + tcg_out_qemu_st_direct(s, memop, data_reg, h); #endif /* CONFIG_SOFTMMU */ } =20 --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315691; cv=none; d=zohomail.com; s=zohoarc; b=bblZ+urde5YuE0H/ylcK/HvN7zh+eOZHBaBzwpLMeVUOtjcjVZQO2CvxLYRQR0Lnkq8wdhBXvJCYpJnnhbt00R0OchTUovSsK/tdd6ba0SFWGS9kIwkM52Gv81452n1bvnNwdgi4YNbwErwFXVoNeF8FMZjpSiirfw1UZEzuqh0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315691; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=E+QlOMba/aSBW632xLY397LQPEBGu7J2mpCgxpenFkM=; b=cir6ewDX5riNp3GDhxvlMHODWomUY/3iKZgd+yDJ/dqxouXMAtnRtZe9DHefLHfmO8hzYHjljNtnh2hgMZMg2T/YuhzvYo/BEPYIbebRBY0mCH3Ay5Mwn+fmt9n7pz4cetCdlNOxMew6F6UcNa5UkEC+KbKDVXYLG2Tw7d3xFQo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315691051318.14714864607697; Sun, 23 Apr 2023 22:54:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqoyu-0008Gg-C8; Mon, 24 Apr 2023 01:43:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqoxM-0005XO-04 for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:44 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqowv-0004Ik-3u for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:43 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-3f1738d0d4cso24547035e9.1 for ; Sun, 23 Apr 2023 22:41:15 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. 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Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 313 +++++++++++++++-------------------- 1 file changed, 133 insertions(+), 180 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index d8d464e4a0..202b90c001 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1667,113 +1667,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) tcg_out_goto(s, lb->raddr); return true; } - -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, - TCGType ext, TCGReg data_reg, TCGReg addr_= reg, - tcg_insn_unit *raddr, tcg_insn_unit *label= _ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D ext; - label->datalo_reg =3D data_reg; - label->addrlo_reg =3D addr_reg; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr; -} - -/* We expect to use a 7-bit scaled negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512); - -/* These offsets are built into the LDP below. */ -QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); -QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 8); - -/* Load and compare a TLB entry, emitting the conditional jump to the - slow path for the failure case, which will be patched later when finali= zing - the slow path. Generated code returns the host addend in X1, - clobbers X0,X2,X3,TMP. */ -static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc, - tcg_insn_unit **label_ptr, int mem_index, - bool is_read) -{ - unsigned a_bits =3D get_alignment_bits(opc); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_mask =3D (1u << a_bits) - 1; - unsigned s_mask =3D (1u << s_bits) - 1; - TCGReg x3; - TCGType mask_type; - uint64_t compare_mask; - - mask_type =3D (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32 - ? TCG_TYPE_I64 : TCG_TYPE_I32); - - /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */ - tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0, - TLB_MASK_TABLE_OFS(mem_index), 1, 0); - - /* Extract the TLB index from the address into X0. */ - tcg_out_insn(s, 3502S, AND_LSR, mask_type =3D=3D TCG_TYPE_I64, - TCG_REG_X0, TCG_REG_X0, addr_reg, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - - /* Add the tlb_table pointer, creating the CPUTLBEntry address into X1= . */ - tcg_out_insn(s, 3502, ADD, 1, TCG_REG_X1, TCG_REG_X1, TCG_REG_X0); - - /* Load the tlb comparator into X0, and the fast path addend into X1. = */ - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_X0, TCG_REG_X1, is_read - ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, TCG_REG_X1, - offsetof(CPUTLBEntry, addend)); - - /* For aligned accesses, we check the first byte and include the align= ment - bits within the address. For unaligned access, we check that we do= n't - cross pages using the address of the last byte of the access. */ - if (a_bits >=3D s_bits) { - x3 =3D addr_reg; - } else { - tcg_out_insn(s, 3401, ADDI, TARGET_LONG_BITS =3D=3D 64, - TCG_REG_X3, addr_reg, s_mask - a_mask); - x3 =3D TCG_REG_X3; - } - compare_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; - - /* Store the page mask part of the address into X3. */ - tcg_out_logicali(s, I3404_ANDI, TARGET_LONG_BITS =3D=3D 64, - TCG_REG_X3, x3, compare_mask); - - /* Perform the address comparison. */ - tcg_out_cmp(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X0, TCG_REG_X3, 0); - - /* If not equal, we jump to the slow path. */ - *label_ptr =3D s->code_ptr; - tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); -} - #else -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_= reg, - unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->addrlo_reg =3D addr_reg; - - /* tst addr, #mask */ - tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask); - - label->label_ptr[0] =3D s->code_ptr; - - /* b.ne slow_path */ - tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); - - label->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { if (!reloc_pc19(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -1801,6 +1695,125 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) } #endif /* CONFIG_SOFTMMU */ =20 +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addr_reg, MemOpIdx oi, + bool is_ld) +{ + TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned a_mask =3D (1u << a_bits) - 1; + +#ifdef CONFIG_SOFTMMU + unsigned s_bits =3D opc & MO_SIZE; + unsigned s_mask =3D (1u << s_bits) - 1; + unsigned mem_index =3D get_mmuidx(oi); + TCGReg x3; + TCGType mask_type; + uint64_t compare_mask; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + mask_type =3D (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32 + ? TCG_TYPE_I64 : TCG_TYPE_I32); + + /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {x0,x1}. */ + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512); + QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); + QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 8); + tcg_out_insn(s, 3314, LDP, TCG_REG_X0, TCG_REG_X1, TCG_AREG0, + TLB_MASK_TABLE_OFS(mem_index), 1, 0); + + /* Extract the TLB index from the address into X0. */ + tcg_out_insn(s, 3502S, AND_LSR, mask_type =3D=3D TCG_TYPE_I64, + TCG_REG_X0, TCG_REG_X0, addr_reg, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + + /* Add the tlb_table pointer, creating the CPUTLBEntry address into X1= . */ + tcg_out_insn(s, 3502, ADD, 1, TCG_REG_X1, TCG_REG_X1, TCG_REG_X0); + + /* Load the tlb comparator into X0, and the fast path addend into X1. = */ + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_X0, TCG_REG_X1, + is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_X1, TCG_REG_X1, + offsetof(CPUTLBEntry, addend)); + + /* + * For aligned accesses, we check the first byte and include the align= ment + * bits within the address. For unaligned access, we check that we do= n't + * cross pages using the address of the last byte of the access. + */ + if (a_bits >=3D s_bits) { + x3 =3D addr_reg; + } else { + tcg_out_insn(s, 3401, ADDI, TARGET_LONG_BITS =3D=3D 64, + TCG_REG_X3, addr_reg, s_mask - a_mask); + x3 =3D TCG_REG_X3; + } + compare_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; + + /* Store the page mask part of the address into X3. */ + tcg_out_logicali(s, I3404_ANDI, TARGET_LONG_BITS =3D=3D 64, + TCG_REG_X3, x3, compare_mask); + + /* Perform the address comparison. */ + tcg_out_cmp(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X0, TCG_REG_X3, 0); + + /* If not equal, we jump to the slow path. */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); + + *h =3D (HostAddress){ + .base =3D TCG_REG_X1, + .index =3D addr_reg, + .index_ext =3D addr_type + }; +#else + if (a_mask) { + ldst =3D new_ldst_label(s); + + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + /* tst addr, #mask */ + tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask); + + /* b.ne slow_path */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); + } + + if (USE_GUEST_BASE) { + *h =3D (HostAddress){ + .base =3D TCG_REG_GUEST_BASE, + .index =3D addr_reg, + .index_ext =3D addr_type + }; + } else { + *h =3D (HostAddress){ + .base =3D addr_reg, + .index =3D TCG_REG_XZR, + .index_ext =3D TCG_TYPE_I64 + }; + } +#endif + + return ldst; +} + static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext, TCGReg data_r, HostAddress h) { @@ -1857,93 +1870,33 @@ static void tcg_out_qemu_st_direct(TCGContext *s, M= emOp memop, static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp memop =3D get_memop(oi); - TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; + TCGLabelQemuLdst *ldst; HostAddress h; =20 - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, true); + tcg_out_qemu_ld_direct(s, get_memop(oi), data_type, data_reg, h); =20 -#ifdef CONFIG_SOFTMMU - tcg_insn_unit *label_ptr; - - tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 1); - - h =3D (HostAddress){ - .base =3D TCG_REG_X1, - .index =3D addr_reg, - .index_ext =3D addr_type - }; - tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, h); - - add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ - unsigned a_bits =3D get_alignment_bits(memop); - if (a_bits) { - tcg_out_test_alignment(s, true, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - if (USE_GUEST_BASE) { - h =3D (HostAddress){ - .base =3D TCG_REG_GUEST_BASE, - .index =3D addr_reg, - .index_ext =3D addr_type - }; - } else { - h =3D (HostAddress){ - .base =3D addr_reg, - .index =3D TCG_REG_XZR, - .index_ext =3D TCG_TYPE_I64 - }; - } - tcg_out_qemu_ld_direct(s, memop, data_type, data_reg, h); -#endif /* CONFIG_SOFTMMU */ } =20 static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp memop =3D get_memop(oi); - TCGType addr_type =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TCG_= TYPE_I32; + TCGLabelQemuLdst *ldst; HostAddress h; =20 - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, false); + tcg_out_qemu_st_direct(s, get_memop(oi), data_reg, h); =20 -#ifdef CONFIG_SOFTMMU - tcg_insn_unit *label_ptr; - - tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 0); - - h =3D (HostAddress){ - .base =3D TCG_REG_X1, - .index =3D addr_reg, - .index_ext =3D addr_type - }; - tcg_out_qemu_st_direct(s, memop, data_reg, h); - - add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ - unsigned a_bits =3D get_alignment_bits(memop); - if (a_bits) { - tcg_out_test_alignment(s, false, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - if (USE_GUEST_BASE) { - h =3D (HostAddress){ - .base =3D TCG_REG_GUEST_BASE, - .index =3D addr_reg, - .index_ext =3D addr_type - }; - } else { - h =3D (HostAddress){ - .base =3D addr_reg, - .index =3D TCG_REG_XZR, - .index_ext =3D TCG_TYPE_I64 - }; - } - tcg_out_qemu_st_direct(s, memop, data_reg, h); -#endif /* CONFIG_SOFTMMU */ } =20 static const tcg_insn_unit *tb_ret_addr; --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315436; cv=none; d=zohomail.com; s=zohoarc; b=ezIyGdNTodw8NuibMOhPWrEN8/+Q6wZttEVVJ8g4V8c9a0KKtj3Lvdx04yvgLn/d6FEUXtx51nmSj73u9UMR/Z+nRUAtA+f16cJooQx7+kR/X0Kk3CfIQp/lMW87ig0ROOFbwdguCRyGvpm8KhanGB+HQ5b9CIvsvcdTWr70VZ0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315436; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/LNx4AQ8LEDs2bqV5zvn6xWFsTqqlF00MmHmvqgX6b8=; b=QNDmyh5wm2NGVyz7m3YQ6mAc7OmZlHTjkzfcqTGN7EqtFugzDkJ0w9C62TyNBt/7+ZIM1bGxQ6G+2j0ZgbHmBH6fV3oIFUbto1ZW052kLHN3I//05Xucv2BqMn8gKHsuznKvquNDWt2MxcfuZsnwjQ/k5eS7+xgHjk+5I2tRgOg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315436305878.1352370644217; Sun, 23 Apr 2023 22:50:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqozY-0001aY-Be; Mon, 24 Apr 2023 01:44:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqoxZ-0005da-EJ for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:58 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqowv-0004JN-4y for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:57 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-2fa47de5b04so3816460f8f.1 for ; Sun, 23 Apr 2023 22:41:15 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314875; x=1684906875; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/LNx4AQ8LEDs2bqV5zvn6xWFsTqqlF00MmHmvqgX6b8=; b=aFnRQb7BWZ51jYFOEA/uce4sH5BvJ98AzkrDe8vUC45mWi9BT4w22FkIFNcBxEr/WL WBdzFARed7YfN+boRc7cpTgBRt0pXRDllzoDBymXeeoalZZVHc5s2aNcKugfdpHl6nqm QEIXtO7aCXerPqSzo6Mli5ym8rhKLKn5pWPo5E6o9i7lkcbFQ9kh8fLTadJ5gEToDhAv jOukUmkOTKOIycdm6+uKWBCucxe9aEnlI9p832z+Kavm0nf4mPkckOlPIf2wpNQaE/4s DOraPPaDsW409bTfpY5JK3rKXOE4hrdiT6uA4XBvA5OKJRLx10lnhLqRs3QTvFOJfwE+ ZO3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314875; x=1684906875; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/LNx4AQ8LEDs2bqV5zvn6xWFsTqqlF00MmHmvqgX6b8=; b=OVGszw7CcMPy2/sNO8GsddjpjipRD+Dq01M4a/744LMgIZCdI0IwacrQ9dlMzbB1oQ 0gKSJDXig/e8DEiju+oXxFl7GM3ov1eb3LtEHNzFbngrrlQwBUIr9SF2u2CVtjn7uJDR MEsUH2AVea0qoVr0yubXG7hJrZbgb697//qp+U/h9/R6nI0OBpytnqSKbqriYVByvpOD RowqwfQsJz1wCEXpiLfGDEb2oDQnRn4e9zscBQwMqVY7md/9v1yQhfjIgiK7mlmHXc6y Eudx/2oxWZCBeB6o4KNEYA0vg2ljpXz9XaFZaCGOpvF8innwgQMVoo546gF88pxfz+qy gzgg== X-Gm-Message-State: AAQBX9eQELIgNebScrK73QMY4OrdsBpRDWa6DFWGg37bCedmw5tGIiY3 4KkqlENIr7nk48vGmD0WcPbHV2YzEbXe+6K3zhjkhA== X-Google-Smtp-Source: AKy350Z1jvqtFiiyZfAeXYueB/IBPxYt2tj2bcj4oHidQ2P7pZZNMmQRHn12zKI9RcOMvTHzyR4D+Q== X-Received: by 2002:a5d:6649:0:b0:2c7:df22:1184 with SMTP id f9-20020a5d6649000000b002c7df221184mr8484465wrw.56.1682314874841; Sun, 23 Apr 2023 22:41:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 15/57] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st} Date: Mon, 24 Apr 2023 06:40:23 +0100 Message-Id: <20230424054105.1579315-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315437814100003 Interpret the variable argument placement in the caller. Pass data_type instead of is_64. We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 113 +++++++++++++++++++-------------------- 1 file changed, 56 insertions(+), 57 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 83c818a58b..6ce52b9612 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1526,15 +1526,18 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, /* Record the context of a call to the out of line helper code for the slow path for a load or store, so that we can later generate the correct helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, - TCGReg datalo, TCGReg datahi, TCGReg addrl= o, - TCGReg addrhi, tcg_insn_unit *raddr, +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, + MemOpIdx oi, TCGType type, + TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + tcg_insn_unit *raddr, tcg_insn_unit *label_ptr) { TCGLabelQemuLdst *label =3D new_ldst_label(s); =20 label->is_ld =3D is_ld; label->oi =3D oi; + label->type =3D type; label->datalo_reg =3D datalo; label->datahi_reg =3D datahi; label->addrlo_reg =3D addrlo; @@ -1796,41 +1799,28 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, M= emOp opc, TCGReg datalo, } #endif =20 -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) +static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, TCGType data_type) { - TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); - MemOpIdx oi; - MemOp opc; -#ifdef CONFIG_SOFTMMU - int mem_index; - TCGReg addend; - tcg_insn_unit *label_ptr; -#else - unsigned a_bits; -#endif - - datalo =3D *args++; - datahi =3D (is64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TARGET_LONG_BITS =3D=3D 64 ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); + MemOp opc =3D get_memop(oi); =20 #ifdef CONFIG_SOFTMMU - mem_index =3D get_mmuidx(oi); - addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1); + TCGReg addend=3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(o= i), 1); =20 - /* This a conditional BL only to load a pointer within this opcode int= o LR - for the slow path. We will not be using the value for a tail call.= */ - label_ptr =3D s->code_ptr; + /* + * This a conditional BL only to load a pointer within this opcode into + * LR for the slow path. We will not be using the value for a tail ca= ll. + */ + tcg_insn_unit *label_ptr =3D s->code_ptr; tcg_out_bl_imm(s, COND_NE, 0); =20 tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend, true); =20 - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } @@ -1918,41 +1908,26 @@ static void tcg_out_qemu_st_direct(TCGContext *s, M= emOp opc, TCGReg datalo, } #endif =20 -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) +static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, TCGType data_type) { - TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); - MemOpIdx oi; - MemOp opc; -#ifdef CONFIG_SOFTMMU - int mem_index; - TCGReg addend; - tcg_insn_unit *label_ptr; -#else - unsigned a_bits; -#endif - - datalo =3D *args++; - datahi =3D (is64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TARGET_LONG_BITS =3D=3D 64 ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); + MemOp opc =3D get_memop(oi); =20 #ifdef CONFIG_SOFTMMU - mem_index =3D get_mmuidx(oi); - addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0); + TCGReg addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(= oi), 0); =20 tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, addrlo, addend, true); =20 /* The conditional call must come last, as we're going to return here.= */ - label_ptr =3D s->code_ptr; + tcg_insn_unit *label_ptr =3D s->code_ptr; tcg_out_bl_imm(s, COND_NE, 0); =20 - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); } @@ -2245,16 +2220,40 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, 0); + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_ld(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I32); + } else { + tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], + args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, 1); + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_ld(s, args[0], args[1], args[2], -1, + args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], + args[4], TCG_TYPE_I64); + } break; case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, 0); + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_st(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I32); + } else { + tcg_out_qemu_st(s, args[0], -1, args[1], args[2], + args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, 1); + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_st(s, args[0], args[1], args[2], -1, + args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], + args[4], TCG_TYPE_I64); + } break; =20 case INDEX_op_bswap16_i32: --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315472; cv=none; d=zohomail.com; s=zohoarc; b=ZULSSIQ4eI2HirTn9+EraGVN/S+gJ80N6nAZbyVbxMJtMMnKgpb5hXZd2jCf+0fVmo6SmXZn2Gl2EgWOgyKeiCvZTqoKRnnkRXwF2izzNDnjlBp6VCnYmXmx1ucyqWzLOMJ8OlrudBmHEtUiuQ2xXu0SSchxmLKQkmEWkcMlj2Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315472; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZLKOkrrM6X6Chuoo3/tcJ4CYY7RF9VAHo0E2og71vlU=; b=T9Pz/ENbKGsQ2xmDYm+VJWcv8XqdYvqx1ZyfZUExYNWSCzoRk0xhqOpH1JHMCQX2IXcH/iMVslvGeM7HV2CAUSWCPx65iE7d1PoFI4FgXijyuCHOeg1UxkJ/haAMni+zbJkdbmzpk6V9zuWhpkWk0VqXJnAvqG1FI3W8XdfWQS0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315472171645.4166183660775; Sun, 23 Apr 2023 22:51:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqoyq-00083t-Vd; Mon, 24 Apr 2023 01:43:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqoxU-0005bv-Ti for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:56 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqowx-0004K1-2Y for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:52 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3f09b4a156eso25505845e9.3 for ; Sun, 23 Apr 2023 22:41:16 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. 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Merge tcg_out_qemu_*_{index,direct} and use it. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 248 ++++++++++++++++++--------------------- 1 file changed, 115 insertions(+), 133 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 6ce52b9612..b6b4ffc546 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1337,6 +1337,13 @@ static void tcg_out_vldst(TCGContext *s, ARMInsn ins= n, tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf); } =20 +typedef struct { + ARMCond cond; + TCGReg base; + int index; + bool index_scratch; +} HostAddress; + #ifdef CONFIG_SOFTMMU /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) @@ -1696,29 +1703,49 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) } #endif /* SOFTMMU */ =20 -static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addend, - bool scratch_addend) +static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, + TCGReg datahi, HostAddress h) { + TCGReg base; + /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); =20 switch (opc & MO_SSIZE) { case MO_UB: - tcg_out_ld8_r(s, COND_AL, datalo, addrlo, addend); + if (h.index < 0) { + tcg_out_ld8_12(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_ld8_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_SB: - tcg_out_ld8s_r(s, COND_AL, datalo, addrlo, addend); + if (h.index < 0) { + tcg_out_ld8s_8(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_ld8s_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_UW: - tcg_out_ld16u_r(s, COND_AL, datalo, addrlo, addend); + if (h.index < 0) { + tcg_out_ld16u_8(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_ld16u_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_SW: - tcg_out_ld16s_r(s, COND_AL, datalo, addrlo, addend); + if (h.index < 0) { + tcg_out_ld16s_8(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_ld16s_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_UL: - tcg_out_ld32_r(s, COND_AL, datalo, addrlo, addend); + if (h.index < 0) { + tcg_out_ld32_12(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_ld32_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_UQ: /* We used pair allocation for datalo, so already should be aligne= d. */ @@ -1726,87 +1753,59 @@ static void tcg_out_qemu_ld_index(TCGContext *s, Me= mOp opc, tcg_debug_assert(datahi =3D=3D datalo + 1); /* LDRD requires alignment; double-check that. */ if (get_alignment_bits(opc) >=3D MO_64) { + if (h.index < 0) { + tcg_out_ldrd_8(s, h.cond, datalo, h.base, 0); + break; + } /* * Rm (the second address op) must not overlap Rt or Rt + 1. * Since datalo is aligned, we can simplify the test via align= ment. * Flip the two address arguments if that works. */ - if ((addend & ~1) !=3D datalo) { - tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend); + if ((h.index & ~1) !=3D datalo) { + tcg_out_ldrd_r(s, h.cond, datalo, h.base, h.index); break; } - if ((addrlo & ~1) !=3D datalo) { - tcg_out_ldrd_r(s, COND_AL, datalo, addend, addrlo); + if ((h.base & ~1) !=3D datalo) { + tcg_out_ldrd_r(s, h.cond, datalo, h.index, h.base); break; } } - if (scratch_addend) { - tcg_out_ld32_rwb(s, COND_AL, datalo, addend, addrlo); - tcg_out_ld32_12(s, COND_AL, datahi, addend, 4); + if (h.index < 0) { + base =3D h.base; + if (datalo =3D=3D h.base) { + tcg_out_mov_reg(s, h.cond, TCG_REG_TMP, base); + base =3D TCG_REG_TMP; + } + } else if (h.index_scratch) { + tcg_out_ld32_rwb(s, h.cond, datalo, h.index, h.base); + tcg_out_ld32_12(s, h.cond, datahi, h.index, 4); + break; } else { - tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP, - addend, addrlo, SHIFT_IMM_LSL(0)); - tcg_out_ld32_12(s, COND_AL, datalo, TCG_REG_TMP, 0); - tcg_out_ld32_12(s, COND_AL, datahi, TCG_REG_TMP, 4); + tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, + h.base, h.index, SHIFT_IMM_LSL(0)); + base =3D TCG_REG_TMP; } + tcg_out_ld32_12(s, h.cond, datalo, base, 0); + tcg_out_ld32_12(s, h.cond, datahi, base, 4); break; default: g_assert_not_reached(); } } =20 -#ifndef CONFIG_SOFTMMU -static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, - TCGReg datahi, TCGReg addrlo) -{ - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); - - switch (opc & MO_SSIZE) { - case MO_UB: - tcg_out_ld8_12(s, COND_AL, datalo, addrlo, 0); - break; - case MO_SB: - tcg_out_ld8s_8(s, COND_AL, datalo, addrlo, 0); - break; - case MO_UW: - tcg_out_ld16u_8(s, COND_AL, datalo, addrlo, 0); - break; - case MO_SW: - tcg_out_ld16s_8(s, COND_AL, datalo, addrlo, 0); - break; - case MO_UL: - tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); - break; - case MO_UQ: - /* We used pair allocation for datalo, so already should be aligne= d. */ - tcg_debug_assert((datalo & 1) =3D=3D 0); - tcg_debug_assert(datahi =3D=3D datalo + 1); - /* LDRD requires alignment; double-check that. */ - if (get_alignment_bits(opc) >=3D MO_64) { - tcg_out_ldrd_8(s, COND_AL, datalo, addrlo, 0); - } else if (datalo =3D=3D addrlo) { - tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4); - tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); - } else { - tcg_out_ld32_12(s, COND_AL, datalo, addrlo, 0); - tcg_out_ld32_12(s, COND_AL, datahi, addrlo, 4); - } - break; - default: - g_assert_not_reached(); - } -} -#endif - static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); + HostAddress h; =20 #ifdef CONFIG_SOFTMMU - TCGReg addend=3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(o= i), 1); + h.cond =3D COND_AL; + h.base =3D addrlo; + h.index_scratch =3D true; + h.index =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 1= ); =20 /* * This a conditional BL only to load a pointer within this opcode into @@ -1815,80 +1814,51 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, tcg_insn_unit *label_ptr =3D s->code_ptr; tcg_out_bl_imm(s, COND_NE, 0); =20 - tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend, true); + tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); =20 add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ +#else unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } - if (guest_base) { - tcg_out_qemu_ld_index(s, opc, datalo, datahi, - addrlo, TCG_REG_GUEST_BASE, false); - } else { - tcg_out_qemu_ld_direct(s, opc, datalo, datahi, addrlo); - } + + h.cond =3D COND_AL; + h.base =3D addrlo; + h.index =3D guest_base ? TCG_REG_GUEST_BASE : -1; + h.index_scratch =3D false; + tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); #endif } =20 -static void tcg_out_qemu_st_index(TCGContext *s, ARMCond cond, MemOp opc, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addend, - bool scratch_addend) -{ - /* Byte swapping is left to middle-end expansion. */ - tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); - - switch (opc & MO_SIZE) { - case MO_8: - tcg_out_st8_r(s, cond, datalo, addrlo, addend); - break; - case MO_16: - tcg_out_st16_r(s, cond, datalo, addrlo, addend); - break; - case MO_32: - tcg_out_st32_r(s, cond, datalo, addrlo, addend); - break; - case MO_64: - /* We used pair allocation for datalo, so already should be aligne= d. */ - tcg_debug_assert((datalo & 1) =3D=3D 0); - tcg_debug_assert(datahi =3D=3D datalo + 1); - /* STRD requires alignment; double-check that. */ - if (get_alignment_bits(opc) >=3D MO_64) { - tcg_out_strd_r(s, cond, datalo, addrlo, addend); - } else if (scratch_addend) { - tcg_out_st32_rwb(s, cond, datalo, addend, addrlo); - tcg_out_st32_12(s, cond, datahi, addend, 4); - } else { - tcg_out_dat_reg(s, cond, ARITH_ADD, TCG_REG_TMP, - addend, addrlo, SHIFT_IMM_LSL(0)); - tcg_out_st32_12(s, cond, datalo, TCG_REG_TMP, 0); - tcg_out_st32_12(s, cond, datahi, TCG_REG_TMP, 4); - } - break; - default: - g_assert_not_reached(); - } -} - -#ifndef CONFIG_SOFTMMU static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, - TCGReg datahi, TCGReg addrlo) + TCGReg datahi, HostAddress h) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); =20 switch (opc & MO_SIZE) { case MO_8: - tcg_out_st8_12(s, COND_AL, datalo, addrlo, 0); + if (h.index < 0) { + tcg_out_st8_12(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_st8_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_16: - tcg_out_st16_8(s, COND_AL, datalo, addrlo, 0); + if (h.index < 0) { + tcg_out_st16_8(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_st16_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_32: - tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); + if (h.index < 0) { + tcg_out_st32_12(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_st32_r(s, h.cond, datalo, h.base, h.index); + } break; case MO_64: /* We used pair allocation for datalo, so already should be aligne= d. */ @@ -1896,29 +1866,39 @@ static void tcg_out_qemu_st_direct(TCGContext *s, M= emOp opc, TCGReg datalo, tcg_debug_assert(datahi =3D=3D datalo + 1); /* STRD requires alignment; double-check that. */ if (get_alignment_bits(opc) >=3D MO_64) { - tcg_out_strd_8(s, COND_AL, datalo, addrlo, 0); + if (h.index < 0) { + tcg_out_strd_8(s, h.cond, datalo, h.base, 0); + } else { + tcg_out_strd_r(s, h.cond, datalo, h.base, h.index); + } + } else if (h.index_scratch) { + tcg_out_st32_rwb(s, h.cond, datalo, h.index, h.base); + tcg_out_st32_12(s, h.cond, datahi, h.index, 4); } else { - tcg_out_st32_12(s, COND_AL, datalo, addrlo, 0); - tcg_out_st32_12(s, COND_AL, datahi, addrlo, 4); + tcg_out_dat_reg(s, h.cond, ARITH_ADD, TCG_REG_TMP, + h.base, h.index, SHIFT_IMM_LSL(0)); + tcg_out_st32_12(s, h.cond, datalo, TCG_REG_TMP, 0); + tcg_out_st32_12(s, h.cond, datahi, TCG_REG_TMP, 4); } break; default: g_assert_not_reached(); } } -#endif =20 static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); + HostAddress h; =20 #ifdef CONFIG_SOFTMMU - TCGReg addend =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(= oi), 0); - - tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, - addrlo, addend, true); + h.cond =3D COND_EQ; + h.base =3D addrlo; + h.index_scratch =3D true; + h.index =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 0= ); + tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); =20 /* The conditional call must come last, as we're going to return here.= */ tcg_insn_unit *label_ptr =3D s->code_ptr; @@ -1926,17 +1906,19 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, =20 add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi, addrlo, addrhi, s->code_ptr, label_ptr); -#else /* !CONFIG_SOFTMMU */ +#else unsigned a_bits =3D get_alignment_bits(opc); + + h.cond =3D COND_AL; if (a_bits) { tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); + h.cond =3D COND_EQ; } - if (guest_base) { - tcg_out_qemu_st_index(s, COND_AL, opc, datalo, datahi, - addrlo, TCG_REG_GUEST_BASE, false); - } else { - tcg_out_qemu_st_direct(s, opc, datalo, datahi, addrlo); - } + + h.base =3D addrlo; + h.index =3D guest_base ? TCG_REG_GUEST_BASE : -1; + h.index_scratch =3D false; + tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); #endif } =20 --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315212; cv=none; d=zohomail.com; s=zohoarc; b=n2G7DB0951H8+F4lXmT3fZEgnqv6cUSuxCviRRefaJqK3Ba0j7JyuO3Y9OpK3nh3DMctZHl49C1KrWdtP49AYZZc+U94jLlEOsI6kEC7BeLPVjJRp9tm2m4UFntvmXxplfZeu9YKwfeHraULgoJQ3XSEbfwDwk3H/WL07M6Vphc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315212; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SdzMRJhqVnkJZuasJRxOLnNhkaxRsl4XQRta0/ryyec=; b=MK/dN1eqeU7ry4zqQu7ns08gFad4ETx4gdBvaiTiFZgbuufzvo7pMNzdqqDtc0qUBSmDUVYriq6JA8T1Y3PNR3S3evRk4JxSJv9QUHCCbv3e4CVakKvD+5LhkSWs8/hhSb7YMBts+utvr+Vz5HmZk3lHrD7EEX11r3CtJzVBePU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16823152122281018.3525835820166; Sun, 23 Apr 2023 22:46:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqoxk-0005sc-O3; Mon, 24 Apr 2023 01:42:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqoxQ-0005YZ-7S for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:48 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqoww-0004Ka-K0 for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:47 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-2f6401ce8f8so2308741f8f.3 for ; Sun, 23 Apr 2023 22:41:17 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. 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Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 351 ++++++++++++++++++--------------------- 1 file changed, 159 insertions(+), 192 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index b6b4ffc546..c744512778 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1434,125 +1434,6 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGR= eg argreg, } } =20 -#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS) - -/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256); - -/* These offsets are built into the LDRD below. */ -QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); -QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 4); - -/* Load and compare a TLB entry, leaving the flags set. Returns the regis= ter - containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */ - -static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, - MemOp opc, int mem_index, bool is_load) -{ - int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); - unsigned s_mask =3D (1 << (opc & MO_SIZE)) - 1; - unsigned a_mask =3D (1 << get_alignment_bits(opc)) - 1; - TCGReg t_addr; - - /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */ - tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); - - /* Extract the tlb index from the address into R0. */ - tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo, - SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)); - - /* - * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. - * Load the tlb comparator into R2/R3 and the fast path addend into R1. - */ - if (cmp_off =3D=3D 0) { - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); - } else { - tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); - } - } else { - tcg_out_dat_reg(s, COND_AL, ARITH_ADD, - TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); - } else { - tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); - } - } - - /* Load the tlb addend. */ - tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, - offsetof(CPUTLBEntry, addend)); - - /* - * Check alignment, check comparators. - * Do this in 2-4 insns. Use MOVW for v7, if possible, - * to reduce the number of sequential conditional instructions. - * Almost all guests have at least 4k pages, which means that we need - * to clear at least 9 bits even for an 8-byte memory, which means it - * isn't worth checking for an immediate operand for BIC. - * - * For unaligned accesses, test the page of the last unit of alignment. - * This leaves the least significant alignment bits unchanged, and of - * course must be zero. - */ - t_addr =3D addrlo; - if (a_mask < s_mask) { - t_addr =3D TCG_REG_R0; - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, - addrlo, s_mask - a_mask); - } - if (use_armv7_instructions && TARGET_PAGE_BITS <=3D 16) { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(TARGET_PAGE_MASK | a_mas= k)); - tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, - t_addr, TCG_REG_TMP, 0); - tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP,= 0); - } else { - if (a_mask) { - tcg_debug_assert(a_mask <=3D 0xff); - tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); - } - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, - SHIFT_IMM_LSR(TARGET_PAGE_BITS)); - tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, - 0, TCG_REG_R2, TCG_REG_TMP, - SHIFT_IMM_LSL(TARGET_PAGE_BITS)); - } - - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0); - } - - return TCG_REG_R1; -} - -/* Record the context of a call to the out of line helper code for the slow - path for a load or store, so that we can later generate the correct - helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, - MemOpIdx oi, TCGType type, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addrhi, - tcg_insn_unit *raddr, - tcg_insn_unit *label_ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D type; - label->datalo_reg =3D datalo; - label->datahi_reg =3D datahi; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr; -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGReg argreg; @@ -1636,29 +1517,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) return true; } #else - -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrl= o, - TCGReg addrhi, unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; - - /* We are expecting a_bits to max out at 7, and can easily support 8. = */ - tcg_debug_assert(a_mask <=3D 0xff); - /* tst addr, #mask */ - tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); - - /* blne slow_path */ - label->label_ptr[0] =3D s->code_ptr; - tcg_out_bl_imm(s, COND_NE, 0); - - label->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { if (!reloc_pc24(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -1703,6 +1561,134 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) } #endif /* SOFTMMU */ =20 +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, bool is_ld) +{ + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + MemOp a_bits =3D get_alignment_bits(opc); + unsigned a_mask =3D (1 << a_bits) - 1; + +#ifdef CONFIG_SOFTMMU + int mem_index =3D get_mmuidx(oi); + int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write); + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + unsigned s_mask =3D (1 << (opc & MO_SIZE)) - 1; + TCGReg t_addr; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */ + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256); + QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); + QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 4); + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); + + /* Extract the tlb index from the address into R0. */ + tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo, + SHIFT_IMM_LSR(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)); + + /* + * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. + * Load the tlb comparator into R2/R3 and the fast path addend into R1. + */ + if (cmp_off =3D=3D 0) { + if (TARGET_LONG_BITS =3D=3D 64) { + tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); + } else { + tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); + } + } else { + tcg_out_dat_reg(s, COND_AL, ARITH_ADD, + TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); + if (TARGET_LONG_BITS =3D=3D 64) { + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); + } else { + tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); + } + } + + /* Load the tlb addend. */ + tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, + offsetof(CPUTLBEntry, addend)); + + /* + * Check alignment, check comparators. + * Do this in 2-4 insns. Use MOVW for v7, if possible, + * to reduce the number of sequential conditional instructions. + * Almost all guests have at least 4k pages, which means that we need + * to clear at least 9 bits even for an 8-byte memory, which means it + * isn't worth checking for an immediate operand for BIC. + * + * For unaligned accesses, test the page of the last unit of alignment. + * This leaves the least significant alignment bits unchanged, and of + * course must be zero. + */ + t_addr =3D addrlo; + if (a_mask < s_mask) { + t_addr =3D TCG_REG_R0; + tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, + addrlo, s_mask - a_mask); + } + if (use_armv7_instructions && TARGET_PAGE_BITS <=3D 16) { + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(TARGET_PAGE_MASK | a_mas= k)); + tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, + t_addr, TCG_REG_TMP, 0); + tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP,= 0); + } else { + if (a_mask) { + tcg_debug_assert(a_mask <=3D 0xff); + tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); + } + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, + SHIFT_IMM_LSR(TARGET_PAGE_BITS)); + tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, + 0, TCG_REG_R2, TCG_REG_TMP, + SHIFT_IMM_LSL(TARGET_PAGE_BITS)); + } + + if (TARGET_LONG_BITS =3D=3D 64) { + tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0); + } + + *h =3D (HostAddress){ + .cond =3D COND_AL, + .base =3D addrlo, + .index =3D TCG_REG_R1, + .index_scratch =3D true, + }; +#else + if (a_mask) { + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + /* We are expecting a_bits to max out at 7 */ + tcg_debug_assert(a_mask <=3D 0xff); + /* tst addr, #mask */ + tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); + } + + *h =3D (HostAddress){ + .cond =3D COND_AL, + .base =3D addrlo, + .index =3D guest_base ? TCG_REG_GUEST_BASE : -1, + .index_scratch =3D false, + }; +#endif + + return ldst; +} + static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, TCGReg datahi, HostAddress h) { @@ -1799,37 +1785,28 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - h.cond =3D COND_AL; - h.base =3D addrlo; - h.index_scratch =3D true; - h.index =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 1= ); + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, true); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; =20 - /* - * This a conditional BL only to load a pointer within this opcode into - * LR for the slow path. We will not be using the value for a tail ca= ll. - */ - tcg_insn_unit *label_ptr =3D s->code_ptr; - tcg_out_bl_imm(s, COND_NE, 0); + /* + * This a conditional BL only to load a pointer within this + * opcode into LR for the slow path. We will not be using + * the value for a tail call. + */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_bl_imm(s, COND_NE, 0); =20 - tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); - - add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); + tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); + } else { + tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); } - - h.cond =3D COND_AL; - h.base =3D addrlo; - h.index =3D guest_base ? TCG_REG_GUEST_BASE : -1; - h.index_scratch =3D false; - tcg_out_qemu_ld_direct(s, opc, datalo, datahi, h); -#endif } =20 static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, @@ -1891,35 +1868,25 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - h.cond =3D COND_EQ; - h.base =3D addrlo; - h.index_scratch =3D true; - h.index =3D tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 0= ); - tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, false); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; =20 - /* The conditional call must come last, as we're going to return here.= */ - tcg_insn_unit *label_ptr =3D s->code_ptr; - tcg_out_bl_imm(s, COND_NE, 0); - - add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - - h.cond =3D COND_AL; - if (a_bits) { - tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); h.cond =3D COND_EQ; - } + tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); =20 - h.base =3D addrlo; - h.index =3D guest_base ? TCG_REG_GUEST_BASE : -1; - h.index_scratch =3D false; - tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); -#endif + /* The conditional call is last, as we're going to return here. */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_bl_imm(s, COND_NE, 0); + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); + } else { + tcg_out_qemu_st_direct(s, opc, datalo, datahi, h); + } } =20 static void tcg_out_epilogue(TCGContext *s); --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315121601110.26199312232438; Sun, 23 Apr 2023 22:45:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqoyp-0007q7-PG; Mon, 24 Apr 2023 01:43:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqoxW-0005cb-Bu for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:56 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqoww-0004Kp-Iw for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:54 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-3f182d745deso39584725e9.0 for ; Sun, 23 Apr 2023 22:41:17 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314876; x=1684906876; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3QSS2Cem/9vemiWtpW9BgZNru5jWel0P/bcFkdHXKRA=; b=nP+GDUtTtqhLNhHZedzxTZtPwWc1tuMfYCVn+xi4qh8exxNiVkmurV7x+7y9i4YODH +NOCqfCfrg9T/MIvpctaqJqF88axh1ihEh6s+5RfugQiEqwWryWG/gZ7nVtOs1WhB7tR Bp+OH21AS4PkzshrM2Nhf+FwJSAekg3GlV9YvVnG9EiRyCBR+xRu+w6wdNdWd61nFwIT AuOxlGaiSNMrf47fKfH41DMB55cbZHQYdYfkOlY771q88PQMk4K9AcvJUgyDK6406Iwn l4L4O7a5khcGVpizwltyf3CnHmbx67+uAQG/Jc7UwDNywofdEbVHuTmOrHwszYwHL/uy ORhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314876; x=1684906876; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3QSS2Cem/9vemiWtpW9BgZNru5jWel0P/bcFkdHXKRA=; b=JBC6QScbZk4ZvnUdOzWglyD3JYV7IXcT+IWFBivxPYbDdUhzeoLGgRDTHJ4oENi+aR 6x5ctGFTAK5ea43J+Du9WHeTCxOjV1NxuHNEmOU22Tl69p90Mm1g4x5FK2DDEs5bJ/ul cx7+B0OEbTjmEMMAFAtjGuj3LnWI+LcRuzFGDCz9t5BIwHM6v9GbXtnCQHWS6caZKiLC yR4tXcPCwQG5NvscqhW7ndPx+sh81ZQNWwQgnCoaIUadbglxHnc8CpQAWSpKYQVMcJLa Dzjs3lO1yh2AUtxSPfJW10FNfSLO8Dz3plyzJ8otPJcDNo0t3atzO6kobGirkdIy8Gn8 r2fQ== X-Gm-Message-State: AAQBX9c1Q5z6m1+euCUl4dEt91GOq+3XHSX3XdMCDqRq2xG8c07rDHaR +/aIj6Hk6g8+ncdJffiAOM5bh6nwwJoO0jNNHVFwdQ== X-Google-Smtp-Source: AKy350bmXsUvN3DFYX9vlVB2sFfO+UZZD7O8w3+WaN5loAzH4tgtVejnjNZnqCD6X1sw2W6ZUbg3UA== X-Received: by 2002:a5d:6b04:0:b0:2f6:121a:c1d0 with SMTP id v4-20020a5d6b04000000b002f6121ac1d0mr8780030wrw.19.1682314876560; Sun, 23 Apr 2023 22:41:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 18/57] tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld, st} Date: Mon, 24 Apr 2023 06:40:26 +0100 Message-Id: <20230424054105.1579315-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1682315123511100007 Content-Type: text/plain; charset="utf-8" Interpret the variable argument placement in the caller. Shift some code around slightly to share more between softmmu and user-only. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/loongarch64/tcg-target.c.inc | 100 +++++++++++++------------------ 1 file changed, 42 insertions(+), 58 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 0940788c6f..2e3c67054b 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1049,39 +1049,31 @@ static void tcg_out_qemu_ld_indexed(TCGContext *s, = TCGReg rd, TCGReg rj, } } =20 -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGType typ= e) +static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, + MemOpIdx oi, TCGType data_type) { - TCGReg addr_regl; - TCGReg data_regl; - MemOpIdx oi; - MemOp opc; -#if defined(CONFIG_SOFTMMU) + MemOp opc =3D get_memop(oi); + TCGReg base, index; + +#ifdef CONFIG_SOFTMMU tcg_insn_unit *label_ptr[1]; -#else - unsigned a_bits; -#endif - TCGReg base; =20 - data_regl =3D *args++; - addr_regl =3D *args++; - oi =3D *args++; - opc =3D get_memop(oi); - -#if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 1); - base =3D tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); - tcg_out_qemu_ld_indexed(s, data_regl, base, TCG_REG_TMP2, opc, type); - add_qemu_ldst_label(s, 1, oi, type, - data_regl, addr_regl, - s->code_ptr, label_ptr); + tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1); + index =3D TCG_REG_TMP2; #else - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { - tcg_out_test_alignment(s, true, addr_regl, a_bits); + tcg_out_test_alignment(s, true, addr_reg, a_bits); } - base =3D tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); - TCGReg guest_base_reg =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_RE= G_ZERO; - tcg_out_qemu_ld_indexed(s, data_regl, base, guest_base_reg, opc, type); + index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; +#endif + + base =3D tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0); + tcg_out_qemu_ld_indexed(s, data_reg, base, index, opc, data_type); + +#ifdef CONFIG_SOFTMMU + add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, + s->code_ptr, label_ptr); #endif } =20 @@ -1109,39 +1101,31 @@ static void tcg_out_qemu_st_indexed(TCGContext *s, = TCGReg data, } } =20 -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGType typ= e) +static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, + MemOpIdx oi, TCGType data_type) { - TCGReg addr_regl; - TCGReg data_regl; - MemOpIdx oi; - MemOp opc; -#if defined(CONFIG_SOFTMMU) + MemOp opc =3D get_memop(oi); + TCGReg base, index; + +#ifdef CONFIG_SOFTMMU tcg_insn_unit *label_ptr[1]; -#else - unsigned a_bits; -#endif - TCGReg base; =20 - data_regl =3D *args++; - addr_regl =3D *args++; - oi =3D *args++; - opc =3D get_memop(oi); - -#if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 0); - base =3D tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); - tcg_out_qemu_st_indexed(s, data_regl, base, TCG_REG_TMP2, opc); - add_qemu_ldst_label(s, 0, oi, type, - data_regl, addr_regl, - s->code_ptr, label_ptr); + tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0); + index =3D TCG_REG_TMP2; #else - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { - tcg_out_test_alignment(s, false, addr_regl, a_bits); + tcg_out_test_alignment(s, false, addr_reg, a_bits); } - base =3D tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); - TCGReg guest_base_reg =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_RE= G_ZERO; - tcg_out_qemu_st_indexed(s, data_regl, base, guest_base_reg, opc); + index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; +#endif + + base =3D tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0); + tcg_out_qemu_st_indexed(s, data_reg, base, index, opc); + +#ifdef CONFIG_SOFTMMU + add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, + s->code_ptr, label_ptr); #endif } =20 @@ -1564,16 +1548,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, TCG_TYPE_I32); + tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, TCG_TYPE_I64); + tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); break; case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, TCG_TYPE_I32); + tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, TCG_TYPE_I64); + tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); break; =20 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315476; cv=none; d=zohomail.com; s=zohoarc; b=S+EfgM/WSc+DHoAysA12qThRQnDSACXb7AVf0x9kDXyYVTvbRmqRR9wiGAkO+y6MaFxuH9UOFDqA46T59aj6Nc4mC93EzsnUTMbAYksGFE/1HpcCx8QEcDQM4HWcdq4w2ISkc6opfXEvY7yTDhueygcOR+SH3plz/1QgDQOMAOs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315476; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PCb5/pWQaLjZZ2RDI9ILyX7XKLBQiXMqZTnOPo1b490=; b=DZjYVY6wWq0dmrUmOV0PyEUiuTb2BLNgPgwjK7Evz0mlOh8ueoKPPqZb/ghPZEyMVsPVkOfclV4xnT6jI8+4SDL7JTglaw//7MdMTkLFN7kIvG2mlQYZpz01imqzG9h/x9uy266fPj7BWToRjtF5y9BwQ6KwdT9FKkdXHb9dFHg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168231547599423.951214087426365; Sun, 23 Apr 2023 22:51:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqoyz-0008Tp-NN; Mon, 24 Apr 2023 01:43:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqoxM-0005YJ-UV for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:45 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqoww-0004Lb-Jb for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:44 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-2fa47de5b04so3816477f8f.1 for ; Sun, 23 Apr 2023 22:41:17 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314877; x=1684906877; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PCb5/pWQaLjZZ2RDI9ILyX7XKLBQiXMqZTnOPo1b490=; b=nBlK/Y3e6OrLbvmmBZK+Ck3zqoF5xRg4eJw3PAWaoB3bt09Ui/wmGRXZUDqHHUyB0i czgGBt8O3flbbrqS2Hp4N2oUzChqbfQFsXzGtya72AkRzotoaeLIzG/zEOAbXvbYE/Go K19Hy275fP1e5m3wGjEMgWDTUP4n/bYVdM2HdxACCHdhwcB0tU8jwMmmw+1I8F/+3Ucb /WhATI0bZguxziHqIjXjimIcnUQpRFzoh5nDK4Brtqhrx/EN/jhHjeq6L1PFofa3oTVs sgUkDSkCOt3wfxynDfq1iLoomH5FmmNG/MM8GFaGOhq4Ym/eoH9wzEMu1UD8G1G6qJ0i 1orQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314877; x=1684906877; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PCb5/pWQaLjZZ2RDI9ILyX7XKLBQiXMqZTnOPo1b490=; b=E2eASAc4e7OVJcV7Ybq6fRRxGItKYttV9d50diYdqSUVVjrKjphKWMVAIoi5Prjoe9 eiO+2GipHBlSX/90hEot9dRvPVQ6GH9iQ0ObkL985rXfy8Pa7ceXMI7/dtuv8M2ShaKg FG96KVBpWS67pf7NwJCJ6tlWJ2oZztGB5W/XGP+R4yWe+3WBdJpe51wTf7T/71iK2b02 iEytf+Z/8awQung14E3SxqKS2LFTChCgHfI7PbX6J51cuh4kEIsZpsTBgJTE6YffsRuG 77ciOfBkOw3Y/JDkpgy1vEI7c+jYcyDgF6NxV6j/Wzt5flfZIe4JinZcHVXtIPuLDWN+ jWpg== X-Gm-Message-State: AAQBX9dVS8hLa2SHbRLIPO6h+vE5odLHRWc2zAykx+IbpytWfrjUe+MC w7sMllB17vA03XsMjlOzqrFwkM4apBZKQIJkvnr56w== X-Google-Smtp-Source: AKy350YFXELN3xfO8c3iO6SbjKJx6tZkZEqw17RJizFPi2lmw20nFu+gig8y59p58OK94z6ItJaUVA== X-Received: by 2002:a5d:5145:0:b0:2cf:f01f:ed89 with SMTP id u5-20020a5d5145000000b002cff01fed89mr8405255wrt.24.1682314877060; Sun, 23 Apr 2023 22:41:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 19/57] tcg/loongarch64: Introduce HostAddress Date: Mon, 24 Apr 2023 06:40:27 +0100 Message-Id: <20230424054105.1579315-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315476957100001 Content-Type: text/plain; charset="utf-8" Collect the 2 parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st}_direct to use it. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/loongarch64/tcg-target.c.inc | 55 +++++++++++++++++--------------- 1 file changed, 30 insertions(+), 25 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 2e3c67054b..6a87a5e5a3 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1013,36 +1013,41 @@ static TCGReg tcg_out_zext_addr_if_32_bit(TCGContex= t *s, return addr; } =20 -static void tcg_out_qemu_ld_indexed(TCGContext *s, TCGReg rd, TCGReg rj, - TCGReg rk, MemOp opc, TCGType type) +typedef struct { + TCGReg base; + TCGReg index; +} HostAddress; + +static void tcg_out_qemu_ld_indexed(TCGContext *s, MemOp opc, TCGType type, + TCGReg rd, HostAddress h) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); =20 switch (opc & MO_SSIZE) { case MO_UB: - tcg_out_opc_ldx_bu(s, rd, rj, rk); + tcg_out_opc_ldx_bu(s, rd, h.base, h.index); break; case MO_SB: - tcg_out_opc_ldx_b(s, rd, rj, rk); + tcg_out_opc_ldx_b(s, rd, h.base, h.index); break; case MO_UW: - tcg_out_opc_ldx_hu(s, rd, rj, rk); + tcg_out_opc_ldx_hu(s, rd, h.base, h.index); break; case MO_SW: - tcg_out_opc_ldx_h(s, rd, rj, rk); + tcg_out_opc_ldx_h(s, rd, h.base, h.index); break; case MO_UL: if (type =3D=3D TCG_TYPE_I64) { - tcg_out_opc_ldx_wu(s, rd, rj, rk); + tcg_out_opc_ldx_wu(s, rd, h.base, h.index); break; } /* fallthrough */ case MO_SL: - tcg_out_opc_ldx_w(s, rd, rj, rk); + tcg_out_opc_ldx_w(s, rd, h.base, h.index); break; case MO_UQ: - tcg_out_opc_ldx_d(s, rd, rj, rk); + tcg_out_opc_ldx_d(s, rd, h.base, h.index); break; default: g_assert_not_reached(); @@ -1053,23 +1058,23 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); - TCGReg base, index; + HostAddress h; =20 #ifdef CONFIG_SOFTMMU tcg_insn_unit *label_ptr[1]; =20 tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1); - index =3D TCG_REG_TMP2; + h.index =3D TCG_REG_TMP2; #else unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addr_reg, a_bits); } - index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; + h.index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; #endif =20 - base =3D tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0); - tcg_out_qemu_ld_indexed(s, data_reg, base, index, opc, data_type); + h.base =3D tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0); + tcg_out_qemu_ld_indexed(s, opc, data_type, data_reg, h); =20 #ifdef CONFIG_SOFTMMU add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, @@ -1077,24 +1082,24 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, #endif } =20 -static void tcg_out_qemu_st_indexed(TCGContext *s, TCGReg data, - TCGReg rj, TCGReg rk, MemOp opc) +static void tcg_out_qemu_st_indexed(TCGContext *s, MemOp opc, + TCGReg rd, HostAddress h) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); =20 switch (opc & MO_SIZE) { case MO_8: - tcg_out_opc_stx_b(s, data, rj, rk); + tcg_out_opc_stx_b(s, rd, h.base, h.index); break; case MO_16: - tcg_out_opc_stx_h(s, data, rj, rk); + tcg_out_opc_stx_h(s, rd, h.base, h.index); break; case MO_32: - tcg_out_opc_stx_w(s, data, rj, rk); + tcg_out_opc_stx_w(s, rd, h.base, h.index); break; case MO_64: - tcg_out_opc_stx_d(s, data, rj, rk); + tcg_out_opc_stx_d(s, rd, h.base, h.index); break; default: g_assert_not_reached(); @@ -1105,23 +1110,23 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); - TCGReg base, index; + HostAddress h; =20 #ifdef CONFIG_SOFTMMU tcg_insn_unit *label_ptr[1]; =20 tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0); - index =3D TCG_REG_TMP2; + h.index =3D TCG_REG_TMP2; #else unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, false, addr_reg, a_bits); } - index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; + h.index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; #endif =20 - base =3D tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0); - tcg_out_qemu_st_indexed(s, data_reg, base, index, opc); + h.base =3D tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0); + tcg_out_qemu_st_indexed(s, opc, data_reg, h); =20 #ifdef CONFIG_SOFTMMU add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315111; cv=none; d=zohomail.com; s=zohoarc; b=Y2szwhMNmPjIxmZvJNp1lgQX9yGifcFeSTjZ1jVViG8g2mdbI7E7JJVWUiJ7RRiara1OWsFy7cA4qHQ/OoDmwKoYEc3vscsCEhCEM5/y2ABKq3qay1PsXft4bTQK2OTh1u1kwEN8ROMyurenPHn2BpJFL7ZmIdadaOi3v7FIs7k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315111; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=N0k727NYZjnrZBTMhehFGEr2gxv6PrKgfLN9LqxUppY=; b=TJ+IxPHzEINiOnEhU/TJ/aDVKZu16pGnL2ogNsz4TrLrsLDM47QGVaCKLv1RMHTzlJ8pvS8IXWAZdZOLuYxpezE590r1TH3xhXXnbvvyWhLpyAjyaUqI/DegfQfMyqxQKkn1BaO4cFxfSdFuORN5H7KNAoDVedSkJM4XVModAAc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315111587686.5320557164273; Sun, 23 Apr 2023 22:45:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqozV-0001ET-5W; Mon, 24 Apr 2023 01:43:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqoxc-0005fr-5C for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:42:02 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqowy-0004M3-G9 for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:41:58 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-2efbaad9d76so3634976f8f.0 for ; Sun, 23 Apr 2023 22:41:18 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314877; x=1684906877; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N0k727NYZjnrZBTMhehFGEr2gxv6PrKgfLN9LqxUppY=; b=fV2rQJXwd+KiTb15xtACEtO4QVtnvGF7x/pga+wxK6vI8bNPxaGJqjHUx/S/QkG6Vq 4GKIUstba3BA14Bko9bFjIP87yyfGjZomyhk0qsng2P/nYCk4EeeJvHn3oAQp/Dj7rED 1/R/EW88hdranhd3ZdYnGJHEcrfEPU+OcECcHLUJpsLjArOF4DOgJMRfjqFKwBxXdfm8 jwpc12buMj2MHUNcjvNLo52MmRM1mJawKFJP6EzCfrJTs0pqPyd6FyQ8GERHTx4td+Pu AFS0EjSjFBGe6vAN7ezkqcea0L/Fz7sfewAkq93RRRCMixnbWacXy87V+13O5AY+Cnp6 j77A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314877; x=1684906877; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N0k727NYZjnrZBTMhehFGEr2gxv6PrKgfLN9LqxUppY=; b=R1GgUT5zKj2PhsIprFN9EBeSY0+fAGFpBF+SKIJ0iAy/ypsMPLSWwC8kNRhjal6bnt FXXSIZ0ohAVMi9AXuVKtxc9MrF+utrStGWNq7Fa8gu5MUXfj2Q07Syh/EKoAL0L08oeV t7hwqz/zxcUFijYLJeptHjRGvHxgPCTPWYsJcoSSNtTtousHNvo9I+3tMZDEOD7NFfJL Z7wCQZNaJapkzrNqBeG+weu3ekqkqTThl9cOJ6WGZlGrN2sOezUkKdgDmqWuOxQEA18W nnbnpSknUReiH3Ka4BGNHiJRXl/eYsUuYwZGcGFElJOW7GnOHaU7UkkQIY16QBAMtOv1 SncA== X-Gm-Message-State: AAQBX9f1RdfHmfOU1c5yyB1i8Ce60PdjGqV6NcGcRiGDV32K2onD56hZ 1plrnHPKkonfAD6t4XspXIKNnn9LmFO0u/ECOMqTqg== X-Google-Smtp-Source: AKy350aUHGYfqysZJYPZ+zggMGmLWJO8akqGRHx9KiTDrQOUgTssh7JSeCYFPKEHnAvHDW8wo8GTKw== X-Received: by 2002:a5d:4a0a:0:b0:2f0:bab2:dc3c with SMTP id m10-20020a5d4a0a000000b002f0bab2dc3cmr10009660wrq.27.1682314877649; Sun, 23 Apr 2023 22:41:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 20/57] tcg/loongarch64: Introduce prepare_host_addr Date: Mon, 24 Apr 2023 06:40:28 +0100 Message-Id: <20230424054105.1579315-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315113621100003 Content-Type: text/plain; charset="utf-8" Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, tcg_out_zext_addr_if_32_bit, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 255 +++++++++++++------------------ 1 file changed, 105 insertions(+), 150 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 6a87a5e5a3..2f2c34b930 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -818,81 +818,12 @@ static void * const qemu_st_helpers[4] =3D { [MO_64] =3D helper_le_stq_mmu, }; =20 -/* We expect to use a 12-bit negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); - static bool tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) { tcg_out_opc_b(s, 0); return reloc_br_sd10k16(s->code_ptr - 1, target); } =20 -/* - * Emits common code for TLB addend lookup, that eventually loads the - * addend in TCG_REG_TMP2. - */ -static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, MemOpIdx oi, - tcg_insn_unit **label_ptr, bool is_load) -{ - MemOp opc =3D get_memop(oi); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_bits =3D get_alignment_bits(opc); - tcg_target_long compare_mask; - int mem_index =3D get_mmuidx(oi); - int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); - int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); - int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); - - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); - - tcg_out_opc_srli_d(s, TCG_REG_TMP2, addrl, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); - tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); - - /* Load the tlb comparator and the addend. */ - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, - is_load ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, - offsetof(CPUTLBEntry, addend)); - - /* We don't support unaligned accesses. */ - if (a_bits < s_bits) { - a_bits =3D s_bits; - } - /* Clear the non-page, non-alignment bits from the address. */ - compare_mask =3D (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - = 1); - tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); - tcg_out_opc_and(s, TCG_REG_TMP1, TCG_REG_TMP1, addrl); - - /* Compare masked address with the TLB entry. */ - label_ptr[0] =3D s->code_ptr; - tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0); - - /* TLB Hit - addend in TCG_REG_TMP2, ready for use. */ -} - -static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, - TCGType type, - TCGReg datalo, TCGReg addrlo, - void *raddr, tcg_insn_unit **label_ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D type; - label->datalo_reg =3D datalo; - label->datahi_reg =3D 0; /* unused */ - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D 0; /* unused */ - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr[0]; -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { MemOpIdx oi =3D l->oi; @@ -941,33 +872,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, T= CGLabelQemuLdst *l) return tcg_out_goto(s, l->raddr); } #else - -/* - * Alignment helpers for user-mode emulation - */ - -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_= reg, - unsigned a_bits) -{ - TCGLabelQemuLdst *l =3D new_ldst_label(s); - - l->is_ld =3D is_ld; - l->addrlo_reg =3D addr_reg; - - /* - * Without micro-architecture details, we don't know which of bstrpick= or - * andi is faster, so use bstrpick as it's not constrained by imm field - * width. (Not to say alignments >=3D 2^12 are going to happen any time - * soon, though) - */ - tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1); - - l->label_ptr[0] =3D s->code_ptr; - tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0); - - l->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { /* resolve label address */ @@ -997,27 +901,102 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) =20 #endif /* CONFIG_SOFTMMU */ =20 -/* - * `ext32u` the address register into the temp register given, - * if target is 32-bit, no-op otherwise. - * - * Returns the address register ready for use with TLB addend. - */ -static TCGReg tcg_out_zext_addr_if_32_bit(TCGContext *s, - TCGReg addr, TCGReg tmp) -{ - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, tmp, addr); - return tmp; - } - return addr; -} - typedef struct { TCGReg base; TCGReg index; } HostAddress; =20 +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addr_reg, MemOpIdx oi, + bool is_ld) +{ + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + +#ifdef CONFIG_SOFTMMU + unsigned s_bits =3D opc & MO_SIZE; + int mem_index =3D get_mmuidx(oi); + int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); + int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); + tcg_target_long compare_mask; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); + + tcg_out_opc_srli_d(s, TCG_REG_TMP2, addr_reg, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); + tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); + + /* Load the tlb comparator and the addend. */ + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, + is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, + offsetof(CPUTLBEntry, addend)); + + /* We don't support unaligned accesses. */ + if (a_bits < s_bits) { + a_bits =3D s_bits; + } + /* Clear the non-page, non-alignment bits from the address. */ + compare_mask =3D (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - = 1); + tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); + tcg_out_opc_and(s, TCG_REG_TMP1, TCG_REG_TMP1, addr_reg); + + /* Compare masked address with the TLB entry. */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0); + + h->index =3D TCG_REG_TMP2; +#else + if (a_bits) { + ldst =3D new_ldst_label(s); + + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + /* + * Without micro-architecture details, we don't know which of + * bstrpick or andi is faster, so use bstrpick as it's not + * constrained by imm field width. Not to say alignments >=3D 2^12 + * are going to happen any time soon. + */ + tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1); + + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0); + } + + h->index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; +#endif + + if (TARGET_LONG_BITS =3D=3D 32) { + h->base =3D TCG_REG_TMP0; + tcg_out_ext32u(s, h->base, addr_reg); + } else { + h->base =3D addr_reg; + } + + return ldst; +} + static void tcg_out_qemu_ld_indexed(TCGContext *s, MemOp opc, TCGType type, TCGReg rd, HostAddress h) { @@ -1057,29 +1036,17 @@ static void tcg_out_qemu_ld_indexed(TCGContext *s, = MemOp opc, TCGType type, static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - tcg_insn_unit *label_ptr[1]; + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, true); + tcg_out_qemu_ld_indexed(s, get_memop(oi), data_type, data_reg, h); =20 - tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1); - h.index =3D TCG_REG_TMP2; -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, true, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - h.index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; -#endif - - h.base =3D tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0); - tcg_out_qemu_ld_indexed(s, opc, data_type, data_reg, h); - -#ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#endif } =20 static void tcg_out_qemu_st_indexed(TCGContext *s, MemOp opc, @@ -1109,29 +1076,17 @@ static void tcg_out_qemu_st_indexed(TCGContext *s, = MemOp opc, static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - tcg_insn_unit *label_ptr[1]; + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, false); + tcg_out_qemu_st_indexed(s, get_memop(oi), data_reg, h); =20 - tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0); - h.index =3D TCG_REG_TMP2; -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, false, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - h.index =3D USE_GUEST_BASE ? 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There are several places where we already convert back from bool to type. Clean things up by using type throughout. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/mips/tcg-target.c.inc | 186 +++++++++++++++++++------------------- 1 file changed, 95 insertions(+), 91 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index a83ebe8729..ef8350e9cd 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1479,7 +1479,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) #endif /* SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, - TCGReg base, MemOp opc, bool is_64) + TCGReg base, MemOp opc, TCGType type) { switch (opc & (MO_SSIZE | MO_BSWAP)) { case MO_UB: @@ -1503,7 +1503,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, tcg_out_opc_imm(s, OPC_LH, lo, base, 0); break; case MO_UL | MO_BSWAP: - if (TCG_TARGET_REG_BITS =3D=3D 64 && is_64) { + if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64) { if (use_mips32r2_instructions) { tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); tcg_out_bswap32(s, lo, lo, TCG_BSWAP_IZ | TCG_BSWAP_OZ); @@ -1528,7 +1528,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, } break; case MO_UL: - if (TCG_TARGET_REG_BITS =3D=3D 64 && is_64) { + if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64) { tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); break; } @@ -1583,7 +1583,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, } =20 static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, - TCGReg base, MemOp opc, bool is_64) + TCGReg base, MemOp opc, TCGType type) { const MIPSInsn lw1 =3D MIPS_BE ? OPC_LWL : OPC_LWR; const MIPSInsn lw2 =3D MIPS_BE ? OPC_LWR : OPC_LWL; @@ -1623,7 +1623,7 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TC= GReg lo, TCGReg hi, case MO_UL: tcg_out_opc_imm(s, lw1, lo, base, 0); tcg_out_opc_imm(s, lw2, lo, base, 3); - if (TCG_TARGET_REG_BITS =3D=3D 64 && is_64 && !sgn) { + if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64 && != sgn) { tcg_out_ext32u(s, lo, lo); } break; @@ -1634,18 +1634,18 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, = TCGReg lo, TCGReg hi, tcg_out_opc_imm(s, lw1, lo, base, 0); tcg_out_opc_imm(s, lw2, lo, base, 3); tcg_out_bswap32(s, lo, lo, - TCG_TARGET_REG_BITS =3D=3D 64 && is_64 + TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D T= CG_TYPE_I64 ? (sgn ? TCG_BSWAP_OS : TCG_BSWAP_OZ) : 0); } else { const tcg_insn_unit *subr =3D - (TCG_TARGET_REG_BITS =3D=3D 64 && is_64 && !sgn + (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64= && !sgn ? bswap32u_addr : bswap32_addr); =20 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0); tcg_out_bswap_subr(s, subr); /* delay slot */ tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 3); - tcg_out_mov(s, is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, lo, TCG_TM= P3); + tcg_out_mov(s, type, lo, TCG_TMP3); } break; =20 @@ -1702,68 +1702,59 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, = TCGReg lo, TCGReg hi, } } =20 -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, TCGType data_type) { - TCGReg addr_regl, addr_regh __attribute__((unused)); - TCGReg data_regl, data_regh; - MemOpIdx oi; - MemOp opc; -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[2]; -#else -#endif - unsigned a_bits, s_bits; - TCGReg base =3D TCG_REG_A0; - - data_regl =3D *args++; - data_regh =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); - addr_regl =3D *args++; - addr_regh =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); - a_bits =3D get_alignment_bits(opc); - s_bits =3D opc & MO_SIZE; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned s_bits =3D opc & MO_SIZE; + TCGReg base; =20 /* * R6 removes the left/right instructions but requires the * system to support misaligned memory accesses. */ #if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1); + tcg_insn_unit *label_ptr[2]; + + base =3D TCG_REG_A0; + tcg_out_tlb_load(s, base, addrlo, addrhi, oi, label_ptr, 1); if (use_mips32r6_instructions || a_bits >=3D s_bits) { - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type); } else { - tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is_64); + tcg_out_qemu_ld_unalign(s, datalo, datahi, base, opc, data_type); } - add_qemu_ldst_label(s, 1, oi, - (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_regl, data_regh, addr_regl, addr_regh, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #else + base =3D addrlo; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addr_regl); - addr_regl =3D base; + tcg_out_ext32u(s, TCG_REG_A0, base); + base =3D TCG_REG_A0; } - if (guest_base =3D=3D 0 && data_regl !=3D addr_regl) { - base =3D addr_regl; - } else if (guest_base =3D=3D (int16_t)guest_base) { - tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); - } else { - tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl= ); + if (guest_base) { + if (guest_base =3D=3D (int16_t)guest_base) { + tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); + } else { + tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, + TCG_GUEST_BASE_REG); + } + base =3D TCG_REG_A0; } if (use_mips32r6_instructions) { if (a_bits) { - tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); + tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type); } else { if (a_bits && a_bits !=3D s_bits) { - tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); + tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } if (a_bits >=3D s_bits) { - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_= 64); + tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type= ); } else { - tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is= _64); + tcg_out_qemu_ld_unalign(s, datalo, datahi, base, opc, data_typ= e); } } #endif @@ -1902,67 +1893,60 @@ static void tcg_out_qemu_st_unalign(TCGContext *s, = TCGReg lo, TCGReg hi, g_assert_not_reached(); } } -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) -{ - TCGReg addr_regl, addr_regh __attribute__((unused)); - TCGReg data_regl, data_regh; - MemOpIdx oi; - MemOp opc; -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[2]; -#endif - unsigned a_bits, s_bits; - TCGReg base =3D TCG_REG_A0; =20 - data_regl =3D *args++; - data_regh =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); - addr_regl =3D *args++; - addr_regh =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); - a_bits =3D get_alignment_bits(opc); - s_bits =3D opc & MO_SIZE; +static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, TCGType data_type) +{ + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned s_bits =3D opc & MO_SIZE; + TCGReg base; =20 /* * R6 removes the left/right instructions but requires the * system to support misaligned memory accesses. */ #if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0); + tcg_insn_unit *label_ptr[2]; + + base =3D TCG_REG_A0; + tcg_out_tlb_load(s, base, addrlo, addrhi, oi, label_ptr, 0); if (use_mips32r6_instructions || a_bits >=3D s_bits) { - tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + tcg_out_qemu_st_direct(s, datalo, datahi, base, opc); } else { - tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc); + tcg_out_qemu_st_unalign(s, datalo, datahi, base, opc); } - add_qemu_ldst_label(s, 0, oi, - (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_regl, data_regh, addr_regl, addr_regh, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #else + base =3D addrlo; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addr_regl); - addr_regl =3D base; + tcg_out_ext32u(s, TCG_REG_A0, base); + base =3D TCG_REG_A0; } - if (guest_base =3D=3D 0) { - base =3D addr_regl; - } else if (guest_base =3D=3D (int16_t)guest_base) { - tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); - } else { - tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl= ); + if (guest_base) { + if (guest_base =3D=3D (int16_t)guest_base) { + tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); + } else { + tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, + TCG_GUEST_BASE_REG); + } + base =3D TCG_REG_A0; } if (use_mips32r6_instructions) { if (a_bits) { - tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); + tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } - tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + tcg_out_qemu_st_direct(s, datalo, datahi, base, opc); } else { if (a_bits && a_bits !=3D s_bits) { - tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); + tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } if (a_bits >=3D s_bits) { - tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + tcg_out_qemu_st_direct(s, datalo, datahi, base, opc); } else { - tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc); + tcg_out_qemu_st_unalign(s, datalo, datahi, base, opc); } } #endif @@ -2425,16 +2409,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, false); + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); + } else { + tcg_out_qemu_ld(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, true); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); + } else if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); + } break; case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, false); + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); + } else { + tcg_out_qemu_st(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, true); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); + } else if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); + } break; =20 case INDEX_op_add2_i32: --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 404 ++++++++++++++++---------------------- 1 file changed, 172 insertions(+), 232 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index ef8350e9cd..94708e6ea7 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1181,120 +1181,6 @@ static int tcg_out_call_iarg_reg2(TCGContext *s, in= t i, TCGReg al, TCGReg ah) return i; } =20 -/* We expect to use a 16-bit negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); - -/* - * Perform the tlb comparison operation. - * The complete host address is placed in BASE. - * Clobbers TMP0, TMP1, TMP2, TMP3. - */ -static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, - TCGReg addrh, MemOpIdx oi, - tcg_insn_unit *label_ptr[2], bool is_load) -{ - MemOp opc =3D get_memop(oi); - unsigned a_bits =3D get_alignment_bits(opc); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_mask =3D (1 << a_bits) - 1; - unsigned s_mask =3D (1 << s_bits) - 1; - int mem_index =3D get_mmuidx(oi); - int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); - int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); - int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); - int add_off =3D offsetof(CPUTLBEntry, addend); - int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - target_ulong tlb_mask; - - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); - - /* Extract the TLB index from the address into TMP3. */ - tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); - - /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3= . */ - tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); - - /* Load the (low-half) tlb comparator. */ - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); - } else { - tcg_out_ldst(s, (TARGET_LONG_BITS =3D=3D 64 ? OPC_LD - : TCG_TARGET_REG_BITS =3D=3D 64 ? OPC_LWU : OPC_L= W), - TCG_TMP0, TCG_TMP3, cmp_off); - } - - /* Zero extend a 32-bit guest address for a 64-bit host. */ - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addrl); - addrl =3D base; - } - - /* - * Mask the page bits, keeping the alignment bits to compare against. - * For unaligned accesses, compare against the end of the access to - * verify that it does not cross a page boundary. - */ - tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; - tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, tlb_mask); - if (a_mask >=3D s_mask) { - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); - } else { - tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP2, addrl, s_mask - a_mask); - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); - } - - if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { - /* Load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); - } - - label_ptr[0] =3D s->code_ptr; - tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); - - /* Load and test the high half tlb comparator. */ - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - /* delay slot */ - tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); - - /* Load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); - - label_ptr[1] =3D s->code_ptr; - tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0); - } - - /* delay slot */ - tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl); -} - -static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, - TCGType ext, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addrhi, - void *raddr, tcg_insn_unit *label_ptr[2]) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D ext; - label->datalo_reg =3D datalo; - label->datahi_reg =3D datahi; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr[0]; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - label->label_ptr[1] =3D label_ptr[1]; - } -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { const tcg_insn_unit *tgt_rx =3D tcg_splitwx_to_rx(s->code_ptr); @@ -1403,32 +1289,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) } =20 #else - -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrl= o, - TCGReg addrhi, unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *l =3D new_ldst_label(s); - - l->is_ld =3D is_ld; - l->addrlo_reg =3D addrlo; - l->addrhi_reg =3D addrhi; - - /* We are expecting a_bits to max out at 7, much lower than ANDI. */ - tcg_debug_assert(a_bits < 16); - tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask); - - l->label_ptr[0] =3D s->code_ptr; - if (use_mips32r6_instructions) { - tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); - } else { - tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); - tcg_out_nop(s); - } - - l->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { void *target; @@ -1478,6 +1338,154 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) } #endif /* SOFTMMU */ =20 +typedef struct { + TCGReg base; + MemOp align; +} HostAddress; + +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, bool is_ld) +{ + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned s_bits =3D opc & MO_SIZE; + unsigned a_mask =3D (1 << a_bits) - 1; + TCGReg base; + +#ifdef CONFIG_SOFTMMU + unsigned s_mask =3D (1 << s_bits) - 1; + int mem_index =3D get_mmuidx(oi); + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); + int add_off =3D offsetof(CPUTLBEntry, addend); + int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write); + target_ulong tlb_mask; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + base =3D TCG_REG_A0; + + /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); + + /* Extract the TLB index from the address into TMP3. */ + tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrlo, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); + + /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3= . */ + tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); + + /* Load the (low-half) tlb comparator. */ + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); + } else { + tcg_out_ldst(s, (TARGET_LONG_BITS =3D=3D 64 ? OPC_LD + : TCG_TARGET_REG_BITS =3D=3D 64 ? OPC_LWU : OPC_L= W), + TCG_TMP0, TCG_TMP3, cmp_off); + } + + /* Zero extend a 32-bit guest address for a 64-bit host. */ + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, base, addrlo); + addrlo =3D base; + } + + /* + * Mask the page bits, keeping the alignment bits to compare against. + * For unaligned accesses, compare against the end of the access to + * verify that it does not cross a page boundary. + */ + tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; + tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, tlb_mask); + if (a_mask >=3D s_mask) { + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo); + } else { + tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP2, addrlo, s_mask - a_mask); + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); + } + + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + /* Load the tlb addend for the fast path. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); + } + + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); + + /* Load and test the high half tlb comparator. */ + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + /* delay slot */ + tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); + + /* Load the tlb addend for the fast path. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); + + ldst->label_ptr[1] =3D s->code_ptr; + tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0); + } + + /* delay slot */ + tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrlo); +#else + if (a_mask && (use_mips32r6_instructions || a_bits !=3D s_bits)) { + ldst =3D new_ldst_label(s); + + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + /* We are expecting a_bits to max out at 7, much lower than ANDI. = */ + tcg_debug_assert(a_bits < 16); + tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask); + + ldst->label_ptr[0] =3D s->code_ptr; + if (use_mips32r6_instructions) { + tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); + } else { + tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); + tcg_out_nop(s); + } + } + + base =3D addrlo; + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_A0, base); + base =3D TCG_REG_A0; + } + if (guest_base) { + if (guest_base =3D=3D (int16_t)guest_base) { + tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); + } else { + tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, + TCG_GUEST_BASE_REG); + } + base =3D TCG_REG_A0; + } +#endif + + h->base =3D base; + h->align =3D a_bits; + return ldst; +} + static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, TCGReg base, MemOp opc, TCGType type) { @@ -1707,57 +1715,23 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); - unsigned a_bits =3D get_alignment_bits(opc); - unsigned s_bits =3D opc & MO_SIZE; - TCGReg base; + TCGLabelQemuLdst *ldst; + HostAddress h; =20 - /* - * R6 removes the left/right instructions but requires the - * system to support misaligned memory accesses. - */ -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[2]; + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, true); =20 - base =3D TCG_REG_A0; - tcg_out_tlb_load(s, base, addrlo, addrhi, oi, label_ptr, 1); - if (use_mips32r6_instructions || a_bits >=3D s_bits) { - tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type); + if (use_mips32r6_instructions || h.align >=3D (opc & MO_SIZE)) { + tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); } else { - tcg_out_qemu_ld_unalign(s, datalo, datahi, base, opc, data_type); + tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type); } - add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#else - base =3D addrlo; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_A0, base); - base =3D TCG_REG_A0; + + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - if (guest_base) { - if (guest_base =3D=3D (int16_t)guest_base) { - tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); - } else { - tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, - TCG_GUEST_BASE_REG); - } - base =3D TCG_REG_A0; - } - if (use_mips32r6_instructions) { - if (a_bits) { - tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); - } - tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type); - } else { - if (a_bits && a_bits !=3D s_bits) { - tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); - } - if (a_bits >=3D s_bits) { - tcg_out_qemu_ld_direct(s, datalo, datahi, base, opc, data_type= ); - } else { - tcg_out_qemu_ld_unalign(s, datalo, datahi, base, opc, data_typ= e); - } - } -#endif } =20 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, @@ -1899,57 +1873,23 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); - unsigned a_bits =3D get_alignment_bits(opc); - unsigned s_bits =3D opc & MO_SIZE; - TCGReg base; + TCGLabelQemuLdst *ldst; + HostAddress h; =20 - /* - * R6 removes the left/right instructions but requires the - * system to support misaligned memory accesses. - */ -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[2]; + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, false); =20 - base =3D TCG_REG_A0; - tcg_out_tlb_load(s, base, addrlo, addrhi, oi, label_ptr, 0); - if (use_mips32r6_instructions || a_bits >=3D s_bits) { - tcg_out_qemu_st_direct(s, datalo, datahi, base, opc); + if (use_mips32r6_instructions || h.align >=3D (opc & MO_SIZE)) { + tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); } else { - tcg_out_qemu_st_unalign(s, datalo, datahi, base, opc); + tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); } - add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#else - base =3D addrlo; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_A0, base); - base =3D TCG_REG_A0; + + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - if (guest_base) { - if (guest_base =3D=3D (int16_t)guest_base) { - tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); - } else { - tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, - TCG_GUEST_BASE_REG); - } - base =3D TCG_REG_A0; - } - if (use_mips32r6_instructions) { - if (a_bits) { - tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); - } - tcg_out_qemu_st_direct(s, datalo, datahi, base, opc); - } else { - if (a_bits && a_bits !=3D s_bits) { - tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); - } - if (a_bits >=3D s_bits) { - tcg_out_qemu_st_direct(s, datalo, datahi, base, opc); - } else { - tcg_out_qemu_st_unalign(s, datalo, datahi, base, opc); - } - } -#endif } =20 static void tcg_out_mb(TCGContext *s, TCGArg a0) --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315528; 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[46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314879; x=1684906879; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KyKsoDmohPBZSp4W8unRK+Qo86bIZbr6mB+lGKIr14Y=; b=ZkPIe1wovs4N8UWsZQ0RO5snYb05/CoMB5vFLXUFytyTRadSObkl3zOfylCRBvwTGg S1pG7Ok8WPs8lBg8mNmFmtj9iJ8DSztrtec45TMZqxh95mLTenhG52Q0nOLt4ZpR71vR 9bFkRbzlN5cwUPJb/F/zG/2s+Esr8vUSr1gJZo7/cOP+vuG8u7yv88zxU3XVHafvSnfi LTq5Yh2Ad0bFeCtpAFWXFl9FCx8JcDgF8jS1EkqFR03K9LEw8b+UXoZaQ7wwUWfgs6DU jPDGnfMgI1JrOHPgxOaDcCLRDuqBifhdB1hsVhEgGJH/7g3LKAK12op9LUODbp3W1Fp4 yhjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314879; x=1684906879; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KyKsoDmohPBZSp4W8unRK+Qo86bIZbr6mB+lGKIr14Y=; b=KRyhELJBtKQCLntgPZLAA9O6OHqW46SGouHsnFNlLWwTODqZEONcywgI67InlTP4K5 UIoe0v/sUBjdYQ8RYDnAqdbBzyTxb5t1Pn7KDeSULCABrG0z/RJikxeIfpf0mMkMaptx T+MjNDDVcXuawSPts8npKoAQLlamkYQTYVext39Mw1FaBgbquANlFCxq1Tjz6zr+c8Kl Q08Lzvd0gE3WIGKJ6MFn6yEkPNMBQomTY9sxNtMSNfCjNsnmnmbo+/d2aheSVM1uI3qR 2WW1s0SZ6FAlgShJO7Y3BZYPoAWqB1k1paWliREDtmEyZT51EiDD2hwDlC6IhAKHpe1B EiCw== X-Gm-Message-State: AAQBX9fNzCenoOsVYaNuL7a8+4fVkYVAUIsS6vcnVoCRV3XFevlHPhku 4CFStksBxN/9raGp0rt/MVLHniHsTMR6bdClRSiItQ== X-Google-Smtp-Source: AKy350Ym3IGd+b4GwL1cIXmNiuaGdJ3p6ncr1SHsAb87dRpVtbt9CfMvwWTgSrA2M0Y8KsROlXSU1w== X-Received: by 2002:a5d:4882:0:b0:2ef:b8d1:9560 with SMTP id g2-20020a5d4882000000b002efb8d19560mr9186824wrq.30.1682314879440; Sun, 23 Apr 2023 22:41:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Daniel Henrique Barboza Subject: [PATCH v3 23/57] tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st} Date: Mon, 24 Apr 2023 06:40:31 +0100 Message-Id: <20230424054105.1579315-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315531146100003 Interpret the variable argument placement in the caller. Pass data_type instead of is64 -- there are several places where we already convert back from bool to type. Clean things up by using type throughout. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 110 +++++++++++++++++++++------------------ 1 file changed, 59 insertions(+), 51 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 77abb7d20c..d1aa2a9f53 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2118,7 +2118,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp o= pc, /* Record the context of a call to the out of line helper code for the slow path for a load or store, so that we can later generate the correct helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, + TCGType type, MemOpIdx oi, TCGReg datalo_reg, TCGReg datahi_reg, TCGReg addrlo_reg, TCGReg addrhi_reg, tcg_insn_unit *raddr, tcg_insn_unit *lptr) @@ -2126,6 +2127,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, MemOpIdx oi, TCGLabelQemuLdst *label =3D new_ldst_label(s); =20 label->is_ld =3D is_ld; + label->type =3D type; label->oi =3D oi; label->datalo_reg =3D datalo_reg; label->datahi_reg =3D datahi_reg; @@ -2288,30 +2290,18 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) =20 #endif /* SOFTMMU */ =20 -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, TCGType data_type) { - TCGReg datalo, datahi, addrlo, rbase; - TCGReg addrhi __attribute__((unused)); - MemOpIdx oi; - MemOp opc, s_bits; + MemOp opc =3D get_memop(oi); + MemOp s_bits =3D opc & MO_SIZE; + TCGReg rbase; + #ifdef CONFIG_SOFTMMU - int mem_index; tcg_insn_unit *label_ptr; -#else - unsigned a_bits; -#endif =20 - datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); - s_bits =3D opc & MO_SIZE; - -#ifdef CONFIG_SOFTMMU - mem_index =3D get_mmuidx(oi); - addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true); + addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), tr= ue); =20 /* Load a pointer into the current opcode w/conditional branch-link. */ label_ptr =3D s->code_ptr; @@ -2319,7 +2309,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) =20 rbase =3D TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } @@ -2364,35 +2354,23 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is_64) } =20 #ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #endif } =20 -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, TCGType data_type) { - TCGReg datalo, datahi, addrlo, rbase; - TCGReg addrhi __attribute__((unused)); - MemOpIdx oi; - MemOp opc, s_bits; + MemOp opc =3D get_memop(oi); + MemOp s_bits =3D opc & MO_SIZE; + TCGReg rbase; + #ifdef CONFIG_SOFTMMU - int mem_index; tcg_insn_unit *label_ptr; -#else - unsigned a_bits; -#endif =20 - datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); - s_bits =3D opc & MO_SIZE; - -#ifdef CONFIG_SOFTMMU - mem_index =3D get_mmuidx(oi); - addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false); + addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), fa= lse); =20 /* Load a pointer into the current opcode w/conditional branch-link. */ label_ptr =3D s->code_ptr; @@ -2400,7 +2378,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) =20 rbase =3D TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); } @@ -2437,8 +2415,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) } =20 #ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #endif } =20 @@ -2972,16 +2950,46 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, false); + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_qemu_ld(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I32); + } else { + tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], + args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, true); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_ld(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I64); + } else if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_ld(s, args[0], args[1], args[2], -1, + args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], + args[4], TCG_TYPE_I64); + } break; case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, false); + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_qemu_st(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I32); + } else { + tcg_out_qemu_st(s, args[0], -1, args[1], args[2], + args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, true); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_st(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I64); + } else if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_st(s, args[0], args[1], args[2], -1, + args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], + args[4], TCG_TYPE_I64); + } break; =20 case INDEX_op_setcond_i32: --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314880; x=1684906880; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=z4Mzsk+fdTdRzO55PgLGhFQu8iRIHSF0DlOUqjWQl44=; b=hmxM+fRHFwdj9LtEJ53wM0yG0Yi5V6s4w2ts/PIjVVF3UQIsDxEHylRwLvG+mZ71m0 jy5rpxYkizKfFz+1P9egnjW6C+UVNpZWODOCZstQMS0l31t1zuYmpZA/3PwFWySrAIjr BsgAcVTicz1T+ChqxyH/LNlcsmrOu+tXF2e23kEMC8d9yt2WM5EeYdJUpA0eSbixu7Ax bSFhT+BGsuyTIvdV9mL2TsvvhGZJjv8gljIb4bMJVv8aS163Emy+g1Pla5wCprpXdz7U ZOpeigJgLWlmm8qMcRqvHcCAKoMx98RYsC8mJkMFs9dJT+V01qraxy3OZG24J0i9hQCl Jbnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314880; x=1684906880; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z4Mzsk+fdTdRzO55PgLGhFQu8iRIHSF0DlOUqjWQl44=; b=DTAHj9usWLHUW7hlq8G5eKzNbFttD5YmDKCC8g1eFq1LXwTpjwGbagMgav+ESrD/NI DsVYuywOM0dp+gNNCkaHChfKSyuFucY0OTLnnPQb+NOPxl/Px4i309kjutWUiePR7Vrj 9LPbQ1BBwtCbQ/v3U4O/u6zSOR25V1eAR5/ruqqPeJ6KVwouvysNIRcCba4QR1cg2spD KOa1167lcr3BDLrydn2Llp1fSxOlvKNs7Xahmz4BM1iMuWBuz8ySGBzDOSZxjXlWsp1j uK5XeRklQde7g8aLNYXhfhQ8ZAo5RdxbtaNPyTA6SQA/lajYgAAB7PfcDwXyjjaol2Ke 8mUg== X-Gm-Message-State: AAQBX9d3eM/hPBq5vz6i+qlGDdqlF7bmRI//84Q17lE/RZb76p/eTg7D /ZEhnce9lEKGedGO1XnmP2UkLJCEew0jTOd5jK5/LA== X-Google-Smtp-Source: AKy350ZpQrfhnf7TjmYJJJfB2EH3TukmqtYb1VC+oZa+a1ZOkgH/cyqiV6ONiJ7mFJo/4cMPFV7zvg== X-Received: by 2002:a7b:cd96:0:b0:3f1:8338:4b8c with SMTP id y22-20020a7bcd96000000b003f183384b8cmr6893866wmj.1.1682314880009; Sun, 23 Apr 2023 22:41:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 24/57] tcg/ppc: Introduce HostAddress Date: Mon, 24 Apr 2023 06:40:32 +0100 Message-Id: <20230424054105.1579315-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315937450100003 Content-Type: text/plain; charset="utf-8" Collect the parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st} to use it. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/ppc/tcg-target.c.inc | 90 +++++++++++++++++++++------------------- 1 file changed, 47 insertions(+), 43 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index d1aa2a9f53..cd473deb36 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2287,67 +2287,71 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) { return tcg_out_fail_alignment(s, l); } - #endif /* SOFTMMU */ =20 +typedef struct { + TCGReg base; + TCGReg index; +} HostAddress; + static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); MemOp s_bits =3D opc & MO_SIZE; - TCGReg rbase; + HostAddress h; =20 #ifdef CONFIG_SOFTMMU tcg_insn_unit *label_ptr; =20 - addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), tr= ue); + h.index =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), t= rue); + h.base =3D TCG_REG_R3; =20 /* Load a pointer into the current opcode w/conditional branch-link. */ label_ptr =3D s->code_ptr; tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); - - rbase =3D TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } - rbase =3D guest_base ? TCG_GUEST_BASE_REG : 0; + h.base =3D guest_base ? TCG_GUEST_BASE_REG : 0; + h.index =3D addrlo; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); - addrlo =3D TCG_REG_TMP1; + h.index =3D TCG_REG_TMP1; } #endif =20 if (TCG_TARGET_REG_BITS =3D=3D 32 && s_bits =3D=3D MO_64) { if (opc & MO_BSWAP) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); - tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo)); - tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0)); - } else if (rbase !=3D 0) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); - tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo)); - tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0)); - } else if (addrlo =3D=3D datahi) { - tcg_out32(s, LWZ | TAI(datalo, addrlo, 4)); - tcg_out32(s, LWZ | TAI(datahi, addrlo, 0)); + tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); + tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); + tcg_out32(s, LWBRX | TAB(datahi, h.base, TCG_REG_R0)); + } else if (h.base !=3D 0) { + tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); + tcg_out32(s, LWZX | TAB(datahi, h.base, h.index)); + tcg_out32(s, LWZX | TAB(datalo, h.base, TCG_REG_R0)); + } else if (h.index =3D=3D datahi) { + tcg_out32(s, LWZ | TAI(datalo, h.index, 4)); + tcg_out32(s, LWZ | TAI(datahi, h.index, 0)); } else { - tcg_out32(s, LWZ | TAI(datahi, addrlo, 0)); - tcg_out32(s, LWZ | TAI(datalo, addrlo, 4)); + tcg_out32(s, LWZ | TAI(datahi, h.index, 0)); + tcg_out32(s, LWZ | TAI(datalo, h.index, 4)); } } else { uint32_t insn =3D qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)]; if (!have_isa_2_06 && insn =3D=3D LDBRX) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); - tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo)); - tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0)); + tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); + tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); + tcg_out32(s, LWBRX | TAB(TCG_REG_R0, h.base, TCG_REG_R0)); tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0); } else if (insn) { - tcg_out32(s, insn | TAB(datalo, rbase, addrlo)); + tcg_out32(s, insn | TAB(datalo, h.base, h.index)); } else { insn =3D qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)]; - tcg_out32(s, insn | TAB(datalo, rbase, addrlo)); + tcg_out32(s, insn | TAB(datalo, h.base, h.index)); tcg_out_movext(s, TCG_TYPE_REG, datalo, TCG_TYPE_REG, opc & MO_SSIZE, datalo); } @@ -2365,52 +2369,52 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, { MemOp opc =3D get_memop(oi); MemOp s_bits =3D opc & MO_SIZE; - TCGReg rbase; + HostAddress h; =20 #ifdef CONFIG_SOFTMMU tcg_insn_unit *label_ptr; =20 - addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), fa= lse); + h.index =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), f= alse); + h.base =3D TCG_REG_R3; =20 /* Load a pointer into the current opcode w/conditional branch-link. */ label_ptr =3D s->code_ptr; tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); - - rbase =3D TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); } - rbase =3D guest_base ? TCG_GUEST_BASE_REG : 0; + h.base =3D guest_base ? TCG_GUEST_BASE_REG : 0; + h.index =3D addrlo; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); - addrlo =3D TCG_REG_TMP1; + h.index =3D TCG_REG_TMP1; } #endif =20 if (TCG_TARGET_REG_BITS =3D=3D 32 && s_bits =3D=3D MO_64) { if (opc & MO_BSWAP) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); - tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo)); - tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0)); - } else if (rbase !=3D 0) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); - tcg_out32(s, STWX | SAB(datahi, rbase, addrlo)); - tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0)); + tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); + tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); + tcg_out32(s, STWBRX | SAB(datahi, h.base, TCG_REG_R0)); + } else if (h.base !=3D 0) { + tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); + tcg_out32(s, STWX | SAB(datahi, h.base, h.index)); + tcg_out32(s, STWX | SAB(datalo, h.base, TCG_REG_R0)); } else { - tcg_out32(s, STW | TAI(datahi, addrlo, 0)); - tcg_out32(s, STW | TAI(datalo, addrlo, 4)); + tcg_out32(s, STW | TAI(datahi, h.index, 0)); + tcg_out32(s, STW | TAI(datalo, h.index, 4)); } } else { uint32_t insn =3D qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)]; if (!have_isa_2_06 && insn =3D=3D STDBRX) { - tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo)); - tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4)); + tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); + tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, h.index, 4)); tcg_out_shri64(s, TCG_REG_R0, datalo, 32); - tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1)); + tcg_out32(s, STWBRX | SAB(TCG_REG_R0, h.base, TCG_REG_TMP1)); } else { - tcg_out32(s, insn | SAB(datalo, rbase, addrlo)); + tcg_out32(s, insn | SAB(datalo, h.base, h.index)); } } =20 --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315419; cv=none; d=zohomail.com; s=zohoarc; b=hpCb3JB2Q9DDpRvdtOZniLgxBOg8rykjYvuaem/U/kv7U/FQ4xWSXN0CBeKTKlx1yGPR654Q3x6IoS2/szIDxxc3yWDCOK6KMUjR2ND5nFScwR9xFos3LdHwzrPGlOoIRqK9DjqfTP7YL0HGmx1fX9zaUC2ddpf3Z3SlM3LP3Io= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315419; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=E8LkZay/KDgOZOAPr4+3iyW8Oh14XA3T4+Op1DdY80A=; b=M+4CBg2nknZaUFspJHF9jD8wdiHQP8rTpXoC1TpHwNzmNZaYu2OpdbWKyyFFKVFSXZmm/w3ChqJshN23/4P+uoeA4gg01jdcMyNRxxQyIbc9cIeSXxn2CN1TqWN+x3SyMYdegdGZz5ObfcV/wwIBh3vwY62SSrB0ZFGojrhZdug= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315419586606.7582222954461; Sun, 23 Apr 2023 22:50:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqoz3-0000Mz-QP; Mon, 24 Apr 2023 01:43:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqoxi-0005oT-KQ for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:42:07 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqox0-0004Or-0S for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:42:06 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-2f4214b430aso2317630f8f.0 for ; Sun, 23 Apr 2023 22:41:21 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. 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Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 377 +++++++++++++++++---------------------- 1 file changed, 168 insertions(+), 209 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index cd473deb36..7239335bdf 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2003,140 +2003,6 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_B= SWAP) + 1] =3D { [MO_BEUQ] =3D helper_be_stq_mmu, }; =20 -/* We expect to use a 16-bit negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); - -/* Perform the TLB load and compare. Places the result of the comparison - in CR7, loads the addend of the TLB into R3, and returns the register - containing the guest address (zero-extended into R4). Clobbers R0 and = R2. */ - -static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc, - TCGReg addrlo, TCGReg addrhi, - int mem_index, bool is_read) -{ - int cmp_off - =3D (is_read - ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); - int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); - int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_bits =3D get_alignment_bits(opc); - - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off); - - /* Extract the page index, shifted into place for tlb index. */ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_shri32(s, TCG_REG_TMP1, addrlo, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - } else { - tcg_out_shri64(s, TCG_REG_TMP1, addrlo, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - } - tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1)); - - /* Load the TLB comparator. */ - if (cmp_off =3D=3D 0 && TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { - uint32_t lxu =3D (TCG_TARGET_REG_BITS =3D=3D 32 || TARGET_LONG_BIT= S =3D=3D 32 - ? LWZUX : LDUX); - tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4)); - } else { - tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4)); - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off = + 4); - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off); - } else { - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off); - } - } - - /* Load the TLB addend for use on the fast path. Do this asap - to minimize any load use delay. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, - offsetof(CPUTLBEntry, addend)); - - /* Clear the non-page, non-alignment bits from the address */ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - /* We don't support unaligned accesses on 32-bits. - * Preserve the bottom bits and thus trigger a comparison - * failure on unaligned accesses. - */ - if (a_bits < s_bits) { - a_bits =3D s_bits; - } - tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0, - (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); - } else { - TCGReg t =3D addrlo; - - /* If the access is unaligned, we need to make sure we fail if we - * cross a page boundary. The trick is to add the access size-1 - * to the address before masking the low bits. That will make the - * address overflow to the next page if we cross a page boundary, - * which will then force a mismatch of the TLB compare. - */ - if (a_bits < s_bits) { - unsigned a_mask =3D (1 << a_bits) - 1; - unsigned s_mask =3D (1 << s_bits) - 1; - tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask)); - t =3D TCG_REG_R0; - } - - /* Mask the address for the requested alignment. */ - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, - (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); - /* Zero-extend the address for use in the final address. */ - tcg_out_ext32u(s, TCG_REG_R4, addrlo); - addrlo =3D TCG_REG_R4; - } else if (a_bits =3D=3D 0) { - tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS= ); - } else { - tcg_out_rld(s, RLDICL, TCG_REG_R0, t, - 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits); - tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BIT= S, 0); - } - } - - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, - 0, 7, TCG_TYPE_I32); - tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32= ); - tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); - } else { - tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, - 0, 7, TCG_TYPE_TL); - } - - return addrlo; -} - -/* Record the context of a call to the out of line helper code for the slow - path for a load or store, so that we can later generate the correct - helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, - TCGType type, MemOpIdx oi, - TCGReg datalo_reg, TCGReg datahi_reg, - TCGReg addrlo_reg, TCGReg addrhi_reg, - tcg_insn_unit *raddr, tcg_insn_unit *lptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->type =3D type; - label->oi =3D oi; - label->datalo_reg =3D datalo_reg; - label->datahi_reg =3D datahi_reg; - label->addrlo_reg =3D addrlo_reg; - label->addrhi_reg =3D addrhi_reg; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D lptr; -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { MemOpIdx oi =3D lb->oi; @@ -2225,27 +2091,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) return true; } #else - -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrl= o, - TCGReg addrhi, unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; - - /* We are expecting a_bits to max out at 7, much lower than ANDI. */ - tcg_debug_assert(a_bits < 16); - tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, a_mask)); - - label->label_ptr[0] =3D s->code_ptr; - tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK); - - label->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { if (!reloc_pc14(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -2294,37 +2139,167 @@ typedef struct { TCGReg index; } HostAddress; =20 +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addrlo, TCGReg addrhi, + MemOpIdx oi, bool is_ld) +{ + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + +#ifdef CONFIG_SOFTMMU + int mem_index =3D get_mmuidx(oi); + int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write); + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); + unsigned s_bits =3D opc & MO_SIZE; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off); + + /* Extract the page index, shifted into place for tlb index. */ + if (TCG_TARGET_REG_BITS =3D=3D 32) { + tcg_out_shri32(s, TCG_REG_TMP1, addrlo, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + } else { + tcg_out_shri64(s, TCG_REG_TMP1, addrlo, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + } + tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1)); + + /* Load the TLB comparator. */ + if (cmp_off =3D=3D 0 && TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + uint32_t lxu =3D (TCG_TARGET_REG_BITS =3D=3D 32 || TARGET_LONG_BIT= S =3D=3D 32 + ? LWZUX : LDUX); + tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4)); + } else { + tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4)); + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off = + 4); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off); + } else { + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off); + } + } + + /* Load the TLB addend for use on the fast path. Do this asap + to minimize any load use delay. */ + h->base =3D TCG_REG_R3; + tcg_out_ld(s, TCG_TYPE_PTR, h->base, TCG_REG_R3, + offsetof(CPUTLBEntry, addend)); + + /* Clear the non-page, non-alignment bits from the address */ + if (TCG_TARGET_REG_BITS =3D=3D 32) { + /* We don't support unaligned accesses on 32-bits. + * Preserve the bottom bits and thus trigger a comparison + * failure on unaligned accesses. + */ + if (a_bits < s_bits) { + a_bits =3D s_bits; + } + tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0, + (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); + } else { + TCGReg t =3D addrlo; + + /* If the access is unaligned, we need to make sure we fail if we + * cross a page boundary. The trick is to add the access size-1 + * to the address before masking the low bits. That will make the + * address overflow to the next page if we cross a page boundary, + * which will then force a mismatch of the TLB compare. + */ + if (a_bits < s_bits) { + unsigned a_mask =3D (1 << a_bits) - 1; + unsigned s_mask =3D (1 << s_bits) - 1; + tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask)); + t =3D TCG_REG_R0; + } + + /* Mask the address for the requested alignment. */ + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, + (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); + /* Zero-extend the address for use in the final address. */ + tcg_out_ext32u(s, TCG_REG_R4, addrlo); + addrlo =3D TCG_REG_R4; + } else if (a_bits =3D=3D 0) { + tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS= ); + } else { + tcg_out_rld(s, RLDICL, TCG_REG_R0, t, + 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits); + tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BIT= S, 0); + } + } + h->index =3D addrlo; + + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, + 0, 7, TCG_TYPE_I32); + tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32= ); + tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); + } else { + tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, + 0, 7, TCG_TYPE_TL); + } + + /* Load a pointer into the current opcode w/conditional branch-link. */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); +#else + if (a_bits) { + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + /* We are expecting a_bits to max out at 7, much lower than ANDI. = */ + tcg_debug_assert(a_bits < 16); + tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, (1 << a_bits) - 1)); + + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK); + } + + h->base =3D guest_base ? TCG_GUEST_BASE_REG : 0; + h->index =3D addrlo; + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); + h->index =3D TCG_REG_TMP1; + } +#endif + + return ldst; +} + static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - tcg_insn_unit *label_ptr; + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, true); =20 - h.index =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), t= rue); - h.base =3D TCG_REG_R3; - - /* Load a pointer into the current opcode w/conditional branch-link. */ - label_ptr =3D s->code_ptr; - tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); -#else /* !CONFIG_SOFTMMU */ - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); - } - h.base =3D guest_base ? TCG_GUEST_BASE_REG : 0; - h.index =3D addrlo; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); - h.index =3D TCG_REG_TMP1; - } -#endif - - if (TCG_TARGET_REG_BITS =3D=3D 32 && s_bits =3D=3D MO_64) { + if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { if (opc & MO_BSWAP) { tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); @@ -2357,10 +2332,12 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, } } =20 -#ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#endif + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); + } } =20 static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, @@ -2368,32 +2345,12 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - tcg_insn_unit *label_ptr; + ldst =3D prepare_host_addr(s, &h, addrlo, addrhi, oi, false); =20 - h.index =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), f= alse); - h.base =3D TCG_REG_R3; - - /* Load a pointer into the current opcode w/conditional branch-link. */ - label_ptr =3D s->code_ptr; - tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); -#else /* !CONFIG_SOFTMMU */ - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); - } - h.base =3D guest_base ? TCG_GUEST_BASE_REG : 0; - h.index =3D addrlo; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); - h.index =3D TCG_REG_TMP1; - } -#endif - - if (TCG_TARGET_REG_BITS =3D=3D 32 && s_bits =3D=3D MO_64) { + if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { if (opc & MO_BSWAP) { tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); @@ -2418,10 +2375,12 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= atalo, TCGReg datahi, } } =20 -#ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi, - addrlo, addrhi, s->code_ptr, label_ptr); -#endif + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D datalo; + ldst->datahi_reg =3D datahi; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); + } } =20 static void tcg_out_nop_fill(tcg_insn_unit *p, int count) --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315780; cv=none; d=zohomail.com; s=zohoarc; b=jsq7qji8KW8FKsQSeiji4SiyeaBgsF6UeH0Aoi0ZuTJATkcQZChCvf3DBSWWGDHCeiztuIsrqIe8hEw+qI1jhZvO4TXRXzDa9SSl+Uu8svs+T5VEjftUlKKngzqxbAEF32Tcwa8jUBo8GdOxbyxhU6007I/BbYMSonshIJKy0JI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315780; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zK0ATTFS6tlkNM6OyhSTkXFnSXwh6GyYuYj0b65bkXQ=; b=VJNJ4jl0OOBED4jl0kvetsK4RU2IHQ8/dMYLE24lxefQK8x5GSGoU7VIpHctLKu5KSbK7snWvL+jYeIm64k8nzXM2xQ3WvvZsip65J44szoZjOiMa8fG0B2gt3VcF2xm4YzgdSNd7nBfkXKTKsfp0hEsGfuCo1UYjKwIn+lQki0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315780588374.32795131783496; Sun, 23 Apr 2023 22:56:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqozb-0002AS-Ii; Mon, 24 Apr 2023 01:44:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqoxj-0005pT-7w for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:42:07 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqox0-0004PV-RI for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:42:06 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-3f1728c2a57so41144525e9.0 for ; Sun, 23 Apr 2023 22:41:22 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314881; x=1684906881; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zK0ATTFS6tlkNM6OyhSTkXFnSXwh6GyYuYj0b65bkXQ=; b=SjtCnYX/aO9PrR/METngosh7TuTcRzPErIVU4VGfS4TKfvZlCxKxXkQt0uKz4DKlhR bH7JADOJWe9yJkDBX9BuKzVMynsgm+cWgwZdwnVuaj5gVGQjJleYb9QJJ9Y6U1VvSTz2 YUBC97R6GR2T76o3Qi1cKs0CLmYyy78IG5BUfjI+hcDUTX5275Nfj1UBid1DIhiQIpG7 SmPE+u8akJ81xPJ0m541giYIMpnoSH5F2FpfdJjxF9gPo85tcf9gdrB5i5yuLmtsMBnh s0Vj/fPcHXqxXWg4Jx2MOJsu+9SM6DuC9v22CRJtpntdITfik1Vl3IQeXpPfFoZKvF2N fEQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314881; x=1684906881; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zK0ATTFS6tlkNM6OyhSTkXFnSXwh6GyYuYj0b65bkXQ=; b=YDY/lNNlDfVxhP/lK6DA3tmAhM4ycapkjsVmqLitmL18J0NQVjGGB2+5lbmsEiuebV QspCKajtL+Ht2LXiULxziykkNBnVq2GuxBb9MtgbRUH45xszqbJtPSqB2cUcCgtIXo3a S5pFL9i6obQ4++QiRgjCFH4jtMQoTSZWbXm9ZGX6jlVeqLDsEiDhfbdN6/szFfDNGkVL u2JshjU3eJlsBUgEQxWUjFAWcPgY9DQR5FQYR8JzRp55sDE0pTaAQblpvhoWO+yMbpCi HJvueRfG/clgvGx9SxRnB92FsWzReqVjmrfm1mLedrb1XmMGOGeCId8HdJWh/2JLride f0NQ== X-Gm-Message-State: AAQBX9fJPV1vC64XPqy5xRnJq4GpX9/YVUR3NLBPmWK5Ch6CKlZohVmW uL5LF+rb1/NxZ141/EVxMtaZRaGpAOUf8UxaZDK+Bg== X-Google-Smtp-Source: AKy350bc4DqETPU5Vf/oWJdhBUOKF2u1X5R5TPM6FMZCKmINV3Bhx0l1lxAE+qvJHIwZpbBtHProNw== X-Received: by 2002:a1c:6a19:0:b0:3f1:929f:60db with SMTP id f25-20020a1c6a19000000b003f1929f60dbmr6138365wmc.39.1682314881447; Sun, 23 Apr 2023 22:41:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Daniel Henrique Barboza Subject: [PATCH v3 26/57] tcg/riscv: Require TCG_TARGET_REG_BITS == 64 Date: Mon, 24 Apr 2023 06:40:34 +0100 Message-Id: <20230424054105.1579315-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315782304100003 The port currently does not support "oversize" guests, which means riscv32 can only target 32-bit guests. We will soon be building TCG once for all guests. This implies that we can only support riscv64. Since all Linux distributions target riscv64 not riscv32, this is not much of a restriction and simplifies the code. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 6 - tcg/riscv/tcg-target.h | 22 ++-- tcg/riscv/tcg-target.c.inc | 206 ++++++++++----------------------- 3 files changed, 72 insertions(+), 162 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index cf0ac4d751..c11710d117 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -13,18 +13,12 @@ C_O0_I1(r) C_O0_I2(LZ, L) C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) -C_O0_I3(LZ, L, L) -C_O0_I3(LZ, LZ, L) -C_O0_I4(LZ, LZ, L, L) C_O0_I4(rZ, rZ, rZ, rZ) C_O1_I1(r, L) C_O1_I1(r, r) -C_O1_I2(r, L, L) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) C_O1_I2(r, rZ, rN) C_O1_I2(r, rZ, rZ) C_O1_I4(r, rZ, rZ, rZ, rZ) -C_O2_I1(r, r, L) -C_O2_I2(r, r, L, L) C_O2_I4(r, r, rZ, rZ, rM, rM) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 0deb33701f..dddf2486c1 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -25,11 +25,14 @@ #ifndef RISCV_TCG_TARGET_H #define RISCV_TCG_TARGET_H =20 -#if __riscv_xlen =3D=3D 32 -# define TCG_TARGET_REG_BITS 32 -#elif __riscv_xlen =3D=3D 64 -# define TCG_TARGET_REG_BITS 64 +/* + * We don't support oversize guests. + * Since we will only build tcg once, this in turn requires a 64-bit host. + */ +#if __riscv_xlen !=3D 64 +#error "unsupported code generation mode" #endif +#define TCG_TARGET_REG_BITS 64 =20 #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 20 @@ -83,13 +86,8 @@ typedef enum { #define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL -#if TCG_TARGET_REG_BITS =3D=3D 32 -#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN -#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN -#else #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL -#endif #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 /* optional instructions */ @@ -106,8 +104,8 @@ typedef enum { #define TCG_TARGET_HAS_sub2_i32 1 #define TCG_TARGET_HAS_mulu2_i32 0 #define TCG_TARGET_HAS_muls2_i32 0 -#define TCG_TARGET_HAS_muluh_i32 (TCG_TARGET_REG_BITS =3D=3D 32) -#define TCG_TARGET_HAS_mulsh_i32 (TCG_TARGET_REG_BITS =3D=3D 32) +#define TCG_TARGET_HAS_muluh_i32 0 +#define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_ext8s_i32 1 #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 1 @@ -128,7 +126,6 @@ typedef enum { #define TCG_TARGET_HAS_setcond2 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 #define TCG_TARGET_HAS_movcond_i64 0 #define TCG_TARGET_HAS_div_i64 1 #define TCG_TARGET_HAS_rem_i64 1 @@ -165,7 +162,6 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 -#endif =20 #define TCG_TARGET_DEFAULT_MO (0) =20 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 266fe1433d..1edc3b1c4d 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -137,15 +137,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKi= nd kind, int slot) #define SOFTMMU_RESERVE_REGS 0 #endif =20 - -static inline tcg_target_long sextreg(tcg_target_long val, int pos, int le= n) -{ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - return sextract32(val, pos, len); - } else { - return sextract64(val, pos, len); - } -} +#define sextreg sextract64 =20 /* test if a constant matches the constraint */ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) @@ -235,7 +227,6 @@ typedef enum { OPC_XOR =3D 0x4033, OPC_XORI =3D 0x4013, =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 OPC_ADDIW =3D 0x1b, OPC_ADDW =3D 0x3b, OPC_DIVUW =3D 0x200503b, @@ -250,23 +241,6 @@ typedef enum { OPC_SRLIW =3D 0x501b, OPC_SRLW =3D 0x503b, OPC_SUBW =3D 0x4000003b, -#else - /* Simplify code throughout by defining aliases for RV32. */ - OPC_ADDIW =3D OPC_ADDI, - OPC_ADDW =3D OPC_ADD, - OPC_DIVUW =3D OPC_DIVU, - OPC_DIVW =3D OPC_DIV, - OPC_MULW =3D OPC_MUL, - OPC_REMUW =3D OPC_REMU, - OPC_REMW =3D OPC_REM, - OPC_SLLIW =3D OPC_SLLI, - OPC_SLLW =3D OPC_SLL, - OPC_SRAIW =3D OPC_SRAI, - OPC_SRAW =3D OPC_SRA, - OPC_SRLIW =3D OPC_SRLI, - OPC_SRLW =3D OPC_SRL, - OPC_SUBW =3D OPC_SUB, -#endif =20 OPC_FENCE =3D 0x0000000f, OPC_NOP =3D OPC_ADDI, /* nop =3D addi r0,r0,0 */ @@ -500,7 +474,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, T= CGReg rd, tcg_target_long lo, hi, tmp; int shift, ret; =20 - if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I32) { + if (type =3D=3D TCG_TYPE_I32) { val =3D (int32_t)val; } =20 @@ -511,7 +485,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, T= CGReg rd, } =20 hi =3D val - lo; - if (TCG_TARGET_REG_BITS =3D=3D 32 || val =3D=3D (int32_t)val) { + if (val =3D=3D (int32_t)val) { tcg_out_opc_upper(s, OPC_LUI, rd, hi); if (lo !=3D 0) { tcg_out_opc_imm(s, OPC_ADDIW, rd, rd, lo); @@ -519,7 +493,6 @@ static void tcg_out_movi(TCGContext *s, TCGType type, T= CGReg rd, return; } =20 - /* We can only be here if TCG_TARGET_REG_BITS !=3D 32 */ tmp =3D tcg_pcrel_diff(s, (void *)val); if (tmp =3D=3D (int32_t)tmp) { tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); @@ -668,15 +641,15 @@ static void tcg_out_ldst(TCGContext *s, RISCVInsn opc= , TCGReg data, static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { - bool is32bit =3D (TCG_TARGET_REG_BITS =3D=3D 32 || type =3D=3D TCG_TYP= E_I32); - tcg_out_ldst(s, is32bit ? OPC_LW : OPC_LD, arg, arg1, arg2); + RISCVInsn insn =3D type =3D=3D TCG_TYPE_I32 ? OPC_LW : OPC_LD; + tcg_out_ldst(s, insn, arg, arg1, arg2); } =20 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { - bool is32bit =3D (TCG_TARGET_REG_BITS =3D=3D 32 || type =3D=3D TCG_TYP= E_I32); - tcg_out_ldst(s, is32bit ? OPC_SW : OPC_SD, arg, arg1, arg2); + RISCVInsn insn =3D type =3D=3D TCG_TYPE_I32 ? OPC_SW : OPC_SD; + tcg_out_ldst(s, insn, arg, arg1, arg2); } =20 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, @@ -853,20 +826,18 @@ static void tcg_out_call_int(TCGContext *s, const tcg= _insn_unit *arg, bool tail) if (offset =3D=3D sextreg(offset, 0, 20)) { /* short jump: -2097150 to 2097152 */ tcg_out_opc_jump(s, OPC_JAL, link, offset); - } else if (TCG_TARGET_REG_BITS =3D=3D 32 || offset =3D=3D (int32_t)off= set) { + } else if (offset =3D=3D (int32_t)offset) { /* long jump: -2147483646 to 2147483648 */ tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0); tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0); ret =3D reloc_call(s->code_ptr - 2, arg); tcg_debug_assert(ret =3D=3D true); - } else if (TCG_TARGET_REG_BITS =3D=3D 64) { + } else { /* far jump: 64-bit */ tcg_target_long imm =3D sextreg((tcg_target_long)arg, 0, 12); tcg_target_long base =3D (tcg_target_long)arg - imm; tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base); tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm); - } else { - g_assert_not_reached(); } } =20 @@ -942,9 +913,6 @@ static void * const qemu_st_helpers[MO_SIZE + 1] =3D { #endif }; =20 -/* We don't support oversize guests */ -QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); - /* We expect to use a 12-bit negative offset from ENV. */ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); @@ -956,8 +924,7 @@ static void tcg_out_goto(TCGContext *s, const tcg_insn_= unit *target) tcg_debug_assert(ok); } =20 -static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrl, - TCGReg addrh, MemOpIdx oi, +static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, MemOpIdx oi, tcg_insn_unit **label_ptr, bool is_load) { MemOp opc =3D get_memop(oi); @@ -973,7 +940,7 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg ad= drl, tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs); =20 - tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addrl, + tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); @@ -992,10 +959,10 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg = addrl, /* Clear the non-page, non-alignment bits from the address. */ compare_mask =3D (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - = 1); if (compare_mask =3D=3D sextreg(compare_mask, 0, 12)) { - tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addrl, compare_mask); + tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr, compare_mask); } else { tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); - tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addrl); + tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr); } =20 /* Compare masked address with the TLB entry. */ @@ -1003,29 +970,26 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg= addrl, tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); =20 /* TLB Hit - translate address using addend. */ - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP0, addrl); - addrl =3D TCG_REG_TMP0; + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_ext32u(s, TCG_REG_TMP0, addr); + addr =3D TCG_REG_TMP0; } - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl); + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addr); return TCG_REG_TMP0; } =20 static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, - TCGType ext, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addrhi, - void *raddr, tcg_insn_unit **label_ptr) + TCGType data_type, TCGReg data_reg, + TCGReg addr_reg, void *raddr, + tcg_insn_unit **label_ptr) { TCGLabelQemuLdst *label =3D new_ldst_label(s); =20 label->is_ld =3D is_ld; label->oi =3D oi; - label->type =3D ext; - label->datalo_reg =3D datalo; - label->datahi_reg =3D datahi; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; + label->type =3D data_type; + label->datalo_reg =3D data_reg; + label->addrlo_reg =3D addr_reg; label->raddr =3D tcg_splitwx_to_rx(raddr); label->label_ptr[0] =3D label_ptr[0]; } @@ -1039,11 +1003,6 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) TCGReg a2 =3D tcg_target_call_iarg_regs[2]; TCGReg a3 =3D tcg_target_call_iarg_regs[3]; =20 - /* We don't support oversize guests */ - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - g_assert_not_reached(); - } - /* resolve label address */ if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; @@ -1073,11 +1032,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) TCGReg a3 =3D tcg_target_call_iarg_regs[3]; TCGReg a4 =3D tcg_target_call_iarg_regs[4]; =20 - /* We don't support oversize guests */ - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - g_assert_not_reached(); - } - /* resolve label address */ if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; @@ -1146,7 +1100,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) =20 #endif /* CONFIG_SOFTMMU */ =20 -static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, +static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val, TCGReg base, MemOp opc, bool is_64) { /* Byte swapping is left to middle-end expansion. */ @@ -1154,37 +1108,28 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg lo, TCGReg hi, =20 switch (opc & (MO_SSIZE)) { case MO_UB: - tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); + tcg_out_opc_imm(s, OPC_LBU, val, base, 0); break; case MO_SB: - tcg_out_opc_imm(s, OPC_LB, lo, base, 0); + tcg_out_opc_imm(s, OPC_LB, val, base, 0); break; case MO_UW: - tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); + tcg_out_opc_imm(s, OPC_LHU, val, base, 0); break; case MO_SW: - tcg_out_opc_imm(s, OPC_LH, lo, base, 0); + tcg_out_opc_imm(s, OPC_LH, val, base, 0); break; case MO_UL: - if (TCG_TARGET_REG_BITS =3D=3D 64 && is_64) { - tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); + if (is_64) { + tcg_out_opc_imm(s, OPC_LWU, val, base, 0); break; } /* FALLTHRU */ case MO_SL: - tcg_out_opc_imm(s, OPC_LW, lo, base, 0); + tcg_out_opc_imm(s, OPC_LW, val, base, 0); break; case MO_UQ: - /* Prefer to load from offset 0 first, but allow for overlap. */ - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_opc_imm(s, OPC_LD, lo, base, 0); - } else if (lo !=3D base) { - tcg_out_opc_imm(s, OPC_LW, lo, base, 0); - tcg_out_opc_imm(s, OPC_LW, hi, base, 4); - } else { - tcg_out_opc_imm(s, OPC_LW, hi, base, 4); - tcg_out_opc_imm(s, OPC_LW, lo, base, 0); - } + tcg_out_opc_imm(s, OPC_LD, val, base, 0); break; default: g_assert_not_reached(); @@ -1193,8 +1138,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, =20 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) { - TCGReg addr_regl, addr_regh __attribute__((unused)); - TCGReg data_regl, data_regh; + TCGReg addr_reg, data_reg; MemOpIdx oi; MemOp opc; #if defined(CONFIG_SOFTMMU) @@ -1204,27 +1148,23 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is_64) #endif TCGReg base; =20 - data_regl =3D *args++; - data_regh =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); - addr_regl =3D *args++; - addr_regh =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); + data_reg =3D *args++; + addr_reg =3D *args++; oi =3D *args++; opc =3D get_memop(oi); =20 #if defined(CONFIG_SOFTMMU) - base =3D tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1); - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); - add_qemu_ldst_label(s, 1, oi, - (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_regl, data_regh, addr_regl, addr_regh, - s->code_ptr, label_ptr); + base =3D tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1); + tcg_out_qemu_ld_direct(s, data_reg, base, opc, is_64); + add_qemu_ldst_label(s, 1, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), + data_reg, addr_reg, s->code_ptr, label_ptr); #else a_bits =3D get_alignment_bits(opc); if (a_bits) { - tcg_out_test_alignment(s, true, addr_regl, a_bits); + tcg_out_test_alignment(s, true, addr_reg, a_bits); } - base =3D addr_regl; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + base =3D addr_reg; + if (TARGET_LONG_BITS =3D=3D 32) { tcg_out_ext32u(s, TCG_REG_TMP0, base); base =3D TCG_REG_TMP0; } @@ -1232,11 +1172,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is_64) tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base= ); base =3D TCG_REG_TMP0; } - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + tcg_out_qemu_ld_direct(s, data_reg, base, opc, is_64); #endif } =20 -static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, +static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg val, TCGReg base, MemOp opc) { /* Byte swapping is left to middle-end expansion. */ @@ -1244,21 +1184,16 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg lo, TCGReg hi, =20 switch (opc & (MO_SSIZE)) { case MO_8: - tcg_out_opc_store(s, OPC_SB, base, lo, 0); + tcg_out_opc_store(s, OPC_SB, base, val, 0); break; case MO_16: - tcg_out_opc_store(s, OPC_SH, base, lo, 0); + tcg_out_opc_store(s, OPC_SH, base, val, 0); break; case MO_32: - tcg_out_opc_store(s, OPC_SW, base, lo, 0); + tcg_out_opc_store(s, OPC_SW, base, val, 0); break; case MO_64: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_opc_store(s, OPC_SD, base, lo, 0); - } else { - tcg_out_opc_store(s, OPC_SW, base, lo, 0); - tcg_out_opc_store(s, OPC_SW, base, hi, 4); - } + tcg_out_opc_store(s, OPC_SD, base, val, 0); break; default: g_assert_not_reached(); @@ -1267,8 +1202,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, =20 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) { - TCGReg addr_regl, addr_regh __attribute__((unused)); - TCGReg data_regl, data_regh; + TCGReg addr_reg, data_reg; MemOpIdx oi; MemOp opc; #if defined(CONFIG_SOFTMMU) @@ -1278,27 +1212,23 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg *args, bool is_64) #endif TCGReg base; =20 - data_regl =3D *args++; - data_regh =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); - addr_regl =3D *args++; - addr_regh =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); + data_reg =3D *args++; + addr_reg =3D *args++; oi =3D *args++; opc =3D get_memop(oi); =20 #if defined(CONFIG_SOFTMMU) - base =3D tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0); - tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); - add_qemu_ldst_label(s, 0, oi, - (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_regl, data_regh, addr_regl, addr_regh, - s->code_ptr, label_ptr); + base =3D tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0); + tcg_out_qemu_st_direct(s, data_reg, base, opc); + add_qemu_ldst_label(s, 0, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), + data_reg, addr_reg, s->code_ptr, label_ptr); #else a_bits =3D get_alignment_bits(opc); if (a_bits) { - tcg_out_test_alignment(s, false, addr_regl, a_bits); + tcg_out_test_alignment(s, false, addr_reg, a_bits); } - base =3D addr_regl; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + base =3D addr_reg; + if (TARGET_LONG_BITS =3D=3D 32) { tcg_out_ext32u(s, TCG_REG_TMP0, base); base =3D TCG_REG_TMP0; } @@ -1306,7 +1236,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base= ); base =3D TCG_REG_TMP0; } - tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + tcg_out_qemu_st_direct(s, data_reg, base, opc); #endif } =20 @@ -1755,19 +1685,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) return C_O1_I4(r, rZ, rZ, rZ, rZ); =20 case INDEX_op_qemu_ld_i32: - return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS - ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); - case INDEX_op_qemu_st_i32: - return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS - ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L)); case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O2_I1(r, r,= L) - : C_O2_I2(r, r, L, L)); + return C_O1_I1(r, L); + case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(LZ, L) - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O0_I3(LZ, L= Z, L) - : C_O0_I4(LZ, LZ, L, L)); + return C_O0_I2(LZ, L); =20 default: g_assert_not_reached(); @@ -1843,9 +1765,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) static void tcg_target_init(TCGContext *s) { tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffff; - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffff; - } + tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffff; =20 tcg_target_call_clobber_regs =3D -1u; tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315943; cv=none; d=zohomail.com; s=zohoarc; b=jrcY2uhAcwyFRFTOyPx/txC3XzF53oJ294GLVeOHw2UBhVVq6W9ArYjyFEeLUfvatC9Sw5a4TrAByCcJSo7jPp9f/kD24GepOKmeb2qaQgHwV0gGQb5nEwoWbrerD4Mm24ImE3B2MKkbjiZIt4ITGSDz5GttUva4WUmYK7zMpcc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315943; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Lj83+ZuDeA8rnosHlZL+RYSkBwDzlxEBOWASJPRt7r8=; b=KMtVCGKlWTwyPsFu4FyAnAyDOTPNC6FAPdSQNlwF7qmlL3TKDinudizXkrnumY9xvPJ2DC703cyqm3RV66uPg1nmaZ/IRJ/zmeKko7ieMU2EJe5YXWF/SP7E97PThG2u2eaBm4yijTSKc8UHaCZbjyCfrk/FulDF+9VvvPZkrgc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315943378396.9522780300473; Sun, 23 Apr 2023 22:59:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqozv-000579-2n; Mon, 24 Apr 2023 01:44:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqoxj-0005qD-Tf for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:42:08 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqox1-0004Pw-C7 for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:42:07 -0400 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-3047ff3269aso96860f8f.0 for ; Sun, 23 Apr 2023 22:41:22 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. 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Pass data_type instead of is64 -- there are several places where we already convert back from bool to type. Clean things up by using type throughout. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 66 ++++++++++++++------------------------ 1 file changed, 24 insertions(+), 42 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 1edc3b1c4d..3b10ecb767 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1101,7 +1101,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) #endif /* CONFIG_SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val, - TCGReg base, MemOp opc, bool is_64) + TCGReg base, MemOp opc, TCGType type) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); @@ -1120,7 +1120,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg val, tcg_out_opc_imm(s, OPC_LH, val, base, 0); break; case MO_UL: - if (is_64) { + if (type =3D=3D TCG_TYPE_I64) { tcg_out_opc_imm(s, OPC_LWU, val, base, 0); break; } @@ -1136,30 +1136,21 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg val, } } =20 -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, + MemOpIdx oi, TCGType data_type) { - TCGReg addr_reg, data_reg; - MemOpIdx oi; - MemOp opc; -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[1]; -#else - unsigned a_bits; -#endif + MemOp opc =3D get_memop(oi); TCGReg base; =20 - data_reg =3D *args++; - addr_reg =3D *args++; - oi =3D *args++; - opc =3D get_memop(oi); - #if defined(CONFIG_SOFTMMU) + tcg_insn_unit *label_ptr[1]; + base =3D tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1); - tcg_out_qemu_ld_direct(s, data_reg, base, opc, is_64); - add_qemu_ldst_label(s, 1, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_reg, addr_reg, s->code_ptr, label_ptr); + tcg_out_qemu_ld_direct(s, data_reg, base, opc, data_type); + add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, + s->code_ptr, label_ptr); #else - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addr_reg, a_bits); } @@ -1172,7 +1163,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base= ); base =3D TCG_REG_TMP0; } - tcg_out_qemu_ld_direct(s, data_reg, base, opc, is_64); + tcg_out_qemu_ld_direct(s, data_reg, base, opc, data_type); #endif } =20 @@ -1200,30 +1191,21 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg val, } } =20 -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, + MemOpIdx oi, TCGType data_type) { - TCGReg addr_reg, data_reg; - MemOpIdx oi; - MemOp opc; -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[1]; -#else - unsigned a_bits; -#endif + MemOp opc =3D get_memop(oi); TCGReg base; =20 - data_reg =3D *args++; - addr_reg =3D *args++; - oi =3D *args++; - opc =3D get_memop(oi); - #if defined(CONFIG_SOFTMMU) + tcg_insn_unit *label_ptr[1]; + base =3D tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0); tcg_out_qemu_st_direct(s, data_reg, base, opc); - add_qemu_ldst_label(s, 0, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_reg, addr_reg, s->code_ptr, label_ptr); + add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, + s->code_ptr, label_ptr); #else - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, false, addr_reg, a_bits); } @@ -1528,16 +1510,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, false); + tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, true); + tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); break; case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, false); + tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, true); + tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); break; =20 case INDEX_op_extrh_i64_i32: --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315607; cv=none; d=zohomail.com; s=zohoarc; b=jpDbwdILQngU0IBiyDOXKrni2F/S0YgA9b1teravpNV4VrS54c3uSjnnxzj6rt6R443+g9fI9e/Mtvewn5+PAyVUIpwE+zoLHcn6sw0MjhYKPXkT04KCiiI+p/KJ7WPl/vLSTfK3Pwd8mQ17CgKQPMZJkSisaa/2F6umGHheKMY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315607; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XnZogszO9zYOnszOSYBVC/f6LR39oy/cEChj2R17Qdo=; b=NjaHUzxHviRBDwFyXjN0yBtqPAjd84JbDkkWC0MLluVyD2hw9/GpSW2xbuCZLfj/10cnZb93g0vQriqWshIeD/WTCfXxORUfr8MfODTbRbMNYYsNBhIZAjMAAMVT8d8abyLkbRDOug3o8UzrRHCoUnN8GqZagkp6e47BVxVoc/g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315607633548.360509775066; Sun, 23 Apr 2023 22:53:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqozj-0003SF-Qe; Mon, 24 Apr 2023 01:44:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqoxn-00060d-LT for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:42:24 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqox2-0004QJ-3x for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:42:10 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-3f19c473b9eso30735145e9.0 for ; Sun, 23 Apr 2023 22:41:23 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. 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Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 253 +++++++++++++++++-------------------- 1 file changed, 114 insertions(+), 139 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 3b10ecb767..b0ed39beff 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -913,10 +913,6 @@ static void * const qemu_st_helpers[MO_SIZE + 1] =3D { #endif }; =20 -/* We expect to use a 12-bit negative offset from ENV. */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); - static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) { tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); @@ -924,76 +920,6 @@ static void tcg_out_goto(TCGContext *s, const tcg_insn= _unit *target) tcg_debug_assert(ok); } =20 -static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, MemOpIdx oi, - tcg_insn_unit **label_ptr, bool is_load) -{ - MemOp opc =3D get_memop(oi); - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_bits =3D get_alignment_bits(opc); - tcg_target_long compare_mask; - int mem_index =3D get_mmuidx(oi); - int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); - int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); - int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); - TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; - - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs); - - tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); - - /* Load the tlb comparator and the addend. */ - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, - is_load ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, - offsetof(CPUTLBEntry, addend)); - - /* We don't support unaligned accesses. */ - if (a_bits < s_bits) { - a_bits =3D s_bits; - } - /* Clear the non-page, non-alignment bits from the address. */ - compare_mask =3D (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - = 1); - if (compare_mask =3D=3D sextreg(compare_mask, 0, 12)) { - tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr, compare_mask); - } else { - tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); - tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr); - } - - /* Compare masked address with the TLB entry. */ - label_ptr[0] =3D s->code_ptr; - tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); - - /* TLB Hit - translate address using addend. */ - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_TMP0, addr); - addr =3D TCG_REG_TMP0; - } - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addr); - return TCG_REG_TMP0; -} - -static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, - TCGType data_type, TCGReg data_reg, - TCGReg addr_reg, void *raddr, - tcg_insn_unit **label_ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D data_type; - label->datalo_reg =3D data_reg; - label->addrlo_reg =3D addr_reg; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr[0]; -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { MemOpIdx oi =3D l->oi; @@ -1051,26 +977,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) return true; } #else - -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_= reg, - unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *l =3D new_ldst_label(s); - - l->is_ld =3D is_ld; - l->addrlo_reg =3D addr_reg; - - /* We are expecting a_bits to max out at 7, so we can always use andi.= */ - tcg_debug_assert(a_bits < 12); - tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask); - - l->label_ptr[0] =3D s->code_ptr; - tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0); - - l->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { /* resolve label address */ @@ -1097,9 +1003,108 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) { return tcg_out_fail_alignment(s, l); } - #endif /* CONFIG_SOFTMMU */ =20 +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, + TCGReg addr_reg, MemOpIdx oi, + bool is_ld) +{ + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned a_mask =3D (1u << a_bits) - 1; + +#ifdef CONFIG_SOFTMMU + unsigned s_bits =3D opc & MO_SIZE; + int mem_index =3D get_mmuidx(oi); + int fast_ofs =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); + int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); + TCGReg mask_base =3D TCG_AREG0, table_base =3D TCG_AREG0; + tcg_target_long compare_mask; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs); + + tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr_reg, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); + + /* Load the tlb comparator and the addend. */ + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, + is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, + offsetof(CPUTLBEntry, addend)); + + /* We don't support unaligned accesses. */ + if (a_bits < s_bits) { + a_bits =3D s_bits; + } + /* Clear the non-page, non-alignment bits from the address. */ + compare_mask =3D (tcg_target_long)TARGET_PAGE_MASK | a_mask; + if (compare_mask =3D=3D sextreg(compare_mask, 0, 12)) { + tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, compare_mask); + } else { + tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); + tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr_reg); + } + + /* Compare masked address with the TLB entry. */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); + + /* TLB Hit - translate address using addend. */ + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg); + addr_reg =3D TCG_REG_TMP0; + } + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addr_reg); + *pbase =3D TCG_REG_TMP0; +#else + if (a_mask) { + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + /* We are expecting a_bits max 7, so we can always use andi. */ + tcg_debug_assert(a_bits < 12); + tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask); + + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0); + } + + TCGReg base =3D addr_reg; + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_ext32u(s, TCG_REG_TMP0, base); + base =3D TCG_REG_TMP0; + } + if (guest_base !=3D 0) { + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base= ); + base =3D TCG_REG_TMP0; + } + *pbase =3D base; +#endif + + return ldst; +} + static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val, TCGReg base, MemOp opc, TCGType type) { @@ -1139,32 +1144,17 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg val, static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; TCGReg base; =20 -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[1]; + ldst =3D prepare_host_addr(s, &base, addr_reg, oi, true); + tcg_out_qemu_ld_direct(s, data_reg, base, get_memop(oi), data_type); =20 - base =3D tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1); - tcg_out_qemu_ld_direct(s, data_reg, base, opc, data_type); - add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, true, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - base =3D addr_reg; - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_TMP0, base); - base =3D TCG_REG_TMP0; - } - if (guest_base !=3D 0) { - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base= ); - base =3D TCG_REG_TMP0; - } - tcg_out_qemu_ld_direct(s, data_reg, base, opc, data_type); -#endif } =20 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg val, @@ -1194,32 +1184,17 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg val, static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; TCGReg base; =20 -#if defined(CONFIG_SOFTMMU) - tcg_insn_unit *label_ptr[1]; + ldst =3D prepare_host_addr(s, &base, addr_reg, oi, false); + tcg_out_qemu_st_direct(s, data_reg, base, get_memop(oi)); =20 - base =3D tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0); - tcg_out_qemu_st_direct(s, data_reg, base, opc); - add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - if (a_bits) { - tcg_out_test_alignment(s, false, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - base =3D addr_reg; - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_TMP0, base); - base =3D TCG_REG_TMP0; - } - if (guest_base !=3D 0) { - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base= ); - base =3D TCG_REG_TMP0; - } - tcg_out_qemu_st_direct(s, data_reg, base, opc); -#endif } =20 static const tcg_insn_unit *tb_ret_addr; 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[46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314883; x=1684906883; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h+hQGAfxVGFgcw51jDi1fjFbmaS4u/aJWSe3Wo6FlWM=; b=ACtyLrakakBQmEc6asqDpJkdPZTAGr1J5eljdp295ly5H/RWmIPUgI5Ege3+C721E9 WlHCD8XPmsjBSa7LO4vdwk5BfUGHa1oJLwCts1k+Fl0pGACdeyjXFpA7+ljkYE2m2jmS MSpyJe438/NqKngZlj2UGPk3drV+Ym1e6togpesPdOWvgRlkSLHtqvK8LeB1YoOisWTT jHM6hVh7fhIj3PYrLy4SFhNETPDq5vWUeuRV9vF6yiJgzn8kFs6siaor4wtTpQeU7K7x x9aumxO1SRB9cf+P7QmKQY3zu06MRFRwFWJ0T3Qs1/hRlYAG1wT1jvRieC1pgF/Wditx u2YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314883; x=1684906883; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h+hQGAfxVGFgcw51jDi1fjFbmaS4u/aJWSe3Wo6FlWM=; b=CIu+nstL+J+hFW9v7J3G824yGLUIdSV9Ic/5kaDSwd7OTclj5S20zxAv8FFtpVUogY O77blYc4bI9ooR+b6tr4dJ/FxYrKHOGsHGtL/00KFEW9HFA43xhcr1pvhu4P8WQEL9YX VAbbVO4eirddpyH4QtiFJ0Tpod5Alf7cvbFJOZEU249FAmj431OEQq5FYqdTw/JDN/QG aG2RyWUcrOKS8Avr7Z2vaV9TdqupY0KOl1SL0UZntQIEOLkANjvA7wLn5QBOTpGMJ9vA 1Kc4wFvQjWXCAODa0NsT09mxi6rl/L3H6XBNrMcZzGMyaxysdaNGx9D4s+gZuhkxfEDn KVoQ== X-Gm-Message-State: AAQBX9dPV/YFTvysBOEeQRY0iWgJeHb169QRMGSOvBxdVn4NDciW2x5C Z7b2IFBXnEzYoxa39LDFK0PhgboX5A+COxlDktLKHA== X-Google-Smtp-Source: AKy350anfP8+QgNrPCXGLBeE+OlSLmPdFu6E1xjCwBePmQDAxC8zwdYPSQqQZENe/gF4z+GgoC0W2Q== X-Received: by 2002:adf:cd82:0:b0:2cf:eb86:bd90 with SMTP id q2-20020adfcd82000000b002cfeb86bd90mr8763061wrj.63.1682314883017; Sun, 23 Apr 2023 22:41:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 29/57] tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st} Date: Mon, 24 Apr 2023 06:40:37 +0100 Message-Id: <20230424054105.1579315-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315922070100015 We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index b399798664..e931f0cde4 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1770,13 +1770,14 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addr_reg, MemOp opc, } =20 static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, - TCGReg data, TCGReg addr, + TCGType type, TCGReg data, TCGReg addr, tcg_insn_unit *raddr, tcg_insn_unit *label= _ptr) { TCGLabelQemuLdst *label =3D new_ldst_label(s); =20 label->is_ld =3D is_ld; label->oi =3D oi; + label->type =3D type; label->datalo_reg =3D data; label->addrlo_reg =3D addr; label->raddr =3D tcg_splitwx_to_rx(raddr); @@ -1900,7 +1901,7 @@ static void tcg_prepare_user_ldst(TCGContext *s, TCGR= eg *addr_reg, #endif /* CONFIG_SOFTMMU */ =20 static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_re= g, - MemOpIdx oi) + MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); #ifdef CONFIG_SOFTMMU @@ -1916,7 +1917,8 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg dat= a_reg, TCGReg addr_reg, =20 tcg_out_qemu_ld_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0); =20 - add_qemu_ldst_label(s, 1, oi, data_reg, addr_reg, s->code_ptr, label_p= tr); + add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, + s->code_ptr, label_ptr); #else TCGReg index_reg; tcg_target_long disp; @@ -1931,7 +1933,7 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg dat= a_reg, TCGReg addr_reg, } =20 static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_re= g, - MemOpIdx oi) + MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); #ifdef CONFIG_SOFTMMU @@ -1947,7 +1949,8 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg dat= a_reg, TCGReg addr_reg, =20 tcg_out_qemu_st_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0); =20 - add_qemu_ldst_label(s, 0, oi, data_reg, addr_reg, s->code_ptr, label_p= tr); + add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, + s->code_ptr, label_ptr); #else TCGReg index_reg; tcg_target_long disp; @@ -2307,13 +2310,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, break; =20 case INDEX_op_qemu_ld_i32: - /* ??? Technically we can use a non-extending instruction. */ + tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I32); + break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args[0], args[1], args[2]); + tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I64); break; case INDEX_op_qemu_st_i32: + tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I32); + break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args[0], args[1], args[2]); + tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I64); break; =20 case INDEX_op_ld16s_i64: --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315613; cv=none; d=zohomail.com; s=zohoarc; b=C9GP5uAUNHvK3duiFii99kurT/gTiS7KUcedmM62j58lf7uR1hZmQOAV67l3EgYcUgkG+F3HyDNBgnwuRuUt03M1/D53B2h72h100tvsF5AUPWM3/S6jk+/042g4rvoBll/Lb75gEiF0IxJCkttXQxtBkoQI67eAob539E9iAMc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315613; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Qowvb+qOV3aQYrEqXjQNCyaJCRa0p6aZo6j5FULejHU=; b=lQWqZCXQ7NivgOy1e9oaC8vpD0WDY62mruENkLW10yhoicXg/4OXJXtqCw0+auw/NBHtNDruNJDL2bCH7vL8MpbjDmFYWAHlCIoCU1io/wRhrtZIdQJpNZwqpDMosdUqyA1b6Wh3W2sIMhJ1Abn93aY251XFfjxULoF+nlRT/fU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315613021539.3439034708446; Sun, 23 Apr 2023 22:53:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqoza-0001zA-NX; Mon, 24 Apr 2023 01:44:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqoxr-00060z-VM for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:42:33 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqox3-0004RM-UZ for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:42:12 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-3f18335a870so24609375e9.0 for ; Sun, 23 Apr 2023 22:41:24 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314883; x=1684906883; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Qowvb+qOV3aQYrEqXjQNCyaJCRa0p6aZo6j5FULejHU=; b=VbJtWDhyEQHmyLdGSnT9W6ug0wZpBBDt1liJs4mokpXE1lsGhe3bm/zxZiwUJoAyS3 rHSjAP1IBBxb5YyvwcJz3vXnF6Yezgx7UJXP3aPCgU15V/Muhk92TGVPIm3cGYQZeYeI 9Em/CDAKZ2b3SnqJA74GPqhCVo7Glu4GvgwqYwCuA5haOrAAhdJTrnRYS7rrpWhPYgPD tnYBf9dc1pxJBXuD5B8VstLdU4hw8uOiuNrrXKLOHf5MIXPp9AUUhNvILSAMAH4DsCgT qwRpciYTfptb5Gv/xQBxg8ry5C7zUgir2v0J1RWbrbOG8UUOS0Cf8hWe3YiBfJpL7Ds3 KaDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314883; x=1684906883; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Qowvb+qOV3aQYrEqXjQNCyaJCRa0p6aZo6j5FULejHU=; b=LBWSgnyqJh1+ivkXHNdPVr/chbQNVteF0vojNMCUnMVVQ7yQa1voS/3D50l6WokzW0 t6jRWX6ouSQ8H/bR/T90j68hzx6Hq8fAA/ONJTdXGw6UKrMEcSWPe/AO3EBo8z8y+vai f2Zt+9I2YVVLIh2LH5Wtq3v7X3NxvErgejVxiNVz/35rghEAYz6oujtKbKWFNJZt8D0/ XY8xTQ2FUM8/Pnag5f+Ji5aeIQ2h8EbLglln9m6hEFTVl69yh5JuYmpoQQXp/1fYSuRn 0Ax1Uo+CQKItqII8ms7dESR5fFxQmPEBqIhyoJSJ1F2EsFbNxzzB8DDsEAS4iSrLH3kb +JzQ== X-Gm-Message-State: AAQBX9fHvqyaf0sZrQXEWxb8N5ptLtC753T1Z+KfJ186R2VUAWKHOdc9 faF4If8zR7eNGLPtMzdx/zsj602eZi4u/WTzTCU2ZA== X-Google-Smtp-Source: AKy350YifikSpYlBZZrNJM2bH4JvTLtX6zv2JnO2LxmWrSS/OdTJl+ypVzpFOL2gTLCBHHDWuSz3Ig== X-Received: by 2002:a5d:4e41:0:b0:2f2:783f:ae4a with SMTP id r1-20020a5d4e41000000b002f2783fae4amr9481138wrt.32.1682314883562; Sun, 23 Apr 2023 22:41:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 30/57] tcg/s390x: Introduce HostAddress Date: Mon, 24 Apr 2023 06:40:38 +0100 Message-Id: <20230424054105.1579315-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315613557100009 Content-Type: text/plain; charset="utf-8" Collect the 3 potential parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st}_direct to use it. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/s390x/tcg-target.c.inc | 109 ++++++++++++++++++++----------------- 1 file changed, 60 insertions(+), 49 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index e931f0cde4..da7ee5b085 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1606,58 +1606,64 @@ static void tcg_out_call(TCGContext *s, const tcg_i= nsn_unit *dest, tcg_out_call_int(s, dest); } =20 +typedef struct { + TCGReg base; + TCGReg index; + int disp; +} HostAddress; + static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data, - TCGReg base, TCGReg index, int disp) + HostAddress h) { switch (opc & (MO_SSIZE | MO_BSWAP)) { case MO_UB: - tcg_out_insn(s, RXY, LLGC, data, base, index, disp); + tcg_out_insn(s, RXY, LLGC, data, h.base, h.index, h.disp); break; case MO_SB: - tcg_out_insn(s, RXY, LGB, data, base, index, disp); + tcg_out_insn(s, RXY, LGB, data, h.base, h.index, h.disp); break; =20 case MO_UW | MO_BSWAP: /* swapped unsigned halfword load with upper bits zeroed */ - tcg_out_insn(s, RXY, LRVH, data, base, index, disp); + tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp); tcg_out_ext16u(s, data, data); break; case MO_UW: - tcg_out_insn(s, RXY, LLGH, data, base, index, disp); + tcg_out_insn(s, RXY, LLGH, data, h.base, h.index, h.disp); break; =20 case MO_SW | MO_BSWAP: /* swapped sign-extended halfword load */ - tcg_out_insn(s, RXY, LRVH, data, base, index, disp); + tcg_out_insn(s, RXY, LRVH, data, h.base, h.index, h.disp); tcg_out_ext16s(s, TCG_TYPE_REG, data, data); break; case MO_SW: - tcg_out_insn(s, RXY, LGH, data, base, index, disp); + tcg_out_insn(s, RXY, LGH, data, h.base, h.index, h.disp); break; =20 case MO_UL | MO_BSWAP: /* swapped unsigned int load with upper bits zeroed */ - tcg_out_insn(s, RXY, LRV, data, base, index, disp); + tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp); tcg_out_ext32u(s, data, data); break; case MO_UL: - tcg_out_insn(s, RXY, LLGF, data, base, index, disp); + tcg_out_insn(s, RXY, LLGF, data, h.base, h.index, h.disp); break; =20 case MO_SL | MO_BSWAP: /* swapped sign-extended int load */ - tcg_out_insn(s, RXY, LRV, data, base, index, disp); + tcg_out_insn(s, RXY, LRV, data, h.base, h.index, h.disp); tcg_out_ext32s(s, data, data); break; case MO_SL: - tcg_out_insn(s, RXY, LGF, data, base, index, disp); + tcg_out_insn(s, RXY, LGF, data, h.base, h.index, h.disp); break; =20 case MO_UQ | MO_BSWAP: - tcg_out_insn(s, RXY, LRVG, data, base, index, disp); + tcg_out_insn(s, RXY, LRVG, data, h.base, h.index, h.disp); break; case MO_UQ: - tcg_out_insn(s, RXY, LG, data, base, index, disp); + tcg_out_insn(s, RXY, LG, data, h.base, h.index, h.disp); break; =20 default: @@ -1666,44 +1672,44 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, M= emOp opc, TCGReg data, } =20 static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data, - TCGReg base, TCGReg index, int disp) + HostAddress h) { switch (opc & (MO_SIZE | MO_BSWAP)) { case MO_UB: - if (disp >=3D 0 && disp < 0x1000) { - tcg_out_insn(s, RX, STC, data, base, index, disp); + if (h.disp >=3D 0 && h.disp < 0x1000) { + tcg_out_insn(s, RX, STC, data, h.base, h.index, h.disp); } else { - tcg_out_insn(s, RXY, STCY, data, base, index, disp); + tcg_out_insn(s, RXY, STCY, data, h.base, h.index, h.disp); } break; =20 case MO_UW | MO_BSWAP: - tcg_out_insn(s, RXY, STRVH, data, base, index, disp); + tcg_out_insn(s, RXY, STRVH, data, h.base, h.index, h.disp); break; case MO_UW: - if (disp >=3D 0 && disp < 0x1000) { - tcg_out_insn(s, RX, STH, data, base, index, disp); + if (h.disp >=3D 0 && h.disp < 0x1000) { + tcg_out_insn(s, RX, STH, data, h.base, h.index, h.disp); } else { - tcg_out_insn(s, RXY, STHY, data, base, index, disp); + tcg_out_insn(s, RXY, STHY, data, h.base, h.index, h.disp); } break; =20 case MO_UL | MO_BSWAP: - tcg_out_insn(s, RXY, STRV, data, base, index, disp); + tcg_out_insn(s, RXY, STRV, data, h.base, h.index, h.disp); break; case MO_UL: - if (disp >=3D 0 && disp < 0x1000) { - tcg_out_insn(s, RX, ST, data, base, index, disp); + if (h.disp >=3D 0 && h.disp < 0x1000) { + tcg_out_insn(s, RX, ST, data, h.base, h.index, h.disp); } else { - tcg_out_insn(s, RXY, STY, data, base, index, disp); + tcg_out_insn(s, RXY, STY, data, h.base, h.index, h.disp); } break; =20 case MO_UQ | MO_BSWAP: - tcg_out_insn(s, RXY, STRVG, data, base, index, disp); + tcg_out_insn(s, RXY, STRVG, data, h.base, h.index, h.disp); break; case MO_UQ: - tcg_out_insn(s, RXY, STG, data, base, index, disp); + tcg_out_insn(s, RXY, STG, data, h.base, h.index, h.disp); break; =20 default: @@ -1883,20 +1889,23 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) return tcg_out_fail_alignment(s, l); } =20 -static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg, - TCGReg *index_reg, tcg_target_long *disp) +static HostAddress tcg_prepare_user_ldst(TCGContext *s, TCGReg addr_reg) { + TCGReg index; + int disp; + if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_TMP0, *addr_reg); - *addr_reg =3D TCG_TMP0; + tcg_out_ext32u(s, TCG_TMP0, addr_reg); + addr_reg =3D TCG_TMP0; } if (guest_base < 0x80000) { - *index_reg =3D TCG_REG_NONE; - *disp =3D guest_base; + index =3D TCG_REG_NONE; + disp =3D guest_base; } else { - *index_reg =3D TCG_GUEST_BASE_REG; - *disp =3D 0; + index =3D TCG_GUEST_BASE_REG; + disp =3D 0; } + return (HostAddress){ .base =3D addr_reg, .index =3D index, .disp =3D = disp }; } #endif /* CONFIG_SOFTMMU */ =20 @@ -1904,31 +1913,32 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg d= ata_reg, TCGReg addr_reg, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); + HostAddress h; + #ifdef CONFIG_SOFTMMU unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; - TCGReg base_reg; =20 - base_reg =3D tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1); + h.base =3D tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1); + h.index =3D TCG_REG_R2; + h.disp =3D 0; =20 tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); label_ptr =3D s->code_ptr; s->code_ptr +=3D 1; =20 - tcg_out_qemu_ld_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0); + tcg_out_qemu_ld_direct(s, opc, data_reg, h); =20 add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, s->code_ptr, label_ptr); #else - TCGReg index_reg; - tcg_target_long disp; unsigned a_bits =3D get_alignment_bits(opc); =20 if (a_bits) { tcg_out_test_alignment(s, true, addr_reg, a_bits); } - tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp); - tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, index_reg, disp); + h =3D tcg_prepare_user_ldst(s, addr_reg); + tcg_out_qemu_ld_direct(s, opc, data_reg, h); #endif } =20 @@ -1936,31 +1946,32 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg d= ata_reg, TCGReg addr_reg, MemOpIdx oi, TCGType data_type) { MemOp opc =3D get_memop(oi); + HostAddress h; + #ifdef CONFIG_SOFTMMU unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; - TCGReg base_reg; =20 - base_reg =3D tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0); + h.base =3D tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0); + h.index =3D TCG_REG_R2; + h.disp =3D 0; =20 tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); label_ptr =3D s->code_ptr; s->code_ptr +=3D 1; =20 - tcg_out_qemu_st_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0); + tcg_out_qemu_st_direct(s, opc, data_reg, h); =20 add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, s->code_ptr, label_ptr); #else - TCGReg index_reg; - tcg_target_long disp; unsigned a_bits =3D get_alignment_bits(opc); =20 if (a_bits) { tcg_out_test_alignment(s, false, addr_reg, a_bits); } - tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp); - tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, index_reg, disp); + h =3D tcg_prepare_user_ldst(s, addr_reg); + tcg_out_qemu_st_direct(s, opc, data_reg, h); #endif } =20 --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315646; cv=none; d=zohomail.com; s=zohoarc; b=JudcXyMxGr1j88/WzkKObF52b4NUFZ4RGY5P/Is6272VhJESlHuMSKPjm3exjqPkVZCTJlQryIFTrt0Sh6v8V3Go3F+PW5iJFuUOHdSj/WCZggkIzwD+ZOG/76hBt+fBAPJlNJBCnoJq1Ddf8t7YkIJxyIRS2SVVA8lCdxNJxj4= ARC-Message-Signature: i=1; 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[46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314884; x=1684906884; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/+D3flHoA+lO9qFOAJD5/z5k4A1tFbbT3jeq7/jtxrQ=; b=pqT7yj5CA1NrmUALzhtHqiNXuBpNUkdlbmsNqMwyMo08N31S8BN7H7GFQOysoiUkad deVQs87Q7TA/5fioVJs5SzjyCdair7tHQKb5GgEJ1E22nNN2Jzq+BG2Zyx9Cn3xdpPMA 5ghjlr/5yxKOmtcqOQYNOxmLus9ie+s+yOnDuNsi5AW9ok1++SxgomjjLQu9WQKsfnqN VrXFE9U6FTpAXzKZXPSK4hvDxeqhHY22NlEWBzYurRZ5mYj7dsf9XvQkEJzVAHjlqdf8 73xf7NKDrRw7SLPRf6cZvR3tbRkuJr1ZBqxrSw0R9NIfRQqUO9wdcql+FQ2p/h52lfop nwEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314884; x=1684906884; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/+D3flHoA+lO9qFOAJD5/z5k4A1tFbbT3jeq7/jtxrQ=; b=eRJj0zlSCODBaYbk885D79K+kSo01D/kxaS6Yzp0r+tInRWWH9xM6qLHrciSeJ9Rog yzkFFzEgQiFTiR+F59n3xAdw6ThNSqfyl5RzuqouZGhPZ32HFnLVg/d5GKWazcplhSMO 3WV1AgD3nWGfE3LjNqgJcQVXLQOMRbXelXml8TwtrU0J04uSNZA2St+lo+j6yw//mbEu JEaRJ2WgszqnIHPPUjUR74kABekYSQT5RjFl/RPM6ZnT2045UYRfzT0fPXmGb1balwrr ALP8lkxWlaaPIhsGamxegZngvXpVXVtDhgvelvwMrw7CH+3BOpcUrpZ560fKllv8Kdlq 3NxQ== X-Gm-Message-State: AAQBX9eHGOYqBSYURyKRAHlc3ViySGy6VO8FpnPlilea+TmTZSKavP5U Khsdv7icD24AXRqdqmzQAPFJ6lgSP5wDjPyc6z+DHg== X-Google-Smtp-Source: AKy350a48gip89YH9o5RkpecSctlE8GdfXDEmKRklxG7clvOzfVMsHU1imKhFPlGM2+5Z2L4vmol/Q== X-Received: by 2002:a5d:4c4e:0:b0:2f6:1a6d:a6c3 with SMTP id n14-20020a5d4c4e000000b002f61a6da6c3mr13188212wrt.21.1682314884229; Sun, 23 Apr 2023 22:41:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 31/57] tcg/s390x: Introduce prepare_host_addr Date: Mon, 24 Apr 2023 06:40:39 +0100 Message-Id: <20230424054105.1579315-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315646766100001 Content-Type: text/plain; charset="utf-8" Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, tcg_prepare_user_ldst, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 263 ++++++++++++++++--------------------- 1 file changed, 113 insertions(+), 150 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index da7ee5b085..c3157d22be 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1718,78 +1718,6 @@ static void tcg_out_qemu_st_direct(TCGContext *s, Me= mOp opc, TCGReg data, } =20 #if defined(CONFIG_SOFTMMU) -/* We're expecting to use a 20-bit negative offset on the tlb memory ops. = */ -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); -QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); - -/* Load and compare a TLB entry, leaving the flags set. Loads the TLB - addend into R2. Returns a register with the santitized guest address. = */ -static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc, - int mem_index, bool is_ld) -{ - unsigned s_bits =3D opc & MO_SIZE; - unsigned a_bits =3D get_alignment_bits(opc); - unsigned s_mask =3D (1 << s_bits) - 1; - unsigned a_mask =3D (1 << a_bits) - 1; - int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); - int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); - int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); - int ofs, a_off; - uint64_t tlb_mask; - - tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE, - TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - tcg_out_insn(s, RXY, NG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, mask_off= ); - tcg_out_insn(s, RXY, AG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, table_of= f); - - /* For aligned accesses, we check the first byte and include the align= ment - bits within the address. For unaligned access, we check that we do= n't - cross pages using the address of the last byte of the access. */ - a_off =3D (a_bits >=3D s_bits ? 0 : s_mask - a_mask); - tlb_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; - if (a_off =3D=3D 0) { - tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask); - } else { - tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off); - tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask); - } - - if (is_ld) { - ofs =3D offsetof(CPUTLBEntry, addr_read); - } else { - ofs =3D offsetof(CPUTLBEntry, addr_write); - } - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_insn(s, RX, C, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs); - } else { - tcg_out_insn(s, RXY, CG, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs= ); - } - - tcg_out_insn(s, RXY, LG, TCG_REG_R2, TCG_REG_R2, TCG_REG_NONE, - offsetof(CPUTLBEntry, addend)); - - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_R3, addr_reg); - return TCG_REG_R3; - } - return addr_reg; -} - -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, - TCGType type, TCGReg data, TCGReg addr, - tcg_insn_unit *raddr, tcg_insn_unit *label= _ptr) -{ - TCGLabelQemuLdst *label =3D new_ldst_label(s); - - label->is_ld =3D is_ld; - label->oi =3D oi; - label->type =3D type; - label->datalo_reg =3D data; - label->addrlo_reg =3D addr; - label->raddr =3D tcg_splitwx_to_rx(raddr); - label->label_ptr[0] =3D label_ptr; -} - static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGReg addr_reg =3D lb->addrlo_reg; @@ -1842,26 +1770,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) return true; } #else -static void tcg_out_test_alignment(TCGContext *s, bool is_ld, - TCGReg addrlo, unsigned a_bits) -{ - unsigned a_mask =3D (1 << a_bits) - 1; - TCGLabelQemuLdst *l =3D new_ldst_label(s); - - l->is_ld =3D is_ld; - l->addrlo_reg =3D addrlo; - - /* We are expecting a_bits to max out at 7, much lower than TMLL. */ - tcg_debug_assert(a_bits < 16); - tcg_out_insn(s, RI, TMLL, addrlo, a_mask); - - tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */ - l->label_ptr[0] =3D s->code_ptr; - s->code_ptr +=3D 1; - - l->raddr =3D tcg_splitwx_to_rx(s->code_ptr); -} - static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { if (!patch_reloc(l->label_ptr[0], R_390_PC16DBL, @@ -1888,91 +1796,146 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *= s, TCGLabelQemuLdst *l) { return tcg_out_fail_alignment(s, l); } +#endif /* CONFIG_SOFTMMU */ =20 -static HostAddress tcg_prepare_user_ldst(TCGContext *s, TCGReg addr_reg) +/* + * For softmmu, perform the TLB load and compare. + * For useronly, perform any required alignment tests. + * In both cases, return a TCGLabelQemuLdst structure if the slow path + * is required and fill in @h with the host address for the fast path. + */ +static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, + TCGReg addr_reg, MemOpIdx oi, + bool is_ld) { - TCGReg index; - int disp; + TCGLabelQemuLdst *ldst =3D NULL; + MemOp opc =3D get_memop(oi); + unsigned a_bits =3D get_alignment_bits(opc); + unsigned a_mask =3D (1u << a_bits) - 1; =20 +#ifdef CONFIG_SOFTMMU + unsigned s_bits =3D opc & MO_SIZE; + unsigned s_mask =3D (1 << s_bits) - 1; + int mem_index =3D get_mmuidx(oi); + int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); + int ofs, a_off; + uint64_t tlb_mask; + + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); + QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); + tcg_out_insn(s, RXY, NG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, mask_off= ); + tcg_out_insn(s, RXY, AG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, table_of= f); + + /* + * For aligned accesses, we check the first byte and include the align= ment + * bits within the address. For unaligned access, we check that we do= n't + * cross pages using the address of the last byte of the access. + */ + a_off =3D (a_bits >=3D s_bits ? 0 : s_mask - a_mask); + tlb_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; + if (a_off =3D=3D 0) { + tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask); + } else { + tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off); + tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask); + } + + if (is_ld) { + ofs =3D offsetof(CPUTLBEntry, addr_read); + } else { + ofs =3D offsetof(CPUTLBEntry, addr_write); + } + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_insn(s, RX, C, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs); + } else { + tcg_out_insn(s, RXY, CG, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs= ); + } + + tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); + ldst->label_ptr[0] =3D s->code_ptr++; + + h->index =3D TCG_REG_R2; + tcg_out_insn(s, RXY, LG, h->index, TCG_REG_R2, TCG_REG_NONE, + offsetof(CPUTLBEntry, addend)); + + h->base =3D addr_reg; + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_ext32u(s, TCG_REG_R3, addr_reg); + h->base =3D TCG_REG_R3; + } + h->disp =3D 0; +#else + if (a_mask) { + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + /* We are expecting a_bits to max out at 7, much lower than TMLL. = */ + tcg_debug_assert(a_bits < 16); + tcg_out_insn(s, RI, TMLL, addr_reg, a_mask); + + tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */ + ldst->label_ptr[0] =3D s->code_ptr++; + } + + h->base =3D addr_reg; if (TARGET_LONG_BITS =3D=3D 32) { tcg_out_ext32u(s, TCG_TMP0, addr_reg); - addr_reg =3D TCG_TMP0; + h->base =3D TCG_TMP0; } if (guest_base < 0x80000) { - index =3D TCG_REG_NONE; - disp =3D guest_base; + h->index =3D TCG_REG_NONE; + h->disp =3D guest_base; } else { - index =3D TCG_GUEST_BASE_REG; - disp =3D 0; + h->index =3D TCG_GUEST_BASE_REG; + h->disp =3D 0; } - return (HostAddress){ .base =3D addr_reg, .index =3D index, .disp =3D = disp }; +#endif + + return ldst; } -#endif /* CONFIG_SOFTMMU */ =20 static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - unsigned mem_index =3D get_mmuidx(oi); - tcg_insn_unit *label_ptr; + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, true); + tcg_out_qemu_ld_direct(s, get_memop(oi), data_reg, h); =20 - h.base =3D tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1); - h.index =3D TCG_REG_R2; - h.disp =3D 0; - - tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); - label_ptr =3D s->code_ptr; - s->code_ptr +=3D 1; - - tcg_out_qemu_ld_direct(s, opc, data_reg, h); - - add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - - if (a_bits) { - tcg_out_test_alignment(s, true, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - h =3D tcg_prepare_user_ldst(s, addr_reg); - tcg_out_qemu_ld_direct(s, opc, data_reg, h); -#endif } =20 static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType data_type) { - MemOp opc =3D get_memop(oi); + TCGLabelQemuLdst *ldst; HostAddress h; =20 -#ifdef CONFIG_SOFTMMU - unsigned mem_index =3D get_mmuidx(oi); - tcg_insn_unit *label_ptr; + ldst =3D prepare_host_addr(s, &h, addr_reg, oi, false); + tcg_out_qemu_st_direct(s, get_memop(oi), data_reg, h); =20 - h.base =3D tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0); - h.index =3D TCG_REG_R2; - h.disp =3D 0; - - tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); - label_ptr =3D s->code_ptr; - s->code_ptr +=3D 1; - - tcg_out_qemu_st_direct(s, opc, data_reg, h); - - add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg, - s->code_ptr, label_ptr); -#else - unsigned a_bits =3D get_alignment_bits(opc); - - if (a_bits) { - tcg_out_test_alignment(s, false, addr_reg, a_bits); + if (ldst) { + ldst->type =3D data_type; + ldst->datalo_reg =3D data_reg; + ldst->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } - h =3D tcg_prepare_user_ldst(s, addr_reg); - tcg_out_qemu_st_direct(s, opc, data_reg, h); -#endif } =20 static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314885; x=1684906885; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ePGQgjAgeqBpbV0KhHIgImg7evASXxc6+J4X6wS7qUw=; b=OAj6GX7mCKtoLQ7ZQ2n69KRgT1R41mubfR5kqKBABUgRb0dxXq1O5JhtuvvHx57jl1 /cPuK6vu8xoWCSU73Z9YqkYXufaDnMRTjkEK52zbfe0uUmZueMLMWgL0yJf8zuhiR1Cv ojdNEQXGq1grXC7mQYPdCryrJzUGZFP6aG7O9R7PhYDCtfYPspGYbmnXgWzENnYaN8yg o/hAaTKa+jRu74ubghrNbxOo/s19PXul8F6zGftuW9wVgjcgEMfPWwCVVHoxYyWDJCH+ DW4R0edTNzqH9ezfxGvVScSzdTTPmyQM7kA7AAQs6jQ6rVrNzx0prI0naX9RWLHXi9cZ ycMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314885; x=1684906885; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ePGQgjAgeqBpbV0KhHIgImg7evASXxc6+J4X6wS7qUw=; b=X2N1H9YgN9mgZ3cwsSzJll2LtELZYoBn0kv3+47iKWM5NK4FmT9LNDRMoguuhWZONy ZdstrBqUpMgB1+XO/s3qzBD18h3afFMfDFRJLDA9t8QfKD8ZHKngLD4LlDNa5sJUYUOX GLfgXvnDp1Q0sPWk4tyiRguEuQxDfkx7vnD/fXs6fhaPPbaW29dkScbnMyK6fjUsWjf3 Wbz4rxFSLjPoqti5df+uKWQm8wpvdFytJaI41X2RyARWSOjuHIUd7iBmdcne+Ez+V0UG /4LN1/GEQW2drknYkIAFzHx3jBUK4bGlOq1kjYschU18Mpvd8PW8VLMn+/T0BlzGSMCV 1SqA== X-Gm-Message-State: AAQBX9fIMpl1sZbrABMAS35uB9mThlWX6Al4ciifzKM0aarCFuk9yu2t c7tuGoLe9RcL+2l07gIUexcozcSz37uwOd1SoM3MPg== X-Google-Smtp-Source: AKy350YsGgoNJ+3HJHv9J2Vg7M7rn8Xxa0aBMvSgL2bFcCjXeasKFZ8KzTLi0c8pAXYXr4mk/TotWQ== X-Received: by 2002:adf:f70b:0:b0:2f9:eeab:4eb0 with SMTP id r11-20020adff70b000000b002f9eeab4eb0mr7857678wrp.34.1682314884919; Sun, 23 Apr 2023 22:41:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 32/57] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return Date: Mon, 24 Apr 2023 06:40:40 +0100 Message-Id: <20230424054105.1579315-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315802055100001 In tcg_canonicalize_memop, we remove MO_SIGN from MO_32 operations with TCG_TYPE_I32. Thus this is never set. We already have an identical test just above which does not include is_64 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 4f477d539c..dbe4bf96b9 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1220,7 +1220,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a, TCGReg addr, tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_O2, oi); =20 /* We let the helper sign-extend SB and SW, but leave SL for here. */ - if (is_64 && (memop & MO_SSIZE) =3D=3D MO_SL) { + if ((memop & MO_SSIZE) =3D=3D MO_SL) { tcg_out_ext32s(s, data, TCG_REG_O0); } else { tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0); --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315915; cv=none; d=zohomail.com; s=zohoarc; b=EkZRwUJZCr3BhSnyqCUquYRF3RZ2K4kAEkoxaN5sFnE0YUsjtdPyeyb7OxshGNc0Fp6QgkncJ6/JONOl+h8jTLOyXsN+hlzENgcAW96Z7Zmyi4cUbm44DeJ2aeElm8QBSdvbtylsyLc0KNURAwOYINXB5BHbmW0daGV9BiH3QQM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315915; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Bq2h9X5UNDb637fCQb6pFT3eLaF1A8JaUegXUakX2qE=; b=Tf1lKgqgom4vHwdfZx4y8FZjq1kIdJGkMbVxC68NPwn8FzVBPD2AY6IOZcXZtt8TUytELHkf/eio9rhJ3e76ILAyBVjpW+zC8CPZsRIwlRMo4uE641UOEIQ3tUj38ui7CGqFumRL/XhOw5ArTljd4CHhD9Znc2geMyqz8mqCZWY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315915381884.73805339444; Sun, 23 Apr 2023 22:58:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqp2D-0007dq-UN; Mon, 24 Apr 2023 01:46:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqoxr-00060x-VQ for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:42:33 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqox5-0004Sh-Lc for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:42:14 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3f173af665fso24579665e9.3 for ; Sun, 23 Apr 2023 22:41:26 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314885; x=1684906885; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Bq2h9X5UNDb637fCQb6pFT3eLaF1A8JaUegXUakX2qE=; b=MmzPiVw94/N8GP4MBrx0ngHM6fB5+bNR233hk9HXByztg2TeGlyGyzGvN9k5d1Fz23 gREr4amY5/u9J/J79xv9RJhqRGC+v+of4sNJc0ZFCMggq6xBY/Z+dTA9MLeOZKhhhN2j OTrnuIfPx/x+szg7bGgoiGA36QogtHUxzEd0C68TCLwpKsKweAGF3PwAZl+cO47HrzZh HT7cQtboY1PittCOfcHXzdbzUZ/ZnwxGzFtJpEUDmgME0TDkaba/gwCw75MvFsmHQn59 heX39jqf9vF05Lpv7r0xBs6YlNqUYBbgq7KCzpZ9/y4UvaHrQo60GE/b42MHgZTAI9Px S+4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314885; x=1684906885; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Bq2h9X5UNDb637fCQb6pFT3eLaF1A8JaUegXUakX2qE=; b=joyah9mx9akFoWa0W5YXE1nQVre2O7y55sOWWMx2mVuj4N26gRzfs+SeHqKd+CvNZi k0bKfbIF9u8vx6z+/PTPn/7+WZUuvYy/6Ew6MmNsr+DU13hagx0KKUY/VXQ259oB+iCq b5XPWgbO6P9WSFCgoJJp6PRDmdKJACnjN9AJrqxZvCgbgQRELmFk+oJfkWu6AJCthxp/ py+68K4u8wLvIFdzEySDRsuxXUNjFx4Ry5DIK1wBd1BbOP0j0idZ+XsNiltzk7zddaC+ Tb/R49qHn4a+D0SXBf7uAJnEaRp+0aiSuZzWlLZ3eMPg8rJW5WXq1H3gD8rzxfZRd3PX OoPQ== X-Gm-Message-State: AAQBX9e4rSiT5NC3gC8wY6tNJWNkxIxnLedZ4KZXFy9IQ7NGfIQe0maK gn+Q+fJlWpRx4lszp0T2MzEiIJtA0AtnSWFzs4PHMw== X-Google-Smtp-Source: AKy350aKDnfwWYyiUwxjo7pw3dPPoA+kXHN67ng9feGDS8QyKBcGD6KeQTlRYJz3t07kiPK7GWTIpg== X-Received: by 2002:adf:f5cc:0:b0:2ff:89d6:3561 with SMTP id k12-20020adff5cc000000b002ff89d63561mr8193563wrp.64.1682314885538; Sun, 23 Apr 2023 22:41:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 33/57] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st} Date: Mon, 24 Apr 2023 06:40:41 +0100 Message-Id: <20230424054105.1579315-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315916161100003 We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index dbe4bf96b9..7e6466d3b6 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1178,7 +1178,7 @@ static const int qemu_st_opc[(MO_SIZE | MO_BSWAP) + 1= ] =3D { }; =20 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, - MemOpIdx oi, bool is_64) + MemOpIdx oi, TCGType data_type) { MemOp memop =3D get_memop(oi); tcg_insn_unit *label_ptr; @@ -1636,10 +1636,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, a0, a1, a2, false); + tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, a0, a1, a2, true); + tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); break; case INDEX_op_qemu_st_i32: tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315668; cv=none; d=zohomail.com; s=zohoarc; b=mGgj7141eV7F9MreJ+s9+xcx9BnEimkQ6KZx5Rt01E9vZ3ML7S8SzrDuZcVrIHiOqJsa1CQyi4Ejdxac3R/fCJYGXDK8esrzMTepWGtw+D93Eu/P/kzaQBs8qdgNMClvhOhz9vLNb8IGxZAO+oTio/u4WWpimyySz8I9+Fsy1tw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315668; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1e3+3125R6Ll+hm5X+IbfdxFrIfgl7VB8JipCIcUQ7c=; b=FJMYBvOhoJ1CSmtEKy1vqlmFIKbx/LhmhZYUW0pYfP3uqSOx+X4XDdZMvPGuLkzJj5ekafHLIcmvtZSMEhZ1BewJ+Vdg+XMu1KP0sjAWHqA+0pRAnzbxU2dskvwx8q33T6B9XCQpiFwD19JWCKqEZIxO/RhtYAO6h0IMGAoR3qw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315668719754.0227907558659; Sun, 23 Apr 2023 22:54:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqozc-0002H5-2H; Mon, 24 Apr 2023 01:44:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqoxr-00060s-Th for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:42:33 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqox5-0004Ez-NY for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:42:14 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-2f7c281a015so2296776f8f.1 for ; Sun, 23 Apr 2023 22:41:26 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315670890100006 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg.c | 13 +++++++++++++ tcg/tcg-ldst.c.inc | 14 -------------- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index cfd3262a4a..6f5daaee5f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -94,6 +94,19 @@ typedef struct QEMU_PACKED { DebugFrameFDEHeader fde; } DebugFrameHeader; =20 +typedef struct TCGLabelQemuLdst { + bool is_ld; /* qemu_ld: true, qemu_st: false */ + MemOpIdx oi; + TCGType type; /* result type of a load */ + TCGReg addrlo_reg; /* reg index for low word of guest virtual add= r */ + TCGReg addrhi_reg; /* reg index for high word of guest virtual ad= dr */ + TCGReg datalo_reg; /* reg index for low word to be loaded or stor= ed */ + TCGReg datahi_reg; /* reg index for high word to be loaded or sto= red */ + const tcg_insn_unit *raddr; /* addr of the next IR of qemu_ld/st IR = */ + tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */ + QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next; +} TCGLabelQemuLdst; + static void tcg_register_jit_int(const void *buf, size_t size, const void *debug_frame, size_t debug_frame_size) diff --git a/tcg/tcg-ldst.c.inc b/tcg/tcg-ldst.c.inc index 403cbb0f06..ffada04af0 100644 --- a/tcg/tcg-ldst.c.inc +++ b/tcg/tcg-ldst.c.inc @@ -20,20 +20,6 @@ * THE SOFTWARE. */ =20 -typedef struct TCGLabelQemuLdst { - bool is_ld; /* qemu_ld: true, qemu_st: false */ - MemOpIdx oi; - TCGType type; /* result type of a load */ - TCGReg addrlo_reg; /* reg index for low word of guest virtual add= r */ - TCGReg addrhi_reg; /* reg index for high word of guest virtual ad= dr */ - TCGReg datalo_reg; /* reg index for low word to be loaded or stor= ed */ - TCGReg datahi_reg; /* reg index for high word to be loaded or sto= red */ - const tcg_insn_unit *raddr; /* addr of the next IR of qemu_ld/st IR = */ - tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */ - QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next; -} TCGLabelQemuLdst; - - /* * Generate TB finalization at the end of block */ --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314886; x=1684906886; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rivgwXGbdDw6Y7e7EyPZeewGUUT+LzpYCC2kVwog6co=; b=uOJKiDEvkBKEwih1nhZNMYX82dd8aDiK69SCv/lu7yB1yxDA0RhK3lvgDBElLsZ8/K zfclDNYH+117lcoUDbu+U4qvw6eYJ4QJvh5Sv5iHpITCsHewlrX8ziel/e2Am2ME6RhG qtwubLutUbOYEcFwZJoQEEfVXCZVkNSF3zMvM6HkwhrmbYaOVSCI3uEd3XQYyQ0SZbB4 VD6GbOCvXUOIT+1XVGA3djmWkEUGGXWarKI0zeAkX8OvMTg4fAs9N26M0HqzyYk/tpPM lcPkFdQsQ95wye+BLBqEW5TtzLAD+9ufTV+oIX/0wcrTPCyBAnwxoJ7CKME2BzhQZzF5 UNIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314886; x=1684906886; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rivgwXGbdDw6Y7e7EyPZeewGUUT+LzpYCC2kVwog6co=; b=UqrS6SeFX+wl0mxsw/kj36VihjR5GeUSsdBt2HV0U2MfLlk/NXQoBEH7Zhp5kE3ejK V9BxEaZl2CAHGpUuEJRhDy87Bm9E54rIwXbbINC+yNH32IFQ8jRVkPsSR/imxEOqyDJe fpNMPia4gkigvfav68TuWaD/9KSDHOHAiyMBgu1m3fNGu4ZIMDgK6b8CGvWV3kECrCKD E/boamsPXIv7krBAhMMtIVKt4b5ss9FvQc4bkuknFh5Bucs2cjdQKdiS6m5r8sGKeDaz tB0sU3wFl6mGRS7qrPG5dZ+toUZakU0bHkuUw/zBRAN+PfJ6lYmgrjVHmu6a/mdf7jtY PsQA== X-Gm-Message-State: AAQBX9cTsEJeUJfsmoIFahKjjhe3m79vTT0Yp7d0BO9KtwBFz3Y5LnL3 inmBkRfrqK6yBqZpgMXrIlK45DhDrHKIp1xH3xybNw== X-Google-Smtp-Source: AKy350YoUkB58jfT7Id2gOJnGmcPblao0NvaphX2b2xxPshVSHE7Z8USpXrvKe9SBVf1t5PzRpDdSA== X-Received: by 2002:a5d:5004:0:b0:2f8:7cac:101a with SMTP id e4-20020a5d5004000000b002f87cac101amr7426268wrt.41.1682314886712; Sun, 23 Apr 2023 22:41:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 35/57] tcg: Replace REG_P with arg_loc_reg_p Date: Mon, 24 Apr 2023 06:40:43 +0100 Message-Id: <20230424054105.1579315-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315670875100005 An inline function is safer than a macro, and REG_P was rather too generic. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 4 ---- tcg/tcg.c | 16 +++++++++++++--- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index e542a4e9b7..0f1ba01a9a 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -58,10 +58,6 @@ typedef struct TCGCallArgumentLoc { unsigned tmp_subindex : 2; } TCGCallArgumentLoc; =20 -/* Avoid "unsigned < 0 is always false" Werror, when iarg_regs is empty. */ -#define REG_P(L) \ - ((int)(L)->arg_slot < (int)ARRAY_SIZE(tcg_target_call_iarg_regs)) - typedef struct TCGHelperInfo { void *func; const char *name; diff --git a/tcg/tcg.c b/tcg/tcg.c index 6f5daaee5f..fa28db0188 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -806,6 +806,16 @@ static void init_ffi_layouts(void) } #endif /* CONFIG_TCG_INTERPRETER */ =20 +static inline bool arg_slot_reg_p(unsigned arg_slot) +{ + /* + * Split the sizeof away from the comparison to avoid Werror from + * "unsigned < 0 is always false", when iarg_regs is empty. + */ + unsigned nreg =3D ARRAY_SIZE(tcg_target_call_iarg_regs); + return arg_slot < nreg; +} + typedef struct TCGCumulativeArgs { int arg_idx; /* tcg_gen_callN args[] */ int info_in_idx; /* TCGHelperInfo in[] */ @@ -3231,7 +3241,7 @@ liveness_pass_1(TCGContext *s) case TCG_CALL_ARG_NORMAL: case TCG_CALL_ARG_EXTEND_U: case TCG_CALL_ARG_EXTEND_S: - if (REG_P(loc)) { + if (arg_slot_reg_p(loc->arg_slot)) { *la_temp_pref(ts) =3D 0; break; } @@ -3258,7 +3268,7 @@ liveness_pass_1(TCGContext *s) case TCG_CALL_ARG_NORMAL: case TCG_CALL_ARG_EXTEND_U: case TCG_CALL_ARG_EXTEND_S: - if (REG_P(loc)) { + if (arg_slot_reg_p(loc->arg_slot)) { tcg_regset_set_reg(*la_temp_pref(ts), tcg_target_call_iarg_regs[loc->arg_slot]); } @@ -4833,7 +4843,7 @@ static void load_arg_stk(TCGContext *s, int stk_slot,= TCGTemp *ts, static void load_arg_normal(TCGContext *s, const TCGCallArgumentLoc *l, TCGTemp *ts, TCGRegSet *allocated_regs) { - if (REG_P(l)) { + if (arg_slot_reg_p(l->arg_slot)) { TCGReg reg =3D tcg_target_call_iarg_regs[l->arg_slot]; load_arg_reg(s, reg, ts, *allocated_regs); tcg_regset_set_reg(*allocated_regs, reg); --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315589; cv=none; d=zohomail.com; s=zohoarc; b=DZPqcFAGuRHnz0ims8uijP9YDX+pCMlE3CbpyNzYhFswOtDSqpNMWQSCX3hwkBlYKTGIAxaSa8ksQEGYG1lCO31r1LluJ2/5xKaXKcKQ7f/fvsed+mUlmXXwZnpplN/80PF0+P1rHgSL7WCII1ja2et10UvyeavPQgdSeY6h+tY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315589; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Yu6T1N8rjMDvjcqVloIbI64DCiKYMAX1Jvlpvr4G/Zc=; b=YRsmUCL8oNiBMjqHT3n03tA72OHhNhdAQEmMGRZQNrRbjgf8QzkBca9rcJ+g3SEhwKijMOvNptrIW4Cyw2QTgWu9PHBsapzFL+ihsZaRXMlhFzj4/4sppg2LZPtm+DlT5kekbWLLsv0t8mJ7FO6crlBWeK/0/JImsCJBaU3zzy0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315589374154.49191988433313; Sun, 23 Apr 2023 22:53:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqp05-0005jY-7O; Mon, 24 Apr 2023 01:44:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqoxw-00063w-2T for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:42:31 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqox8-0004UE-7s for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:42:19 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-3f1957e80a2so63436255e9.1 for ; Sun, 23 Apr 2023 22:41:28 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314887; x=1684906887; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Yu6T1N8rjMDvjcqVloIbI64DCiKYMAX1Jvlpvr4G/Zc=; b=unEiPoC3DGCbNlUVzWehnKJGBznQaFcD5SYtJBHW/C5O5WsSnZBkXAaxZuol/U+9js duT/VeJRTp94ans53sImsHCleGJRj5+KaX1C0LphQlmH4CpD4ZLYYGFRKytnu1m/hnGF P+5sMSXcwKFaGe5slJARNPutPo395qq0ODpPAvZDTe9+DyaBtgRxMqe9FZdMhE9reX90 M7+R9UvjijDMR7yzztgko0I6WCpQL6cAv+36Ail22WVRc7bkQVMCyOjyQADLQQ3UD2vR hUIflzKiwjkUk/8khkrvPqsrUEcYW9Zr4C2w75bUK2tt8vah0Jqzlwtm9WzeY3CdY+Bk JmUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314887; x=1684906887; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Yu6T1N8rjMDvjcqVloIbI64DCiKYMAX1Jvlpvr4G/Zc=; b=CzKtOzukftI7ua/jP6AdaqRFLcRg6vAijt7xF3lyJPSgUf6SUl6XoZuLm68upRupm2 3aKa+KvPmuxcC0AE6fveumKVYMDcFcJTAKIIhoTK1s6EfdAt5Rxk8JQctHiDP9lQFx86 CF7twiBqJxurdpW2gb79NK2nnik9q0oewhJ/2NiIaF0B5D7gn5oiSlD1DdWzHZ+mXWbC laScwaQZN9atkHaVA2tl58nvrrgYHPY1k/qDFC+WGQezTZ6JwltHOtNxB+gqfZxD78pK 5QIa6cj18fZNK6aSfIx6nQQYBhVmiOkbrAWj1ZDVhl7TyjDYuLPVHyF1Gn1KDIidB5s8 KwEQ== X-Gm-Message-State: AAQBX9fTY3vQHFCUdtTif8aHmCR0MjsC3l7wKbnxtKJ6CqQP3hzSCxlB ZJ7Lk3FiJQ9al7EZdlTVxttVX2fY6fGdeSuCt4g76Q== X-Google-Smtp-Source: AKy350ZzN1G26p5JWJJQ5xGMjLZg4qXX5Hdxtsrmt3iFNN143kS9jsijdwNkgL3mnv5LzRgIGbagpA== X-Received: by 2002:a5d:6a11:0:b0:2f6:661:c03c with SMTP id m17-20020a5d6a11000000b002f60661c03cmr9340020wru.28.1682314887384; Sun, 23 Apr 2023 22:41:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 36/57] tcg: Introduce arg_slot_stk_ofs Date: Mon, 24 Apr 2023 06:40:44 +0100 Message-Id: <20230424054105.1579315-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315590485100003 Unify all computation of argument stack offset in one function. This requires that we adjust ref_slot to be in the same units, by adding max_reg_slots during init_call_layout. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tcg.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index fa28db0188..057423c121 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -816,6 +816,15 @@ static inline bool arg_slot_reg_p(unsigned arg_slot) return arg_slot < nreg; } =20 +static inline int arg_slot_stk_ofs(unsigned arg_slot) +{ + unsigned max =3D TCG_STATIC_CALL_ARGS_SIZE / sizeof(tcg_target_long); + unsigned stk_slot =3D arg_slot - ARRAY_SIZE(tcg_target_call_iarg_regs); + + tcg_debug_assert(stk_slot < max); + return TCG_TARGET_CALL_STACK_OFFSET + stk_slot * sizeof(tcg_target_lon= g); +} + typedef struct TCGCumulativeArgs { int arg_idx; /* tcg_gen_callN args[] */ int info_in_idx; /* TCGHelperInfo in[] */ @@ -1055,6 +1064,7 @@ static void init_call_layout(TCGHelperInfo *info) } } assert(ref_base + cum.ref_slot <=3D max_stk_slots); + ref_base +=3D max_reg_slots; =20 if (ref_base !=3D 0) { for (int i =3D cum.info_in_idx - 1; i >=3D 0; --i) { @@ -4826,7 +4836,7 @@ static void load_arg_reg(TCGContext *s, TCGReg reg, T= CGTemp *ts, } } =20 -static void load_arg_stk(TCGContext *s, int stk_slot, TCGTemp *ts, +static void load_arg_stk(TCGContext *s, unsigned arg_slot, TCGTemp *ts, TCGRegSet allocated_regs) { /* @@ -4836,8 +4846,7 @@ static void load_arg_stk(TCGContext *s, int stk_slot,= TCGTemp *ts, */ temp_load(s, ts, tcg_target_available_regs[ts->type], allocated_regs, = 0); tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, - TCG_TARGET_CALL_STACK_OFFSET + - stk_slot * sizeof(tcg_target_long)); + arg_slot_stk_ofs(arg_slot)); } =20 static void load_arg_normal(TCGContext *s, const TCGCallArgumentLoc *l, @@ -4848,18 +4857,16 @@ static void load_arg_normal(TCGContext *s, const TC= GCallArgumentLoc *l, load_arg_reg(s, reg, ts, *allocated_regs); tcg_regset_set_reg(*allocated_regs, reg); } else { - load_arg_stk(s, l->arg_slot - ARRAY_SIZE(tcg_target_call_iarg_regs= ), - ts, *allocated_regs); + load_arg_stk(s, l->arg_slot, ts, *allocated_regs); } } =20 -static void load_arg_ref(TCGContext *s, int arg_slot, TCGReg ref_base, +static void load_arg_ref(TCGContext *s, unsigned arg_slot, TCGReg ref_base, intptr_t ref_off, TCGRegSet *allocated_regs) { TCGReg reg; - int stk_slot =3D arg_slot - ARRAY_SIZE(tcg_target_call_iarg_regs); =20 - if (stk_slot < 0) { + if (arg_slot_reg_p(arg_slot)) { reg =3D tcg_target_call_iarg_regs[arg_slot]; tcg_reg_free(s, reg, *allocated_regs); tcg_out_addi_ptr(s, reg, ref_base, ref_off); @@ -4869,8 +4876,7 @@ static void load_arg_ref(TCGContext *s, int arg_slot,= TCGReg ref_base, *allocated_regs, 0, false); tcg_out_addi_ptr(s, reg, ref_base, ref_off); tcg_out_st(s, TCG_TYPE_PTR, reg, TCG_REG_CALL_STACK, - TCG_TARGET_CALL_STACK_OFFSET - + stk_slot * sizeof(tcg_target_long)); + arg_slot_stk_ofs(arg_slot)); } } =20 @@ -4900,8 +4906,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *= op) case TCG_CALL_ARG_BY_REF: load_arg_stk(s, loc->ref_slot, ts, allocated_regs); load_arg_ref(s, loc->arg_slot, TCG_REG_CALL_STACK, - TCG_TARGET_CALL_STACK_OFFSET - + loc->ref_slot * sizeof(tcg_target_long), + arg_slot_stk_ofs(loc->ref_slot), &allocated_regs); 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[46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314888; x=1684906888; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RzQZ5WVAoEKvcmnzgqGk5zASE/mhxboQtmOP6HVA4UQ=; b=inprkCKQ2eq4l4tV+Zf9One1wQTA7s6dXhx/w/lCK20zineyln5fst2bgj18TcYpu5 DRZFzARzRthcIjn6y7n8iaeHogPe/fcjWZmFSso9w9S5k1twhOJagetX+7meIYl6D8XE AlZ52bb3Zo0x1iVd+u9VJ4uc23a0/FYOYyBkVwuqwpI08d+NagZ0L/uPoUPGLiCNgFo+ IDQ/k45mKeJ58D6r9SxtaaKnOQaJaeZrxVrEMjIqm+pbTIsI7qqxkiqxBeWF4/EP9Yp2 vJqVD7pzanXCQVhVHw8Y7qB1XzzexpsWVdeG1a9x0cjgLZaSekzdGfYWxmVLU83ot2aq T3kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314888; x=1684906888; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RzQZ5WVAoEKvcmnzgqGk5zASE/mhxboQtmOP6HVA4UQ=; b=KNq8wsq8Uu+nOOjhyb1xbaVj5UKZABRM6Pbh3lUrUVl8fkY2RBLbw0kFx6G5AEOIyx c+NOCSeDh3kVDmNrEU3isgpFj14CBUcdslNwWFDDGd9o10qme0Iaa+/+8F+Z0/1S7RK1 WYUfSwF7xgmCcPzWZxRBxCtFKvCsYd9mA/2cTHWUfYKfnNJtimFsW5/1VwXB+gziEI/b 0JjeHL3FCp3QfytbchQInx6K6Ff35J7obMCr9jLvk77p+18vS9WGP+9KiuMbfjoRUeug 3SPTt6Tlu4M8f7U6jlYu4W4hsuWhcjD7lQNmiFst5mY+A8ys1zgJwAAx55qv5AFkCJeR di5w== X-Gm-Message-State: AAQBX9duPy8+rusmuxaIgkIUvYGbkIrVVF/SyGNE5fgMgvalrm0oZPc3 v//SWFgohABDGnhRiXvsCYkA444JbFh+OrPS/DcRMQ== X-Google-Smtp-Source: AKy350Z1bBGzjELkWtJIkCnJFsq+DqBmKNKI2FB8m5q8xyb12Cc+aXxZCfVqu4QR7aChCx6q47N/Kg== X-Received: by 2002:a5d:6e0a:0:b0:304:7929:470d with SMTP id h10-20020a5d6e0a000000b003047929470dmr1973859wrz.53.1682314887942; Sun, 23 Apr 2023 22:41:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 37/57] tcg: Widen helper_*_st[bw]_mmu val arguments Date: Mon, 24 Apr 2023 06:40:45 +0100 Message-Id: <20230424054105.1579315-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x429.google.com X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315590502100004 While the old type was correct in the ideal sense, some ABIs require the argument to be zero-extended. Using uint32_t for all such values is a decent compromise. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 10 +++++++--- accel/tcg/cputlb.c | 6 +++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h index 2ba22bd5fe..684e394b06 100644 --- a/include/tcg/tcg-ldst.h +++ b/include/tcg/tcg-ldst.h @@ -55,15 +55,19 @@ tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, = target_ulong addr, tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, uintptr_t retaddr); =20 -void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, +/* + * Value extended to at least uint32_t, so that some ABIs do not require + * zero-extension from uint8_t or uint16_t. + */ +void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr); -void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, +void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr); void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr); void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr); -void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, +void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr); void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e984a98dc4..665c41fc12 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2503,7 +2503,7 @@ full_stb_mmu(CPUArchState *env, target_ulong addr, ui= nt64_t val, store_helper(env, addr, val, oi, retaddr, MO_UB); } =20 -void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, +void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { full_stb_mmu(env, addr, val, oi, retaddr); @@ -2516,7 +2516,7 @@ static void full_le_stw_mmu(CPUArchState *env, target= _ulong addr, uint64_t val, store_helper(env, addr, val, oi, retaddr, MO_LEUW); } =20 -void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, +void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { full_le_stw_mmu(env, addr, val, oi, retaddr); @@ -2529,7 +2529,7 @@ static void full_be_stw_mmu(CPUArchState *env, target= _ulong addr, uint64_t val, store_helper(env, addr, val, oi, retaddr, MO_BEUW); } =20 -void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, +void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { full_be_stw_mmu(env, addr, val, oi, retaddr); --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314888; x=1684906888; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h6BFFJQsnYJf+DuNKwmWkOsSgqkNtn/h0gMQ0w3QpZI=; b=tvJAXqWxP9uw2LAgMdA5rEVDKvXEY5LqCEaubcOI1c4U8i2zISlSVun36nA0qh6KHy 1ykxu3zY+J252Z75M0r7pYb1UI50NmZhz/ofauO30+LGEqAYyW5M06JBlY3wj06Dzxln xIdC0W9gcfRkiGuxA9wvvKLsuo6aTAfCfDNCYfVjlYpY1V9JnzAo/x5VsNlOU1wuINBD PQxQ6i8sHwk+r1MJ/it1uaUAckTXh69f4lZ5ifIjY7f+b0j3XfY1xU1zACl1kbpVdzin VUpXvw3t8Sl3DDBUuVt3s7pbOGnx9RNyYxyHMV7wM96iFlUMTkQU1CVFekbTS2X1MQs0 c+cQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314888; x=1684906888; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h6BFFJQsnYJf+DuNKwmWkOsSgqkNtn/h0gMQ0w3QpZI=; b=LsFELjZ6bUeIWodK9riDRlHMutNmjT42NxfuvNa3Kru+ozxHeUamb2WnTpVbbRcGuP 2yu7OiHjnpVCG4/sZYuUwtk2Lw2sW3dvbp72JHjFL43hf6Df8holX8Y27o928c6haudz Z3/6IFC0D0exer0ysPeHua1KHVpm8jnOObTokAWtUYfZyh+9JU+j6wdT+Fz6zZJIHWyC iOPd2rzKypxxOZAVt4b1joDvgynBp/5rpIBGBkkU55ijiZgHUIMxcdly3vmidxGsXAvZ SHoOuzzZ7YOSqf3cqaA+MOc6b+D+BhepDMJDEN2JXD6h4WgBlrvNnufuQCuILuc388Bn 6vUQ== X-Gm-Message-State: AAQBX9dowjyzjvxarczXv++DHExASqi4ZP3nq5z9HCFyEA/OXosNfK1e Uh4rKG4JLSEtdMMELgtch4MKW3mF+F1Caj/HMtDfWw== X-Google-Smtp-Source: AKy350aMB2ex1YxknozcBFBr/r+Ew3/ZQo+lrEa+xYc+9HmUNYJfdj6NW7pbM0MzhbJ8e9yJKfya9w== X-Received: by 2002:adf:e711:0:b0:2ef:84c:a4bc with SMTP id c17-20020adfe711000000b002ef084ca4bcmr13177748wrm.19.1682314888541; Sun, 23 Apr 2023 22:41:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 38/57] tcg: Add routines for calling slow-path helpers Date: Mon, 24 Apr 2023 06:40:46 +0100 Message-Id: <20230424054105.1579315-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315532710100007 Content-Type: text/plain; charset="utf-8" Add tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. These and their subroutines use the existing knowledge of the host function call abi to load the function call arguments and return results. These will be used to simplify the backends in turn. Signed-off-by: Richard Henderson --- tcg/tcg.c | 461 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 458 insertions(+), 3 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 057423c121..610df88626 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -181,6 +181,22 @@ static bool tcg_target_const_match(int64_t val, TCGTyp= e type, int ct); static int tcg_out_ldst_finalize(TCGContext *s); #endif =20 +typedef struct TCGLdstHelperParam { + TCGReg (*ra_gen)(TCGContext *s, const TCGLabelQemuLdst *l, int arg_reg= ); + unsigned ntmp; + int tmp[3]; +} TCGLdstHelperParam; + +static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *= l, + const TCGLdstHelperParam *p) + __attribute__((unused)); +static void tcg_out_ld_helper_ret(TCGContext *s, const TCGLabelQemuLdst *l, + bool load_sign, const TCGLdstHelperParam= *p) + __attribute__((unused)); +static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *= l, + const TCGLdstHelperParam *p) + __attribute__((unused)); + TCGContext tcg_init_ctx; __thread TCGContext *tcg_ctx; =20 @@ -459,9 +475,8 @@ static void tcg_out_movext1(TCGContext *s, const TCGMov= Extend *i) * between the sources and destinations. */ =20 -static void __attribute__((unused)) -tcg_out_movext2(TCGContext *s, const TCGMovExtend *i1, - const TCGMovExtend *i2, int scratch) +static void tcg_out_movext2(TCGContext *s, const TCGMovExtend *i1, + const TCGMovExtend *i2, int scratch) { TCGReg src1 =3D i1->src; TCGReg src2 =3D i2->src; @@ -715,6 +730,50 @@ static TCGHelperInfo all_helpers[] =3D { }; static GHashTable *helper_table; =20 +#if TCG_TARGET_REG_BITS =3D=3D 32 +# define dh_typecode_ttl dh_typecode_i32 +#else +# define dh_typecode_ttl dh_typecode_i64 +#endif + +static TCGHelperInfo info_helper_ld32_mmu =3D { + .flags =3D TCG_CALL_NO_WG, + .typemask =3D dh_typemask(ttl, 0) /* return tcg_target_ulong */ + | dh_typemask(env, 1) + | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i32, 3) /* unsigned oi */ + | dh_typemask(ptr, 4) /* uintptr_t ra */ +}; + +static TCGHelperInfo info_helper_ld64_mmu =3D { + .flags =3D TCG_CALL_NO_WG, + .typemask =3D dh_typemask(i64, 0) /* return uint64_t */ + | dh_typemask(env, 1) + | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i32, 3) /* unsigned oi */ + | dh_typemask(ptr, 4) /* uintptr_t ra */ +}; + +static TCGHelperInfo info_helper_st32_mmu =3D { + .flags =3D TCG_CALL_NO_WG, + .typemask =3D dh_typemask(void, 0) + | dh_typemask(env, 1) + | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i32, 3) /* uint32_t data */ + | dh_typemask(i32, 4) /* unsigned oi */ + | dh_typemask(ptr, 5) /* uintptr_t ra */ +}; + +static TCGHelperInfo info_helper_st64_mmu =3D { + .flags =3D TCG_CALL_NO_WG, + .typemask =3D dh_typemask(void, 0) + | dh_typemask(env, 1) + | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i64, 3) /* uint64_t data */ + | dh_typemask(i32, 4) /* unsigned oi */ + | dh_typemask(ptr, 5) /* uintptr_t ra */ +}; + #ifdef CONFIG_TCG_INTERPRETER static ffi_type *typecode_to_ffi(int argmask) { @@ -1126,6 +1185,11 @@ static void tcg_context_init(unsigned max_cpus) (gpointer)&all_helpers[i]); } =20 + init_call_layout(&info_helper_ld32_mmu); + init_call_layout(&info_helper_ld64_mmu); + init_call_layout(&info_helper_st32_mmu); + init_call_layout(&info_helper_st64_mmu); + #ifdef CONFIG_TCG_INTERPRETER init_ffi_layouts(); #endif @@ -5011,6 +5075,397 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp= *op) } } =20 +/* + * Similarly for qemu_ld/st slow path helpers. + * We must re-implement tcg_gen_callN and tcg_reg_alloc_call simultaneousl= y, + * using only the provided backend tcg_out_* functions. + */ + +static int tcg_out_helper_stk_ofs(TCGType type, unsigned slot) +{ + int ofs =3D arg_slot_stk_ofs(slot); + + /* + * Each stack slot is TCG_TARGET_LONG_BITS. If the host does not + * require extension to uint64_t, adjust the address for uint32_t. + */ + if (HOST_BIG_ENDIAN && + TCG_TARGET_REG_BITS =3D=3D 64 && + type =3D=3D TCG_TYPE_I32) { + ofs +=3D 4; + } + return ofs; +} + +static void tcg_out_helper_load_regs(TCGContext *s, + unsigned nmov, TCGMovExtend *mov, + unsigned ntmp, const int *tmp) +{ + switch (nmov) { + default: + /* The backend must have provided enough temps for the worst case.= */ + tcg_debug_assert(ntmp + 1 >=3D nmov); + + for (unsigned i =3D nmov - 1; i >=3D 2; --i) { + TCGReg dst =3D mov[i].dst; + + for (unsigned j =3D 0; j < i; ++j) { + if (dst =3D=3D mov[j].src) { + /* + * Conflict. + * Copy the source to a temporary, recurse for the + * remaining moves, perform the extension from our + * scratch on the way out. + */ + TCGReg scratch =3D tmp[--ntmp]; + tcg_out_mov(s, mov[i].src_type, scratch, mov[i].src); + mov[i].src =3D scratch; + + tcg_out_helper_load_regs(s, i, mov, ntmp, tmp); + tcg_out_movext1(s, &mov[i]); + return; + } + } + + /* No conflicts: perform this move and continue. */ + tcg_out_movext1(s, &mov[i]); + } + /* fall through for the final two moves */ + + case 2: + tcg_out_movext2(s, mov, mov + 1, ntmp ? tmp[0] : -1); + return; + case 1: + tcg_out_movext1(s, mov); + return; + case 0: + g_assert_not_reached(); + } +} + +static void tcg_out_helper_load_slots(TCGContext *s, + unsigned nmov, TCGMovExtend *mov, + unsigned ntmp, const int *tmp) +{ + unsigned i; + + /* + * Start from the end, storing to the stack first. + * This frees those registers, so we need not consider overlap. + */ + for (i =3D nmov; i-- > 0; ) { + unsigned slot =3D mov[i].dst; + + if (arg_slot_reg_p(slot)) { + goto found_reg; + } + + TCGReg src =3D mov[i].src; + TCGType dst_type =3D mov[i].dst_type; + MemOp dst_mo =3D dst_type =3D=3D TCG_TYPE_I32 ? MO_32 : MO_64; + + /* The argument is going onto the stack; extend into scratch. */ + if ((mov[i].src_ext & MO_SIZE) !=3D dst_mo) { + tcg_debug_assert(ntmp !=3D 0); + mov[i].dst =3D src =3D tmp[0]; + tcg_out_movext1(s, &mov[i]); + } + + tcg_out_st(s, dst_type, src, TCG_REG_CALL_STACK, + tcg_out_helper_stk_ofs(dst_type, slot)); + } + return; + + found_reg: + /* + * The remaining arguments are in registers. + * Convert slot numbers to argument registers. + */ + nmov =3D i + 1; + for (i =3D 0; i < nmov; ++i) { + mov[i].dst =3D tcg_target_call_iarg_regs[mov[i].dst]; + } + tcg_out_helper_load_regs(s, nmov, mov, ntmp, tmp); +} + +static unsigned tcg_out_helper_add_mov(TCGMovExtend *mov, + const TCGCallArgumentLoc *loc, + TCGType dst_type, TCGType src_type, + TCGReg lo, TCGReg hi) +{ + if (dst_type <=3D TCG_TYPE_REG) { + MemOp src_ext; + + switch (loc->kind) { + case TCG_CALL_ARG_NORMAL: + src_ext =3D src_type =3D=3D TCG_TYPE_I32 ? MO_32 : MO_64; + break; + case TCG_CALL_ARG_EXTEND_U: + dst_type =3D TCG_TYPE_REG; + src_ext =3D MO_UL; + break; + case TCG_CALL_ARG_EXTEND_S: + dst_type =3D TCG_TYPE_REG; + src_ext =3D MO_SL; + break; + default: + g_assert_not_reached(); + } + + mov[0].dst =3D loc->arg_slot; + mov[0].dst_type =3D dst_type; + mov[0].src =3D lo; + mov[0].src_type =3D src_type; + mov[0].src_ext =3D src_ext; + return 1; + } + + assert(TCG_TARGET_REG_BITS =3D=3D 32); + + mov[0].dst =3D loc[HOST_BIG_ENDIAN].arg_slot; + mov[0].src =3D lo; + mov[0].dst_type =3D TCG_TYPE_I32; + mov[0].src_type =3D TCG_TYPE_I32; + mov[0].src_ext =3D MO_32; + + mov[1].dst =3D loc[!HOST_BIG_ENDIAN].arg_slot; + mov[1].src =3D hi; + mov[1].dst_type =3D TCG_TYPE_I32; + mov[1].src_type =3D TCG_TYPE_I32; + mov[1].src_ext =3D MO_32; + + return 2; +} + +static void tcg_out_helper_load_common_args(TCGContext *s, + const TCGLabelQemuLdst *ldst, + const TCGLdstHelperParam *parm, + const TCGHelperInfo *info, + unsigned next_arg) +{ + const TCGCallArgumentLoc *loc =3D &info->in[0]; + TCGType type; + unsigned slot; + tcg_target_ulong imm; + + /* + * Handle env, which is always first. + */ + TCGMovExtend env_mov =3D { + .dst =3D loc->arg_slot, + .src =3D TCG_AREG0, + .dst_type =3D TCG_TYPE_PTR, + .src_type =3D TCG_TYPE_PTR, + .src_ext =3D sizeof(void *) =3D=3D 4 ? MO_32 : MO_64 + }; + tcg_out_helper_load_slots(s, 1, &env_mov, parm->ntmp, parm->tmp); + + /* + * Handle oi. + */ + imm =3D ldst->oi; + loc =3D &info->in[next_arg]; + type =3D TCG_TYPE_I32; + switch (loc->kind) { + case TCG_CALL_ARG_NORMAL: + break; + case TCG_CALL_ARG_EXTEND_U: + case TCG_CALL_ARG_EXTEND_S: + /* No extension required for MemOpIdx. */ + tcg_debug_assert(imm <=3D INT32_MAX); + type =3D TCG_TYPE_REG; + break; + default: + g_assert_not_reached(); + } + slot =3D loc->arg_slot; + + if (arg_slot_reg_p(slot)) { + tcg_out_movi(s, type, tcg_target_call_iarg_regs[slot], imm); + } else { + int ofs =3D tcg_out_helper_stk_ofs(type, slot); + if (!tcg_out_sti(s, type, imm, TCG_REG_CALL_STACK, ofs)) { + tcg_debug_assert(parm->ntmp !=3D 0); + tcg_out_movi(s, type, parm->tmp[0], imm); + tcg_out_st(s, type, parm->tmp[0], TCG_REG_CALL_STACK, ofs); + } + } + next_arg++; + + /* + * Handle ra. + */ + imm =3D (uintptr_t)ldst->raddr; + loc =3D &info->in[next_arg]; + type =3D TCG_TYPE_PTR; + slot =3D loc->arg_slot; + + if (arg_slot_reg_p(slot)) { + TCGReg dst =3D tcg_target_call_iarg_regs[slot]; + + if (parm->ra_gen) { + tcg_out_mov(s, type, dst, parm->ra_gen(s, ldst, dst)); + } else { + tcg_out_movi(s, type, dst, imm); + } + } else { + int ofs =3D tcg_out_helper_stk_ofs(type, slot); + TCGReg ra_reg; + + if (parm->ra_gen) { + ra_reg =3D parm->ra_gen(s, ldst, -1); + } else if (tcg_out_sti(s, type, imm, TCG_REG_CALL_STACK, ofs)) { + return; + } else { + tcg_debug_assert(parm->ntmp !=3D 0); + ra_reg =3D parm->tmp[0]; + tcg_out_movi(s, type, ra_reg, imm); + } + tcg_out_st(s, type, ra_reg, TCG_REG_CALL_STACK, ofs); + } +} + +static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *= ldst, + const TCGLdstHelperParam *parm) +{ + const TCGHelperInfo *info; + const TCGCallArgumentLoc *loc; + TCGMovExtend mov[2]; + unsigned next_arg, nmov; + MemOp mop =3D get_memop(ldst->oi); + + switch (mop & MO_SIZE) { + case MO_8: + case MO_16: + case MO_32: + info =3D &info_helper_ld32_mmu; + break; + case MO_64: + info =3D &info_helper_ld64_mmu; + break; + default: + g_assert_not_reached(); + } + + /* Defer env argument. */ + next_arg =3D 1; + + loc =3D &info->in[next_arg]; + nmov =3D tcg_out_helper_add_mov(mov, loc, TCG_TYPE_TL, TCG_TYPE_TL, + ldst->addrlo_reg, ldst->addrhi_reg); + next_arg +=3D nmov; + + tcg_out_helper_load_slots(s, nmov, mov, parm->ntmp, parm->tmp); + + /* No special attention for 32 and 64-bit return values. */ + tcg_debug_assert(info->out_kind =3D=3D TCG_CALL_RET_NORMAL); + + tcg_out_helper_load_common_args(s, ldst, parm, info, next_arg); +} + +static void tcg_out_ld_helper_ret(TCGContext *s, const TCGLabelQemuLdst *l= dst, + bool load_sign, + const TCGLdstHelperParam *parm) +{ + TCGMovExtend mov[2]; + + if (ldst->type <=3D TCG_TYPE_REG) { + MemOp mop =3D get_memop(ldst->oi); + + mov[0].dst =3D ldst->datalo_reg; + mov[0].src =3D tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, 0); + mov[0].dst_type =3D ldst->type; + mov[0].src_type =3D TCG_TYPE_REG; + + /* + * If load_sign, then we allowed the helper to perform the + * appropriate sign extension to tcg_target_ulong, and all + * we need now is a plain move. + * + * If they do not, then we expect the relevant extension + * instruction to be no more expensive than a move, and + * we thus save the icache etc by only using one of two + * helper functions. + */ + if (load_sign || !(mop & MO_SIGN)) { + if (TCG_TARGET_REG_BITS =3D=3D 32 || ldst->type =3D=3D TCG_TYP= E_I32) { + mov[0].src_ext =3D MO_32; + } else { + mov[0].src_ext =3D MO_64; + } + } else { + mov[0].src_ext =3D mop & MO_SSIZE; + } + tcg_out_movext1(s, mov); + } else { + assert(TCG_TARGET_REG_BITS =3D=3D 32); + + mov[0].dst =3D ldst->datalo_reg; + mov[0].src =3D + tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, HOST_BIG_ENDIAN); + mov[0].dst_type =3D TCG_TYPE_I32; + mov[0].src_type =3D TCG_TYPE_I32; + mov[0].src_ext =3D MO_32; + + mov[1].dst =3D ldst->datahi_reg; + mov[1].src =3D + tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, !HOST_BIG_ENDIAN= ); + mov[1].dst_type =3D TCG_TYPE_REG; + mov[1].src_type =3D TCG_TYPE_REG; + mov[1].src_ext =3D MO_32; + + tcg_out_movext2(s, mov, mov + 1, parm->ntmp ? parm->tmp[0] : -1); + } +} + +static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *= ldst, + const TCGLdstHelperParam *parm) +{ + const TCGHelperInfo *info; + const TCGCallArgumentLoc *loc; + TCGMovExtend mov[4]; + TCGType data_type; + unsigned next_arg, nmov, n; + MemOp mop =3D get_memop(ldst->oi); + + switch (mop & MO_SIZE) { + case MO_8: + case MO_16: + case MO_32: + info =3D &info_helper_st32_mmu; + data_type =3D TCG_TYPE_I32; + break; + case MO_64: + info =3D &info_helper_st64_mmu; + data_type =3D TCG_TYPE_I64; + break; + default: + g_assert_not_reached(); + } + + /* Defer env argument. */ + next_arg =3D 1; + nmov =3D 0; + + /* Handle addr argument. */ + loc =3D &info->in[next_arg]; + n =3D tcg_out_helper_add_mov(mov, loc, TCG_TYPE_TL, TCG_TYPE_TL, + ldst->addrlo_reg, ldst->addrhi_reg); + next_arg +=3D n; + nmov +=3D n; + + /* Handle data argument. */ + loc =3D &info->in[next_arg]; + n =3D tcg_out_helper_add_mov(mov + nmov, loc, data_type, ldst->type, + ldst->datalo_reg, ldst->datahi_reg); + next_arg +=3D n; + nmov +=3D n; + tcg_debug_assert(nmov <=3D ARRAY_SIZE(mov)); + + tcg_out_helper_load_slots(s, nmov, mov, parm->ntmp, parm->tmp); + tcg_out_helper_load_common_args(s, ldst, parm, info, next_arg); +} + #ifdef CONFIG_PROFILER =20 /* avoid copy/paste errors */ --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315769; cv=none; d=zohomail.com; s=zohoarc; b=I2IBT2A8UQXfI8DA/zRtS8CqNBDMicvLZceAUT24WGnhkuxnPxvo6uRs85IDNhwrQEdUMQuGfdbRwjKjv1u0DzTSbEUnkOkiisw4MWkuqqGvF4Y12nFZbMhTxSfY8JPHAHSGDz3bk/vbP7gespFenojzKGhFo2YVKGPsqo1RUg8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315769; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JmuglVw1T6vmkIujcut/4t9lRSs3+xsqbhm0pfkrC4g=; b=NEl5mT68nNcRzMNRA/zXGvwjhb0xeGfW9PrrhWsR+9Zip9g900RwyTBGiDhy2NF03jG5imCwVLxiy72s1sB+0pKBLDWIjYv08/cTh+5fPsT0UsZ40AWXX5kvctgUpiwUAMDlOi2EvvupRWvSBNAa9WjqPClf/tLMT1DJKMKTrko= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315769251768.3780543631445; Sun, 23 Apr 2023 22:56:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqp1A-0006bO-Pu; Mon, 24 Apr 2023 01:45:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqoy0-00068i-5L for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:42:33 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqox8-0004Ed-Rz for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:42:23 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-2fc3f1d6f8cso2400346f8f.3 for ; Sun, 23 Apr 2023 22:41:29 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id j22-20020a5d6e56000000b002fbb285b01fsm9997852wrz.25.2023.04.23.22.41.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:41:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682314889; x=1684906889; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JmuglVw1T6vmkIujcut/4t9lRSs3+xsqbhm0pfkrC4g=; b=UTGeOm/UOzcskyC3HRvxpplPe4n8zjDYW1TtKT9yxEq/yK1oyz+MYfWpkvA2dwRejC xewaDifiPbDEaRUEHGk2fzNdu/zVVaKzJzMRMml08mEwqPs2QUztW9hhoM+hCu0jKiXM 1rpcvXw+yTH0PmJzGJGAixZa4SIP0fsH2Z7WBQhrmisDAQ1YaEGpt1/4pY+sb0GbigZQ AYoCv7yHmY3xbtDJabdzTNYF/NqrSts9pIdEIkcxl79d3NbX3Hn2Vx87emuU1KMERv4P TEePJz6V6JcVjWKm7h9mdgPgYJs8pCQVlRkcW1of0HJFGbOHbvHnN6M8l2YiUZPS/AIq JvNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682314889; x=1684906889; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JmuglVw1T6vmkIujcut/4t9lRSs3+xsqbhm0pfkrC4g=; b=N/0lhUXb1/V1wII+mMg/+w68c/rK66y+0Kl2r17mqiTYz5pIh9kgeEWgM5f6z90Q2L sIM7UmQeqmIwdywXRZQxR8EDgl45JzU4Q77bvx2WZJqS4giQpGysty6QjwPhtOi9sKzR a+TY0QnMBYIaupxaVS3mM4SMdJxdq1Jbu0srgSgyHShWvHTsUjw+rlBxjSMlgY44wVQ6 0NeFi8Saqkd6CRSISBeSGybzsr7WMJPZlAjJRcgZAUNuB4KfPJwFD/QpUVWQysO7V3nm 4E4b7EMdLqXpg9tVaJexuXVf6GGug3iGswNMoqERzSpVuC9SSDAyhjM1SFJcOTUtNpel zjjg== X-Gm-Message-State: AAQBX9df1wbMXHFEsaZQLe+aBDwYOMTeGYVx7d+0sGxtXahIHIxWRqO2 6ya6tAIQj19NWRkZ+jXYA9dqDK3LLUvWPspjP9xdRg== X-Google-Smtp-Source: AKy350YKyXZpkOjFq+0rtnTxsEL9LCE1XWqBzy3LhH48RDdoPIu8jS838/FSjQ12piobVz5p3LVbog== X-Received: by 2002:a5d:6683:0:b0:2fd:e026:5738 with SMTP id l3-20020a5d6683000000b002fde0265738mr8943789wru.23.1682314889072; Sun, 23 Apr 2023 22:41:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 39/57] tcg/i386: Convert tcg_out_qemu_ld_slow_path Date: Mon, 24 Apr 2023 06:40:47 +0100 Message-Id: <20230424054105.1579315-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315771287100002 Content-Type: text/plain; charset="utf-8" Use tcg_out_ld_helper_args and tcg_out_ld_helper_ret. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 71 +++++++++++++++------------------------ 1 file changed, 28 insertions(+), 43 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index fabb03cd74..4f3a7c7a6d 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1804,13 +1804,37 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_B= SWAP) + 1] =3D { [MO_BEUQ] =3D helper_be_stq_mmu, }; =20 +/* + * Because i686 has no register parameters and because x86_64 has xchg + * to handle addr/data register overlap, we have placed all input arguments + * before we need might need a scratch reg. + * + * Even then, a scratch is only needed for l->raddr. Rather than expose + * a general-purpose scratch when we don't actually know it's available, + * use the ra_gen hook to load into RAX if needed. + */ +#if TCG_TARGET_REG_BITS =3D=3D 64 +static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int ar= g) +{ + if (arg < 0) { + arg =3D TCG_REG_RAX; + } + tcg_out_movi(s, TCG_TYPE_PTR, arg, (uintptr_t)l->raddr); + return arg; +} +static const TCGLdstHelperParam ldst_helper_param =3D { + .ra_gen =3D ldst_ra_gen +}; +#else +static const TCGLdstHelperParam ldst_helper_param =3D { }; +#endif + /* * Generate code for the slow path for a load at the end of block */ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(l->oi); tcg_insn_unit **label_ptr =3D &l->label_ptr[0]; =20 /* resolve label address */ @@ -1819,49 +1843,10 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); } =20 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - int ofs =3D 0; - - tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); - ofs +=3D 4; - - tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - } - - tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs); - ofs +=3D 4; - - tcg_out_sti(s, TCG_TYPE_PTR, (uintptr_t)l->raddr, TCG_REG_ESP, ofs= ); - } else { - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); - tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], - l->addrlo_reg); - tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], oi); - tcg_out_movi(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[3], - (uintptr_t)l->raddr); - } - + tcg_out_ld_helper_args(s, l, &ldst_helper_param); tcg_out_branch(s, 1, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param); =20 - if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { - TCGMovExtend ext[2] =3D { - { .dst =3D l->datalo_reg, .dst_type =3D TCG_TYPE_I32, - .src =3D TCG_REG_EAX, .src_type =3D TCG_TYPE_I32, .src_ext = =3D MO_UL }, - { .dst =3D l->datahi_reg, .dst_type =3D TCG_TYPE_I32, - .src =3D TCG_REG_EDX, .src_type =3D TCG_TYPE_I32, .src_ext = =3D MO_UL }, - }; - tcg_out_movext2(s, &ext[0], &ext[1], -1); - } else { - tcg_out_movext(s, l->type, l->datalo_reg, - TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_EAX); - } - - /* Jump to the code corresponding to next IR of qemu_st */ tcg_out_jmp(s, l->raddr); return true; } --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315802; cv=none; d=zohomail.com; s=zohoarc; b=eZzsL1SNI0Ob5QO6t6iz45YWiDQCJfGnIjsv3igt5Wc5DDTI47ISN9r7SsIJ7t6f5BTLO23vDlkZYo6+82YHWhFhoz1ZjZ9AugXxEbKVSiYhguyPfk/qdK2S5aXGPK5QMwUUCn+a+FiKb7Ak1lCV/xALPQBsWDAN26jqM38XbXM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315802; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[46.193.226.34]) by smtp.gmail.com with ESMTPSA id u6-20020adff886000000b002f7780eee10sm9986693wrp.59.2023.04.23.22.44.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:44:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682315070; x=1684907070; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DyXO1yYcoTiYsNUxk6ECTx6lZnwHVIRHDFe68cV9zdA=; b=YZBvyGuOvS/vA+39E37lzl8UtM30hnbyl0tDA4NFVjtC5Imy4JYHSkLQW6sgwTlWWu t5vpH0qwQ8kgQMTaRmjvrxzNWROPtXRdDoNvRpSmOYDkwAXXIIosXCEc5zT3tapMshVE aafIzzWBXiePhENeOdtVjkhvw/+HukVYAThazgZzbek6OcqW/42w+oIyrQJNRUk7VFI+ /NSo2zRcFQInRHCWZscT4QClcrsbiEaHQrTMkvpRkDYn8S6Eb/rylGUrVFcbn4UO637Q spcNOK7f4RCZvB1coyDPf6u8YQ+mfYXi2CKt/2xoXItJXHJOjvYG6KIID2zSLeic+0SW 2ECA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682315070; x=1684907070; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DyXO1yYcoTiYsNUxk6ECTx6lZnwHVIRHDFe68cV9zdA=; b=PnmrNrK8uK9/HMklg0iOrXFgQYYGOz53Lv3zj8TXX1FW3ksVKHTTlolXrHfbKQupA9 k0z8aoIabF/Er1AWznxYr1aO1W5iT8nM1MGS7i4azog++KZjWS2svn/1fyvId04BXwt5 BIu8xXb6XqINtDv206Nt3cI2WL9olfjh5RnaaovsQVz7yAnfYjobZXyjQtngLyTHTBpG DFnIEBiq3y40UXv/i2tYVJo0Rh2PVr4RPzG0JFjr8XT+C+JOxQQmVpWnevXeb4EKIKUa 08JOQLU3yaTtYtBhre9B5YzXWEmVn7NCLCsph9cOUb6tSIAiYbcxmkcY2ZDztK2MmXwa 7Dmw== X-Gm-Message-State: AAQBX9fh7XwaHJ/0gTliQizK2PaChBIe/fcqoDpIYLuq6VTY8WrBqOW6 JPGbh3yuvnPV5c7T+5wVKnsE+0DtMdNjgGNG6uqL8w== X-Google-Smtp-Source: AKy350aQouMkGToA8Z1zbs0X+IH7dLoh8VRABiD0FHGqnV7UCqkWvsjp02Fj5AsEvpUkRI0NKL0lyA== X-Received: by 2002:adf:f009:0:b0:2ee:f77f:3d02 with SMTP id j9-20020adff009000000b002eef77f3d02mr8000129wro.0.1682315069858; Sun, 23 Apr 2023 22:44:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 40/57] tcg/i386: Convert tcg_out_qemu_st_slow_path Date: Mon, 24 Apr 2023 06:40:48 +0100 Message-Id: <20230424054105.1579315-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315804057100007 Content-Type: text/plain; charset="utf-8" Use tcg_out_st_helper_args. This eliminates the use of a tail call to the store helper. This may or may not be an improvement, depending on the call/return branch prediction of the host microarchitecture. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 57 +++------------------------------------ 1 file changed, 4 insertions(+), 53 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 4f3a7c7a6d..b77a4c71a6 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1856,11 +1856,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) */ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; + MemOp opc =3D get_memop(l->oi); tcg_insn_unit **label_ptr =3D &l->label_ptr[0]; - TCGReg retaddr; =20 /* resolve label address */ tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); @@ -1868,56 +1865,10 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); } =20 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - int ofs =3D 0; + tcg_out_st_helper_args(s, l, &ldst_helper_param); + tcg_out_branch(s, 1, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 - tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); - ofs +=3D 4; - - tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - } - - tcg_out_st(s, TCG_TYPE_I32, l->datalo_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - - if (s_bits =3D=3D MO_64) { - tcg_out_st(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - } - - tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs); - ofs +=3D 4; - - retaddr =3D TCG_REG_EAX; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, ofs); - } else { - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); - tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1], - l->addrlo_reg); - tcg_out_mov(s, (s_bits =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - tcg_target_call_iarg_regs[2], l->datalo_reg); - tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], oi); - - if (ARRAY_SIZE(tcg_target_call_iarg_regs) > 4) { - retaddr =3D tcg_target_call_iarg_regs[4]; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - } else { - retaddr =3D TCG_REG_RAX; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, - TCG_TARGET_CALL_STACK_OFFSET); - } - } - - /* "Tail call" to the helper, with the return address back inline. */ - tcg_out_push(s, retaddr); - tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_jmp(s, l->raddr); return true; } #else --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315422; cv=none; d=zohomail.com; s=zohoarc; b=eJ3nNbEYNf7rLHTfHhrXEjGcKI5ykFE5znbfOTKlEDTDle9++hwcqZUMRsEWkZAa0rvhlpTug+WfQqFAFAAJ2U2e9eD8P7wRCj6GXnhHAqZL2GjzzlszgDIr53qXuHE8pC9fmo1z2lmW0UcYLi2YFXEsLPWG3CLt3O0vq5hWYhY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315422; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5ZL038/Ng9nS/xr0DDxwNdtMDtu/OB6KUuAjmGyJXv0=; b=AbjOoOpRc0C0MK3bmzIq5nj6HcMa5oxwM9PaBlInE/ygg2tzXCnurF7np/8jExlQDW1wuk/siXnL0G+6Y8BEXUfSMtboobJkqUQ4rMvwEH8ZCScXSX5pSL6/zWqMQHrY4FJtaTq8Z/HLN5sk6t3BcLUKo98aFk3+iEg+WXx9aSg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315422668702.829827265645; Sun, 23 Apr 2023 22:50:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqp2N-00087c-P7; Mon, 24 Apr 2023 01:46:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqp0C-0005to-Bt for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:44:43 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqp03-0005GQ-W6 for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:44:35 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-2f86ee42669so3818541f8f.2 for ; Sun, 23 Apr 2023 22:44:31 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. 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Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 40 +++++++++++++++--------------------- 1 file changed, 16 insertions(+), 24 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 202b90c001..62dd22d73c 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1580,13 +1580,6 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext,= TCGReg d, } } =20 -static void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target) -{ - ptrdiff_t offset =3D tcg_pcrel_diff(s, target); - tcg_debug_assert(offset =3D=3D sextract64(offset, 0, 21)); - tcg_out_insn(s, 3406, ADR, rd, offset); -} - typedef struct { TCGReg base; TCGReg index; @@ -1627,47 +1620,46 @@ static void * const qemu_st_helpers[MO_SIZE + 1] = =3D { #endif }; =20 +static const TCGLdstHelperParam ldst_helper_param =3D { + .ntmp =3D 1, .tmp =3D { TCG_REG_TMP } +}; + static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc19(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); - tcg_out_mov(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X1, lb->addrlo_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, oi); - tcg_out_adr(s, TCG_REG_X3, lb->raddr); + tcg_out_ld_helper_args(s, lb, &ldst_helper_param); tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); - - tcg_out_movext(s, lb->type, lb->datalo_reg, - TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_X0); + tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); tcg_out_goto(s, lb->raddr); return true; } =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); - MemOp size =3D opc & MO_SIZE; + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc19(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); - tcg_out_mov(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X1, lb->addrlo_reg); - tcg_out_mov(s, size =3D=3D MO_64, TCG_REG_X2, lb->datalo_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, oi); - tcg_out_adr(s, TCG_REG_X4, lb->raddr); + tcg_out_st_helper_args(s, lb, &ldst_helper_param); tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE]); tcg_out_goto(s, lb->raddr); return true; } #else +static void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target) +{ + ptrdiff_t offset =3D tcg_pcrel_diff(s, target); + tcg_debug_assert(offset =3D=3D sextract64(offset, 0, 21)); + tcg_out_insn(s, 3406, ADR, rd, offset); +} + static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { if (!reloc_pc19(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[46.193.226.34]) by smtp.gmail.com with ESMTPSA id u6-20020adff886000000b002f7780eee10sm9986693wrp.59.2023.04.23.22.44.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:44:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682315071; x=1684907071; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e67Crv76HZSCg/mw2UfCxuP3kRlNk2dyxOLXgebiI/I=; b=V5R0e9oJ1k3/iy/GfS3btBIZK9PMyzOkPGpML3uDDAkjWsyrcdV4cnlttM+GcHBL4X L5VkO9cnL08vbAVhO5M760t6w9pGWh3HhKF1/0eEmjDhuoTgkQhbD9KKkRKcD3yWQZLQ 0KDnRJRa825Ao3zkies8fHbIy+zx4b6hffb1RfV9KoNzoYgcNlcreObX6K/Jn19EOQyj O3Ets6nDRNOomD15Z+TzRNNTHgfmQF3p9tRKNcQKf00fzLQ4xd+k35kK9igMForXbq2c cABddqN/lnk4J3NeJ74EjR0RqqRon/D7VsvT+jE9UNQrh5ICvpeKQBXdwYQJQTiezzgk 9n+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682315071; x=1684907071; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e67Crv76HZSCg/mw2UfCxuP3kRlNk2dyxOLXgebiI/I=; b=SHhtf1yxaFcUlTDs7EdyppFqy8XdlXaynKyBM/XW9ixe3VeNv1jwHM6lGxsxVFydSr FBk1ToQt4QfUD7Uz7suye5iiO26PtEpP+lHJCDknmOW8HlRisY7hrWArhMWMULK4NJ9Z VIj+aS4Br2k2ZZE1zNELJ1Wfve8z2zANcqsq1tjoZQBznlu93ULYgObwmBPD9z+KyUPi kM7zMqC9UQQzuwHh6iG0gFeC8wDB5WJg4wLBfGlFx+Z9AlDmHF+HrLFjbu5yPPTO8yZC egNZR4Wsr1hZ4RNZTN390EKGcPrN8QdT2aqD3NAcU7Q1xZa+21B7wlgOgm0kOM2j8+YI C/nA== X-Gm-Message-State: AAQBX9eGsFheF2wppCyOjGgGPURd8/fytUAe+YaIp2k8zmTGz0XCTHbE D0K+c9xTCJf5Ud3x39LhmiR0U9yltwnoTJFAfV451g== X-Google-Smtp-Source: AKy350YJAZ4RB9s/3c20vso7XU07flestcrfgdUeVQ/uf+2cUUm8MJPcxhjiCvho6ZRI/uY/0uaneQ== X-Received: by 2002:a1c:f715:0:b0:3f0:5887:bea3 with SMTP id v21-20020a1cf715000000b003f05887bea3mr7041346wmh.27.1682315071091; Sun, 23 Apr 2023 22:44:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 42/57] tcg/arm: Convert tcg_out_qemu_{ld,st}_slow_path Date: Mon, 24 Apr 2023 06:40:50 +0100 Message-Id: <20230424054105.1579315-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315907269100007 Content-Type: text/plain; charset="utf-8" Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. This allows our local tcg_out_arg_* infrastructure to be removed. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 140 +++++---------------------------------- 1 file changed, 18 insertions(+), 122 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index c744512778..df514e56fc 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -690,8 +690,8 @@ tcg_out_ldrd_rwb(TCGContext *s, ARMCond cond, TCGReg rt= , TCGReg rn, TCGReg rm) tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 1); } =20 -static void tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, int imm8) +static void __attribute__((unused)) +tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); } @@ -969,28 +969,16 @@ static void tcg_out_ext8u(TCGContext *s, TCGReg rd, T= CGReg rn) tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff); } =20 -static void __attribute__((unused)) -tcg_out_ext8u_cond(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) -{ - tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff); -} - static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) { /* sxth */ tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn); } =20 -static void tcg_out_ext16u_cond(TCGContext *s, ARMCond cond, - TCGReg rd, TCGReg rn) -{ - /* uxth */ - tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn); -} - static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) { - tcg_out_ext16u_cond(s, COND_AL, rd, rn); + /* uxth */ + tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | (rd << 12) | rn); } =20 static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) @@ -1382,92 +1370,29 @@ static void * const qemu_st_helpers[MO_SIZE + 1] = =3D { #endif }; =20 -/* Helper routines for marshalling helper function arguments into - * the correct registers and stack. - * argreg is where we want to put this argument, arg is the argument itsel= f. - * Return value is the updated argreg ready for the next call. - * Note that argreg 0..3 is real registers, 4+ on stack. - * - * We provide routines for arguments which are: immediate, 32 bit - * value in register, 16 and 8 bit values in register (which must be zero - * extended before use) and 64 bit value in a lo:hi register pair. - */ -#define DEFINE_TCG_OUT_ARG(NAME, ARGTYPE, MOV_ARG, EXT_ARG) = \ -static TCGReg NAME(TCGContext *s, TCGReg argreg, ARGTYPE arg) = \ -{ = \ - if (argreg < 4) { = \ - MOV_ARG(s, COND_AL, argreg, arg); = \ - } else { = \ - int ofs =3D (argreg - 4) * 4; = \ - EXT_ARG; = \ - tcg_debug_assert(ofs + 4 <=3D TCG_STATIC_CALL_ARGS_SIZE); = \ - tcg_out_st32_12(s, COND_AL, arg, TCG_REG_CALL_STACK, ofs); = \ - } = \ - return argreg + 1; = \ -} - -DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32, uint32_t, tcg_out_movi32, - (tcg_out_movi32(s, COND_AL, TCG_REG_TMP, arg), arg =3D TCG_REG_TMP)) -DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8, TCGReg, tcg_out_ext8u_cond, - (tcg_out_ext8u_cond(s, COND_AL, TCG_REG_TMP, arg), arg =3D TCG_REG_TMP= )) -DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16, TCGReg, tcg_out_ext16u_cond, - (tcg_out_ext16u_cond(s, COND_AL, TCG_REG_TMP, arg), arg =3D TCG_REG_TM= P)) -DEFINE_TCG_OUT_ARG(tcg_out_arg_reg32, TCGReg, tcg_out_mov_reg, ) - -static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg, - TCGReg arglo, TCGReg arghi) +static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int ar= g) { - /* 64 bit arguments must go in even/odd register pairs - * and in 8-aligned stack slots. - */ - if (argreg & 1) { - argreg++; - } - if (argreg >=3D 4 && (arglo & 1) =3D=3D 0 && arghi =3D=3D arglo + 1) { - tcg_out_strd_8(s, COND_AL, arglo, - TCG_REG_CALL_STACK, (argreg - 4) * 4); - return argreg + 2; - } else { - argreg =3D tcg_out_arg_reg32(s, argreg, arglo); - argreg =3D tcg_out_arg_reg32(s, argreg, arghi); - return argreg; - } + /* We arrive at the slow path via "BLNE", so R14 contains l->raddr. */ + return TCG_REG_R14; } =20 +static const TCGLdstHelperParam ldst_helper_param =3D { + .ra_gen =3D ldst_ra_gen, + .ntmp =3D 1, + .tmp =3D { TCG_REG_TMP }, +}; + static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGReg argreg; - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - argreg =3D tcg_out_arg_reg32(s, TCG_REG_R0, TCG_AREG0); - if (TARGET_LONG_BITS =3D=3D 64) { - argreg =3D tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi= _reg); - } else { - argreg =3D tcg_out_arg_reg32(s, argreg, lb->addrlo_reg); - } - argreg =3D tcg_out_arg_imm32(s, argreg, oi); - argreg =3D tcg_out_arg_reg32(s, argreg, TCG_REG_R14); - - /* Use the canonical unsigned helpers and minimize icache usage. */ + tcg_out_ld_helper_args(s, lb, &ldst_helper_param); tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); - - if ((opc & MO_SIZE) =3D=3D MO_64) { - TCGMovExtend ext[2] =3D { - { .dst =3D lb->datalo_reg, .dst_type =3D TCG_TYPE_I32, - .src =3D TCG_REG_R0, .src_type =3D TCG_TYPE_I32, .src_ext = =3D MO_UL }, - { .dst =3D lb->datahi_reg, .dst_type =3D TCG_TYPE_I32, - .src =3D TCG_REG_R1, .src_type =3D TCG_TYPE_I32, .src_ext = =3D MO_UL }, - }; - tcg_out_movext2(s, &ext[0], &ext[1], TCG_REG_TMP); - } else { - tcg_out_movext(s, TCG_TYPE_I32, lb->datalo_reg, - TCG_TYPE_I32, opc & MO_SSIZE, TCG_REG_R0); - } + tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); =20 tcg_out_goto(s, COND_AL, lb->raddr); return true; @@ -1475,42 +1400,13 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGReg argreg, datalo, datahi; - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - argreg =3D TCG_REG_R0; - argreg =3D tcg_out_arg_reg32(s, argreg, TCG_AREG0); - if (TARGET_LONG_BITS =3D=3D 64) { - argreg =3D tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi= _reg); - } else { - argreg =3D tcg_out_arg_reg32(s, argreg, lb->addrlo_reg); - } - - datalo =3D lb->datalo_reg; - datahi =3D lb->datahi_reg; - switch (opc & MO_SIZE) { - case MO_8: - argreg =3D tcg_out_arg_reg8(s, argreg, datalo); - break; - case MO_16: - argreg =3D tcg_out_arg_reg16(s, argreg, datalo); - break; - case MO_32: - default: - argreg =3D tcg_out_arg_reg32(s, argreg, datalo); - break; - case MO_64: - argreg =3D tcg_out_arg_reg64(s, argreg, datalo, datahi); - break; - } - - argreg =3D tcg_out_arg_imm32(s, argreg, oi); - argreg =3D tcg_out_arg_reg32(s, argreg, TCG_REG_R14); + tcg_out_st_helper_args(s, lb, &ldst_helper_param); =20 /* Tail-call to the helper, which will return to the fast path. */ tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315403216153.30349911017868; Sun, 23 Apr 2023 22:50:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqp2Y-0001Af-S8; Mon, 24 Apr 2023 01:47:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqp0G-0005x6-2N for qemu-devel@nongnu.org; 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[46.193.226.34]) by smtp.gmail.com with ESMTPSA id u6-20020adff886000000b002f7780eee10sm9986693wrp.59.2023.04.23.22.44.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:44:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682315071; x=1684907071; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WIdMYknenlDL6zEabJSzjI8eOseBt6FLgSg6Xk98IsQ=; b=rVKPE3y/e4mhwCnHFohU2X/wnxZd40F4yQyJ9ssQN+TqCdTmPfdfeqt3x+JVD/OTS6 mFiGgDyY4qshaxzKI2WzX5BBCcHidS27Hzf3yIiS1ncByqFp9/iBdU1Ya8m/BSDP4kRe /dXqr1VlRNCi810rY/J61yBLzDz1UO1nt5WTmP9c0iSXJMAMhUMgBQi8trIOOD10HJbB 0uaMMexDMpMWou3PlzT8oCoMUfG0fWxNUsoC9WBxMMwoLCVFoAsHtF39DA+WT2NfTzTh GUMshHCe502HG1RTkV5HD+C7yF6PIRDi2tG4yb+B0lZF4KuIcdXRUz6qIaFzyGZDQsO5 deTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682315071; x=1684907071; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WIdMYknenlDL6zEabJSzjI8eOseBt6FLgSg6Xk98IsQ=; b=AElg9uQVnodk9crRLC71Ev5q6NIl6gi6wU4437dSh/RWVTRrijZgq/zCxyTl9t3rw7 oKqDrW/BP/0Z1XciMnDrwS4NawP0PNoBBe57rK9Yg+T7g3tNPMflBPGq2Y+qRjAWvgs1 VGyOAlO7iNcTTu4WbL2wNpAmdrq+usaXU5OeHrmpyt5wgH1rDZBRg4y7znpf1ZlL+387 SfRtSJ2XXbhsr5y7/FZSzX0U67fYRBEl2RNV8J+dt/1TvdshliEjeVQwG0LQdUSKDI7+ yEJhj64OgKlymKh+gpVS10wJ2stsS0E7kGfOXkrh9ACIHPtb84SSp4C1kblUgm7jc4S+ 4zsA== X-Gm-Message-State: AAQBX9fhH8lsoz4fJ2kFtZxtct/YjLBquRhKHKABS9asOnQo/tEnJtgb 4iJbi5I2g1fwl2QbqcNR4NMrCPBrgKFvolvWgErv4w== X-Google-Smtp-Source: AKy350ZQOQ7fI5/y2ztgB0L245TKkmVwmvm4e6I03y1t+9g7w0xrbThwKZaaKkxgi0G/BuMXkyjNzw== X-Received: by 2002:a5d:4c49:0:b0:2fb:f93f:b96 with SMTP id n9-20020a5d4c49000000b002fbf93f0b96mr9232857wrt.31.1682315071688; Sun, 23 Apr 2023 22:44:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 43/57] tcg/loongarch64: Convert tcg_out_qemu_{ld, st}_slow_path Date: Mon, 24 Apr 2023 06:40:51 +0100 Message-Id: <20230424054105.1579315-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1682315404766100002 Content-Type: text/plain; charset="utf-8" Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 37 ++++++++++---------------------- 1 file changed, 11 insertions(+), 26 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 2f2c34b930..60d2c904dd 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -824,51 +824,36 @@ static bool tcg_out_goto(TCGContext *s, const tcg_ins= n_unit *target) return reloc_br_sd10k16(s->code_ptr - 1, target); } =20 +static const TCGLdstHelperParam ldst_helper_param =3D { + .ntmp =3D 1, .tmp =3D { TCG_REG_TMP0 } +}; + static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - MemOp size =3D opc & MO_SIZE; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - /* call load helper */ - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A1, l->addrlo_reg); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A2, oi); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, (tcg_target_long)l->raddr); - - tcg_out_call_int(s, qemu_ld_helpers[size], false); - - tcg_out_movext(s, l->type, l->datalo_reg, - TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_A0); + tcg_out_ld_helper_args(s, l, &ldst_helper_param); + tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE], false); + tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param); return tcg_out_goto(s, l->raddr); } =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - MemOp size =3D opc & MO_SIZE; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - /* call store helper */ - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A1, l->addrlo_reg); - tcg_out_movext(s, size =3D=3D MO_64 ? TCG_TYPE_I32 : TCG_TYPE_I32, TCG= _REG_A2, - l->type, size, l->datalo_reg); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, oi); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A4, (tcg_target_long)l->raddr); - - tcg_out_call_int(s, qemu_st_helpers[size], false); - + tcg_out_st_helper_args(s, l, &ldst_helper_param); + tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); return tcg_out_goto(s, l->raddr); } #else --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315634; cv=none; d=zohomail.com; s=zohoarc; b=FmK4wKeuPLOCyfdBVsIXtru3fUrijn8CdKInFk9K4oNKrvcKyt+Av7JG/+Hvxk68+tk7qWqy2rN87z6Hx1EU8Imq20gIEDPam+tHGNMFONrmJszHYV7xpHHH4SJ9N2O9J2FeMZ/Qb6oSIQeMJqYq8NictESJdxhhu1T0uj/w7n8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315634; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kF/KuD0+uQLXuYT2v2A5wco+ARF0bjd47P8BXDbif68=; b=DEiDn7Ef79daDKpdQY0qjlU0yuWEZQQUj2BiUrI7CA+jqAT8IHltRssbWrCKm/KfYoaLybbbdsvAv5Jqur/9yN9ftOXzC7YLs2Bc5llCLTwXdk/7zE90e/ki/Ta+aOJIosw2DmkAjzm+XbJg+CftuOTcbPPYGntlATbGOePMRS4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315634888833.9737116788993; Sun, 23 Apr 2023 22:53:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqp3U-0004KC-1B; Mon, 24 Apr 2023 01:48:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqp0G-0005wu-1J for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:44:45 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqp05-0005Hf-MD for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:44:41 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-2f7db354092so2314106f8f.2 for ; Sun, 23 Apr 2023 22:44:33 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id u6-20020adff886000000b002f7780eee10sm9986693wrp.59.2023.04.23.22.44.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:44:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682315072; x=1684907072; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kF/KuD0+uQLXuYT2v2A5wco+ARF0bjd47P8BXDbif68=; b=Wv1S/7sK4OGei3ZKuseQx1PgHH7It+1zWPJY38RJyXJn5Eg4zFC7YzZVL6CBKRR75m Q4EW9B8vn5rHIH3XdvCCPGFjzEPXAJAqNIFdWBZpYluu8IWhdWjurRH/YC+aLUh656pb aGUlnN2l/dvaRtIRsF8bd0HpQwWpd1oGHq/SanyhWSBRiLhWKavBBtuOpHRsuqKO1whH /UdTJaMGq89XMC9mg9/a8gBwimQYyZwUSuLBb/uEXDphS6cEsHN/7ThPaxpCamrTv4ge qnLD3DYeZ4bgkF46gNl7xiH8d+9+W7Nx5rVtU8TgiR9NFQ78TcNwuIYbnSoWeLAtbYWy pFPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682315072; x=1684907072; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kF/KuD0+uQLXuYT2v2A5wco+ARF0bjd47P8BXDbif68=; b=koPT3vaz3X8FECunGbgA0xw0Vr5bRSvNGfwmll5U1p2LOp+oGZJsPHbVmw+otM4JT6 EROZ492cZXopXgpc1mIqJdSeE765liteCHDRFPDrTG2kI/7Nbqq0rMraNbuJnKWG8lGn sFh6gsPKBb4bNTRpPa2Sty6YsO+w6crkrLZyYZaVSgexWI5qOlANy0xB2iNvesintZJH WqiXleGRO5G7UDGAzEyXjw55xeS1qH/hh1/929LYPO6DQ0cS8CA1RK2cV9VTiVz03mlO ezzeuR56Q0QyftC12S9ghLus0RucDUSwarc6jNSsfqSW4IwBYUADFjn6vqoSB6NCBfr8 g6Ig== X-Gm-Message-State: AAQBX9cZco9wZYzA2pBw3PdNXg2UxI2DLH8PSRFmENNDfZQxQPf/1g05 4foAXJWL9y+0W2vBqWHYC1bMGt51GCbK8HatlT+2/A== X-Google-Smtp-Source: AKy350bE/g6xELbGgEXLa7tMzc8W62JXBXqNZ8uPwzNyf7Z1DqBJaoDtNBkGZjkGGbrgd3GXjSZZMw== X-Received: by 2002:adf:fb01:0:b0:2f2:b71a:40cb with SMTP id c1-20020adffb01000000b002f2b71a40cbmr8159529wrr.56.1682315072173; Sun, 23 Apr 2023 22:44:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 44/57] tcg/mips: Convert tcg_out_qemu_{ld,st}_slow_path Date: Mon, 24 Apr 2023 06:40:52 +0100 Message-Id: <20230424054105.1579315-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315635387100001 Content-Type: text/plain; charset="utf-8" Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. This allows our local tcg_out_arg_* infrastructure to be removed. We are no longer filling the call or return branch delay slots, nor are we tail-calling for the store, but this seems a small price to pay. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 154 ++++++-------------------------------- 1 file changed, 22 insertions(+), 132 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 94708e6ea7..022960d79a 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1115,79 +1115,15 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_B= SWAP) + 1] =3D { [MO_BEUQ] =3D helper_be_stq_mmu, }; =20 -/* Helper routines for marshalling helper function arguments into - * the correct registers and stack. - * I is where we want to put this argument, and is updated and returned - * for the next call. ARG is the argument itself. - * - * We provide routines for arguments which are: immediate, 32 bit - * value in register, 16 and 8 bit values in register (which must be zero - * extended before use) and 64 bit value in a lo:hi register pair. - */ - -static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg) -{ - if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { - tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg); - } else { - /* For N32 and N64, the initial offset is different. But there - we also have 8 argument register so we don't run out here. */ - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); - tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i); - } - return i + 1; -} - -static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg) -{ - TCGReg tmp =3D TCG_TMP0; - if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { - tmp =3D tcg_target_call_iarg_regs[i]; - } - tcg_out_ext8u(s, tmp, arg); - return tcg_out_call_iarg_reg(s, i, tmp); -} - -static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg) -{ - TCGReg tmp =3D TCG_TMP0; - if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { - tmp =3D tcg_target_call_iarg_regs[i]; - } - tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff); - return tcg_out_call_iarg_reg(s, i, tmp); -} - -static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg) -{ - TCGReg tmp =3D TCG_TMP0; - if (arg =3D=3D 0) { - tmp =3D TCG_REG_ZERO; - } else { - if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { - tmp =3D tcg_target_call_iarg_regs[i]; - } - tcg_out_movi(s, TCG_TYPE_REG, tmp, arg); - } - return tcg_out_call_iarg_reg(s, i, tmp); -} - -static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg = ah) -{ - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); - i =3D (i + 1) & ~1; - i =3D tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al)); - i =3D tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah)); - return i; -} +/* We have four temps, we might as well expose three of them. */ +static const TCGLdstHelperParam ldst_helper_param =3D { + .ntmp =3D 3, .tmp =3D { TCG_TMP0, TCG_TMP1, TCG_TMP2 } +}; =20 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { const tcg_insn_unit *tgt_rx =3D tcg_splitwx_to_rx(s->code_ptr); - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - TCGReg v0; - int i; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_pc16(l->label_ptr[0], tgt_rx) @@ -1196,29 +1132,13 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) return false; } =20 - i =3D 1; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - i =3D tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); - } else { - i =3D tcg_out_call_iarg_reg(s, i, l->addrlo_reg); - } - i =3D tcg_out_call_iarg_imm(s, i, oi); - i =3D tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr); + tcg_out_ld_helper_args(s, l, &ldst_helper_param); + tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], fals= e); /* delay slot */ - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); + tcg_out_nop(s); =20 - v0 =3D l->datalo_reg; - if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { - /* We eliminated V0 from the possible output registers, so it - cannot be clobbered here. So we must move V1 first. */ - if (MIPS_BE) { - tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1); - v0 =3D l->datahi_reg; - } else { - tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1); - } - } + tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); =20 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { @@ -1226,22 +1146,14 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) } =20 /* delay slot */ - if (TCG_TARGET_REG_BITS =3D=3D 64 && l->type =3D=3D TCG_TYPE_I32) { - /* we always sign-extend 32-bit loads */ - tcg_out_ext32s(s, v0, TCG_REG_V0); - } else { - tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO); - } + tcg_out_nop(s); return true; } =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { const tcg_insn_unit *tgt_rx =3D tcg_splitwx_to_rx(s->code_ptr); - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; - int i; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_pc16(l->label_ptr[0], tgt_rx) @@ -1250,41 +1162,19 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) return false; } =20 - i =3D 1; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - i =3D tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); - } else { - i =3D tcg_out_call_iarg_reg(s, i, l->addrlo_reg); - } - switch (s_bits) { - case MO_8: - i =3D tcg_out_call_iarg_reg8(s, i, l->datalo_reg); - break; - case MO_16: - i =3D tcg_out_call_iarg_reg16(s, i, l->datalo_reg); - break; - case MO_32: - i =3D tcg_out_call_iarg_reg(s, i, l->datalo_reg); - break; - case MO_64: - if (TCG_TARGET_REG_BITS =3D=3D 32) { - i =3D tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_re= g); - } else { - i =3D tcg_out_call_iarg_reg(s, i, l->datalo_reg); - } - break; - default: - g_assert_not_reached(); - } - i =3D tcg_out_call_iarg_imm(s, i, oi); + tcg_out_st_helper_args(s, l, &ldst_helper_param); =20 - /* Tail call to the store helper. Thus force the return address - computation to take place in the return address register. */ - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr); - i =3D tcg_out_call_iarg_reg(s, i, TCG_REG_RA); - tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true); + tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], false= ); /* delay slot */ - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); + tcg_out_nop(s); + + tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); + if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { + return false; + } + + /* delay slot */ + tcg_out_nop(s); return true; } =20 --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315907; cv=none; d=zohomail.com; s=zohoarc; b=lsLLQWroWgXVF5BE5QRlczlypt1OPcWIDGUaTmJRWtCQNI14jS8JADIP2f0rQ/LMcVQ6cB5zRadr6h2OjeoKDpe5bnifVQO0geNT/Pd5r/ZJonplu2/iYHbW6m444ZjAocJJA/ONwOaOqhlxtDdl7vlwQYZjuLq1udczxd+zO5k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315907; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Bp+7jHuRwCoumX81kkmi2LLSK4XPzI38mrYIrW5iAjM=; b=Mn4iyaEwVcsH/LlWlcOOfroUfNT+kamlVMtXtYb+DAlyFSSbBemy6Qd03AmRUjoBCFy5PgSSmptcBgSVcknOD9wumMQnc+5oZz/mkk/75tFqwETgkR3mUPj1nNo+KbJlTxgn65uIQ4Tk9lt9XAq2uRpXSP1lGvoDsc3Iaokilq0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315907114768.7636662559232; Sun, 23 Apr 2023 22:58:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqp3X-0004o3-EG; Mon, 24 Apr 2023 01:48:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqp0J-00060S-Rl for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:44:56 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqp0A-0005IA-CN for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:44:47 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-3047ff3269aso97929f8f.0 for ; Sun, 23 Apr 2023 22:44:33 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. 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Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 88 ++++++++++++---------------------------- 1 file changed, 26 insertions(+), 62 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 7239335bdf..042136fee7 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2003,44 +2003,38 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_B= SWAP) + 1] =3D { [MO_BEUQ] =3D helper_be_stq_mmu, }; =20 +static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int ar= g) +{ + if (arg < 0) { + arg =3D TCG_REG_TMP1; + } + tcg_out32(s, MFSPR | RT(arg) | LR); + return arg; +} + +/* + * For the purposes of ppc32 sorting 4 input registers into 4 argument + * registers, there is an outside chance we would require 3 temps. + * Because of constraints, no inputs are in r3, and env will not be + * placed into r3 until after the sorting is done, and is thus free. + */ +static const TCGLdstHelperParam ldst_helper_param =3D { + .ra_gen =3D ldst_ra_gen, + .ntmp =3D 3, + .tmp =3D { TCG_REG_TMP1, TCG_REG_R0, TCG_REG_R3 } +}; + static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); - TCGReg hi, lo, arg =3D TCG_REG_R3; + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); - - lo =3D lb->addrlo_reg; - hi =3D lb->addrhi_reg; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - arg |=3D (TCG_TARGET_CALL_ARG_I64 =3D=3D TCG_CALL_ARG_EVEN); - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - } else { - /* If the address needed to be zero-extended, we'll have already - placed it in R4. The only remaining case is 64-bit guest. */ - tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); - } - - tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); - tcg_out32(s, MFSPR | RT(arg) | LR); - + tcg_out_ld_helper_args(s, lb, &ldst_helper_param); tcg_out_call_int(s, LK, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); - - lo =3D lb->datalo_reg; - hi =3D lb->datahi_reg; - if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { - tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4); - tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3); - } else { - tcg_out_movext(s, lb->type, lo, - TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_R3); - } + tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); =20 tcg_out_b(s, 0, lb->raddr); return true; @@ -2048,43 +2042,13 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; - TCGReg hi, lo, arg =3D TCG_REG_R3; + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); - - lo =3D lb->addrlo_reg; - hi =3D lb->addrhi_reg; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - arg |=3D (TCG_TARGET_CALL_ARG_I64 =3D=3D TCG_CALL_ARG_EVEN); - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - } else { - /* If the address needed to be zero-extended, we'll have already - placed it in R4. The only remaining case is 64-bit guest. */ - tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); - } - - lo =3D lb->datalo_reg; - hi =3D lb->datahi_reg; - if (TCG_TARGET_REG_BITS =3D=3D 32 && s_bits =3D=3D MO_64) { - arg |=3D (TCG_TARGET_CALL_ARG_I64 =3D=3D TCG_CALL_ARG_EVEN); - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - } else { - tcg_out_movext(s, s_bits =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I3= 2, - arg++, lb->type, s_bits, lo); - } - - tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); - tcg_out32(s, MFSPR | RT(arg) | LR); - + tcg_out_st_helper_args(s, lb, &ldst_helper_param); tcg_out_call_int(s, LK, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 tcg_out_b(s, 0, lb->raddr); --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315478; cv=none; d=zohomail.com; s=zohoarc; b=IqjBHTrZFOj/ZdUWMkhxAU8xUbrJ/+FQO4MZ6rygln2uPW1S6Q9jzba/x3UXMZ2B7mn8NO3iKq+lCfHcdTOMnKzK5qvL4YLXKpGBRf2n5SNqnY1+iiSVMRILmnJYXEItxHd91yBi1PHSFGw8I4jPcWy955ysDJE1tR1OWQdzGxk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315478; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QhG/YblVw95Lhxb+Zi1tBoEAbDtFZFxW4Ta81aHHVFo=; b=nkW2CdEpPHwqSs7wH4NUo0WE5o3BuFc/jCEUXiU+3tly4kQMrKF6Kz3zbFbO6RmP7E6bqPxOfWSGeV3XtlTK4ISLGQYtYBkNdzE6aX4z+erMmh5z7UGjFt1pM9X/7vUHuvvYl+9nGGzbdRFwNyKt1u9ANMMbld/pmt+L3oDZq8c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168231547851793.5132236856233; Sun, 23 Apr 2023 22:51:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqp4a-0005o4-TK; Mon, 24 Apr 2023 01:49:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqp0g-0006J4-O2 for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:45:19 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqp0H-0005Io-U8 for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:45:05 -0400 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-2f46348728eso2305178f8f.3 for ; Sun, 23 Apr 2023 22:44:34 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id u6-20020adff886000000b002f7780eee10sm9986693wrp.59.2023.04.23.22.44.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:44:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682315073; x=1684907073; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QhG/YblVw95Lhxb+Zi1tBoEAbDtFZFxW4Ta81aHHVFo=; b=eGx+Nh5gFKiD+sdKX2F0VcnOEFCQ/HBpaMYQUbAHLvIXwv4G7m6DVhRO5Z2lWIGWYP G9GsdmDYet602ukiacSzVVWS1iyZPhm+EIDh2LDhDXlaSs+IYbGQ1ZFOfkf8Vlff3ebY 6xVczSB+6Z5vCYXA45Oev6g1Yh+UqPI4SH4KSgYEdp507ChBAa47a7h9KdDkTtFIw4it vdrS6o9takR6a6FbeFFtHV2UprHgFPARA5yPUsDbz4YsJkGpmubx374tDXMVvlbBwNSZ 49vHuRlm4c5/KQfcm6/BpFLtHaUjXbgTV0tNABbw/m+kHTEfysrTBVb0l2/uNwb1oI56 gIlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682315073; x=1684907073; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QhG/YblVw95Lhxb+Zi1tBoEAbDtFZFxW4Ta81aHHVFo=; b=X17rQIKa5hacLST9yekIn8B0g3lhf2kyvap5etSzTKlIxu41scZNXhEAzuzUgO3duD cQb1VnPHDorXijAdrabNymyqrwMcS9TVBACK4db2bp2y+QG7nsFJBG+ENcqjwXuWlxYe UM59PQKsYMZ9Ddm2yXSC7n5dpl7gvrV8bIhBi9jeXkizohW+bew0T6aosKaNLMd0Y6Ws jy89t6dN1Q4z9eDTxywaTNJtcD/5Ct4eogrzo62UMrr0WpUTEyn4h4DEMpY9//o3ZcCq v/ll+oUJC7BW6GYv6JMxn3BFqzM9RExEATtbD6RafrXzQ4NiQ2LUXmkXi9E1FAEy16GL 0vFg== X-Gm-Message-State: AAQBX9d5tYei4rPxS3ejGJbL8+vqRdPQFFelY/bdVQEmej4MaLgy3SZ7 sRFdi7NhwAGUHZrXzm+WskiPdWmRzDv2ozteUllRaA== X-Google-Smtp-Source: AKy350a0TATkSKAQigOMRPd7kcmMFr0h3+oGGpMco6iMDtEY1xC9o1pRrUz2SdMPz7RSZqqG4+1qmw== X-Received: by 2002:a5d:4f05:0:b0:2ef:baa1:f3fc with SMTP id c5-20020a5d4f05000000b002efbaa1f3fcmr7977418wru.19.1682315073355; Sun, 23 Apr 2023 22:44:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com, Daniel Henrique Barboza Subject: [PATCH v3 46/57] tcg/riscv: Convert tcg_out_qemu_{ld,st}_slow_path Date: Mon, 24 Apr 2023 06:40:54 +0100 Message-Id: <20230424054105.1579315-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315478937100005 Content-Type: text/plain; charset="utf-8" Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 37 ++++++++++--------------------------- 1 file changed, 10 insertions(+), 27 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index b0ed39beff..4c8e38599b 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -920,14 +920,14 @@ static void tcg_out_goto(TCGContext *s, const tcg_ins= n_unit *target) tcg_debug_assert(ok); } =20 +/* We have three temps, we might as well expose them. */ +static const TCGLdstHelperParam ldst_helper_param =3D { + .ntmp =3D 3, .tmp =3D { TCG_REG_TMP0, TCG_REG_TMP1, TCG_REG_TMP2 } +}; + static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - TCGReg a0 =3D tcg_target_call_iarg_regs[0]; - TCGReg a1 =3D tcg_target_call_iarg_regs[1]; - TCGReg a2 =3D tcg_target_call_iarg_regs[2]; - TCGReg a3 =3D tcg_target_call_iarg_regs[3]; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -935,13 +935,9 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, T= CGLabelQemuLdst *l) } =20 /* call load helper */ - tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); - tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); - tcg_out_movi(s, TCG_TYPE_PTR, a2, oi); - tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr); - + tcg_out_ld_helper_args(s, l, &ldst_helper_param); tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); - tcg_out_mov(s, (opc & MO_SIZE) =3D=3D MO_64, l->datalo_reg, a0); + tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); =20 tcg_out_goto(s, l->raddr); return true; @@ -949,14 +945,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, T= CGLabelQemuLdst *l) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; - TCGReg a0 =3D tcg_target_call_iarg_regs[0]; - TCGReg a1 =3D tcg_target_call_iarg_regs[1]; - TCGReg a2 =3D tcg_target_call_iarg_regs[2]; - TCGReg a3 =3D tcg_target_call_iarg_regs[3]; - TCGReg a4 =3D tcg_target_call_iarg_regs[4]; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -964,13 +953,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, T= CGLabelQemuLdst *l) } =20 /* call store helper */ - tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); - tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); - tcg_out_movext(s, s_bits =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, a= 2, - l->type, s_bits, l->datalo_reg); - tcg_out_movi(s, TCG_TYPE_PTR, a3, oi); - tcg_out_movi(s, TCG_TYPE_PTR, a4, (tcg_target_long)l->raddr); - + tcg_out_st_helper_args(s, l, &ldst_helper_param); tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); =20 tcg_out_goto(s, l->raddr); --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315773; cv=none; d=zohomail.com; s=zohoarc; b=m0+m76SaCrM0D+XeRuM6DA33QySu0k+s2jdOQVyNrv687KkR5Dzv/8I0q+uNfAOu4dPlkbU1YtfSdvFpfkQMTJGrJNKz2KaVR/xzj2UNqqZNHa7TL2j7GnCUWqcqydGimaBS5fR/T176wuDbRoAAF1qp3rtaGIouvyjXcyhxSo8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315773; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8inodTGUilDAhT6OBmWmJGZ3vieMgwqC5uJSdvFYggQ=; b=caNC53Wr9CZ/KCFW+/N+9OI7jZO+gwjl57UBJABUIVxyvkis/gW3qNxm3HN3NMVp1rWNi11szpzLL51vgp/FT0TK/cZjSY9WTk8JCuerNMS5mYfzGQD2TQd0cN12dbVwG/CWCNRFcVLF+BjcOs88z8+VAf8LhX1a8Mj6sqfP/mQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315773543989.4553587540643; Sun, 23 Apr 2023 22:56:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqp2b-0001il-Hz; Mon, 24 Apr 2023 01:47:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqp0L-00060W-Pc for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:44:56 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqp0C-0005J5-SM for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:44:49 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-3f173af665fso24594205e9.3 for ; Sun, 23 Apr 2023 22:44:34 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. 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Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 35 ++++++++++------------------------- 1 file changed, 10 insertions(+), 25 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index c3157d22be..dfcf4d9e34 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1718,26 +1718,22 @@ static void tcg_out_qemu_st_direct(TCGContext *s, M= emOp opc, TCGReg data, } =20 #if defined(CONFIG_SOFTMMU) +static const TCGLdstHelperParam ldst_helper_param =3D { + .ntmp =3D 1, .tmp =3D { TCG_TMP0 } +}; + static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGReg addr_reg =3D lb->addrlo_reg; - TCGReg data_reg =3D lb->datalo_reg; - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(lb->oi); =20 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg); - } - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, oi); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R5, (uintptr_t)lb->raddr); - tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]); - tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R2); + tcg_out_ld_helper_args(s, lb, &ldst_helper_param); + tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); + tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); =20 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); return true; @@ -1745,25 +1741,14 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGReg addr_reg =3D lb->addrlo_reg; - TCGReg data_reg =3D lb->datalo_reg; - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); - MemOp size =3D opc & MO_SIZE; + MemOp opc =3D get_memop(lb->oi); =20 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg); - } - tcg_out_movext(s, size =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, - TCG_REG_R4, lb->type, size, data_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, oi); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R6, (uintptr_t)lb->raddr); + tcg_out_st_helper_args(s, lb, &ldst_helper_param); tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315799; cv=none; d=zohomail.com; s=zohoarc; b=JSS0QTSPbXhLj4cMWSYbo7rfFepTlFW0yH/zZIeEtzcFczOJp/lcs9cEC06byhA5uhTGubc4R1RCboFrziBomjQgO34IZVV86Xn/tLP3iXMxOiOi2Lyy95gOpeUQDjjRn/nYLjtDo5ymcV7HxAOWTimWg4IGKiSfbU7SgrWBHws= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315799; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=I/zSZo4J7v0p5c8aMIcv0bwGQ0NvaaNKP+yN/zUi81E=; b=Yuae5M6qaxC8xs4aqohUE3kl8metsiiEYeNeXpTojO8yAYIdG3dHwoPr1xfF04xKjdZYTSbPSJJiWteGiKBnFw+yRFt9Zst5m+G+cL5hUFnK0tkRzWujkQ1/hh4+6zdVvH4n0R0iGB0cj5g9rgPJuvNSbNnHE4G2JuDs79QGHiQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315798976433.3583215443043; Sun, 23 Apr 2023 22:56:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqp5A-0007Uq-Qw; Mon, 24 Apr 2023 01:49:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqp0r-0006ZZ-9i for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:45:21 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqp0I-0005JQ-2b for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:45:20 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-3f1950f5628so26773365e9.3 for ; Sun, 23 Apr 2023 22:44:35 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id u6-20020adff886000000b002f7780eee10sm9986693wrp.59.2023.04.23.22.44.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:44:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682315074; x=1684907074; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=I/zSZo4J7v0p5c8aMIcv0bwGQ0NvaaNKP+yN/zUi81E=; b=aXXTkZMsBBpm742Z1RSsJqqFEEWUOaCHiteadUsrw+nYbF4G+sWYbu+YTB5KCORFxm psy4w3rmeAcjNza7vc2ivHMRriG3Cd/8+dxVIPVoYnAIDYXUBsSPbqoTRDpbPOUzoe2J iAvLfLreLvtdQansUFHRdSgAJr6KTNZ0CIDrKymy6nZHMx3fvkzGQm6A1Y6g5mUBFywr yps684vRpmbZY2W21Je2C+dT92FHh9U792BtWZmmuUlVV7dTL8nAnbhzP13wieMPyQGh jTzALGiW8KJs9bu7K2SOA9WOv1amIPKZ+qB/8JhUG8dCzRbBCk4vlAPTY03wQ63GjSbU nVlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682315074; x=1684907074; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I/zSZo4J7v0p5c8aMIcv0bwGQ0NvaaNKP+yN/zUi81E=; b=PUdClWaB2k20LIYdsn8UM29giI3n8ik4ToiK6VTagrkrOawhqpBCIFZjS9PBFFjZd9 clRMH6TTkWVuyIXqkKE1uytcOU5F8dijgLbAFMDtaZWf6Ouu7fnMM7UWo5cXrIKtBRYe R2+XIDk0WDb0HR+d8RkoUwRbunnk5ENkthp3ZWW6ahLaWjetLXo9R1FdA0NbQJlgQkgW MXZvmA9xXCiQG7vEwYkEbrOjnjg6dA/OwARGGdNd6xHzSfL1pLej+6mm4qOHO21w6JDr n3IFEFRupv7wBwWgnFYX1tLEPvjnyzOrhlP0yv9p5GQCJmIFiCJwRaRW5y3FQNl4jP9+ mO2A== X-Gm-Message-State: AAQBX9cx7kGVyunqPCFuQosdYQAv4TAdge3ycGSO7dtmbL47/II1EOiz G+GIjuZ3aIm9vibDefvgfR7Yug52Au0vYeBDkw3A3g== X-Google-Smtp-Source: AKy350aoBfINHni9q0yvD+Er5kTUinmfH8vzEUfRMwAxhiujMY6VnoEFjgXuXbGyw585OmCV0M+xUw== X-Received: by 2002:a05:600c:3783:b0:3f0:a9b1:81e0 with SMTP id o3-20020a05600c378300b003f0a9b181e0mr6822091wmr.19.1682315074448; Sun, 23 Apr 2023 22:44:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 48/57] tcg/loongarch64: Simplify constraints on qemu_ld/st Date: Mon, 24 Apr 2023 06:40:56 +0100 Message-Id: <20230424054105.1579315-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315799451100003 Content-Type: text/plain; charset="utf-8" The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 2 -- tcg/loongarch64/tcg-target-con-str.h | 1 - tcg/loongarch64/tcg-target.c.inc | 23 ++++------------------- 3 files changed, 4 insertions(+), 22 deletions(-) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-tar= get-con-set.h index 172c107289..c2bde44613 100644 --- a/tcg/loongarch64/tcg-target-con-set.h +++ b/tcg/loongarch64/tcg-target-con-set.h @@ -17,9 +17,7 @@ C_O0_I1(r) C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) -C_O0_I2(LZ, L) C_O1_I1(r, r) -C_O1_I1(r, L) C_O1_I2(r, r, rC) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) diff --git a/tcg/loongarch64/tcg-target-con-str.h b/tcg/loongarch64/tcg-tar= get-con-str.h index 541ff47fa9..6e9ccca3ad 100644 --- a/tcg/loongarch64/tcg-target-con-str.h +++ b/tcg/loongarch64/tcg-target-con-str.h @@ -14,7 +14,6 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) -REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 60d2c904dd..83fa45c802 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -133,18 +133,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKi= nd kind, int slot) #define TCG_CT_CONST_C12 0x1000 #define TCG_CT_CONST_WSZ 0x2000 =20 -#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) -/* - * For softmmu, we need to avoid conflicts with the first 5 - * argument registers to call the helper. Some of these are - * also used for the tlb lookup. - */ -#ifdef CONFIG_SOFTMMU -#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5) -#else -#define SOFTMMU_RESERVE_REGS 0 -#endif - +#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) =20 static inline tcg_target_long sextreg(tcg_target_long val, int pos, int le= n) { @@ -1541,16 +1530,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) case INDEX_op_st32_i64: case INDEX_op_st_i32: case INDEX_op_st_i64: + case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st_i64: return C_O0_I2(rZ, r); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: return C_O0_I2(rZ, rZ); =20 - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_st_i64: - return C_O0_I2(LZ, L); - case INDEX_op_ext8s_i32: case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: @@ -1586,11 +1573,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_ld32u_i64: case INDEX_op_ld_i32: case INDEX_op_ld_i64: - return C_O1_I1(r, r); - case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return C_O1_I1(r, L); + return C_O1_I1(r, r); =20 case INDEX_op_andc_i32: case INDEX_op_andc_i64: --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315470; cv=none; d=zohomail.com; s=zohoarc; b=cfXXCZoBjy3etJ98+VHlfQks7x7l7oErs22Uv4rnRquJtt7NXobb+rA52PogFiD+AfB5tXgGPtq8nqTopdlwQZV3yxTXPeMyT2nxrs90hnX87k4W6r6rWSuWyveUKlbdNVQRbvqM+xDcpYfuDOLgZ0vQ82meXzjG2RiAu+35ewM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315470; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aucysoTI00/6AHztRhanSz7uVuWer883go2thcLlz8w=; b=h56+sowrkwkLHPBY2PLl76OQt50SVDkoxm9/o3MwUuVgC/sI+3l/UZWUOSpW5gyzhMbPUYF9vZVMCUoGmjHnqHqefKSZY0GCjaFhWsDpH6sPm9ZW1vExTvrodfBXW2wqdWAIwD6rJRnOdnjfQcHE8JIKJYuJE2wbAciXV3kTK5Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315469968477.29138033795664; Sun, 23 Apr 2023 22:51:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqp4l-0006MF-3p; Mon, 24 Apr 2023 01:49:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqp0R-00064Y-Jo for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:44:56 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqp0F-0005K6-QG for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:44:54 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-3f1950f5628so26773645e9.3 for ; Sun, 23 Apr 2023 22:44:36 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id u6-20020adff886000000b002f7780eee10sm9986693wrp.59.2023.04.23.22.44.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:44:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682315075; x=1684907075; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aucysoTI00/6AHztRhanSz7uVuWer883go2thcLlz8w=; b=f3ep/6zd/1pwmG7tP+/zE4Ya3VpSttQCUxtm3oAypUb7D7452orcbRJYrKI9HSDvsY JuSxQ0vMpFg4qs6VCYrGODMhz2FV3ER4Ku8vz1BupKh56g3hSiAJwl83EXk2FGQtYSr5 vMhSbhOKeZOLoVKaBSqpoBoWH678tpZuizzJBx0sDQq3RkTp5SSdGQZTLMe1Nu+PMgsV YiNhQytqIiFlLHyjfTgiPmx6GLjM/Q9EVzZqQXo3KGDKGrrpKcj1H6yndY9n2N5fLLa1 5dnHsLIrMFCnwhFnkOK9UfYoqvrjfQxpHTR13qT3ZlsmKzuvYeNFgt12HgoUGKiA42ic Exug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682315075; x=1684907075; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aucysoTI00/6AHztRhanSz7uVuWer883go2thcLlz8w=; b=d2u1nwIl+eajMUAaSe6DrAkrcV9MIJYvGLI8emrMp44C01m1XEV4ZdIyYkYAE9CeIF kPpSuZc/9JOjkcOUunGoLsBKFofQ1euPvqt6+Tk/PdKsThCrnoN+cJ3x86XTuNCSyGrb 3DOZs4hEqBDETcMD/fijclTSVKsjeKeKSlc54tvhyNJ8/4eHsg4Ordi3ZiDxoq/I3PSP guG3xW06nHIT5pbX5+fi4zuv8fEmpGBbvVumqt6PVubysaLqHNIPTHdaV5cSrslZYZmd 2jkxvwwRbHRcKK+vBXGm7MvqgRKObac7IwvrXBQnOx4082PtpCMNWjWJfBK4XhYxWEIf XgJQ== X-Gm-Message-State: AAQBX9ey9FKm8F0SJrfw8OjDmz6G30ZSLxXZPfdf9OmrHdzH+v791xOF soKI5VjvIM9HfbpcQ3auxeTFdzaZ78rdfMfXWHSwKQ== X-Google-Smtp-Source: AKy350Z/gg08OfHL7L+Md4Cbp1vwuxU7urSI6higZwNcC53Dfn0ssCAUoiQMR4EJAiEkuxv8TU9d5w== X-Received: by 2002:a7b:c3d5:0:b0:3ee:b3bf:5f7c with SMTP id t21-20020a7bc3d5000000b003eeb3bf5f7cmr6642571wmj.23.1682315075069; Sun, 23 Apr 2023 22:44:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 49/57] tcg/mips: Remove MO_BSWAP handling Date: Mon, 24 Apr 2023 06:40:57 +0100 Message-Id: <20230424054105.1579315-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315471896100003 Content-Type: text/plain; charset="utf-8" While performing the load in the delay slot of the call to the common bswap helper function is cute, it is not worth the added complexity. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 4 +- tcg/mips/tcg-target.c.inc | 284 ++++++-------------------------------- 2 files changed, 48 insertions(+), 240 deletions(-) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 2431fc5353..42bd7fff01 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -204,8 +204,8 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_ext16u_i64 0 /* andi rt, rs, 0xffff */ #endif =20 -#define TCG_TARGET_DEFAULT_MO (0) -#define TCG_TARGET_HAS_MEMORY_BSWAP 1 +#define TCG_TARGET_DEFAULT_MO 0 +#define TCG_TARGET_HAS_MEMORY_BSWAP 0 =20 #define TCG_TARGET_NEED_LDST_LABELS =20 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 022960d79a..31d58e1977 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1088,31 +1088,35 @@ static void tcg_out_call(TCGContext *s, const tcg_i= nsn_unit *arg, } =20 #if defined(CONFIG_SOFTMMU) -static void * const qemu_ld_helpers[(MO_SSIZE | MO_BSWAP) + 1] =3D { +static void * const qemu_ld_helpers[MO_SSIZE + 1] =3D { [MO_UB] =3D helper_ret_ldub_mmu, [MO_SB] =3D helper_ret_ldsb_mmu, - [MO_LEUW] =3D helper_le_lduw_mmu, - [MO_LESW] =3D helper_le_ldsw_mmu, - [MO_LEUL] =3D helper_le_ldul_mmu, - [MO_LEUQ] =3D helper_le_ldq_mmu, - [MO_BEUW] =3D helper_be_lduw_mmu, - [MO_BESW] =3D helper_be_ldsw_mmu, - [MO_BEUL] =3D helper_be_ldul_mmu, - [MO_BEUQ] =3D helper_be_ldq_mmu, -#if TCG_TARGET_REG_BITS =3D=3D 64 - [MO_LESL] =3D helper_le_ldsl_mmu, - [MO_BESL] =3D helper_be_ldsl_mmu, +#if HOST_BIG_ENDIAN + [MO_UW] =3D helper_be_lduw_mmu, + [MO_SW] =3D helper_be_ldsw_mmu, + [MO_UL] =3D helper_be_ldul_mmu, + [MO_SL] =3D helper_be_ldsl_mmu, + [MO_UQ] =3D helper_be_ldq_mmu, +#else + [MO_UW] =3D helper_le_lduw_mmu, + [MO_SW] =3D helper_le_ldsw_mmu, + [MO_UL] =3D helper_le_ldul_mmu, + [MO_UQ] =3D helper_le_ldq_mmu, + [MO_SL] =3D helper_le_ldsl_mmu, #endif }; =20 -static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] =3D { +static void * const qemu_st_helpers[MO_SIZE + 1] =3D { [MO_UB] =3D helper_ret_stb_mmu, - [MO_LEUW] =3D helper_le_stw_mmu, - [MO_LEUL] =3D helper_le_stl_mmu, - [MO_LEUQ] =3D helper_le_stq_mmu, - [MO_BEUW] =3D helper_be_stw_mmu, - [MO_BEUL] =3D helper_be_stl_mmu, - [MO_BEUQ] =3D helper_be_stq_mmu, +#if HOST_BIG_ENDIAN + [MO_UW] =3D helper_be_stw_mmu, + [MO_UL] =3D helper_be_stl_mmu, + [MO_UQ] =3D helper_be_stq_mmu, +#else + [MO_UW] =3D helper_le_stw_mmu, + [MO_UL] =3D helper_le_stl_mmu, + [MO_UQ] =3D helper_le_stq_mmu, +#endif }; =20 /* We have four temps, we might as well expose three of them. */ @@ -1134,7 +1138,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) =20 tcg_out_ld_helper_args(s, l, &ldst_helper_param); =20 - tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], fals= e); + tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); /* delay slot */ tcg_out_nop(s); =20 @@ -1164,7 +1168,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) =20 tcg_out_st_helper_args(s, l, &ldst_helper_param); =20 - tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], false= ); + tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); /* delay slot */ tcg_out_nop(s); =20 @@ -1379,52 +1383,19 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, TCGReg base, MemOp opc, TCGType type) { - switch (opc & (MO_SSIZE | MO_BSWAP)) { + switch (opc & MO_SSIZE) { case MO_UB: tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); break; case MO_SB: tcg_out_opc_imm(s, OPC_LB, lo, base, 0); break; - case MO_UW | MO_BSWAP: - tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); - tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OZ); - break; case MO_UW: tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); break; - case MO_SW | MO_BSWAP: - tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); - tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OS); - break; case MO_SW: tcg_out_opc_imm(s, OPC_LH, lo, base, 0); break; - case MO_UL | MO_BSWAP: - if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64) { - if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); - tcg_out_bswap32(s, lo, lo, TCG_BSWAP_IZ | TCG_BSWAP_OZ); - } else { - tcg_out_bswap_subr(s, bswap32u_addr); - /* delay slot */ - tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0); - tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); - } - break; - } - /* FALLTHRU */ - case MO_SL | MO_BSWAP: - if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, OPC_LW, lo, base, 0); - tcg_out_bswap32(s, lo, lo, 0); - } else { - tcg_out_bswap_subr(s, bswap32_addr); - /* delay slot */ - tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); - tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3); - } - break; case MO_UL: if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64) { tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); @@ -1434,35 +1405,6 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TC= GReg lo, TCGReg hi, case MO_SL: tcg_out_opc_imm(s, OPC_LW, lo, base, 0); break; - case MO_UQ | MO_BSWAP: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, OPC_LD, lo, base, 0); - tcg_out_bswap64(s, lo, lo); - } else { - tcg_out_bswap_subr(s, bswap64_addr); - /* delay slot */ - tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0); - tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); - } - } else if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); - tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); - tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); - tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); - } else { - tcg_out_bswap_subr(s, bswap32_addr); - /* delay slot */ - tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); - tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4); - tcg_out_bswap_subr(s, bswap32_addr); - /* delay slot */ - tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); - tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); - } - break; case MO_UQ: /* Prefer to load from offset 0 first, but allow for overlap. */ if (TCG_TARGET_REG_BITS =3D=3D 64) { @@ -1487,25 +1429,20 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, = TCGReg lo, TCGReg hi, const MIPSInsn lw2 =3D MIPS_BE ? OPC_LWR : OPC_LWL; const MIPSInsn ld1 =3D MIPS_BE ? OPC_LDL : OPC_LDR; const MIPSInsn ld2 =3D MIPS_BE ? OPC_LDR : OPC_LDL; + bool sgn =3D opc & MO_SIGN; =20 - bool sgn =3D (opc & MO_SIGN); - - switch (opc & (MO_SSIZE | MO_BSWAP)) { - case MO_SW | MO_BE: - case MO_UW | MO_BE: - tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); - tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); - if (use_mips32r2_instructions) { - tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); - } else { - tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); - tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); - } - break; - - case MO_SW | MO_LE: - case MO_UW | MO_LE: - if (use_mips32r2_instructions && lo !=3D base) { + switch (opc & MO_SIZE) { + case MO_16: + if (HOST_BIG_ENDIAN) { + tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); + tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); + if (use_mips32r2_instructions) { + tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); + } else { + tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); + tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0); + } + } else if (use_mips32r2_instructions && lo !=3D base) { tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); @@ -1517,8 +1454,7 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TC= GReg lo, TCGReg hi, } break; =20 - case MO_SL: - case MO_UL: + case MO_32: tcg_out_opc_imm(s, lw1, lo, base, 0); tcg_out_opc_imm(s, lw2, lo, base, 3); if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64 && != sgn) { @@ -1526,28 +1462,7 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, T= CGReg lo, TCGReg hi, } break; =20 - case MO_UL | MO_BSWAP: - case MO_SL | MO_BSWAP: - if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, lw1, lo, base, 0); - tcg_out_opc_imm(s, lw2, lo, base, 3); - tcg_out_bswap32(s, lo, lo, - TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D T= CG_TYPE_I64 - ? (sgn ? TCG_BSWAP_OS : TCG_BSWAP_OZ) : 0); - } else { - const tcg_insn_unit *subr =3D - (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64= && !sgn - ? bswap32u_addr : bswap32_addr); - - tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0); - tcg_out_bswap_subr(s, subr); - /* delay slot */ - tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 3); - tcg_out_mov(s, type, lo, TCG_TMP3); - } - break; - - case MO_UQ: + case MO_64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_opc_imm(s, ld1, lo, base, 0); tcg_out_opc_imm(s, ld2, lo, base, 7); @@ -1559,42 +1474,6 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, T= CGReg lo, TCGReg hi, } break; =20 - case MO_UQ | MO_BSWAP: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, ld1, lo, base, 0); - tcg_out_opc_imm(s, ld2, lo, base, 7); - tcg_out_bswap64(s, lo, lo); - } else { - tcg_out_opc_imm(s, ld1, TCG_TMP0, base, 0); - tcg_out_bswap_subr(s, bswap64_addr); - /* delay slot */ - tcg_out_opc_imm(s, ld2, TCG_TMP0, base, 7); - tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); - } - } else if (use_mips32r2_instructions) { - tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0); - tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3); - tcg_out_opc_imm(s, lw1, TCG_TMP1, base, 4 + 0); - tcg_out_opc_imm(s, lw2, TCG_TMP1, base, 4 + 3); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); - tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); - tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); - } else { - tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0); - tcg_out_bswap_subr(s, bswap32_addr); - /* delay slot */ - tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3); - tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 4 + 0); - tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); - tcg_out_bswap_subr(s, bswap32_addr); - /* delay slot */ - tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 4 + 3); - tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); - } - break; - default: g_assert_not_reached(); } @@ -1627,50 +1506,16 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= atalo, TCGReg datahi, static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, TCGReg base, MemOp opc) { - /* Don't clutter the code below with checks to avoid bswapping ZERO. = */ - if ((lo | hi) =3D=3D 0) { - opc &=3D ~MO_BSWAP; - } - - switch (opc & (MO_SIZE | MO_BSWAP)) { + switch (opc & MO_SIZE) { case MO_8: tcg_out_opc_imm(s, OPC_SB, lo, base, 0); break; - - case MO_16 | MO_BSWAP: - tcg_out_bswap16(s, TCG_TMP1, lo, 0); - lo =3D TCG_TMP1; - /* FALLTHRU */ case MO_16: tcg_out_opc_imm(s, OPC_SH, lo, base, 0); break; - - case MO_32 | MO_BSWAP: - tcg_out_bswap32(s, TCG_TMP3, lo, 0); - lo =3D TCG_TMP3; - /* FALLTHRU */ case MO_32: tcg_out_opc_imm(s, OPC_SW, lo, base, 0); break; - - case MO_64 | MO_BSWAP: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_bswap64(s, TCG_TMP3, lo); - tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0); - } else if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo); - tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); - tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); - tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0); - tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4); - } else { - tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0); - tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0); - tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0); - tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4); - } - break; case MO_64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_opc_imm(s, OPC_SD, lo, base, 0); @@ -1679,7 +1524,6 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4); } break; - default: g_assert_not_reached(); } @@ -1693,54 +1537,18 @@ static void tcg_out_qemu_st_unalign(TCGContext *s, = TCGReg lo, TCGReg hi, const MIPSInsn sd1 =3D MIPS_BE ? OPC_SDL : OPC_SDR; const MIPSInsn sd2 =3D MIPS_BE ? OPC_SDR : OPC_SDL; =20 - /* Don't clutter the code below with checks to avoid bswapping ZERO. = */ - if ((lo | hi) =3D=3D 0) { - opc &=3D ~MO_BSWAP; - } - - switch (opc & (MO_SIZE | MO_BSWAP)) { - case MO_16 | MO_BE: + switch (opc & MO_SIZE) { + case MO_16: tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); - tcg_out_opc_imm(s, OPC_SB, TCG_TMP0, base, 0); - tcg_out_opc_imm(s, OPC_SB, lo, base, 1); + tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, = 0); + tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, = 1); break; =20 - case MO_16 | MO_LE: - tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); - tcg_out_opc_imm(s, OPC_SB, lo, base, 0); - tcg_out_opc_imm(s, OPC_SB, TCG_TMP0, base, 1); - break; - - case MO_32 | MO_BSWAP: - tcg_out_bswap32(s, TCG_TMP3, lo, 0); - lo =3D TCG_TMP3; - /* fall through */ case MO_32: tcg_out_opc_imm(s, sw1, lo, base, 0); tcg_out_opc_imm(s, sw2, lo, base, 3); break; =20 - case MO_64 | MO_BSWAP: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_bswap64(s, TCG_TMP3, lo); - lo =3D TCG_TMP3; - } else if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? hi : lo); - tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? lo : hi); - tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); - tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); - hi =3D MIPS_BE ? TCG_TMP0 : TCG_TMP1; - lo =3D MIPS_BE ? TCG_TMP1 : TCG_TMP0; - } else { - tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0); - tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 0 + 0); - tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 0 + 3); - tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0); - tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 4 + 0); - tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 4 + 3); - break; - } - /* fall through */ case MO_64: if (TCG_TARGET_REG_BITS =3D=3D 64) { tcg_out_opc_imm(s, sd1, lo, base, 0); --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315519; cv=none; d=zohomail.com; s=zohoarc; b=nZZyDCRfHnc4mStVg1dI39unJ1DJradEdqc4QO/P6eQU1oDB5HMNQljh7L3IT7gez1Ow5OgXRLzZ8auNU4FjJfHofBb44DmrDmTd5LmGtBNVKPe4mmo1tJoaR194lEOI5gSGEEgj3SpDyfw+g6AZJMDyPFSfXZO699bWLoyZ/tg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315519; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=64H1HdxJ2Vo9fMDDBGxTfjpGZYN3L1dEu1eUYP7zZpo=; b=eEpchcT3iF5z0uEGGfGPM7QijB/iFTPsNYW0CVfx1BAg20rS7/jdg9P6AAvko9ZrafGUSVECSd3SOI8TeH9zTQkyAYfT738tkxSAziVYqbCPC4tpFS4lKIg95JL3M5lPpM9fsTfX0BteRcqakVHbtiuRYX2BPlMinWwiC3V/t5o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315519340896.6478054418683; Sun, 23 Apr 2023 22:51:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqp2o-0002hX-5v; Mon, 24 Apr 2023 01:47:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqp0K-00060T-6L for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:44:56 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqp0A-0005KI-Fb for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:44:47 -0400 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-2f46348728eso2305188f8f.3 for ; Sun, 23 Apr 2023 22:44:36 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id u6-20020adff886000000b002f7780eee10sm9986693wrp.59.2023.04.23.22.44.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:44:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682315075; x=1684907075; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=64H1HdxJ2Vo9fMDDBGxTfjpGZYN3L1dEu1eUYP7zZpo=; b=jW+j/ruRCg+N/1a11czPzEPC2rYJvzloAUY9AtbAuCTRTBuI6JN2rFR4YyiMC9Ow/y nmmHjD/uaUXCkaatLY8mH52268drwwZTPmhfzJk+HRzllso5DGbat/anPqqdg9DSBG03 pj6BwUfLay6zc6yotD6Y/66U9FWLYS+0u9/fNN8qhGi/WwlTqe1aXWyzixQ5sTm3K1PS eO6nu/CRYv884N9h8lWw5V/W3hD0xCJW4STE4gmvXAmEwQlh33L6fCoCOpZz89y9AMmz 9ZzVzqEhfwDvm7+n5sVTP+d7wlw8RVV+I+aOPpHlW7jThkrP3iEYe4rSDGfdWhv4Ull5 YgKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682315075; x=1684907075; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=64H1HdxJ2Vo9fMDDBGxTfjpGZYN3L1dEu1eUYP7zZpo=; b=iKSB6KurZaM1X3N5UJOnYne3a9KOlwIdT8XHmi0/PetnufgaOEEaTzIh0/2/T4wS9+ 0XpKX6Lme/jefofgyA4FTNYDOE1vKMaLfvzBAT0/MzXPBAgWWkEmefU41wbvR6wNJ4p2 K7CsFAA24NnI7Eysuaaxten1ZktL5PSyh49PLxRU/o85v2x0z1EY0onE7Vps8Y4vWtnq KkokxalmUEe2bEyd91DOT1C2xVy5sZRcXNOcoRJ8ZtoOb4+xpUuR80kHa5fO4rb8HbZX LEc0hjsiKI8ETPb6XLS+MxwBoT3R2yV4Nml47DisuBnzWPqzDhQ3mWxYVli3u0GU1+vv +fWg== X-Gm-Message-State: AAQBX9cNxvVhvWW+ZYhPxOA5goqz8nNSKsiPBpHi115NGXPBLLyZSd4j DNbkOpULYMbWg7AeVrXp7GTZCr04VfSJaZoWBS4bsA== X-Google-Smtp-Source: AKy350ZUYb5t0OjdojhGq4w6kUFpnU1vf2hsTIMb+sKb2MGlGYBktGLd9P+UxnDU2geGa4ATsplhaA== X-Received: by 2002:a05:6000:1290:b0:2f9:1224:2474 with SMTP id f16-20020a056000129000b002f912242474mr8489859wrx.23.1682315075672; Sun, 23 Apr 2023 22:44:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 50/57] tcg/mips: Reorg tlb load within prepare_host_addr Date: Mon, 24 Apr 2023 06:40:58 +0100 Message-Id: <20230424054105.1579315-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315521034100003 Content-Type: text/plain; charset="utf-8" Compare the address vs the tlb entry with sign-extended values. This simplifies the page+alignment mask constant, and the generation of the last byte address for the misaligned test. Move the tlb addend load up, and the zero-extension down. This frees up a register, which allows us use TMP3 as the returned base address register instead of A0, which we were using as a 5th temporary. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 38 ++++++++++++++++++-------------------- 1 file changed, 18 insertions(+), 20 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 31d58e1977..695c137023 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -370,6 +370,8 @@ typedef enum { ALIAS_PADDI =3D sizeof(void *) =3D=3D 4 ? OPC_ADDIU : OPC_DADDIU, ALIAS_TSRL =3D TARGET_LONG_BITS =3D=3D 32 || TCG_TARGET_REG_BITS = =3D=3D 32 ? OPC_SRL : OPC_DSRL, + ALIAS_TADDI =3D TARGET_LONG_BITS =3D=3D 32 || TCG_TARGET_REG_BITS = =3D=3D 32 + ? OPC_ADDIU : OPC_DADDIU, } MIPSInsn; =20 /* @@ -1263,14 +1265,12 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, int add_off =3D offsetof(CPUTLBEntry, addend); int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write); - target_ulong tlb_mask; =20 ldst =3D new_ldst_label(s); ldst->is_ld =3D is_ld; ldst->oi =3D oi; ldst->addrlo_reg =3D addrlo; ldst->addrhi_reg =3D addrhi; - base =3D TCG_REG_A0; =20 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); @@ -1290,15 +1290,12 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); } else { - tcg_out_ldst(s, (TARGET_LONG_BITS =3D=3D 64 ? OPC_LD - : TCG_TARGET_REG_BITS =3D=3D 64 ? OPC_LWU : OPC_L= W), - TCG_TMP0, TCG_TMP3, cmp_off); + tcg_out_ld(s, TCG_TYPE_TL, TCG_TMP0, TCG_TMP3, cmp_off); } =20 - /* Zero extend a 32-bit guest address for a 64-bit host. */ - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addrlo); - addrlo =3D base; + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + /* Load the tlb addend for the fast path. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); } =20 /* @@ -1306,18 +1303,18 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, * For unaligned accesses, compare against the end of the access to * verify that it does not cross a page boundary. */ - tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; - tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, tlb_mask); - if (a_mask >=3D s_mask) { - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo); - } else { - tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP2, addrlo, s_mask - a_mask); + tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, TARGET_PAGE_MASK | a_mask); + if (a_mask < s_mask) { + tcg_out_opc_imm(s, ALIAS_TADDI, TCG_TMP2, addrlo, s_mask - a_mask); tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); + } else { + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo); } =20 - if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { - /* Load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); + /* Zero extend a 32-bit guest address for a 64-bit host. */ + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_TMP2, addrlo); + addrlo =3D TCG_TMP2; } =20 ldst->label_ptr[0] =3D s->code_ptr; @@ -1329,14 +1326,15 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); =20 /* Load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); =20 ldst->label_ptr[1] =3D s->code_ptr; tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0); } =20 /* delay slot */ - tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrlo); + base =3D TCG_TMP3; + tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo); #else if (a_mask && (use_mips32r6_instructions || a_bits !=3D s_bits)) { ldst =3D new_ldst_label(s); --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315853; cv=none; d=zohomail.com; s=zohoarc; b=NUp9CXoZ3CXxRuOYeeYcQss3sGwyhnIX0iPxJYbqnqfbQbYRVlPFaFiHSSWalcezt38wwLwoQxtjwKZXt0odc0vM2liqY6ES1+A5dkovEHj6sa2JqUDNN10FuKlmpx8HhsLPVawKGsIAPGiPk++EgKJDaixTAA9q1A3clUPK8qo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315853; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=k8auTOlyLXqTfCckvUiWN7Zc35mefBco1qqtfpVHTz4=; b=Jyise5G3cLUUuM0gG7xswByaiZZIpQ3iWdArFE8unQSUo9NtTpFxqJyLWEKfevmvnL1nY/sMlgXqwHySG8/cUku4conPpcbKvplewY0ScpjbINBkdbTKcvVgo1jlEvis0eF3kVvHNLIcIYYF4aYZscAKcn0bFRY4RnKURFpuZe8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315853175888.9128848463745; Sun, 23 Apr 2023 22:57:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqp4i-0006Hy-Jp; Mon, 24 Apr 2023 01:49:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqp0k-0006O3-91 for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:45:19 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqp0H-0005Kh-Vf for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:45:13 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-3f19c473b9eso30783525e9.0 for ; Sun, 23 Apr 2023 22:44:37 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id u6-20020adff886000000b002f7780eee10sm9986693wrp.59.2023.04.23.22.44.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:44:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682315076; x=1684907076; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=k8auTOlyLXqTfCckvUiWN7Zc35mefBco1qqtfpVHTz4=; b=Yq71wfiIl9tZ2CcABXmqp+Jj+f+6FnbojU+FVLL5tX86chUHYpQNq7MNCtwRe1X5hl KqqQqIk6VPCgdXJJCp0kWL4uyGY1IWrO9NRJNg1l1Mlj/0Y3qEZSDN90Jy/rM0SSuzbz f+jNy4E9eIM3nlrF6ZiFziyd+uOTnsIwDGEB5IEnLVMnOA9MEuSOQBfoKEuUlfcN3Nik zDmTeH06BVXZTPNeHRlFjOaiSlZ9ewWo4Mfxl0WkelotEVL/1QbETMAzdq+GY90dKN/J alq9stHHHInr0FC1y3BngygMkqeEOOOlQT/+ppaSUI2BvLMT/WXgDOAdkDbk/1ENcJ7V aRBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682315076; x=1684907076; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k8auTOlyLXqTfCckvUiWN7Zc35mefBco1qqtfpVHTz4=; b=PuCcmv69jH32JSHHRuz2LPr6s3pz+HSnr7kJu+2xfJdrkEygcI6VZdC5Q4JMQKT094 xlr9/BUhm+5Q9gHOVyzzRtK0ey/OBykDadAA1Tmji9TrM6EFU170fdVKQjegEHtZx4nj K4l591vAxg5o34phg2/CnEK7LfdPl4CoRVUD1K/lHPtIotyijYdbPatAwgp6Jjyb4Jp2 dC2t9D94F95bxCQEeqJW0vNXHaOLvDjgdmEsgPfuwBSgMPtc1QA5yw9xaCMSEtZLIg6J EMMHU0oD4EYD7wsM176zgZkAEJtgbAlCM5PVP7EsGfdcyMR+4MNsUC2uOEDpEBeDoUIg ++Tw== X-Gm-Message-State: AAQBX9ebNIMZzF6XW64ZyeVarOGr8nyr/58IG637Hl5fmWT5KX08bI+v PvxzhNW1ArBxs1Eyjs9VRpojjBBXQiE5KEiN1kFV7A== X-Google-Smtp-Source: AKy350a/S7pnnHQyi3InFQxE9nHIOTsIdd8lZyPjTdn9VWhB5uYAekSTTdqicQnxqhxFiPPvDgg4Vg== X-Received: by 2002:a1c:7912:0:b0:3f1:94e2:e5bc with SMTP id l18-20020a1c7912000000b003f194e2e5bcmr6366520wme.11.1682315076267; Sun, 23 Apr 2023 22:44:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 51/57] tcg/mips: Simplify constraints on qemu_ld/st Date: Mon, 24 Apr 2023 06:40:59 +0100 Message-Id: <20230424054105.1579315-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315853863100001 Content-Type: text/plain; charset="utf-8" The softmmu tlb uses TCG_REG_TMP[0-3], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, and have eliminated use of A0, we can allow any allocatable reg. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-con-set.h | 13 +++++-------- tcg/mips/tcg-target-con-str.h | 2 -- tcg/mips/tcg-target.c.inc | 30 ++++++++---------------------- 3 files changed, 13 insertions(+), 32 deletions(-) diff --git a/tcg/mips/tcg-target-con-set.h b/tcg/mips/tcg-target-con-set.h index fe3e868a2f..864034f468 100644 --- a/tcg/mips/tcg-target-con-set.h +++ b/tcg/mips/tcg-target-con-set.h @@ -12,15 +12,13 @@ C_O0_I1(r) C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) -C_O0_I2(SZ, S) -C_O0_I3(SZ, S, S) -C_O0_I3(SZ, SZ, S) +C_O0_I3(rZ, r, r) +C_O0_I3(rZ, rZ, r) C_O0_I4(rZ, rZ, rZ, rZ) -C_O0_I4(SZ, SZ, S, S) -C_O1_I1(r, L) +C_O0_I4(rZ, rZ, r, r) C_O1_I1(r, r) C_O1_I2(r, 0, rZ) -C_O1_I2(r, L, L) +C_O1_I2(r, r, r) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) C_O1_I2(r, r, rIK) @@ -30,7 +28,6 @@ C_O1_I2(r, rZ, rN) C_O1_I2(r, rZ, rZ) C_O1_I4(r, rZ, rZ, rZ, 0) C_O1_I4(r, rZ, rZ, rZ, rZ) -C_O2_I1(r, r, L) -C_O2_I2(r, r, L, L) +C_O2_I1(r, r, r) C_O2_I2(r, r, r, r) C_O2_I4(r, r, rZ, rZ, rN, rN) diff --git a/tcg/mips/tcg-target-con-str.h b/tcg/mips/tcg-target-con-str.h index e4b2965c72..413c280a7a 100644 --- a/tcg/mips/tcg-target-con-str.h +++ b/tcg/mips/tcg-target-con-str.h @@ -9,8 +9,6 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) -REGS('L', ALL_QLOAD_REGS) -REGS('S', ALL_QSTORE_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 695c137023..5ad9867882 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -176,20 +176,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, #define TCG_CT_CONST_WSZ 0x2000 /* word size */ =20 #define ALL_GENERAL_REGS 0xffffffffu -#define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0)) - -#ifdef CONFIG_SOFTMMU -#define ALL_QLOAD_REGS \ - (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2)) -#define ALL_QSTORE_REGS \ - (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \ - ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \ - : (1 << TCG_REG_A1))) -#else -#define ALL_QLOAD_REGS NOA0_REGS -#define ALL_QSTORE_REGS NOA0_REGS -#endif - =20 static bool is_p2m1(tcg_target_long val) { @@ -2232,18 +2218,18 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_qemu_ld_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); + ? C_O1_I1(r, r) : C_O1_I2(r, r, r)); case INDEX_op_qemu_st_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S)); + ? C_O0_I2(rZ, r) : C_O0_I3(rZ, r, r)); case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) - : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(r, r, L) - : C_O2_I2(r, r, L, L)); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) + : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(r, r, r) + : C_O2_I2(r, r, r, r)); case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(SZ, S) - : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(SZ, SZ, S) - : C_O0_I4(SZ, SZ, S, S)); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(rZ, r) + : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(rZ, rZ, r) + : C_O0_I4(rZ, rZ, r, r)); =20 default: g_assert_not_reached(); --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315265; cv=none; d=zohomail.com; s=zohoarc; b=cPYleEppmCQJ849GPuriQzHcPECRfF/VZIz3o1yPlwP0IhNUvSY6M5QAkCfTcR834eZnGfytyC0ayx+MEPZbj+XFdtNiQvnjkfad8/x5NqlNpqklNnJnLO8YmhO8fr0M4efKJvhAXFdne6se0DLxGZWKdSLl+ba5id7bGMN9R1M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315265; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eTTppFvpCeQOyLgVasYHuYDrv+swYGMzo0e4SF2rHxM=; b=Mheq6EvjdVsOMVc8ym448EErVUYJRc3MqGUC4wb2/SSEUsTa4+Y/JyQQmJb0tdNpNVJ3PHmdOzcDu4KTGc0N/+Tuex2lBiv1DIg5BVCQlpix56fIkyAZeJqP7uWN1uGohDYRh2gB5W7ndg2IeFK1v6Fj+fBseUOeJ3lkK5KXL7c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16823152650261015.8507958603134; Sun, 23 Apr 2023 22:47:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqp2Z-0001Pr-LW; Mon, 24 Apr 2023 01:47:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqp0P-00064T-B8 for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:44:56 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqp0F-0005L5-OA for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:44:52 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3f19a80a330so9376865e9.2 for ; Sun, 23 Apr 2023 22:44:37 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id u6-20020adff886000000b002f7780eee10sm9986693wrp.59.2023.04.23.22.44.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:44:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682315077; x=1684907077; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eTTppFvpCeQOyLgVasYHuYDrv+swYGMzo0e4SF2rHxM=; b=HrKLf2/t3FDOmOgY10zUvxxBO0MJrTaxEk5y+MqO4xy6XU6Je2VpIWa+m64bz0nPxM KhgY/nnKMlBGyV6cnMXa6I6sCIkXFU68ITiBwjsNgnuEcox7YlkZAPEgygknYeC36VFe afW0ED0DB2MW/MNASoOY1eQ0tcy3iFvXLb1XCY1Wp57EkK6MvSsh6m43b5/URFQyKZEm pCInQE/hnjG+I58OF/fziAUy3pPDxdsBaJTrz0VzhtULosXRbHjWwfDW4wlb7GHMAMEC 3eTSPkqUwvIOPGpiVa/ll6ok9sKfZ9oAr/0zQAAlsLP1KGhZX6rwyQjnpgQ/SfFzjqDe JAPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682315077; x=1684907077; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eTTppFvpCeQOyLgVasYHuYDrv+swYGMzo0e4SF2rHxM=; b=TgEddckXBfg2LVMxIxbfiLYjJV4xm8bEL3orvFhNBxheEvk1bppvMHmPn496ATzopl RkwLWnSd3WJ9XiE9085SB4NHyJxtRBj+IvpSysQ7yliUobXfGtDlOViTcekrY4WyFz8t W02rOd6gosDoEQoAe6t75CawdMQzk7L3mi6B/FbX31ZTgBTCvekfCCVolz+WLDOQMNQd phjdajYLne5yIpSMizURr1lHWXLjcFlmZ2rVv6eVAqNshxpUdJEgkjZSX/3zjJ6aGeUr yUmMLeb6adLWIzw7GCXCCcDFaSdZ7Bo1bm0HopG29hcvW39uiAcQWqyQ/3oOqAdS4gyw 3wVg== X-Gm-Message-State: AAQBX9cJV5q0cm4H+8tourmwmew0b06SdzcpHOxowIHV93yooizjVRYy IrtWBtKfisvaF+PHSH/vmCLiMXWANBIGOjJwgcEi7A== X-Google-Smtp-Source: AKy350ZNHjCtInLgUl9HZ8yC/K5OWsQ7UuL2iaMbgUyrEtZnQEKDr2udlSmRbzXQ9JSBMCwo7hISrg== X-Received: by 2002:a7b:cb96:0:b0:3f0:5519:9049 with SMTP id m22-20020a7bcb96000000b003f055199049mr7136363wmi.8.1682315076840; Sun, 23 Apr 2023 22:44:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com, Daniel Henrique Barboza Subject: [PATCH v3 52/57] tcg/ppc: Reorg tcg_out_tlb_read Date: Mon, 24 Apr 2023 06:41:00 +0100 Message-Id: <20230424054105.1579315-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315266274100003 Content-Type: text/plain; charset="utf-8" Allocate TCG_REG_TMP2. Use R0, TMP1, TMP2 instead of any of the normally allocated registers for the tlb load. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 84 ++++++++++++++++++++++++---------------- 1 file changed, 51 insertions(+), 33 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 042136fee7..6850ecbc80 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -68,6 +68,7 @@ #else # define TCG_REG_TMP1 TCG_REG_R12 #endif +#define TCG_REG_TMP2 TCG_REG_R11 =20 #define TCG_VEC_TMP1 TCG_REG_V0 #define TCG_VEC_TMP2 TCG_REG_V1 @@ -2015,13 +2016,11 @@ static TCGReg ldst_ra_gen(TCGContext *s, const TCGL= abelQemuLdst *l, int arg) /* * For the purposes of ppc32 sorting 4 input registers into 4 argument * registers, there is an outside chance we would require 3 temps. - * Because of constraints, no inputs are in r3, and env will not be - * placed into r3 until after the sorting is done, and is thus free. */ static const TCGLdstHelperParam ldst_helper_param =3D { .ra_gen =3D ldst_ra_gen, .ntmp =3D 3, - .tmp =3D { TCG_REG_TMP1, TCG_REG_R0, TCG_REG_R3 } + .tmp =3D { TCG_REG_TMP1, TCG_REG_TMP2, TCG_REG_R0 } }; =20 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) @@ -2135,41 +2134,44 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_AREG0, table_off); =20 /* Extract the page index, shifted into place for tlb index. */ if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_shri32(s, TCG_REG_TMP1, addrlo, + tcg_out_shri32(s, TCG_REG_R0, addrlo, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); } else { - tcg_out_shri64(s, TCG_REG_TMP1, addrlo, + tcg_out_shri64(s, TCG_REG_R0, addrlo, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); } - tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1)); + tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0)); =20 - /* Load the TLB comparator. */ + /* Load the (low part) TLB comparator into TMP2. */ if (cmp_off =3D=3D 0 && TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { uint32_t lxu =3D (TCG_TARGET_REG_BITS =3D=3D 32 || TARGET_LONG_BIT= S =3D=3D 32 ? LWZUX : LDUX); - tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4)); + tcg_out32(s, lxu | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2)); } else { - tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4)); + tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2)); if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off = + 4); - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, + TCG_REG_TMP1, cmp_off + 4 * HOST_BIG_ENDIAN); } else { - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off); + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off= ); } } =20 - /* Load the TLB addend for use on the fast path. Do this asap - to minimize any load use delay. */ - h->base =3D TCG_REG_R3; - tcg_out_ld(s, TCG_TYPE_PTR, h->base, TCG_REG_R3, - offsetof(CPUTLBEntry, addend)); + /* + * Load the TLB addend for use on the fast path. + * Do this asap to minimize any load use delay. + */ + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, + offsetof(CPUTLBEntry, addend)); + } =20 - /* Clear the non-page, non-alignment bits from the address */ + /* Clear the non-page, non-alignment bits from the address in R0. */ if (TCG_TARGET_REG_BITS =3D=3D 32) { /* We don't support unaligned accesses on 32-bits. * Preserve the bottom bits and thus trigger a comparison @@ -2200,9 +2202,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, if (TARGET_LONG_BITS =3D=3D 32) { tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); - /* Zero-extend the address for use in the final address. */ - tcg_out_ext32u(s, TCG_REG_R4, addrlo); - addrlo =3D TCG_REG_R4; } else if (a_bits =3D=3D 0) { tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS= ); } else { @@ -2211,21 +2210,36 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BIT= S, 0); } } - h->index =3D addrlo; =20 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, + /* Low part comparison into cr7. */ + tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 0, 7, TCG_TYPE_I32); - tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32= ); + + /* Load the high part TLB comparator into TMP2. */ + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1, + cmp_off + 4 * !HOST_BIG_ENDIAN); + + /* Load addend, deferred for this case. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, + offsetof(CPUTLBEntry, addend)); + + /* High part comparison into cr6. */ + tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_TMP2, 0, 6, TCG_TYPE_I= 32); + + /* Combine comparisons into cr7. */ tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); } else { - tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, + /* Full comparison into cr7. */ + tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 0, 7, TCG_TYPE_TL); } =20 /* Load a pointer into the current opcode w/conditional branch-link. */ ldst->label_ptr[0] =3D s->code_ptr; tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); + + h->base =3D TCG_REG_TMP1; #else if (a_bits) { ldst =3D new_ldst_label(s); @@ -2243,13 +2257,16 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, } =20 h->base =3D guest_base ? TCG_GUEST_BASE_REG : 0; - h->index =3D addrlo; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); - h->index =3D TCG_REG_TMP1; - } #endif =20 + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + /* Zero-extend the guest address for use in the host address. */ + tcg_out_ext32u(s, TCG_REG_R0, addrlo); + h->index =3D TCG_REG_R0; + } else { + h->index =3D addrlo; + } + return ldst; } =20 @@ -3901,7 +3918,8 @@ static void tcg_target_init(TCGContext *s) #if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS =3D=3D 64 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ #endif - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1); tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2); if (USE_REG_TB) { --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315417; cv=none; d=zohomail.com; s=zohoarc; b=JBBfhgweQEnZfWYxeU7GJ3bboFRZObkkQ+biXNhZy+YkQ4ccgZD1jBqR1pOQp0Xn/Gdte7hylflmodemDzBai1UKG/NFMZYefkjtBY8LxGJouwxb8rX5UxrrTvZ5csZVCTzf0T6biqT6eJgJcLW2w+oZuqSTMQTkC2tu4ej/EcA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315417; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=M0CeyWjMqe57NR22sbQHD4MYtLkRo2vj3jA4zBvWRdg=; b=cCIVCz7vtC4hkX3rgbDdyBr0VhgRa92TGE068eypVSxn6trSDBlSjTNG4yrdO8hCe4s29sZHLXn2rDVYPiDdgAK5fn7d1pHXUPj6nd/2luVDm6xS4p/LcRefJZDfQ+ERG+6tomaj/VA7ccqfr/vDRwqmcj7xoyz6L13n+nKinzU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315417184433.61556063003013; Sun, 23 Apr 2023 22:50:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqp4g-0006AA-4Z; Mon, 24 Apr 2023 01:49:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqp0S-00064b-0u for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:44:56 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqp0F-0005LJ-Q6 for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:44:54 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-3f18dacd392so22122875e9.0 for ; Sun, 23 Apr 2023 22:44:38 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id u6-20020adff886000000b002f7780eee10sm9986693wrp.59.2023.04.23.22.44.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:44:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682315077; x=1684907077; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=M0CeyWjMqe57NR22sbQHD4MYtLkRo2vj3jA4zBvWRdg=; b=x0O2MMXzuxtgXc98eVZyavVQrKe/c3yNwRazTZI2qt20MKQQGO23wXEn+iYQCQukUX FH/XGHUg55vSvxerxhce9yQMyhaz7RysUROXz8y0P1H1AwOcwCcEhsQnyb5Bw/O4Oqe6 eMFxYmTsVXrqJlxIqAk6TplfCgwWGBAEt5+bkexjpja5+T2DP4dP4IRNOwiToTILf46W 4RO2GsHZ9ao9zJI+allGQrOirAbTgb+X1VD5dZIFG3O70LJ14mSsdeFRMDQ0+mT8JfRx XHjW29XnElpqTnIHKZXlGbcLmk2l0c5u8wmtpSkCNPg2dxGVvCX8RdOKGeuytE6omb6r OgLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682315077; x=1684907077; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M0CeyWjMqe57NR22sbQHD4MYtLkRo2vj3jA4zBvWRdg=; b=iG8okiHb1eTbu7eA/hoTEqG2iq5Muy6fj+D+KDYz1dZLJvCQ0Ul8zFNDDh67uvulYP 989+tkBqBETKRG9EmN0dnDuytcfMI6biO4eeDufb4P0IbVTrqfGK/02A6yjz+BOxv8EX wHhFXWZfGpZW3xpb8Z9stROm0qcP/GfUb11OFoeDTY05Xx8vGLWoXt3MtaHTWJmB5cTL rurorYlP4e+d0gsfIV3oe4/1r+X8g02udKCAuA0AW3v+uO1uQz15W5vtYfM1+kEIPHN6 jLcXGaCeaIXzcU/RliQ29fZ7kb7qgA4zIhUQCD5i/C6mq3tnP4ueYtPPsDl094OZRImW xehQ== X-Gm-Message-State: AAQBX9cgNv0js887W8gNydvSwj0vNZ6wZDX7I0xTNz5irTGsPCU2vnpq Br17THFJ3+oAlE9I3+t/QAIflPo7PZcYisLS0RC4dA== X-Google-Smtp-Source: AKy350ZmP9Awwb+pNtW+/VgU3BIn5HW4YkL35er79DU0yjh4pan+ykBhfE4aJ0pH8X19cytncAVEaw== X-Received: by 2002:adf:f384:0:b0:2f2:9198:f0f with SMTP id m4-20020adff384000000b002f291980f0fmr8146842wro.10.1682315077408; Sun, 23 Apr 2023 22:44:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com, Daniel Henrique Barboza Subject: [PATCH v3 53/57] tcg/ppc: Adjust constraints on qemu_ld/st Date: Mon, 24 Apr 2023 06:41:01 +0100 Message-Id: <20230424054105.1579315-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315418639100003 Content-Type: text/plain; charset="utf-8" The softmmu tlb uses TCG_REG_{TMP1,TMP2,R0}, not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h | 11 ++++------- tcg/ppc/tcg-target-con-str.h | 2 -- tcg/ppc/tcg-target.c.inc | 32 ++++++++++---------------------- 3 files changed, 14 insertions(+), 31 deletions(-) diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h index a1a345883d..f206b29205 100644 --- a/tcg/ppc/tcg-target-con-set.h +++ b/tcg/ppc/tcg-target-con-set.h @@ -12,18 +12,15 @@ C_O0_I1(r) C_O0_I2(r, r) C_O0_I2(r, ri) -C_O0_I2(S, S) C_O0_I2(v, r) -C_O0_I3(S, S, S) +C_O0_I3(r, r, r) C_O0_I4(r, r, ri, ri) -C_O0_I4(S, S, S, S) -C_O1_I1(r, L) +C_O0_I4(r, r, r, r) C_O1_I1(r, r) C_O1_I1(v, r) C_O1_I1(v, v) C_O1_I1(v, vr) C_O1_I2(r, 0, rZ) -C_O1_I2(r, L, L) C_O1_I2(r, rI, ri) C_O1_I2(r, rI, rT) C_O1_I2(r, r, r) @@ -36,7 +33,7 @@ C_O1_I2(v, v, v) C_O1_I3(v, v, v, v) C_O1_I4(r, r, ri, rZ, rZ) C_O1_I4(r, r, r, ri, ri) -C_O2_I1(L, L, L) -C_O2_I2(L, L, L, L) +C_O2_I1(r, r, r) +C_O2_I2(r, r, r, r) C_O2_I4(r, r, rI, rZM, r, r) C_O2_I4(r, r, r, r, rI, rZM) diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h index 298ca20d5b..f3bf030bc3 100644 --- a/tcg/ppc/tcg-target-con-str.h +++ b/tcg/ppc/tcg-target-con-str.h @@ -14,8 +14,6 @@ REGS('A', 1u << TCG_REG_R3) REGS('B', 1u << TCG_REG_R4) REGS('C', 1u << TCG_REG_R5) REGS('D', 1u << TCG_REG_R6) -REGS('L', ALL_QLOAD_REGS) -REGS('S', ALL_QSTORE_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 6850ecbc80..5a4ec0470a 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -93,18 +93,6 @@ #define ALL_GENERAL_REGS 0xffffffffu #define ALL_VECTOR_REGS 0xffffffff00000000ull =20 -#ifdef CONFIG_SOFTMMU -#define ALL_QLOAD_REGS \ - (ALL_GENERAL_REGS & \ - ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5))) -#define ALL_QSTORE_REGS \ - (ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \ - (1 << TCG_REG_R5) | (1 << TCG_REG_R6))) -#else -#define ALL_QLOAD_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3)) -#define ALL_QSTORE_REGS ALL_QLOAD_REGS -#endif - TCGPowerISA have_isa; static bool have_isel; bool have_altivec; @@ -3752,23 +3740,23 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_qemu_ld_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O1_I1(r, L) - : C_O1_I2(r, L, L)); + ? C_O1_I1(r, r) + : C_O1_I2(r, r, r)); =20 case INDEX_op_qemu_st_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O0_I2(S, S) - : C_O0_I3(S, S, S)); + ? C_O0_I2(r, r) + : C_O0_I3(r, r, r)); =20 case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) - : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(L, L, L) - : C_O2_I2(L, L, L, L)); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) + : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(r, r, r) + : C_O2_I2(r, r, r, r)); =20 case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(S, S) - : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(S, S, S) - : C_O0_I4(S, S, S, S)); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(r, r) + : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(r, r, r) + : C_O0_I4(r, r, r, r)); =20 case INDEX_op_add_vec: case INDEX_op_sub_vec: --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315942; cv=none; d=zohomail.com; s=zohoarc; b=Gn/aym81QbpFwtTG2PBSMrdfqmh8ehK1zZCe0ToW9qrIrTU31wZGOXbcToKFM/xWJNNTFQVGp1DMG1NWr2xYucYw7KIFM7lVi13knGHUEI59NCYw4pvBL3lyUfLdge2dhr38JZqhbDwYnmYW4Ahb7S5PJw+1S25QjL0xmWRsXlg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315942; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qWj3vIxSlO8Q0IQAph2NSAlaNgeUKOrsmzRl/9QoxjM=; b=MM5fdSBSPTgHk9Eo8xh/zt69e1Tp42fd887jxzlTn1wIl0JafcRlxIiOti3ljfhNC7sekZaIh5mBCeOwb06mKNHvTocpSTBlJ7wMu11ZoCRYrBPc4R4Ctjt02YBDOtcPYmWmuboLMiQUlSiPFBrydEjTAqCvjYSMkIEYWpYcSxo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315942012864.4685924351832; Sun, 23 Apr 2023 22:59:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqp3M-0003ZT-09; Mon, 24 Apr 2023 01:47:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqp0k-0006O1-EV for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:45:19 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqp0I-0005Ly-0v for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:45:11 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-3f1e2555b5aso6138315e9.0 for ; Sun, 23 Apr 2023 22:44:39 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id u6-20020adff886000000b002f7780eee10sm9986693wrp.59.2023.04.23.22.44.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:44:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682315078; x=1684907078; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qWj3vIxSlO8Q0IQAph2NSAlaNgeUKOrsmzRl/9QoxjM=; b=yoEw3zDY0foIEusVR8XPn1czPjOqYt0FlfxOlDHu/7lLIXoCvJGMkvOOY1kPxOza3r vf6f7Cy5PUo9K3vcDxbUGLllgOCePFNf1ygpwUrIvS9iNIzMebgUl7KVjDC/MOuLD1uu clkKcLhTozayONu84y3uPCt8pl8jPifTCkoUWNDZgupGfyAcu7bMozj6ozW0Scg1ob0c 9tqrezJtxWHaII5Fc9xZp+4881AovhSlKue2cjvyhaVVZSExZg4k6ToYmnar7IMb1R2w Gxdlr0/Hg9lY1HHvbiUDRtMae68PyJEVVNYweOoGm3SVVWMmUg4H3xaNL1BzHW0/orX4 Un2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682315078; x=1684907078; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qWj3vIxSlO8Q0IQAph2NSAlaNgeUKOrsmzRl/9QoxjM=; b=UKv1ImKTwKKA1jZACcpZOS2ABwJywxyaFnCoqIJkk0KY+GR99mX4bcCmq/tCDF28yg wP3M5BwlemA2q2LfGZEKOuU59bCE0+oIqisTL7y+cgE9SrHi3OFycT6bxEG2SGI8XZZu Vb6RD3Bl4sSj+fxnK0AigqJL8ULM77cJHdJVKUj5SrBo2yrvlfqym4B4Zc2na+LPo2rJ N7GbNifsk777I8jHCF00bFUoVv1rP7u2f130QHmr0uswWg/hjNXqwy38+6FM6BY6KhZz 6XI5swMplLojdix91JWWox1GJn6E39ofp8Fac4UoFdVU94cOHyd0UM63i5GRV0HhmtoZ zkXw== X-Gm-Message-State: AAQBX9fUhXQzQrZHO2z1tXlVtSz8HpBAzXewNi1HuHzlbikPWiNi+hlt oJbDI4/PF14c/GwjAXRldzn9WfLSIq+6WzcSRM+T1A== X-Google-Smtp-Source: AKy350aICtNkHgOSrD1FmdAwsCcMNFqw0zkdTgXMf4A+OWDyjei2FJlk3s0X+7bMcP9+2NvBQDFBvQ== X-Received: by 2002:a05:600c:2309:b0:3ed:f5b5:37fc with SMTP id 9-20020a05600c230900b003edf5b537fcmr6650896wmo.1.1682315078064; Sun, 23 Apr 2023 22:44:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com, Daniel Henrique Barboza Subject: [PATCH v3 54/57] tcg/ppc: Remove unused constraints A, B, C, D Date: Mon, 24 Apr 2023 06:41:02 +0100 Message-Id: <20230424054105.1579315-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315944170100002 Content-Type: text/plain; charset="utf-8" These constraints have not been used for quite some time. Fixes: 77b73de67632 ("Use rem/div[u]_i32 drop div[u]2_i32") Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/ppc/tcg-target-con-str.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h index f3bf030bc3..9dcbc3df50 100644 --- a/tcg/ppc/tcg-target-con-str.h +++ b/tcg/ppc/tcg-target-con-str.h @@ -10,10 +10,6 @@ */ REGS('r', ALL_GENERAL_REGS) REGS('v', ALL_VECTOR_REGS) -REGS('A', 1u << TCG_REG_R3) -REGS('B', 1u << TCG_REG_R4) -REGS('C', 1u << TCG_REG_R5) -REGS('D', 1u << TCG_REG_R6) =20 /* * Define constraint letters for constants: --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315610; cv=none; d=zohomail.com; s=zohoarc; b=gypyS+6zrghWCDHzTxnmCr1K9uurYhdTN+mxLw4D32Fa2v19b/EAk0SGlNIhVHejTTWeDNRFmO5Ap3L6TAqSk+WLd5BgAmt1SV5ZK3iVWsLYEUwA/ECkyvF975L+ajCg8P/RthzHZUf+vJshFquriEjYiyZH4x5pOFc/D/T7kFI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315610; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=G0ifE83LtMRyfgkZHIOBSNcl6mKPbZ43dLi8uqtEacY=; b=jyRuG0I8tBVhupf2LtzgYDdcZ0BvEvuBzOTpPyGrT7ef6eeUs+gITtqYcZI1KLwUwaNQSmQWEZ6ipKOtX3RFiwxJygEvuwWbZdkAgih3fgaYxLQ6LFbpMZMAH23omJ54TD/R4nP5W71rsjLPjJAP4RY2Xbp7+NdU9kgB1NIhqZc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315610443312.54750032532274; Sun, 23 Apr 2023 22:53:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqp4g-0006AB-6F; Mon, 24 Apr 2023 01:49:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqp0b-0006F9-4U for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:45:19 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqp0H-0005MR-Sd for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:45:03 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-3010889c6ebso2304117f8f.2 for ; Sun, 23 Apr 2023 22:44:40 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id u6-20020adff886000000b002f7780eee10sm9986693wrp.59.2023.04.23.22.44.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:44:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682315079; x=1684907079; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G0ifE83LtMRyfgkZHIOBSNcl6mKPbZ43dLi8uqtEacY=; b=xNiXFJYn0HJXP2hnvh5iITRlVIwJDWg5sByVmkRkQ6k5XZk2DoKVg/fdJ0stKNIbxM YrEa/Dr3dWjGc5F+lfry2bFMLN78AmoBapDccKZqluR0Z2qF+bGtNg1oG7kUwxuxgSYr r+Uz/YPkwQweyeqJ3+qa9UJWjkOe5fxyKvPzYcs1fXSrq7VRQOxY4zS7Fn8xiq4xO0g0 240VtylU9+nS2quLh4L6w/6296AjlhtXO0VbX496Yv3MkKQSbPUqxdLjFBb/1kty0lI1 Ob2CLixYy3PZpT7i7aSDzi95BcHzOwDtWaBx/lUTg8yGb5toFS9GfbFZIVDptDjBvvlx mmiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682315079; x=1684907079; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G0ifE83LtMRyfgkZHIOBSNcl6mKPbZ43dLi8uqtEacY=; b=MhyihZIh7PQqxGqZ2+CQdhT+SYp00Q5l+DFSpqKV6CejdrxDPX1uoBn3CXJDpY0msv ZHUUqrhSDWX87NqSxa9az98XKj2XxPfG/wLxUpP1F4K7F1pgSqapPcoBvsaM2yxC1LT2 CTnn6d5W7Z7Ml2/mrP2QplDoiZV12HZfOi7Qdvhd3Dvb0FD23yIKkiqyfnzdrp+OKUsy +9V3MDh6zs69T3oK7Tezajwh9SYoOu27gtY2HipT8rokVSgEGztnab9LYlHzEm/7cC4v 2i1VDrV0zaQodFb91/7kLVHvLI9GCFGfDlj99XC0PgghsJCPO8kAH+jKomKR5BZsAAl2 7DUQ== X-Gm-Message-State: AAQBX9dO5Y8K4Igpl69cNXxUOaa68/hmye3n1W0SuuGiqpJZoj4LMZ0J 7xw2fcEeHtIU5yTl+y3LKGIuL4T5SRvXZVDYJE/4gw== X-Google-Smtp-Source: AKy350ZVdm285qJUembk0iW+8trQ3Kl5Xiou9FM8Kq4aWbmkmseX4vjaf7SAIqcePCVe1bCA5MBTjA== X-Received: by 2002:adf:ff83:0:b0:2f9:5841:a4d4 with SMTP id j3-20020adfff83000000b002f95841a4d4mr8233932wrr.27.1682315078851; Sun, 23 Apr 2023 22:44:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com, Daniel Henrique Barboza Subject: [PATCH v3 55/57] tcg/riscv: Simplify constraints on qemu_ld/st Date: Mon, 24 Apr 2023 06:41:03 +0100 Message-Id: <20230424054105.1579315-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315611569100007 Content-Type: text/plain; charset="utf-8" The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 2 -- tcg/riscv/tcg-target-con-str.h | 1 - tcg/riscv/tcg-target.c.inc | 16 +++------------- 3 files changed, 3 insertions(+), 16 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index c11710d117..1a8b8e9f2b 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -10,11 +10,9 @@ * tcg-target-con-str.h; the constraint combination is inclusive or. */ C_O0_I1(r) -C_O0_I2(LZ, L) C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) C_O0_I4(rZ, rZ, rZ, rZ) -C_O1_I1(r, L) C_O1_I1(r, r) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h index 8d8afaee53..6f1cfb976c 100644 --- a/tcg/riscv/tcg-target-con-str.h +++ b/tcg/riscv/tcg-target-con-str.h @@ -9,7 +9,6 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) -REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 4c8e38599b..d5239418dd 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -125,17 +125,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKi= nd kind, int slot) #define TCG_CT_CONST_N12 0x400 #define TCG_CT_CONST_M12 0x800 =20 -#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) -/* - * For softmmu, we need to avoid conflicts with the first 5 - * argument registers to call the helper. Some of these are - * also used for the tlb lookup. - */ -#ifdef CONFIG_SOFTMMU -#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5) -#else -#define SOFTMMU_RESERVE_REGS 0 -#endif +#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) =20 #define sextreg sextract64 =20 @@ -1626,10 +1616,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return C_O1_I1(r, L); + return C_O1_I1(r, r); case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - return C_O0_I2(LZ, L); + return C_O0_I2(rZ, r); =20 default: g_assert_not_reached(); --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315917; cv=none; d=zohomail.com; s=zohoarc; b=ENkx9Qz+wt08QyaAU26fE36JB+rxRyVq+M36xyr6rfc1YczTSz55BSMynjPhKDcWZ5yRK74ni6u0C12CMv3bJSrGObYSBRitRcR3GKTBOpfoUx2U6Na/eQrobawetB+8xK6IsEX4qHeUkPhcn/q+hQmaXijC7TwZIRzzckmHQBM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315917; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WrmqAOuR2/yJANGPopXn5FwM+vXCIwdTliCaNgd+uz0=; b=eynn97vZc/Fk/MduT0pR6BGnwpGyJVPDxD/v2X3X1gvQZ+5O39QRep+rii5yRQ9mSfRgkbg+D0qP57wy22BJCY+2Cqa/N5XNx7RTT6C+UyMy8HKW3EB/AyfF2ys4+4B9C01XMmsIl2g8KpDVQ8exc9NSZMOOI2t6dN/eOJMEEZk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315917097981.6458342641205; Sun, 23 Apr 2023 22:58:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqp4r-0006bB-8z; Mon, 24 Apr 2023 01:49:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqp0b-0006FF-4o for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:45:19 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqp0H-0005MY-Tt for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:45:04 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-2f46348728eso2305219f8f.3 for ; Sun, 23 Apr 2023 22:44:41 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id u6-20020adff886000000b002f7780eee10sm9986693wrp.59.2023.04.23.22.44.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:44:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682315079; x=1684907079; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WrmqAOuR2/yJANGPopXn5FwM+vXCIwdTliCaNgd+uz0=; b=loIzhHVZ8cgAyCUje2Ol0tC5Qt51NjEgcT4ZD9Zb1mlwqhk0tOlMugfWrtEQagx2wY qlw1gWu0L20Oe1mD+X/Cu1PUaIJPx5hT0Nc3AYOxMWStRTDn0GmixILlCWyE1l4BnG2K JyFl6h3Zj/bPkuiXJq1fZdiMW166ZnvVkh4AvFu0uVQLQXFdvbjYk2qrJDJwj/DGh0nR ViyYKW+q5Srv1AqV36Eaz0AcUSfD1Q6ZyCNlpSYyVwELChJUh1YCJQcsLQBqmgS6EpAu j6HqXMqv0n+Dp9qbp2SDhNprGk1g7cfhJemzPLI/j4IhSTVqzmFoU5x96cYcbQbNE53X xnaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682315079; x=1684907079; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WrmqAOuR2/yJANGPopXn5FwM+vXCIwdTliCaNgd+uz0=; b=SAHNFxyeaNsYReeL6LrLGETUiiqRkXRQS4rwbOVhMha7A8yZy7WpRyNBlU8QwV2rmo 7qTwb0Wpi/0VhN5KQPHRBx/CtAsxzilFnVM6DtlAphdG3iBcfZTpHjNF5fz41/hW3mCi CnO6oxsQuVR2UwUkKKCyXtG6FSvVTtcEbWYcUlzt/BOH3VQkJzdsI2hXFOL3sLdi3Yaq jFR4am0q28cY+FT508iFatY8OoExM7uvymLP5NTuN86pg2T5iLC3ZRhdkHbh/5P4awn9 g7BqAQ9WA7L9NLPgWJq+Cg3zFq61zVp3gko8BaBsp6bkn0VAi1h9OZeuhHK/8c215iVJ ySRA== X-Gm-Message-State: AAQBX9esdLREbtq8P2Fx0E+5oKuPHEgMxC4EG063MImAz4YHDhzafhcG X6HNAYlQ4kF8rSgUaPeHqZnASUhAfJghvFjfyJdFhQ== X-Google-Smtp-Source: AKy350YLuLGV8ZheQEDDsp8qyRoZQukAvkXyZKEyz/r7xn8sYqfCboOZzm2FV6WC52pWumUTwABB3A== X-Received: by 2002:a5d:428e:0:b0:2f9:b08a:a3af with SMTP id k14-20020a5d428e000000b002f9b08aa3afmr7404891wrq.49.1682315079542; Sun, 23 Apr 2023 22:44:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 56/57] tcg/s390x: Use ALGFR in constructing softmmu host address Date: Mon, 24 Apr 2023 06:41:04 +0100 Message-Id: <20230424054105.1579315-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315918396100009 Content-Type: text/plain; charset="utf-8" Rather than zero-extend the guest address into a register, use an add instruction which zero-extends the second input. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index dfcf4d9e34..dd13326670 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -149,6 +149,7 @@ typedef enum S390Opcode { RRE_ALGR =3D 0xb90a, RRE_ALCR =3D 0xb998, RRE_ALCGR =3D 0xb988, + RRE_ALGFR =3D 0xb91a, RRE_CGR =3D 0xb920, RRE_CLGR =3D 0xb921, RRE_DLGR =3D 0xb987, @@ -1853,10 +1854,11 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, tcg_out_insn(s, RXY, LG, h->index, TCG_REG_R2, TCG_REG_NONE, offsetof(CPUTLBEntry, addend)); =20 - h->base =3D addr_reg; if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_R3, addr_reg); - h->base =3D TCG_REG_R3; + tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg); + h->base =3D TCG_REG_NONE; + } else { + h->base =3D addr_reg; } h->disp =3D 0; #else --=20 2.34.1 From nobody Sun May 19 12:45:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1682315574; cv=none; d=zohomail.com; s=zohoarc; b=agnhUdhE0RZMs4IWivlevFc/jmHApwlfIb7L04RisEKBixtyOyKHf6V84CabUoP0iPwNzjquyE/eulM0fAiFTe6P4Jckkm8fFFANZqpu0JS/IvKNrO9khPStNSQP1x0Sd8VJICITiHquOWWqzjD8PL4r7tty5Uem3FzkxWzkgwg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1682315574; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=V0NN2hpnzMNaQXsS3LeulCiRo0il3NBwU75zZGVxlFw=; b=eNObwnll2yfUTrArkTGS6q5tfH4+V07Ybh8Xn5iC3ieC0l1O/5lKxF2msSiYFnttFT/2S133yPWXR3gXXc2xU6s6MkZk1riXY9DVMe8ETfpup0WBsmp0LGXw3lD2xBCeOZrqpjcp/ibXbB9r9X6LV3/4K865muFlLoQo8eRjp/E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1682315574708698.6778794534006; Sun, 23 Apr 2023 22:52:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqp5N-0007u7-I4; Mon, 24 Apr 2023 01:50:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqp0x-0006jy-U4 for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:45:43 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqp0I-0005NZ-Uw for qemu-devel@nongnu.org; Mon, 24 Apr 2023 01:45:23 -0400 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-2febac9cacdso2316507f8f.1 for ; Sun, 23 Apr 2023 22:44:40 -0700 (PDT) Received: from stoup.c.hoisthospitality.com (cust-west-loneq8-46-193-226-34.wb.wifirst.net. [46.193.226.34]) by smtp.gmail.com with ESMTPSA id u6-20020adff886000000b002f7780eee10sm9986693wrp.59.2023.04.23.22.44.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 22:44:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682315080; x=1684907080; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=V0NN2hpnzMNaQXsS3LeulCiRo0il3NBwU75zZGVxlFw=; b=Pk+Cib0gWXNgLzURVy9ATLUZ0zPes8CGBbxFT2RYkk+xdALdboPicHzv8uRtfCwwLO rgXt/TayZjus5PmjM2RL1PQTe0ai43mbfoXB4px1Q+0IITGRU+BIvpjNG1hOs3JtSSHT a/1NiQvGphAm7C8EeOtJQvHvjrm66/huRSzXt09iLnLW0UE96gGHzKce8v3EJs28HxBI AnpFEITopgYyyBAsweiN0v93qGT4Uu6wJJHaEZawqMuToPLuBHy7Yp69ZaJYa8UvU+ft BMxqeRTHhd7/9xHaeqntUByiCnz8f/rwiIMWtO5Efm4KEiQ2ZfOl1p9F+F+6ZEdD8c8M fneQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682315080; x=1684907080; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V0NN2hpnzMNaQXsS3LeulCiRo0il3NBwU75zZGVxlFw=; b=QkggdzgTqW2Rt07iqMLBsgnRmm3yDE3ZxjDtWIqBylk2FsQxLFgmAuxvAr7wk6+Kp7 IAIFgKDXhwb/CRDqTm97JaYBY0r0OCQCtiy80YSr73A2FKFG/m1BwToylKFCjjHfaSVx llmmuknbJEBTgSF9kzKQ8KU3If35CG7afJS3KfQFVUKoJw1mVonyZ/Ox9B8+Z4OWH885 KYfNMTIfnt22nSdzI6DEJVKm1Nyu6NKIrElag5GJ6GCSbE15Dxcf6QrWrV+4AehwRHYA PTfL6IO419eeqPtwoDd9OUT3Bk8ie9qqOfr2hrj5L8TzTFpFbMiUpmlXH/3a9i4WeHOH R5tA== X-Gm-Message-State: AAQBX9em5JEvCeibnTKlGTUWJYs/EqewPPb0shZIEK6nTWwOV+dZOMfD tmKDMndHapjhFQbgDoB7I8BDg5HC74HQvgIqj7P6PA== X-Google-Smtp-Source: AKy350acQEice4iYcox63pth3p+iCYo1xXkJz0/U7gwdRm41xl7bbxBoG5wpQ9UWnyUEmLihHPXTFA== X-Received: by 2002:a5d:6781:0:b0:304:7159:d3e4 with SMTP id v1-20020a5d6781000000b003047159d3e4mr3090999wru.44.1682315079994; Sun, 23 Apr 2023 22:44:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, git@xen0n.name, jiaxun.yang@flygoat.com Subject: [PATCH v3 57/57] tcg/s390x: Simplify constraints on qemu_ld/st Date: Mon, 24 Apr 2023 06:41:05 +0100 Message-Id: <20230424054105.1579315-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230424054105.1579315-1-richard.henderson@linaro.org> References: <20230424054105.1579315-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1682315576390100003 Content-Type: text/plain; charset="utf-8" Adjust the softmmu tlb to use R0+R1, not any of the normally available registers. Since we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 2 -- tcg/s390x/tcg-target-con-str.h | 1 - tcg/s390x/tcg-target.c.inc | 36 ++++++++++++---------------------- 3 files changed, 12 insertions(+), 27 deletions(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index 15f1c55103..ecc079bb6d 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -10,12 +10,10 @@ * tcg-target-con-str.h; the constraint combination is inclusive or. */ C_O0_I1(r) -C_O0_I2(L, L) C_O0_I2(r, r) C_O0_I2(r, ri) C_O0_I2(r, rA) C_O0_I2(v, r) -C_O1_I1(r, L) C_O1_I1(r, r) C_O1_I1(v, r) C_O1_I1(v, v) diff --git a/tcg/s390x/tcg-target-con-str.h b/tcg/s390x/tcg-target-con-str.h index 6fa64a1ed6..25675b449e 100644 --- a/tcg/s390x/tcg-target-con-str.h +++ b/tcg/s390x/tcg-target-con-str.h @@ -9,7 +9,6 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) -REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) REGS('v', ALL_VECTOR_REGS) REGS('o', 0xaaaa) /* odd numbered general regs */ =20 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index dd13326670..aacbaf21d5 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -44,18 +44,6 @@ #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16) #define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) =20 -/* - * For softmmu, we need to avoid conflicts with the first 3 - * argument registers to perform the tlb lookup, and to call - * the helper function. - */ -#ifdef CONFIG_SOFTMMU -#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_R2, 3) -#else -#define SOFTMMU_RESERVE_REGS 0 -#endif - - /* Several places within the instruction set 0 means "no register" rather than TCG_REG_R0. */ #define TCG_REG_NONE 0 @@ -1814,13 +1802,13 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, ldst->oi =3D oi; ldst->addrlo_reg =3D addr_reg; =20 - tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE, + tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); =20 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); - tcg_out_insn(s, RXY, NG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, mask_off= ); - tcg_out_insn(s, RXY, AG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, table_of= f); + tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_off); + tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_off); =20 /* * For aligned accesses, we check the first byte and include the align= ment @@ -1830,10 +1818,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, a_off =3D (a_bits >=3D s_bits ? 0 : s_mask - a_mask); tlb_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; if (a_off =3D=3D 0) { - tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask); + tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); } else { - tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off); - tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask); + tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off); + tgen_andi(s, TCG_TYPE_TL, TCG_REG_R0, tlb_mask); } =20 if (is_ld) { @@ -1842,16 +1830,16 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, ofs =3D offsetof(CPUTLBEntry, addr_write); } if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_insn(s, RX, C, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs); + tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); } else { - tcg_out_insn(s, RXY, CG, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs= ); + tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); } =20 tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); ldst->label_ptr[0] =3D s->code_ptr++; =20 - h->index =3D TCG_REG_R2; - tcg_out_insn(s, RXY, LG, h->index, TCG_REG_R2, TCG_REG_NONE, + h->index =3D TCG_TMP0; + tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE, offsetof(CPUTLBEntry, addend)); =20 if (TARGET_LONG_BITS =3D=3D 32) { @@ -3155,10 +3143,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return C_O1_I1(r, L); + return C_O1_I1(r, r); case INDEX_op_qemu_st_i64: case INDEX_op_qemu_st_i32: - return C_O0_I2(L, L); + return C_O0_I2(r, r); =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: --=20 2.34.1