Hi,
This version dropped patch 12 from v7. Alistair mentioned that it would
limiti static CPUs needlesly, since there's nothing preventing a static
CPU to allow for extension changes during runtime, and that misa-w is
enough to prevent write_misa() during runtime. I agree.
I also amended the commit message of patch 11 to remove any mention
about misa_ext_mask rollbacks (which the code wasn't doing). The patch
itself is changing validate_set_extensions() to avoid misa_ext_mask to
be overwritten during write_misa() in the first place, so no
misa_ext_mask rollback should be even mentioned.
Changes from v7:
- patch 12: drooped
- patch 11: use a sane commit message.
- v7 link: https://lists.gnu.org/archive/html/qemu-devel/2023-04/msg02916.html
Daniel Henrique Barboza (9):
target/riscv/cpu.c: add riscv_cpu_validate_v()
target/riscv/cpu.c: remove set_vext_version()
target/riscv/cpu.c: remove set_priv_version()
target/riscv: add PRIV_VERSION_LATEST
target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
target/riscv/cpu.c: validate extensions before riscv_timer_init()
target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
target/riscv: rework write_misa()
Weiwei Li (2):
target/riscv: Mask the implicitly enabled extensions in isa_string
based on priv version
target/riscv: Update check for Zca/Zcf/Zcd
target/riscv/cpu.c | 333 ++++++++++++++----------
target/riscv/cpu.h | 3 +
target/riscv/csr.c | 47 ++--
target/riscv/insn_trans/trans_rvd.c.inc | 12 +-
target/riscv/insn_trans/trans_rvf.c.inc | 14 +-
target/riscv/insn_trans/trans_rvi.c.inc | 5 +-
target/riscv/translate.c | 5 +-
7 files changed, 244 insertions(+), 175 deletions(-)
--
2.40.0