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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681982575630100001 Content-Type: text/plain; charset="utf-8" The RVV verification will error out if fails and it's being done at the end of riscv_cpu_validate_set_extensions(), after we've already set some extensions that are dependent on RVV. Let's put it in its own function and do it earlier. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 89 +++++++++++++++++++++++++--------------------- 1 file changed, 48 insertions(+), 41 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index befa64528f..feca13aefb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -797,6 +797,46 @@ static void riscv_cpu_disas_set_info(CPUState *s, disa= ssemble_info *info) } } =20 +static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, + Error **errp) +{ + int vext_version =3D VEXT_VERSION_1_00_0; + + if (!is_power_of_2(cfg->vlen)) { + error_setg(errp, "Vector extension VLEN must be power of 2"); + return; + } + if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { + error_setg(errp, + "Vector extension implementation only supports VLEN " + "in the range [128, %d]", RV_VLEN_MAX); + return; + } + if (!is_power_of_2(cfg->elen)) { + error_setg(errp, "Vector extension ELEN must be power of 2"); + return; + } + if (cfg->elen > 64 || cfg->elen < 8) { + error_setg(errp, + "Vector extension implementation only supports ELEN " + "in the range [8, 64]"); + return; + } + if (cfg->vext_spec) { + if (!g_strcmp0(cfg->vext_spec, "v1.0")) { + vext_version =3D VEXT_VERSION_1_00_0; + } else { + error_setg(errp, "Unsupported vector spec version '%s'", + cfg->vext_spec); + return; + } + } else { + qemu_log("vector version is not specified, " + "use the default value v1.0\n"); + } + set_vext_version(env, vext_version); +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -804,6 +844,7 @@ static void riscv_cpu_disas_set_info(CPUState *s, disas= semble_info *info) static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; + Error *local_err =3D NULL; =20 /* Do some ISA extension error checking */ if (riscv_has_ext(env, RVG) && @@ -872,8 +913,14 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU= *cpu, Error **errp) return; } =20 - /* The V vector extension depends on the Zve64d extension */ if (riscv_has_ext(env, RVV)) { + riscv_cpu_validate_v(env, &cpu->cfg, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + + /* The V vector extension depends on the Zve64d extension */ cpu->cfg.ext_zve64d =3D true; } =20 @@ -1008,46 +1055,6 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) cpu->cfg.ext_zksed =3D true; cpu->cfg.ext_zksh =3D true; } - - if (riscv_has_ext(env, RVV)) { - int vext_version =3D VEXT_VERSION_1_00_0; - if (!is_power_of_2(cpu->cfg.vlen)) { - error_setg(errp, - "Vector extension VLEN must be power of 2"); - return; - } - if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { - error_setg(errp, - "Vector extension implementation only supports VLEN= " - "in the range [128, %d]", RV_VLEN_MAX); - return; - } - if (!is_power_of_2(cpu->cfg.elen)) { - error_setg(errp, - "Vector extension ELEN must be power of 2"); - return; - } - if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { - error_setg(errp, - "Vector extension implementation only supports ELEN= " - "in the range [8, 64]"); - return; - } - if (cpu->cfg.vext_spec) { - if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { - vext_version =3D VEXT_VERSION_1_00_0; - } else { - error_setg(errp, - "Unsupported vector spec version '%s'", - cpu->cfg.vext_spec); - return; - } - } else { - qemu_log("vector version is not specified, " - "use the default value v1.0\n"); - } - set_vext_version(env, vext_version); - } } =20 #ifndef CONFIG_USER_ONLY --=20 2.40.0 From nobody Tue May 14 14:16:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1681982557; cv=none; d=zohomail.com; s=zohoarc; b=CrlxIBs0qkk32KA95aNltklPaVhO7UK3jG6baKjknN2tYWF/oNQmtLpEySgmolE8FceZtU9/OeYvoIHCvOxuKFrxA9F8c46ssBdsDVMBbQcvs1E5msJHlnzboPe5J8x7zDh+eM/V6G9BCjbCL3edAxeC1b7eZJKV1kTa/RF1BbA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Thu, 20 Apr 2023 02:21:13 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH RESEND v7 02/12] target/riscv/cpu.c: remove set_vext_version() Date: Thu, 20 Apr 2023 06:20:50 -0300 Message-Id: <20230420092100.177464-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230420092100.177464-1-dbarboza@ventanamicro.com> References: <20230420092100.177464-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681982559053100003 Content-Type: text/plain; charset="utf-8" This setter is doing nothing else but setting env->vext_ver. Assign the value directly. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index feca13aefb..fed7b467e4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -252,11 +252,6 @@ static void set_priv_version(CPURISCVState *env, int p= riv_ver) env->priv_ver =3D priv_ver; } =20 -static void set_vext_version(CPURISCVState *env, int vext_ver) -{ - env->vext_ver =3D vext_ver; -} - #ifndef CONFIG_USER_ONLY static uint8_t satp_mode_from_str(const char *satp_mode_str) { @@ -834,7 +829,7 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RI= SCVCPUConfig *cfg, qemu_log("vector version is not specified, " "use the default value v1.0\n"); } - set_vext_version(env, vext_version); + env->vext_ver =3D vext_version; } =20 /* --=20 2.40.0 From nobody Tue May 14 14:16:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::29; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681982561542100015 Content-Type: text/plain; charset="utf-8" The setter is doing nothing special. Just set env->priv_ver directly. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 29 ++++++++++++----------------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fed7b467e4..bec60fe585 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -247,11 +247,6 @@ static void set_misa(CPURISCVState *env, RISCVMXL mxl,= uint32_t ext) env->misa_ext_mask =3D env->misa_ext =3D ext; } =20 -static void set_priv_version(CPURISCVState *env, int priv_ver) -{ - env->priv_ver =3D priv_ver; -} - #ifndef CONFIG_USER_ONLY static uint8_t satp_mode_from_str(const char *satp_mode_str) { @@ -350,7 +345,7 @@ static void riscv_any_cpu_init(Object *obj) VM_1_10_SV32 : VM_1_10_SV57); #endif =20 - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver =3D PRIV_VERSION_1_12_0; } =20 #if defined(TARGET_RISCV64) @@ -361,7 +356,7 @@ static void rv64_base_cpu_init(Object *obj) set_misa(env, MXL_RV64, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver =3D PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -371,7 +366,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); #endif @@ -383,7 +378,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -396,7 +391,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_11_0); + env->priv_ver =3D PRIV_VERSION_1_11_0; =20 cpu->cfg.ext_zfh =3D true; cpu->cfg.mmu =3D true; @@ -430,7 +425,7 @@ static void rv128_base_cpu_init(Object *obj) set_misa(env, MXL_RV128, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver =3D PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -443,7 +438,7 @@ static void rv32_base_cpu_init(Object *obj) set_misa(env, MXL_RV32, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver =3D PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif @@ -453,7 +448,7 @@ static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif @@ -465,7 +460,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -478,7 +473,7 @@ static void rv32_ibex_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_11_0); + env->priv_ver =3D PRIV_VERSION_1_11_0; cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -492,7 +487,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -1174,7 +1169,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) } =20 if (priv_version >=3D PRIV_VERSION_1_10_0) { - set_priv_version(env, priv_version); + env->priv_ver =3D priv_version; } =20 riscv_cpu_validate_misa_priv(env, &local_err); --=20 2.40.0 From nobody Tue May 14 14:16:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1681982551; cv=none; d=zohomail.com; s=zohoarc; b=UOAWCMyD0KunTqTaYJJ1SAHxCcWwyNLJAHs4Uer0yGWELyaAUk0fsJHESjwnexKn04hBLANUxowsfEdbblyzbcRzrdmBws+9PTSbkuP6KmD2ywlBPQeMmD96r5WBeVbaY8PU0m0QWFtcQ6JqDZMfb1jNISFZHYEiPsNojfq2MoU= ARC-Message-Signature: i=1; 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Thu, 20 Apr 2023 02:21:19 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Richard Henderson Subject: [PATCH RESEND v7 04/12] target/riscv: add PRIV_VERSION_LATEST Date: Thu, 20 Apr 2023 06:20:52 -0300 Message-Id: <20230420092100.177464-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230420092100.177464-1-dbarboza@ventanamicro.com> References: <20230420092100.177464-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681982553033100003 Content-Type: text/plain; charset="utf-8" All these generic CPUs are using the latest priv available, at this moment PRIV_VERSION_1_12_0: - riscv_any_cpu_init() - rv32_base_cpu_init() - rv64_base_cpu_init() - rv128_base_cpu_init() Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll make it easier to update everything at once when a new priv version is available. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 8 ++++---- target/riscv/cpu.h | 2 ++ 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bec60fe585..dd35cf378f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -345,7 +345,7 @@ static void riscv_any_cpu_init(Object *obj) VM_1_10_SV32 : VM_1_10_SV57); #endif =20 - env->priv_ver =3D PRIV_VERSION_1_12_0; + env->priv_ver =3D PRIV_VERSION_LATEST; } =20 #if defined(TARGET_RISCV64) @@ -356,7 +356,7 @@ static void rv64_base_cpu_init(Object *obj) set_misa(env, MXL_RV64, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_1_12_0; + env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -425,7 +425,7 @@ static void rv128_base_cpu_init(Object *obj) set_misa(env, MXL_RV128, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_1_12_0; + env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -438,7 +438,7 @@ static void rv32_base_cpu_init(Object *obj) set_misa(env, MXL_RV32, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_1_12_0; + env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de7e43126a..15423585d0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -61,6 +61,8 @@ enum { PRIV_VERSION_1_10_0 =3D 0, PRIV_VERSION_1_11_0, PRIV_VERSION_1_12_0, + + PRIV_VERSION_LATEST =3D PRIV_VERSION_1_12_0, }; =20 #define VEXT_VERSION_1_00_0 0x00010000 --=20 2.40.0 From nobody Tue May 14 14:16:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::34; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681982506638100003 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Using implicitly enabled extensions such as Zca/Zcf/Zcd instead of their super extensions can simplify the extension related check. However, they may have higher priv version than their super extensions. So we should mask them in the isa_string based on priv version to make them invisible to user if the specified priv version is lower than their minimal priv version. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index dd35cf378f..9bb0e6b180 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1721,7 +1721,8 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char = **isa_str, int i; =20 for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { + if (cpu->env.priv_ver >=3D isa_edata_arr[i].min_version && + isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { new =3D g_strconcat(old, "_", isa_edata_arr[i].name, NULL); g_free(old); old =3D new; --=20 2.40.0 From nobody Tue May 14 14:16:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::336; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681982611788100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Even though Zca/Zcf/Zcd can be included by C/F/D, however, their priv version is higher than the priv version of C/F/D. So if we use check for them instead of check for C/F/D totally, it will trigger new problem when we try to disable the extensions based on the configured priv version. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvd.c.inc | 12 +++++++----- target/riscv/insn_trans/trans_rvf.c.inc | 14 ++++++++------ target/riscv/insn_trans/trans_rvi.c.inc | 5 +++-- target/riscv/translate.c | 5 +++-- 4 files changed, 21 insertions(+), 15 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 2c51e01c40..6bdb55ef43 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -31,9 +31,11 @@ } \ } while (0) =20 -#define REQUIRE_ZCD(ctx) do { \ - if (!ctx->cfg_ptr->ext_zcd) { \ - return false; \ +#define REQUIRE_ZCD_OR_DC(ctx) do { \ + if (!ctx->cfg_ptr->ext_zcd) { \ + if (!has_ext(ctx, RVD) || !has_ext(ctx, RVC)) { \ + return false; \ + } \ } \ } while (0) =20 @@ -67,13 +69,13 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) =20 static bool trans_c_fld(DisasContext *ctx, arg_fld *a) { - REQUIRE_ZCD(ctx); + REQUIRE_ZCD_OR_DC(ctx); return trans_fld(ctx, a); } =20 static bool trans_c_fsd(DisasContext *ctx, arg_fsd *a) { - REQUIRE_ZCD(ctx); + REQUIRE_ZCD_OR_DC(ctx); return trans_fsd(ctx, a); } =20 diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index b2de4fcf3f..c47138575a 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -30,10 +30,12 @@ } \ } while (0) =20 -#define REQUIRE_ZCF(ctx) do { \ - if (!ctx->cfg_ptr->ext_zcf) { \ - return false; \ - } \ +#define REQUIRE_ZCF_OR_FC(ctx) do { \ + if (!ctx->cfg_ptr->ext_zcf) { \ + if (!has_ext(ctx, RVF) || !has_ext(ctx, RVC)) { \ + return false; \ + } \ + } \ } while (0) =20 static bool trans_flw(DisasContext *ctx, arg_flw *a) @@ -69,13 +71,13 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) =20 static bool trans_c_flw(DisasContext *ctx, arg_flw *a) { - REQUIRE_ZCF(ctx); + REQUIRE_ZCF_OR_FC(ctx); return trans_flw(ctx, a); } =20 static bool trans_c_fsw(DisasContext *ctx, arg_fsw *a) { - REQUIRE_ZCF(ctx); + REQUIRE_ZCF_OR_FC(ctx); return trans_fsw(ctx, a); } =20 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index c70c495fc5..e33f63bea1 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -56,7 +56,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2); =20 gen_set_pc(ctx, cpu_pc); - if (!ctx->cfg_ptr->ext_zca) { + if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) { TCGv t0 =3D tcg_temp_new(); =20 misaligned =3D gen_new_label(); @@ -169,7 +169,8 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCG= Cond cond) =20 gen_set_label(l); /* branch taken */ =20 - if (!ctx->cfg_ptr->ext_zca && ((ctx->base.pc_next + a->imm) & 0x3)) { + if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca && + ((ctx->base.pc_next + a->imm) & 0x3)) { /* misaligned */ gen_exception_inst_addr_mis(ctx); } else { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 928da0d3f0..a889454137 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -549,7 +549,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_u= long imm) =20 /* check misaligned: */ next_pc =3D ctx->base.pc_next + imm; - if (!ctx->cfg_ptr->ext_zca) { + if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) { if ((next_pc & 0x3) !=3D 0) { gen_exception_inst_addr_mis(ctx); return; @@ -1123,7 +1123,8 @@ static void decode_opc(CPURISCVState *env, DisasConte= xt *ctx, uint16_t opcode) * The Zca extension is added as way to refer to instructions in t= he C * extension that do not include the floating-point loads and stor= es */ - if (ctx->cfg_ptr->ext_zca && decode_insn16(ctx, opcode)) { + if ((has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zca) && + decode_insn16(ctx, opcode)) { return; } } else { --=20 2.40.0 From nobody Tue May 14 14:16:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1681982564; cv=none; d=zohomail.com; s=zohoarc; b=g4flVgFcwhNHUk09D3n/57QggER3GquTRrXE8lWv+GFBF/5UiDpxjl/r/3EKNUdCtR7XYNZf4m1Iw3KPYULRgcQzn3M9hqt5VsrdsNhJdtnYhgebINIE955LedPlhTImECw1Akk19SrT/Pj19KMWcFckaaZLnXWHPNHmT/Afbcc= ARC-Message-Signature: i=1; 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Thu, 20 Apr 2023 02:21:27 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH RESEND v7 07/12] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers Date: Thu, 20 Apr 2023 06:20:55 -0300 Message-Id: <20230420092100.177464-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230420092100.177464-1-dbarboza@ventanamicro.com> References: <20230420092100.177464-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::34; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681982565146100001 Content-Type: text/plain; charset="utf-8" We're doing env->priv_spec validation and assignment at the start of riscv_cpu_realize(), which is fine, but then we're doing a force disable on extensions that aren't compatible with the priv version. This second step is being done too early. The disabled extensions might be re-enabled again in riscv_cpu_validate_set_extensions() by accident. A better place to put this code is at the end of riscv_cpu_validate_set_extensions() after all the validations are completed. Add a new helper, riscv_cpu_disable_priv_spec_isa_exts(), to disable the extesions after the validation is done. While we're at it, create a riscv_cpu_validate_priv_spec() helper to host all env->priv_spec related validation to unclog riscv_cpu_realize a bit. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 91 ++++++++++++++++++++++++++++------------------ 1 file changed, 56 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9bb0e6b180..c928925544 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -827,6 +827,52 @@ static void riscv_cpu_validate_v(CPURISCVState *env, R= ISCVCPUConfig *cfg, env->vext_ver =3D vext_version; } =20 +static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env =3D &cpu->env; + int priv_version =3D -1; + + if (cpu->cfg.priv_spec) { + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { + priv_version =3D PRIV_VERSION_1_12_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { + priv_version =3D PRIV_VERSION_1_11_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { + priv_version =3D PRIV_VERSION_1_10_0; + } else { + error_setg(errp, + "Unsupported privilege spec version '%s'", + cpu->cfg.priv_spec); + return; + } + + env->priv_ver =3D priv_version; + } +} + +static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) +{ + CPURISCVState *env =3D &cpu->env; + int i; + + /* Force disable extensions if priv spec version does not match */ + for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { + if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && + (env->priv_ver < isa_edata_arr[i].min_version)) { + isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); +#ifndef CONFIG_USER_ONLY + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx + " because privilege spec version does not match", + isa_edata_arr[i].name, env->mhartid); +#else + warn_report("disabling %s extension because " + "privilege spec version does not match", + isa_edata_arr[i].name); +#endif + } + } +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -1045,6 +1091,12 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) cpu->cfg.ext_zksed =3D true; cpu->cfg.ext_zksh =3D true; } + + /* + * Disable isa extensions based on priv spec after we + * validated and set everything we need. + */ + riscv_cpu_disable_priv_spec_isa_exts(cpu); } =20 #ifndef CONFIG_USER_ONLY @@ -1144,7 +1196,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); CPUClass *cc =3D CPU_CLASS(mcc); - int i, priv_version =3D -1; Error *local_err =3D NULL; =20 cpu_exec_realizefn(cs, &local_err); @@ -1153,23 +1204,10 @@ static void riscv_cpu_realize(DeviceState *dev, Err= or **errp) return; } =20 - if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { - priv_version =3D PRIV_VERSION_1_12_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { - priv_version =3D PRIV_VERSION_1_11_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { - priv_version =3D PRIV_VERSION_1_10_0; - } else { - error_setg(errp, - "Unsupported privilege spec version '%s'", - cpu->cfg.priv_spec); - return; - } - } - - if (priv_version >=3D PRIV_VERSION_1_10_0) { - env->priv_ver =3D priv_version; + riscv_cpu_validate_priv_spec(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; } =20 riscv_cpu_validate_misa_priv(env, &local_err); @@ -1178,23 +1216,6 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) return; } =20 - /* Force disable extensions if priv spec version does not match */ - for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && - (env->priv_ver < isa_edata_arr[i].min_version)) { - isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); -#ifndef CONFIG_USER_ONLY - warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx - " because privilege spec version does not match", - isa_edata_arr[i].name, env->mhartid); -#else - warn_report("disabling %s extension because " - "privilege spec version does not match", - isa_edata_arr[i].name); -#endif - } - } - if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available --=20 2.40.0 From nobody Tue May 14 14:16:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681982518643100007 Content-Type: text/plain; charset="utf-8" Let's remove more code that is open coded in riscv_cpu_realize() and put it into a helper. Let's also add an error message instead of just asserting out if env->misa_mxl_max !=3D env->misa_mlx. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 50 ++++++++++++++++++++++++++++++---------------- 1 file changed, 33 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c928925544..43635144bd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -873,6 +873,33 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCV= CPU *cpu) } } =20 +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); + CPUClass *cc =3D CPU_CLASS(mcc); + CPURISCVState *env =3D &cpu->env; + + /* Validate that MISA_MXL is set properly. */ + switch (env->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + case MXL_RV128: + cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; + break; +#endif + case MXL_RV32: + cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; + break; + default: + g_assert_not_reached(); + } + + if (env->misa_mxl_max !=3D env->misa_mxl) { + error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); + return; + } +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -1195,7 +1222,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) RISCVCPU *cpu =3D RISCV_CPU(dev); CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); - CPUClass *cc =3D CPU_CLASS(mcc); Error *local_err =3D NULL; =20 cpu_exec_realizefn(cs, &local_err); @@ -1204,6 +1230,12 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) return; } =20 + riscv_cpu_validate_misa_mxl(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + riscv_cpu_validate_priv_spec(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); @@ -1232,22 +1264,6 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) } #endif /* CONFIG_USER_ONLY */ =20 - /* Validate that MISA_MXL is set properly. */ - switch (env->misa_mxl_max) { -#ifdef TARGET_RISCV64 - case MXL_RV64: - case MXL_RV128: - cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; - break; -#endif - case MXL_RV32: - cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; - break; - default: - g_assert_not_reached(); - } - assert(env->misa_mxl_max =3D=3D env->misa_mxl); - riscv_cpu_validate_set_extensions(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.40.0 From nobody Tue May 14 14:16:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1681982558; cv=none; d=zohomail.com; s=zohoarc; b=XBRulFMIlsxF3JDjRMTlzFxYR1D3fGiQQRVAIQMnKe1J3C9LTO41i/Ww7SkGXVWF5JCc4s5nZ05f+gFO4SxwCnASAHymSgt7D2I9lbxe0wnfCAwZq1i1I1sFUmuk/DD3nPaSgArIQ24Fz18ZXYyqGnsfCLciMqcKcX70FyIJRkc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681982558; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Thu, 20 Apr 2023 02:21:33 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH RESEND v7 09/12] target/riscv/cpu.c: validate extensions before riscv_timer_init() Date: Thu, 20 Apr 2023 06:20:57 -0300 Message-Id: <20230420092100.177464-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230420092100.177464-1-dbarboza@ventanamicro.com> References: <20230420092100.177464-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c35; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681982559063100004 Content-Type: text/plain; charset="utf-8" There is no need to init timers if we're not even sure that our extensions are valid. Execute riscv_cpu_validate_set_extensions() before riscv_timer_init(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 43635144bd..2d7f0ac785 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1257,13 +1257,6 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) return; } =20 - -#ifndef CONFIG_USER_ONLY - if (cpu->cfg.ext_sstc) { - riscv_timer_init(cpu); - } -#endif /* CONFIG_USER_ONLY */ - riscv_cpu_validate_set_extensions(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); @@ -1271,6 +1264,10 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) } =20 #ifndef CONFIG_USER_ONLY + if (cpu->cfg.ext_sstc) { + riscv_timer_init(cpu); + } + if (cpu->cfg.pmu_num) { if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpm= f) { cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, --=20 2.40.0 From nobody Tue May 14 14:16:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681982573169100001 Content-Type: text/plain; charset="utf-8" We have 4 config settings being done in riscv_cpu_init(): ext_ifencei, ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu" device, which happens to be the parent device of every RISC-V cpu. The result is that these 4 configs are being set every time, and every other CPU should always account for them. CPUs such as sifive_e need to disable settings that aren't enabled simply because the parent class happens to be enabling it. Moving all configurations from the parent class to each CPU will centralize the config of each CPU into its own init(), which is clearer than having to account to whatever happens to be set in the parent device. These settings are also being set in register_cpu_props() when no 'misa_ext' is set, so for these CPUs we don't need changes. Named CPUs will receive all cfgs that the parent were setting into their init(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 59 ++++++++++++++++++++++++++++++++++++---------- 1 file changed, 47 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2d7f0ac785..7d407321aa 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -332,7 +332,8 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) =20 static void riscv_any_cpu_init(Object *obj) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; #if defined(TARGET_RISCV32) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #elif defined(TARGET_RISCV64) @@ -346,6 +347,12 @@ static void riscv_any_cpu_init(Object *obj) #endif =20 env->priv_ver =3D PRIV_VERSION_LATEST; + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; } =20 #if defined(TARGET_RISCV64) @@ -364,12 +371,19 @@ static void rv64_base_cpu_init(Object *obj) =20 static void rv64_sifive_u_cpu_init(Object *obj) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv64_sifive_e_cpu_init(Object *obj) @@ -379,10 +393,14 @@ static void rv64_sifive_e_cpu_init(Object *obj) =20 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; - cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv64_thead_c906_cpu_init(Object *obj) @@ -410,6 +428,9 @@ static void rv64_thead_c906_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_SV39); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.pmp =3D true; } =20 static void rv128_base_cpu_init(Object *obj) @@ -446,12 +467,19 @@ static void rv32_base_cpu_init(Object *obj) =20 static void rv32_sifive_u_cpu_init(Object *obj) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv32_sifive_e_cpu_init(Object *obj) @@ -461,10 +489,14 @@ static void rv32_sifive_e_cpu_init(Object *obj) =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; - cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv32_ibex_cpu_init(Object *obj) @@ -474,11 +506,15 @@ static void rv32_ibex_cpu_init(Object *obj) =20 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_11_0; - cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif cpu->cfg.epmp =3D true; + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv32_imafcu_nommu_cpu_init(Object *obj) @@ -488,10 +524,14 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 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Thu, 20 Apr 2023 02:21:39 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH RESEND v7 11/12] target/riscv: rework write_misa() Date: Thu, 20 Apr 2023 06:20:59 -0300 Message-Id: <20230420092100.177464-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230420092100.177464-1-dbarboza@ventanamicro.com> References: <20230420092100.177464-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681982516610100001 Content-Type: text/plain; charset="utf-8" write_misa() must use as much common logic as possible. We want to open code just the bits that are exclusive to the CSR write operation and TCG internals. Our validation is done with riscv_cpu_validate_set_extensions(), but we need a small tweak first. When enabling RVG we're doing: env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; env->misa_ext_mask =3D env->misa_ext; This works fine for realize() time but this can potentially overwrite env->misa_ext_mask if we reutilize the function for write_misa(). Instead of doing misa_ext_mask =3D misa_ext, sum up the RVG extensions in misa_ext_mask as well. This won't change realize() time behavior (misa_ext_mask is still =3D=3D misa_ext) and will ensure that write_misa() won't change misa_ext_mask by accident. After that, rewrite write_misa() to work as follows: - mask the write using misa_ext_mask to avoid enabling unsupported extensions; - suppress RVC if the next insn isn't aligned; - disable RVG if any of RVG dependencies are being disabled by the user; - assign env->misa_ext and run riscv_cpu_validate_set_extensions(). On error, rollback to the previous values of misa_ext and misa_ext_mask; - on success, check if there's a chance that misa_ext_mask was overwritten during the process and restore it; - handle RVF and MSTATUS_FS and continue as usual. Let's keep write_misa() as experimental for now until this logic gains enough mileage. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li --- target/riscv/cpu.c | 4 ++-- target/riscv/cpu.h | 1 + target/riscv/csr.c | 47 ++++++++++++++++++++-------------------------- 3 files changed, 23 insertions(+), 29 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7d407321aa..4fa720a39d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -944,7 +944,7 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, = Error **errp) * Check consistency between chosen extensions while setting * cpu->cfg accordingly. */ -static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; @@ -960,7 +960,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) cpu->cfg.ext_ifencei =3D true; =20 env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; - env->misa_ext_mask =3D env->misa_ext; + env->misa_ext_mask |=3D RVI | RVM | RVA | RVF | RVD; } =20 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 15423585d0..1f39edc687 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -548,6 +548,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); =20 #define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 865ee9efda..d449da2657 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1387,39 +1387,18 @@ static RISCVException read_misa(CPURISCVState *env,= int csrno, static RISCVException write_misa(CPURISCVState *env, int csrno, target_ulong val) { + RISCVCPU *cpu =3D env_archcpu(env); + uint32_t orig_misa_ext =3D env->misa_ext; + Error *local_err =3D NULL; + if (!riscv_cpu_cfg(env)->misa_w) { /* drop write to misa */ return RISCV_EXCP_NONE; } =20 - /* 'I' or 'E' must be present */ - if (!(val & (RVI | RVE))) { - /* It is not, drop write to misa */ - return RISCV_EXCP_NONE; - } - - /* 'E' excludes all other extensions */ - if (val & RVE) { - /* - * when we support 'E' we can do "val =3D RVE;" however - * for now we just drop writes if 'E' is present. - */ - return RISCV_EXCP_NONE; - } - - /* - * misa.MXL writes are not supported by QEMU. - * Drop writes to those bits. - */ - /* Mask extensions that are not supported by this hart */ val &=3D env->misa_ext_mask; =20 - /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ - if ((val & RVD) && !(val & RVF)) { - val &=3D ~RVD; - } - /* * Suppress 'C' if next instruction is not aligned * TODO: this should check next_pc @@ -1428,18 +1407,32 @@ static RISCVException write_misa(CPURISCVState *env= , int csrno, val &=3D ~RVC; } =20 + /* Disable RVG if any of its dependencies are disabled */ + if (!(val & RVI && val & RVM && val & RVA && + val & RVF && val & RVD)) { + val &=3D ~RVG; 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Thu, 20 Apr 2023 02:21:42 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH RESEND v7 12/12] target/riscv: forbid write_misa() for static CPUs Date: Thu, 20 Apr 2023 06:21:00 -0300 Message-Id: <20230420092100.177464-13-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230420092100.177464-1-dbarboza@ventanamicro.com> References: <20230420092100.177464-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::33; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681982586837100003 Content-Type: text/plain; charset="utf-8" Static CPUs don't want their extensions changed by user interaction. We can prevent it during init by not exposing user facing properties, but write_misa() is also capable of disabling/enabling extension during runtime. We have a way of telling whether a CPU is static or not by checking for TYPE_RISCV_DYNAMIC_CPU. Use it to make write_misa() a no-op for these CPUs. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 5 +++++ target/riscv/cpu.h | 2 ++ target/riscv/csr.c | 5 +++++ 3 files changed, 12 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4fa720a39d..3cbcf6d320 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1452,6 +1452,11 @@ static void riscv_cpu_init(Object *obj) #endif /* CONFIG_USER_ONLY */ } =20 +bool riscv_cpu_is_static(RISCVCPU *cpu) +{ + return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_DYNAMIC_CPU) =3D=3D= NULL; +} + typedef struct RISCVCPUMisaExtConfig { const char *name; const char *description; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1f39edc687..1913ab9d8d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -587,6 +587,8 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *en= v, target_ulong riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); =20 +bool riscv_cpu_is_static(RISCVCPU *cpu); + #include "exec/cpu-all.h" =20 FIELD(TB_FLAGS, MEM_IDX, 0, 3) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d449da2657..929c5477dd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1391,6 +1391,11 @@ static RISCVException write_misa(CPURISCVState *env,= int csrno, uint32_t orig_misa_ext =3D env->misa_ext; Error *local_err =3D NULL; =20 + if (riscv_cpu_is_static(cpu)) { + /* never write MISA for static CPUs */ + return RISCV_EXCP_NONE; + } + if (!riscv_cpu_cfg(env)->misa_w) { /* drop write to misa */ return RISCV_EXCP_NONE; --=20 2.40.0