From nobody Fri May 17 04:49:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1681299864; cv=none; d=zohomail.com; s=zohoarc; b=GTl+tfJg8s3rDY4BIWmjQY23HagBLbOFeruOAEeFBo8jUc71fuiDOy5QyIpff16vssVd1ETLCkm5lcXrdtASJftPZ3dFqF5p+B2Qb071BSQwn7jfWQwX3PVvreQ2iSPt6yyEpGpfWQjMUNrKot7KPrZYi/G3hMJqCFT1J9iyFDM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681299864; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=es1PvJYw9d2r23P0DzMd3BW6TZP7rodwja8w1R+yBl8=; b=fLZTHV5VGtAlppUvbOlIf8TTOsu3jSssjPmUXJZndYJDY4Yr8xFtrNtINKD1crtoldGLvcFPo8YWXYULv1kYihwSf2B1SE0YM91BxbkXTylJDGnzIj1hTU27dZhGoZgq4KrduoheHoPqXotCI3RwA16MDZkpuvlzd84shAb4MyE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168129986415995.37720052906309; Wed, 12 Apr 2023 04:44:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pmYt6-0004j5-0P; Wed, 12 Apr 2023 07:43:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pmYt3-0004f4-Il for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:41 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pmYt0-0002NE-NI for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:41 -0400 Received: by mail-wr1-x432.google.com with SMTP id l18so10512595wrb.9 for ; Wed, 12 Apr 2023 04:43:37 -0700 (PDT) Received: from stoup.hotel.gast (ip-037-024-010-236.um08.pools.vodafone-ip.de. [37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299816; x=1683891816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=es1PvJYw9d2r23P0DzMd3BW6TZP7rodwja8w1R+yBl8=; b=W552nbUcyiIpxvWAZBhvSMuF18TcXEgyQL7K0GjcOm5tUVwtOjJP9jx8+UD7pnkqVX RvaHOa1VaVCa4QEsXda6aukwBZPHDbK5s4e9Vw0d3hNcxkVsuTWlfKKfCTRsA4pOY6g/ SKlpwF4XSu+LwhnvRya87ovbxfPTazDwq5+UFahXPWxuAcfRRJi7ubBMCeljt2S9eMK/ qQSx2ZRta2/ihOQzlTpz3BKBdFeC8QdNZ0AKwu/Mhp/omO6tbS6tpfRtOEmJzd0E++5f glt9i40OyGJt3aLWh+j9sqjaakFF+Y41kZ2d4jpAjX0NKkfGF0fHcDqsDW1t3tIMNc23 xmRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299816; x=1683891816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=es1PvJYw9d2r23P0DzMd3BW6TZP7rodwja8w1R+yBl8=; b=Lr1Cqt8pXbUDmnb8whcVbFiNZrIjb4Xm4OhnFCVNWenMppj9QtaEwHJZZl0PgC1tu/ mP82EkBx+36XCkKBx/VV11NwNNhcMwhcZWoUGIWCjE9Z2/3/HSFIXNYE/o3iAOiCHzcD 67au2gFw016ve4R9bTYUkPqhY1EGXwi7Og3b9/pCeivaMCvouzmcckS7zvlrRqAtOsFA RzwQyJl3iubfKcUycx3pKBuEjiZzNDlApHJ+tIgDZorcIoNheAOeJL4gIVFkPAvWMZvC pYp/3fuOW/TV/TlcTZJYq22wI8RmdwjFYFLDx7MvJXBLBADUSpDNbjgkFh9J5BDZhGEc Wdaw== X-Gm-Message-State: AAQBX9cQJ42CiLjeNK67h9mwBGuhC1p8Q31rpsCwSIEvs4MmI/asqsvC 519go9XldEEBhfQlyIA7OXkdGKOVvh/89RHlsrG+/Nsm X-Google-Smtp-Source: AKy350bqgd0aFXGysbBv3mGQaoiFiDA+0wmjjGyJo3FuSL7xHdTClwvDHoyLgEDLGn1BMZ7pX17Jhg== X-Received: by 2002:adf:fecb:0:b0:2e5:1ee3:df77 with SMTP id q11-20020adffecb000000b002e51ee3df77mr12169128wrs.46.1681299816220; Wed, 12 Apr 2023 04:43:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, LIU Zhiwei , Weiwei Li , Alistair Francis , Daniel Henrique Barboza Subject: [PATCH v7 01/25] target/riscv: Extract virt enabled state from tb flags Date: Wed, 12 Apr 2023 13:43:09 +0200 Message-Id: <20230412114333.118895-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681299866188100003 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei Virt enabled state is not a constant, so we should put it into tb flags. Thus we can use it like a constant condition at translation phase. Reported-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: LIU Zhiwei Reviewed-by: Weiwei Li Message-Id: <20230324143031.1093-2-zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-2-richard.henderson@linaro.org> --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 1 + target/riscv/translate.c | 10 +--------- 3 files changed, 4 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 86e08d10da..aa53d0e256 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -648,6 +648,8 @@ FIELD(TB_FLAGS, VTA, 24, 1) FIELD(TB_FLAGS, VMA, 25, 1) /* Native debug itrigger */ FIELD(TB_FLAGS, ITRIGGER, 26, 1) +/* Virtual mode enabled */ +FIELD(TB_FLAGS, VIRT_ENABLED, 27, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 433ea529b0..1d90977d46 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -104,6 +104,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ul= ong *pc, =20 flags =3D FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, get_field(env->mstatus_hs, MSTATUS_VS)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, env->virt_enab= led); } if (cpu->cfg.debug && !icount_enabled()) { flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d0094922b6..ebd00529ff 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1171,15 +1171,7 @@ static void riscv_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) ctx->mstatus_fs =3D tb_flags & TB_FLAGS_MSTATUS_FS; ctx->mstatus_vs =3D tb_flags & TB_FLAGS_MSTATUS_VS; ctx->priv_ver =3D env->priv_ver; -#if !defined(CONFIG_USER_ONLY) - if (riscv_has_ext(env, RVH)) { - ctx->virt_enabled =3D env->virt_enabled; - } else { - ctx->virt_enabled =3D false; - } -#else - ctx->virt_enabled =3D false; -#endif + ctx->virt_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); ctx->misa_ext =3D env->misa_ext; ctx->frm =3D -1; /* unknown rounding mode */ ctx->cfg_ptr =3D &(cpu->cfg); --=20 2.34.1 From nobody Fri May 17 04:49:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1681300055; cv=none; d=zohomail.com; s=zohoarc; b=ivQZnAEdSkFx2lp66BnunD5w1vr+HWOdwO+xL7XAn0ik6o93Q7YGPQ/YodSw2aQFx4xXyOVk2xC5IIc97ZSjp352fT37sJAkQ+qYZJZPE2ObJ4t9XwL5FoY2A+1azdiFSc4lpGjQaKYvJNxF6r2j6uz1lIQhDQAov4n8xVA610c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681300055; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sZWSjtdLuqRfAHXhQ1Qn/4gxDZYp/Ml73FoJP/ry5BM=; b=cVaRjhoY9Y2ctW3vTEix2EdA9hcpR3JqjpIazvJIcGntI6G90OcHKo5PnPp5HbTcrYapHPzz0bAY6/uBTtFARQWcZzsZEA9fVTqnsKHN8i1n06scmk7rTLkhkcaFr+MWESk4aZHmk95UOamU1c4OvY8Way5PPgnLihjOgXhH1Y4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168130005544992.98636339527798; Wed, 12 Apr 2023 04:47:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pmYtC-0004u9-Ud; Wed, 12 Apr 2023 07:43:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pmYt6-0004k4-65 for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:44 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pmYt1-0002NQ-Db for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:42 -0400 Received: by mail-wr1-x430.google.com with SMTP id e7so493582wrc.12 for ; Wed, 12 Apr 2023 04:43:38 -0700 (PDT) Received: from stoup.hotel.gast (ip-037-024-010-236.um08.pools.vodafone-ip.de. [37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299817; x=1683891817; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sZWSjtdLuqRfAHXhQ1Qn/4gxDZYp/Ml73FoJP/ry5BM=; b=zpqh7kOkoha8JhKb8g6iNhXDgtTC5gVB1VnvX3BxHnU+cYFLT6D2R1NFVydFAqm0yA eRGva3gmlWbKGZAPpDWsXHHKW4Gjw2p0PvqEEvwqgc1ND3q3IGkp0njS7U5Q1ClLZSy3 RiIVBc4JVY8wPe4h/YmX0VWygaRV9WTN3x8X1ISiJp54+rgNtN5SvlZ4qTNCMXyYarmq q6RcX0og6WA8/rDTOZA4C22iNXQIeZWWXnd/sfxE85VqwqpUX3vsufs8zea+IDSrey8g B6lwAKgtn31TkxxGoCjnA8KYd7eVHXQl1u1/91DbYh70K/2+Hk5kd+XUuPPeZYDw+o5v uz3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299817; x=1683891817; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sZWSjtdLuqRfAHXhQ1Qn/4gxDZYp/Ml73FoJP/ry5BM=; b=kemPkLAtFYYdrPIfCypguYCUbjyGUyNjzYUS0RXW6SNCSmqeVKt2Q1QLnu8H1r7Y2f tZ8XELf0iyNJypi0RjaM63VaXVbT/wZYSCG7KyDquwUKmK+7lz8KYFXHcS+eK0GVEhDI Yia6pyp1xD4jVsi1ZZ1HuFtY5+wcJlFNAlFRoMFEfuFOzO1XXqH7scOthzKNnPSy9/T/ /wvcBXy2juG/gpaJgWq8PBxOE1RzHLABLrnBB1QV7cifKdEZ0yiY/koyKlRDgpPAwKlL ih7URfFuFgRVpVUvW2bL88EIXncxi/A8sjLPeV88hl/LNT267DzepXfpRVNF7neu60UI zZvw== X-Gm-Message-State: AAQBX9dS2WIdpMV8y/jYbSYsavGMWSrFEAqLuWsPjzc1B9QxJ3jPb3AI 9MasH7YWEDyBlO21jimYucWbv7MNln/3tqUCngwJ7cO6 X-Google-Smtp-Source: AKy350ZaDMMESbl/6kbV9YprKZDOelzwcaB+WpQB+So77RUf4yqwE9MSQKfJUlFFFkCdXmCyr7wUNw== X-Received: by 2002:a5d:4564:0:b0:2ef:ba74:44c2 with SMTP id a4-20020a5d4564000000b002efba7444c2mr1748824wrc.2.1681299817039; Wed, 12 Apr 2023 04:43:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, LIU Zhiwei , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 02/25] target/riscv: Add a general status enum for extensions Date: Wed, 12 Apr 2023 13:43:10 +0200 Message-Id: <20230412114333.118895-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681300057040100003 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei The pointer masking is the only extension that directly use status. The vector or float extension uses the status in an indirect way. Replace the pointer masking extension special status fields with the general status. Reviewed-by: Richard Henderson Signed-off-by: LIU Zhiwei Message-Id: <20230324143031.1093-3-zhiwei_liu@linux.alibaba.com> [rth: Add a typedef for the enum] Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-3-richard.henderson@linaro.org> --- target/riscv/cpu.h | 8 ++++++++ target/riscv/cpu_bits.h | 12 ++++-------- target/riscv/cpu.c | 2 +- target/riscv/csr.c | 14 +++++++------- 4 files changed, 20 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index aa53d0e256..ba11279716 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -97,6 +97,14 @@ enum { TRANSLATE_G_STAGE_FAIL }; =20 +/* Extension context status */ +typedef enum { + EXT_STATUS_DISABLED =3D 0, + EXT_STATUS_INITIAL, + EXT_STATUS_CLEAN, + EXT_STATUS_DIRTY, +} RISCVExtStatus; + #define MMU_USER_IDX 3 =20 #define MAX_RISCV_PMPS (16) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index a16bfaf43f..fb63b8e125 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -9,6 +9,9 @@ (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \ (uint64_t)(mask))) =20 +/* Extension context status mask */ +#define EXT_STATUS_MASK 0x3ULL + /* Floating point round mode */ #define FSR_RD_SHIFT 5 #define FSR_RD (0x7 << FSR_RD_SHIFT) @@ -735,13 +738,6 @@ typedef enum RISCVException { #define PM_ENABLE 0x00000001ULL #define PM_CURRENT 0x00000002ULL #define PM_INSN 0x00000004ULL -#define PM_XS_MASK 0x00000003ULL - -/* PointerMasking XS bits values */ -#define PM_EXT_DISABLE 0x00000000ULL -#define PM_EXT_INITIAL 0x00000001ULL -#define PM_EXT_CLEAN 0x00000002ULL -#define PM_EXT_DIRTY 0x00000003ULL =20 /* Execution enviornment configuration bits */ #define MENVCFG_FIOM BIT(0) @@ -781,7 +777,7 @@ typedef enum RISCVException { #define S_OFFSET 5ULL #define M_OFFSET 8ULL =20 -#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET) +#define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET) #define U_PM_ENABLE (PM_ENABLE << U_OFFSET) #define U_PM_CURRENT (PM_CURRENT << U_OFFSET) #define U_PM_INSN (PM_INSN << U_OFFSET) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fab38859ec..32c04214a1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -759,7 +759,7 @@ static void riscv_cpu_reset_hold(Object *obj) i++; } /* mmte is supposed to have pm.current hardwired to 1 */ - env->mmte |=3D (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); + env->mmte |=3D (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT); #endif env->xl =3D riscv_cpu_mxl(env); riscv_cpu_update_mask(env); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f4d2dcfdc8..4268828dc4 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3534,7 +3534,7 @@ static RISCVException write_mmte(CPURISCVState *env, = int csrno, =20 /* hardwiring pm.instruction bit to 0, since it's not supported yet */ wpri_val &=3D ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); - env->mmte =3D wpri_val | PM_EXT_DIRTY; + env->mmte =3D wpri_val | EXT_STATUS_DIRTY; riscv_cpu_update_mask(env); =20 /* Set XS and SD bits, since PM CSRs are dirty */ @@ -3614,7 +3614,7 @@ static RISCVException write_mpmmask(CPURISCVState *en= v, int csrno, if ((env->priv =3D=3D PRV_M) && (env->mmte & M_PM_ENABLE)) { env->cur_pmmask =3D val; } - env->mmte |=3D PM_EXT_DIRTY; + env->mmte |=3D EXT_STATUS_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ mstatus =3D env->mstatus | MSTATUS_XS; @@ -3642,7 +3642,7 @@ static RISCVException write_spmmask(CPURISCVState *en= v, int csrno, if ((env->priv =3D=3D PRV_S) && (env->mmte & S_PM_ENABLE)) { env->cur_pmmask =3D val; } - env->mmte |=3D PM_EXT_DIRTY; + env->mmte |=3D EXT_STATUS_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ mstatus =3D env->mstatus | MSTATUS_XS; @@ -3670,7 +3670,7 @@ static RISCVException write_upmmask(CPURISCVState *en= v, int csrno, if ((env->priv =3D=3D PRV_U) && (env->mmte & U_PM_ENABLE)) { env->cur_pmmask =3D val; } - env->mmte |=3D PM_EXT_DIRTY; + env->mmte |=3D EXT_STATUS_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ mstatus =3D env->mstatus | MSTATUS_XS; @@ -3694,7 +3694,7 @@ static RISCVException write_mpmbase(CPURISCVState *en= v, int csrno, if ((env->priv =3D=3D PRV_M) && (env->mmte & M_PM_ENABLE)) { env->cur_pmbase =3D val; } - env->mmte |=3D PM_EXT_DIRTY; + env->mmte |=3D EXT_STATUS_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ mstatus =3D env->mstatus | MSTATUS_XS; @@ -3722,7 +3722,7 @@ static RISCVException write_spmbase(CPURISCVState *en= v, int csrno, if ((env->priv =3D=3D PRV_S) && (env->mmte & S_PM_ENABLE)) { env->cur_pmbase =3D val; } - env->mmte |=3D PM_EXT_DIRTY; + env->mmte |=3D EXT_STATUS_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ mstatus =3D env->mstatus | MSTATUS_XS; @@ -3750,7 +3750,7 @@ static RISCVException write_upmbase(CPURISCVState *en= v, int csrno, if ((env->priv =3D=3D PRV_U) && (env->mmte & U_PM_ENABLE)) { env->cur_pmbase =3D val; } - env->mmte |=3D PM_EXT_DIRTY; + env->mmte |=3D EXT_STATUS_DIRTY; =20 /* Set XS and SD bits, since PM CSRs are dirty */ mstatus =3D env->mstatus | MSTATUS_XS; --=20 2.34.1 From nobody Fri May 17 04:49:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299818; x=1683891818; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EKbGyzdb6cvD2agcBZ2QYZh6VK7dmyekZkQ2foWy+l8=; b=ymQZcciH+u37PRMsU3Wcipl5CA7nVULsKwNKHjqCc4JdXQCa5diPsXjgEjpyetRc70 5Ns6tXzLNv5DTk1Z1q16GeDS52HDPYTexFysvWoQc1UH73As2Qzf+aaNzSftlFoudo5p bZNMm8EboEdCQ77qtHH56M9kRexXcdYpLGeUtINOfM0TVgYHvZeqYNQCMoY5G+0fofFj UpJz3gw24eXem84/1sEm+ylQcVpgB2yoPM+kaIpIhffRQxtjRMKUBp5rWJQsvQLW3kUN gpougmr6s7BI1D+HmcJD/X46wRl9uP0PzLxlS5ncMXFCVIIOH8r8fxqdcOUBVDUClHJl qEdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299818; x=1683891818; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EKbGyzdb6cvD2agcBZ2QYZh6VK7dmyekZkQ2foWy+l8=; b=zFED0FUyP0AROIA/wPqfQ/pDcWeGJoXHUnQJI+WQkR8EdwJzSMq/OWfCtXLjgBIiTs bouUmBwYe/+C7HtwwQH2KzhsYTga3W7Mngcp1b+2m0t9bDqZknoxsGWwtFmrjXubRWQF uaH5IWuC6rRPX1g9R9xWk6i11rJfbLlF032TjMIdY3h8cRQQ0Bxmp0V7+GjaHNuQalnq yqGlW1P3cnPqIdsa6Cg6CY7sb9bMGCutX6Gf3QDgfQ17eqR2lx6MDC0T4voUnN59Lb6M UBGbOZDTuZYNf6zII4Pg/rGjvGJcDrIq+v/jyFxWYnwdlC/EOMVHPFlI/05fKDJEr70I DkPg== X-Gm-Message-State: AAQBX9fH8eVKu6sl1PLN9qXWRcFnfgVWhEsiLt9ZnFSUtgpritIlSkkv Rb9kvIbErJViBb74YMHzUwkfhk4+PjAiInnvCQ8gXxOF X-Google-Smtp-Source: AKy350YYXLPPjewZplXjxHT9N87luC6j+bVCv5GIJFPdqpUCtO0MtsxBeio0jnBAaOkcsUNB9dL3Ww== X-Received: by 2002:adf:ef4d:0:b0:2ef:e73d:605d with SMTP id c13-20020adfef4d000000b002efe73d605dmr1629175wrp.30.1681299817778; Wed, 12 Apr 2023 04:43:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, LIU Zhiwei , Weiwei Li , Alistair Francis , Daniel Henrique Barboza Subject: [PATCH v7 03/25] target/riscv: Encode the FS and VS on a normal way for tb flags Date: Wed, 12 Apr 2023 13:43:11 +0200 Message-Id: <20230412114333.118895-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681300016194100001 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei Reuse the MSTATUS_FS and MSTATUS_VS for the tb flags positions is not a normal way. It will make it hard to change the tb flags layout. And even worse, if we want to keep tb flags for a same extension togather without a hole. Reviewed-by: Richard Henderson Signed-off-by: LIU Zhiwei Reviewed-by: Weiwei Li Message-Id: <20230324143031.1093-4-zhiwei_liu@linux.alibaba.com> [rth: Adjust trans_rvf.c.inc as well; use the typedef] Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-4-richard.henderson@linaro.org> --- target/riscv/cpu.h | 15 ++++++------ target/riscv/cpu_helper.c | 11 +++++---- target/riscv/translate.c | 32 +++++++++++-------------- target/riscv/insn_trans/trans_rvf.c.inc | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 8 +++---- 5 files changed, 32 insertions(+), 36 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ba11279716..51d39687fe 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -631,18 +631,17 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_= ulong); =20 #define TB_FLAGS_PRIV_MMU_MASK 3 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) -#define TB_FLAGS_MSTATUS_FS MSTATUS_FS -#define TB_FLAGS_MSTATUS_VS MSTATUS_VS =20 #include "exec/cpu-all.h" =20 FIELD(TB_FLAGS, MEM_IDX, 0, 3) -FIELD(TB_FLAGS, LMUL, 3, 3) -FIELD(TB_FLAGS, SEW, 6, 3) -/* Skip MSTATUS_VS (0x600) bits */ -FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) -FIELD(TB_FLAGS, VILL, 12, 1) -/* Skip MSTATUS_FS (0x6000) bits */ +FIELD(TB_FLAGS, FS, 3, 2) +/* Vector flags */ +FIELD(TB_FLAGS, VS, 5, 2) +FIELD(TB_FLAGS, LMUL, 7, 3) +FIELD(TB_FLAGS, SEW, 10, 3) +FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) +FIELD(TB_FLAGS, VILL, 14, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 15, 1) FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1d90977d46..8412ef26ee 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -79,16 +79,17 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ul= ong *pc, } =20 #ifdef CONFIG_USER_ONLY - flags |=3D TB_FLAGS_MSTATUS_FS; - flags |=3D TB_FLAGS_MSTATUS_VS; + flags =3D FIELD_DP32(flags, TB_FLAGS, FS, EXT_STATUS_DIRTY); + flags =3D FIELD_DP32(flags, TB_FLAGS, VS, EXT_STATUS_DIRTY); #else flags |=3D cpu_mmu_index(env, 0); if (riscv_cpu_fp_enabled(env)) { - flags |=3D env->mstatus & MSTATUS_FS; + flags =3D FIELD_DP32(flags, TB_FLAGS, FS, + get_field(env->mstatus, MSTATUS_FS)); } - if (riscv_cpu_vector_enabled(env)) { - flags |=3D env->mstatus & MSTATUS_VS; + flags =3D FIELD_DP32(flags, TB_FLAGS, VS, + get_field(env->mstatus, MSTATUS_VS)); } =20 if (riscv_has_ext(env, RVH)) { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ebd00529ff..411e771e6f 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -64,10 +64,10 @@ typedef struct DisasContext { RISCVMXL xl; uint32_t misa_ext; uint32_t opcode; - uint32_t mstatus_fs; - uint32_t mstatus_vs; - uint32_t mstatus_hs_fs; - uint32_t mstatus_hs_vs; + RISCVExtStatus mstatus_fs; + RISCVExtStatus mstatus_vs; + RISCVExtStatus mstatus_hs_fs; + RISCVExtStatus mstatus_hs_vs; uint32_t mem_idx; /* * Remember the rounding mode encoded in the previous fp instruction, @@ -601,8 +601,6 @@ static TCGv get_address_indexed(DisasContext *ctx, int = rs1, TCGv offs) =20 #ifndef CONFIG_USER_ONLY /* - * The states of mstatus_fs are: - * 0 =3D disabled, 1 =3D initial, 2 =3D clean, 3 =3D dirty * We will have already diagnosed disabled state, * and need to turn initial/clean into dirty. */ @@ -614,9 +612,9 @@ static void mark_fs_dirty(DisasContext *ctx) return; } =20 - if (ctx->mstatus_fs !=3D MSTATUS_FS) { + if (ctx->mstatus_fs !=3D EXT_STATUS_DIRTY) { /* Remember the state change for the rest of the TB. */ - ctx->mstatus_fs =3D MSTATUS_FS; + ctx->mstatus_fs =3D EXT_STATUS_DIRTY; =20 tmp =3D tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); @@ -624,9 +622,9 @@ static void mark_fs_dirty(DisasContext *ctx) tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); } =20 - if (ctx->virt_enabled && ctx->mstatus_hs_fs !=3D MSTATUS_FS) { + if (ctx->virt_enabled && ctx->mstatus_hs_fs !=3D EXT_STATUS_DIRTY) { /* Remember the stage change for the rest of the TB. */ - ctx->mstatus_hs_fs =3D MSTATUS_FS; + ctx->mstatus_hs_fs =3D EXT_STATUS_DIRTY; =20 tmp =3D tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); @@ -640,8 +638,6 @@ static inline void mark_fs_dirty(DisasContext *ctx) { } =20 #ifndef CONFIG_USER_ONLY /* - * The states of mstatus_vs are: - * 0 =3D disabled, 1 =3D initial, 2 =3D clean, 3 =3D dirty * We will have already diagnosed disabled state, * and need to turn initial/clean into dirty. */ @@ -649,9 +645,9 @@ static void mark_vs_dirty(DisasContext *ctx) { TCGv tmp; =20 - if (ctx->mstatus_vs !=3D MSTATUS_VS) { + if (ctx->mstatus_vs !=3D EXT_STATUS_DIRTY) { /* Remember the state change for the rest of the TB. */ - ctx->mstatus_vs =3D MSTATUS_VS; + ctx->mstatus_vs =3D EXT_STATUS_DIRTY; =20 tmp =3D tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); @@ -659,9 +655,9 @@ static void mark_vs_dirty(DisasContext *ctx) tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); } =20 - if (ctx->virt_enabled && ctx->mstatus_hs_vs !=3D MSTATUS_VS) { + if (ctx->virt_enabled && ctx->mstatus_hs_vs !=3D EXT_STATUS_DIRTY) { /* Remember the stage change for the rest of the TB. */ - ctx->mstatus_hs_vs =3D MSTATUS_VS; + ctx->mstatus_hs_vs =3D EXT_STATUS_DIRTY; =20 tmp =3D tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); @@ -1168,8 +1164,8 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) =20 ctx->pc_succ_insn =3D ctx->base.pc_first; ctx->mem_idx =3D FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); - ctx->mstatus_fs =3D tb_flags & TB_FLAGS_MSTATUS_FS; - ctx->mstatus_vs =3D tb_flags & TB_FLAGS_MSTATUS_VS; + ctx->mstatus_fs =3D FIELD_EX32(tb_flags, TB_FLAGS, FS); + ctx->mstatus_vs =3D FIELD_EX32(tb_flags, TB_FLAGS, VS); ctx->priv_ver =3D env->priv_ver; ctx->virt_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); ctx->misa_ext =3D env->misa_ext; diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index 9e9fa2087a..b2de4fcf3f 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -19,7 +19,7 @@ */ =20 #define REQUIRE_FPU do {\ - if (ctx->mstatus_fs =3D=3D 0) \ + if (ctx->mstatus_fs =3D=3D EXT_STATUS_DISABLED) \ if (!ctx->cfg_ptr->ext_zfinx) \ return false; \ } while (0) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index ca3c4c1a3d..ecbdf1b3d7 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -29,12 +29,12 @@ static inline bool is_overlapped(const int8_t astart, i= nt8_t asize, =20 static bool require_rvv(DisasContext *s) { - return s->mstatus_vs !=3D 0; + return s->mstatus_vs !=3D EXT_STATUS_DISABLED; } =20 static bool require_rvf(DisasContext *s) { - if (s->mstatus_fs =3D=3D 0) { + if (s->mstatus_fs =3D=3D EXT_STATUS_DISABLED) { return false; } =20 @@ -52,7 +52,7 @@ static bool require_rvf(DisasContext *s) =20 static bool require_scale_rvf(DisasContext *s) { - if (s->mstatus_fs =3D=3D 0) { + if (s->mstatus_fs =3D=3D EXT_STATUS_DISABLED) { return false; } =20 @@ -70,7 +70,7 @@ static bool require_scale_rvf(DisasContext *s) =20 static bool require_scale_rvfmin(DisasContext *s) { - if (s->mstatus_fs =3D=3D 0) { + if (s->mstatus_fs =3D=3D EXT_STATUS_DISABLED) { return false; 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[37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299819; x=1683891819; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HVh+zRIWjFC/l6dDWYElki++Cx2rWrykEl8ZmED7Ed8=; b=YaXR6NLhUnlhFhTFwv7nDOMCXYgU3nYRjTq9B1DYQ+cJqZbRxManFIGWPSkttA7HJS ZWdwnWOF3gEKuYsHzPVFLXpbOjmko6zdhCqr6VCE1dIkbPicPjUfrbYyq4aLfaRnWYWT Drbhg7KM7ev1mL0z1aBgNso9h6xOXNJyhEao0NsOUDV50yEspegRRBqZvui6AureN6FA QD+AopDjNIh5gCWPf2EdneCKVsj4NXK5YEWBIXziffAnDfT30HW/t8IJI1enOD2A33Ev SCWnjcTKUXlFOIly1hqpbAPp9b1xO9rcFTA3HYRJVfQOb4nO4Bsd2XiAF58bPtszw7v4 nBTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299819; x=1683891819; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HVh+zRIWjFC/l6dDWYElki++Cx2rWrykEl8ZmED7Ed8=; b=fF04NbfN4vpc8bMGsI/+9fCXtpdxW7Oouk0Ei27EnehqfJQLhh8oFUorlVoQpgqIQE B9xRtAbBJqTv3iJK9pZ5CBuAiVlJXlG3xQEGrXTZhg6fDSzJlghg0zgYJxLGqe4YA9lm 0MazShE0j48JACnrqkGEB2YQuc4e3bsdcIDGbmRk5qFPDwuc96h/1VoFumaIWMgNG5pt j1ZsnBkmosiaHBgN/Zmj92nYJ5Vz0brLIGOB0ntRrIbjXureuPjMPklTbwdWRmpttq13 Dq2PEgkBbIC0hRAlm5HqXFNPjLvdmH9msvC3UlU9WUXvxymlzqJBGPN4HKElfuYzLOLU +b4w== X-Gm-Message-State: AAQBX9fK+HUlPDKP8gV+54QvEH8BK5BXRmIc9/M7jYaNjNBt05fsi4n6 W2HEanCRJtRjV9mcM987ZJAEgm9etkrR+Vycn3n6bj6n X-Google-Smtp-Source: AKy350bnNL0E4BaJrr1O9+srEw074qy39l9s4Ou49ZTz4tYafkz7m3hQlZvZEwuiDjuXufH6S4bSDQ== X-Received: by 2002:a5d:61c8:0:b0:2f4:cf53:c961 with SMTP id q8-20020a5d61c8000000b002f4cf53c961mr878137wrv.54.1681299818713; Wed, 12 Apr 2023 04:43:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, LIU Zhiwei , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 04/25] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags Date: Wed, 12 Apr 2023 13:43:12 +0200 Message-Id: <20230412114333.118895-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681299869428100003 Content-Type: text/plain; charset="utf-8" Merge with mstatus_{fs,vs}. We might perform a redundant assignment to one or the other field, but it's a trivial and saves 4 bits from TB_FLAGS. Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-5-richard.henderson@linaro.org> --- target/riscv/cpu.h | 16 +++++++--------- target/riscv/cpu_helper.c | 33 ++++++++++++++++----------------- target/riscv/translate.c | 32 ++++++++++---------------------- 3 files changed, 33 insertions(+), 48 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 51d39687fe..ab64d5f92d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -644,19 +644,17 @@ FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) FIELD(TB_FLAGS, VILL, 14, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 15, 1) -FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) -FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ -FIELD(TB_FLAGS, XL, 20, 2) +FIELD(TB_FLAGS, XL, 16, 2) /* If PointerMasking should be applied */ -FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) -FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) -FIELD(TB_FLAGS, VTA, 24, 1) -FIELD(TB_FLAGS, VMA, 25, 1) +FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) +FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) +FIELD(TB_FLAGS, VTA, 20, 1) +FIELD(TB_FLAGS, VMA, 21, 1) /* Native debug itrigger */ -FIELD(TB_FLAGS, ITRIGGER, 26, 1) +FIELD(TB_FLAGS, ITRIGGER, 22, 1) /* Virtual mode enabled */ -FIELD(TB_FLAGS, VIRT_ENABLED, 27, 1) +FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8412ef26ee..e3e620137b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -45,7 +45,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulon= g *pc, { CPUState *cs =3D env_cpu(env); RISCVCPU *cpu =3D RISCV_CPU(cs); - + RISCVExtStatus fs, vs; uint32_t flags =3D 0; =20 *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; @@ -79,18 +79,12 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ul= ong *pc, } =20 #ifdef CONFIG_USER_ONLY - flags =3D FIELD_DP32(flags, TB_FLAGS, FS, EXT_STATUS_DIRTY); - flags =3D FIELD_DP32(flags, TB_FLAGS, VS, EXT_STATUS_DIRTY); + fs =3D EXT_STATUS_DIRTY; + vs =3D EXT_STATUS_DIRTY; #else flags |=3D cpu_mmu_index(env, 0); - if (riscv_cpu_fp_enabled(env)) { - flags =3D FIELD_DP32(flags, TB_FLAGS, FS, - get_field(env->mstatus, MSTATUS_FS)); - } - if (riscv_cpu_vector_enabled(env)) { - flags =3D FIELD_DP32(flags, TB_FLAGS, VS, - get_field(env->mstatus, MSTATUS_VS)); - } + fs =3D get_field(env->mstatus, MSTATUS_FS); + vs =3D get_field(env->mstatus, MSTATUS_VS); =20 if (riscv_has_ext(env, RVH)) { if (env->priv =3D=3D PRV_M || @@ -100,18 +94,23 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_u= long *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, HLSX, 1); } =20 - flags =3D FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, - get_field(env->mstatus_hs, MSTATUS_FS)); - - flags =3D FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, - get_field(env->mstatus_hs, MSTATUS_VS)); - flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, env->virt_enab= led); + if (env->virt_enabled) { + flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); + /* + * Merge DISABLED and !DIRTY states using MIN. + * We will set both fields when dirtying. + */ + fs =3D MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); + vs =3D MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); + } } if (cpu->cfg.debug && !icount_enabled()) { flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); } #endif =20 + flags =3D FIELD_DP32(flags, TB_FLAGS, FS, fs); + flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); if (env->cur_pmmask < (env->xl =3D=3D MXL_RV32 ? UINT32_MAX : UINT64_M= AX)) { flags =3D FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 411e771e6f..3092c942ab 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -66,8 +66,6 @@ typedef struct DisasContext { uint32_t opcode; RISCVExtStatus mstatus_fs; RISCVExtStatus mstatus_vs; - RISCVExtStatus mstatus_hs_fs; - RISCVExtStatus mstatus_hs_vs; uint32_t mem_idx; /* * Remember the rounding mode encoded in the previous fp instruction, @@ -620,16 +618,12 @@ static void mark_fs_dirty(DisasContext *ctx) tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); - } =20 - if (ctx->virt_enabled && ctx->mstatus_hs_fs !=3D EXT_STATUS_DIRTY) { - /* Remember the stage change for the rest of the TB. */ - ctx->mstatus_hs_fs =3D EXT_STATUS_DIRTY; - - tmp =3D tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); - tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + if (ctx->virt_enabled) { + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs= )); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs= )); + } } } #else @@ -653,16 +647,12 @@ static void mark_vs_dirty(DisasContext *ctx) tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); - } =20 - if (ctx->virt_enabled && ctx->mstatus_hs_vs !=3D EXT_STATUS_DIRTY) { - /* Remember the stage change for the rest of the TB. */ - ctx->mstatus_hs_vs =3D EXT_STATUS_DIRTY; - - tmp =3D tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); - tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); - tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + if (ctx->virt_enabled) { + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs= )); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs= )); + } } } #else @@ -1171,8 +1161,6 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->misa_ext =3D env->misa_ext; ctx->frm =3D -1; /* unknown rounding mode */ ctx->cfg_ptr =3D &(cpu->cfg); - ctx->mstatus_hs_fs =3D FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); - ctx->mstatus_hs_vs =3D FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); ctx->hlsx =3D FIELD_EX32(tb_flags, TB_FLAGS, HLSX); ctx->vill =3D FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew =3D FIELD_EX32(tb_flags, TB_FLAGS, SEW); --=20 2.34.1 From nobody Fri May 17 04:49:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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[37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299819; x=1683891819; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MWsW7ULWn4A1fSKqhQgD2QQ0V+0wVuw8Sc2XWLbfpiw=; b=EaGiVx4GjyyxgSsuNjJfa17MmsOKGI61kKrBoCOg/r7MFkgDWealhajr5GU/1r361p lsBlJ5LSdh3Gu5YaDhGX7so8r8b9mlAxU2z/lzBqBtR1NHidKH6xFCGckErGpkdUcVrA dvbyvUFKT8U1UZvWjpg6QR2ZM+hbwCSUHDutG6KZXJrNmTYYxdbA0kQZrP14dZa5xRa/ 1qWkSHXfWU1w0kk7UUgZbd+BMuX6VLaz59aMnOZYoOdsqItr3NP7jhgCWsl6ES7tVoUW gqvmBUfMDIovJUDfbEFsWvh9IBS6s6PnnAKWlz5FMSdxhawBC1UdQOBtJdnd34iW1jQT EpCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299819; x=1683891819; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MWsW7ULWn4A1fSKqhQgD2QQ0V+0wVuw8Sc2XWLbfpiw=; b=K2eNtzgudVG7RPQnpg6nrKmFgJV61DcbDiHacL+lIZOoPujBLx8lM+L+xQ0J8YIzI+ m2Al/T/oyKTtd8d4BYy93aqBiZ3fSPssxGohU3Z1ATZZqAa9KPixP2lc6U9DKuj5OLoR hSK6L11dMESm/iVyOQVwxWzELEwuD9zt6y8ajYNnl6E+Eyx8reQTtifVZtVSJkjWmI9h YVSXuuHtmq5RDjN5zr+B0nF1O4GgjnixgeplHa9N7GcUgTBI5qX5ZWKBPVnOkamZdYae Omc8xr4jjC1AcPgI/KmGFXwKUMWIAgeA/CgsnEiy+8VExCUtBiziNpFOhLTnIxZzFrWp NGiQ== X-Gm-Message-State: AAQBX9fXeVLbjV3AI6/9JDAlv3Y8byRSLaGBvqchyFy9/NToxGrRiWcR QrtFO8aL1d6IkSXjYV+zOZzkJMM8nDzKAszRXBD246W1 X-Google-Smtp-Source: AKy350bLbx8sijfM45JuFC1RyuNL0nuur4YKtVteIDEvu53o+No+y1jx0z5AB2ht9hoq8Gu2cWEVTw== X-Received: by 2002:adf:f1ca:0:b0:2f4:eb13:4091 with SMTP id z10-20020adff1ca000000b002f4eb134091mr758520wro.45.1681299819677; Wed, 12 Apr 2023 04:43:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, LIU Zhiwei , Weiwei Li , Alistair Francis , Daniel Henrique Barboza Subject: [PATCH v7 05/25] target/riscv: Add a tb flags field for vstart Date: Wed, 12 Apr 2023 13:43:13 +0200 Message-Id: <20230412114333.118895-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681299900304100007 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei Once we mistook the vstart directly from the env->vstart. As env->vstart is= not a constant, we should record it in the tb flags if we want to use it in translation. Reported-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: LIU Zhiwei Reviewed-by: Weiwei Li Message-Id: <20230324143031.1093-5-zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-6-richard.henderson@linaro.org> --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 1 + target/riscv/translate.c | 4 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 14 +++++++------- 4 files changed, 11 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ab64d5f92d..786ad047ee 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -655,6 +655,7 @@ FIELD(TB_FLAGS, VMA, 21, 1) FIELD(TB_FLAGS, ITRIGGER, 22, 1) /* Virtual mode enabled */ FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) +FIELD(TB_FLAGS, VSTART_EQ_ZERO, 24, 1) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e3e620137b..7579e83c3d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -74,6 +74,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulon= g *pc, FIELD_EX64(env->vtype, VTYPE, VTA)); flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, FIELD_EX64(env->vtype, VTYPE, VMA)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart = =3D=3D 0); } else { flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3092c942ab..3ab8a9999e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -99,7 +99,7 @@ typedef struct DisasContext { uint8_t vta; uint8_t vma; bool cfg_vta_all_1s; - target_ulong vstart; + bool vstart_eq_zero; bool vl_eq_vlmax; CPUState *cs; TCGv zero; @@ -1168,7 +1168,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->vta =3D FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_al= l_1s; ctx->vma =3D FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_al= l_1s; ctx->cfg_vta_all_1s =3D cpu->cfg.rvv_ta_all_1s; - ctx->vstart =3D env->vstart; + ctx->vstart_eq_zero =3D FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->misa_mxl_max =3D env->misa_mxl_max; ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index ecbdf1b3d7..6c07eebc52 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -547,7 +547,7 @@ static bool vext_check_sds(DisasContext *s, int vd, int= vs1, int vs2, int vm) */ static bool vext_check_reduction(DisasContext *s, int vs2) { - return require_align(vs2, s->lmul) && (s->vstart =3D=3D 0); + return require_align(vs2, s->lmul) && s->vstart_eq_zero; } =20 /* @@ -3083,7 +3083,7 @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *a) { if (require_rvv(s) && vext_check_isa_ill(s) && - s->vstart =3D=3D 0) { + s->vstart_eq_zero) { TCGv_ptr src2, mask; TCGv dst; TCGv_i32 desc; @@ -3112,7 +3112,7 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *= a) { if (require_rvv(s) && vext_check_isa_ill(s) && - s->vstart =3D=3D 0) { + s->vstart_eq_zero) { TCGv_ptr src2, mask; TCGv dst; TCGv_i32 desc; @@ -3148,7 +3148,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ vext_check_isa_ill(s) && \ require_vm(a->vm, a->rd) && \ (a->rd !=3D a->rs2) && \ - (s->vstart =3D=3D 0)) { \ + s->vstart_eq_zero) { \ uint32_t data =3D 0; \ gen_helper_gvec_3_ptr *fn =3D gen_helper_##NAME; \ TCGLabel *over =3D gen_new_label(); \ @@ -3189,7 +3189,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_= m *a) !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) && require_vm(a->vm, a->rd) && require_align(a->rd, s->lmul) && - (s->vstart =3D=3D 0)) { + s->vstart_eq_zero) { uint32_t data =3D 0; TCGLabel *over =3D gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); @@ -3638,7 +3638,7 @@ static bool vcompress_vm_check(DisasContext *s, arg_r= *a) require_align(a->rs2, s->lmul) && (a->rd !=3D a->rs2) && !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs1, 1) && - (s->vstart =3D=3D 0); + s->vstart_eq_zero; } =20 static bool trans_vcompress_vm(DisasContext *s, arg_r *a) @@ -3677,7 +3677,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME = * a) \ QEMU_IS_ALIGNED(a->rd, LEN) && \ QEMU_IS_ALIGNED(a->rs2, LEN)) { \ uint32_t maxsz =3D (s->cfg_ptr->vlen >> 3) * LEN; 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[37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299820; x=1683891820; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AmmNXj22HP7KMuzDURhipUP2NYBo1bwlMxGUrM5ujg4=; b=JYxktg14OyscHvAJSlWTTTMGJoWJab/Pv42K4KJzZYMTdfQHZkBqhiam+/nHG9/1Kb zqQmsGBvCIDo26AQY/2H7ehJIC286cEdZEzxp6ULD5UQsAwBMN5DcU7hICY0BTs4F7vX 4HRgFBAVE5/RMEeb9fr5S7Sk969lHxW/zoJHhO5FujSBBSq9XpZzwHz/zK/iDZAaV42p EGkVpJEyjHxKLarB7wVe94Ys6/l8zO4E5tQCfMgR7pqmRXSdsdwpBaEYOG6OTbIG+ru2 aWDHROFHbbv7cah2aXMDF8qcW1JJNb+YFyZGrUR055NUxnih7sygK7e4qdis75wDFlHg kNSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299820; x=1683891820; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AmmNXj22HP7KMuzDURhipUP2NYBo1bwlMxGUrM5ujg4=; b=2iCu3WXVzg9ikqGVWiuEvL8j8T1qs20PV9HLH4GHBi7zz1Ml24bvaXwaUKwYbSsrsw F35HkdRr6zM2xSoffAyKIcAhyS4GFVm1ZNoeKyN90erSpCPbyz6tpncsuKeivcU9rXp2 K85W0FFwA5+GaMFgg6UBqFyfATuhe+/hLU9ACgUJL9H46a1doQmtWEU/s4jcO8AWXgKS CSxnlqFtoUptCC2THS4PSRUiELru7btrgB5V8LMusSN41lmlxMy9DalHdvb7wAW+Vj/r W3t8TiJ3dOS9pUsm1q2WnCc/UEAGlOrqVdRUAa/CMrzsVof4rae06HaIYVONASoMJmt7 TDXg== X-Gm-Message-State: AAQBX9d0bUNumfy31lK5UJIKsLmSz/fmgT9CkaHvaD/hSlJ7I4h7M0SE fG5V6jkTggpAZcNNyTOtN4KOjREZ/fRQxdF2qXYQzvm5 X-Google-Smtp-Source: AKy350bS17pNkKhRKU9MhNTKrRPWregoNroRduIxpAB8VWimeMKiS5hGyoyCKfKBv16Sq6DfMx5oUg== X-Received: by 2002:adf:db47:0:b0:2f2:4db4:1f5b with SMTP id f7-20020adfdb47000000b002f24db41f5bmr4751710wrj.29.1681299820519; Wed, 12 Apr 2023 04:43:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Fei Wu , LIU Zhiwei , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 06/25] target/riscv: Separate priv from mmu_idx Date: Wed, 12 Apr 2023 13:43:14 +0200 Message-Id: <20230412114333.118895-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681300328276100002 Content-Type: text/plain; charset="utf-8" From: Fei Wu Currently it's assumed the 2 low bits of mmu_idx map to privilege mode, this assumption won't last as we are about to add more mmu_idx. Here an individual priv field is added into TB_FLAGS. Reviewed-by: Richard Henderson Signed-off-by: Fei Wu Message-Id: <20230324054154.414846-2-fei2.wu@intel.com> Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-7-richard.henderson@linaro.org> --- target/riscv/cpu.h | 2 +- target/riscv/cpu_helper.c | 4 +++- target/riscv/translate.c | 2 ++ target/riscv/insn_trans/trans_privileged.c.inc | 2 +- target/riscv/insn_trans/trans_xthead.c.inc | 14 +------------- 5 files changed, 8 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 786ad047ee..9b971ee1b0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -629,7 +629,6 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *en= v, target_ulong riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); =20 -#define TB_FLAGS_PRIV_MMU_MASK 3 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) =20 #include "exec/cpu-all.h" @@ -656,6 +655,7 @@ FIELD(TB_FLAGS, ITRIGGER, 22, 1) /* Virtual mode enabled */ FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) FIELD(TB_FLAGS, VSTART_EQ_ZERO, 24, 1) +FIELD(TB_FLAGS, PRIV, 25, 2) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 7579e83c3d..36d6e422d7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -83,6 +83,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulon= g *pc, fs =3D EXT_STATUS_DIRTY; vs =3D EXT_STATUS_DIRTY; #else + flags =3D FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); + flags |=3D cpu_mmu_index(env, 0); fs =3D get_field(env->mstatus, MSTATUS_FS); vs =3D get_field(env->mstatus, MSTATUS_VS); @@ -751,7 +753,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, */ MemTxResult res; MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; - int mode =3D mmu_idx & TB_FLAGS_PRIV_MMU_MASK; + int mode =3D env->priv; bool use_background =3D false; hwaddr ppn; int napot_bits =3D 0; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3ab8a9999e..6d59348f0c 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -67,6 +67,7 @@ typedef struct DisasContext { RISCVExtStatus mstatus_fs; RISCVExtStatus mstatus_vs; uint32_t mem_idx; + uint32_t priv; /* * Remember the rounding mode encoded in the previous fp instruction, * which we have already installed into env->fp_status. Or -1 for @@ -1153,6 +1154,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) uint32_t tb_flags =3D ctx->base.tb->flags; =20 ctx->pc_succ_insn =3D ctx->base.pc_first; + ctx->priv =3D FIELD_EX32(tb_flags, TB_FLAGS, PRIV); ctx->mem_idx =3D FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); ctx->mstatus_fs =3D FIELD_EX32(tb_flags, TB_FLAGS, FS); ctx->mstatus_vs =3D FIELD_EX32(tb_flags, TB_FLAGS, VS); diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index e3bee971c6..7c2837194c 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -52,7 +52,7 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) * that no exception will be raised when fetching them. */ =20 - if (semihosting_enabled(ctx->mem_idx < PRV_S) && + if (semihosting_enabled(ctx->priv =3D=3D PRV_U) && (pre_addr & TARGET_PAGE_MASK) =3D=3D (post_addr & TARGET_PAGE_MASK= )) { pre =3D opcode_at(&ctx->base, pre_addr); ebreak =3D opcode_at(&ctx->base, ebreak_addr); diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index df504c3f2c..3e13b1d74d 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -263,25 +263,13 @@ static bool trans_th_tst(DisasContext *ctx, arg_th_ts= t *a) =20 /* XTheadCmo */ =20 -static inline int priv_level(DisasContext *ctx) -{ -#ifdef CONFIG_USER_ONLY - return PRV_U; -#else - /* Priv level is part of mem_idx. */ - return ctx->mem_idx & TB_FLAGS_PRIV_MMU_MASK; -#endif -} - /* Test if priv level is M, S, or U (cannot fail). */ #define REQUIRE_PRIV_MSU(ctx) =20 /* Test if priv level is M or S. */ #define REQUIRE_PRIV_MS(ctx) \ do { \ - int priv =3D priv_level(ctx); \ - if (!(priv =3D=3D PRV_M || \ - priv =3D=3D PRV_S)) { \ + if (ctx->priv =3D=3D PRV_U) { \ return false; \ } \ } while (0) --=20 2.34.1 From nobody Fri May 17 04:49:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1681300052; cv=none; d=zohomail.com; s=zohoarc; b=fZRABfBhE75HiIk5UmvPOFCfURcobDUkFA2vRCkgnJeh0268QPlob6hge6Q+JdKuhv6MIL/LelFRtZHOG5gveKkbG+ATBF7PK9B39v+syKZ0Wkx73pngVocHtQjq+A140w8+odHLzoUyjOf75GjjCwHxsBOkuwq405eEoiudgTE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681300052; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vFpmN4l+aiQZzHkMQF0Is1Gbr8TTg8AJfI2hz+TEgNU=; b=Aq8XFXrbTr7F1f/FvsLVtGo8bcwPHTJuQtLwLYVqhm56XomUlT6yITWjk6uDHBGKs9DHp4PECIH5jR8VW8YVhy4VxGJs3sInlTQaZdOBUWZ6XuACrlHspDlwsuOplaapgoU6KL2PjIsPblrO+jAsxy8vo0W3a/x1X324O1ybT9U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681300052100362.88284357359146; Wed, 12 Apr 2023 04:47:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pmYtd-0005m8-Vs; Wed, 12 Apr 2023 07:44:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pmYt8-0004l5-DZ for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:47 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pmYt4-0002NE-1m for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:45 -0400 Received: by mail-wr1-x432.google.com with SMTP id l18so10512845wrb.9 for ; Wed, 12 Apr 2023 04:43:41 -0700 (PDT) Received: from stoup.hotel.gast (ip-037-024-010-236.um08.pools.vodafone-ip.de. [37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299821; x=1683891821; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vFpmN4l+aiQZzHkMQF0Is1Gbr8TTg8AJfI2hz+TEgNU=; b=nubkifGATpQrBCVy4n7E0dP6pAc1PkiFqkKd3VkYpkLWWgA+z6/AHXD6SsbJB9QUxd 0Od0dfFs161Qb7JD776X970PESx5q24GgMNOZTlVNSSGnoQPm334rfc1Hy/dHrmsn09V flmFoJ6Ztu4yqFM0wwe2JXdvgWLEEG92aj+3anO/UjpqIO3Q0K8POx/UZM0X9/kIrEc4 f6Od1BxtJgiCC0yKN8PA/td1VNllIFEOve8KI39zWjkdHHg25XOYj6VTub8559IXCIB1 uKnG3YaK3AsAq0sGOTQrwDCY2NLkE3kQl4Zgn1lQQ5bQoW8Klx8pSq26bRKd5OC1Xm+A 5rGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299821; x=1683891821; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vFpmN4l+aiQZzHkMQF0Is1Gbr8TTg8AJfI2hz+TEgNU=; b=tu78DYeATl0JJIwHDVMt9ayDDie0zz/0oIPTrKT+Zs5ve/2aoO3lWAHu0YaV/KxScv eOuM7hG/9cEbuL0DY1fbA6uaR67DOZ79QmjAxcoRoNkN2zxVWLM0i1aKNKRzEJ6wPdcG GhR7Y+Te5/JoLZ5h5dzk4ce9QNQ29qdk2wzEOIsxOvdd1q2cvW6XEI0TrCkTCSN37FnI cpzfgpBrL6iKeAM8RaElmpk8lOTCMK5fxOXdnz3Vixd2EHspdUCJmVXpQzeykLwz7xSh w1hl1hl//l+/BD/uiKO6etAtNnS2He1LShD9VL+i4ETeGxmxbKdyRrWbWph2d0zzyYuc YeKg== X-Gm-Message-State: AAQBX9c0rDSmTPhyjLPUshKuKIRZs4Y8uaSEmu+bczwo0UAF5/45qekG s733nFpvYaql+brcMuK+OIuyRVtydxBZTeMnu85g2JRc X-Google-Smtp-Source: AKy350b+ahkWuQAw9FZv7AL7NFyGVT3t587ErzSTQFFa+wBqbH0GFUV3GHovjV1NBoRHYBzD2umlGQ== X-Received: by 2002:adf:dfcc:0:b0:2ef:af46:1278 with SMTP id q12-20020adfdfcc000000b002efaf461278mr11347284wrn.10.1681299821156; Wed, 12 Apr 2023 04:43:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Fei Wu , LIU Zhiwei , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 07/25] target/riscv: Reduce overhead of MSTATUS_SUM change Date: Wed, 12 Apr 2023 13:43:15 +0200 Message-Id: <20230412114333.118895-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681300054008100010 Content-Type: text/plain; charset="utf-8" From: Fei Wu Kernel needs to access user mode memory e.g. during syscalls, the window is usually opened up for a very limited time through MSTATUS.SUM, the overhead is too much if tlb_flush() gets called for every SUM change. This patch creates a separate MMU index for S+SUM, so that it's not necessary to flush tlb anymore when SUM changes. This is similar to how ARM handles Privileged Access Never (PAN). Result of 'pipe 10' from unixbench boosts from 223656 to 1705006. Many other syscalls benefit a lot from this too. Reviewed-by: Richard Henderson Signed-off-by: Fei Wu Message-Id: <20230324054154.414846-3-fei2.wu@intel.com> Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-8-richard.henderson@linaro.org> --- target/riscv/cpu.h | 2 -- target/riscv/internals.h | 14 ++++++++++++++ target/riscv/cpu_helper.c | 17 +++++++++++++++-- target/riscv/csr.c | 3 +-- target/riscv/op_helper.c | 5 +++-- target/riscv/insn_trans/trans_rvh.c.inc | 4 ++-- 6 files changed, 35 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9b971ee1b0..6239c99f4c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -629,8 +629,6 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *en= v, target_ulong riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); =20 -#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) - #include "exec/cpu-all.h" =20 FIELD(TB_FLAGS, MEM_IDX, 0, 3) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 5620fbffb6..b55152a7dc 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -21,6 +21,20 @@ =20 #include "hw/registerfields.h" =20 +/* + * The current MMU Modes are: + * - U 0b000 + * - S 0b001 + * - S+SUM 0b010 + * - M 0b011 + * - HLV/HLVX/HSV adds 0b100 + */ +#define MMUIdx_U 0 +#define MMUIdx_S 1 +#define MMUIdx_S_SUM 2 +#define MMUIdx_M 3 +#define MMU_HYP_ACCESS_BIT (1 << 2) + /* share data between vector helpers and decode code */ FIELD(VDATA, VM, 0, 1) FIELD(VDATA, LMUL, 1, 3) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 36d6e422d7..174a77706b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "qemu/main-loop.h" #include "cpu.h" +#include "internals.h" #include "pmu.h" #include "exec/exec-all.h" #include "instmap.h" @@ -36,7 +37,19 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #ifdef CONFIG_USER_ONLY return 0; #else - return env->priv; + if (ifetch) { + return env->priv; + } + + /* All priv -> mmu_idx mapping are here */ + int mode =3D env->priv; + if (mode =3D=3D PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { + mode =3D get_field(env->mstatus, MSTATUS_MPP); + } + if (mode =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_SUM)) { + return MMUIdx_S_SUM; + } + return mode; #endif } =20 @@ -588,7 +601,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, boo= l enable) =20 bool riscv_cpu_two_stage_lookup(int mmu_idx) { - return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; + return mmu_idx & MMU_HYP_ACCESS_BIT; } =20 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4268828dc4..124be448dc 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1270,8 +1270,7 @@ static RISCVException write_mstatus(CPURISCVState *en= v, int csrno, val =3D legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val); =20 /* flush tlb on mstatus fields that affect VM */ - if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | - MSTATUS_MPRV | MSTATUS_SUM)) { + if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPV)) { tlb_flush(env_cpu(env)); } mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index bd21c6eeef..00bdf77f32 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -20,6 +20,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "internals.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -428,14 +429,14 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) =20 target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address) { - int mmu_idx =3D cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK; + int mmu_idx =3D cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT; =20 return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); } =20 target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address) { - int mmu_idx =3D cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK; + int mmu_idx =3D cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT; =20 return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); } diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index 4b730cd492..ae98b45e5e 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -42,7 +42,7 @@ static bool do_hlv(DisasContext *ctx, arg_r2 *a, MemOp mo= p) if (check_access(ctx)) { TCGv dest =3D dest_gpr(ctx, a->rd); TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - int mem_idx =3D ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK; + int mem_idx =3D ctx->mem_idx | MMU_HYP_ACCESS_BIT; tcg_gen_qemu_ld_tl(dest, addr, mem_idx, mop); gen_set_gpr(ctx, a->rd, dest); } @@ -89,7 +89,7 @@ static bool do_hsv(DisasContext *ctx, arg_r2_s *a, MemOp = mop) if (check_access(ctx)) { TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); - int mem_idx =3D ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK; + int mem_idx =3D ctx->mem_idx | MMU_HYP_ACCESS_BIT; tcg_gen_qemu_st_tl(data, addr, mem_idx, mop); } return true; --=20 2.34.1 From nobody Fri May 17 04:49:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299822; x=1683891822; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nYIzXxaKlE7pVBf36j8eV1KDqBsqyyZsO57pOhE6S3s=; b=ONqpGGePtrPAOKWUp+MMlXKvAAooORMK36G0DfY8L2Lp+ZSrKpcsQ2pvjEmclVEubR IaIlilj7qIVZ9slBvCt+e8nwPhQ1RM15ChtOwtvsPEqjypRxJoSdjHV2E26sY/se4Jp1 okiN+cCb7Be6FCD5MJlhnSNh6L5CUE4NsDSyL02NFqjsOsit8q/MPNwFE0+ieVuZri6l A/JkYWgMyOyTTJa0/NvxCOVCNyQli0blYlcYhoQ7WrqAdJ+umHlBIfr8w68HV5wagZpM Wh7knq6ENbQtJsuHrsUx/8gr8rhyz4/nO70sRIfeG1Uv4SIZkjZS3S+BzflAHi4V/N8u uyQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299822; x=1683891822; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nYIzXxaKlE7pVBf36j8eV1KDqBsqyyZsO57pOhE6S3s=; b=v+ZMsafqRMFT+6Hjz7YS3v8VdmkcQjezh5DvPUE2BXXKXEWxfH0RFs890gk3cFm/W0 ih6Acb9VsTY9+IcYvwg2zKAN4tNhHnJx+gOGBeAxuhjpQ6+i3NubqUwAbw9HYOe+cHCo wMOD/iLTFAQxk1Tu1qbEJTjaHeddyvqXp7nukXdXPqE3whfpuzzTCSGo12JhVTuUM3J1 uybR+2fJH3vWE0llKh/dI9KHM3q5ADNeQD6ZVxiUvlw+ij93c2QxrxK9DKgGu2XAmbXb B2bM23N8NgpQHzTQEgdjFhlslvujkljCg3+LBZC1/YbPa0JVD+sqm4WkrMxrNhVeAIxj ti8A== X-Gm-Message-State: AAQBX9flG3uSiR5r//uq1LftKm5UMLSiB8GZYjRvzpge1YnQVY1Nv+pG 78sdpMAmqgjT111HhLhRPozukcj7acR2nkWM6Ouk+xBO X-Google-Smtp-Source: AKy350ZKkbH7wXDu8y2Wni6JAVagqG7zb/Dzulmic22b8y+OJKUqI4vqXZUU9+TbOngZc6Sj5JMc1Q== X-Received: by 2002:adf:fa02:0:b0:2f2:7adf:3c67 with SMTP id m2-20020adffa02000000b002f27adf3c67mr3858978wrr.61.1681299822045; Wed, 12 Apr 2023 04:43:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 08/25] accel/tcg: Add cpu_ld*_code_mmu Date: Wed, 12 Apr 2023 13:43:16 +0200 Message-Id: <20230412114333.118895-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681300136939100003 Content-Type: text/plain; charset="utf-8" At least RISC-V has the need to be able to perform a read using execute permissions, outside of translation. Add helpers to facilitate this. Signed-off-by: Richard Henderson Acked-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-9-richard.henderson@linaro.org> --- include/exec/cpu_ldst.h | 9 +++++++ accel/tcg/cputlb.c | 48 ++++++++++++++++++++++++++++++++++ accel/tcg/user-exec.c | 58 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 115 insertions(+) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 09b55cc0ee..c141f0394f 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -445,6 +445,15 @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env= , uintptr_t mmu_idx, # define cpu_stq_mmu cpu_stq_le_mmu #endif =20 +uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra); +uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra); +uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra); +uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra); + uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr); uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr); uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e984a98dc4..e62c8f3c3f 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2768,3 +2768,51 @@ uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr add= r) MemOpIdx oi =3D make_memop_idx(MO_TEUQ, cpu_mmu_index(env, true)); return full_ldq_code(env, addr, oi, 0); } + +uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t retaddr) +{ + return full_ldub_code(env, addr, oi, retaddr); +} + +uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t retaddr) +{ + MemOp mop =3D get_memop(oi); + int idx =3D get_mmuidx(oi); + uint16_t ret; + + ret =3D full_lduw_code(env, addr, make_memop_idx(MO_TEUW, idx), retadd= r); + if ((mop & MO_BSWAP) !=3D MO_TE) { + ret =3D bswap16(ret); + } + return ret; +} + +uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t retaddr) +{ + MemOp mop =3D get_memop(oi); + int idx =3D get_mmuidx(oi); + uint32_t ret; + + ret =3D full_ldl_code(env, addr, make_memop_idx(MO_TEUL, idx), retaddr= ); + if ((mop & MO_BSWAP) !=3D MO_TE) { + ret =3D bswap32(ret); + } + return ret; +} + +uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t retaddr) +{ + MemOp mop =3D get_memop(oi); + int idx =3D get_mmuidx(oi); + uint64_t ret; + + ret =3D full_ldq_code(env, addr, make_memop_idx(MO_TEUQ, idx), retaddr= ); + if ((mop & MO_BSWAP) !=3D MO_TE) { + ret =3D bswap64(ret); + } + return ret; +} diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index a7e0c3e2f4..fc597a010d 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1219,6 +1219,64 @@ uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr) return ret; } =20 +uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + void *haddr; + uint8_t ret; + + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_INST_FETCH); + ret =3D ldub_p(haddr); + clear_helper_retaddr(); + return ret; +} + +uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + void *haddr; + uint16_t ret; + + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_INST_FETCH); + ret =3D lduw_p(haddr); + clear_helper_retaddr(); + if (get_memop(oi) & MO_BSWAP) { + ret =3D bswap16(ret); + } + return ret; +} + +uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + void *haddr; + uint32_t ret; + + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_INST_FETCH); + ret =3D ldl_p(haddr); + clear_helper_retaddr(); + if (get_memop(oi) & MO_BSWAP) { + ret =3D bswap32(ret); + } + return ret; +} + +uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + void *haddr; + uint64_t ret; + + validate_memop(oi, MO_BEUQ); + haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D ldq_p(haddr); + clear_helper_retaddr(); + if (get_memop(oi) & MO_BSWAP) { + ret =3D bswap64(ret); + } + return ret; +} + #include "ldst_common.c.inc" =20 /* --=20 2.34.1 From nobody Fri May 17 04:49:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1681300111; cv=none; d=zohomail.com; s=zohoarc; b=Ps35HV8qVsbpdiImIVIfE0ZNYNcW264VK/bDyPq+bFaXmPW+n5wiW9EnINv31j8xNhQndnh5v4rwlmOceuVRCkuhy+k5Z47Z5Z65mT/mvGKupKRo2PKZg0tDG6+05xX5L5ly9R16BH0vJGxwEnEm1azIArJ6SfQubgdrAcWqcMI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681300111; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jf2N922f7MxhHGZfTcgNdzsCq9UU22b0tOdlcxX9fy8=; b=lT1fRfJuVrFIm5EHEFeQ6riIamj1fAsx2f/O7HHk56I9HyHKdd1jQ8b6mfZtdqy93iTqe7KxyNHgFETCiludL4nAf0v4BAbSoETihi0Sei9DlhYvTBrZpu1yD670/G4HKEjgjlF7G+t5GGCgYMfkcOKD7fyE1LlbD3SA7fD4H0U= ARC-Authentication-Results: i=1; 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[37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299823; x=1683891823; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jf2N922f7MxhHGZfTcgNdzsCq9UU22b0tOdlcxX9fy8=; b=v/jWYxdJsgTuWFPt6wHpyVXn2fUj/zYPVBvMTgmj+8NBdxqnxOIr6zyx31dKLv5sb1 Sfie28Z3vW3trfGGnL5kSPdiUVVO0joqiR7ai//b4jKF19uxA9okt4+bE2EHzQaCMn0x APUQMJmhYKtWRT+nyCENCV+Uu85AydKyV98g5lkYq/bC83I2iPAFsGkhFFEE3SP2Q6eV o1lkCwKEPPHNT0/j+jblNG6qAu53yve3LL6hpW/fs1KH8pQ1K9XoPeuUP7jku/Vt7lEL WkRnCVFnDgwIQBaEyaNazdcfYly/h8jTN64LsmhvAV4QJ4+rWdTxMUjEAZEWUstQmoJa vU6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299823; x=1683891823; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jf2N922f7MxhHGZfTcgNdzsCq9UU22b0tOdlcxX9fy8=; b=PE7dsA15B32lB08sZsX45GAmtJ/+r72rrHicNk3JyRjlSpzTAbndotqQ7ZUiZrsMWx 2Oyo2KBzn+38aj9cmtx4pRiRBI+eQ1kAK7y5LKhffqpfUQ8cvwvPPWVFskaCC6gcjQHq NgvyvSMkB4Z6Z2YYQVMZUqF/dSnSMswQCE5qZ5miYRhC0QW31cQluTTZGfalCIZ9+EXY iaUTwAglwPL6hageHV10NwKmknvf7DZACif+TcHT/MEtEraka7DsRCUTeojETyl1x7bK f2wKXMmBEKH1Zcw/PTk+OjXDDp6U7pmhfUBa1coZtyecAV/lh6aAcII88oiO85/MZKm7 nOBA== X-Gm-Message-State: AAQBX9fefW6P8eNCalruf+WycQFnAcFHDde0ST1ZVPf1aVSMTYk53vOg 8slb+zbrYW719vr1uCcGtil0gXmywGP0BjD3JPeSr8sh X-Google-Smtp-Source: AKy350Z9I8VNHI/2rTFt8qdAoLS5u/dXJyYo6UGRa8rszrfmxZje4BBdckRBqMN1zRQki3cusGc59Q== X-Received: by 2002:a5d:4e8b:0:b0:2f5:20b:e944 with SMTP id e11-20020a5d4e8b000000b002f5020be944mr586206wru.29.1681299823058; Wed, 12 Apr 2023 04:43:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 09/25] target/riscv: Use cpu_ld*_code_mmu for HLVX Date: Wed, 12 Apr 2023 13:43:17 +0200 Message-Id: <20230412114333.118895-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681300113440100005 Content-Type: text/plain; charset="utf-8" Use the new functions to properly check execute permission for the read rather than read permission. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-10-richard.henderson@linaro.org> --- target/riscv/op_helper.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 00bdf77f32..4a0bb5b11a 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -427,18 +427,27 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) helper_hyp_tlb_flush(env); } =20 +/* + * TODO: These implementations are not quite correct. They perform the + * access using execute permission just fine, but the final PMP check + * is supposed to have read permission as well. Without replicating + * a fair fraction of cputlb.c, fixing this requires adding new mmu_idx + * which would imply that exact check in tlb_fill. + */ target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address) { int mmu_idx =3D cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT; + MemOpIdx oi =3D make_memop_idx(MO_TEUW, mmu_idx); =20 - return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); + return cpu_ldw_code_mmu(env, address, oi, GETPC()); } =20 target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address) { int mmu_idx =3D cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT; + MemOpIdx oi =3D make_memop_idx(MO_TEUL, mmu_idx); =20 - return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); + return cpu_ldl_code_mmu(env, address, oi, GETPC()); } =20 #endif /* !CONFIG_USER_ONLY */ --=20 2.34.1 From nobody Fri May 17 04:49:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1681300387; cv=none; d=zohomail.com; s=zohoarc; b=MmO6nWSosMmF6/IIn24/D3jgIaRpKflz/mX2hSzW9Io+7Xhxevtn42cvH5JijkV3vo4U2ii2Wsf/D7ExaCN1c37GhvirOPnuNH57MMuE2VyhNlT7GeqXVCuXS2xSNw7M1OHShe4C/soVpytmjBWD5zi91QWq/ZHhncGRsprKuME= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681300387; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vKKuPzhzhJX3Aqm998ZahUXy3w/Jj2uJkgEst/LLnAU=; b=IIseTrVvl2drQOrCQUuJV8WfG45xu3VtvnIoRSvIV+tc0NFlp+fW664T/BzETw0LQlkkxg0Ae4TprWpJ2ZVGkVICdEjuEuHvYwws+K+71gmkkTwMuncBZ8nDZ9GX9PjLyd+dEJ1lSpnlbwI4vSehWc5alzWkBf73rOgqXY4vEN4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681300387614302.5948281575219; Wed, 12 Apr 2023 04:53:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pmYtX-0005Gc-7s; Wed, 12 Apr 2023 07:44:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pmYtA-0004qi-OL for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:48 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pmYt7-0002Q8-TH for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:48 -0400 Received: by mail-wr1-x42a.google.com with SMTP id l18so10512985wrb.9 for ; Wed, 12 Apr 2023 04:43:45 -0700 (PDT) Received: from stoup.hotel.gast (ip-037-024-010-236.um08.pools.vodafone-ip.de. [37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299824; x=1683891824; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vKKuPzhzhJX3Aqm998ZahUXy3w/Jj2uJkgEst/LLnAU=; b=y01HkMiPV386N+ceVyAi1jdaV/cGlLe+C7Fb3zULUh+oUx5D1UCMuFdIQ+NXw7lRpd wdF8Q4xzRh912tgaoZwVGEQueHmE/+Dw3uLglTPonhIZUHFLeuUmb8/EYf2RBaBIS/Sm DOPKcXCVxkIi8BbOGFt4PzDnAQF2ok9lk6D55HrLEx947IkUy2B5opxUFJhQR/YKeBtY e9OsvjH4VkHKheXY/yFWOOK+mYHR5vetVaw5kkIzMM3yKBcI2uOmL6qWNf9NBVLPZiTi JI5FCNkWTYsXCjSDC6+eZFmVo+6HrjxrpeSr94ooQMEvCuHHQArIu3ofdBNP4VZpd4Rd K/wA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299824; x=1683891824; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vKKuPzhzhJX3Aqm998ZahUXy3w/Jj2uJkgEst/LLnAU=; b=pDaGvlx+qeS3akYKuBNmKuYsjN6dAtl/OBhJb/icu8OhfUaouD2uf9PlbZBP9ZrRNs XKoqGXrygo6NPsO0JEMTiXYUqxWCJo7TJSkXYpTXB/XsCrX8sPwQ8GGExWkqR9g37AfW IWndhk7m6+AAtQBNTRgCpBjpq0Ft7CneZKaEZodV5Rr4OnqwvzKDfxYZVZHJt4/Mx7Re wyyyKEs00mjLBbu1/HydpwN/KVi1gBzeBtlBZrDUIMgepgNe8a1yMHW5aRSuzQJIXrpV 6d5bHsnwIwDnAy//Kb7igT3R+0qBGnf9VO5PxVd33hEMB5ta8zvp/5FgqX5SRdMj6m9F Wclg== X-Gm-Message-State: AAQBX9e95eWsGsO16rvHnWn0e+us1248CG6nCiDDgIk0nv/v3RmUS1e7 cb7xpYeEm5xgj0to9qKVKDj5UJzz/CgqNXsvW7Q0x1cQ X-Google-Smtp-Source: AKy350ZDKwqh3lnla6P6BgzGHAQgFw3+Ei70SEqvpHX75g73KM2BQIpaRyYqgNjJT4qp3BeybtQ2eQ== X-Received: by 2002:adf:ce05:0:b0:2e5:1da2:2a06 with SMTP id p5-20020adfce05000000b002e51da22a06mr4513646wrn.5.1681299824055; Wed, 12 Apr 2023 04:43:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 10/25] target/riscv: Handle HLV, HSV via helpers Date: Wed, 12 Apr 2023 13:43:18 +0200 Message-Id: <20230412114333.118895-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681300388935100003 Content-Type: text/plain; charset="utf-8" Implement these instructions via helpers, in expectation of determining the mmu_idx to use at runtime. This allows the permission check to also be moved out of line, which allows HLSX to be removed from TB_FLAGS. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-11-richard.henderson@linaro.org> --- target/riscv/cpu.h | 6 +- target/riscv/helper.h | 12 ++- target/riscv/cpu_helper.c | 26 ++--- target/riscv/op_helper.c | 99 +++++++++++++++-- target/riscv/translate.c | 2 - target/riscv/insn_trans/trans_rvh.c.inc | 137 ++++++++++-------------- 6 files changed, 169 insertions(+), 113 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6239c99f4c..35cf2e2691 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -639,8 +639,7 @@ FIELD(TB_FLAGS, LMUL, 7, 3) FIELD(TB_FLAGS, SEW, 10, 3) FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) FIELD(TB_FLAGS, VILL, 14, 1) -/* Is a Hypervisor instruction load/store allowed? */ -FIELD(TB_FLAGS, HLSX, 15, 1) +FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ FIELD(TB_FLAGS, XL, 16, 2) /* If PointerMasking should be applied */ @@ -652,8 +651,7 @@ FIELD(TB_FLAGS, VMA, 21, 1) FIELD(TB_FLAGS, ITRIGGER, 22, 1) /* Virtual mode enabled */ FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) -FIELD(TB_FLAGS, VSTART_EQ_ZERO, 24, 1) -FIELD(TB_FLAGS, PRIV, 25, 2) +FIELD(TB_FLAGS, PRIV, 24, 2) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 1880e95c50..98e97810fd 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -123,8 +123,16 @@ DEF_HELPER_1(itrigger_match, void, env) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(hyp_tlb_flush, void, env) DEF_HELPER_1(hyp_gvma_tlb_flush, void, env) -DEF_HELPER_2(hyp_hlvx_hu, tl, env, tl) -DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlv_bu, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlv_hu, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlv_wu, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlv_d, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlvx_hu, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_2(hyp_hlvx_wu, TCG_CALL_NO_WG, tl, env, tl) +DEF_HELPER_FLAGS_3(hyp_hsv_b, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(hyp_hsv_h, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(hyp_hsv_w, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(hyp_hsv_d, TCG_CALL_NO_WG, void, env, tl, tl) #endif =20 /* Vector functions */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 174a77706b..abf275d2c6 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -102,24 +102,16 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_= ulong *pc, fs =3D get_field(env->mstatus, MSTATUS_FS); vs =3D get_field(env->mstatus, MSTATUS_VS); =20 - if (riscv_has_ext(env, RVH)) { - if (env->priv =3D=3D PRV_M || - (env->priv =3D=3D PRV_S && !env->virt_enabled) || - (env->priv =3D=3D PRV_U && !env->virt_enabled && - get_field(env->hstatus, HSTATUS_HU))) { - flags =3D FIELD_DP32(flags, TB_FLAGS, HLSX, 1); - } - - if (env->virt_enabled) { - flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); - /* - * Merge DISABLED and !DIRTY states using MIN. - * We will set both fields when dirtying. - */ - fs =3D MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); - vs =3D MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); - } + if (env->virt_enabled) { + flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); + /* + * Merge DISABLED and !DIRTY states using MIN. + * We will set both fields when dirtying. + */ + fs =3D MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); + vs =3D MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); } + if (cpu->cfg.debug && !icount_enabled()) { flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 4a0bb5b11a..663382785e 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -427,6 +427,91 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) helper_hyp_tlb_flush(env); } =20 +static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra) +{ + if (env->priv =3D=3D PRV_M) { + /* always allowed */ + } else if (env->virt_enabled) { + riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra); + } else if (env->priv =3D=3D PRV_U && !get_field(env->hstatus, HSTATUS_= HU)) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); + } + + return cpu_mmu_index(env, x) | MMU_HYP_ACCESS_BIT; +} + +target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr) +{ + uintptr_t ra =3D GETPC(); + int mmu_idx =3D check_access_hlsv(env, false, ra); + MemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); + + return cpu_ldb_mmu(env, addr, oi, ra); +} + +target_ulong helper_hyp_hlv_hu(CPURISCVState *env, target_ulong addr) +{ + uintptr_t ra =3D GETPC(); + int mmu_idx =3D check_access_hlsv(env, false, ra); + MemOpIdx oi =3D make_memop_idx(MO_TEUW, mmu_idx); + + return cpu_ldw_mmu(env, addr, oi, ra); +} + +target_ulong helper_hyp_hlv_wu(CPURISCVState *env, target_ulong addr) +{ + uintptr_t ra =3D GETPC(); + int mmu_idx =3D check_access_hlsv(env, false, ra); + MemOpIdx oi =3D make_memop_idx(MO_TEUL, mmu_idx); + + return cpu_ldl_mmu(env, addr, oi, ra); +} + +target_ulong helper_hyp_hlv_d(CPURISCVState *env, target_ulong addr) +{ + uintptr_t ra =3D GETPC(); + int mmu_idx =3D check_access_hlsv(env, false, ra); + MemOpIdx oi =3D make_memop_idx(MO_TEUQ, mmu_idx); + + return cpu_ldq_mmu(env, addr, oi, ra); +} + +void helper_hyp_hsv_b(CPURISCVState *env, target_ulong addr, target_ulong = val) +{ + uintptr_t ra =3D GETPC(); + int mmu_idx =3D check_access_hlsv(env, false, ra); + MemOpIdx oi =3D make_memop_idx(MO_UB, mmu_idx); + + cpu_stb_mmu(env, addr, val, oi, ra); +} + +void helper_hyp_hsv_h(CPURISCVState *env, target_ulong addr, target_ulong = val) +{ + uintptr_t ra =3D GETPC(); + int mmu_idx =3D check_access_hlsv(env, false, ra); + MemOpIdx oi =3D make_memop_idx(MO_TEUW, mmu_idx); + + cpu_stw_mmu(env, addr, val, oi, ra); +} + +void helper_hyp_hsv_w(CPURISCVState *env, target_ulong addr, target_ulong = val) +{ + uintptr_t ra =3D GETPC(); + int mmu_idx =3D check_access_hlsv(env, false, ra); + MemOpIdx oi =3D make_memop_idx(MO_TEUL, mmu_idx); + + cpu_stl_mmu(env, addr, val, oi, ra); +} + +void helper_hyp_hsv_d(CPURISCVState *env, target_ulong addr, target_ulong = val) +{ + uintptr_t ra =3D GETPC(); + int mmu_idx =3D check_access_hlsv(env, false, ra); + MemOpIdx oi =3D make_memop_idx(MO_TEUQ, mmu_idx); + + cpu_stq_mmu(env, addr, val, oi, ra); +} + /* * TODO: These implementations are not quite correct. They perform the * access using execute permission just fine, but the final PMP check @@ -434,20 +519,22 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) * a fair fraction of cputlb.c, fixing this requires adding new mmu_idx * which would imply that exact check in tlb_fill. */ -target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address) +target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong addr) { - int mmu_idx =3D cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT; + uintptr_t ra =3D GETPC(); + int mmu_idx =3D check_access_hlsv(env, true, ra); MemOpIdx oi =3D make_memop_idx(MO_TEUW, mmu_idx); =20 - return cpu_ldw_code_mmu(env, address, oi, GETPC()); + return cpu_ldw_code_mmu(env, addr, oi, GETPC()); } =20 -target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address) +target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong addr) { - int mmu_idx =3D cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT; + uintptr_t ra =3D GETPC(); + int mmu_idx =3D check_access_hlsv(env, true, ra); MemOpIdx oi =3D make_memop_idx(MO_TEUL, mmu_idx); =20 - return cpu_ldl_code_mmu(env, address, oi, GETPC()); + return cpu_ldl_code_mmu(env, addr, oi, ra); } =20 #endif /* !CONFIG_USER_ONLY */ diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6d59348f0c..928da0d3f0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -80,7 +80,6 @@ typedef struct DisasContext { bool virt_inst_excp; bool virt_enabled; const RISCVCPUConfig *cfg_ptr; - bool hlsx; /* vector extension */ bool vill; /* @@ -1163,7 +1162,6 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->misa_ext =3D env->misa_ext; ctx->frm =3D -1; /* unknown rounding mode */ ctx->cfg_ptr =3D &(cpu->cfg); - ctx->hlsx =3D FIELD_EX32(tb_flags, TB_FLAGS, HLSX); ctx->vill =3D FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew =3D FIELD_EX32(tb_flags, TB_FLAGS, SEW); ctx->lmul =3D sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index ae98b45e5e..3e9322130f 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -16,158 +16,131 @@ * this program. If not, see . */ =20 -#ifndef CONFIG_USER_ONLY -static bool check_access(DisasContext *ctx) -{ - if (!ctx->hlsx) { - tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, - offsetof(CPURISCVState, bins)); - if (ctx->virt_enabled) { - generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); - } else { - generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); - } - return false; - } - return true; -} -#endif - -static bool do_hlv(DisasContext *ctx, arg_r2 *a, MemOp mop) -{ #ifdef CONFIG_USER_ONLY - return false; +#define do_hlv(ctx, a, func) false +#define do_hsv(ctx, a, func) false #else - decode_save_opc(ctx); - if (check_access(ctx)) { - TCGv dest =3D dest_gpr(ctx, a->rd); - TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - int mem_idx =3D ctx->mem_idx | MMU_HYP_ACCESS_BIT; - tcg_gen_qemu_ld_tl(dest, addr, mem_idx, mop); - gen_set_gpr(ctx, a->rd, dest); - } - return true; -#endif +static void gen_helper_hyp_hlv_b(TCGv r, TCGv_env e, TCGv a) +{ + gen_helper_hyp_hlv_bu(r, e, a); + tcg_gen_ext8s_tl(r, r); } =20 +static void gen_helper_hyp_hlv_h(TCGv r, TCGv_env e, TCGv a) +{ + gen_helper_hyp_hlv_hu(r, e, a); + tcg_gen_ext16s_tl(r, r); +} + +static void gen_helper_hyp_hlv_w(TCGv r, TCGv_env e, TCGv a) +{ + gen_helper_hyp_hlv_wu(r, e, a); + tcg_gen_ext32s_tl(r, r); +} + +static bool do_hlv(DisasContext *ctx, arg_r2 *a, + void (*func)(TCGv, TCGv_env, TCGv)) +{ + TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + + decode_save_opc(ctx); + func(dest, cpu_env, addr); + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +static bool do_hsv(DisasContext *ctx, arg_r2_s *a, + void (*func)(TCGv_env, TCGv, TCGv)) +{ + TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); + TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); + + decode_save_opc(ctx); + func(cpu_env, addr, data); + return true; +} +#endif /* CONFIG_USER_ONLY */ + static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a) { REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_SB); + return do_hlv(ctx, a, gen_helper_hyp_hlv_b); } =20 static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a) { REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_TESW); + return do_hlv(ctx, a, gen_helper_hyp_hlv_h); } =20 static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a) { REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_TESL); + return do_hlv(ctx, a, gen_helper_hyp_hlv_w); } =20 static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a) { REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_UB); + return do_hlv(ctx, a, gen_helper_hyp_hlv_bu); } =20 static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a) { REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_TEUW); -} - -static bool do_hsv(DisasContext *ctx, arg_r2_s *a, MemOp mop) -{ -#ifdef CONFIG_USER_ONLY - return false; -#else - decode_save_opc(ctx); - if (check_access(ctx)) { - TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); - int mem_idx =3D ctx->mem_idx | MMU_HYP_ACCESS_BIT; - tcg_gen_qemu_st_tl(data, addr, mem_idx, mop); - } - return true; -#endif + return do_hlv(ctx, a, gen_helper_hyp_hlv_hu); } =20 static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a) { REQUIRE_EXT(ctx, RVH); - return do_hsv(ctx, a, MO_SB); + return do_hsv(ctx, a, gen_helper_hyp_hsv_b); } =20 static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a) { REQUIRE_EXT(ctx, RVH); - return do_hsv(ctx, a, MO_TESW); + return do_hsv(ctx, a, gen_helper_hyp_hsv_h); } =20 static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a) { REQUIRE_EXT(ctx, RVH); - return do_hsv(ctx, a, MO_TESL); + return do_hsv(ctx, a, gen_helper_hyp_hsv_w); } =20 static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_TEUL); + return do_hlv(ctx, a, gen_helper_hyp_hlv_wu); } =20 static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); - return do_hlv(ctx, a, MO_TEUQ); + return do_hlv(ctx, a, gen_helper_hyp_hlv_d); } =20 static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) { REQUIRE_64BIT(ctx); REQUIRE_EXT(ctx, RVH); - return do_hsv(ctx, a, MO_TEUQ); + return do_hsv(ctx, a, gen_helper_hyp_hsv_d); } =20 -#ifndef CONFIG_USER_ONLY -static bool do_hlvx(DisasContext *ctx, arg_r2 *a, - void (*func)(TCGv, TCGv_env, TCGv)) -{ - decode_save_opc(ctx); - if (check_access(ctx)) { - TCGv dest =3D dest_gpr(ctx, a->rd); - TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); - func(dest, cpu_env, addr); - gen_set_gpr(ctx, a->rd, dest); - } - return true; -} -#endif - static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a) { REQUIRE_EXT(ctx, RVH); -#ifndef CONFIG_USER_ONLY - return do_hlvx(ctx, a, gen_helper_hyp_hlvx_hu); -#else - return false; -#endif + return do_hlv(ctx, a, gen_helper_hyp_hlvx_hu); } =20 static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a) { REQUIRE_EXT(ctx, RVH); -#ifndef CONFIG_USER_ONLY - return do_hlvx(ctx, a, gen_helper_hyp_hlvx_wu); -#else - return false; -#endif + return do_hlv(ctx, a, gen_helper_hyp_hlvx_wu); } =20 static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) --=20 2.34.1 From nobody Fri May 17 04:49:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299825; x=1683891825; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d5xHxmaEOgXeHn2A8bHUUouqfxAhC2pmFZSPjP/T4RA=; b=iUFz6FMNJKOwmKWjet0a5BDbOC5RP1/hvbzKia/CJNC51T0WUDnyNUtoW2yCKYdG8O m9+SPinDpvdG9KU4qwEsJXozVJJF3CB2pLxyf52CXZfL6P6v0TELHRmsAb6YdGi8LIxY EMi2CzNH8ZtBzDKlvukANZENiWe1qZ3OosWsTwKBlU3R+I7gkPs/kgP394NMeCHNluCQ JTuW+gLChrF134ow9A0WVK33F0rlXQYMyDXJ7VuBLjaF1d8y2YHUmGK8M+3w5OzikwW8 5bms+kTZrBUl2Q5joojdDXJs1Q0C0k+KF9UavbY1sC/MhaoYAD6PGOsOqrNibK8kymKF 0M5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299825; x=1683891825; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d5xHxmaEOgXeHn2A8bHUUouqfxAhC2pmFZSPjP/T4RA=; b=I7D04VYVkLZruxBPAWDi2/nuHlX8XaUKQA8Yzds7wDTLd3MzuFV+13zNVSJSyc8j4Y +FsEOvre+u54apjpK5c8dO1SyT0Jj4Q8ODRt7Y4Va5ypZKxkrXTMuZBIUwJr9tCiPtTH GU/o1P8X5TEb6IrdTn6EaqVrWlveXqSm2uXrqQfJimOg4cGbGON2SFoIe/uAlmAKKTqD MKDy+cN3C7hFpLUqpNwpPGSHPS/mO2JZ4CMxF0Sv4ozB5tI1a2b7IoieCbSxso3U4GO5 /FnFg7W3ii95fopEaSrn0PU0S36Np1w6x8h/wISWtqokLNt/bYOFjE9YchRsPUw7dLe7 G7/Q== X-Gm-Message-State: AAQBX9e7p0lGYAOA4Bq4t354Bspuv8EWRVk2txw2Yp9/d0R9m1vUw+ml sI2ClekNR5oCY+KKcjMPdcwhXhCcJOAtaut0qOy7VdNV X-Google-Smtp-Source: AKy350bLBhl9BslDvEm2ceQ7VV35OyNiP7h9WSARfXDPMzm2Xqp/2OwFdygK0G62N60tAWZ+/pRrJQ== X-Received: by 2002:adf:e34c:0:b0:2e5:a86c:fe74 with SMTP id n12-20020adfe34c000000b002e5a86cfe74mr8403377wrj.51.1681299824828; Wed, 12 Apr 2023 04:43:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 11/25] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT Date: Wed, 12 Apr 2023 13:43:19 +0200 Message-Id: <20230412114333.118895-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681300009137100005 Content-Type: text/plain; charset="utf-8" We will enable more uses of this bit in the future. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-12-richard.henderson@linaro.org> --- target/riscv/internals.h | 6 ++++-- target/riscv/cpu_helper.c | 2 +- target/riscv/op_helper.c | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index b55152a7dc..7b63c0f1b6 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -27,13 +27,15 @@ * - S 0b001 * - S+SUM 0b010 * - M 0b011 - * - HLV/HLVX/HSV adds 0b100 + * - U+2STAGE 0b100 + * - S+2STAGE 0b101 + * - S+SUM+2STAGE 0b110 */ #define MMUIdx_U 0 #define MMUIdx_S 1 #define MMUIdx_S_SUM 2 #define MMUIdx_M 3 -#define MMU_HYP_ACCESS_BIT (1 << 2) +#define MMU_2STAGE_BIT (1 << 2) =20 /* share data between vector helpers and decode code */ FIELD(VDATA, VM, 0, 1) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index abf275d2c6..291a1acbf7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -593,7 +593,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, boo= l enable) =20 bool riscv_cpu_two_stage_lookup(int mmu_idx) { - return mmu_idx & MMU_HYP_ACCESS_BIT; + return mmu_idx & MMU_2STAGE_BIT; } =20 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 663382785e..a5de3daee7 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -437,7 +437,7 @@ static int check_access_hlsv(CPURISCVState *env, bool x= , uintptr_t ra) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } =20 - return cpu_mmu_index(env, x) | MMU_HYP_ACCESS_BIT; + return cpu_mmu_index(env, x) | MMU_2STAGE_BIT; } =20 target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr) --=20 2.34.1 From nobody Fri May 17 04:49:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1681299858; cv=none; d=zohomail.com; s=zohoarc; b=lLqktF6I9KUkFk0Pn6i9/M7G07NtwfE95oMSN9ltVhQapAj/KFJLJPHXqKB+d4cf3/hWMiQ1IVL+Pyd9STtb8kXaf+bNREU74DvxA05Eqnp0rpRywTU345LXKEAQQR/lYcS7WgDHR4s50sZEhxdsBQvmxQEFLP4T/o5ynherM4Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681299858; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3Lv2amYuxnL/rjHsnpYSrIfjZprlyKOd0sUgv/cdui0=; b=S1wWFRfVfJaBAq/jnpuUppKvH5KieLFvygcPolsNjf2EdNT6Soeeyb78d24fZJeG3D4o08kNBy4KJmXsd7xOkfwXOs/5NuTngsJLJHboy81yv4IML7abnLR44UcsR/nYDLUHpDDiknMN4SyqUQGabrm16kz9pHUiOYRnRSVuxoM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681299858908874.8010035913628; Wed, 12 Apr 2023 04:44:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pmYtQ-0004z2-JA; Wed, 12 Apr 2023 07:44:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pmYtB-0004s0-PI for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:50 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pmYt9-0002NQ-72 for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:49 -0400 Received: by mail-wr1-x430.google.com with SMTP id e7so493967wrc.12 for ; Wed, 12 Apr 2023 04:43:45 -0700 (PDT) Received: from stoup.hotel.gast (ip-037-024-010-236.um08.pools.vodafone-ip.de. [37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299825; x=1683891825; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3Lv2amYuxnL/rjHsnpYSrIfjZprlyKOd0sUgv/cdui0=; b=dxAvSN0Za8XtSpewBHotI+liYkI3R0XrGZHy6SfbuCEyIm+MtuFxfbEFSzIPpEJAdS fisDH/mrWbVKN0sPmo21Uj+sNykOQQEIsaJt+/3JqfN2mDEIEuU4OFGaTGnoamkefCxj 6WvLu1enXEJvVTVFvl2YD2p/u3jHl8RZ3xLOpWUJV9cDapiclgm5Kbd2hZZq2H3byg0D NR4ED99Azidh5iIcL8mFWah1sux7Vc6gsJmIA088+/ENagtw3NOl8gVMpmskUuHdAbWo SH7ASFGp4zmfIeGVXUTgOm2eKloNo0G7Qgz2JmRFvO7pmRQvLFgXywDDVRC4bd4iZ39T 7pdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299825; x=1683891825; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3Lv2amYuxnL/rjHsnpYSrIfjZprlyKOd0sUgv/cdui0=; b=RgOIzyYG29A7j0MCo8oS4+tKhGIFau/ufaLKzIgP+1udCrjInxq9yW6QvsuPZJHT2K blq0Af2DkLe9dGYCU0PnRNj2Hcnv1D0MwX4qKVcXj51akNhDEKmg11DpczqqJJXjq1Na n87UUnuB7GLjQml2noGrHW9zu5nWJQgMCSDsgP3jUL4OnE7qmzYLPYuqTnrcNvyJQAnD R1o4xNfDkDyyeeMZvdnZ7CuEA4zKKGK2kOjaW3x63xDSKwYJkM/OiESD4FACKi1YsVgY amDhMA3hMh0SjdTcZV4pDapp++bWKSIX0wjsV+HNqLDEQ+9NsxOb3Vr3Csc2w6EF7wVy S8gw== X-Gm-Message-State: AAQBX9cim2VgDqP24IWEVInasWRTrSh3UVxu7mWsgsnhAZx5IAEllVG6 IwpvJDxvZ/C3hYCUcCUW93WZVOIpEouOIdlDWPylwLnV X-Google-Smtp-Source: AKy350bSlVpqpYgiKK0h4iTEx4tEv+WydjbMlJhSii4QBrwUS0TqB1rs+7le7vC9RiUctWb0rMnZMQ== X-Received: by 2002:adf:f2c5:0:b0:2d1:70cc:66e0 with SMTP id d5-20020adff2c5000000b002d170cc66e0mr1541381wrp.44.1681299825582; Wed, 12 Apr 2023 04:43:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 12/25] target/riscv: Introduce mmuidx_sum Date: Wed, 12 Apr 2023 13:43:20 +0200 Message-Id: <20230412114333.118895-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681299860640100003 Content-Type: text/plain; charset="utf-8" In get_physical_address, we should use the setting passed via mmu_idx rather than checking env->mstatus directly. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-13-richard.henderson@linaro.org> --- target/riscv/internals.h | 5 +++++ target/riscv/cpu_helper.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 7b63c0f1b6..0b61f337dd 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -37,6 +37,11 @@ #define MMUIdx_M 3 #define MMU_2STAGE_BIT (1 << 2) =20 +static inline bool mmuidx_sum(int mmu_idx) +{ + return (mmu_idx & 3) =3D=3D MMUIdx_S_SUM; +} + /* share data between vector helpers and decode code */ FIELD(VDATA, VM, 0, 1) FIELD(VDATA, LMUL, 1, 3) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 291a1acbf7..29ee9b1b42 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -842,7 +842,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, widened =3D 2; } /* status.SUM will be ignored if execute on background */ - sum =3D get_field(env->mstatus, MSTATUS_SUM) || use_background || is_d= ebug; + sum =3D mmuidx_sum(mmu_idx) || use_background || is_debug; switch (vm) { case VM_1_10_SV32: levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; --=20 2.34.1 From nobody Fri May 17 04:49:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1681299898; cv=none; d=zohomail.com; s=zohoarc; b=JcVrlOJ0Wsiz7k3xxfqItiM9XXpxl14JiUOM4aHsZvy3NlH3BTiEb1F3+bxIRiH+YulB3/lpi0K0y7aT8fXrdVPI/M9JautbbrvyAAYJaHM0uDW4jMV9RyeSmGITzPDOnerrxAlN7Xxlcp+YuQwHkdj4IRJtsLRw1rtEiuhPe+E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681299898; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ctqzVVZjJ45Im/ugL7sow9fNEblGak+zrzESoiQbQPE=; b=HVD9dezZtawDX59DgPFvLeLB47bWjsp5YyWlvadwd4Rr8TueDHYpjR+GT0C/K+EdYeuCfljID0TNg1sPXXRT9wruaBbS/FaA4sl61aLX7a89O+6+CX4I5t2zs8T/Eb51xpKjsNyz/UwOB/mr1+BgE5/vY+VhhMseS/VLZwi7nuE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681299898162600.1436616160662; Wed, 12 Apr 2023 04:44:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pmYtb-0005VB-Kj; Wed, 12 Apr 2023 07:44:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pmYtC-0004sW-6x for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:50 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pmYtA-0002RC-Fq for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:49 -0400 Received: by mail-wr1-x434.google.com with SMTP id g5so13963307wrb.5 for ; Wed, 12 Apr 2023 04:43:47 -0700 (PDT) Received: from stoup.hotel.gast (ip-037-024-010-236.um08.pools.vodafone-ip.de. [37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299826; x=1683891826; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ctqzVVZjJ45Im/ugL7sow9fNEblGak+zrzESoiQbQPE=; b=xUJ/UTUS1t2FeTQIcLLY7FY8FvnT0PrL2a2JNjJB4DJztR2lK/dqGE+j+aoTJ16ncB dMfavDP08SUjeKTCxh6HejLswjK8pdHCg1RQ3LDkNPoKcYNk5W8Q9VOliTQ7DqxzTZYB jOVkSZQcAjNV4Vpxg/cbEPQyhrW2SYWX7nzzBmlDSLkLMB5xjxAdilOswW8EIIiKLxpw +iXDtReQ/AC2WUAnJXpXM0hkuL0hScHyMVySKO3qxeh8hYNNGvUIOR4I3ssNU9vI5qJB tRGtM6Cw3gpfC7ZM/Ikl4PbIL7d41fPJr9Uvns5cqKNRXpaeFzvvP68KZnP76kntXzSH r8AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299826; x=1683891826; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ctqzVVZjJ45Im/ugL7sow9fNEblGak+zrzESoiQbQPE=; b=5xVj83psEJYfgJJqtn1QAU7ZIAYKo5XAcVWCx9HXr0E7QmQ0LqXBNtRmXn4Ox6E/kQ 9LkgS9cxovPFfxihL7rk5PGYyswAgeWv8pD0NaxGvyHjFBss9CYFWdpOh5P6kVW/KJLe 2D6xms1av1Am9P+eXhHzYQcR1VE9c8x7pSL42B4wpjGQMcc2543G3nsGxoG8DhHg8Jse 1Vn1yC0qDZZqkIsCm2fXQbnQJLJp0ADZQs7+/62upeK5thUvzCFmIaMNfGytMsZ1GdxK y2fYyU43Rsez5DVSUrMuZJGzqnngfwN1INFeROSKJfcjibhH2BlAKi8ftSkO/HoJk8Iy Pqew== X-Gm-Message-State: AAQBX9fNwce1Ed6+4iSDHv4JTX0wOrpL4uElm+lYx4e6GcGzQTn/OcQq LMePvHXLSP6fjKRR/sVsjVUUptzo02pB5emxWWjP9hqA X-Google-Smtp-Source: AKy350Zv2UeMEO2ESCuvf8xzRPh0ExPADi2rrt8wm4FYxQTWUVHkFJ9H98dY19TCRbIZrFGafy08cg== X-Received: by 2002:a5d:4b4c:0:b0:2f2:af44:60e7 with SMTP id w12-20020a5d4b4c000000b002f2af4460e7mr1598229wrs.68.1681299826504; Wed, 12 Apr 2023 04:43:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 13/25] target/riscv: Introduce mmuidx_priv Date: Wed, 12 Apr 2023 13:43:21 +0200 Message-Id: <20230412114333.118895-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681299899609100003 Content-Type: text/plain; charset="utf-8" Use the priv level encoded into the mmu_idx, rather than starting from env->priv. We have already checked MPRV+MPP in riscv_cpu_mmu_index -- no need to repeat that. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-14-richard.henderson@linaro.org> --- target/riscv/internals.h | 9 +++++++++ target/riscv/cpu_helper.c | 6 +----- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 0b61f337dd..4aa1cb409f 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -37,6 +37,15 @@ #define MMUIdx_M 3 #define MMU_2STAGE_BIT (1 << 2) =20 +static inline int mmuidx_priv(int mmu_idx) +{ + int ret =3D mmu_idx & 3; + if (ret =3D=3D MMUIdx_S_SUM) { + ret =3D PRV_S; + } + return ret; +} + static inline bool mmuidx_sum(int mmu_idx) { return (mmu_idx & 3) =3D=3D MMUIdx_S_SUM; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 29ee9b1b42..57bb19c76e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -758,7 +758,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, */ MemTxResult res; MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; - int mode =3D env->priv; + int mode =3D mmuidx_priv(mmu_idx); bool use_background =3D false; hwaddr ppn; int napot_bits =3D 0; @@ -781,10 +781,6 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, */ if (riscv_cpu_two_stage_lookup(mmu_idx)) { mode =3D get_field(env->hstatus, HSTATUS_SPVP); - } else if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { - if (get_field(env->mstatus, MSTATUS_MPRV)) { - mode =3D get_field(env->mstatus, MSTATUS_MPP); - } } =20 if (first_stage =3D=3D false) { --=20 2.34.1 From nobody Fri May 17 04:49:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1681299867; cv=none; d=zohomail.com; s=zohoarc; b=np5oak5jzqXQg8+f668rUCqnJYtl1q3cwvpXygphfgdavS5ingiSjCQoOieuuwFL/F22FfUKI2rdAJ4g17LDenTeSdJf6VR2aM99R1eTe6Iki35lqLgjByIl9QMtX3Hinp8qob0Ls5CTsGhu4siFEdjLyMseeqcOxWTRMMvMDOA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681299867; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=a4Zsigsmxtifc1mTfNj4Cc3gPaSn9A3+wFQ54BAyMXU=; b=l/Mpvp1L8u2zGBzJ4P3I23a/c+pYsKwH8x/kRqF4lX46mtDi6HE9LJGkEqJWc3BJcmHbZNov+ZjngeZd7FummsqsQKXi1qshTqPBt5J4tuAS4k+15EPDcwo82WG6M4YgneyueWj4X30wlrrKM6j6UP9zMTLEKXw5io3AQcvjcYI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681299867927701.7772166057548; Wed, 12 Apr 2023 04:44:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pmYtc-0005cR-Na; Wed, 12 Apr 2023 07:44:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pmYtD-0004v0-3V for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:51 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pmYtB-0002Rd-0g for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:50 -0400 Received: by mail-wr1-x431.google.com with SMTP id v6so10561142wrv.8 for ; Wed, 12 Apr 2023 04:43:48 -0700 (PDT) Received: from stoup.hotel.gast (ip-037-024-010-236.um08.pools.vodafone-ip.de. [37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299827; x=1683891827; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a4Zsigsmxtifc1mTfNj4Cc3gPaSn9A3+wFQ54BAyMXU=; b=U4A9LEu4gse6uImkH9lAKhvjWvKPgcFYdtbvkjFBqOpydp4ZzGnI/GufNqLCK53CvA zJPP1FIH36U63Liy1dzWhD1yEcEOoc1nzOzhMWyoON97TWmmE/guenzIv+n5nysIRiIh +VQPhTv0lF711vRdCbPCkNnzo3vf3LPOLhTNjW+ht+y/g9T3eRvnNrfUbH9Af2bKBgmi hDmmkg6otQl5s9FPPNBXQ7hX9Fqv/v5eo1x9PxCWhrZ/3K8WHg47sfuH6RrEs+Jomhx6 jv8tJDzW9YDtKEV26QebxKyz9yz7QmCw086D6pjsn8SrPsZsMksEA3P6B6ppTihPji1h tlEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299827; x=1683891827; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a4Zsigsmxtifc1mTfNj4Cc3gPaSn9A3+wFQ54BAyMXU=; b=6sVPR+C/5Q+ABx2dgLkcPBJxpI27O+fARccWQUZQfxtidEpvzYlWpRBr8r2fmSQ30+ xtxoKXqR0GWCOnEe9b80dpNVTMBw7bv21sIl0kU+5SVrXk9WkJg6JdMS3Y6lJwzR9438 jWgsg05jRotfMdrZV7YGYZCuk4LZsjX48lT7GR6veCgte6YGwlaoUsxe65Ug6yhIzmt7 TV7TLxFosM7rM1hatoOXTowJgEoU+a5N8OA0LMBGUW0tCAun/zTdzPgzTddaYrz9iKpu aiZUoxg3nYn3AfLqsy7irU08Yxuu6yrgHSZA4kIiMLnA4KvwwgMdHaY2pB6yUC3vQ4SY GO7Q== X-Gm-Message-State: AAQBX9eRVNrkPu6+uQL1PBmnURdwJcx6vNRsdhZoMoLM3euRYT6ho+rr oYauyszg/R+HH3BMm6GtnkJqVGJLKr5UlpAjezQqa10N X-Google-Smtp-Source: AKy350bwARQ6ZiR+R5ksTsBGQFYoZSKeyLz0exk5D04VqeOTW7zxEl+ZQ1oVdE/RW+lz+ragiZrGKQ== X-Received: by 2002:adf:f1cc:0:b0:2f0:23bf:da7d with SMTP id z12-20020adff1cc000000b002f023bfda7dmr8837713wro.29.1681299827355; Wed, 12 Apr 2023 04:43:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 14/25] target/riscv: Introduce mmuidx_2stage Date: Wed, 12 Apr 2023 13:43:22 +0200 Message-Id: <20230412114333.118895-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681299868257100001 Content-Type: text/plain; charset="utf-8" Move and rename riscv_cpu_two_stage_lookup, to match the other mmuidx_* functions. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-15-richard.henderson@linaro.org> --- target/riscv/cpu.h | 1 - target/riscv/internals.h | 5 +++++ target/riscv/cpu_helper.c | 20 ++++++-------------- 3 files changed, 11 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 35cf2e2691..d1f888a790 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -581,7 +581,6 @@ target_ulong riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); -bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 4aa1cb409f..b5f823c7ec 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -51,6 +51,11 @@ static inline bool mmuidx_sum(int mmu_idx) return (mmu_idx & 3) =3D=3D MMUIdx_S_SUM; } =20 +static inline bool mmuidx_2stage(int mmu_idx) +{ + return mmu_idx & MMU_2STAGE_BIT; +} + /* share data between vector helpers and decode code */ FIELD(VDATA, VM, 0, 1) FIELD(VDATA, LMUL, 1, 3) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 57bb19c76e..9dfd1d739b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -591,11 +591,6 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bo= ol enable) } } =20 -bool riscv_cpu_two_stage_lookup(int mmu_idx) -{ - return mmu_idx & MMU_2STAGE_BIT; -} - int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) { CPURISCVState *env =3D &cpu->env; @@ -779,7 +774,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, * MPRV does not affect the virtual-machine load/store * instructions, HLV, HLVX, and HSV. */ - if (riscv_cpu_two_stage_lookup(mmu_idx)) { + if (mmuidx_2stage(mmu_idx)) { mode =3D get_field(env->hstatus, HSTATUS_SPVP); } =20 @@ -1175,8 +1170,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hw= addr physaddr, } =20 env->badaddr =3D addr; - env->two_stage_lookup =3D env->virt_enabled || - riscv_cpu_two_stage_lookup(mmu_idx); + env->two_stage_lookup =3D env->virt_enabled || mmuidx_2stage(mmu_idx); env->two_stage_indirect_lookup =3D false; cpu_loop_exit_restore(cs, retaddr); } @@ -1201,8 +1195,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, g_assert_not_reached(); } env->badaddr =3D addr; - env->two_stage_lookup =3D env->virt_enabled || - riscv_cpu_two_stage_lookup(mmu_idx); + env->two_stage_lookup =3D env->virt_enabled || mmuidx_2stage(mmu_idx); env->two_stage_indirect_lookup =3D false; cpu_loop_exit_restore(cs, retaddr); } @@ -1256,7 +1249,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, * MPRV does not affect the virtual-machine load/store * instructions, HLV, HLVX, and HSV. */ - if (riscv_cpu_two_stage_lookup(mmu_idx)) { + if (mmuidx_2stage(mmu_idx)) { mode =3D get_field(env->hstatus, HSTATUS_SPVP); } else if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH && get_field(env->mstatus, MSTATUS_MPRV)) { @@ -1268,7 +1261,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, =20 pmu_tlb_fill_incr_ctr(cpu, access_type); if (env->virt_enabled || - ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && + ((mmuidx_2stage(mmu_idx) || two_stage_lookup) && access_type !=3D MMU_INST_FETCH)) { /* Two stage lookup */ ret =3D get_physical_address(env, &pa, &prot, address, @@ -1366,8 +1359,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, } else { raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error, - env->virt_enabled || - riscv_cpu_two_stage_lookup(mmu_idx), + env->virt_enabled || mmuidx_2stage(mmu_idx), two_stage_indirect_error); cpu_loop_exit_restore(cs, retaddr); } --=20 2.34.1 From nobody Fri May 17 04:49:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1681300387; cv=none; d=zohomail.com; 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[37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299828; x=1683891828; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1b/kBvvVthJX/VbKnXsWeX6FiZxYMKF2JWi4jeCwEjI=; b=jfp6IJ9b6SfvDChBPWboAtWgpFxpKJNIvu7lhf0kVA7Eu8IQo2XlTqKRpz0rt/paXg 4w6PfgYIt946339LuxW6JFkQxE/OaKO2mhL+B8VSXySbn7HywzBJpf90AU7vxSXfnkTV h+hNIxtWLpTcDL5tZLvJZm8e5039skLZYRe1Q49lDVzEXgmapyE3dJh6IuCpU/bswRHr HJmr7Y7mi5rHCefuGETh0/fLqzwYFcvR0atM7FqWAZ8WPNAWKSjEorGFD1tI8jLsmh/d pFlizOwI5NWUBKjoF/hLYZLnoAB8LGxECo+fRmMOfs+ttNQguj1yignVOd0pawzOa3h4 jm1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299828; x=1683891828; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1b/kBvvVthJX/VbKnXsWeX6FiZxYMKF2JWi4jeCwEjI=; b=Z2+xApHnFaZdfMrfjrZN2ipWh4MlNOcJec8oLTaMW21/tZPKUb3OWoTPL0rWjJxh9I 4mlYI3Ex9o7W+ZR/hZ2wvgi4YOismWp3GiZl7term8f/45v9MNBnUUIuK7Ry+UMcCjI0 JOyrLVpmsVZFWOmt/2+HK3m0kBmBX2DX8OK3JdwOucBW7uPzsC4P+cfPlvPMLsKZP+hh 1TRSo8X3K3NFzZ0cyCqA+BkzZfOd19ascAFSC6/QX2s6N9SDA7Ig3rIyXj2SuISAXYWG JqM20klOOnkpNWJ25OW/QoYtZq4VH92jHBjgZG5xxFInZDiX3iUSp4/bp54/qHNSTalQ duAA== X-Gm-Message-State: AAQBX9fEUQCd9ZHF3w/pPoB4EqUZjC0iO0IdHSCLyyqCvf35bJW0uVuN Sr21feyk0uqPSfoUBQo9lWR7ygmxvMnHMpZNcSKae+NP X-Google-Smtp-Source: AKy350Zklz/sR+JJFQpTGIjMKnrtVHh3IcxpkkuU7U+heZ+X0HG7fk3a48HRreXt5LQJw7RVQy8m6g== X-Received: by 2002:a5d:540e:0:b0:2f0:27cc:1e7 with SMTP id g14-20020a5d540e000000b002f027cc01e7mr4409096wrv.9.1681299828407; Wed, 12 Apr 2023 04:43:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 15/25] target/riscv: Move hstatus.spvp check to check_access_hlsv Date: Wed, 12 Apr 2023 13:43:23 +0200 Message-Id: <20230412114333.118895-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681300388933100001 Content-Type: text/plain; charset="utf-8" The current cpu_mmu_index value is really irrelevant to the HLV/HSV lookup. Provide the correct priv level directly. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-16-richard.henderson@linaro.org> --- target/riscv/cpu_helper.c | 10 +--------- target/riscv/op_helper.c | 2 +- 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9dfd1d739b..ccba3c45e7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -770,14 +770,6 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, use_background =3D true; } =20 - /* - * MPRV does not affect the virtual-machine load/store - * instructions, HLV, HLVX, and HSV. - */ - if (mmuidx_2stage(mmu_idx)) { - mode =3D get_field(env->hstatus, HSTATUS_SPVP); - } - if (first_stage =3D=3D false) { /* * We are in stage 2 translation, this is similar to stage 1. @@ -1250,7 +1242,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, * instructions, HLV, HLVX, and HSV. */ if (mmuidx_2stage(mmu_idx)) { - mode =3D get_field(env->hstatus, HSTATUS_SPVP); + ; } else if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH && get_field(env->mstatus, MSTATUS_MPRV)) { mode =3D get_field(env->mstatus, MSTATUS_MPP); diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index a5de3daee7..49c19d971d 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -437,7 +437,7 @@ static int check_access_hlsv(CPURISCVState *env, bool x= , uintptr_t ra) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } =20 - return cpu_mmu_index(env, x) | MMU_2STAGE_BIT; + return get_field(env->hstatus, HSTATUS_SPVP) | MMU_2STAGE_BIT; } =20 target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr) --=20 2.34.1 From nobody Fri May 17 04:49:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1681300051; cv=none; d=zohomail.com; s=zohoarc; b=A4wbmreUjvjRkv5gwV8EQB6qA6dAMWzpw4ODfTC163OHL7bX+ybyo3lf8Ym7I0Qhja6h11J5SRRK6u19NR9Y/JvFhGlc0xjSlcewmVnARYfqSG6q08r+sDKh7tQzl1yfg27RFWpAnrpjuGNfuikEXCFLTJrvC5PA8YMCdZw8zkc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681300051; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fc7ZqB0501n3cQfOjNTftlZU8unqltEwwtjDsL6xclU=; b=ThLI1STvDeBb1BVXxhULwSxdlx9C/RtKKiZl5z4Wo2pRQnQsVFU5RM4kcRZl8nb6rxg8AOUWbaSvJb2Ps52h+lc0X3NJN4L6MCdtKRbsilCvQs8qA6ibNGNXGHWBxSXW9wRtDI+nuibp8BQzsBcej5H++Ttyi7CGXzHXKmdqeqs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681300051430518.4712599184788; Wed, 12 Apr 2023 04:47:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pmYti-0006Lz-2N; Wed, 12 Apr 2023 07:44:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pmYtD-0004vj-U0 for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:53 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pmYtC-0002Or-3O for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:51 -0400 Received: by mail-wr1-x429.google.com with SMTP id e7so494153wrc.12 for ; Wed, 12 Apr 2023 04:43:49 -0700 (PDT) Received: from stoup.hotel.gast (ip-037-024-010-236.um08.pools.vodafone-ip.de. [37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299829; x=1683891829; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fc7ZqB0501n3cQfOjNTftlZU8unqltEwwtjDsL6xclU=; b=CnCsJy3yNooYT9AkA2kepFNlR146UK7RsPYjW4Rz720wOJJQHAcHjpBfjtz/3IbP0y Bq5IE097CecxHpxRMiYhyJVHcIz2dzaMfhaCqFg+1XFQXqBD8D6F6OHjGjaNPvLQ7eEN 07WEHo5Wq3e0lrsbQm+A4ysa/17C+klJX2TD7qksLzpn0uM4ustSpSMJV6QwZbeklX4U 7mQhrHl42vugLPgh1YHMDedXSJ/t105dHT+qpnhsYwRGB+9vgPQ665tCQWNFiEGgsa9S UtEA5PznDPPFOmM3xUq8oyKEQQ+wJBJ6PnIjvt775k6r4DayWg1Z/gXLjt9jwFIMwETY Gwww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299829; x=1683891829; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fc7ZqB0501n3cQfOjNTftlZU8unqltEwwtjDsL6xclU=; b=SRTfyM3Gjh4Ixu5mjUmrbON/NPFfCKPqHn6ab79ebldAlEAH34BlQ8mg4v0P7mjg5I MgBfln7RdXfOa6b8cCE+Yj8oUWK5oBCqXr+MAGY4GItaO1siR1KCWtM6+e2fiWC5LKfF IlNtxTNIoimJ1RJdD+qAOUzl6nGhJ4IMy55dQZ1HWLVRUNAi6lrjfCD9wKHxTddDThPH Uj2CVp6M6jydvMdicM1d3jBa4a9H3W8n7kISC+AcH8U9rog8EU6Xfdy1eOr53Tqe0/D2 aMA0i871LOnSTkVR0ujL0clIYTVZDARzAefhhulq8MtzhJrJrLl2hkqH2kzYZWQHDG5l +iRA== X-Gm-Message-State: AAQBX9cH6uKcYi9eAGsrqYwVAL+F5ir4pXPyN2/rtekdInBgGszoLXJX GePnq8VXO/hLSyuticfwAZInoJEx6w8d7YBWQVpTzT17 X-Google-Smtp-Source: AKy350a/hOvYlcMMPfQkRGJLCbiZ24/CjIak8NMlcbut6+1dF7bHaRN2LAcF2iu9cXqErTAC5eL+bg== X-Received: by 2002:a5d:50c1:0:b0:2ef:b5a0:35e8 with SMTP id f1-20020a5d50c1000000b002efb5a035e8mr10364496wrt.20.1681299829356; Wed, 12 Apr 2023 04:43:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 16/25] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index Date: Wed, 12 Apr 2023 13:43:24 +0200 Message-Id: <20230412114333.118895-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681300052001100001 Content-Type: text/plain; charset="utf-8" Incorporate the virt_enabled and MPV checks into the cpu_mmu_index function, so we don't have to keep doing it within tlb_fill and subroutines. This also elides a flush on changes to MPV. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-17-richard.henderson@linaro.org> --- target/riscv/cpu_helper.c | 49 ++++++++++++++------------------------- target/riscv/csr.c | 6 +---- 2 files changed, 18 insertions(+), 37 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index ccba3c45e7..baa4b3a1d2 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -37,19 +37,21 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #ifdef CONFIG_USER_ONLY return 0; #else - if (ifetch) { - return env->priv; - } + bool virt =3D env->virt_enabled; + int mode =3D env->priv; =20 /* All priv -> mmu_idx mapping are here */ - int mode =3D env->priv; - if (mode =3D=3D PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { - mode =3D get_field(env->mstatus, MSTATUS_MPP); + if (!ifetch) { + if (mode =3D=3D PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { + mode =3D get_field(env->mstatus, MSTATUS_MPP); + virt =3D get_field(env->mstatus, MSTATUS_MPV); + } + if (mode =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_SUM)) { + mode =3D MMUIdx_S_SUM; + } } - if (mode =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_SUM)) { - return MMUIdx_S_SUM; - } - return mode; + + return mode | (virt ? MMU_2STAGE_BIT : 0); #endif } =20 @@ -1162,7 +1164,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hw= addr physaddr, } =20 env->badaddr =3D addr; - env->two_stage_lookup =3D env->virt_enabled || mmuidx_2stage(mmu_idx); + env->two_stage_lookup =3D mmuidx_2stage(mmu_idx); env->two_stage_indirect_lookup =3D false; cpu_loop_exit_restore(cs, retaddr); } @@ -1187,7 +1189,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, g_assert_not_reached(); } env->badaddr =3D addr; - env->two_stage_lookup =3D env->virt_enabled || mmuidx_2stage(mmu_idx); + env->two_stage_lookup =3D mmuidx_2stage(mmu_idx); env->two_stage_indirect_lookup =3D false; cpu_loop_exit_restore(cs, retaddr); } @@ -1225,7 +1227,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, int prot, prot2, prot_pmp; bool pmp_violation =3D false; bool first_stage_error =3D true; - bool two_stage_lookup =3D false; + bool two_stage_lookup =3D mmuidx_2stage(mmu_idx); bool two_stage_indirect_error =3D false; int ret =3D TRANSLATE_FAIL; int mode =3D mmu_idx; @@ -1237,24 +1239,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,= int size, qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); =20 - /* - * MPRV does not affect the virtual-machine load/store - * instructions, HLV, HLVX, and HSV. - */ - if (mmuidx_2stage(mmu_idx)) { - ; - } else if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH && - get_field(env->mstatus, MSTATUS_MPRV)) { - mode =3D get_field(env->mstatus, MSTATUS_MPP); - if (riscv_has_ext(env, RVH) && get_field(env->mstatus, MSTATUS_MPV= )) { - two_stage_lookup =3D true; - } - } - pmu_tlb_fill_incr_ctr(cpu, access_type); - if (env->virt_enabled || - ((mmuidx_2stage(mmu_idx) || two_stage_lookup) && - access_type !=3D MMU_INST_FETCH)) { + if (two_stage_lookup) { /* Two stage lookup */ ret =3D get_physical_address(env, &pa, &prot, address, &env->guest_phys_fault_addr, access_typ= e, @@ -1350,8 +1336,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, return false; } else { raise_mmu_exception(env, address, access_type, pmp_violation, - first_stage_error, - env->virt_enabled || mmuidx_2stage(mmu_idx), + first_stage_error, two_stage_lookup, two_stage_indirect_error); cpu_loop_exit_restore(cs, retaddr); } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 124be448dc..211acad5ae 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1270,7 +1270,7 @@ static RISCVException write_mstatus(CPURISCVState *en= v, int csrno, val =3D legalize_mpp(env, get_field(mstatus, MSTATUS_MPP), val); =20 /* flush tlb on mstatus fields that affect VM */ - if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPV)) { + if ((val ^ mstatus) & MSTATUS_MXR) { tlb_flush(env_cpu(env)); } mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | @@ -1318,10 +1318,6 @@ static RISCVException write_mstatush(CPURISCVState *= env, int csrno, uint64_t valh =3D (uint64_t)val << 32; uint64_t mask =3D MSTATUS_MPV | MSTATUS_GVA; =20 - if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { - tlb_flush(env_cpu(env)); - } - env->mstatus =3D (env->mstatus & ~mask) | (valh & mask); =20 return RISCV_EXCP_NONE; --=20 2.34.1 From nobody Fri May 17 04:49:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1681300112; cv=none; d=zohomail.com; s=zohoarc; b=g24Df/6InlXVGMDoqHHOgKhInP4DJhoM9YN8Lkn8mEfrw7GACIN12APLTEhrwrbARtUIuzPGB+XSRq6iZ3mlQiaQe1aVsG+ujxeyAmYgKbPvMPiW0jTOEDXi6yx2IlB5MIVeKG2ews0x4J3T6aqRb+e+SG32oi/Ddh/4tsGEr8w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681300112; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PGKLd4EHm+dCotYmJKaBamFgwpM99B3AQVGNyZFQsdk=; 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[37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299830; x=1683891830; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PGKLd4EHm+dCotYmJKaBamFgwpM99B3AQVGNyZFQsdk=; b=QTF9njU393ydPl4QfHDvoJ8NgV5kD34YNrIFg9uMEPMwLND7vtcYS1ztBKBHoV8Rra yr18xSt41U3ZmIq5oWfRiC6kgvNmaxGveqmJ+JDJrrKNqoCN4vcBRUaCQ3PSVbO1p4l2 NLQBQeuPoJp01bzqcWfOlnJQqwM1bt43+Qk42yYYL4UkajtwzERtGKHZmERoLTHtoN5r ywdXXTVsdTteYGSaA9X7n6bsqpR9NoWBctkWth0t9kNIU5hN1YF99IwWL3RDgkWcGKwp u308NZDgO2Er+38tZPz6GxTLDovol7HMi04ZpM6WQM2CM/NSkQN5gY+h1UxsyCpnmRvA q0eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299830; x=1683891830; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PGKLd4EHm+dCotYmJKaBamFgwpM99B3AQVGNyZFQsdk=; b=wZukGK6tbiNJlUAfWefBPaIwszVQ7eNMCG/fcci64w2yajoeMaiypT5n8+PbR9ll+B QZUgZuYmJq9SvEuF1PmOHkPsIbRSY9ArfQqjSvYHccPt9ePIdFygef0OUHXQ6akSUP1W UFsaSfO8QqDWMSCxP68D1zA22Y15aZj7lvgTA2CjQF0zvRnEnp1x7y0dRuWO/1q4lD0S GhrEAKghpf+Zy2Vayn3pSNML1PHUSnSc2YlmGE+eYcaPiDz0MGrZCCQJh+dpNF4Lyk0x Ypw7yUDvPzIs+P/KYDMSkTpJBS/V8S93th9ttkT/HNqp8ujkNuWRkjlZ20cO5XeSX9IF CntQ== X-Gm-Message-State: AAQBX9eq+olE18ioks43rygDbmzQDHkd2FCLSW+YcFoaQ9nLT90vvRSO toMcUxeVVXSNCn0v4D4xOGqhM2PThqecv/NotmuwdLNZ X-Google-Smtp-Source: AKy350YeXzl7vGOQWx8T/TR1r6n2rHEI+GalmJjZBEA1gBg95x4BcNd4fOyRlOM/UL+fFSgCz497dQ== X-Received: by 2002:a05:600c:ad2:b0:3f0:7ddf:d8e4 with SMTP id c18-20020a05600c0ad200b003f07ddfd8e4mr1602192wmr.17.1681299830573; Wed, 12 Apr 2023 04:43:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 17/25] target/riscv: Check SUM in the correct register Date: Wed, 12 Apr 2023 13:43:25 +0200 Message-Id: <20230412114333.118895-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681300112775100002 Content-Type: text/plain; charset="utf-8" Table 9.5 "Effect of MPRV..." specifies that MPV=3D1 uses VS-level vsstatus.SUM instead of HS-level sstatus.SUM. For HLV/HSV instructions, the HS-level register does not apply, but the VS-level register presumably does, though this is not mentioned explicitly in the manual. However, it matches the behavior for MPV. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-18-richard.henderson@linaro.org> --- target/riscv/cpu_helper.c | 12 ++++++++---- target/riscv/op_helper.c | 6 +++++- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index baa4b3a1d2..38bd83f66d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -42,11 +42,16 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) =20 /* All priv -> mmu_idx mapping are here */ if (!ifetch) { - if (mode =3D=3D PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { + uint64_t status =3D env->mstatus; + + if (mode =3D=3D PRV_M && get_field(status, MSTATUS_MPRV)) { mode =3D get_field(env->mstatus, MSTATUS_MPP); virt =3D get_field(env->mstatus, MSTATUS_MPV); + if (virt) { + status =3D env->vsstatus; + } } - if (mode =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_SUM)) { + if (mode =3D=3D PRV_S && get_field(status, MSTATUS_SUM)) { mode =3D MMUIdx_S_SUM; } } @@ -826,8 +831,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, } widened =3D 2; } - /* status.SUM will be ignored if execute on background */ - sum =3D mmuidx_sum(mmu_idx) || use_background || is_debug; + sum =3D mmuidx_sum(mmu_idx) || is_debug; switch (vm) { case VM_1_10_SV32: levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 49c19d971d..66a9065a5d 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -437,7 +437,11 @@ static int check_access_hlsv(CPURISCVState *env, bool = x, uintptr_t ra) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } =20 - return get_field(env->hstatus, HSTATUS_SPVP) | MMU_2STAGE_BIT; + int mode =3D get_field(env->hstatus, HSTATUS_SPVP); + if (!x && mode =3D=3D PRV_S && get_field(env->vsstatus, MSTATUS_SUM)) { + mode =3D MMUIdx_S_SUM; + } + return mode | MMU_2STAGE_BIT; } =20 target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr) --=20 2.34.1 From nobody Fri May 17 04:49:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1681300236; cv=none; d=zohomail.com; s=zohoarc; b=SabCPvC4w1M3SqSco23//eEp+N3y8US/gVDhhhILSANSWqjUZXxNhhrR4HhzL7RL0WXB0k1MhFlnfXRkz8cHOwjqosINFca6KPgoyZpUsOmtgkSTG0wUNjxH4SfkmHXXTHck/bW44N0vxN9jsy2gywZilCSMEJ5bWEDr8UoKa5M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681300236; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VRysGopMuvQKVUYQZTztZp4OETaqkIX63XPVMpwePPA=; b=ncDjcMzS2bF7zP/bw5AW6BV2eFTf5bLUxeEpzEoQrRQvoNQQLD/4amD6WVAHvh8A/QxU6FkvoQGtTC2Brss43UoibfdhBCZglBaXjRrK1Rz+TSwYyb+kHlp7/WAaA2whrxOzr85HcxmQtWK4+EI+563YqRq5XHzjSaHYpbOLgO8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168130023690961.19624459939928; Wed, 12 Apr 2023 04:50:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pmYti-0006Nh-Ae; Wed, 12 Apr 2023 07:44:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pmYtI-0004xE-70 for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:57 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pmYtF-0002TT-41 for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:55 -0400 Received: by mail-wm1-x330.google.com with SMTP id m8so20047771wmq.5 for ; Wed, 12 Apr 2023 04:43:52 -0700 (PDT) Received: from stoup.hotel.gast (ip-037-024-010-236.um08.pools.vodafone-ip.de. [37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299831; x=1683891831; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VRysGopMuvQKVUYQZTztZp4OETaqkIX63XPVMpwePPA=; b=QJ3F18qOPbwQNDoW+wchI3it8GRc+GussBXF1STfJmsi5SLrFqNbwQaYrs+ylqzIO7 Qjhm3SIpvEuKhxgjP8BMI9HDxx+7veVSXfVAbtotqsMD/cU9dBo59Wkor/6+Fncn2BfY sVJCX5SEHZ6ImZFisg47wFz5z8Cr5cConbTB47l5zbqoVTpXx5a3j20gNs2aIFKxUduP F6AzjFKIvFwNXjuVolFS3LeJCXW8aZJZuGlH4wMJQ+OOIsKb8sTUqinobAGVizt0s6uP uRGn/cIt899oNqIvDLBJFvwt67k63LpZ5nqXhWTx83EXyDc9YshEgI5FR/vM6dqLdkhh qUiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299831; x=1683891831; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VRysGopMuvQKVUYQZTztZp4OETaqkIX63XPVMpwePPA=; b=0LB4TwPDj2ACanb/Awd0QgsCRvaq/CVUYDIw6mMqvpl2NhmKCz+qxdvuJfnV5wgjkf kCgTqNpXj9PQ/sbH07EQE0lsaz8xa5sehB/cUjH6UapMVf4C1bz1Zkrb+X5Ng1bdW0QN ZTG+Ta3ZP8gW8ZDE055qhnYTKdS/kVqwUq+g4VBqxAHozsbUerbjmq/nOm9/U5sjx+6A R0zD10SzqmAQcL9JgotsKJYj3gUvvUbJIz6nBbARrV33lWxt2Ni5PyHOpZiqk14P+J2F +2s9X644Srmoe14YHisQMSQMcHtLsgpkkkZZep27cs0kPFlVZzZrUxzarEFOSUDfX4on d6Sw== X-Gm-Message-State: AAQBX9e9HdQuU1huUnhpcNmyGFUd35hoCpC3Zf+B7GBcOlC2sUaHLfEI hf7accqJqbfSmfhB0E4uhKQI69Jst58TRoxaQ+wBIOTc X-Google-Smtp-Source: AKy350bvuDFgwcboZTIKmtWn1tIaEAiu/BYgWnH6b8vMfrJfLAe2m3S8iUn1ZuTciYXd/2DIluW+gw== X-Received: by 2002:a1c:7917:0:b0:3f0:9f28:fb6c with SMTP id l23-20020a1c7917000000b003f09f28fb6cmr1061289wme.12.1681299831380; Wed, 12 Apr 2023 04:43:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 18/25] target/riscv: Hoist second stage mode change to callers Date: Wed, 12 Apr 2023 13:43:26 +0200 Message-Id: <20230412114333.118895-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681300239079100005 Content-Type: text/plain; charset="utf-8" Move the check from the top of get_physical_address to the two callers, where passing mmu_idx makes no sense. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-19-richard.henderson@linaro.org> --- target/riscv/cpu_helper.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 38bd83f66d..5753e4e612 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -777,14 +777,6 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, use_background =3D true; } =20 - if (first_stage =3D=3D false) { - /* - * We are in stage 2 translation, this is similar to stage 1. - * Stage 2 is always taken as U-mode - */ - mode =3D PRV_U; - } - if (mode =3D=3D PRV_M || !riscv_cpu_cfg(env)->mmu) { *physical =3D addr; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -890,7 +882,7 @@ restart: /* Do the second stage translation on the base PTE address. */ int vbase_ret =3D get_physical_address(env, &vbase, &vbase_pro= t, base, NULL, MMU_DATA_LOAD, - mmu_idx, false, true, + MMUIdx_U, false, true, is_debug); =20 if (vbase_ret !=3D TRANSLATE_SUCCESS) { @@ -1271,7 +1263,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, im_address =3D pa; =20 ret =3D get_physical_address(env, &pa, &prot2, im_address, NUL= L, - access_type, mmu_idx, false, true, + access_type, MMUIdx_U, false, true, false); =20 qemu_log_mask(CPU_LOG_MMU, --=20 2.34.1 From nobody Fri May 17 04:49:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1681300237; cv=none; d=zohomail.com; s=zohoarc; b=HoZyF5Gun03AbNKD8veuDU3nvQvswVLDrxPsWH9sseCq1Z6txfSF3kEfaEjZuwQd/4g//FucYi+Uzo84kdMsRCfPbMyR6bpmiWrYNQJjmWK8vHKGd9ctsPMwsPckItlv99L3Wulrwx+f1EQ4sc2Kh5Z81Os+1F6CJ8zuTL9cyS8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681300237; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4dyXCtchSD+HKn11xxL6vJfEveqvcGr2NQzNKSenNrQ=; b=ORKxVEjHDSnmGKC9JAslnaKuVR90dBTI+edciMioxEHnXWuR7O/FacaO5Egi40/QI5ylX+sKJMmB3Z9p7Ak2ce6N9adWHxYkt7PjYqBf3IWJmpL9qk/Ep6o5HVysFk9SO5m1tuK2bBY28zsKA+g11hssgmTDNcNgTJ5pA/2C4/8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681300237038660.943494385734; Wed, 12 Apr 2023 04:50:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pmYtf-0005xa-A0; Wed, 12 Apr 2023 07:44:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pmYtG-0004wy-V6 for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:57 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pmYtF-0002Rd-3j for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:54 -0400 Received: by mail-wr1-x431.google.com with SMTP id v6so10561386wrv.8 for ; Wed, 12 Apr 2023 04:43:52 -0700 (PDT) Received: from stoup.hotel.gast (ip-037-024-010-236.um08.pools.vodafone-ip.de. [37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299832; x=1683891832; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4dyXCtchSD+HKn11xxL6vJfEveqvcGr2NQzNKSenNrQ=; b=BKIDOmBSyPRnXY7Vdzj9fSl2kqvbzlnJEMpcXPAvRXqM8mjU6jcsGgHhKLfj7WaOen 19yCWM6+e9R6QpUNCH6gf+g7yOA/jHBywUDfReRRihufm53f11lU0+uqxfjEaLfbpCpo if1D869VpRXNqfm+vBPSjmdGtZb8uj4QCWjRNpBKlwmzn2UWFF9FWMMDWqscxpxAeXXp MYDSMl2508/6OMKFSes0NHL/1QcgQp9Yrm73FIHiBsncLssgJtSdJUrejYFqHybQyXC2 P4idbz5EH7vx7mSpct2onVk55GqflZuA+avYDu9b5vgBki9txWF5KcMV+ZaW6NzTSnUp ifDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299832; x=1683891832; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4dyXCtchSD+HKn11xxL6vJfEveqvcGr2NQzNKSenNrQ=; b=DVXda2iKIEMQs7vMhWRLU3vQs0CD6oboIl8vv0ZR8fmeQy+J+JK/44PTIpPf2NliEc M5aqlfJ9OXUVHE8yt0spWMYLCk1/DdyNve62dXIesSe6GlDorKTDC0eKQRiHwNWr4rcc LdvNx5OkhDIn4Ak9MLR0BHyvXZsNFhLGtaJyQTSufEAa+6+71RV5C570l1BYdAZNem0F v2ACG++tdm+PPer/XVP2HQ7wtuZ4splXtbWKtAP5R8zHdITvRkzDJb2teyRlgek3boaM 94KAaDdXXLGw13TqjVLy4vUpSM5t6nZM7d3Tdt/+DCuSMNx31RvGNMI6e94uCqDDJiKZ TlSQ== X-Gm-Message-State: AAQBX9dqWyOFMqEmIIO+wGRVoxJwBbIaDhnOOmh1nprRT1QGJeJZqw4V Ha7UA0/ARZI7a34tCxirtDvGj+eZseFC8AunkRteQa0A X-Google-Smtp-Source: AKy350Y4mSs9yEOtaPu8bsIuycDfsZRSCjMoxh4lcsT3j/olLMkDihgx+xJAFc4OLJkyCBbdmnM1Tg== X-Received: by 2002:a05:6000:1003:b0:2f2:d852:c3f8 with SMTP id a3-20020a056000100300b002f2d852c3f8mr4209725wrx.39.1681299832312; Wed, 12 Apr 2023 04:43:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 19/25] target/riscv: Hoist pbmte and hade out of the level loop Date: Wed, 12 Apr 2023 13:43:27 +0200 Message-Id: <20230412114333.118895-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681300239218100007 Content-Type: text/plain; charset="utf-8" These values are constant for every level of pte lookup. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-20-richard.henderson@linaro.org> --- target/riscv/cpu_helper.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 5753e4e612..7c9f89d4d3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -856,6 +856,14 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, return TRANSLATE_FAIL; } =20 + bool pbmte =3D env->menvcfg & MENVCFG_PBMTE; + bool hade =3D env->menvcfg & MENVCFG_HADE; + + if (first_stage && two_stage && env->virt_enabled) { + pbmte =3D pbmte && (env->henvcfg & HENVCFG_PBMTE); + hade =3D hade && (env->henvcfg & HENVCFG_HADE); + } + int ptshift =3D (levels - 1) * ptidxbits; int i; =20 @@ -916,14 +924,6 @@ restart: return TRANSLATE_FAIL; } =20 - bool pbmte =3D env->menvcfg & MENVCFG_PBMTE; - bool hade =3D env->menvcfg & MENVCFG_HADE; - - if (first_stage && two_stage && env->virt_enabled) { - pbmte =3D pbmte && (env->henvcfg & HENVCFG_PBMTE); - hade =3D hade && (env->henvcfg & HENVCFG_HADE); - } - if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { ppn =3D pte >> PTE_PPN_SHIFT; } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) { --=20 2.34.1 From nobody Fri May 17 04:49:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1681300006; cv=none; d=zohomail.com; s=zohoarc; b=PCheSrp5p+G1M2/VoHHWvqZBOr4OCmdohhnXq4AijCObdBOIBG2gQQ5aMq4HRXI2H7SHDwyqwb+9+gME6Ken+sqNQS3fBrWL0sltjxR32NGgSVPdIfp0gp2vzjTwJcYAbl9hA5rPfA8fWqxkEacSvDvyWZpu83c3EtrbCNwKxzA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681300006; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4wya4UWrfM6HlFM9BlBmRDPTvoeLhiO0tJTDNDDUjUY=; b=frLkyiWUYnpJPjiEROuAvb2PYwcaEmYstdrwMNjedmwWYyfmZHMoj1CXsmLMrQg9t0YDR73dCAMG4xVTOAnYV3P9NVbtlKOUZ+raPtjTf4mJuOS4RQ0z9UZmsYXxqnCzHtSWiTYsW/GRNMUsMMa7HHHUzaKXZyhGSer0f/ElO8M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681300006214907.2594656939715; Wed, 12 Apr 2023 04:46:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pmYth-0006Fv-5p; Wed, 12 Apr 2023 07:44:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pmYtI-0004xZ-Py for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:57 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pmYtG-0002UB-On for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:56 -0400 Received: by mail-wr1-x431.google.com with SMTP id v6so10561422wrv.8 for ; Wed, 12 Apr 2023 04:43:54 -0700 (PDT) Received: from stoup.hotel.gast (ip-037-024-010-236.um08.pools.vodafone-ip.de. [37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299833; x=1683891833; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4wya4UWrfM6HlFM9BlBmRDPTvoeLhiO0tJTDNDDUjUY=; b=iW8EY7N3pHi4bOxiGnuzivpg4mm4O1zwdElQMn393nM1ciyctixacvZmaBO0XdTcz0 Ti4EG3ndAmPaQvOVOzM8ErLqm+7bsPef519uwcuXqRiWHfBdkcsW+M8/pfbOHfqYfUwj byZ9GUa9yt4ftR2KANRmnJWVrDObQpvOoLjns4qdZGsugll0yPCcKz/TvY6EoPUOL+RL LS+dxiVjqmWLxCpEQ6DbUwdd0aB6WuloZO8Nxd5f9V3Lh9obBArPHWlzcskKUn+ys4gG xbIq0KsgGOjgr/5znjgDfEydQEWliK4pFZCpZG+sE+lMt2d7mfhYIWivHM8bu0Jy4C/O sb9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299833; x=1683891833; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4wya4UWrfM6HlFM9BlBmRDPTvoeLhiO0tJTDNDDUjUY=; b=fCJnoaELFu9ujmWpD3YOeFhUgOT2geJJPsd8QHaXBnQnpbZMJFaZX/A26U7fkjWKFm N3LW5W9Y0P8S0zwVnyxBH/L3uPyCI5GX/KPzXrlkdUdt4WfUTu91j8OBZ/UX70ePKFRj n3wlhKXFSTf3STOviuf+ukfwa7Ln5Bkz+EQWbGTxWy9XYLVv9AwDJrZoWqomKNn0rRy8 VX0B/aSCmR9y1JaS/0b2O12OksRO4HOLnET1AyPvEWGFgHAatbX8fmsP11j4Gs9y8dFU ocLke9JpqYfvMmPLZOska9M6C0Gkb5fUtg5U9NwMxmiYjO14T0MiploG3XzT+g20nQzj 3Qng== X-Gm-Message-State: AAQBX9fxRquzTv6tI1ETD/6weXKSqJeX/ZtNFeerHIPW1o+W3HmYK81P CWmI5yCqVsxEUYmR3v84ssPNYkFXwaLj3PkaijTiRLFh X-Google-Smtp-Source: AKy350YfmfJkX+7nPPral9DpjjGMI42X10YB35PBSy8dXyeXF446du4PBWjYscmzt40YELCopVxynA== X-Received: by 2002:adf:f20b:0:b0:2d1:e517:4992 with SMTP id p11-20020adff20b000000b002d1e5174992mr4008816wro.69.1681299833415; Wed, 12 Apr 2023 04:43:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 20/25] target/riscv: Move leaf pte processing out of level loop Date: Wed, 12 Apr 2023 13:43:28 +0200 Message-Id: <20230412114333.118895-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681300008090100003 Content-Type: text/plain; charset="utf-8" Move the code that never loops outside of the loop. Unchain the if-return-else statements. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-21-richard.henderson@linaro.org> --- target/riscv/cpu_helper.c | 238 ++++++++++++++++++++------------------ 1 file changed, 125 insertions(+), 113 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 7c9f89d4d3..c2d083f029 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -865,6 +865,8 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, } =20 int ptshift =3D (levels - 1) * ptidxbits; + target_ulong pte; + hwaddr pte_addr; int i; =20 #if !TCG_OVERSIZED_GUEST @@ -881,7 +883,6 @@ restart: } =20 /* check that physical address of PTE is legal */ - hwaddr pte_addr; =20 if (two_stage && first_stage) { int vbase_prot; @@ -913,7 +914,6 @@ restart: return TRANSLATE_PMP_FAIL; } =20 - target_ulong pte; if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { pte =3D address_space_ldl(cs->as, pte_addr, attrs, &res); } else { @@ -938,128 +938,140 @@ restart: if (!(pte & PTE_V)) { /* Invalid PTE */ return TRANSLATE_FAIL; - } else if (!pbmte && (pte & PTE_PBMT)) { + } + if (pte & (PTE_R | PTE_W | PTE_X)) { + goto leaf; + } + + /* Inner PTE, continue walking */ + if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { return TRANSLATE_FAIL; - } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { - /* Inner PTE, continue walking */ - if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { - return TRANSLATE_FAIL; - } - base =3D ppn << PGSHIFT; - } else if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D PTE_W) { - /* Reserved leaf PTE flags: PTE_W */ - return TRANSLATE_FAIL; - } else if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D (PTE_W | PTE_X))= { - /* Reserved leaf PTE flags: PTE_W + PTE_X */ - return TRANSLATE_FAIL; - } else if ((pte & PTE_U) && ((mode !=3D PRV_U) && - (!sum || access_type =3D=3D MMU_INST_FETCH))) { - /* User PTE flags when not U mode and mstatus.SUM is not set, - or the access type is an instruction fetch */ - return TRANSLATE_FAIL; - } else if (!(pte & PTE_U) && (mode !=3D PRV_S)) { - /* Supervisor PTE flags when not S mode */ - return TRANSLATE_FAIL; - } else if (ppn & ((1ULL << ptshift) - 1)) { - /* Misaligned PPN */ - return TRANSLATE_FAIL; - } else if (access_type =3D=3D MMU_DATA_LOAD && !((pte & PTE_R) || - ((pte & PTE_X) && mxr))) { - /* Read access check failed */ - return TRANSLATE_FAIL; - } else if (access_type =3D=3D MMU_DATA_STORE && !(pte & PTE_W)) { - /* Write access check failed */ - return TRANSLATE_FAIL; - } else if (access_type =3D=3D MMU_INST_FETCH && !(pte & PTE_X)) { - /* Fetch access check failed */ - return TRANSLATE_FAIL; - } else { - /* if necessary, set accessed and dirty bits. */ - target_ulong updated_pte =3D pte | PTE_A | + } + base =3D ppn << PGSHIFT; + } + + /* No leaf pte at any translation level. */ + return TRANSLATE_FAIL; + + leaf: + if (ppn & ((1ULL << ptshift) - 1)) { + /* Misaligned PPN */ + return TRANSLATE_FAIL; + } + if (!pbmte && (pte & PTE_PBMT)) { + /* Reserved without Svpbmt. */ + return TRANSLATE_FAIL; + } + if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D PTE_W) { + /* Reserved leaf PTE flags: PTE_W */ + return TRANSLATE_FAIL; + } + if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D (PTE_W | PTE_X)) { + /* Reserved leaf PTE flags: PTE_W + PTE_X */ + return TRANSLATE_FAIL; + } + if ((pte & PTE_U) && + ((mode !=3D PRV_U) && (!sum || access_type =3D=3D MMU_INST_FETCH))= ) { + /* + * User PTE flags when not U mode and mstatus.SUM is not set, + * or the access type is an instruction fetch. + */ + return TRANSLATE_FAIL; + } + if (!(pte & PTE_U) && (mode !=3D PRV_S)) { + /* Supervisor PTE flags when not S mode */ + return TRANSLATE_FAIL; + } + if (access_type =3D=3D MMU_DATA_LOAD && + !((pte & PTE_R) || ((pte & PTE_X) && mxr))) { + /* Read access check failed */ + return TRANSLATE_FAIL; + } + if (access_type =3D=3D MMU_DATA_STORE && !(pte & PTE_W)) { + /* Write access check failed */ + return TRANSLATE_FAIL; + } + if (access_type =3D=3D MMU_INST_FETCH && !(pte & PTE_X)) { + /* Fetch access check failed */ + return TRANSLATE_FAIL; + } + + /* If necessary, set accessed and dirty bits. */ + target_ulong updated_pte =3D pte | PTE_A | (access_type =3D=3D MMU_DATA_STORE ? PTE_D : 0); =20 - /* Page table updates need to be atomic with MTTCG enabled */ - if (updated_pte !=3D pte) { - if (!hade) { - return TRANSLATE_FAIL; - } + /* Page table updates need to be atomic with MTTCG enabled */ + if (updated_pte !=3D pte) { + if (!hade) { + return TRANSLATE_FAIL; + } =20 - /* - * - if accessed or dirty bits need updating, and the PTE = is - * in RAM, then we do so atomically with a compare and s= wap. - * - if the PTE is in IO space or ROM, then it can't be up= dated - * and we return TRANSLATE_FAIL. - * - if the PTE changed by the time we went to update it, = then - * it is no longer valid and we must re-walk the page ta= ble. - */ - MemoryRegion *mr; - hwaddr l =3D sizeof(target_ulong), addr1; - mr =3D address_space_translate(cs->as, pte_addr, &addr1, &= l, - false, MEMTXATTRS_UNSPECIFIED= ); - if (memory_region_is_ram(mr)) { - target_ulong *pte_pa =3D - qemu_map_ram_ptr(mr->ram_block, addr1); + /* + * - if accessed or dirty bits need updating, and the PTE is + * in RAM, then we do so atomically with a compare and swap. + * - if the PTE is in IO space or ROM, then it can't be updated + * and we return TRANSLATE_FAIL. + * - if the PTE changed by the time we went to update it, then + * it is no longer valid and we must re-walk the page table. + */ + MemoryRegion *mr; + hwaddr l =3D sizeof(target_ulong), addr1; + mr =3D address_space_translate(cs->as, pte_addr, &addr1, &l, + false, MEMTXATTRS_UNSPECIFIED); + if (memory_region_is_ram(mr)) { + target_ulong *pte_pa =3D qemu_map_ram_ptr(mr->ram_block, addr1= ); #if TCG_OVERSIZED_GUEST - /* - * MTTCG is not enabled on oversized TCG guests so - * page table updates do not need to be atomic - */ - *pte_pa =3D pte =3D updated_pte; + /* + * MTTCG is not enabled on oversized TCG guests so + * page table updates do not need to be atomic + */ + *pte_pa =3D pte =3D updated_pte; #else - target_ulong old_pte =3D - qatomic_cmpxchg(pte_pa, pte, updated_pte); - if (old_pte !=3D pte) { - goto restart; - } else { - pte =3D updated_pte; - } + target_ulong old_pte =3D qatomic_cmpxchg(pte_pa, pte, updated_= pte); + if (old_pte !=3D pte) { + goto restart; + } + pte =3D updated_pte; #endif - } else { - /* - * misconfigured PTE in ROM (AD bits are not preset) or - * PTE is in IO space and can't be updated atomically - */ - return TRANSLATE_FAIL; - } - } - + } else { /* - * for superpage mappings, make a fake leaf PTE for the TLB's - * benefit. + * Misconfigured PTE in ROM (AD bits are not preset) or + * PTE is in IO space and can't be updated atomically. */ - target_ulong vpn =3D addr >> PGSHIFT; - - if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { - napot_bits =3D ctzl(ppn) + 1; - if ((i !=3D (levels - 1)) || (napot_bits !=3D 4)) { - return TRANSLATE_FAIL; - } - } - - napot_mask =3D (1 << napot_bits) - 1; - *physical =3D (((ppn & ~napot_mask) | (vpn & napot_mask) | - (vpn & (((target_ulong)1 << ptshift) - 1)) - ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); - - /* set permissions on the TLB entry */ - if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { - *prot |=3D PAGE_READ; - } - if (pte & PTE_X) { - *prot |=3D PAGE_EXEC; - } - /* - * add write permission on stores or if the page is already di= rty, - * so that we TLB miss on later writes to update the dirty bit - */ - if ((pte & PTE_W) && - (access_type =3D=3D MMU_DATA_STORE || (pte & PTE_D))) { - *prot |=3D PAGE_WRITE; - } - return TRANSLATE_SUCCESS; + return TRANSLATE_FAIL; } } - return TRANSLATE_FAIL; + + /* For superpage mappings, make a fake leaf PTE for the TLB's benefit.= */ + target_ulong vpn =3D addr >> PGSHIFT; + + if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { + napot_bits =3D ctzl(ppn) + 1; + if ((i !=3D (levels - 1)) || (napot_bits !=3D 4)) { + return TRANSLATE_FAIL; + } + } + + napot_mask =3D (1 << napot_bits) - 1; + *physical =3D (((ppn & ~napot_mask) | (vpn & napot_mask) | + (vpn & (((target_ulong)1 << ptshift) - 1)) + ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); + + /* set permissions on the TLB entry */ + if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { + *prot |=3D PAGE_READ; + } + if (pte & PTE_X) { + *prot |=3D PAGE_EXEC; + } + /* + * Add write permission on stores or if the page is already dirty, + * so that we TLB miss on later writes to update the dirty bit. + */ + if ((pte & PTE_W) && (access_type =3D=3D MMU_DATA_STORE || (pte & PTE_= D))) { + *prot |=3D PAGE_WRITE; + } + return TRANSLATE_SUCCESS; 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[37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299834; x=1683891834; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YAXm4ASIFttpyWJKyvCjhM0MOstGOXoJQiE+ToyL5+M=; b=JQEcA83IUV8RsbqU9Jt1Ab2eJb90z0Dew09aJl+CBYZxLWseO/BOfWLdsJRDAZIifJ Y2gqzORdm82xcIfN3QvNmWNnfhUNVnSqVq5FCDqDxZr4dm5sntl4uH7QlI4Cypo7OuIl ftNBdg4dm1/FRBRkETXEWeAf6X2gKfr0mMaoHBtPahd9zu34B34uuikcBDMwZHZ/z4Ad eyfbFcLurDAdOJba8aKW9XEoSPcUzoLy2I2x4Xwcz3kTZnxDPvt+U/Gb1AjyCzQHONEh QejIVWnUoF1/w14eUNAvcS/wv6nNtiM1VUq+bSyocHDPUDg8nsQuC7fB9RSCxkOcS7sE EHGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299834; x=1683891834; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YAXm4ASIFttpyWJKyvCjhM0MOstGOXoJQiE+ToyL5+M=; b=Cte3Jhwq+k11P+ZFDVzD/6PDkVIm5j0qtG+P5aa9iQqmCFhs7P90bfsBt96bwaSBjC XuMvzbo7agdIQjjUO5Gpx9CRxQnEzm+HbWn/bvC8EDtCNawwotFp0R4uhfBnuGImAB1u 3CLRKXuXOi5Jk18Vg2GgXAvB7rE4/kctpeZIsBTtL0aKjeBdnHYmFGnFMJ5TSidMJtaO z+1P7xOt2P0XrDdPQxvOWKYwSfAIP1GyFgsdxt/0dH+x/5OJDMLoPF2uStqGSgAESRDv O7p7n7fET2KQvYLwXhTy6W3staRr/d43nV2a//o/EeuG/iQD0ug7KTwHZNLYTIQWbnWm m6Mg== X-Gm-Message-State: AAQBX9d0dTmrTPFzNJ1twBrUBzTvP6B2krkgdlmaa9NPugIkD9j2R+PD eJGOKUfsFulONEWZ8G2RVSOtzacd9pDhvim5G8TPlxaK X-Google-Smtp-Source: AKy350YvIlQGifSQ7fBdXpQoq61rIGmkxDMHypVyv/Q3fHE7g2Gw/ISPnjZMuFP7kaUuE6vRhjHAcA== X-Received: by 2002:a5d:6dd0:0:b0:2cf:9889:8428 with SMTP id d16-20020a5d6dd0000000b002cf98898428mr4319572wrz.35.1681299834123; Wed, 12 Apr 2023 04:43:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 21/25] target/riscv: Suppress pte update with is_debug Date: Wed, 12 Apr 2023 13:43:29 +0200 Message-Id: <20230412114333.118895-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681300396454100003 Content-Type: text/plain; charset="utf-8" The debugger should not modify PTE_A or PTE_D. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-22-richard.henderson@linaro.org> --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c2d083f029..6dc3fdf594 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1001,7 +1001,7 @@ restart: (access_type =3D=3D MMU_DATA_STORE ? PTE_D : 0); =20 /* Page table updates need to be atomic with MTTCG enabled */ - if (updated_pte !=3D pte) { + if (updated_pte !=3D pte && !is_debug) { if (!hade) { return TRANSLATE_FAIL; } --=20 2.34.1 From nobody Fri May 17 04:49:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1681299883; cv=none; d=zohomail.com; s=zohoarc; b=lmhbMo+w1jy4ho7ikTVC+zeX5gm1HTBYV/eeb3eaDeFC5SEua0UtJaPzJwHtf8SlF0+rFIY8N05h5SO3PW6LLjOyTMjgVRXWGoRSMSIrvAzKE+zXfjPobaUTdRLw3LZ1Fprlp01Wwmuo7uN6N29RhbNqp8bDOqTHXlSQVuTDmxU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681299883; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Zn52Ufb7DRbVaQ81Qm+6XQB/991khVVrBH6/wkfCyPw=; b=k91Kbg6gIA62x7D49vp9J8nG8uJrDTA6PTYV/b0GW0ju7j763WqxaR+Q3gSaHlJ9X2JalPQdZN4hCOp6D+NXbDWappN3GbLUe/81a9bAaiH2Wkd6mRGQiYqYe55UHZM3ruDNeCHVJF2ssiAM4YpwUxMLUe5q1wPBwZUMIANKjYU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168129988341674.54051359104255; Wed, 12 Apr 2023 04:44:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pmYtk-0006aU-Rw; Wed, 12 Apr 2023 07:44:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pmYtJ-0004z4-UD for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:59 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pmYtI-0002NQ-Ai for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:57 -0400 Received: by mail-wr1-x430.google.com with SMTP id e7so494456wrc.12 for ; Wed, 12 Apr 2023 04:43:55 -0700 (PDT) Received: from stoup.hotel.gast (ip-037-024-010-236.um08.pools.vodafone-ip.de. [37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299835; x=1683891835; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zn52Ufb7DRbVaQ81Qm+6XQB/991khVVrBH6/wkfCyPw=; b=tct9DIzAzD/uENt4eA2Cqn0Fmd8KmINwv3jrPeu7YUoQLVUOVMPtzAs11P6KlHoEBq psbFabdJIBPWD8DQTUYlUO5bBp6p39SwcTmPc665VJgPvKHUuOW+CqMdp8GkU0XJ9oPj 7ul9MXh2162cSexD4qFLsIoMAFyFaVC4ZBRwsAz1P016MjhKtLo95qBEvRVU3AP3CaKX nDJFB10/mTbU4jfLUWHkqxm0ZIcYbCSBiVXXCFptlpFk2L9542vlDyh/zh6bnFMuTR1J P0A7IWrKn80LU++ix5yPdWrYQtInz+oRSBp+3hDDaFa8/fwnedql3nDOcE9P+A5Y7Ev9 z38w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299835; x=1683891835; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zn52Ufb7DRbVaQ81Qm+6XQB/991khVVrBH6/wkfCyPw=; b=q7CKL8ehhIdCmhydA2w6AKL9fYmpFTf1feAKCCMMb4AMg4OXbNBDHOdUESbj/0LvNC 5YOrMI+1CGrsFFKiZDjm4NGwerASDW2PVmWGm+DKUk6xIiFpxwB9QDK+lCi6qvODDsga zN0T9naOk/MGajOlWGUuzAe6NthLGn9YvuzjRN4CYGB/YQp7tjl7xoZ6zaC9EcEm1/+G mAgv4MNwxXq90Gbv4ts0+Lz4wMjKrkJDL1x4//6c1feivt06ceiqLAGpiXoCy2nHFgok 3IlJO0L7iyZCQ2kdP19dC5FrRebk+IdYuI+1BrsCg5mvlkBI/LMKZb7YGa517q3ynZ/y 3HvQ== X-Gm-Message-State: AAQBX9cKOWZXwGl19s3OtpJZa6vsIdjq0HaxMWCP8dKn8JEho0cn/5bH XBhy9r7ryweJXRCDtfYlvU4++/PXw3kq3WIZEU+q+pJC X-Google-Smtp-Source: AKy350Y7eOmOq9QKa+ymbWiAbGYqs2gUm360EMJFkcH6lpvLADPH9jRCJHxcCQB4Dt272SSs6fVbHg== X-Received: by 2002:a5d:4902:0:b0:2c7:d575:e8a4 with SMTP id x2-20020a5d4902000000b002c7d575e8a4mr9580924wrq.65.1681299835563; Wed, 12 Apr 2023 04:43:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 22/25] target/riscv: Don't modify SUM with is_debug Date: Wed, 12 Apr 2023 13:43:30 +0200 Message-Id: <20230412114333.118895-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681299885607100003 Content-Type: text/plain; charset="utf-8" If we want to give the debugger a greater view of memory than the cpu, we should simply disable the access check entirely, not simply for this one corner case. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-23-richard.henderson@linaro.org> --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 6dc3fdf594..9a2b944990 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -823,7 +823,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, } widened =3D 2; } - sum =3D mmuidx_sum(mmu_idx) || is_debug; + sum =3D mmuidx_sum(mmu_idx); switch (vm) { case VM_1_10_SV32: levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; --=20 2.34.1 From nobody Fri May 17 04:49:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1681300016; cv=none; d=zohomail.com; s=zohoarc; b=CwMThZmF0V8YjPcdXOXYN0G/JDLrx6XLgoWmyXEjTjsAQVSAVextzZS4OWxoTXNksYO1ozOmMFEBIHx+ZdAbeIfr035iKLh8SJb8OXWc/VkRoK/y+AaqzvyIRzIUkz7C9bX/MILU+36k1koSb3dVCSfavR+BVl6CYm4NqR5qNtc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681300016; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ia5N2/U/AO+3qNL0VIGZiWVWDwXAJ3RRrVuamnKN6gs=; b=hgEzN83rkmy/CgiwTdTLIm2IiR1s56zvAEe5CFkWO1lw5QngMFtD7uzJxokA+7ivNrtAXgdVu2sCJUWBv90vZvqZ9IZjL7c95oV9cKid8CSGpB+53owf5D9AF6uNaQ4SzVdn8XCTcyKw3H7K0W8A+12d35ehzsapFzxPenj3NuA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681300016725209.56531498465336; Wed, 12 Apr 2023 04:46:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pmYtj-0006W3-RW; Wed, 12 Apr 2023 07:44:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pmYtK-0004zG-Ma for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:59 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pmYtI-0002Rd-Ra for qemu-devel@nongnu.org; Wed, 12 Apr 2023 07:43:58 -0400 Received: by mail-wr1-x431.google.com with SMTP id v6so10561548wrv.8 for ; Wed, 12 Apr 2023 04:43:56 -0700 (PDT) Received: from stoup.hotel.gast (ip-037-024-010-236.um08.pools.vodafone-ip.de. [37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299836; x=1683891836; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ia5N2/U/AO+3qNL0VIGZiWVWDwXAJ3RRrVuamnKN6gs=; b=XGws3MzszdtAXrTZpOBPFyrF/g1amQqNqyEbNRxDOwD7oWlsBcdQXtlhco9Smf5EN1 bgexxb79eii3srT78wW9PzidwBAw1lOsClDuJZ7iKOAyA0DoEjdVkqUN075p7SFEROad 10fpImO4APwZkyYjpvzdLq3uTCyK3xvI/YAjbWqKv76rPt2ga6AklUamSoGmSs6PO5D8 CcjwWnCuXkrSjZFZT/wt/bf2GgrpPW0LEqeu/mG7QU+TASaZGeyv35DkKXcBPhWNvDW7 OCltDL0t6a5tEpcv0Vlppj6g0VC5u9KNGjHBBKUdCYP39AM1KwlWtnzu++iNdfuxvUpa pASQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299836; x=1683891836; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681300018176100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-24-richard.henderson@linaro.org> --- target/riscv/cpu_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9a2b944990..c7c384bae3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -962,14 +962,14 @@ restart: /* Reserved without Svpbmt. */ return TRANSLATE_FAIL; } - if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D PTE_W) { - /* Reserved leaf PTE flags: PTE_W */ - return TRANSLATE_FAIL; - } - if ((pte & (PTE_R | PTE_W | PTE_X)) =3D=3D (PTE_W | PTE_X)) { - /* Reserved leaf PTE flags: PTE_W + PTE_X */ + + /* Check for reserved combinations of RWX flags. */ + switch (pte & (PTE_R | PTE_W | PTE_X)) { + case PTE_W: + case PTE_W | PTE_X: return TRANSLATE_FAIL; } + if ((pte & PTE_U) && ((mode !=3D PRV_U) && (!sum || access_type =3D=3D MMU_INST_FETCH))= ) { /* --=20 2.34.1 From nobody Fri May 17 04:49:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1681300052; cv=none; d=zohomail.com; s=zohoarc; b=DbqcPJwyPcvvfim5KHA10rjvuslP3KnJ66gob70CxwMijqn4m45ctm5XMLxp+hW+ghezgkJrubmmgs+UdPhjNI9di26kkhCPIuTwTm/5SeDhp4a+Bur91lZNFv4OWOio/R8x13J00/bwF5Vm+1grsQCL+P+xJXunKTQIuXAoWUQ= ARC-Message-Signature: i=1; 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[37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299837; x=1683891837; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=M8HoEQ5oqUBzgSiPkg41KaPcHxMWLCXEpmxQRlUQgmQ=; b=nJzOtn/+ToFW+ybfxz8jOABM1E3vPQ8vyaeAoTbeRgrWMCEhinWPmUJNMK+tdZbeWZ Wq2WD8dWA/QCd1r/dsSZtbKlj8b4WBBZIdaHmm+Q0C1+Ud+nwzuzjj315NCyhoWOXAtl QUFi6Rs/Rt6pB56atBvvG76E9LWLbRSvz4tL6ZG9rJOf4hdWaIvoiNbM5MrDRmwAYsDj DUhygJWmP3MPUkOYyA0FgAHGw1g6OMH/QYrlYlzRzB2pScY7IpdSN/X2ZR0NWbs4AHXp rJhRx+4b00O118umgVvsMOWmY25p/CLB2CD7JuYOX/saT4o5O9T+ozvKN/9zDpAXyaDv WqCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299837; x=1683891837; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M8HoEQ5oqUBzgSiPkg41KaPcHxMWLCXEpmxQRlUQgmQ=; b=KQgORmg/S2ZxPvV2/QWYR8CvKIbnj92WVXrIQV4c4NVY5aObvIHu0VfCKB4EeKtH+1 3pE4eLmH2ezS9AlyVxY/Bi4js5ZYdsXSyWVTwbfoQY7/QFGCPsm8JkdWOaI88LqWEwS2 616/fMitHWhMxGnioM06IWZuM7RHbLaoXS2O5PAnxNI4MHmjbRz9WE2hKYsz8Q9K/pkU TQviAONKo5DLmm07CBlD685kgvwQrdJi+4fWNGMlPt5RZIRwRNphPxoo80WLFJpdSLFW 1WU8ucnCtgc9FfApYQld5vqH5/J0GHovzRbGV4Eco29MIpgxxc68uiKL20SsRhTpbMAW 67vw== X-Gm-Message-State: AAQBX9eq+Lda1Le0JAkkVtLWqHGeff95c1UN89RzpP+FDLczoLODUomP cb2xnBq8Fs/w4f24jC0aFuHKGljZV/Kx0ZKoaoQoQ29v X-Google-Smtp-Source: AKy350bbCMBW/Fi2D9zPMpA9V+S5yuLYM7WhQHJn0z0NXeJ2seEudb8LZZPEVemp3Lyh099kJ/QUIQ== X-Received: by 2002:adf:e441:0:b0:2e4:bfa0:8c30 with SMTP id t1-20020adfe441000000b002e4bfa08c30mr4769296wrm.47.1681299837424; Wed, 12 Apr 2023 04:43:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 24/25] target/riscv: Reorg access check in get_physical_address Date: Wed, 12 Apr 2023 13:43:32 +0200 Message-Id: <20230412114333.118895-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681300053969100009 Content-Type: text/plain; charset="utf-8" We were effectively computing the protection bits twice, once while performing access checks and once while returning the valid bits to the caller. Reorg so we do this once. Move the computation of mxr close to its single use. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-25-richard.henderson@linaro.org> --- target/riscv/cpu_helper.c | 69 ++++++++++++++++++++------------------- 1 file changed, 36 insertions(+), 33 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c7c384bae3..7849e18554 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -747,7 +747,7 @@ static int get_physical_address_pmp(CPURISCVState *env,= int *prot, * @is_debug: Is this access from a debugger or the monitor? */ static int get_physical_address(CPURISCVState *env, hwaddr *physical, - int *prot, vaddr addr, + int *ret_prot, vaddr addr, target_ulong *fault_pte_addr, int access_type, int mmu_idx, bool first_stage, bool two_stage, @@ -779,20 +779,14 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, =20 if (mode =3D=3D PRV_M || !riscv_cpu_cfg(env)->mmu) { *physical =3D addr; - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + *ret_prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TRANSLATE_SUCCESS; } =20 - *prot =3D 0; + *ret_prot =3D 0; =20 hwaddr base; - int levels, ptidxbits, ptesize, vm, sum, mxr, widened; - - if (first_stage =3D=3D true) { - mxr =3D get_field(env->mstatus, MSTATUS_MXR); - } else { - mxr =3D get_field(env->vsstatus, MSTATUS_MXR); - } + int levels, ptidxbits, ptesize, vm, sum, widened; =20 if (first_stage =3D=3D true) { if (use_background) { @@ -835,7 +829,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, levels =3D 5; ptidxbits =3D 9; ptesize =3D 8; break; case VM_1_10_MBARE: *physical =3D addr; - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + *ret_prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TRANSLATE_SUCCESS; default: g_assert_not_reached(); @@ -970,6 +964,27 @@ restart: return TRANSLATE_FAIL; } =20 + int prot =3D 0; + if (pte & PTE_R) { + prot |=3D PAGE_READ; + } + if (pte & PTE_W) { + prot |=3D PAGE_WRITE; + } + if (pte & PTE_X) { + bool mxr; + + if (first_stage =3D=3D true) { + mxr =3D get_field(env->mstatus, MSTATUS_MXR); + } else { + mxr =3D get_field(env->vsstatus, MSTATUS_MXR); + } + if (mxr) { + prot |=3D PAGE_READ; + } + prot |=3D PAGE_EXEC; + } + if ((pte & PTE_U) && ((mode !=3D PRV_U) && (!sum || access_type =3D=3D MMU_INST_FETCH))= ) { /* @@ -982,17 +997,9 @@ restart: /* Supervisor PTE flags when not S mode */ return TRANSLATE_FAIL; } - if (access_type =3D=3D MMU_DATA_LOAD && - !((pte & PTE_R) || ((pte & PTE_X) && mxr))) { - /* Read access check failed */ - return TRANSLATE_FAIL; - } - if (access_type =3D=3D MMU_DATA_STORE && !(pte & PTE_W)) { - /* Write access check failed */ - return TRANSLATE_FAIL; - } - if (access_type =3D=3D MMU_INST_FETCH && !(pte & PTE_X)) { - /* Fetch access check failed */ + + if (!((prot >> access_type) & 1)) { + /* Access check failed */ return TRANSLATE_FAIL; } =20 @@ -1057,20 +1064,16 @@ restart: (vpn & (((target_ulong)1 << ptshift) - 1)) ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); =20 - /* set permissions on the TLB entry */ - if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { - *prot |=3D PAGE_READ; - } - if (pte & PTE_X) { - *prot |=3D PAGE_EXEC; - } /* - * Add write permission on stores or if the page is already dirty, - * so that we TLB miss on later writes to update the dirty bit. + * Remove write permission unless this is a store, or the page is + * already dirty, so that we TLB miss on later writes to update + * the dirty bit. */ - if ((pte & PTE_W) && (access_type =3D=3D MMU_DATA_STORE || (pte & PTE_= D))) { - *prot |=3D PAGE_WRITE; + if (access_type !=3D MMU_DATA_STORE && !(pte & PTE_D)) { + prot &=3D ~PAGE_WRITE; } + *ret_prot =3D prot; + return TRANSLATE_SUCCESS; } =20 --=20 2.34.1 From nobody Fri May 17 04:49:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[37.24.10.236]) by smtp.gmail.com with ESMTPSA id k9-20020a5d4289000000b002d21379bcabsm16980826wrq.110.2023.04.12.04.43.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Apr 2023 04:43:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681299838; x=1683891838; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NoQh8yWVm3hAFzwy/qPB+auaAmUwei9hlZGr86CydxQ=; b=kt3E4SgZNmIZI+gaYwAzRQ8G1J/IB70YWIOS6Xe7xnUxDG8lkGx6VhPkGFaptJG5E/ YMme7EOKqeHOcWMJcKUT5hKe+aV/G/D+jKiDd3d+T+Su9jAIMjej7Cv8PC8umikoDGPz 36E+Pcjnmf9dvuwJ8ulyJSvzDcEs/8H+BiDEeP0gZjtzb6+iVVwnzS7xUwcFpdIVBTR9 lUA80wGv0sotcNnp05C3mgHI9Ec90WVUNi2jkbwsXNhXq1btYsjpqr80CDKkFOFK1haU C5pNjswMDesfg/FvNOced0WwXcjsFiQiyxtzCmVdC1JOHQ/CBj/DfRcY2hIL9k8MPf0j UVfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681299838; x=1683891838; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NoQh8yWVm3hAFzwy/qPB+auaAmUwei9hlZGr86CydxQ=; b=jVzC4oLT0j9LIpbZCa5a5e+HDiakXpBUxP1PzuedFWPIRn5/utcVdayrJ2+CetppZN S8H6bPZqCs022gT9kxDXFR3oh28j20WvG7+lISYS6ivsqRxcsNi9rLpuZDISN2VrG1FL 7VUoOjXXn3d+Xynq/4SoTdSP0HvzIZGBmu2RPJrKozVy8XcNA/VlYDgfMd1AK1FHe1DH 2p47536lDDb4oGjie5Rb0C2Fibzk/9ulrKaToYMkdSR/ZwWa1HLwP6gIRt6b09W9UaOx Mqg1b7JpWY8c30ga82h1ROxPZljZ/HdHUfFslybsKYP4UnqM9Z1iejZinbj23B/5QlMp hSjg== X-Gm-Message-State: AAQBX9d+kDlexAlsXS8hLKdhugegVHMTYkl9Dhp3FELAZxH06+tDvuml 52t+Rtl7CpOfd5Wwp1KX7+/OPACARY870SPmqsSqRw1p X-Google-Smtp-Source: AKy350bAWVGAYOxT+xcVUgwRtHS5FUJU5BapyJ0dBrOulkAQlTU6yRKZ2fO1OHCYS8tmRLdeDyY9RA== X-Received: by 2002:a5d:4846:0:b0:2ef:ba74:663 with SMTP id n6-20020a5d4846000000b002efba740663mr10594545wrs.27.1681299838379; Wed, 12 Apr 2023 04:43:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, qemu-riscv@nongnu.org, Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v7 25/25] target/riscv: Reorg sum check in get_physical_address Date: Wed, 12 Apr 2023 13:43:33 +0200 Message-Id: <20230412114333.118895-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230412114333.118895-1-richard.henderson@linaro.org> References: <20230412114333.118895-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681299889718100003 Content-Type: text/plain; charset="utf-8" Implement this by adjusting prot, which reduces the set of checks required. This prevents exec to be set for U pages in MMUIdx_S_SUM. While it had been technically incorrect, it did not manifest as a bug, because we will never attempt to execute from MMUIdx_S_SUM. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-26-richard.henderson@linaro.org> --- target/riscv/cpu_helper.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 7849e18554..32a65f8007 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -786,7 +786,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, *ret_prot =3D 0; =20 hwaddr base; - int levels, ptidxbits, ptesize, vm, sum, widened; + int levels, ptidxbits, ptesize, vm, widened; =20 if (first_stage =3D=3D true) { if (use_background) { @@ -817,7 +817,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, } widened =3D 2; } - sum =3D mmuidx_sum(mmu_idx); + switch (vm) { case VM_1_10_SV32: levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; @@ -985,15 +985,15 @@ restart: prot |=3D PAGE_EXEC; } =20 - if ((pte & PTE_U) && - ((mode !=3D PRV_U) && (!sum || access_type =3D=3D MMU_INST_FETCH))= ) { - /* - * User PTE flags when not U mode and mstatus.SUM is not set, - * or the access type is an instruction fetch. - */ - return TRANSLATE_FAIL; - } - if (!(pte & PTE_U) && (mode !=3D PRV_S)) { + if (pte & PTE_U) { + if (mode !=3D PRV_U) { + if (!mmuidx_sum(mmu_idx)) { + return TRANSLATE_FAIL; + } + /* SUM allows only read+write, not execute. */ + prot &=3D PAGE_READ | PAGE_WRITE; + } + } else if (mode !=3D PRV_S) { /* Supervisor PTE flags when not S mode */ return TRANSLATE_FAIL; } --=20 2.34.1