From nobody Fri May 17 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1681238161; cv=none; d=zohomail.com; s=zohoarc; b=bZIOEVEo6IErmIWokBzmaX9087q70SLKy77uAMUMBe7fKhfkDPubiCnKxr1kIaRNmY6T2lE0+ireMgcRs9Tj4WfQvMTyczTLEMXKlqo6tsX8sTk6VRjQ+hd5rS6r6GumuMl1DC8gibroI7lmkTxTFkp8IcHVpzQIpEfgg0QWOVk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681238161; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lmStwCNgSObqo+NH/HFqMIH32YeK18ZNbk6p/9FRX4Q=; b=Xax3TPVA4XUxILt8FGSaLaeMM5hLf/X0v38XNWitqabfWGi72XN5sB/N+NwCvr+YpF842c3nrRRb9ymV6LVszbv2c2gQY1amEN+gkiCqnJtxvN4M9fkOSvJpnuXaXoJcn2fYS6/FfMpVwdlT9FvijKqCdnTETt/0SKGY1fGFYAc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681238161880608.5451445739485; Tue, 11 Apr 2023 11:36:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pmIqC-0000IM-KQ; Tue, 11 Apr 2023 14:35:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pmIpy-0008Ms-KJ for qemu-devel@nongnu.org; Tue, 11 Apr 2023 14:35:27 -0400 Received: from mail-oo1-xc35.google.com ([2607:f8b0:4864:20::c35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pmIpu-0008EM-Go for qemu-devel@nongnu.org; Tue, 11 Apr 2023 14:35:24 -0400 Received: by mail-oo1-xc35.google.com with SMTP id s19-20020a4adb93000000b00540fa505f2dso4757701oou.7 for ; Tue, 11 Apr 2023 11:35:22 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id 4-20020a4a1404000000b005413e617935sm6149983ood.15.2023.04.11.11.35.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Apr 2023 11:35:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1681238121; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lmStwCNgSObqo+NH/HFqMIH32YeK18ZNbk6p/9FRX4Q=; b=nTELt2y4fABA+aSG8yMVnNni/Z9nVtOKICVH8gVc76Vs08azpMc/zKnaDvBtk8QYmx QQfzsLAYS4vIb9jYdY7YWl2QjQrqWetikyMiUNAUeOlvRhiQxZoJ1vqAYKMuDys5A2C2 9gRm9w/G5veEKVLP0uXJBJAVyF0CK1a+xTHT/mnW4CCGtfklh4VySXgrRpelFv8PQQ5N qoZJw6sXlLYBLmXry0bU7orubsMlpVQhgofOwBVLrH2TXdug4hJEzYrPcRb22LuO8EuX VYAkmNeGLIj12UNzGzD0Jb2chEj7Q43AP7EfOvCoG1BYNwXpdFmPYB3BBRfnSZAYVojR g7bQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681238121; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lmStwCNgSObqo+NH/HFqMIH32YeK18ZNbk6p/9FRX4Q=; b=ciCDXyga774q9ltape18yqzN004jXayfKgFGEq+G8mETPfpSzqwfLOOr7xkxhctTf2 QUXqaHgKwvnfCUQRDRVP3qPx9KIr7UdoxAwcd3kVfkO1dTy7SX97sR9/arUtqAmsWD3W Q5dV8a/eYirGNbdsWeA/Pq7Lk7M/5DrqPe0DA91VYe98P//bbX9fljZ+qozSd/Shm+Ih 4FminL94tiKnWB5fUURfeaqnfZeg/Jo2qJKTx+ICl6git61BwbqTioIrus8dEtvG1eP7 O7rhq+NnrIv8rufk+O3kkpGDMX3kxoPR+Vjwjpj7AKP7M9/NVL607AnbC8svrKATSzaL y+Rg== X-Gm-Message-State: AAQBX9dv7kID3egA353YK7+CAG8H38/5QlzTNnMOsfqodSRxDd41mRq/ bfWP/yjsje6FhQEN3++4r+uKlo6pk+4w20b1Kqs= X-Google-Smtp-Source: AKy350YqgzYa0PcMdH/FOoZ9jqHQn79i/Z50IJ2YBOh1OT1E8HCB2Q91HM8BQhVDQ/kKMtlnfH2Edw== X-Received: by 2002:a4a:330c:0:b0:517:9157:9480 with SMTP id q12-20020a4a330c000000b0051791579480mr7235680ooq.4.1681238120875; Tue, 11 Apr 2023 11:35:20 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, richard.henderson@linaro.org, Daniel Henrique Barboza Subject: [PATCH v3 1/3] target/riscv: add CPU QOM header Date: Tue, 11 Apr 2023 15:35:09 -0300 Message-Id: <20230411183511.189632-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230411183511.189632-1-dbarboza@ventanamicro.com> References: <20230411183511.189632-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c35; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681238163115100007 Content-Type: text/plain; charset="utf-8" QMP CPU commands are usually implemented by a separated file, -qmp-cmds.c, to allow them to be build only for softmmu targets. This file uses a CPU QOM header with basic QOM declarations for the arch. We'll introduce query-cpu-definitions for RISC-V CPUs in the next patch, but first we need a cpu-qom.h header with the definitions of TYPE_RISCV_CPU and RISCVCPUClass declarations. These were moved from cpu.h to the new file, and cpu.h now includes "cpu-qom.h". Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu-qom.h | 70 ++++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 46 +-------------------------- 2 files changed, 71 insertions(+), 45 deletions(-) create mode 100644 target/riscv/cpu-qom.h diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h new file mode 100644 index 0000000000..b9318e0783 --- /dev/null +++ b/target/riscv/cpu-qom.h @@ -0,0 +1,70 @@ +/* + * QEMU RISC-V CPU QOM header + * + * Copyright (c) 2023 Ventana Micro Systems Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef RISCV_CPU_QOM_H +#define RISCV_CPU_QOM_H + +#include "hw/core/cpu.h" +#include "qom/object.h" + +#define TYPE_RISCV_CPU "riscv-cpu" + +#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU +#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) +#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU + +#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") +#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") +#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") +#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") +#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") +#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") +#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") +#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") +#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") +#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") +#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") +#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") + +#if defined(TARGET_RISCV32) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 +#elif defined(TARGET_RISCV64) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 +#endif + +typedef struct CPUArchState CPURISCVState; + +OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) + +/** + * RISCVCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * + * A RISCV CPU model. + */ +struct RISCVCPUClass { + /*< private >*/ + CPUClass parent_class; + /*< public >*/ + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + +#endif /* RISCV_CPU_QOM_H */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 86e08d10da..fa2655306d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -28,6 +28,7 @@ #include "qemu/int128.h" #include "cpu_bits.h" #include "qapi/qapi-types-common.h" +#include "cpu-qom.h" =20 #define TCG_GUEST_DEFAULT_MO 0 =20 @@ -37,32 +38,6 @@ */ #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -#define TYPE_RISCV_CPU "riscv-cpu" - -#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU -#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) -#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU - -#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") -#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") -#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") -#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") -#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") -#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") -#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") -#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") -#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") -#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") -#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") -#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") -#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") - -#if defined(TARGET_RISCV32) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 -#elif defined(TARGET_RISCV64) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 -#endif - #define RV(x) ((target_ulong)1 << (x - 'A')) =20 /* Consider updating misa_ext_cfgs[] when adding new MISA bits here */ @@ -101,8 +76,6 @@ enum { =20 #define MAX_RISCV_PMPS (16) =20 -typedef struct CPUArchState CPURISCVState; - #if !defined(CONFIG_USER_ONLY) #include "pmp.h" #include "debug.h" @@ -387,23 +360,6 @@ struct CPUArchState { uint64_t kvm_timer_frequency; }; =20 -OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) - -/* - * RISCVCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * - * A RISCV CPU model. - */ -struct RISCVCPUClass { - /* < private > */ - CPUClass parent_class; - /* < public > */ - DeviceRealize parent_realize; - ResettablePhases parent_phases; -}; - /* * map is a 16-bit bitmap: the most significant set bit in map is the maxi= mum * satp mode that is supported. It may be chosen by the user and must resp= ect --=20 2.39.2 From nobody Fri May 17 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1681238198; cv=none; d=zohomail.com; s=zohoarc; b=g2JbYhkoJfzQvKQ4x4E1VzpftN5LJ8BQBALogJaiJIFoeKjLkfoHKkcrk3wPDCvTGiS4Va3b3PTsNMZxney8w4w9Vse/3MxT7bvB9N6vMWbVmt8B/ezm0WvaJBRx8u6xqc2iHGi+8X1QBcG0WKsIchdnWtL4v8QqwegWEOX0IgQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681238198; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LZ3mmOEkWa5eq/nwdQtgRGIfZCHeoxLG18jcmaPS/MY=; b=oGG/O6AZIp/p3ttWhNdlUoRoz5NodAK7BU0Ojs20nk2xZ1UaJfIMmCSfQs+W/1QsNnQXBgBicnIiOAsUsy52pAlns79NnchOrXCJX/oGqYC2GTTy0EMPoe9gQGTxW93zWGVvDHw2HdNwgUqjLC86hVHYv9Ny1+xGVZ6Qx/msbd4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681238198097890.163472650168; Tue, 11 Apr 2023 11:36:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pmIqT-0000lC-2D; Tue, 11 Apr 2023 14:35:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pmIq2-00006q-BC for qemu-devel@nongnu.org; Tue, 11 Apr 2023 14:35:36 -0400 Received: from mail-oo1-xc2f.google.com ([2607:f8b0:4864:20::c2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pmIpz-0008H1-4q for qemu-devel@nongnu.org; Tue, 11 Apr 2023 14:35:29 -0400 Received: by mail-oo1-xc2f.google.com with SMTP id j4-20020a4adf44000000b0053e8b5524abso5374692oou.2 for ; Tue, 11 Apr 2023 11:35:26 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id 4-20020a4a1404000000b005413e617935sm6149983ood.15.2023.04.11.11.35.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Apr 2023 11:35:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1681238125; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LZ3mmOEkWa5eq/nwdQtgRGIfZCHeoxLG18jcmaPS/MY=; b=eAcW+CTK85erdl/8DqPEdBTrCIr7JM1cDrgtGDITYD+VWagGpUBEEQ4e9lVntSOUE2 egG8ZsyOl3X5ZVZgZfkv6eyP9eIfGil+grCzbW6BwC5nR7NNOZiByA1KvcdzdFU8o/lU 985wZwNWvjO3R2Oz+Q5syKY+52rMGVxiTxB9kaTjJ29l1a1Z8Tf+XMkxkdpnV255K8jX XIzMTNrVJpFhF5v8GhGYv21sACPnmSlDfGGZ3OgwiUOCHrn/qPz70olYwAItjyb1pB86 8K9ui7K+J+1AIXn8UV7yeNRYo+1F8g4/EMAbWA4/ahuUClK22P965vliTd1r2R7uS2oi zv0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681238125; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LZ3mmOEkWa5eq/nwdQtgRGIfZCHeoxLG18jcmaPS/MY=; b=VF5+NzmrEs5ZBivboqp4/bNIp8ZNceTyxtWLCMP9Jzud6jAbVH4QI31+oUEcEaQv/4 bprZif6prLKT5q3HsRVsGFRM/9Kj6jrrwuca6G+pwwBQEIiQ8Hly9KYbYYmKNhCDRsNW UgtP3CIAX7/ZFkYS0GY0wdnjC+t1BgtX3Og4XTuTQRMZ7EtOVQKiPc0yfk/ct3GdEOcy aAiXjDxENraUzlVO4ceFMBRfaVybMKCena+yESozU1/CBmP2vaAAUg5UchN2zd9WT7q0 dC7K+h2Y3uczM2vr22K5X5CyawcybQvVChQz+GBroxqCIihasZgkOko4sBj7RTpqmeHm 8YqQ== X-Gm-Message-State: AAQBX9fCyjgClSheKbyyAtsYA87ky7qnX+JBS15NwMSMhi/bcUfo/LdP INe4yG/70YW0u/JSZ1u392TdVfvcYlsxTTQEYFU= X-Google-Smtp-Source: AKy350ZKPL2rG3/fCO9aJE7dShtWl2lR9Ax66hIljYsD+UJ9Yt8DZxaOMugHKUeHznGbU752y+hx4g== X-Received: by 2002:a4a:3387:0:b0:53b:6b36:2a9a with SMTP id q129-20020a4a3387000000b0053b6b362a9amr6033822ooq.8.1681238124082; Tue, 11 Apr 2023 11:35:24 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, richard.henderson@linaro.org, Daniel Henrique Barboza Subject: [PATCH v3 2/3] target/riscv: add query-cpy-definitions support Date: Tue, 11 Apr 2023 15:35:10 -0300 Message-Id: <20230411183511.189632-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230411183511.189632-1-dbarboza@ventanamicro.com> References: <20230411183511.189632-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681238199214100001 Content-Type: text/plain; charset="utf-8" This command is used by tooling like libvirt to retrieve a list of supported CPUs. Each entry returns a CpuDefinitionInfo object that contains more information about each CPU. This initial support includes only the name of the CPU and its typename. Here's what the command produces for the riscv64 target: $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio {"QMP": {"version": (...)} {"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}} {"return": {}} {"execute": "query-cpu-definitions"} {"return": [ {"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated= ": false}, {"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": false,= "deprecated": false}, {"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated":= false}, {"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "depr= ecated": false}, {"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": false, "de= precated": false}, {"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": false,= "deprecated": false}, {"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": false,= "deprecated": false}] } Next patch will introduce a way to tell whether a given CPU is static or not. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- qapi/machine-target.json | 6 ++-- target/riscv/meson.build | 3 +- target/riscv/riscv-qmp-cmds.c | 53 +++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+), 3 deletions(-) create mode 100644 target/riscv/riscv-qmp-cmds.c diff --git a/qapi/machine-target.json b/qapi/machine-target.json index 2e267fa458..f3a3de6648 100644 --- a/qapi/machine-target.json +++ b/qapi/machine-target.json @@ -324,7 +324,8 @@ 'TARGET_I386', 'TARGET_S390X', 'TARGET_MIPS', - 'TARGET_LOONGARCH64' ] } } + 'TARGET_LOONGARCH64', + 'TARGET_RISCV' ] } } =20 ## # @query-cpu-definitions: @@ -341,4 +342,5 @@ 'TARGET_I386', 'TARGET_S390X', 'TARGET_MIPS', - 'TARGET_LOONGARCH64' ] } } + 'TARGET_LOONGARCH64', + 'TARGET_RISCV' ] } } diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 5b7f813a3e..e1ff6d9b95 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -32,7 +32,8 @@ riscv_softmmu_ss.add(files( 'monitor.c', 'machine.c', 'pmu.c', - 'time_helper.c' + 'time_helper.c', + 'riscv-qmp-cmds.c', )) =20 target_arch +=3D {'riscv': riscv_ss} diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c new file mode 100644 index 0000000000..128677add9 --- /dev/null +++ b/target/riscv/riscv-qmp-cmds.c @@ -0,0 +1,53 @@ +/* + * QEMU CPU QMP commands for RISC-V + * + * Copyright (c) 2023 Ventana Micro Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" + +#include "qapi/qapi-commands-machine-target.h" +#include "cpu-qom.h" + +static void riscv_cpu_add_definition(gpointer data, gpointer user_data) +{ + ObjectClass *oc =3D data; + CpuDefinitionInfoList **cpu_list =3D user_data; + CpuDefinitionInfo *info =3D g_malloc0(sizeof(*info)); + const char *typename =3D object_class_get_name(oc); + + info->name =3D g_strndup(typename, + strlen(typename) - strlen("-" TYPE_RISCV_CPU)); + info->q_typename =3D g_strdup(typename); + + QAPI_LIST_PREPEND(*cpu_list, info); +} + +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +{ + CpuDefinitionInfoList *cpu_list =3D NULL; + GSList *list =3D object_class_get_list(TYPE_RISCV_CPU, false); + + g_slist_foreach(list, riscv_cpu_add_definition, &cpu_list); + g_slist_free(list); + + return cpu_list; +} --=20 2.39.2 From nobody Fri May 17 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1681238176; cv=none; d=zohomail.com; s=zohoarc; b=UVmFDGllcscGafL5UiWhwFVawUaC4C5RRs/9lMsfK+xguOJozgZCDTXquiTHkmQT98tO4xwWQRS4Bu2GV1lioepXW7vFLWtXE9cS06pqWhJHxZTDnM1BO02CL2gko9TpGAC6AfR6MCL9s0Q1S0Rv0a6giOWUAjNqX/gDdJg9eC4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681238176; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qEsTxGvLvsUaZXsQ/JW6z6RCxq/TKEsXbTivyDouRwQ=; b=P5P8hEj8cCc3hY+oOBZr9PgrdujpASso8eAhk0Rv5mQuxlYsATbqGBlHT9XOuLN04nXSOvdPWsdMpCAGZ1gB5O3CE3SWm9j8b4pqA3qZS17HwMPhr3NgCj45C4ii89KRdo+3NeLt/sqF/HmN80/iQNcrVHGlM+sUnGXh+LEBGhs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681238176631203.2383335838141; Tue, 11 Apr 2023 11:36:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pmIqU-0000vF-Dp; Tue, 11 Apr 2023 14:35:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pmIq3-0000Ej-QR for qemu-devel@nongnu.org; Tue, 11 Apr 2023 14:35:36 -0400 Received: from mail-oi1-x230.google.com ([2607:f8b0:4864:20::230]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pmIq1-0008HQ-TP for qemu-devel@nongnu.org; Tue, 11 Apr 2023 14:35:31 -0400 Received: by mail-oi1-x230.google.com with SMTP id bb20so1188781oib.12 for ; Tue, 11 Apr 2023 11:35:28 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id 4-20020a4a1404000000b005413e617935sm6149983ood.15.2023.04.11.11.35.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Apr 2023 11:35:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1681238127; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qEsTxGvLvsUaZXsQ/JW6z6RCxq/TKEsXbTivyDouRwQ=; b=J1zQJTTQhX5oEECV3T0YZI+Hyko57DxUmEUmu7Obd15YA0pO8h0dw+2J5Dt+9Bs4aG koGOU8/fRXwr5MLe30j7G1sXY9OkXBgs10NfNoR8RnE1JMEl4hc4XxLqXQNzTGHmUv5b QV50s8hU1kteKFqSTazMeXWQ+WNr+jzi070K8QDufsR152MXkCTyBTHPpqO3VGaai2De DWCKIFy7ObhrLl7tQLmAfG4HwryglRZT/PpRTqGfv3X6RCT+me4MSuPpF4XuuoUZ9OeJ QPHoFP59KquOK46IiwjI6bKWO+Ee+BzCF7akpRCCju/82vy4Htm4mxjpad4gjJZUqM6A KTSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681238127; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qEsTxGvLvsUaZXsQ/JW6z6RCxq/TKEsXbTivyDouRwQ=; b=OAiD6K76921yTI1XSS8Q1x/eZ/3A1V+5Hoyuci2abKg/JJbXuhNJZnIwaQ9NCVyGZK OrB7CDgNKrglO6YB3745HFqz9KE4IUlLM3F7p6EB6AAkLdHwbt2FBNMorANNTP64syAx e4pZ5dtxMEBntzi/I0rITVNAtBmxSBtTZbs7iArtNUngYvm5LYAa3wU+N5ZF8K6dlCon uoH2Gi63qLgmQXN/F7encHpzHR+eH8/lUR/ceoFEP0cJeeYBK/m94vjlCimnPR3BBpUG 5RP0bi9hVRZWFoReb6qbBHhTDv6gS9tlB3Hs9KBYCXbZ5uJLFrO6gzx0cTCxyx4dolrY VliA== X-Gm-Message-State: AAQBX9eCq2BM21HZ8fUMHHNdWjdshrf7i22o1HaCbchl6on1drbO9jTp OQDpOHOfXrzvoEZEsMGUSoJUMWeItyUVrhTFJ1M= X-Google-Smtp-Source: AKy350bVRkmc/kqmtqimEBbMaaTgddaN/izUdDY3kuaEXejrV1Pv0MIZM6s7URi5d+wO4p/B4u0T6g== X-Received: by 2002:a05:6808:1416:b0:389:7ffe:5059 with SMTP id w22-20020a056808141600b003897ffe5059mr1947978oiv.58.1681238127317; Tue, 11 Apr 2023 11:35:27 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, richard.henderson@linaro.org, Daniel Henrique Barboza Subject: [PATCH v3 3/3] target/riscv: add TYPE_RISCV_DYNAMIC_CPU Date: Tue, 11 Apr 2023 15:35:11 -0300 Message-Id: <20230411183511.189632-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230411183511.189632-1-dbarboza@ventanamicro.com> References: <20230411183511.189632-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681238178391100001 Content-Type: text/plain; charset="utf-8" This new abstract type will be used to differentiate between static and non-static CPUs in query-cpu-definitions. All generic CPUs were changed to be of this type. Named CPUs are kept as TYPE_RISCV_CPU and will still be considered static. This is the output of query-cpu-definitions after this change for the riscv64 target: $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio {"QMP": {"version": (...)} {"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}} {"return": {}} {"execute": "query-cpu-definitions"} {"return": [ {"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated= ": false}, {"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": true, = "deprecated": false}, {"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated":= false}, {"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "depr= ecated": false}, {"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": true, "dep= recated": false}, {"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": true, = "deprecated": false}, {"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": true, = "deprecated": false} ]} Suggested-by: Richard Henderson Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu-qom.h | 2 +- target/riscv/cpu.c | 20 ++++++++++++++++---- target/riscv/riscv-qmp-cmds.c | 4 ++++ 3 files changed, 21 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index b9318e0783..b29090ad86 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -23,6 +23,7 @@ #include "qom/object.h" =20 #define TYPE_RISCV_CPU "riscv-cpu" +#define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu" =20 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) @@ -66,5 +67,4 @@ struct RISCVCPUClass { DeviceRealize parent_realize; ResettablePhases parent_phases; }; - #endif /* RISCV_CPU_QOM_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fab38859ec..56f2b345cf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1788,6 +1788,13 @@ void riscv_cpu_list(void) .instance_init =3D initfn \ } =20 +#define DEFINE_DYNAMIC_CPU(type_name, initfn) \ + { \ + .name =3D type_name, \ + .parent =3D TYPE_RISCV_DYNAMIC_CPU, \ + .instance_init =3D initfn \ + } + static const TypeInfo riscv_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_CPU, @@ -1799,23 +1806,28 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .class_size =3D sizeof(RISCVCPUClass), .class_init =3D riscv_cpu_class_init, }, - DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), + { + .name =3D TYPE_RISCV_DYNAMIC_CPU, + .parent =3D TYPE_RISCV_CPU, + .abstract =3D true, + }, + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), #if defined(CONFIG_KVM) DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), #endif #if defined(TARGET_RISCV32) - DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init= ), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), #elif defined(TARGET_RISCV64) - DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), #endif }; =20 diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c index 128677add9..5ecff1afb3 100644 --- a/target/riscv/riscv-qmp-cmds.c +++ b/target/riscv/riscv-qmp-cmds.c @@ -33,11 +33,15 @@ static void riscv_cpu_add_definition(gpointer data, gpo= inter user_data) CpuDefinitionInfoList **cpu_list =3D user_data; CpuDefinitionInfo *info =3D g_malloc0(sizeof(*info)); const char *typename =3D object_class_get_name(oc); + ObjectClass *dyn_class; =20 info->name =3D g_strndup(typename, strlen(typename) - strlen("-" TYPE_RISCV_CPU)); info->q_typename =3D g_strdup(typename); =20 + dyn_class =3D object_class_dynamic_cast(oc, TYPE_RISCV_DYNAMIC_CPU); + info->q_static =3D dyn_class =3D=3D NULL; + QAPI_LIST_PREPEND(*cpu_list, info); } =20 --=20 2.39.2