From nobody Fri May 17 10:34:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681203834988914.0556026820191; Tue, 11 Apr 2023 02:03:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pm9u7-0004Qr-IZ; Tue, 11 Apr 2023 05:03:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pm9u1-0004QY-Gs; Tue, 11 Apr 2023 05:03:01 -0400 Received: from bg4.exmail.qq.com ([43.154.221.58]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pm9ty-0005Oj-Sz; Tue, 11 Apr 2023 05:03:01 -0400 Received: from pek-vx-bsp2.wrs.com ( [60.247.85.88]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 11 Apr 2023 17:02:11 +0800 (CST) X-QQ-mid: bizesmtp90t1681203743t0ap21fw X-QQ-SSF: 01200000000000D0F000000A0000000 X-QQ-FEAT: cy+SGFpNa8duaVCl5WNrH/sW0Sn8KWt+x+a4B58qA8ieBl997q2AcKrs3YV+9 ZqXALJMrxHyOJuOu6FeK7WGf2u/rngm8MQEeeb1Ib1OcRgZbuSutzgwfYg9coI6HHEWUUFy gFl0nI+Jyqx5OL3gBS33JlSu9S+Fjw7ExwDuDlUzinqHygonktylmpn3kt4lqshskXkpdB9 NnnHp7dupGqCvqzBwDSsIa1LOSHip9GwQ7GoK2gbbA6ksb1eJfT6xQToi7u3uQ80J+zT4fT q7QxPUXMHvTP/oo4+DGjnGvpq52EBzLRc2PUsafClYSMiNrj9Lih9Z0ET9TBrtylGlhu8k7 1jENfE5BiccVWvcrsw= X-QQ-GoodBg: 0 X-BIZMAIL-ID: 17000592329357289727 From: Bin Meng To: Alistair Francis , Daniel Henrique Barboza , Liu Zhiwei , Weiwei Li , Palmer Dabbelt Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Fei Wu Subject: [PATCH] target/riscv: Restore the predicate() NULL check behavior Date: Tue, 11 Apr 2023 17:02:11 +0800 Message-Id: <20230411090211.3039186-1-bmeng@tinylab.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:tinylab.org:qybglogicsvrgz:qybglogicsvrgz7a-0 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=43.154.221.58; envelope-from=bmeng@tinylab.org; helo=bg4.exmail.qq.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1681203836525100001 Content-Type: text/plain; charset="utf-8" When reading a non-existent CSR QEMU should raise illegal instruction exception, but currently it just exits due to the g_assert() check. This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617, Some comments are also added to indicate that predicate() must be provided for an implemented CSR. Reported-by: Fei Wu Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li --- target/riscv/csr.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d522efc0b6..736ab64275 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3797,6 +3797,11 @@ static inline RISCVException riscv_csrrw_check(CPURI= SCVState *env, return RISCV_EXCP_ILLEGAL_INST; } =20 + /* ensure CSR is implemented by checking predicate */ + if (!csr_ops[csrno].predicate) { + return RISCV_EXCP_ILLEGAL_INST; + } + /* privileged spec version check */ if (env->priv_ver < csr_min_priv) { return RISCV_EXCP_ILLEGAL_INST; @@ -3814,7 +3819,6 @@ static inline RISCVException riscv_csrrw_check(CPURIS= CVState *env, * illegal instruction exception should be triggered instead of virtual * instruction exception. Hence this comes after the read / write chec= k. */ - g_assert(csr_ops[csrno].predicate !=3D NULL); RISCVException ret =3D csr_ops[csrno].predicate(env, csrno); if (ret !=3D RISCV_EXCP_NONE) { return ret; @@ -3991,7 +3995,10 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env,= int csrno, return ret; } =20 -/* Control and Status Register function table */ +/* + * Control and Status Register function table + * riscv_csr_operations::predicate() must be provided for an implemented C= SR + */ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* User Floating-Point CSRs */ [CSR_FFLAGS] =3D { "fflags", fs, read_fflags, write_fflags }, --=20 2.25.1