From nobody Fri May 17 05:54:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=kernel.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681149066981152.06689754960223; Mon, 10 Apr 2023 10:51:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1plvec-00022f-Di; Mon, 10 Apr 2023 13:50:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1plveW-00021d-N2 for qemu-devel@nongnu.org; Mon, 10 Apr 2023 13:50:05 -0400 Received: from mail-ej1-f47.google.com ([209.85.218.47]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1plveT-0002EA-Ha for qemu-devel@nongnu.org; Mon, 10 Apr 2023 13:50:03 -0400 Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-94a34a0fc1dso141920666b.1 for ; Mon, 10 Apr 2023 10:50:01 -0700 (PDT) Received: from localhost.localdomain (aftr-82-135-86-174.dynamic.mnet-online.de. [82.135.86.174]) by smtp.googlemail.com with ESMTPSA id n19-20020a509353000000b005002daeb27asm5129282eda.37.2023.04.10.10.49.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 10:49:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681149000; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pibcdHZFVT8rJ8Zk2e4zwoqg5iti1gNkPEmP94VKqjE=; b=IDUlz9wG4dNDgI5h74dAbpipCGqIASwNYnfkKuDTJ6NBEdazTJMw8wKtThp4tZJJZw e8+yo4lHXeVdhqqwsYSH/6wKqdq/lOOUH2wVdEk5Ti8xIcEhKGZffp8c9yw9ZeOfa/gu uLZjlVOFCEfqV5OaVAcNBnLPX8tMtN3FZs+7kwOpEocUKaQWay4WXd+YQmJvoUVmrVfP kekZDCyuVvs4ucUT77WQEEt72hUnVAy2HNR9bWbVUcKLt4cTDcYNqBPddrhecb/ZepAk 3+WDct8Ac+PSS5t0d24cYr6G4C5bX58mvLgL9eJ0nqVhl0YeNr8xFixdvm5D9Hoss4kZ vc0A== X-Gm-Message-State: AAQBX9coHhH6igntu6y4htGzlXuaXo2m8foJBw1Hg9sodGe85ANgAAEp 1iDVJten+wYO4hkJ/DUeYAECoTF6nMwjuPxr X-Google-Smtp-Source: AKy350bsbzcYaD3NeTULAXt8XpePkgjftb1UL+jMEysWAeS35AjmjbCqrC48SYlre7q/npyYtcnwNw== X-Received: by 2002:aa7:dd16:0:b0:504:b2a6:7bfe with SMTP id i22-20020aa7dd16000000b00504b2a67bfemr1595601edv.23.1681148999951; Mon, 10 Apr 2023 10:49:59 -0700 (PDT) From: Johannes Thumshirn To: qemu-devel@nongnu.org Cc: Alistair Francis , Javier Rodriguez , =?UTF-8?q?Jorge=20Sanjuan=20Garc=C3=ADa?= , Peter Maydell , Dmitry Fomichev , Johannes Thumshirn , Alistair Francis Subject: [PATCH v3 1/4] Add MEN Chameleon Bus emulation Date: Mon, 10 Apr 2023 19:49:07 +0200 Message-Id: <20230410174910.4806-2-jth@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410174910.4806-1-jth@kernel.org> References: <20230410174910.4806-1-jth@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=209.85.218.47; envelope-from=morbidrsa@gmail.com; helo=mail-ej1-f47.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1681149067501100001 Content-Type: text/plain; charset="utf-8" The MEN Chameleon Bus (MCB) is an on-chip bus system exposing IP Cores of an FPGA to a outside bus system like PCIe. Acked-by: Alistair Francis Signed-off-by: Johannes Thumshirn --- MAINTAINERS | 6 ++ hw/Kconfig | 1 + hw/mcb/Kconfig | 2 + hw/mcb/mcb.c | 182 +++++++++++++++++++++++++++++++++++++++++++ hw/mcb/meson.build | 1 + hw/meson.build | 1 + include/hw/mcb/mcb.h | 106 +++++++++++++++++++++++++ 7 files changed, 299 insertions(+) create mode 100644 hw/mcb/Kconfig create mode 100644 hw/mcb/mcb.c create mode 100644 hw/mcb/meson.build create mode 100644 include/hw/mcb/mcb.h diff --git a/MAINTAINERS b/MAINTAINERS index 98cb2d64cf..badec8abdd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1947,6 +1947,12 @@ R: Paolo Bonzini S: Odd Fixes F: hw/char/ =20 +MEN Chameleon Bus +M: Johannes Thumshirn +S: Maintained +F: hw/mcb/ +F: include/hw/mcb/ + Network devices M: Jason Wang S: Odd Fixes diff --git a/hw/Kconfig b/hw/Kconfig index ba62ff6417..f5ef84b10b 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -18,6 +18,7 @@ source intc/Kconfig source ipack/Kconfig source ipmi/Kconfig source isa/Kconfig +source mcb/Kconfig source mem/Kconfig source misc/Kconfig source net/Kconfig diff --git a/hw/mcb/Kconfig b/hw/mcb/Kconfig new file mode 100644 index 0000000000..36a7a583a8 --- /dev/null +++ b/hw/mcb/Kconfig @@ -0,0 +1,2 @@ +config MCB + bool diff --git a/hw/mcb/mcb.c b/hw/mcb/mcb.c new file mode 100644 index 0000000000..8322a2b791 --- /dev/null +++ b/hw/mcb/mcb.c @@ -0,0 +1,182 @@ +/* + * QEMU MEN Chameleon Bus emulation + * + * Copyright (C) 2023 Johannes Thumshirn + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/module.h" +#include "hw/mcb/mcb.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" + +ChameleonDeviceDescriptor *mcb_new_chameleon_descriptor(MCBus *bus, uint8_= t id, + uint8_t rev, + uint8_t var, + uint32_t size) +{ + BusChild *kid; + ChameleonDeviceDescriptor *gdd; + uint32_t reg1 =3D 0; + uint32_t offset =3D 0x200; + uint32_t end =3D 0; + + gdd =3D g_new0(ChameleonDeviceDescriptor, 1); + if (!gdd) { + return NULL; + } + + reg1 |=3D GDD_DEV(id); + reg1 |=3D GDD_DTY(CHAMELEON_DTYPE_GENERAL); + reg1 |=3D GDD_REV(rev); + reg1 |=3D GDD_VAR(var); + gdd->reg1 =3D cpu_to_le32(reg1); + + QTAILQ_FOREACH(kid, &BUS(bus)->children, sibling) { + DeviceState *qdev =3D kid->child; + MCBDevice *mdev =3D MCB_DEVICE(qdev); + + if (mdev->gdd) { + offset =3D mdev->gdd->offset; + end =3D offset + mdev->gdd->size; + } + } + + gdd->offset =3D offset + end; + gdd->size =3D size; + + return gdd; +} + +static void mcb_irq_handler(void *opaque, int irq_num, int level) +{ + MCBDevice *dev =3D opaque; + MCBus *bus =3D MCB_BUS(qdev_get_parent_bus(DEVICE(dev))); + + if (bus->set_irq) { + bus->set_irq(dev, irq_num, level); + } +} + +qemu_irq mcb_allocate_irq(MCBDevice *dev) +{ + int irq =3D 0; + return qemu_allocate_irq(mcb_irq_handler, dev, irq); +} + +MCBDevice *mcb_device_find(MCBus *bus, hwaddr addr) +{ + BusChild *kid; + uint32_t start; + uint32_t end; + + QTAILQ_FOREACH(kid, &BUS(bus)->children, sibling) { + DeviceState *qdev =3D kid->child; + MCBDevice *mdev =3D MCB_DEVICE(qdev); + + start =3D mdev->gdd->offset; + end =3D start + mdev->gdd->size; + + if (addr >=3D start && addr <=3D end) { + return mdev; + } + } + return NULL; +} + +void mcb_bus_init(MCBus *bus, size_t bus_size, + DeviceState *parent, + uint8_t n_slots, + qemu_irq_handler handler) +{ + qbus_init(bus, bus_size, TYPE_MCB_BUS, parent, NULL); + bus->n_slots =3D n_slots; + bus->set_irq =3D handler; +} + +static void mcb_device_realize(DeviceState *dev, Error **errp) +{ + MCBDevice *mdev =3D MCB_DEVICE(dev); + MCBus *bus =3D MCB_BUS(qdev_get_parent_bus(dev)); + MCBDeviceClass *k =3D MCB_DEVICE_GET_CLASS(dev); + + if (mdev->slot < 0) { + mdev->slot =3D bus->free_slot; + } + + if (mdev->slot >=3D bus->n_slots) { + error_setg(errp, "Only %" PRIu8 " slots available.", bus->n_slots); + return; + } + bus->free_slot =3D mdev->slot + 1; + + mdev->irq =3D qemu_allocate_irqs(bus->set_irq, mdev, 1); + + k->realize(dev, errp); +} + +static void mcb_device_unrealize(DeviceState *dev) +{ + MCBDevice *mdev =3D MCB_DEVICE(dev); + MCBDeviceClass *k =3D MCB_DEVICE_GET_CLASS(dev); + + if (k->unrealize) { + k->unrealize(dev); + return; + } + + qemu_free_irqs(mdev->irq, 1); +} + +static Property mcb_device_props[] =3D { + DEFINE_PROP_INT32("slot", MCBDevice, slot, -1), + DEFINE_PROP_END_OF_LIST() +}; + +static void mcb_device_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *k =3D DEVICE_CLASS(klass); + + set_bit(DEVICE_CATEGORY_INPUT, k->categories); + k->bus_type =3D TYPE_MCB_BUS; + k->realize =3D mcb_device_realize; + k->unrealize =3D mcb_device_unrealize; + device_class_set_props(k, mcb_device_props); +} + +const VMStateDescription vmstate_mcb_device =3D { + .name =3D "mcb_device", + .version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_INT32(slot, MCBDevice), + VMSTATE_END_OF_LIST() + } +}; + +static const TypeInfo mcb_device_info =3D { + .name =3D TYPE_MCB_DEVICE, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(MCBDevice), + .class_size =3D sizeof(MCBDeviceClass), + .class_init =3D mcb_device_class_init, + .abstract =3D true, +}; + +static const TypeInfo mcb_bus_info =3D { + .name =3D TYPE_MCB_BUS, + .parent =3D TYPE_BUS, + .instance_size =3D sizeof(MCBus), +}; + +static void mcb_register_types(void) +{ + type_register_static(&mcb_device_info); + type_register_static(&mcb_bus_info); +} + +type_init(mcb_register_types); diff --git a/hw/mcb/meson.build b/hw/mcb/meson.build new file mode 100644 index 0000000000..a385edc07c --- /dev/null +++ b/hw/mcb/meson.build @@ -0,0 +1 @@ +softmmu_ss.add(when: 'CONFIG_MCB', if_true: files('mcb.c')) diff --git a/hw/meson.build b/hw/meson.build index c7ac7d3d75..3d1462ad8b 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -18,6 +18,7 @@ subdir('intc') subdir('ipack') subdir('ipmi') subdir('isa') +subdir('mcb') subdir('mem') subdir('misc') subdir('net') diff --git a/include/hw/mcb/mcb.h b/include/hw/mcb/mcb.h new file mode 100644 index 0000000000..03d7e12ad2 --- /dev/null +++ b/include/hw/mcb/mcb.h @@ -0,0 +1,106 @@ +/* + * QEMU MEN Chameleon Bus emulation + * + * Copyright (C) 2023 Johannes Thumshirn + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + */ + +#ifndef QEMU_MCB_H +#define QEMU_MCB_H + +#include "hw/qdev-core.h" +#include "qom/object.h" +#include "exec/memory.h" + +#define CHAMELEON_DTYPE_GENERAL 0x0 +#define CHAMELEON_DTYPE_END 0xf + +typedef struct { + uint32_t reg1; + uint32_t reg2; + uint32_t offset; + uint32_t size; +} ChameleonDeviceDescriptor; + +#define GDD_DEV(x) (((x) & 0x3ff) << 18) +#define GDD_DTY(x) (((x) & 0xf) << 28) +#define GDD_REV(x) (((x) & 0x3f) << 5) +#define GDD_VAR(x) (((x) & 0x3f) << 11) + +/* GDD Register 1 fields */ +#define GDD_IRQ(x) ((x) & 0x1f) + +/* GDD Register 2 fields */ +#define GDD_BAR(x) ((x) & 0x7) +#define GDD_INS(x) (((x) >> 3) & 0x3f) +#define GDD_GRP(x) (((x) >> 9) & 0x3f) + +typedef struct MCBus MCBus; + +#define TYPE_MCB_BUS "MEN Chameleon Bus" +OBJECT_DECLARE_SIMPLE_TYPE(MCBus, MCB_BUS) + +struct MCBus { + /*< private >*/ + BusState parent_obj; + + uint8_t n_slots; + uint8_t free_slot; + qemu_irq_handler set_irq; + MemoryRegion mmio_region; +}; + +typedef struct MCBDevice MCBDevice; +typedef struct MCBDeviceClass MCBDeviceClass; + +#define TYPE_MCB_DEVICE "mcb-device" +#define MCB_DEVICE(obj) \ + OBJECT_CHECK(MCBDevice, (obj), TYPE_MCB_DEVICE) +#define MCB_DEVICE_CLASS(klass) \ + OBJECT_CLASS_CHECK(MCBDeviceClass, (klass), TYPE_MCB_DEVICE) +#define MCB_DEVICE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(MCBDeviceClass, (obj), TYPE_MCB_DEVICE) + +struct MCBDeviceClass { + /*< private >*/ + DeviceClass parent_class; + /*< public >*/ + + + DeviceRealize realize; + DeviceUnrealize unrealize; +}; + +struct MCBDevice { + /*< private >*/ + DeviceState parent_obj; + /*< public >*/ + + qemu_irq *irq; + ChameleonDeviceDescriptor *gdd; + int slot; + + uint8_t rev; + uint8_t var; +}; + +extern const VMStateDescription vmstate_mcb_device; + +ChameleonDeviceDescriptor *mcb_new_chameleon_descriptor(MCBus *bus, uint8_= t id, + uint8_t rev, + uint8_t var, + uint32_t size); + +#define VMSTATE_MCB_DEVICE(_field, _state) \ + VMSTATE_STRUCT(_field, _state, 1, vmstate_mcb_device, MCBDevice) + +MCBDevice *mcb_device_find(MCBus *bus, hwaddr addr); +void mcb_bus_init(MCBus *bus, size_t bus_size, + DeviceState *parent, + uint8_t n_slots, + qemu_irq_handler handler); + +qemu_irq mcb_allocate_irq(MCBDevice *dev); +#endif --=20 2.39.2 From nobody Fri May 17 05:54:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=kernel.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681149080345925.6014715567059; Mon, 10 Apr 2023 10:51:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1plved-00023r-0o; Mon, 10 Apr 2023 13:50:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1plveX-00021i-FW for qemu-devel@nongnu.org; Mon, 10 Apr 2023 13:50:05 -0400 Received: from mail-ed1-f50.google.com ([209.85.208.50]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1plveV-0002EN-31 for qemu-devel@nongnu.org; Mon, 10 Apr 2023 13:50:04 -0400 Received: by mail-ed1-f50.google.com with SMTP id 4fb4d7f45d1cf-50489acccdfso1371741a12.1 for ; Mon, 10 Apr 2023 10:50:02 -0700 (PDT) Received: from localhost.localdomain (aftr-82-135-86-174.dynamic.mnet-online.de. [82.135.86.174]) by smtp.googlemail.com with ESMTPSA id n19-20020a509353000000b005002daeb27asm5129282eda.37.2023.04.10.10.50.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 10:50:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681149001; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+jb7ryK3VqNFA6tSClMkrHqVatLxl4Q4pq+0cLxYBnE=; b=UY1bwBVCiYGrYghyvhWAehzZwQJuus/k0UZUeq1xIRQ/D+AlTDMqPOsdasmr4g76wd oFqvLq1feV9zvRfGjn7rG1ZK+T64PAP/Rn3eN+ODddWqh05jjsLjZTIo01GM2stJxU+H hBJKwnE/iX/JRYhBIJqglj9+0JC0my5zUADKrXDu3AYEmF1/LGtx4WkhEKgOq49OfOhR DXvvCiTFIlOvfHgt3/n/S/k8Gs7pc9kp2SbvguU0K/Jn4b7Z67akUqUTWpLvfjIf5Zsx lc4AV0uDfQdU2lOjeFfxTcgH07ex6izf8XSTRhno8ueDGJNCjp08jQUMYIH1yiP13OGi d8Pg== X-Gm-Message-State: AAQBX9ek/1iGrygGT6ZzA4w8RxVU1EsXaKGBeEnz8u3+SG38j+hfiJ3p qcb7DEi/UbuU1OLyLiYYxhXMUmfsxGy0RvrP X-Google-Smtp-Source: AKy350bZEa02IOdciH9+aarhLZxjB3NuvC4A0hD0Ks+8brjtkRE9NFB4T0I2KnbaSllmLFfExQfisQ== X-Received: by 2002:aa7:d8c7:0:b0:504:91ca:5da3 with SMTP id k7-20020aa7d8c7000000b0050491ca5da3mr5883158eds.22.1681149000907; Mon, 10 Apr 2023 10:50:00 -0700 (PDT) From: Johannes Thumshirn To: qemu-devel@nongnu.org Cc: Alistair Francis , Javier Rodriguez , =?UTF-8?q?Jorge=20Sanjuan=20Garc=C3=ADa?= , Peter Maydell , Dmitry Fomichev , Johannes Thumshirn Subject: [PATCH v3 2/4] Add MEN Chameleon Bus via PCI carrier Date: Mon, 10 Apr 2023 19:49:08 +0200 Message-Id: <20230410174910.4806-3-jth@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410174910.4806-1-jth@kernel.org> References: <20230410174910.4806-1-jth@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=209.85.208.50; envelope-from=morbidrsa@gmail.com; helo=mail-ed1-f50.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1681149080902100001 Content-Type: text/plain; charset="utf-8" Add PCI based MEN Chameleon Bus carrier emulation. Signed-off-by: Johannes Thumshirn Acked-by: Alistair Francis --- hw/mcb/Kconfig | 6 + hw/mcb/mcb-pci.c | 297 ++++++++++++++++++++++++++++++++++++++++++++ hw/mcb/meson.build | 1 + hw/mcb/trace-events | 3 + hw/mcb/trace.h | 1 + meson.build | 1 + 6 files changed, 309 insertions(+) create mode 100644 hw/mcb/mcb-pci.c create mode 100644 hw/mcb/trace-events create mode 100644 hw/mcb/trace.h diff --git a/hw/mcb/Kconfig b/hw/mcb/Kconfig index 36a7a583a8..7deb96c2fe 100644 --- a/hw/mcb/Kconfig +++ b/hw/mcb/Kconfig @@ -1,2 +1,8 @@ config MCB bool + +config MCB_PCI + bool + default y if PCI_DEVICES + depends on PCI + select MCB diff --git a/hw/mcb/mcb-pci.c b/hw/mcb/mcb-pci.c new file mode 100644 index 0000000000..516f133c2e --- /dev/null +++ b/hw/mcb/mcb-pci.c @@ -0,0 +1,297 @@ +/* + * QEMU MEN Chameleon Bus emulation + * + * Copyright (C) 2023 Johannes Thumshirn + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/mcb/mcb.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_device.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" +#include "trace.h" + +typedef struct { + uint8_t revision; + char model; + uint8_t minor; + uint8_t bus_type; + uint16_t magic; + uint16_t reserved; + /* This one has no '\0' at the end!!! */ + char filename[12]; +} ChameleonFPGAHeader; +#define CHAMELEON_BUS_TYPE_WISHBONE 0 +#define CHAMELEONV2_MAGIC 0xabce + +typedef struct { + PCIDevice dev; + MCBus bus; + MemoryRegion ctbl; + uint16_t status; + uint8_t int_set; + ChameleonFPGAHeader *header; + + uint8_t minor; + uint8_t rev; + uint8_t model; +} MPCIState; + +#define TYPE_MCB_PCI "mcb-pci" + +#define MPCI(obj) \ + OBJECT_CHECK(MPCIState, (obj), TYPE_MCB_PCI) + +#define CHAMELEON_TABLE_SIZE 0x200 +#define N_MODULES 32 + +#define PCI_VENDOR_ID_MEN 0x1a88 +#define PCI_DEVICE_ID_MEN_MCBPCI 0x4d45 + +static uint32_t read_header(MPCIState *s, hwaddr addr) +{ + uint32_t ret =3D 0; + ChameleonFPGAHeader *header =3D s->header; + + switch (addr >> 2) { + case 0: + ret |=3D header->revision; + ret |=3D header->model << 8; + ret |=3D header->minor << 16; + ret |=3D header->bus_type << 24; + break; + case 1: + ret |=3D header->magic; + ret |=3D header->reserved << 16; + break; + case 2: + memcpy(&ret, header->filename, sizeof(uint32_t)); + break; + case 3: + memcpy(&ret, header->filename + sizeof(uint32_t), + sizeof(uint32_t)); + break; + case 4: + memcpy(&ret, header->filename + 2 * sizeof(uint32_t), + sizeof(uint32_t)); + } + + return ret; +} + +static uint32_t read_gdd(MCBDevice *mdev, int reg) +{ + ChameleonDeviceDescriptor *gdd; + uint32_t ret =3D 0; + + gdd =3D mdev->gdd; + + switch (reg) { + case 0: + ret =3D gdd->reg1; + break; + case 1: + ret =3D gdd->reg2; + break; + case 2: + ret =3D gdd->offset; + break; + case 3: + ret =3D gdd->size; + break; + } + + return ret; +} + +static uint64_t mpci_chamtbl_read(void *opaque, hwaddr addr, unsigned size) +{ + MPCIState *s =3D opaque; + MCBus *bus =3D &s->bus; + MCBDevice *mdev; + + trace_mpci_chamtbl_read(addr, size); + + if (addr < sizeof(ChameleonFPGAHeader)) { + return le32_to_cpu(read_header(s, addr)); + } else if (addr >=3D sizeof(ChameleonFPGAHeader) && + addr < CHAMELEON_TABLE_SIZE) { + /* Handle read on chameleon table */ + BusChild *kid; + DeviceState *qdev; + int slot; + int offset; + int i; + + offset =3D addr - sizeof(ChameleonFPGAHeader); + slot =3D offset / sizeof(ChameleonDeviceDescriptor); + + kid =3D QTAILQ_FIRST(&BUS(bus)->children); + for (i =3D 0; i < slot; i++) { + kid =3D QTAILQ_NEXT(kid, sibling); + if (!kid) { /* Last element */ + return ~0U; + } + } + qdev =3D kid->child; + mdev =3D MCB_DEVICE(qdev); + offset -=3D slot * 16; + + return le32_to_cpu(read_gdd(mdev, offset / 4)); + } + + return 0; +} + +static void mpci_chamtbl_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + + if (addr < CHAMELEON_TABLE_SIZE) { + trace_mpci_chamtbl_write(addr, val); + } + + return; +} + +static const MemoryRegionOps mpci_chamtbl_ops =3D { + .read =3D mpci_chamtbl_read, + .write =3D mpci_chamtbl_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + }, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + }, +}; + +static void mcb_pci_set_irq(void *opaque, int intno, int level) +{ + MCBDevice *mdev =3D opaque; + MCBus *bus =3D MCB_BUS(qdev_get_parent_bus(DEVICE(mdev))); + PCIDevice *pcidev =3D PCI_DEVICE(BUS(bus)->parent); + MPCIState *dev =3D MPCI(pcidev); + + if (level) { + pci_set_irq(&dev->dev, !dev->int_set); + pci_set_irq(&dev->dev, dev->int_set); + } else { + uint16_t level_status =3D dev->status; + + if (level_status && !dev->int_set) { + pci_irq_assert(&dev->dev); + dev->int_set =3D 1; + } else if (!level_status && dev->int_set) { + pci_irq_deassert(&dev->dev); + dev->int_set =3D 0; + } + } +} + +static void mcb_pci_write_config(PCIDevice *pci_dev, uint32_t address, + uint32_t val, int len) +{ + pci_default_write_config(pci_dev, address, val, len); +} + +static void mcb_pci_realize(PCIDevice *pci_dev, Error **errp) +{ + MPCIState *s =3D MPCI(pci_dev); + uint8_t *pci_conf =3D s->dev.config; + ChameleonFPGAHeader *header; + MCBus *bus =3D &s->bus; + + header =3D g_new0(ChameleonFPGAHeader, 1); + + s->header =3D header; + + header->revision =3D s->rev; + header->model =3D (char) s->model; + header->minor =3D s->minor; + header->bus_type =3D CHAMELEON_BUS_TYPE_WISHBONE; + header->magic =3D CHAMELEONV2_MAGIC; + memcpy(&header->filename, "QEMU MCB PCI", 12); + + pci_dev->config_write =3D mcb_pci_write_config; + pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 0x01); /* Interrupt pin A */ + pci_conf[PCI_COMMAND] =3D PCI_COMMAND_MEMORY; + + mcb_bus_init(bus, sizeof(MCBus), DEVICE(pci_dev), N_MODULES, + mcb_pci_set_irq); + + memory_region_init(&bus->mmio_region, OBJECT(s), "mcb-pci.mmio", + 2048 * 1024); + memory_region_init_io(&s->ctbl, OBJECT(s), &mpci_chamtbl_ops, + s, "mpci_chamtbl_ops", CHAMELEON_TABLE_SIZE); + memory_region_add_subregion(&bus->mmio_region, 0, &s->ctbl); + pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, + &bus->mmio_region); + +} + +static void mcb_pci_unrealize(PCIDevice *pci_dev) +{ + MPCIState *s =3D MPCI(pci_dev); + + g_free(s->header); + s->header =3D NULL; +} + +static const VMStateDescription vmstate_mcb_pci =3D { + .name =3D "mcb-pci", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_PCI_DEVICE(dev, MPCIState), + VMSTATE_END_OF_LIST() + } +}; + +static Property mcb_pci_props[] =3D { + DEFINE_PROP_UINT8("revision", MPCIState, rev, 1), + DEFINE_PROP_UINT8("minor", MPCIState, minor, 0), + DEFINE_PROP_UINT8("model", MPCIState, model, 0x41), + DEFINE_PROP_END_OF_LIST(), +}; + +static void mcb_pci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + k->realize =3D mcb_pci_realize; + k->exit =3D mcb_pci_unrealize; + k->vendor_id =3D PCI_VENDOR_ID_MEN; + k->device_id =3D PCI_DEVICE_ID_MEN_MCBPCI; + k->class_id =3D PCI_CLASS_BRIDGE_OTHER; + + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + dc->desc =3D "MEN Chameleon Bus over PCI"; + dc->vmsd =3D &vmstate_mcb_pci; + device_class_set_props(dc, mcb_pci_props); +} + +static const TypeInfo mcb_pci_info =3D { + .name =3D TYPE_MCB_PCI, + .parent =3D TYPE_PCI_DEVICE, + .instance_size =3D sizeof(MPCIState), + .class_init =3D mcb_pci_class_init, + .interfaces =3D (InterfaceInfo[]) { + { INTERFACE_PCIE_DEVICE }, + { } + }, +}; + +static void mcb_pci_register_types(void) +{ + type_register(&mcb_pci_info); +} +type_init(mcb_pci_register_types); diff --git a/hw/mcb/meson.build b/hw/mcb/meson.build index a385edc07c..4e1a0f0cdb 100644 --- a/hw/mcb/meson.build +++ b/hw/mcb/meson.build @@ -1 +1,2 @@ softmmu_ss.add(when: 'CONFIG_MCB', if_true: files('mcb.c')) +softmmu_ss.add(when: 'CONFIG_MCB_PCI', if_true: files('mcb-pci.c')) diff --git a/hw/mcb/trace-events b/hw/mcb/trace-events new file mode 100644 index 0000000000..e1adf9c8e3 --- /dev/null +++ b/hw/mcb/trace-events @@ -0,0 +1,3 @@ +# mcb-pci.c +mpci_chamtbl_read(unsigned long addr, unsigned int size) "read from addres= s 0x%lx size %d" +mpci_chamtbl_write(unsigned long addr, uint64_t val) "invalid write to 0x%= lx: 0x%" PRIx64 diff --git a/hw/mcb/trace.h b/hw/mcb/trace.h new file mode 100644 index 0000000000..35653b3381 --- /dev/null +++ b/hw/mcb/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_mcb.h" diff --git a/meson.build b/meson.build index 29f8644d6d..ff8305440b 100644 --- a/meson.build +++ b/meson.build @@ -2986,6 +2986,7 @@ if have_system 'hw/input', 'hw/intc', 'hw/isa', + 'hw/mcb', 'hw/mem', 'hw/mips', 'hw/misc', --=20 2.39.2 From nobody Fri May 17 05:54:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[82.135.86.174]) by smtp.googlemail.com with ESMTPSA id n19-20020a509353000000b005002daeb27asm5129282eda.37.2023.04.10.10.50.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 10:50:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681149002; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FE6Q2IcdC4/dlJSljQioDP6Jf5qnL+b5tpnHVTBSVH0=; b=gtsAAQvOAsU5AtTUySVLcTtwkx/pfJ51JEmd065Y+rjxqTXamPRk7H0qSUMkcMlHxF 0LsCGIckC15VNoaUGO47qvdTYtwSW5E2nC9vGH45IcoAtQhu2kliY3Dc9GHZ2XB8GLos rR3JdWY7CrfKJWed6gQqfdPQWQgeVu/l3ELeWomq17xepme7OQvhUiwkKARb+bNAwZD5 RR7XJxAA+rq74TNCQ1WOldpBGMap/tI/ndexNwYs03DXbTnVvOnEKFGL51FDwzLdXS/D bXxQzHCFCOTt2fo7WTrb4qRLuLhajG7oetpcTaHB2iJO7dKX1JHuhj3phlPFwVzUlpdy d05A== X-Gm-Message-State: AAQBX9dGugpUjzQ0dbrL2EzGYHt1q+Wn1rdUx9M7FWh1kQa/PBwQnFH+ OnieYVBON5ba1OXdhIrP/SclPhNZH7AAbpdu X-Google-Smtp-Source: AKy350apXbUKNiim/ghCp/M+r57HCrL7GY+VQtZIhLEutJt1BTQOTrPQ1RTHmzzXfqc+QIyg6JTmLg== X-Received: by 2002:a05:6402:344f:b0:504:8173:6240 with SMTP id l15-20020a056402344f00b0050481736240mr5688408edc.37.1681149002108; Mon, 10 Apr 2023 10:50:02 -0700 (PDT) From: Johannes Thumshirn To: qemu-devel@nongnu.org Cc: Alistair Francis , Javier Rodriguez , =?UTF-8?q?Jorge=20Sanjuan=20Garc=C3=ADa?= , Peter Maydell , Dmitry Fomichev , Johannes Thumshirn , Alistair Francis Subject: [PATCH v3 3/4] serial-mcb: Add serial via MEN chameleon bus Date: Mon, 10 Apr 2023 19:49:09 +0200 Message-Id: <20230410174910.4806-4-jth@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410174910.4806-1-jth@kernel.org> References: <20230410174910.4806-1-jth@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=209.85.208.48; envelope-from=morbidrsa@gmail.com; helo=mail-ed1-f48.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1681149060183100003 Content-Type: text/plain; charset="utf-8" Add MEN z125 UART over MEN Chameleon Bus emulation. Acked-by: Alistair Francis Signed-off-by: Johannes Thumshirn --- hw/char/Kconfig | 6 +++ hw/char/meson.build | 1 + hw/char/serial-mcb.c | 115 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 122 insertions(+) create mode 100644 hw/char/serial-mcb.c diff --git a/hw/char/Kconfig b/hw/char/Kconfig index 6b6cf2fc1d..9e8ebf1d3d 100644 --- a/hw/char/Kconfig +++ b/hw/char/Kconfig @@ -71,3 +71,9 @@ config GOLDFISH_TTY =20 config SHAKTI_UART bool + +config SERIAL_MCB + bool + default y if MCB + depends on MCB + select SERIAL diff --git a/hw/char/meson.build b/hw/char/meson.build index e02c60dd54..d5893a142d 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -20,6 +20,7 @@ softmmu_ss.add(when: 'CONFIG_SHAKTI_UART', if_true: files= ('shakti_uart.c')) softmmu_ss.add(when: 'CONFIG_VIRTIO_SERIAL', if_true: files('virtio-consol= e.c')) softmmu_ss.add(when: 'CONFIG_XEN_BUS', if_true: files('xen_console.c')) softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_uartlite.c')) +softmmu_ss.add(when: 'CONFIG_SERIAL_MCB', if_true: files('serial-mcb.c')) =20 softmmu_ss.add(when: 'CONFIG_AVR_USART', if_true: files('avr_usart.c')) softmmu_ss.add(when: 'CONFIG_COLDFIRE', if_true: files('mcf_uart.c')) diff --git a/hw/char/serial-mcb.c b/hw/char/serial-mcb.c new file mode 100644 index 0000000000..09f8fec11e --- /dev/null +++ b/hw/char/serial-mcb.c @@ -0,0 +1,115 @@ +/* + * QEMU MEN 16z125 UART over MCB emulation + * + * Copyright (C) 2023 Johannes Thumshirn + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/module.h" +#include "hw/char/serial.h" +#include "hw/mcb/mcb.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" +#include "migration/vmstate.h" + +struct MCBSerialState { + MCBDevice dev; + SerialState state; +}; + +#define TYPE_MCB_SERIAL "mcb-serial" +OBJECT_DECLARE_SIMPLE_TYPE(MCBSerialState, MCB_SERIAL) + +static void serial_mcb_realize(DeviceState *dev, Error **errp) +{ + MCBDevice *mdev =3D MCB_DEVICE(dev); + MCBSerialState *mss =3D DO_UPCAST(MCBSerialState, dev, mdev); + MCBus *bus =3D MCB_BUS(qdev_get_parent_bus(DEVICE(dev))); + SerialState *s =3D &mss->state; + + mdev->gdd =3D mcb_new_chameleon_descriptor(bus, 125, mdev->rev, + mdev->var, 0x10); + if (!mdev->gdd) { + return; + } + + s->baudbase =3D 115200; + if (!qdev_realize(DEVICE(s), NULL, errp)) { + return; + } + + s->irq =3D mcb_allocate_irq(&mss->dev); + memory_region_init_io(&s->io, OBJECT(mss), &serial_io_ops, s, "serial"= , 8); + memory_region_add_subregion(&bus->mmio_region, mdev->gdd->offset, &s->= io); +} + +static void serial_mcb_unrealize(DeviceState *dev) +{ + MCBDevice *mdev =3D MCB_DEVICE(dev); + MCBSerialState *mss =3D DO_UPCAST(MCBSerialState, dev, mdev); + SerialState *s =3D &mss->state; + + qdev_unrealize(DEVICE(s)); + qemu_free_irq(s->irq); + g_free(&mdev->gdd); +} + +static const VMStateDescription vmstate_mcb_serial =3D { + .name =3D "mcb-serial", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_MCB_DEVICE(dev, MCBSerialState), + VMSTATE_STRUCT(state, MCBSerialState, 0, vmstate_serial, SerialSta= te), + VMSTATE_END_OF_LIST() + } +}; + +static Property serial_mcb_properties[] =3D { + DEFINE_PROP_UINT8("rev", MCBSerialState, dev.rev, 0), + DEFINE_PROP_UINT8("var", MCBSerialState, dev.var, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void serial_mcb_class_initfn(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + MCBDeviceClass *mc =3D MCB_DEVICE_CLASS(klass); + + mc->realize =3D serial_mcb_realize; + mc->unrealize =3D serial_mcb_unrealize; + + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); + dc->desc =3D "MEN 16z125 UART over MCB"; + dc->vmsd =3D &vmstate_mcb_serial; + device_class_set_props(dc, serial_mcb_properties); +} + +static void serial_mcb_init(Object *o) +{ + MCBSerialState *mss =3D MCB_SERIAL(o); + + object_initialize_child(o, "serial", &mss->state, TYPE_SERIAL); + + qdev_alias_all_properties(DEVICE(&mss->state), o); +} + +static const TypeInfo serial_mcb_info =3D { + .name =3D "mcb-serial", + .parent =3D TYPE_MCB_DEVICE, + .instance_size =3D sizeof(MCBSerialState), + .instance_init =3D serial_mcb_init, + .class_init =3D serial_mcb_class_initfn, +}; + +static void serial_mcb_register_types(void) +{ + type_register_static(&serial_mcb_info); +} + +type_init(serial_mcb_register_types); --=20 2.39.2 From nobody Fri May 17 05:54:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=kernel.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681149055183770.817439923524; Mon, 10 Apr 2023 10:50:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1plveh-00027J-A1; Mon, 10 Apr 2023 13:50:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1plveY-00022R-Nn for qemu-devel@nongnu.org; Mon, 10 Apr 2023 13:50:10 -0400 Received: from mail-ej1-f47.google.com ([209.85.218.47]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1plveW-0002NG-O8 for qemu-devel@nongnu.org; Mon, 10 Apr 2023 13:50:06 -0400 Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-94a34a0b9e2so104304666b.1 for ; Mon, 10 Apr 2023 10:50:04 -0700 (PDT) Received: from localhost.localdomain (aftr-82-135-86-174.dynamic.mnet-online.de. [82.135.86.174]) by smtp.googlemail.com with ESMTPSA id n19-20020a509353000000b005002daeb27asm5129282eda.37.2023.04.10.10.50.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 10:50:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681149003; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kmJdS+UNWtRGRmUQMkJm593ZKkMfzAjPRmYbqbhhPew=; b=6uIcME+X59ilSbc3qf3lYZZSx5+f5mVy3V6oNwEldGndxh3k6wsoxkItQxwtBDOE8i 8pIw4DKA5gUXb94p1Ae+aFUu+3bSmg9T43QU1UXFuadKgZVhPtJPMlbcsvQz3NJi9HIm 9bwcsgTHMtLxuWkflvGiOQaMuMCl2rY3LwuXp09QnjixfyK2UENAlhduWTyeh8xg331s a376TcamkWejb0ZQhijMxXPTPSPMOBQ1bz1EAfbKR5fmUDSjPOXky8eHB49pyeWWyH4/ t31pXu/bdY15NGRBX+RP7DjuAKrHsr0zc3EeuMOjg+I2sTd4xf9mQdnSq85b9WXzKtL0 HGZQ== X-Gm-Message-State: AAQBX9eG4XhcJp424H5N1AdG6FEAOiCVhJFd7ZrOxmyQAJth3923iN51 F39di4LUBMeTtB4elO4933gxoayc5MiOqo6/ X-Google-Smtp-Source: AKy350ZlVsrg5MkyY5ZOYNQ30QCYyeuwUgVM9Q6aXlPEpDUqpFQhqWSBQGa6L23cwkU16EPPOz4ZdQ== X-Received: by 2002:a05:6402:12c9:b0:4a0:e305:a0de with SMTP id k9-20020a05640212c900b004a0e305a0demr12059550edx.19.1681149003218; Mon, 10 Apr 2023 10:50:03 -0700 (PDT) From: Johannes Thumshirn To: qemu-devel@nongnu.org Cc: Alistair Francis , Javier Rodriguez , =?UTF-8?q?Jorge=20Sanjuan=20Garc=C3=ADa?= , Peter Maydell , Dmitry Fomichev , Johannes Thumshirn Subject: [PATCH v3 4/4] wdt_z069: Add support for MEN 16z069 Watchdog Date: Mon, 10 Apr 2023 19:49:10 +0200 Message-Id: <20230410174910.4806-5-jth@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410174910.4806-1-jth@kernel.org> References: <20230410174910.4806-1-jth@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=209.85.218.47; envelope-from=morbidrsa@gmail.com; helo=mail-ej1-f47.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1681149057213100001 Content-Type: text/plain; charset="utf-8" Add 16z069 Watchdog over MEN Chameleon BUS emulation. Signed-off-by: Johannes Thumshirn --- hw/watchdog/Kconfig | 5 + hw/watchdog/meson.build | 1 + hw/watchdog/wdt_z069.c | 218 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 224 insertions(+) create mode 100644 hw/watchdog/wdt_z069.c diff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig index 66e1d029e3..a3f1196f66 100644 --- a/hw/watchdog/Kconfig +++ b/hw/watchdog/Kconfig @@ -20,3 +20,8 @@ config WDT_IMX2 =20 config WDT_SBSA bool + +config WDT_Z069 + bool + default y if MCB + depends on MCB diff --git a/hw/watchdog/meson.build b/hw/watchdog/meson.build index 8974b5cf4c..7bc353774e 100644 --- a/hw/watchdog/meson.build +++ b/hw/watchdog/meson.build @@ -6,4 +6,5 @@ softmmu_ss.add(when: 'CONFIG_WDT_DIAG288', if_true: files('= wdt_diag288.c')) softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('wdt_aspeed.c')) softmmu_ss.add(when: 'CONFIG_WDT_IMX2', if_true: files('wdt_imx2.c')) softmmu_ss.add(when: 'CONFIG_WDT_SBSA', if_true: files('sbsa_gwdt.c')) +softmmu_ss.add(when: 'CONFIG_WDT_Z069', if_true: files('wdt_z069.c')) specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_watchdog.c')) diff --git a/hw/watchdog/wdt_z069.c b/hw/watchdog/wdt_z069.c new file mode 100644 index 0000000000..b20ceab532 --- /dev/null +++ b/hw/watchdog/wdt_z069.c @@ -0,0 +1,218 @@ +/* + * QEMU MEN 16z069 Watchdog over MCB emulation + * + * Copyright (C) 2023 Johannes Thumshirn + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + */ +#include "qemu/osdep.h" +#include "qemu/module.h" +#include "qemu/timer.h" +#include "sysemu/watchdog.h" +#include "hw/mcb/mcb.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" + +/* #define Z069_DEBUG 1 */ + +#ifdef Z069_DEBUG +#define z069_debug(fmt, ...) \ + fprintf(stderr, "wdt_z069: %s: "fmt, __func__, ##__VA_ARGS__) +#else +#define z069_debug(fmt, ...) +#endif + +#define MEN_Z069_WTR 0x10 +#define MEN_Z069_WTR_WDEN BIT(15) +#define MEN_Z069_WTR_WDET_MASK 0x7fff +#define MEN_Z069_WVR 0x14 + +#define CLK_500(x) ((x) * 2) /* 500Hz in ms */ + +typedef struct { + /*< private >*/ + MCBDevice dev; + + /*< public >*/ + QEMUTimer *timer; + + bool enabled; + unsigned int timeout; + + MemoryRegion mmio; + + /* Registers */ + uint16_t wtr; + uint16_t wvr; +} MENZ069State; + +static void men_z069_wdt_enable(MENZ069State *s) +{ + z069_debug("next timeout will fire in +%dms\n", s->timeout); + timer_mod(s->timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->timeout= ); +} + +static void men_z069_wdt_disable(MENZ069State *s) +{ + timer_del(s->timer); +} + +static uint64_t men_z069_wdt_read(void *opaque, hwaddr addr, unsigned size) +{ + MENZ069State *s =3D opaque; + uint64_t ret; + + switch (addr) { + case MEN_Z069_WTR: + ret =3D s->wtr; + break; + case MEN_Z069_WVR: + ret =3D s->wvr; + break; + default: + ret =3D 0UL; + break; + } + + z069_debug("returning: 0x%"PRIx64" @ 0x%lx\n", ret, addr); + return ret; +} + +static void men_z069_wdt_write(void *opaque, hwaddr addr, uint64_t v, + unsigned size) +{ + MENZ069State *s =3D opaque; + bool old_ena =3D s->enabled; + uint16_t val =3D v & 0xffff; + uint16_t tout; + + z069_debug("got: 0x%"PRIx64" @ 0x%lx\n", v, addr); + + switch (addr) { + case MEN_Z069_WTR: + s->wtr =3D val; + tout =3D val & MEN_Z069_WTR_WDET_MASK; + s->timeout =3D CLK_500(tout); + s->enabled =3D val & MEN_Z069_WTR_WDEN; + z069_debug("new timeout: %u (0x%x) %u\n", tout, tout, s->timeout); + + if (old_ena && !s->enabled) { + men_z069_wdt_disable(s); + } else if (!old_ena && s->enabled) { + men_z069_wdt_enable(s); + } + + break; + case MEN_Z069_WVR: + /* The watchdog trigger value toggles between 0x5555 and 0xaaaa */ + if (val =3D=3D (s->wvr ^ 0xffff)) { + s->wvr =3D val; + z069_debug("watchdog triggered, next timeout will fire in +%dm= s\n", + s->timeout); + timer_mod(s->timer, + qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + s->timeout); + } + break; + default: + break; + } + return; +} + +static const MemoryRegionOps men_z069_io_ops =3D { + .read =3D men_z069_wdt_read, + .write =3D men_z069_wdt_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + }, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + }, +}; + +static void men_z069_timer_expired(void *opaque) +{ + MENZ069State *s =3D opaque; + + watchdog_perform_action(); + timer_del(s->timer); +} + +static void men_z069_wdt_realize(DeviceState *dev, Error **errp) +{ + MCBDevice *mdev =3D MCB_DEVICE(dev); + MENZ069State *s =3D DO_UPCAST(MENZ069State, dev, mdev); + MCBus *bus =3D MCB_BUS(qdev_get_parent_bus(DEVICE(dev))); + + mdev->gdd =3D mcb_new_chameleon_descriptor(bus, 69, mdev->rev, + mdev->var, 0x18); + if (!mdev->gdd) { + return; + } + + s->wvr =3D 0x5555; + s->wtr =3D 0x7fff; + s->timeout =3D CLK_500(s->wtr & MEN_Z069_WTR_WDET_MASK); + s->timer =3D timer_new_ms(QEMU_CLOCK_VIRTUAL, + men_z069_timer_expired, s); + + memory_region_init_io(&s->mmio, OBJECT(s), + &men_z069_io_ops, s, "z069.wdt", 0x16); + memory_region_add_subregion(&bus->mmio_region, mdev->gdd->offset, + &s->mmio); +} + +static void men_z069_wdt_unrealize(DeviceState *dev) +{ + MCBDevice *mdev =3D MCB_DEVICE(dev); + + g_free(&mdev->gdd); +} + +static const VMStateDescription vmstate_z069_wdt =3D { + .name =3D "z069-wdt", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_MCB_DEVICE(dev, MENZ069State), + VMSTATE_TIMER_PTR(timer, MENZ069State), + VMSTATE_END_OF_LIST() + } +}; + +static Property men_z069_wdt_properties[] =3D { + DEFINE_PROP_UINT8("rev", MENZ069State, dev.rev, 0), + DEFINE_PROP_UINT8("var", MENZ069State, dev.var, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void men_z069_wdt_class_intifn(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + MCBDeviceClass *mc =3D MCB_DEVICE_CLASS(klass); + + mc->realize =3D men_z069_wdt_realize; + mc->unrealize =3D men_z069_wdt_unrealize; + + dc->desc =3D "MEN 16z069 Watchdog Timer"; + dc->vmsd =3D &vmstate_z069_wdt; + device_class_set_props(dc, men_z069_wdt_properties); +} + +static const TypeInfo men_z069_wdt_info =3D { + .name =3D "z069-wdt", + .parent =3D TYPE_MCB_DEVICE, + .instance_size =3D sizeof(MENZ069State), + .class_init =3D men_z069_wdt_class_intifn, +}; + +static void men_z069_wdt_register_types(void) +{ + type_register_static(&men_z069_wdt_info); +} + +type_init(men_z069_wdt_register_types); --=20 2.39.2