From nobody Fri May 17 05:54:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1681145668; cv=none; d=zohomail.com; s=zohoarc; b=nz7rmxXsEoy8l8UsG2wI5MgyLX1jlfrDoz4cmVl8HTzP+djWAiqywOHM3EWgSkQJ98ds3SR8Ny2L8fg6dYjjv9HEJc8auBBdlcB5iP/OmqOu2fUBCi9mTtdqK01wZBWBRdK5SxZDqeVrWbNE9Vz8b+tlmNSt1lVRGwtq2kUIU9s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681145668; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7f97QPiu1Fd+OM3S7vziX0p5A2QzwngIPHhNMODXrEY=; b=cD+QZVFOoz3xistnsPq66S9jeGjIUlJLzOp1r5xizKAxfAWfnReCQzoz9CiOMkYPlMAL+HeESL6yyNhWil2jkQXWHRzhhNXQf/s8sNn2ppOJAKM+i6cEBZvxXEBRgT9XTWhbh7jh1Txyi2mC4Z11QeTknc69rPYDFsRB5iXvSEQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681145668582582.8171535635886; Mon, 10 Apr 2023 09:54:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1plulP-0003m6-0r; Mon, 10 Apr 2023 12:53:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1plulN-0003kH-FR for qemu-devel@nongnu.org; Mon, 10 Apr 2023 12:53:05 -0400 Received: from mail-oa1-x2b.google.com ([2001:4860:4864:20::2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1plulL-0007Kq-K2 for qemu-devel@nongnu.org; Mon, 10 Apr 2023 12:53:05 -0400 Received: by mail-oa1-x2b.google.com with SMTP id 586e51a60fabf-1842d8976d9so6707373fac.9 for ; Mon, 10 Apr 2023 09:53:03 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id zq36-20020a0568718ea400b0017f647294f5sm4191896oab.16.2023.04.10.09.52.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 09:53:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1681145582; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7f97QPiu1Fd+OM3S7vziX0p5A2QzwngIPHhNMODXrEY=; b=l9INqYBFLZyPzMeDTQOk6gz63K1Wi/MHuYpxW1lEAe4dsqf8jFftiVmFuTJzRdAbqQ Um7K2kCS62Y3eu9ElC4mAolpTLqr07WvA/TPBHtU7Rj1z0f3/t4G8jP0MgpaRfD8aIgN SGasgdURy+xBA5KnRFGWtT7pwcGOK2QfkYcZo7CYbSM6aQbPj6PafPf6M8NV7zJ7zP52 ZeMGmLUfYAr4x5Vr44igk4U18qDybIkQZsVWQN5RqdkhBn7Aao5EM6dkdIO5zoIZigok 5qIXodMXQeuwK2t5h6GadGfcz7sesGltu+HMIp7BnchIgcKqWtDVLeZyx2nTC7P42xt0 U9Kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681145582; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7f97QPiu1Fd+OM3S7vziX0p5A2QzwngIPHhNMODXrEY=; b=4Pj3yEPKOOWDBlRNe/brd85EXBeQj4Fqnn2ad46lJpbYsh/qDMTLAe0gLOjLVpju9G CNXO5dwSmx9603kkQOZhC6R+4sAJzC7Yz0V667C+Sxyu5B3ihDKZbOXzqjTekSZfZtLC QFZNoq1mOZT12E5xws2DvJgUQbMiq1+vGemEfD77dCCH+Y3anxza5LLjk7qo74/3GUez scI0EH8kfgyMB/0V5d7vznck2HkClK1gxz59+rC+jleSe1pEQltLincoWZNuTW7Nsc4Q 3joysaZozZYv9EWI0oBv1U/FCho1bF9I3otqVm9uVODAMVOG/GbJbGE5f5DqwYHGVTVw LYTg== X-Gm-Message-State: AAQBX9caNcZETDJ9p/N/Nv1CKhxBfnm9IThVxB/Zvd2FYxwQVb7a6o9U Us5dw68D+YSvtzjijDjd/Tc3Uo4TnB48wo6wOQA= X-Google-Smtp-Source: AKy350YOHCSpNQv7O37Je/6stb+fB+u8KvhN6BbYRpbNaDiBTFHXG9NvZcQGyLqmqO4S13+3Nkn4Cg== X-Received: by 2002:a05:6870:5583:b0:176:317d:16ee with SMTP id n3-20020a056870558300b00176317d16eemr6683501oao.19.1681145582143; Mon, 10 Apr 2023 09:53:02 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v2 1/4] target/riscv: add CPU QOM header Date: Mon, 10 Apr 2023 13:52:48 -0300 Message-Id: <20230410165251.99107-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410165251.99107-1-dbarboza@ventanamicro.com> References: <20230410165251.99107-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681145670705100001 Content-Type: text/plain; charset="utf-8" QMP CPU commands are usually implemented by a separated file, -qmp-cmds.c, to allow them to be build only for softmmu targets. This file uses a CPU QOM header with basic QOM declarations for the arch. We'll introduce query-cpu-definitions for RISC-V CPUs in the next patch, but first we need a cpu-qom.h header with the definitions of TYPE_RISCV_CPU and RISCVCPUClass declarations. These were moved from cpu.h to the new file, and cpu.h now includes "cpu-qom.h". Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson --- target/riscv/cpu-qom.h | 70 ++++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 46 +-------------------------- 2 files changed, 71 insertions(+), 45 deletions(-) create mode 100644 target/riscv/cpu-qom.h diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h new file mode 100644 index 0000000000..b9318e0783 --- /dev/null +++ b/target/riscv/cpu-qom.h @@ -0,0 +1,70 @@ +/* + * QEMU RISC-V CPU QOM header + * + * Copyright (c) 2023 Ventana Micro Systems Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef RISCV_CPU_QOM_H +#define RISCV_CPU_QOM_H + +#include "hw/core/cpu.h" +#include "qom/object.h" + +#define TYPE_RISCV_CPU "riscv-cpu" + +#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU +#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) +#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU + +#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") +#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") +#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") +#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") +#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") +#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") +#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") +#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") +#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") +#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") +#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") +#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") + +#if defined(TARGET_RISCV32) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 +#elif defined(TARGET_RISCV64) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 +#endif + +typedef struct CPUArchState CPURISCVState; + +OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) + +/** + * RISCVCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * + * A RISCV CPU model. + */ +struct RISCVCPUClass { + /*< private >*/ + CPUClass parent_class; + /*< public >*/ + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + +#endif /* RISCV_CPU_QOM_H */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cbf3de2708..d830a64713 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -28,6 +28,7 @@ #include "qemu/int128.h" #include "cpu_bits.h" #include "qapi/qapi-types-common.h" +#include "cpu-qom.h" =20 #define TCG_GUEST_DEFAULT_MO 0 =20 @@ -37,32 +38,6 @@ */ #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -#define TYPE_RISCV_CPU "riscv-cpu" - -#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU -#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) -#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU - -#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") -#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") -#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") -#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") -#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") -#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") -#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") -#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") -#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") -#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") -#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") -#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") -#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") - -#if defined(TARGET_RISCV32) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 -#elif defined(TARGET_RISCV64) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 -#endif - #define RV(x) ((target_ulong)1 << (x - 'A')) =20 /* @@ -103,8 +78,6 @@ enum { =20 #define MAX_RISCV_PMPS (16) =20 -typedef struct CPUArchState CPURISCVState; - #if !defined(CONFIG_USER_ONLY) #include "pmp.h" #include "debug.h" @@ -389,23 +362,6 @@ struct CPUArchState { uint64_t kvm_timer_frequency; }; =20 -OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) - -/* - * RISCVCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * - * A RISCV CPU model. - */ -struct RISCVCPUClass { - /* < private > */ - CPUClass parent_class; - /* < public > */ - DeviceRealize parent_realize; - ResettablePhases parent_phases; -}; - /* * map is a 16-bit bitmap: the most significant set bit in map is the maxi= mum * satp mode that is supported. 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([191.255.108.232]) by smtp.gmail.com with ESMTPSA id zq36-20020a0568718ea400b0017f647294f5sm4191896oab.16.2023.04.10.09.53.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 09:53:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1681145585; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+SKXBRJdA9KUw/4IAA9R3X/vHCTMNddy95IWzacAV94=; b=DCuMzgtaV6/8YryveBOUnWhRhzOgPiP8dxPz+OTKeNuoM7P7R4gS8b5L6yW1UCZSQY s1syP1u9GShinaYVfY2IYR5E7SXrgWJ1W4Ls+9TwQZS5RmmS+kbGphkfWiu7uTj1qX7y x9caTRslTuCV453yEnf29QvKP+P69GGZV6+vC29TQuelAor2M+QZN73T7LB8SMK5AVU4 3tLjYCro1JJZ9B0/4+6zQ6JZ0cP2oj9PxkvE+l/+rT3QRU6coWXDuUAVtg2WWNBLESj+ 5YCcLPtltme2j3znwWQra2DvDww64v6aYOwfZvTyc0mkPHzkAExqhKlnQXvRfK6PZV3I XKmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681145585; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+SKXBRJdA9KUw/4IAA9R3X/vHCTMNddy95IWzacAV94=; b=mMxsqWI59sq/ZBYPGaFcfmrvgGMY7iz9pfwVBhg0TDh51exdW8c+nUFtLUWwSS5wUy 2y2OJ2O5UXoIiMHg6zO5MpP8R0s6fleSWovT0AH7MMxW7To6JDBKmETNbCwtLubv+rMW 5bVeel8CGBEOYoWlHEn8yKqFrYt2w+Lq484KLq8ukBqrbaV8ETUxW7Y0t2s1mQLHAFCp gqxnigL8HtLqrfeMDPV1xekWwuVKQhpvV0uTuimWtOkfzbPw5euJNDMSds7M30nU8vIy 49b7wwNJioGKXOmU2pgD4QidwO3Vo7+I9iR/QhhbH7kT/XaZjzId8J/Uhe2ZylcWKzus D2hA== X-Gm-Message-State: AAQBX9eqfrHQNkALRQJQ8A7Yzm03P6ZKE03ymdhSrxGJsWNxgrmDUMPw U6OO/frE4rY8IImgyYUjdnJ65wvoLRvRQPBSihA= X-Google-Smtp-Source: AKy350bmMiGxuYTotDg8EwwLbao2P5bpIykvmT1FGWlLzRVLWkAOBChGkNA0nL0lYuREEjAja1xSBw== X-Received: by 2002:a05:6870:d113:b0:184:12f8:e22e with SMTP id e19-20020a056870d11300b0018412f8e22emr6877917oac.5.1681145585025; Mon, 10 Apr 2023 09:53:05 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v2 2/4] target/riscv: add query-cpy-definitions support Date: Mon, 10 Apr 2023 13:52:49 -0300 Message-Id: <20230410165251.99107-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410165251.99107-1-dbarboza@ventanamicro.com> References: <20230410165251.99107-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::29; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681145655848100001 Content-Type: text/plain; charset="utf-8" This command is used by tooling like libvirt to retrieve a list of supported CPUs. Each entry returns a CpuDefinitionInfo object that contains more information about each CPU. This initial support includes only the name of the CPU and its typename. Here's what the command produces for the riscv64 target: $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio {"QMP": {"version": (...)} {"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}} {"return": {}} {"execute": "query-cpu-definitions"} {"return": [ {"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated= ": false}, {"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": false,= "deprecated": false}, {"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated":= false}, {"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "depr= ecated": false}, {"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": false, "de= precated": false}, {"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": false,= "deprecated": false}, {"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": false,= "deprecated": false}] } Next patches will implement the 'static' attribute of CpuDefinitionInfo. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson --- qapi/machine-target.json | 6 ++-- target/riscv/meson.build | 3 +- target/riscv/riscv-qmp-cmds.c | 53 +++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+), 3 deletions(-) create mode 100644 target/riscv/riscv-qmp-cmds.c diff --git a/qapi/machine-target.json b/qapi/machine-target.json index 2e267fa458..f3a3de6648 100644 --- a/qapi/machine-target.json +++ b/qapi/machine-target.json @@ -324,7 +324,8 @@ 'TARGET_I386', 'TARGET_S390X', 'TARGET_MIPS', - 'TARGET_LOONGARCH64' ] } } + 'TARGET_LOONGARCH64', + 'TARGET_RISCV' ] } } =20 ## # @query-cpu-definitions: @@ -341,4 +342,5 @@ 'TARGET_I386', 'TARGET_S390X', 'TARGET_MIPS', - 'TARGET_LOONGARCH64' ] } } + 'TARGET_LOONGARCH64', + 'TARGET_RISCV' ] } } diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 5b7f813a3e..e1ff6d9b95 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -32,7 +32,8 @@ riscv_softmmu_ss.add(files( 'monitor.c', 'machine.c', 'pmu.c', - 'time_helper.c' + 'time_helper.c', + 'riscv-qmp-cmds.c', )) =20 target_arch +=3D {'riscv': riscv_ss} diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c new file mode 100644 index 0000000000..128677add9 --- /dev/null +++ b/target/riscv/riscv-qmp-cmds.c @@ -0,0 +1,53 @@ +/* + * QEMU CPU QMP commands for RISC-V + * + * Copyright (c) 2023 Ventana Micro Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" + +#include "qapi/qapi-commands-machine-target.h" +#include "cpu-qom.h" + +static void riscv_cpu_add_definition(gpointer data, gpointer user_data) +{ + ObjectClass *oc =3D data; + CpuDefinitionInfoList **cpu_list =3D user_data; + CpuDefinitionInfo *info =3D g_malloc0(sizeof(*info)); + const char *typename =3D object_class_get_name(oc); + + info->name =3D g_strndup(typename, + strlen(typename) - strlen("-" TYPE_RISCV_CPU)); + info->q_typename =3D g_strdup(typename); + + QAPI_LIST_PREPEND(*cpu_list, info); +} + +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +{ + CpuDefinitionInfoList *cpu_list =3D NULL; + GSList *list =3D object_class_get_list(TYPE_RISCV_CPU, false); + + g_slist_foreach(list, riscv_cpu_add_definition, &cpu_list); + g_slist_free(list); + + return cpu_list; +} --=20 2.39.2 From nobody Fri May 17 05:54:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1681145673; cv=none; d=zohomail.com; s=zohoarc; b=BQsKXGo6q9arbLLak6P9+Fjy+pMRWTMTRf3Juw04eLn/MUnP+plTqwKzJRIDwDKgMe5SGwYN09oLm05td5F4vykinC9r9WkzsUedpgDwYP7j/2RoeSRjGBVB8wavPptjXVTm40nmDB7z7OoEJkWBw/ziOlLWVo+iB6hhW0+zfGA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681145673; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QQVAabeAJXG93R9o2+wybfrTUqipz7vwVTHH4p1nQcc=; b=Kp/R2yGJFa+D8+vN6fJ3G95OdA/dqcY28DPs9VaJrVB32pTmWDob4pe6yBVWNEWVRX+ERB5X1WpzMf6uLjOkceh4z+y5ZCOuZbh0QBKo+e/0GpgIPXbjxbGVr8iLWIFQfeWFLMz2poxuLXh8SR/4Fe7szrTH9u52cixyqdHYlZY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16811456730344.123109561555907; Mon, 10 Apr 2023 09:54:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1plulU-0003qF-Ix; Mon, 10 Apr 2023 12:53:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1plulT-0003ph-1V for qemu-devel@nongnu.org; Mon, 10 Apr 2023 12:53:11 -0400 Received: from mail-oa1-x33.google.com ([2001:4860:4864:20::33]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1plulR-0007Mc-6Y for qemu-devel@nongnu.org; Mon, 10 Apr 2023 12:53:10 -0400 Received: by mail-oa1-x33.google.com with SMTP id 586e51a60fabf-1842e278605so6628896fac.6 for ; Mon, 10 Apr 2023 09:53:08 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id zq36-20020a0568718ea400b0017f647294f5sm4191896oab.16.2023.04.10.09.53.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 09:53:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1681145588; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QQVAabeAJXG93R9o2+wybfrTUqipz7vwVTHH4p1nQcc=; b=ZSr+JNci/efL6NVUiJvaWLSnNNjBtyZ/0J/CV0UFohMHN7HfVfnBw7I1tyIWOJWHTs ockA8KeZfDowNjM+L3PQ1ArZ1dKa6parjQ5LdnwSH5uoxfLf4aF5biyYrNvpq7Fzijm/ CiGdUTOQQbdgWUGc9p3GFBrXJ7loiZm2ns+M2YFmFnvupk87W5O3jxS4JuI8c3ZnfOu2 iOEd9hEFtknGukxrQlapFW/+ZDG6mD6VSjfRcse6idZolQyYUvQ6askbE7XeqkAPA3oF YMKN9S1ajAtIMuhz1Q6Dct2Z5xYHq1nP6lHgdZTsU7fWLXxOXrkaxALkDiLT+sE99aQL wUVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681145588; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QQVAabeAJXG93R9o2+wybfrTUqipz7vwVTHH4p1nQcc=; b=kpVgSuUGkWaG3wHSBXQtgLFSs500qcRiCTlyymNh9/wu/6XJMP4EWkrOvdZDVpqnb0 JArdwV4WEpbQhrQnqNI+xehzF6MThKnAu5LeN4aEaJGDFbnlO1OuEOXpH+wQz2iRmGi+ QnsTawrGqwHJ8URtm/l3uDFGxIYFpGvO7NplntqGad223pYPVGwb6GDTBwSxmgiKd4Sm 7a6EqvTl6mc+4Kl+vzuichVYTXWv5dAbtq/hcXkDvvwWyxezgorjxWjwwLwaaeOYgzpB vNeE15NdRzH3ydmcgBC8btESW1xtAQREYo4Y42Q/pB5YOH0ZVG17ouLUV1Y4qY3zPKq6 zi2g== X-Gm-Message-State: AAQBX9ePJKFTmcz0iqDEn3u9/jiUrQPKLos4V7yzYKpe+B7DioNOwlzV +hHgZ9ZgjqVHjuKszOxOj9KcEey8V/bqFCdC8QA= X-Google-Smtp-Source: AKy350Z+pAoBFOHt6y4dIOh6bPkguWLwQvMseDxCVo5Vb94KuCta4x47sPW/TNrt0a3cKlmKO54Ubg== X-Received: by 2002:a05:6870:4687:b0:17e:997e:9472 with SMTP id a7-20020a056870468700b0017e997e9472mr7278684oap.31.1681145587821; Mon, 10 Apr 2023 09:53:07 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v2 3/4] target/riscv: add 'static' attribute of query-cpu-definitions Date: Mon, 10 Apr 2023 13:52:50 -0300 Message-Id: <20230410165251.99107-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410165251.99107-1-dbarboza@ventanamicro.com> References: <20230410165251.99107-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::33; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681145674945100003 Content-Type: text/plain; charset="utf-8" 'static' is defined in the QMP doc as: "whether a CPU definition is static and will not change depending on QEMU version, machine type, machine options and accelerator options. A static model is always migration-safe." For RISC-V we'll consider all named CPUs as static since their extensions can't be changed by user input. Generic CPUs will be considered non-static. We aren't ready to make the change for generic CPUs yet because we're using the same class init for every CPU. We'll deal with it next. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu-qom.h | 3 +++ target/riscv/cpu.c | 6 ++++++ target/riscv/riscv-qmp-cmds.c | 2 ++ 3 files changed, 11 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index b9318e0783..687cb6f4d0 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -54,6 +54,7 @@ OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CP= U) =20 /** * RISCVCPUClass: + * @static_model: See CpuDefinitionInfo::static * @parent_realize: The parent class' realize handler. * @parent_phases: The parent class' reset phase handlers. * @@ -65,6 +66,8 @@ struct RISCVCPUClass { /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; + + bool static_model; }; =20 #endif /* RISCV_CPU_QOM_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cb68916fce..30a1e74ea6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1679,6 +1679,12 @@ static void riscv_cpu_class_init(ObjectClass *c, voi= d *data) resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NUL= L, &mcc->parent_phases); =20 + /* + * Consider all models to be static. Each CPU is free to + * set it to false if needed. + */ + mcc->static_model =3D true; + cc->class_by_name =3D riscv_cpu_class_by_name; cc->has_work =3D riscv_cpu_has_work; cc->dump_state =3D riscv_cpu_dump_state; diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c index 128677add9..639f2c052e 100644 --- a/target/riscv/riscv-qmp-cmds.c +++ b/target/riscv/riscv-qmp-cmds.c @@ -30,6 +30,7 @@ static void riscv_cpu_add_definition(gpointer data, gpointer user_data) { ObjectClass *oc =3D data; + RISCVCPUClass *cc =3D RISCV_CPU_CLASS(oc); CpuDefinitionInfoList **cpu_list =3D user_data; CpuDefinitionInfo *info =3D g_malloc0(sizeof(*info)); const char *typename =3D object_class_get_name(oc); @@ -37,6 +38,7 @@ static void riscv_cpu_add_definition(gpointer data, gpoin= ter user_data) info->name =3D g_strndup(typename, strlen(typename) - strlen("-" TYPE_RISCV_CPU)); info->q_typename =3D g_strdup(typename); + info->q_static =3D cc->static_model; =20 QAPI_LIST_PREPEND(*cpu_list, info); } --=20 2.39.2 From nobody Fri May 17 05:54:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1681145655; cv=none; d=zohomail.com; s=zohoarc; b=SNlzemuyGlXDJzecLUlmicSXfLJo4xdp896RgcTt49ns1EyuSIwN++SCudgEW+UD8T+39b1yF+vhVDI54m0geNdd9O9dVommVqXt3mNpboUl45HPWfchrrBYB1ZjRRTrjQlijhgacv5QooaDBvl3cmx9mTh2jen7fP0RHWE+Hu0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681145655; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8S9VXdeC8xdVFGVtSrYNnF6V/UoWhvL4Al8I8wZ8h/E=; b=Rq166kjY5aEIhhY+BviKVpmY/FClKWc4SJuoT3tK3xJi8qA7DEQFZAYonhIO6+oIsGjhKMHi4jJla/PfErQulZw1Ar10zSnTNCeiMFAOunJ971bmi+D/CRMCBWg47Lwfm5vnk4Lf0IYA5hSWClPpnzCPurtPs5L9aYFnMMwK1so= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681145655333451.613050953178; Mon, 10 Apr 2023 09:54:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1plulX-0003rj-EE; Mon, 10 Apr 2023 12:53:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1plulV-0003rB-Rw for qemu-devel@nongnu.org; Mon, 10 Apr 2023 12:53:13 -0400 Received: from mail-oa1-x2c.google.com ([2001:4860:4864:20::2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1plulT-0007Io-Ki for qemu-devel@nongnu.org; Mon, 10 Apr 2023 12:53:13 -0400 Received: by mail-oa1-x2c.google.com with SMTP id 586e51a60fabf-18447b9a633so3924956fac.7 for ; Mon, 10 Apr 2023 09:53:11 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id zq36-20020a0568718ea400b0017f647294f5sm4191896oab.16.2023.04.10.09.53.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 09:53:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1681145590; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8S9VXdeC8xdVFGVtSrYNnF6V/UoWhvL4Al8I8wZ8h/E=; b=beiqwl4LcSryXdjQpwOh9PCkZcaScvlnf0fMPxFzTFsIEdbO8+CDo/FSVSGdPVZeVv Yy/YRQB5wMXLI6pNCxwv7Fq9MUn5ytBh+3BApzcCRBdJWlPN5G0FrlbLYAqTjjIMy3Sr GA6NhbHPzfMZ+ALxMVqGzNzQWcaPMwV+teT4ImOH7RqBI9RsS6CuVY/XXn8MG/rvFUUL ZdxWacBc3Urlc/CjFEy10NzQ64MYirEFJSxnYg6eqqTXOnu3AS3pxww3SBL5DKP+psie qXqkLLnPnimmbcJvyq2o/OO2LRnYQ0iihcJDYm4hbMoxsDq7195pIVEzRXkYeFXzcPkj 79dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681145590; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8S9VXdeC8xdVFGVtSrYNnF6V/UoWhvL4Al8I8wZ8h/E=; b=t73ctkY9+Kc+r6IdBGW7uN/MrlUlIAfi38VwD3ZCJ2PEmMMX1gDJQQU29NNAE8wVT3 fGyI+GChuEi967kCPgd8L1GM6eM7PeM8pOJQmJN8xL+oheHnUvP9Wrp+u6gcY3RwqpHO 4O/7Huazy34ZThZGxYMdr7fhIxRIvXDmAMbN3MzhiGvMmyqHggzTQ8ZIWLCrA2oG1hI9 pl7ahHe33X7kWbNQtD9vAEdkdqPNG5UAyJs3PLVKLcdg6FFN4AFYdEpOC8ZUTqHJV+tm 1xwQWHk2DVVqCHg25eSWbqgf4HawnqGB+DjYri5Fpl+rUhcL0dsrldh4mYZtzkQbP4Pn rlpw== X-Gm-Message-State: AAQBX9c47xLZyEqg+oaB1KYDLiauXWltYVFAhCCafHFcsYfENaccU1Or 3KamD9mEJZU+wE6Uk/ui3YVLX9IVONmnlvc+Mrw= X-Google-Smtp-Source: AKy350aOUpQEWptmcihM4jdTKcKdEFZESR8foSz3hqe71QjvrUCXxVhyPe3uROnNv/i22cSFg+aubg== X-Received: by 2002:a05:6870:4191:b0:17e:a87f:1eac with SMTP id y17-20020a056870419100b0017ea87f1eacmr9923480oac.21.1681145590703; Mon, 10 Apr 2023 09:53:10 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v2 4/4] target/riscv: make generic cpus not static Date: Mon, 10 Apr 2023 13:52:51 -0300 Message-Id: <20230410165251.99107-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410165251.99107-1-dbarboza@ventanamicro.com> References: <20230410165251.99107-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681145656304100003 Content-Type: text/plain; charset="utf-8" A CPU is declared static or not by changing the class attribute 'static'. For now the base class is defining every CPU as static via riscv_cpu_class_init(). To change this setting for generic CPUs we'll need a different class init for them. Then we'll ned a macro that allows us to set a different .class_init implementation for the CPU. With all that we're now able to set 'static' as false for the 'any', 'rv32', 'rv64' and 'x-rv128' CPUs. For the riscv64 target: $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio {"QMP": {"version": (...) } {"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}} {"return": {}} {"execute": "query-cpu-definitions"} {"return": [ {"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated= ": false}, {"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": true, = "deprecated": false}, {"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated":= false}, {"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "depr= ecated": false}, {"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": true, "dep= recated": false}, {"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": true, = "deprecated": false}, {"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": true, = "deprecated": false}] } Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 30a1e74ea6..cc881ef040 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -340,6 +340,13 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) } #endif =20 +static void riscv_generic_cpu_class_init(ObjectClass *c, void *data) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); + + mcc->static_model =3D false; +} + static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -1779,6 +1786,14 @@ void riscv_cpu_list(void) .instance_init =3D initfn \ } =20 +#define DEFINE_CPU_WITH_CLASSFN(type_name, initfn, classfn) \ + { \ + .name =3D type_name, \ + .parent =3D TYPE_RISCV_CPU, \ + .instance_init =3D initfn, \ + .class_init =3D classfn \ + } + static const TypeInfo riscv_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_CPU, @@ -1790,23 +1805,27 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .class_size =3D sizeof(RISCVCPUClass), .class_init =3D riscv_cpu_class_init, }, - DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), + DEFINE_CPU_WITH_CLASSFN(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init, + riscv_generic_cpu_class_init), #if defined(CONFIG_KVM) DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), #endif #if defined(TARGET_RISCV32) - DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), + DEFINE_CPU_WITH_CLASSFN(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init, + riscv_generic_cpu_class_init), DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init= ), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), #elif defined(TARGET_RISCV64) - DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), + DEFINE_CPU_WITH_CLASSFN(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init, + riscv_generic_cpu_class_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), + DEFINE_CPU_WITH_CLASSFN(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init, + riscv_generic_cpu_class_init), #endif }; =20 --=20 2.39.2