Smstateen FCSR implementation

[RFC PATCH 0/4] Smstateen FCSR implementation

Mayuresh Chitale posted 4 patches 1 year ago

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Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liweiwei@iscas.ac.cn>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/cpu.c                        |  3 ++-
target/riscv/cpu.h                        |  4 ++++
target/riscv/cpu_helper.c                 |  5 +++++
target/riscv/csr.c                        | 25 ++++++++++++++++++++++-
target/riscv/insn_trans/trans_rvf.c.inc   | 24 +++++++++++++++++++---
target/riscv/insn_trans/trans_rvzfh.c.inc |  4 ++++
target/riscv/translate.c                  |  2 ++
7 files changed, 62 insertions(+), 5 deletions(-)

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[RFC PATCH 0/4] Smstateen FCSR implementation

Posted by Mayuresh Chitale 1 year ago

Patch 4 and 5 of the smstateen series need to be re-submitted with
changes described in the email below:
https://lists.nongnu.org/archive/html/qemu-riscv/2022-11/msg00155.html
Hence spliting the patch 4 of the original series into three patches and
re-submitting along with the original patch 5.

Mayuresh Chitale (4):
  target/riscv: smstateen check for fcsr
  target/riscv: Add fcsr field in tb->flags
  target/riscv: check smstateen fcsr flag
  target/riscv: smstateen knobs

 target/riscv/cpu.c                        |  3 ++-
 target/riscv/cpu.h                        |  4 ++++
 target/riscv/cpu_helper.c                 |  5 +++++
 target/riscv/csr.c                        | 25 ++++++++++++++++++++++-
 target/riscv/insn_trans/trans_rvf.c.inc   | 24 +++++++++++++++++++---
 target/riscv/insn_trans/trans_rvzfh.c.inc |  4 ++++
 target/riscv/translate.c                  |  2 ++
 7 files changed, 62 insertions(+), 5 deletions(-)

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2.34.1