From nobody Fri May 17 10:44:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1681129853; cv=none; d=zohomail.com; s=zohoarc; b=TUfmM75IzD+R/7zYjdmJBuiV/RKf9WLVZIjoKKMp1EuM7qOYkyMheUxoJQTXEcbk9naEf9BAxzF9Ms9fcP//HDxr8XTSXMBAbpcfNGhmJZ5Nw2YIAPTVKO0/vj93zMH+LB0HzSg7+MeVxGxFCyNGQiZGiibIbSpozuntgPzV4xA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681129853; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7f97QPiu1Fd+OM3S7vziX0p5A2QzwngIPHhNMODXrEY=; b=bW67WT1M/nYePwsnwbMKGJ2KU2igmGbZRt3Ufw+vQiSIsr++Ru5IP77TVIulDvxhczW2i60+hwbZt+3H14S74eS6jjCIwh5Sihrpmy9PJHJRz/VY5KrOpXT9c+2Yf+XS5rCWxCOByPJHCnP4wkmuvzFacWE7n0F+RqlvYe+QTAQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681129853131416.4853345559827; Mon, 10 Apr 2023 05:30:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1plqfB-0007OZ-OO; Mon, 10 Apr 2023 08:30:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1plqeq-0007Ac-02 for qemu-devel@nongnu.org; Mon, 10 Apr 2023 08:30:06 -0400 Received: from mail-oi1-x22f.google.com ([2607:f8b0:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1plqel-0000sV-T1 for qemu-devel@nongnu.org; Mon, 10 Apr 2023 08:30:03 -0400 Received: by mail-oi1-x22f.google.com with SMTP id w13so23615208oik.2 for ; Mon, 10 Apr 2023 05:29:56 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id o13-20020a056808124d00b00387160bcd46sm4297016oiv.46.2023.04.10.05.29.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 05:29:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1681129795; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7f97QPiu1Fd+OM3S7vziX0p5A2QzwngIPHhNMODXrEY=; b=QuWFxAQ/lHvuToKCvIjGN1OcZR4DK2tSzho0Sb+ruJCHNSmSJQsm3CWUtAC+f6045N s59EwgR8GhsQC6r91YecUh30y7a9oLjbmEHjaQ6jEBHqFLUaoZ0+yeK7ndBt3V61Alo0 DLIgxQr/ZnvktWbnfTEzBUpLwY+mO7/ir/dyzPZqY7LuEEZw9y4pE+xqFKEIlinLt6/E xCG5lupH///COaY3w7GF/lAdj8QkURfIlvyNgvF5pHBfhJAThSCMa0DvCbnGjRKu5B+z sew4x2zPKv0aoVETMBefvrf/4J0FmwuXkrN10cwH0G8IVIBONufhXOkmOcmXP9PoQ7yO IWHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681129795; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7f97QPiu1Fd+OM3S7vziX0p5A2QzwngIPHhNMODXrEY=; b=XPeQbq8xmwraKDd9ZLZPtk4gcK7daFvP/PAXKXrfO4wXQKXAOSa6EWMFfwW3TN1VE0 21Dp9SmcvDrCBGTq2lizx0axkmUQ1LFaxLgXUz2rT1mrCQ/p7MGZlFUI2UrpS4vCEKOw 2tCYPCh7q41UiR2aCxGlh1oH3dO9ZTKouBtIxIgcALvtrKzuhr19EUzMs73BpFWjHn9u MExszWnrIOTaQi7PSfMHsE8Zo+z/XTQEPQ1jmra6M7pgbS69plmkIPOabvN2khz+Ra/t M9WwfDQSqubXTep1L5X1hXuwKFxcKWfY7XIDO+s/hbsHPgd9eKt2OX35Vf8bPhHIkrQ2 T8hQ== X-Gm-Message-State: AAQBX9ffVEKzcFj+4BArq1Fg6F9AzwVzotVgNIQgSdOl9DB+oGCfSYFC QtRf03K4D3gzCS0skvEQQjPBZlAq9tKchOwH+2E= X-Google-Smtp-Source: AKy350YyYQIBP7lSCjxQQRXmjqMkocnO9d5wLZK+wlo7lCX5tHxXRpCW4UOsi1Tke8S0laBwbOJWEg== X-Received: by 2002:aca:6244:0:b0:389:7d24:def5 with SMTP id w65-20020aca6244000000b003897d24def5mr2977333oib.10.1681129795457; Mon, 10 Apr 2023 05:29:55 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 1/4] target/riscv: add CPU QOM header Date: Mon, 10 Apr 2023 09:29:42 -0300 Message-Id: <20230410122945.77439-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410122945.77439-1-dbarboza@ventanamicro.com> References: <20230410122945.77439-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681129855499100009 Content-Type: text/plain; charset="utf-8" QMP CPU commands are usually implemented by a separated file, -qmp-cmds.c, to allow them to be build only for softmmu targets. This file uses a CPU QOM header with basic QOM declarations for the arch. We'll introduce query-cpu-definitions for RISC-V CPUs in the next patch, but first we need a cpu-qom.h header with the definitions of TYPE_RISCV_CPU and RISCVCPUClass declarations. These were moved from cpu.h to the new file, and cpu.h now includes "cpu-qom.h". Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu-qom.h | 70 ++++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 46 +-------------------------- 2 files changed, 71 insertions(+), 45 deletions(-) create mode 100644 target/riscv/cpu-qom.h diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h new file mode 100644 index 0000000000..b9318e0783 --- /dev/null +++ b/target/riscv/cpu-qom.h @@ -0,0 +1,70 @@ +/* + * QEMU RISC-V CPU QOM header + * + * Copyright (c) 2023 Ventana Micro Systems Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef RISCV_CPU_QOM_H +#define RISCV_CPU_QOM_H + +#include "hw/core/cpu.h" +#include "qom/object.h" + +#define TYPE_RISCV_CPU "riscv-cpu" + +#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU +#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) +#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU + +#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") +#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") +#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") +#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") +#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") +#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") +#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") +#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") +#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") +#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") +#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") +#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") + +#if defined(TARGET_RISCV32) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 +#elif defined(TARGET_RISCV64) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 +#endif + +typedef struct CPUArchState CPURISCVState; + +OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) + +/** + * RISCVCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * + * A RISCV CPU model. + */ +struct RISCVCPUClass { + /*< private >*/ + CPUClass parent_class; + /*< public >*/ + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + +#endif /* RISCV_CPU_QOM_H */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cbf3de2708..d830a64713 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -28,6 +28,7 @@ #include "qemu/int128.h" #include "cpu_bits.h" #include "qapi/qapi-types-common.h" +#include "cpu-qom.h" =20 #define TCG_GUEST_DEFAULT_MO 0 =20 @@ -37,32 +38,6 @@ */ #define TARGET_INSN_START_EXTRA_WORDS 1 =20 -#define TYPE_RISCV_CPU "riscv-cpu" - -#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU -#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) -#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU - -#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") -#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") -#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") -#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") -#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") -#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") -#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") -#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") -#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") -#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") -#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") -#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") -#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") - -#if defined(TARGET_RISCV32) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 -#elif defined(TARGET_RISCV64) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 -#endif - #define RV(x) ((target_ulong)1 << (x - 'A')) =20 /* @@ -103,8 +78,6 @@ enum { =20 #define MAX_RISCV_PMPS (16) =20 -typedef struct CPUArchState CPURISCVState; - #if !defined(CONFIG_USER_ONLY) #include "pmp.h" #include "debug.h" @@ -389,23 +362,6 @@ struct CPUArchState { uint64_t kvm_timer_frequency; }; =20 -OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) - -/* - * RISCVCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * - * A RISCV CPU model. - */ -struct RISCVCPUClass { - /* < private > */ - CPUClass parent_class; - /* < public > */ - DeviceRealize parent_realize; - ResettablePhases parent_phases; -}; - /* * map is a 16-bit bitmap: the most significant set bit in map is the maxi= mum * satp mode that is supported. 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([191.255.108.232]) by smtp.gmail.com with ESMTPSA id o13-20020a056808124d00b00387160bcd46sm4297016oiv.46.2023.04.10.05.29.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 05:29:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1681129798; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+SKXBRJdA9KUw/4IAA9R3X/vHCTMNddy95IWzacAV94=; b=ZL3iu4HJ31DXsAiCrrDBLr3bKjH7hEUpYv06ybEnRsjfUeahiFP0FI3kay/SIFFR2L +Q8maCPKNZ7kD8GrgMXCXLoWtoEda4oEYQrLBvUqM0XYHX3S/NqVJOxR6VaCETmLCqB4 UueMGQ/2XbbmlMK1vvcvCGECmoGeqQCueiANrB2hcuXC/SeNSpmn5DX0JC9/Pide2Oah PGc+p2scKEPFWt6+TZwWVzP3dsYmRYt9rBa6m95WpgYDChcVFErj6TfQ93xh8QeZZUr8 THvj7du8KpukcuvhHZKLUHL4vzHwdfudfPwNOK5HPslgq/makBwzUAN+0PkeNU0kmjoE dmAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681129798; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+SKXBRJdA9KUw/4IAA9R3X/vHCTMNddy95IWzacAV94=; b=q9m/aXnUBNP6dPX6CGSZuvCkqLuanXv9yA4hMenh5hsjuEKEb6v7CaBr7NCQD/K4zv CGt4TFMClpY6JMpYcTAwkvfniWsqitYuf8j8Nr5Jtrn95WWDjWvh3rPrEsC486ieza8K PFJc8ZZc/ARdksgeAs/JFqqUVqqZz+0283bA5A0mu9N53KO62SelgXFCWHh6muNzS/aj G/AJg54ApdnyBDiaW/8JjFxJiadjN+6OlJrp9wdSwcMMZvH3SQZB6k5SBZY2GHBgUMuM SzGnLHGkobhnaHzqFzjR0o0CwWmEfNjxt53+mvznf6osLwxF1wydxC+P2nVECK06Ctlk y4Fw== X-Gm-Message-State: AAQBX9eAAKfWwFyt4CX649oCPLSe4nJHIN6oUfAMma79c9QLoG+5eYE8 sXNWMdrKRWxyp1/xTJuvHZNPTLwoD/fDmnsrH44= X-Google-Smtp-Source: AKy350bCLs0RgGd8Gfde98QxLJUr5LApo4lK4TaxX9kv711zVOSttPhrt+6vqyElSXE/Ys9aqN4HZw== X-Received: by 2002:a05:6808:252:b0:386:d4f7:6791 with SMTP id m18-20020a056808025200b00386d4f76791mr3816717oie.37.1681129798368; Mon, 10 Apr 2023 05:29:58 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 2/4] target/riscv: add query-cpy-definitions support Date: Mon, 10 Apr 2023 09:29:43 -0300 Message-Id: <20230410122945.77439-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410122945.77439-1-dbarboza@ventanamicro.com> References: <20230410122945.77439-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681129855517100010 Content-Type: text/plain; charset="utf-8" This command is used by tooling like libvirt to retrieve a list of supported CPUs. Each entry returns a CpuDefinitionInfo object that contains more information about each CPU. This initial support includes only the name of the CPU and its typename. Here's what the command produces for the riscv64 target: $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio {"QMP": {"version": (...)} {"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}} {"return": {}} {"execute": "query-cpu-definitions"} {"return": [ {"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated= ": false}, {"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": false,= "deprecated": false}, {"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated":= false}, {"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "depr= ecated": false}, {"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": false, "de= precated": false}, {"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": false,= "deprecated": false}, {"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": false,= "deprecated": false}] } Next patches will implement the 'static' attribute of CpuDefinitionInfo. Signed-off-by: Daniel Henrique Barboza --- qapi/machine-target.json | 6 ++-- target/riscv/meson.build | 3 +- target/riscv/riscv-qmp-cmds.c | 53 +++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+), 3 deletions(-) create mode 100644 target/riscv/riscv-qmp-cmds.c diff --git a/qapi/machine-target.json b/qapi/machine-target.json index 2e267fa458..f3a3de6648 100644 --- a/qapi/machine-target.json +++ b/qapi/machine-target.json @@ -324,7 +324,8 @@ 'TARGET_I386', 'TARGET_S390X', 'TARGET_MIPS', - 'TARGET_LOONGARCH64' ] } } + 'TARGET_LOONGARCH64', + 'TARGET_RISCV' ] } } =20 ## # @query-cpu-definitions: @@ -341,4 +342,5 @@ 'TARGET_I386', 'TARGET_S390X', 'TARGET_MIPS', - 'TARGET_LOONGARCH64' ] } } + 'TARGET_LOONGARCH64', + 'TARGET_RISCV' ] } } diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 5b7f813a3e..e1ff6d9b95 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -32,7 +32,8 @@ riscv_softmmu_ss.add(files( 'monitor.c', 'machine.c', 'pmu.c', - 'time_helper.c' + 'time_helper.c', + 'riscv-qmp-cmds.c', )) =20 target_arch +=3D {'riscv': riscv_ss} diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c new file mode 100644 index 0000000000..128677add9 --- /dev/null +++ b/target/riscv/riscv-qmp-cmds.c @@ -0,0 +1,53 @@ +/* + * QEMU CPU QMP commands for RISC-V + * + * Copyright (c) 2023 Ventana Micro Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" + +#include "qapi/qapi-commands-machine-target.h" +#include "cpu-qom.h" + +static void riscv_cpu_add_definition(gpointer data, gpointer user_data) +{ + ObjectClass *oc =3D data; + CpuDefinitionInfoList **cpu_list =3D user_data; + CpuDefinitionInfo *info =3D g_malloc0(sizeof(*info)); + const char *typename =3D object_class_get_name(oc); + + info->name =3D g_strndup(typename, + strlen(typename) - strlen("-" TYPE_RISCV_CPU)); + info->q_typename =3D g_strdup(typename); + + QAPI_LIST_PREPEND(*cpu_list, info); +} + +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +{ + CpuDefinitionInfoList *cpu_list =3D NULL; + GSList *list =3D object_class_get_list(TYPE_RISCV_CPU, false); + + g_slist_foreach(list, riscv_cpu_add_definition, &cpu_list); + g_slist_free(list); + + return cpu_list; +} --=20 2.39.2 From nobody Fri May 17 10:44:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1681129894; cv=none; d=zohomail.com; s=zohoarc; b=QjaeLyRpH3K9EPGbs5A7tDla/2e6L6CBUAlwIzyLpGtgpjhrXlAcOXqvWmHAjhfEVqws5Os/RrM4bw2Ventb+jq+/qH4Hxqp+Fwyt8HYNauRBImxLFCiQDf1NKbbHp4Wp7DiRTCSimo1Z5cqWILwha+pgsyvFJXsmZjEWuKLHXQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681129894; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QQVAabeAJXG93R9o2+wybfrTUqipz7vwVTHH4p1nQcc=; b=aJeUCO5lPVoYBDR31ttoGll/WSIycU5ARxnclrT9hfO0QU/C/Fc97wNBXaQgSoL4pCEVf9fiWQRxvqh4S4NdM/6q9Qy3/LfkZJlnQt40K7BRuV+P86OfvZ4IqJaxnkSCow3KFsc6qgBxexhNcZBBrHiFN14LrNFSbyfcSBHWdSI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681129894613662.087262509927; Mon, 10 Apr 2023 05:31:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1plqfL-0007ST-BS; Mon, 10 Apr 2023 08:30:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1plqer-0007Ag-Mb for qemu-devel@nongnu.org; Mon, 10 Apr 2023 08:30:06 -0400 Received: from mail-oi1-x22c.google.com ([2607:f8b0:4864:20::22c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1plqeo-0000tq-UE for qemu-devel@nongnu.org; Mon, 10 Apr 2023 08:30:05 -0400 Received: by mail-oi1-x22c.google.com with SMTP id bf5so3050794oib.8 for ; Mon, 10 Apr 2023 05:30:02 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id o13-20020a056808124d00b00387160bcd46sm4297016oiv.46.2023.04.10.05.29.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 05:30:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1681129801; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QQVAabeAJXG93R9o2+wybfrTUqipz7vwVTHH4p1nQcc=; b=dkiqu/aTnyD3IXaXxzQiOJz2WPJeLXwU5/yfjrucXPCvZyURP9CBZTMGBYe8Xhsm17 TgTSsPGaVjXq/LVBxvfHKj/tv7VnvAf+aITYdTXAlz6ZqlmM85hFszbGWRhfA2TBv2gY tDE5ZofV73oFaf6eLtrm2UYG3cYOHSS0VfkzWOq8Z/O+G5eXWp9sSVjvj5B4lssl0nMg 3mPvHAkgyEY2pw38LVSeRvz1rFvGRHRtaeU0n0SxHAguWnjdlvTSusXhBFa5fyN8t8EG isN50P08Uq3XJ7vkfdwALM0Bcua+WIbUWsHmjlprBaR6EKRPRLQSXGNPhEmQhkVWpYjc 9IgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681129801; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QQVAabeAJXG93R9o2+wybfrTUqipz7vwVTHH4p1nQcc=; b=fCxtxcRInJkQauDuH1cA15BOFZZ0hL/bEYFiGrZAXWDXHGQsNM49TnRausUhFj7w36 ECVQcT884Ir9OdTiVeeHL5kPGOeIdw2aRNX8jTSkxLv74RnzKonlAJZafxXVD7dkokMf KL2MoquzBl/dcJNOIAjf8qf2c78BZbfrHdjgiUhl8k+i0bKjpSn96Jh4qylAVAdPxX16 4ze3RmlDcd588NGedX1+T0o2+alW26n8MInt4fS0jfVKimRRHMT21/RrdI5X72x1fIG7 QMnk/K8zHD1BDPwH89QmHTkPkmMoiObBxWbEPRUl4pyfBIjphe5NWGMjW4d8E+KUXjPl Z15A== X-Gm-Message-State: AAQBX9dLYiKuUCwO23HBJZH2KVBe2Tj/wlzMB6ZF646Vxzb3mICNwd1t B2x3if81RFyDGg2yzU+FALcSJdkDJ/gKX0aEHzI= X-Google-Smtp-Source: AKy350b5y/gGpGqg2jB8WE73FEy7r038wHNPXEeQQgzDU42hmzapxIurR8h+5r4PkI6lgw3Sb8QG0g== X-Received: by 2002:a05:6808:1a11:b0:386:e309:cfbf with SMTP id bk17-20020a0568081a1100b00386e309cfbfmr5966386oib.13.1681129801386; Mon, 10 Apr 2023 05:30:01 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 3/4] target/riscv: add 'static' attribute of query-cpu-definitions Date: Mon, 10 Apr 2023 09:29:44 -0300 Message-Id: <20230410122945.77439-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410122945.77439-1-dbarboza@ventanamicro.com> References: <20230410122945.77439-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681129896826100007 Content-Type: text/plain; charset="utf-8" 'static' is defined in the QMP doc as: "whether a CPU definition is static and will not change depending on QEMU version, machine type, machine options and accelerator options. A static model is always migration-safe." For RISC-V we'll consider all named CPUs as static since their extensions can't be changed by user input. Generic CPUs will be considered non-static. We aren't ready to make the change for generic CPUs yet because we're using the same class init for every CPU. We'll deal with it next. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu-qom.h | 3 +++ target/riscv/cpu.c | 6 ++++++ target/riscv/riscv-qmp-cmds.c | 2 ++ 3 files changed, 11 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index b9318e0783..687cb6f4d0 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -54,6 +54,7 @@ OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CP= U) =20 /** * RISCVCPUClass: + * @static_model: See CpuDefinitionInfo::static * @parent_realize: The parent class' realize handler. * @parent_phases: The parent class' reset phase handlers. * @@ -65,6 +66,8 @@ struct RISCVCPUClass { /*< public >*/ DeviceRealize parent_realize; ResettablePhases parent_phases; + + bool static_model; }; =20 #endif /* RISCV_CPU_QOM_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cb68916fce..30a1e74ea6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1679,6 +1679,12 @@ static void riscv_cpu_class_init(ObjectClass *c, voi= d *data) resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NUL= L, &mcc->parent_phases); =20 + /* + * Consider all models to be static. Each CPU is free to + * set it to false if needed. + */ + mcc->static_model =3D true; + cc->class_by_name =3D riscv_cpu_class_by_name; cc->has_work =3D riscv_cpu_has_work; cc->dump_state =3D riscv_cpu_dump_state; diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c index 128677add9..639f2c052e 100644 --- a/target/riscv/riscv-qmp-cmds.c +++ b/target/riscv/riscv-qmp-cmds.c @@ -30,6 +30,7 @@ static void riscv_cpu_add_definition(gpointer data, gpointer user_data) { ObjectClass *oc =3D data; + RISCVCPUClass *cc =3D RISCV_CPU_CLASS(oc); CpuDefinitionInfoList **cpu_list =3D user_data; CpuDefinitionInfo *info =3D g_malloc0(sizeof(*info)); const char *typename =3D object_class_get_name(oc); @@ -37,6 +38,7 @@ static void riscv_cpu_add_definition(gpointer data, gpoin= ter user_data) info->name =3D g_strndup(typename, strlen(typename) - strlen("-" TYPE_RISCV_CPU)); info->q_typename =3D g_strdup(typename); + info->q_static =3D cc->static_model; =20 QAPI_LIST_PREPEND(*cpu_list, info); } --=20 2.39.2 From nobody Fri May 17 10:44:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1681129892; cv=none; d=zohomail.com; s=zohoarc; b=k4sZBHSFop/Eu1zRgJxjEcoVOdwFMiHYha/DYtN5XpYwBoRH/EmPNfDu3wI+XRS1gqKLPrV63vHLxljdcWYQGrD4OmcCTqKl4/YHyYLdHYpqoJ8ncIlpfKc6N7LGoNXAZV1DMc6by7onw6dJT3OtxynS79RihVTRcs4TnGOyT2g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1681129892; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+8eN100PVmLq4Irfczq1tK9TJADhtWJGfBNp8oFnf+o=; b=jiO+kN3+sPUByryIG3QDP9O+HzycspWn1ihI0EzaJIift/Fh8aWM0G3eWNdyqKEGkqI7msu5KxAvXNQrTfjbBRhYu/kWIYHQ3f+LKIM2Ub/WqKsR/rojx/kQBDoK5qI+hIbsfZOT5/fb1TruXX17Na25N0fMVoGzYUXm2wBMrTs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1681129892466796.2725679017144; Mon, 10 Apr 2023 05:31:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1plqfF-0007Q0-Hb; Mon, 10 Apr 2023 08:30:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1plqey-0007I7-2c for qemu-devel@nongnu.org; Mon, 10 Apr 2023 08:30:13 -0400 Received: from mail-oi1-x22c.google.com ([2607:f8b0:4864:20::22c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1plqet-000162-6Q for qemu-devel@nongnu.org; Mon, 10 Apr 2023 08:30:09 -0400 Received: by mail-oi1-x22c.google.com with SMTP id bl22so21003659oib.11 for ; Mon, 10 Apr 2023 05:30:06 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id o13-20020a056808124d00b00387160bcd46sm4297016oiv.46.2023.04.10.05.30.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 05:30:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1681129805; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+8eN100PVmLq4Irfczq1tK9TJADhtWJGfBNp8oFnf+o=; b=jtXYKgf+GwxgzXxnxsueQlBrr2Z+i0D1XGTDZiZSPurucYJVdIBAlC8OM2nr5AH+qs zeaxvZQm9XpzIQj56PQDsYKwLICzg1hLk6BSJLC5Ab8yRjEQ9GDU7UA67sCTKAQYBGlc J59NH/fr3DylmkNbktwhgHn2B9yLaNU4S4tgAagvfVQf5s05xn7B8Ywcj8NmLPrr3hlp wLCVRKTCuzUsJDu5muwJbqpmTlLCuj48BaSuNdP8JSLv564sLlhzfTkZ+ptNextjOsEM 4k25tRE+GEMFnxD8ws5cHCHhY+tJNQmhggSviTs7/ljBipL27FFTiisOeqf/kcMQr8XM PV0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681129805; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+8eN100PVmLq4Irfczq1tK9TJADhtWJGfBNp8oFnf+o=; b=bIvsIuiuOuQEMCwWLpt/2qoqmKqJs8oILleBOy67rZhcZoE4rvdQLiBXmEZNXF0/83 7fdFA7ck68vBBi1HlTRv0VMkCCFPuZAHWO+EWFGgFS0gEr+C7n6DS4mdkAYbFftAQ34I Tt2xaZgURur9rrCs8d3seoHtKRIMaSkU8E0zcqRob8Kjy486ILC4vEbd0oDs1/4l9GV4 N60KlO30+7ejUuk28GDtBut/Oa5fABtOWfztoChsJ0R/Vn+zbyMcAGQXGHtLW3mVXKRV tj6St9X/gr4ft5Xd0xS0p62XB3ciIZtb9Jm9atsaZglBtM9S4YRLJY2/JzO5lbVbUTCx QWwQ== X-Gm-Message-State: AAQBX9fC6AZk3b9Zl3qbkiENWUYRWOaTF+eHteA2sWRrFZbDE0++JkRo INf1pFKZ/8SYE8ZZYzTZKS/yezRkwpsfTn4azAE= X-Google-Smtp-Source: AKy350alOk807TBHvhHO8UOElQ1z3yZ6e7+PjYJENPl4huS2NW6Flz+Jg9povlm39SIHbgfKNUeMWw== X-Received: by 2002:aca:1715:0:b0:38b:79e1:3fda with SMTP id j21-20020aca1715000000b0038b79e13fdamr4282593oii.34.1681129804497; Mon, 10 Apr 2023 05:30:04 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 4/4] target/riscv: make generic cpus not static Date: Mon, 10 Apr 2023 09:29:45 -0300 Message-Id: <20230410122945.77439-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410122945.77439-1-dbarboza@ventanamicro.com> References: <20230410122945.77439-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1681129893994100001 Content-Type: text/plain; charset="utf-8" A CPU is declared static or not by changing the class attribute 'static'. For now the base class is defining every CPU as static via riscv_cpu_class_init(). To change this setting for generic CPUs we'll need a different class init for them. Then we'll ned a macro that allows us to set a different .class_init implementation for the CPU. With all that we're now able to set 'static' as false for the 'any', 'rv32', 'rv64' and 'x-rv128' CPUs. For the riscv64 target: $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio {"QMP": {"version": (...) } {"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}} {"return": {}} {"execute": "query-cpu-definitions"} {"return": [ {"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated= ": false}, {"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": true, = "deprecated": false}, {"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated":= false}, {"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "depr= ecated": false}, {"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": true, "dep= recated": false}, {"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": true, = "deprecated": false}, {"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": true, = "deprecated": false}] } Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 48 ++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 44 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 30a1e74ea6..4a9624404c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -340,6 +340,13 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) } #endif =20 +static void riscv_any_cpu_class_init(ObjectClass *c, void *data) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); + + mcc->static_model =3D false; +} + static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -360,6 +367,13 @@ static void riscv_any_cpu_init(Object *obj) } =20 #if defined(TARGET_RISCV64) +static void rv64_base_cpu_class_init(ObjectClass *c, void *data) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); + + mcc->static_model =3D false; +} + static void rv64_base_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -430,6 +444,13 @@ static void rv64_thead_c906_cpu_init(Object *obj) #endif } =20 +static void rv128_base_cpu_class_init(ObjectClass *c, void *data) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); + + mcc->static_model =3D false; +} + static void rv128_base_cpu_init(Object *obj) { if (qemu_tcg_mttcg_enabled()) { @@ -449,6 +470,13 @@ static void rv128_base_cpu_init(Object *obj) #endif } #else +static void rv32_base_cpu_class_init(ObjectClass *c, void *data) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); + + mcc->static_model =3D false; +} + static void rv32_base_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -1779,6 +1807,14 @@ void riscv_cpu_list(void) .instance_init =3D initfn \ } =20 +#define DEFINE_CPU_WITH_CLASSFN(type_name, initfn, classfn) \ + { \ + .name =3D type_name, \ + .parent =3D TYPE_RISCV_CPU, \ + .instance_init =3D initfn, \ + .class_init =3D classfn \ + } + static const TypeInfo riscv_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_CPU, @@ -1790,23 +1826,27 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .class_size =3D sizeof(RISCVCPUClass), .class_init =3D riscv_cpu_class_init, }, - DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), + DEFINE_CPU_WITH_CLASSFN(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init, + riscv_any_cpu_class_init), #if defined(CONFIG_KVM) DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), #endif #if defined(TARGET_RISCV32) - DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), + DEFINE_CPU_WITH_CLASSFN(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init, + rv32_base_cpu_class_init), DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init= ), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), #elif defined(TARGET_RISCV64) - DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), + DEFINE_CPU_WITH_CLASSFN(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init, + rv64_base_cpu_class_init), + DEFINE_CPU_WITH_CLASSFN(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init, + rv128_base_cpu_class_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), #endif }; =20 --=20 2.39.2