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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922192479100002 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg.c | 4 +--- tcg/i386/tcg-target.c.inc | 8 +++----- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index bb52bc060b..100f81edb2 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1174,9 +1174,7 @@ static TCGTemp *tcg_global_reg_new_internal(TCGContex= t *s, TCGType type, { TCGTemp *ts; =20 - if (TCG_TARGET_REG_BITS =3D=3D 32 && type !=3D TCG_TYPE_I32) { - tcg_abort(); - } + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64 || type =3D=3D TCG_TYPE= _I32); =20 ts =3D tcg_global_alloc(s); ts->base_type =3D type; diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 4444eb9234..aa7ee16b25 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1369,8 +1369,8 @@ static void tcg_out_addi(TCGContext *s, int reg, tcg_= target_long val) } } =20 -/* Use SMALL !=3D 0 to force a short forward branch. */ -static void tcg_out_jxx(TCGContext *s, int opc, TCGLabel *l, int small) +/* Set SMALL to force a short forward branch. */ +static void tcg_out_jxx(TCGContext *s, int opc, TCGLabel *l, bool small) { int32_t val, val1; =20 @@ -1385,9 +1385,7 @@ static void tcg_out_jxx(TCGContext *s, int opc, TCGLa= bel *l, int small) } tcg_out8(s, val1); } else { - if (small) { - tcg_abort(); - } + tcg_debug_assert(!small); if (opc =3D=3D -1) { tcg_out8(s, OPC_JMP_long); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680921867496100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/tcg/tcg.h | 6 ------ target/i386/tcg/translate.c | 20 ++++++++++---------- target/s390x/tcg/translate.c | 4 ++-- tcg/optimize.c | 10 ++++------ tcg/tcg.c | 8 ++++---- tcg/aarch64/tcg-target.c.inc | 4 ++-- tcg/arm/tcg-target.c.inc | 2 +- tcg/i386/tcg-target.c.inc | 14 +++++++------- tcg/mips/tcg-target.c.inc | 14 +++++++------- tcg/ppc/tcg-target.c.inc | 8 ++++---- tcg/s390x/tcg-target.c.inc | 8 ++++---- tcg/sparc64/tcg-target.c.inc | 2 +- tcg/tci/tcg-target.c.inc | 2 +- 13 files changed, 47 insertions(+), 55 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 5cfaa53938..b19e167e1d 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -967,12 +967,6 @@ typedef struct TCGTargetOpDef { const char *args_ct_str[TCG_MAX_OP_ARGS]; } TCGTargetOpDef; =20 -#define tcg_abort() \ -do {\ - fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\ - abort();\ -} while (0) - bool tcg_op_supported(TCGOpcode op); =20 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args); diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 9dfad2f7bc..91c9c0c478 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -476,7 +476,7 @@ static TCGv gen_op_deposit_reg_v(DisasContext *s, MemOp= ot, int reg, TCGv dest, break; #endif default: - tcg_abort(); + g_assert_not_reached(); } return cpu_regs[reg]; } @@ -660,7 +660,7 @@ static void gen_lea_v_seg(DisasContext *s, MemOp aflag,= TCGv a0, } break; default: - tcg_abort(); + g_assert_not_reached(); } =20 if (ovr_seg >=3D 0) { @@ -765,7 +765,7 @@ static void gen_helper_in_func(MemOp ot, TCGv v, TCGv_i= 32 n) gen_helper_inl(v, cpu_env, n); break; default: - tcg_abort(); + g_assert_not_reached(); } } =20 @@ -782,7 +782,7 @@ static void gen_helper_out_func(MemOp ot, TCGv_i32 v, T= CGv_i32 n) gen_helper_outl(cpu_env, v, n); break; default: - tcg_abort(); + g_assert_not_reached(); } } =20 @@ -1932,7 +1932,7 @@ static void gen_rotc_rm_T1(DisasContext *s, MemOp ot,= int op1, break; #endif default: - tcg_abort(); + g_assert_not_reached(); } } else { switch (ot) { @@ -1951,7 +1951,7 @@ static void gen_rotc_rm_T1(DisasContext *s, MemOp ot,= int op1, break; #endif default: - tcg_abort(); + g_assert_not_reached(); } } /* store */ @@ -2282,7 +2282,7 @@ static AddressParts gen_lea_modrm_0(CPUX86State *env,= DisasContext *s, break; =20 default: - tcg_abort(); + g_assert_not_reached(); } =20 done: @@ -2434,7 +2434,7 @@ static inline uint32_t insn_get(CPUX86State *env, Dis= asContext *s, MemOp ot) ret =3D x86_ldl_code(env, s); break; default: - tcg_abort(); + g_assert_not_reached(); } return ret; } @@ -3723,7 +3723,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); break; default: - tcg_abort(); + g_assert_not_reached(); } break; case 0x99: /* CDQ/CWD */ @@ -3748,7 +3748,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_op_mov_reg_v(s, MO_16, R_EDX, s->T0); break; default: - tcg_abort(); + g_assert_not_reached(); } break; case 0x1af: /* imul Gv, Ev */ diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 2d9b4bbb1f..46b874e94d 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -418,7 +418,7 @@ static int get_mem_index(DisasContext *s) case PSW_ASC_HOME >> FLAG_MASK_PSW_SHIFT: return MMU_HOME_IDX; default: - tcg_abort(); + g_assert_not_reached(); break; } #endif @@ -652,7 +652,7 @@ static void gen_op_calc_cc(DisasContext *s) gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr); break; default: - tcg_abort(); + g_assert_not_reached(); } =20 /* We now have cc in cc_op as constant */ diff --git a/tcg/optimize.c b/tcg/optimize.c index ce05989c39..9614fa3638 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -453,9 +453,7 @@ static uint64_t do_constant_folding_2(TCGOpcode op, uin= t64_t x, uint64_t y) return (uint64_t)x % ((uint64_t)y ? : 1); =20 default: - fprintf(stderr, - "Unrecognized operation %d in do_constant_folding.\n", op); - tcg_abort(); + g_assert_not_reached(); } } =20 @@ -493,7 +491,7 @@ static bool do_constant_folding_cond_32(uint32_t x, uin= t32_t y, TCGCond c) case TCG_COND_GTU: return x > y; default: - tcg_abort(); + g_assert_not_reached(); } } =20 @@ -521,7 +519,7 @@ static bool do_constant_folding_cond_64(uint64_t x, uin= t64_t y, TCGCond c) case TCG_COND_GTU: return x > y; default: - tcg_abort(); + g_assert_not_reached(); } } =20 @@ -541,7 +539,7 @@ static bool do_constant_folding_cond_eq(TCGCond c) case TCG_COND_EQ: return 1; default: - tcg_abort(); + g_assert_not_reached(); } } =20 diff --git a/tcg/tcg.c b/tcg/tcg.c index 100f81edb2..c3a8578951 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3680,7 +3680,7 @@ static void temp_sync(TCGContext *s, TCGTemp *ts, TCG= RegSet allocated_regs, =20 case TEMP_VAL_DEAD: default: - tcg_abort(); + g_assert_not_reached(); } ts->mem_coherent =3D 1; } @@ -3767,7 +3767,7 @@ static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet = required_regs, } } =20 - tcg_abort(); + g_assert_not_reached(); } =20 static TCGReg tcg_reg_alloc_pair(TCGContext *s, TCGRegSet required_regs, @@ -3813,7 +3813,7 @@ static TCGReg tcg_reg_alloc_pair(TCGContext *s, TCGRe= gSet required_regs, } } } - tcg_abort(); + g_assert_not_reached(); } =20 /* Make sure the temporary is in a register. If needed, allocate the regi= ster @@ -3860,7 +3860,7 @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCG= RegSet desired_regs, break; case TEMP_VAL_DEAD: default: - tcg_abort(); + g_assert_not_reached(); } set_temp_val_reg(s, ts, reg); } diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index a091326f84..1315cb92ab 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1778,7 +1778,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, Mem= Op memop, TCGType ext, tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r); break; default: - tcg_abort(); + g_assert_not_reached(); } } =20 @@ -1800,7 +1800,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, Mem= Op memop, tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r); break; default: - tcg_abort(); + g_assert_not_reached(); } } =20 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index d06ac60c15..b4daa97e7a 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2302,7 +2302,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ default: - tcg_abort(); + g_assert_not_reached(); } } =20 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index aa7ee16b25..f4baf6e6e9 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -218,7 +218,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int ty= pe, tcg_patch8(code_ptr, value); break; default: - tcg_abort(); + g_assert_not_reached(); } return true; } @@ -1095,7 +1095,7 @@ static inline void tcg_out_pushi(TCGContext *s, tcg_t= arget_long val) tcg_out_opc(s, OPC_PUSH_Iv, 0, 0, 0); tcg_out32(s, val); } else { - tcg_abort(); + g_assert_not_reached(); } } =20 @@ -1359,7 +1359,7 @@ static void tgen_arithi(TCGContext *s, int c, int r0, return; } =20 - tcg_abort(); + g_assert_not_reached(); } =20 static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) @@ -1523,7 +1523,7 @@ static void tcg_out_brcond2(TCGContext *s, const TCGA= rg *args, label_this, small); break; default: - tcg_abort(); + g_assert_not_reached(); } tcg_out_label(s, label_next); } @@ -1958,7 +1958,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) } break; default: - tcg_abort(); + g_assert_not_reached(); } =20 /* Jump to the code corresponding to next IR of qemu_st */ @@ -2788,7 +2788,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, /* load bits 0..15 */ tcg_out_modrm(s, OPC_MOVL_EvGv | P_DATA16, a2, a0); } else { - tcg_abort(); + g_assert_not_reached(); } break; =20 @@ -2841,7 +2841,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ default: - tcg_abort(); + g_assert_not_reached(); } =20 #undef OP_32_64 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 80748d892e..668bc73ee6 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -798,7 +798,7 @@ static void tcg_out_setcond(TCGContext *s, TCGCond cond= , TCGReg ret, break; =20 default: - tcg_abort(); + g_assert_not_reached(); break; } } @@ -855,7 +855,7 @@ static void tcg_out_brcond(TCGContext *s, TCGCond cond,= TCGReg arg1, break; =20 default: - tcg_abort(); + g_assert_not_reached(); break; } =20 @@ -1337,7 +1337,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) } break; default: - tcg_abort(); + g_assert_not_reached(); } i =3D tcg_out_call_iarg_imm(s, i, oi); =20 @@ -1527,7 +1527,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, } break; default: - tcg_abort(); + g_assert_not_reached(); } } =20 @@ -1775,7 +1775,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, break; =20 default: - tcg_abort(); + g_assert_not_reached(); } } =20 @@ -1848,7 +1848,7 @@ static void tcg_out_qemu_st_unalign(TCGContext *s, TC= GReg lo, TCGReg hi, break; =20 default: - tcg_abort(); + g_assert_not_reached(); } } static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) @@ -2420,7 +2420,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ default: - tcg_abort(); + g_assert_not_reached(); } } =20 diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index afadf9a1e3..e696d153b8 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1509,7 +1509,7 @@ static void tcg_out_cmp(TCGContext *s, int cond, TCGA= rg arg1, TCGArg arg2, break; =20 default: - tcg_abort(); + g_assert_not_reached(); } op |=3D BF(cr) | ((type =3D=3D TCG_TYPE_I64) << 21); =20 @@ -1680,7 +1680,7 @@ static void tcg_out_setcond(TCGContext *s, TCGType ty= pe, TCGCond cond, break; =20 default: - tcg_abort(); + g_assert_not_reached(); } } =20 @@ -1834,7 +1834,7 @@ static void tcg_out_cmp2(TCGContext *s, const TCGArg = *args, break; =20 default: - tcg_abort(); + g_assert_not_reached(); } } =20 @@ -3125,7 +3125,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ default: - tcg_abort(); + g_assert_not_reached(); } } =20 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 844532156b..d07d28bcfd 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1641,7 +1641,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, Mem= Op opc, TCGReg data, break; =20 default: - tcg_abort(); + g_assert_not_reached(); } } =20 @@ -1687,7 +1687,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, Mem= Op opc, TCGReg data, break; =20 default: - tcg_abort(); + g_assert_not_reached(); } } =20 @@ -1818,7 +1818,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, data_reg); break; default: - tcg_abort(); + g_assert_not_reached(); } tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, oi); tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R6, (uintptr_t)lb->raddr); @@ -2645,7 +2645,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ default: - tcg_abort(); + g_assert_not_reached(); } } =20 diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 694f2b9dd4..4ee5732b66 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1701,7 +1701,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ default: - tcg_abort(); + g_assert_not_reached(); } } =20 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index c1d34d7bd1..5309c3ffe1 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -796,7 +796,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ default: - tcg_abort(); + g_assert_not_reached(); } } =20 --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680921960; cv=none; d=zohomail.com; s=zohoarc; b=eRY5xZ+x6pG2h83LB9aORO+0TGddfI7tFSry5jCVnuA1ooh5zzXsbXiCKez0jrXLeR1oXTidh8XFKaZSdeUi5Dk9KQfhHfRcEdSxdxYgWCc4LCYc/PmSdYMx41BT2dM+dw+MTU8v0ltjdrpAinwjwzNofQAvIUG2904zt6i08DY= ARC-Message-Signature: i=1; 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([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921799; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E3hqrO6JYyROHM0s8wk6ulIEMRo0UNCl9y6pJbnLNsA=; b=iMhkKu+NYW65orGWYSrbl2CkP3yX6doZr+lhU7gcpH/fgkm5aqH4M/2265DzrpvHrt kIeUT/RFFY5bNv1IbJTSmgjOPQhxy9lQ6t0yTdWwWUU6YjCbl5BX/m3KKGkyOe35Otg6 hGqkkk5tmaep4hcXIUxzfg4AYXbDWpvzPkcB7FNLTxWY5vAMjgA1DN3VqXnjn7Mdr50h Cs+qO7m+vSAm2bwg30Oh9UNmIhjArhKP9YWJDSskXDYkFZVLOu9TepfL0HnY/CvhHNNu pBxTIoAu1f79nyxA59iCtqxB+ArgZ8O2ZEIVUnTBsKW8JTXgPpt9GREPOZ8dFp0Sl15v bNJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921799; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E3hqrO6JYyROHM0s8wk6ulIEMRo0UNCl9y6pJbnLNsA=; b=h6d3YlTFABUcnm6oTqP+wpcYpOuTO+Qx2kZCc4dUuLI9ZSbsx2k262xJBu/CZKFwho ZajvTUtz2lFoZf+bCNBbYJfcCNpmjVry8qwrTG18PbUlSDrtcgo/NnPnD4kxHO/AQeNo oLe37VBuUSNydQ7YLm8OZ2qvp2hGi9IgxBl/mzCGcxHmIBeXn6H+rlp4GqYBC8y8G/2c 53Sv3D3ZE8qD2kWlEnAnkBIuTxHpk2cnze5F7O9Dr+N27yd0bIwA+RPn+IAMcuEpCzMk 8iN6YyX9nfm6OvypOH9U/gqkfVnIMuwNrnmPVMSxWD1lvhzEx8FKBZjSviwi2OWLmanz R0EA== X-Gm-Message-State: AAQBX9e4914kHOPgOWcuFMEoCye42FlRnD/QAdpeKgwzdqkosVw+zUjS eBU7LcVNa+c7xncaRL0D2a6hKBAXg7mYROBwedM= X-Google-Smtp-Source: AKy350YHwbVXiizBnKAe+xuewXOJEk3jD4yPyYqFMx7njzgN+5RYZgjnCdirOocRq9FM2W0Rmgyg4Q== X-Received: by 2002:a17:902:da86:b0:19e:6700:174 with SMTP id j6-20020a170902da8600b0019e67000174mr5626436plx.25.1680921798800; Fri, 07 Apr 2023 19:43:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 03/42] tcg: Split out tcg_out_ext8s Date: Fri, 7 Apr 2023 19:42:35 -0700 Message-Id: <20230408024314.3357414-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680921961474100003 Content-Type: text/plain; charset="utf-8" We will need a backend interface for performing 8-bit sign-extend. Use it in tcg_reg_alloc_op in the meantime. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg.c | 21 ++++++++++++++++----- tcg/aarch64/tcg-target.c.inc | 11 +++++++---- tcg/arm/tcg-target.c.inc | 10 ++++------ tcg/i386/tcg-target.c.inc | 10 +++++----- tcg/loongarch64/tcg-target.c.inc | 11 ++++------- tcg/mips/tcg-target.c.inc | 12 ++++++++---- tcg/ppc/tcg-target.c.inc | 10 ++++------ tcg/riscv/tcg-target.c.inc | 9 +++------ tcg/s390x/tcg-target.c.inc | 10 +++------- tcg/sparc64/tcg-target.c.inc | 7 +++++++ tcg/tci/tcg-target.c.inc | 21 ++++++++++++++++++++- 11 files changed, 81 insertions(+), 51 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index c3a8578951..76ba3e28cd 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -105,6 +105,7 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCG= Reg ret, TCGReg arg1, static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); +static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg = arg); static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g); static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); static void tcg_out_goto_tb(TCGContext *s, int which); @@ -4496,11 +4497,21 @@ static void tcg_reg_alloc_op(TCGContext *s, const T= CGOp *op) } =20 /* emit instruction */ - if (def->flags & TCG_OPF_VECTOR) { - tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op), - new_args, const_args); - } else { - tcg_out_op(s, op->opc, new_args, const_args); + switch (op->opc) { + case INDEX_op_ext8s_i32: + tcg_out_ext8s(s, TCG_TYPE_I32, new_args[0], new_args[1]); + break; + case INDEX_op_ext8s_i64: + tcg_out_ext8s(s, TCG_TYPE_I64, new_args[0], new_args[1]); + break; + default: + if (def->flags & TCG_OPF_VECTOR) { + tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op), + new_args, const_args); + } else { + tcg_out_op(s, op->opc, new_args, const_args); + } + break; } =20 /* move the outputs in the correct register if needed */ diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 1315cb92ab..4f4f814293 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1419,6 +1419,11 @@ static inline void tcg_out_sxt(TCGContext *s, TCGTyp= e ext, MemOp s_bits, tcg_out_sbfm(s, ext, rd, rn, 0, bits); } =20 +static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg r= n) +{ + tcg_out_sxt(s, type, MO_8, rd, rn); +} + static inline void tcg_out_uxt(TCGContext *s, MemOp s_bits, TCGReg rd, TCGReg rn) { @@ -2230,10 +2235,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; =20 - case INDEX_op_ext8s_i64: - case INDEX_op_ext8s_i32: - tcg_out_sxt(s, ext, MO_8, a0, a1); - break; case INDEX_op_ext16s_i64: case INDEX_op_ext16s_i32: tcg_out_sxt(s, ext, MO_16, a0, a1); @@ -2310,6 +2311,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ + case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ + case INDEX_op_ext8s_i64: default: g_assert_not_reached(); } diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index b4daa97e7a..04a860897f 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -958,10 +958,10 @@ static void tcg_out_udiv(TCGContext *s, ARMCond cond, tcg_out32(s, 0x0730f010 | (cond << 28) | (rd << 16) | rn | (rm << 8)); } =20 -static void tcg_out_ext8s(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg r= n) +static void tcg_out_ext8s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) { /* sxtb */ - tcg_out32(s, 0x06af0070 | (cond << 28) | (rd << 12) | rn); + tcg_out32(s, 0x06af0070 | (COND_AL << 28) | (rd << 12) | rn); } =20 static void __attribute__((unused)) @@ -1533,7 +1533,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) datahi =3D lb->datahi_reg; switch (opc & MO_SSIZE) { case MO_SB: - tcg_out_ext8s(s, COND_AL, datalo, TCG_REG_R0); + tcg_out_ext8s(s, TCG_TYPE_I32, datalo, TCG_REG_R0); break; case MO_SW: tcg_out_ext16s(s, COND_AL, datalo, TCG_REG_R0); @@ -2244,9 +2244,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_bswap32(s, COND_AL, args[0], args[1]); break; =20 - case INDEX_op_ext8s_i32: - tcg_out_ext8s(s, COND_AL, args[0], args[1]); - break; case INDEX_op_ext16s_i32: tcg_out_ext16s(s, COND_AL, args[0], args[1]); break; @@ -2301,6 +2298,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ + case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ default: g_assert_not_reached(); } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index f4baf6e6e9..532fc8e283 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1266,8 +1266,9 @@ static inline void tcg_out_ext8u(TCGContext *s, int d= est, int src) tcg_out_modrm(s, OPC_MOVZBL + P_REXB_RM, dest, src); } =20 -static void tcg_out_ext8s(TCGContext *s, int dest, int src, int rexw) +static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg= src) { + int rexw =3D type =3D=3D TCG_TYPE_I32 ? 0 : P_REXW; /* movsbl */ tcg_debug_assert(src < 4 || TCG_TARGET_REG_BITS =3D=3D 64); tcg_out_modrm(s, OPC_MOVSBL + P_REXB_RM + rexw, dest, src); @@ -1929,7 +1930,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) data_reg =3D l->datalo_reg; switch (opc & MO_SSIZE) { case MO_SB: - tcg_out_ext8s(s, data_reg, TCG_REG_EAX, rexw); + tcg_out_ext8s(s, l->type, data_reg, TCG_REG_EAX); break; case MO_SW: tcg_out_ext16s(s, data_reg, TCG_REG_EAX, rexw); @@ -2669,9 +2670,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, a0); break; =20 - OP_32_64(ext8s): - tcg_out_ext8s(s, a0, a1, rexw); - break; OP_32_64(ext16s): tcg_out_ext16s(s, a0, a1, rexw); break; @@ -2840,6 +2838,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ + case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ + case INDEX_op_ext8s_i64: default: g_assert_not_reached(); } diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index c5f55afd68..a96f655c44 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -441,7 +441,7 @@ static void tcg_out_ext32u(TCGContext *s, TCGReg ret, T= CGReg arg) tcg_out_opc_bstrpick_d(s, ret, arg, 0, 31); } =20 -static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) +static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg = arg) { tcg_out_opc_sext_b(s, ret, arg); } @@ -893,7 +893,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TC= GLabelQemuLdst *l) =20 switch (opc & MO_SSIZE) { case MO_SB: - tcg_out_ext8s(s, l->datalo_reg, TCG_REG_A0); + tcg_out_ext8s(s, type, l->datalo_reg, TCG_REG_A0); break; case MO_SW: tcg_out_ext16s(s, l->datalo_reg, TCG_REG_A0); @@ -1246,11 +1246,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); break; =20 - case INDEX_op_ext8s_i32: - case INDEX_op_ext8s_i64: - tcg_out_ext8s(s, a0, a1); - break; - case INDEX_op_ext8u_i32: case INDEX_op_ext8u_i64: tcg_out_ext8u(s, a0, a1); @@ -1627,6 +1622,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ + case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ + case INDEX_op_ext8s_i64: default: g_assert_not_reached(); } diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 668bc73ee6..8fc9d02bd5 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -552,6 +552,12 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } =20 +static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg r= s) +{ + tcg_debug_assert(TCG_TARGET_HAS_ext8s_i32); + tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -2245,10 +2251,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_not_i64: i1 =3D OPC_NOR; goto do_unary; - case INDEX_op_ext8s_i32: - case INDEX_op_ext8s_i64: - i1 =3D OPC_SEB; - goto do_unary; case INDEX_op_ext16s_i32: case INDEX_op_ext16s_i64: i1 =3D OPC_SEH; @@ -2419,6 +2421,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ + case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ + case INDEX_op_ext8s_i64: default: g_assert_not_reached(); } diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index e696d153b8..26c3a72017 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -774,7 +774,7 @@ static inline void tcg_out_rlw(TCGContext *s, int op, T= CGReg ra, TCGReg rs, tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me)); } =20 -static inline void tcg_out_ext8s(TCGContext *s, TCGReg dst, TCGReg src) +static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dst, TCGReg = src) { tcg_out32(s, EXTSB | RA(dst) | RS(src)); } @@ -2625,7 +2625,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ld8s_i32: case INDEX_op_ld8s_i64: tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); - tcg_out_ext8s(s, args[0], args[0]); + tcg_out_ext8s(s, TCG_TYPE_REG, args[0], args[0]); break; case INDEX_op_ld16u_i32: case INDEX_op_ld16u_i64: @@ -2973,10 +2973,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_st(s, args, true); break; =20 - case INDEX_op_ext8s_i32: - case INDEX_op_ext8s_i64: - tcg_out_ext8s(s, args[0], args[1]); - break; case INDEX_op_ext16s_i32: case INDEX_op_ext16s_i64: tcg_out_ext16s(s, args[0], args[1]); @@ -3124,6 +3120,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ + case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ + case INDEX_op_ext8s_i64: default: g_assert_not_reached(); } diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 558de127ef..04b27f6887 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -585,7 +585,7 @@ static void tcg_out_ext32u(TCGContext *s, TCGReg ret, T= CGReg arg) tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32); } =20 -static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) +static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg = arg) { tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24); tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24); @@ -1612,11 +1612,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_ext32u(s, a0, a1); break; =20 - case INDEX_op_ext8s_i32: - case INDEX_op_ext8s_i64: - tcg_out_ext8s(s, a0, a1); - break; - case INDEX_op_ext16s_i32: case INDEX_op_ext16s_i64: tcg_out_ext16s(s, a0, a1); @@ -1651,6 +1646,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ + case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ + case INDEX_op_ext8s_i64: default: g_assert_not_reached(); } diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index d07d28bcfd..1232ccb122 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1092,7 +1092,7 @@ static inline void tcg_out_risbg(TCGContext *s, TCGRe= g dest, TCGReg src, tcg_out16(s, (ofs << 8) | (RIEf_RISBG & 0xff)); } =20 -static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg sr= c) +static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg= src) { tcg_out_insn(s, RRE, LGBR, dest, src); } @@ -2233,9 +2233,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, } break; =20 - case INDEX_op_ext8s_i32: - tgen_ext8s(s, TCG_TYPE_I32, args[0], args[1]); - break; case INDEX_op_ext16s_i32: tgen_ext16s(s, TCG_TYPE_I32, args[0], args[1]); break; @@ -2537,9 +2534,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, } break; =20 - case INDEX_op_ext8s_i64: - tgen_ext8s(s, TCG_TYPE_I64, args[0], args[1]); - break; case INDEX_op_ext16s_i64: tgen_ext16s(s, TCG_TYPE_I64, args[0], args[1]); break; @@ -2644,6 +2638,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ + case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ + case INDEX_op_ext8s_i64: default: g_assert_not_reached(); } diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 4ee5732b66..7952cfc4da 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -496,6 +496,11 @@ static void tcg_out_movi(TCGContext *s, TCGType type, tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T2); } =20 +static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg r= s) +{ + g_assert_not_reached(); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -1700,6 +1705,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ + case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ + case INDEX_op_ext8s_i64: default: g_assert_not_reached(); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 5309c3ffe1..029508e308 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -557,6 +557,24 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } =20 +static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg r= s) +{ + switch (type) { + case TCG_TYPE_I32: + tcg_debug_assert(TCG_TARGET_HAS_ext8s_i32); + tcg_out_op_rr(s, INDEX_op_ext8s_i32, rd, rs); + break; +#if TCG_TARGET_REG_BITS =3D=3D 64 + case TCG_TYPE_I64: + tcg_debug_assert(TCG_TARGET_HAS_ext8s_i64); + tcg_out_op_rr(s, INDEX_op_ext8s_i64, rd, rs); + break; +#endif + default: + g_assert_not_reached(); + } +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -715,7 +733,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */ - CASE_32_64(ext8s) /* Optional (TCG_TARGET_HAS_ext8s_*). */ CASE_32_64(ext8u) /* Optional (TCG_TARGET_HAS_ext8u_*). */ CASE_32_64(ext16s) /* Optional (TCG_TARGET_HAS_ext16s_*). */ CASE_32_64(ext16u) /* Optional (TCG_TARGET_HAS_ext16u_*). */ @@ -795,6 +812,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ + case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ + case INDEX_op_ext8s_i64: default: g_assert_not_reached(); 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([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921800; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j0Ph8Ug+s0n+stGqfOvAQ1H9lMffwJrULYbE3AOr9sA=; b=DjPHMkryhRU7Lmqe+L53itYmmbASuHPQZhFtshN/0LJ84QPfqxsNtzDTJTf1Vbr/6V ON8keKY5CF+zBcTw/dEpoRoZ4Qy2TF2/m1DQMS4NNw36UaWM2z4nQNh7/mzMwhuZFC0n Up3t8VDPVkMaidCCIqnifaW5c6QSeADFMdAbUjOuKAH9Ko4k5o/24cSYaIsAC5peOPLk fWC9pZUIz950W8gaqZGCXGv5aFdmX+uADZNKk1NGioBMYvyfJk6Ku4AsYbkTi9STgVxX K1r9kyfs/gaaoJ51lD6d94Dp4+uCN5iEFmjI7gU7S+2uzUg7zD8i1fBY/by34yq47Lh4 2CaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921800; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j0Ph8Ug+s0n+stGqfOvAQ1H9lMffwJrULYbE3AOr9sA=; b=Es/PqYTbvJBkZjHCCShZo0kvZTRFPKpEqlU2c4gnog58/TC5bbGZvBIpHX7Iz3wQ8/ cZxjfgXu9qVyFUgXPJSB4H/GAnrTJ6+kts5e4aZ6AgWgBrksKBvGrMX+fh5CKAap+qsj laMaZwudoeKZPwPJT6CAS+o5PD1IWmFfu9qZjNQBC6iTOGNu7HrhDOjgMWJxhalF4GOX hiZg/zF9dW3QJ2rBZwckURWFZIBOwi+XMGy3r97L1DNDXKNNzyoLvxjQ1UK48EXlHNNx JM82M48Hh91MROJOXSlMCe9L2QQ9CSPFtsH0gDk/AIsfagr6kteQLbvKj72zHhyrL2sg RiFA== X-Gm-Message-State: AAQBX9cBTdF030gSl6bMEBCo+B17YOL41aRjUv54cBKfa3HFiujkqZ/E yD4WhWlITdSq2pSqMOOZmkQwIjOvtIBktXqn2uk= X-Google-Smtp-Source: AKy350Z7tAeOhDzbGV4tgRM3GHztw0QkbPIxUgXIp/thCiuILo2y1P7XH0StPPFtVaeFFdqTX5W/Ig== X-Received: by 2002:a17:90b:3847:b0:246:696f:b1f1 with SMTP id nl7-20020a17090b384700b00246696fb1f1mr2503545pjb.6.1680921799746; Fri, 07 Apr 2023 19:43:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 04/42] tcg: Split out tcg_out_ext8u Date: Fri, 7 Apr 2023 19:42:36 -0700 Message-Id: <20230408024314.3357414-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680921983460100011 Content-Type: text/plain; charset="utf-8" We will need a backend interface for performing 8-bit zero-extend. Use it in tcg_reg_alloc_op in the meantime. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg.c | 5 +++++ tcg/aarch64/tcg-target.c.inc | 11 +++++++---- tcg/arm/tcg-target.c.inc | 12 +++++++++--- tcg/i386/tcg-target.c.inc | 7 +++---- tcg/loongarch64/tcg-target.c.inc | 7 ++----- tcg/mips/tcg-target.c.inc | 9 ++++++++- tcg/ppc/tcg-target.c.inc | 7 +++++++ tcg/riscv/tcg-target.c.inc | 7 ++----- tcg/s390x/tcg-target.c.inc | 14 +++++--------- tcg/sparc64/tcg-target.c.inc | 9 ++++++++- tcg/tci/tcg-target.c.inc | 14 +++++++++++++- 11 files changed, 69 insertions(+), 33 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 76ba3e28cd..b02ffc5679 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -106,6 +106,7 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg = arg); +static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g); static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); static void tcg_out_goto_tb(TCGContext *s, int which); @@ -4504,6 +4505,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TC= GOp *op) case INDEX_op_ext8s_i64: tcg_out_ext8s(s, TCG_TYPE_I64, new_args[0], new_args[1]); break; + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + tcg_out_ext8u(s, new_args[0], new_args[1]); + break; default: if (def->flags & TCG_OPF_VECTOR) { tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op), diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 4f4f814293..cca91363ce 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1432,6 +1432,11 @@ static inline void tcg_out_uxt(TCGContext *s, MemOp = s_bits, tcg_out_ubfm(s, 0, rd, rn, 0, bits); } =20 +static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rn) +{ + tcg_out_uxt(s, MO_8, rd, rn); +} + static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd, TCGReg rn, int64_t aimm) { @@ -2243,10 +2248,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext32s_i64: tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a1); break; - case INDEX_op_ext8u_i64: - case INDEX_op_ext8u_i32: - tcg_out_uxt(s, MO_8, a0, a1); - break; case INDEX_op_ext16u_i64: case INDEX_op_ext16u_i32: tcg_out_uxt(s, MO_16, a0, a1); @@ -2313,6 +2314,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: default: g_assert_not_reached(); } diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 04a860897f..b99f08a54b 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -964,8 +964,13 @@ static void tcg_out_ext8s(TCGContext *s, TCGType t, TC= GReg rd, TCGReg rn) tcg_out32(s, 0x06af0070 | (COND_AL << 28) | (rd << 12) | rn); } =20 +static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rn) +{ + tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff); +} + static void __attribute__((unused)) -tcg_out_ext8u(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) +tcg_out_ext8u_cond(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) { tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff); } @@ -1365,8 +1370,8 @@ static TCGReg NAME(TCGContext *s, TCGReg argreg, ARGT= YPE arg) \ =20 DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32, uint32_t, tcg_out_movi32, (tcg_out_movi32(s, COND_AL, TCG_REG_TMP, arg), arg =3D TCG_REG_TMP)) -DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8, TCGReg, tcg_out_ext8u, - (tcg_out_ext8u(s, COND_AL, TCG_REG_TMP, arg), arg =3D TCG_REG_TMP)) +DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8, TCGReg, tcg_out_ext8u_cond, + (tcg_out_ext8u_cond(s, COND_AL, TCG_REG_TMP, arg), arg =3D TCG_REG_TMP= )) DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16, TCGReg, tcg_out_ext16u, (tcg_out_ext16u(s, COND_AL, TCG_REG_TMP, arg), arg =3D TCG_REG_TMP)) DEFINE_TCG_OUT_ARG(tcg_out_arg_reg32, TCGReg, tcg_out_mov_reg, ) @@ -2299,6 +2304,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ + case INDEX_op_ext8u_i32: default: g_assert_not_reached(); } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 532fc8e283..cb4bbf2071 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1259,7 +1259,7 @@ static inline void tcg_out_rolw_8(TCGContext *s, int = reg) tcg_out_shifti(s, SHIFT_ROL + P_DATA16, reg, 8); } =20 -static inline void tcg_out_ext8u(TCGContext *s, int dest, int src) +static void tcg_out_ext8u(TCGContext *s, TCGReg dest, TCGReg src) { /* movzbl */ tcg_debug_assert(src < 4 || TCG_TARGET_REG_BITS =3D=3D 64); @@ -2673,9 +2673,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, OP_32_64(ext16s): tcg_out_ext16s(s, a0, a1, rexw); break; - OP_32_64(ext8u): - tcg_out_ext8u(s, a0, a1); - break; OP_32_64(ext16u): tcg_out_ext16u(s, a0, a1); break; @@ -2840,6 +2837,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: default: g_assert_not_reached(); } diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index a96f655c44..a206b9cfc5 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1246,11 +1246,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); break; =20 - case INDEX_op_ext8u_i32: - case INDEX_op_ext8u_i64: - tcg_out_ext8u(s, a0, a1); - break; - case INDEX_op_ext16s_i32: case INDEX_op_ext16s_i64: tcg_out_ext16s(s, a0, a1); @@ -1624,6 +1619,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: default: g_assert_not_reached(); } diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 8fc9d02bd5..5a712e3da5 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -558,6 +558,11 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type,= TCGReg rd, TCGReg rs) tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs); } =20 +static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -1099,7 +1104,7 @@ static int tcg_out_call_iarg_reg8(TCGContext *s, int = i, TCGReg arg) if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { tmp =3D tcg_target_call_iarg_regs[i]; } - tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff); + tcg_out_ext8u(s, tmp, arg); return tcg_out_call_iarg_reg(s, i, tmp); } =20 @@ -2423,6 +2428,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: default: g_assert_not_reached(); } diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 26c3a72017..61f489eae1 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -779,6 +779,11 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type,= TCGReg dst, TCGReg src) tcg_out32(s, EXTSB | RA(dst) | RS(src)); } =20 +static void tcg_out_ext8u(TCGContext *s, TCGReg dst, TCGReg src) +{ + tcg_out32(s, ANDI | SAI(src, dst, 0xff)); +} + static inline void tcg_out_ext16s(TCGContext *s, TCGReg dst, TCGReg src) { tcg_out32(s, EXTSH | RA(dst) | RS(src)); @@ -3122,6 +3127,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: default: g_assert_not_reached(); } diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 04b27f6887..d9b08014ce 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1597,11 +1597,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_st(s, args, true); break; =20 - case INDEX_op_ext8u_i32: - case INDEX_op_ext8u_i64: - tcg_out_ext8u(s, a0, a1); - break; - case INDEX_op_ext16u_i32: case INDEX_op_ext16u_i64: tcg_out_ext16u(s, a0, a1); @@ -1648,6 +1643,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: default: g_assert_not_reached(); } diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 1232ccb122..338a91c591 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1097,7 +1097,7 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type= , TCGReg dest, TCGReg src) tcg_out_insn(s, RRE, LGBR, dest, src); } =20 -static void tgen_ext8u(TCGContext *s, TCGType type, TCGReg dest, TCGReg sr= c) +static void tcg_out_ext8u(TCGContext *s, TCGReg dest, TCGReg src) { tcg_out_insn(s, RRE, LLGCR, dest, src); } @@ -1153,7 +1153,7 @@ static void tgen_andi(TCGContext *s, TCGType type, TC= GReg dest, uint64_t val) return; } if ((val & valid) =3D=3D 0xff) { - tgen_ext8u(s, TCG_TYPE_I64, dest, dest); + tcg_out_ext8u(s, dest, dest); return; } if ((val & valid) =3D=3D 0xffff) { @@ -1806,7 +1806,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) } switch (opc & MO_SIZE) { case MO_UB: - tgen_ext8u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg); + tcg_out_ext8u(s, TCG_REG_R4, data_reg); break; case MO_UW: tgen_ext16u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg); @@ -2236,9 +2236,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_ext16s_i32: tgen_ext16s(s, TCG_TYPE_I32, args[0], args[1]); break; - case INDEX_op_ext8u_i32: - tgen_ext8u(s, TCG_TYPE_I32, args[0], args[1]); - break; case INDEX_op_ext16u_i32: tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]); break; @@ -2541,9 +2538,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_ext32s_i64: tgen_ext32s(s, args[0], args[1]); break; - case INDEX_op_ext8u_i64: - tgen_ext8u(s, TCG_TYPE_I64, args[0], args[1]); - break; case INDEX_op_ext16u_i64: tgen_ext16u(s, TCG_TYPE_I64, args[0], args[1]); break; @@ -2640,6 +2634,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: default: g_assert_not_reached(); } diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 7952cfc4da..4792b04b54 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -501,6 +501,11 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type,= TCGReg rd, TCGReg rs) g_assert_not_reached(); } =20 +static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_arithi(s, rd, rs, 0xff, ARITH_AND); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -883,7 +888,7 @@ static void emit_extend(TCGContext *s, TCGReg r, int op) */ switch (op & MO_SIZE) { case MO_8: - tcg_out_arithi(s, r, r, 0xff, ARITH_AND); + tcg_out_ext8u(s, r, r); break; case MO_16: tcg_out_arithi(s, r, r, 16, SHIFT_SLL); @@ -1707,6 +1712,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: default: g_assert_not_reached(); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 029508e308..e946d9165e 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -575,6 +575,17 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type,= TCGReg rd, TCGReg rs) } } =20 +static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) +{ + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_debug_assert(TCG_TARGET_HAS_ext8u_i64); + tcg_out_op_rr(s, INDEX_op_ext8u_i64, rd, rs); + } else { + tcg_debug_assert(TCG_TARGET_HAS_ext8u_i32); + tcg_out_op_rr(s, INDEX_op_ext8u_i32, rd, rs); + } +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -733,7 +744,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */ - CASE_32_64(ext8u) /* Optional (TCG_TARGET_HAS_ext8u_*). */ CASE_32_64(ext16s) /* Optional (TCG_TARGET_HAS_ext16s_*). */ CASE_32_64(ext16u) /* Optional (TCG_TARGET_HAS_ext16u_*). */ CASE_64(ext32s) /* Optional (TCG_TARGET_HAS_ext32s_i64). */ @@ -814,6 +824,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: default: g_assert_not_reached(); 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([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921801; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gYwSzduz8Bue5pevbs9+ksI0Zfn7jotFrOGIqHRIGwg=; b=HCE4Xw4paLVa7YDIXgo/srr18xH8lDfmtV565neqYDLECSoVMxASz034Jte6G27Gld Y6oUYrYWxbxTyOH8fqxERgzd6v2Egc6QxK8IfrD0XEvAT6G4CbnaNJQzqEwMa3X5lOsH k1gZGMOoNzilv2vWkMNjsD49LWUkLSTN6/65nG+QSMwk6lvLN+//XcgkGAN0CKRN2cEX pA1oTp4Cu0DaO4BvYiUFNK9MkdbriAmMNHi75Nt1pWAFAUfdGIw8HV1aTtEslCz4vYoG zJuelrCfOvIpsvPCmukNgXIMIb7GtfXsi+/H6PkonoDV3SsXAgJQuScW6yQBHJA63BbA UbMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921801; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gYwSzduz8Bue5pevbs9+ksI0Zfn7jotFrOGIqHRIGwg=; b=VMTG7gS9ZUjUs/hCcFKEh8/NpWy+w9oOg8nV/2MSyvH93zUBHj1gEvVwL3iSn+BpiE /c3Bkv2/mH5HE6QJDwrwdgxc+QXPN/zTsRwYm61fx0Pm9j6tT9UstijQOdoZrNe6cxKt +PRZlVo/zLhH+3kHrEzouiDeMlWD2ZRLVmPtfvDgMcwzCfwhOe5EWLJwNU/d60WShLA6 AGqPvY8Lax55WlC1nkUH2xkQB2qL2lzzgIQPKBF8ILXjKbFqNRJMjgfbTZdAEIeKYZDW 6O43RXxd6n7odsdJRV6qAwGTbVbaVKrsJbyZyUceiEX57OGmS+dO8YqfHn8tzbFBK7NH Odrw== X-Gm-Message-State: AAQBX9d+IEfFfF7MJqK+vzSovNmSVFqOwQuXOU9I3Npl1zqnaQwgqJPw tewck7pMHozRYlE/IN7vf7PrtZoY3jSsMwshEyY= X-Google-Smtp-Source: AKy350bf5Ozi9g5WW2UF3LBC36SYBVv3KDOI+hgvmiGHK0npi+Se00ETVwqzS69faVE4UstmOgpb/w== X-Received: by 2002:a17:90a:bc85:b0:246:634d:a89c with SMTP id x5-20020a17090abc8500b00246634da89cmr3147958pjr.41.1680921801382; Fri, 07 Apr 2023 19:43:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 05/42] tcg: Split out tcg_out_ext16s Date: Fri, 7 Apr 2023 19:42:37 -0700 Message-Id: <20230408024314.3357414-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922000034100003 Content-Type: text/plain; charset="utf-8" We will need a backend interface for performing 16-bit sign-extend. Use it in tcg_reg_alloc_op in the meantime. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg.c | 7 +++++++ tcg/aarch64/tcg-target.c.inc | 13 ++++++++----- tcg/arm/tcg-target.c.inc | 10 ++++------ tcg/i386/tcg-target.c.inc | 16 ++++++++-------- tcg/loongarch64/tcg-target.c.inc | 13 +++++-------- tcg/mips/tcg-target.c.inc | 11 ++++++++--- tcg/ppc/tcg-target.c.inc | 12 +++++------- tcg/riscv/tcg-target.c.inc | 9 +++------ tcg/s390x/tcg-target.c.inc | 12 ++++-------- tcg/sparc64/tcg-target.c.inc | 7 +++++++ tcg/tci/tcg-target.c.inc | 21 ++++++++++++++++++++- 11 files changed, 79 insertions(+), 52 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index b02ffc5679..739f92c2ee 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -106,6 +106,7 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TC= GReg ret, TCGReg arg); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg = arg); +static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg= arg); static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g); static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); @@ -4509,6 +4510,12 @@ static void tcg_reg_alloc_op(TCGContext *s, const TC= GOp *op) case INDEX_op_ext8u_i64: tcg_out_ext8u(s, new_args[0], new_args[1]); break; + case INDEX_op_ext16s_i32: + tcg_out_ext16s(s, TCG_TYPE_I32, new_args[0], new_args[1]); + break; + case INDEX_op_ext16s_i64: + tcg_out_ext16s(s, TCG_TYPE_I64, new_args[0], new_args[1]); + break; default: if (def->flags & TCG_OPF_VECTOR) { tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op), diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index cca91363ce..3527c14d04 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1424,6 +1424,11 @@ static void tcg_out_ext8s(TCGContext *s, TCGType typ= e, TCGReg rd, TCGReg rn) tcg_out_sxt(s, type, MO_8, rd, rn); } =20 +static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg = rn) +{ + tcg_out_sxt(s, type, MO_16, rd, rn); +} + static inline void tcg_out_uxt(TCGContext *s, MemOp s_bits, TCGReg rd, TCGReg rn) { @@ -2233,17 +2238,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_rev(s, TCG_TYPE_I32, MO_16, a0, a1); if (a2 & TCG_BSWAP_OS) { /* Output must be sign-extended. */ - tcg_out_sxt(s, ext, MO_16, a0, a0); + tcg_out_ext16s(s, ext, a0, a0); } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) =3D=3D TCG_BSWAP_O= Z) { /* Output must be zero-extended, but input isn't. */ tcg_out_uxt(s, MO_16, a0, a0); } break; =20 - case INDEX_op_ext16s_i64: - case INDEX_op_ext16s_i32: - tcg_out_sxt(s, ext, MO_16, a0, a1); - break; case INDEX_op_ext_i32_i64: case INDEX_op_ext32s_i64: tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a1); @@ -2316,6 +2317,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i64: + case INDEX_op_ext16s_i32: default: g_assert_not_reached(); } diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index b99f08a54b..cddf977a58 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -975,10 +975,10 @@ tcg_out_ext8u_cond(TCGContext *s, ARMCond cond, TCGRe= g rd, TCGReg rn) tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff); } =20 -static void tcg_out_ext16s(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg = rn) +static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) { /* sxth */ - tcg_out32(s, 0x06bf0070 | (cond << 28) | (rd << 12) | rn); + tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn); } =20 static void tcg_out_ext16u(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg = rn) @@ -1541,7 +1541,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) tcg_out_ext8s(s, TCG_TYPE_I32, datalo, TCG_REG_R0); break; case MO_SW: - tcg_out_ext16s(s, COND_AL, datalo, TCG_REG_R0); + tcg_out_ext16s(s, TCG_TYPE_I32, datalo, TCG_REG_R0); break; default: tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); @@ -2249,9 +2249,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_bswap32(s, COND_AL, args[0], args[1]); break; =20 - case INDEX_op_ext16s_i32: - tcg_out_ext16s(s, COND_AL, args[0], args[1]); - break; case INDEX_op_ext16u_i32: tcg_out_ext16u(s, COND_AL, args[0], args[1]); break; @@ -2305,6 +2302,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_ext8u_i32: + case INDEX_op_ext16s_i32: default: g_assert_not_reached(); } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index cb4bbf2071..9cbf8a90f4 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1280,8 +1280,9 @@ static inline void tcg_out_ext16u(TCGContext *s, int = dest, int src) tcg_out_modrm(s, OPC_MOVZWL, dest, src); } =20 -static inline void tcg_out_ext16s(TCGContext *s, int dest, int src, int re= xw) +static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGRe= g src) { + int rexw =3D type =3D=3D TCG_TYPE_I32 ? 0 : P_REXW; /* movsw[lq] */ tcg_out_modrm(s, OPC_MOVSWL + rexw, dest, src); } @@ -1891,7 +1892,6 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) MemOp opc =3D get_memop(oi); TCGReg data_reg; tcg_insn_unit **label_ptr =3D &l->label_ptr[0]; - int rexw =3D (l->type =3D=3D TCG_TYPE_I64 ? P_REXW : 0); =20 /* resolve label address */ tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4); @@ -1933,7 +1933,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) tcg_out_ext8s(s, l->type, data_reg, TCG_REG_EAX); break; case MO_SW: - tcg_out_ext16s(s, data_reg, TCG_REG_EAX, rexw); + tcg_out_ext16s(s, l->type, data_reg, TCG_REG_EAX); break; #if TCG_TARGET_REG_BITS =3D=3D 64 case MO_SL: @@ -2153,6 +2153,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, TCGReg base, int index, intptr_t ofs, int seg, bool is64, MemOp memop) { + TCGType type =3D is64 ? TCG_TYPE_I64 : TCG_TYPE_I32; bool use_movbe =3D false; int rexw =3D is64 * P_REXW; int movop =3D OPC_MOVL_GvEv; @@ -2195,7 +2196,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, if (use_movbe) { tcg_out_modrm_sib_offset(s, OPC_MOVBE_GyMy + P_DATA16 + seg, datalo, base, index, 0, ofs); - tcg_out_ext16s(s, datalo, datalo, rexw); + tcg_out_ext16s(s, type, datalo, datalo); } else { tcg_out_modrm_sib_offset(s, OPC_MOVSWL + rexw + seg, datalo, base, index, 0, ofs); @@ -2670,9 +2671,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, a0); break; =20 - OP_32_64(ext16s): - tcg_out_ext16s(s, a0, a1, rexw); - break; OP_32_64(ext16u): tcg_out_ext16u(s, a0, a1); break; @@ -2816,7 +2814,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, if (a1 < 4 && a0 < 8) { tcg_out_modrm(s, OPC_MOVSBL, a0, a1 + 4); } else { - tcg_out_ext16s(s, a0, a1, 0); + tcg_out_ext16s(s, TCG_TYPE_I32, a0, a1); tcg_out_shifti(s, SHIFT_SAR, a0, 8); } break; @@ -2839,6 +2837,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: default: g_assert_not_reached(); } diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index a206b9cfc5..a365fbcf8f 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -446,7 +446,7 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type, = TCGReg ret, TCGReg arg) tcg_out_opc_sext_b(s, ret, arg); } =20 -static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) +static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg= arg) { tcg_out_opc_sext_h(s, ret, arg); } @@ -896,7 +896,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TC= GLabelQemuLdst *l) tcg_out_ext8s(s, type, l->datalo_reg, TCG_REG_A0); break; case MO_SW: - tcg_out_ext16s(s, l->datalo_reg, TCG_REG_A0); + tcg_out_ext16s(s, type, l->datalo_reg, TCG_REG_A0); break; case MO_SL: tcg_out_ext32s(s, l->datalo_reg, TCG_REG_A0); @@ -1246,11 +1246,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); break; =20 - case INDEX_op_ext16s_i32: - case INDEX_op_ext16s_i64: - tcg_out_ext16s(s, a0, a1); - break; - case INDEX_op_ext16u_i32: case INDEX_op_ext16u_i64: tcg_out_ext16u(s, a0, a1); @@ -1351,7 +1346,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_bswap16_i64: tcg_out_opc_revb_2h(s, a0, a1); if (a2 & TCG_BSWAP_OS) { - tcg_out_ext16s(s, a0, a0); + tcg_out_ext16s(s, TCG_TYPE_REG, a0, a0); } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) =3D=3D TCG_BSWAP_O= Z) { tcg_out_ext16u(s, a0, a0); } @@ -1621,6 +1616,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: default: g_assert_not_reached(); } diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 5a712e3da5..9d305b9cf4 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -563,6 +563,12 @@ static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TC= GReg rs) tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); } =20 +static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg = rs) +{ + tcg_debug_assert(TCG_TARGET_HAS_ext16s_i32); + tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -2256,9 +2262,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_not_i64: i1 =3D OPC_NOR; goto do_unary; - case INDEX_op_ext16s_i32: - case INDEX_op_ext16s_i64: - i1 =3D OPC_SEH; do_unary: tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); break; @@ -2430,6 +2433,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: default: g_assert_not_reached(); } diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 61f489eae1..526397c789 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -784,7 +784,7 @@ static void tcg_out_ext8u(TCGContext *s, TCGReg dst, TC= GReg src) tcg_out32(s, ANDI | SAI(src, dst, 0xff)); } =20 -static inline void tcg_out_ext16s(TCGContext *s, TCGReg dst, TCGReg src) +static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dst, TCGReg= src) { tcg_out32(s, EXTSH | RA(dst) | RS(src)); } @@ -842,7 +842,7 @@ static void tcg_out_bswap16(TCGContext *s, TCGReg dst, = TCGReg src, int flags) if (have_isa_3_10) { tcg_out32(s, BRH | RA(dst) | RS(src)); if (flags & TCG_BSWAP_OS) { - tcg_out_ext16s(s, dst, dst); + tcg_out_ext16s(s, TCG_TYPE_REG, dst, dst); } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) =3D=3D TCG_BSWA= P_OZ) { tcg_out_ext16u(s, dst, dst); } @@ -861,7 +861,7 @@ static void tcg_out_bswap16(TCGContext *s, TCGReg dst, = TCGReg src, int flags) tcg_out_rlw(s, RLWIMI, tmp, src, 8, 16, 23); =20 if (flags & TCG_BSWAP_OS) { - tcg_out_ext16s(s, dst, tmp); + tcg_out_ext16s(s, TCG_TYPE_REG, dst, tmp); } else { tcg_out_mov(s, TCG_TYPE_REG, dst, tmp); } @@ -2978,10 +2978,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_st(s, args, true); break; =20 - case INDEX_op_ext16s_i32: - case INDEX_op_ext16s_i64: - tcg_out_ext16s(s, args[0], args[1]); - break; case INDEX_op_ext_i32_i64: case INDEX_op_ext32s_i64: tcg_out_ext32s(s, args[0], args[1]); @@ -3129,6 +3125,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: default: g_assert_not_reached(); } diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index d9b08014ce..12ee7b29af 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -591,7 +591,7 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type, = TCGReg ret, TCGReg arg) tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24); } =20 -static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) +static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg= arg) { tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16); @@ -1607,11 +1607,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_ext32u(s, a0, a1); break; =20 - case INDEX_op_ext16s_i32: - case INDEX_op_ext16s_i64: - tcg_out_ext16s(s, a0, a1); - break; - case INDEX_op_ext32s_i64: case INDEX_op_extrl_i64_i32: case INDEX_op_ext_i32_i64: @@ -1645,6 +1640,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: default: g_assert_not_reached(); } diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 338a91c591..024867336a 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1102,7 +1102,7 @@ static void tcg_out_ext8u(TCGContext *s, TCGReg dest,= TCGReg src) tcg_out_insn(s, RRE, LLGCR, dest, src); } =20 -static void tgen_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg s= rc) +static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGRe= g src) { tcg_out_insn(s, RRE, LGHR, dest, src); } @@ -1609,7 +1609,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, Mem= Op opc, TCGReg data, case MO_SW | MO_BSWAP: /* swapped sign-extended halfword load */ tcg_out_insn(s, RXY, LRVH, data, base, index, disp); - tgen_ext16s(s, TCG_TYPE_I64, data, data); + tcg_out_ext16s(s, TCG_TYPE_REG, data, data); break; case MO_SW: tcg_out_insn(s, RXY, LGH, data, base, index, disp); @@ -2233,9 +2233,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, } break; =20 - case INDEX_op_ext16s_i32: - tgen_ext16s(s, TCG_TYPE_I32, args[0], args[1]); - break; case INDEX_op_ext16u_i32: tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]); break; @@ -2531,9 +2528,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, } break; =20 - case INDEX_op_ext16s_i64: - tgen_ext16s(s, TCG_TYPE_I64, args[0], args[1]); - break; case INDEX_op_ext_i32_i64: case INDEX_op_ext32s_i64: tgen_ext32s(s, args[0], args[1]); @@ -2636,6 +2630,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: default: g_assert_not_reached(); } diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 4792b04b54..e4a8bd6e27 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -501,6 +501,11 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type,= TCGReg rd, TCGReg rs) g_assert_not_reached(); } =20 +static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg = rs) +{ + g_assert_not_reached(); +} + static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) { tcg_out_arithi(s, rd, rs, 0xff, ARITH_AND); @@ -1714,6 +1719,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: default: g_assert_not_reached(); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index e946d9165e..167f8123b1 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -586,6 +586,24 @@ static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TC= GReg rs) } } =20 +static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg = rs) +{ + switch (type) { + case TCG_TYPE_I32: + tcg_debug_assert(TCG_TARGET_HAS_ext16s_i32); + tcg_out_op_rr(s, INDEX_op_ext16s_i32, rd, rs); + break; +#if TCG_TARGET_REG_BITS =3D=3D 64 + case TCG_TYPE_I64: + tcg_debug_assert(TCG_TARGET_HAS_ext16s_i64); + tcg_out_op_rr(s, INDEX_op_ext16s_i64, rd, rs); + break; +#endif + default: + g_assert_not_reached(); + } +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -744,7 +762,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */ - CASE_32_64(ext16s) /* Optional (TCG_TARGET_HAS_ext16s_*). */ CASE_32_64(ext16u) /* Optional (TCG_TARGET_HAS_ext16u_*). */ CASE_64(ext32s) /* Optional (TCG_TARGET_HAS_ext32s_i64). */ CASE_64(ext32u) /* Optional (TCG_TARGET_HAS_ext32u_i64). */ @@ -826,6 +843,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: default: g_assert_not_reached(); } --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921802; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VLoGO+fofhKFzHTKhPmy3saPTeLEd9sLATIHQOs8puY=; b=tWCVfZ3ibkv1FtkspQw0rhLfk50SA0LDWzGuYLqHUtQEkHl3dqvYFPi2k4wTD7hJfX mVbUNx8F2ujffKfNkO+eMrjUUenC4Rw6iJ94AGEqwYnZOKGsD9ZMf6RCH20J4cX2WwxQ GnBy9CEoDt8L5L5tG4e7eJLelVepg3WYXwG26UInBqI3uSEs0gsYDxNpWEM1V2Kjy0E/ bLX6/RwiZ7vOi6F3nPRbZXUMYOCZCVqPvvENPbTHVlIUU9v2KbJ1uKjEAZxPWeTchjtN qN6eHemXn5N31rHR/FcBlK2YFlMNPe00yW90I072MbHS25syLN2o1Ji61UmF4+tf6WI1 Za0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921802; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VLoGO+fofhKFzHTKhPmy3saPTeLEd9sLATIHQOs8puY=; b=wKICPvlwLhgezWwqB2+K2AKGUclxF0UAamF4YI6iNJUxaENhn4+8PNAQHIKDeKxSqx hEJ7iFekvTr4mKK874/juvTkBhkn/oZitAJHeWK4iOgnIK2Xg2gIm5fX9kZR9ScKy4XB 97WMIyBNkU7ZZmqQ8v9qrwbPclR0ac58tqZ6ptXenBE9BxVnxbuIOwyJFJV3OhtGZML7 jNlvTIrwRSKkleX4R0a9hm2dj1Awjwe4eK3B6w/NmgBcZ57gFwvhjJnUPxCAug1WzqmQ 8mKHLRKh4E7gjjT18q2sgk1NowN/D9oNKT4z2Z+2mkSMBrly2TbDb2eF1RaPmtGb7uQX xImA== X-Gm-Message-State: AAQBX9fkhDjANr8rQ+2h6DBC8Cvs5bcW5nvr3h9OIHJDBnsw5froymKr 9objyHbrubo03HscK6M+55rc2c09D0r+jHJGBnE= X-Google-Smtp-Source: AKy350YcTdWwqM57rU+ENpTuS5YF2imiZ9kl7z7cyAPTC8TSuxIzMmrmkYa1jyFc5giROE8Ysisu0A== X-Received: by 2002:a17:903:646:b0:1a5:27d5:179b with SMTP id kh6-20020a170903064600b001a527d5179bmr394811plb.17.1680921802458; Fri, 07 Apr 2023 19:43:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 06/42] tcg: Split out tcg_out_ext16u Date: Fri, 7 Apr 2023 19:42:38 -0700 Message-Id: <20230408024314.3357414-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922059823100001 Content-Type: text/plain; charset="utf-8" We will need a backend interface for performing 16-bit zero-extend. Use it in tcg_reg_alloc_op in the meantime. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg.c | 5 +++++ tcg/aarch64/tcg-target.c.inc | 13 ++++++++----- tcg/arm/tcg-target.c.inc | 17 ++++++++++------- tcg/i386/tcg-target.c.inc | 8 +++----- tcg/loongarch64/tcg-target.c.inc | 7 ++----- tcg/mips/tcg-target.c.inc | 5 +++++ tcg/ppc/tcg-target.c.inc | 4 +++- tcg/riscv/tcg-target.c.inc | 7 ++----- tcg/s390x/tcg-target.c.inc | 17 ++++++----------- tcg/sparc64/tcg-target.c.inc | 11 +++++++++-- tcg/tci/tcg-target.c.inc | 14 +++++++++++++- 11 files changed, 66 insertions(+), 42 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 739f92c2ee..5b0db747e8 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -108,6 +108,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg = arg); static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg= arg); static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg); +static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g); static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); static void tcg_out_goto_tb(TCGContext *s, int which); @@ -4516,6 +4517,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TC= GOp *op) case INDEX_op_ext16s_i64: tcg_out_ext16s(s, TCG_TYPE_I64, new_args[0], new_args[1]); break; + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: + tcg_out_ext16u(s, new_args[0], new_args[1]); + break; default: if (def->flags & TCG_OPF_VECTOR) { tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op), diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 3527c14d04..f55829e9ce 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1442,6 +1442,11 @@ static void tcg_out_ext8u(TCGContext *s, TCGReg rd, = TCGReg rn) tcg_out_uxt(s, MO_8, rd, rn); } =20 +static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) +{ + tcg_out_uxt(s, MO_16, rd, rn); +} + static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd, TCGReg rn, int64_t aimm) { @@ -2241,7 +2246,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_ext16s(s, ext, a0, a0); } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) =3D=3D TCG_BSWAP_O= Z) { /* Output must be zero-extended, but input isn't. */ - tcg_out_uxt(s, MO_16, a0, a0); + tcg_out_ext16u(s, a0, a0); } break; =20 @@ -2249,10 +2254,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext32s_i64: tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a1); break; - case INDEX_op_ext16u_i64: - case INDEX_op_ext16u_i32: - tcg_out_uxt(s, MO_16, a0, a1); - break; case INDEX_op_extu_i32_i64: case INDEX_op_ext32u_i64: tcg_out_movr(s, TCG_TYPE_I32, a0, a1); @@ -2319,6 +2320,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext8u_i64: case INDEX_op_ext16s_i64: case INDEX_op_ext16s_i32: + case INDEX_op_ext16u_i64: + case INDEX_op_ext16u_i32: default: g_assert_not_reached(); } diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index cddf977a58..8fa0c6cbc0 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -981,12 +981,18 @@ static void tcg_out_ext16s(TCGContext *s, TCGType t, = TCGReg rd, TCGReg rn) tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn); } =20 -static void tcg_out_ext16u(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg = rn) +static void tcg_out_ext16u_cond(TCGContext *s, ARMCond cond, + TCGReg rd, TCGReg rn) { /* uxth */ tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn); } =20 +static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) +{ + tcg_out_ext16u_cond(s, COND_AL, rd, rn); +} + static void tcg_out_bswap16(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn, int flags) { @@ -1372,8 +1378,8 @@ DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32, uint32_t, tcg_o= ut_movi32, (tcg_out_movi32(s, COND_AL, TCG_REG_TMP, arg), arg =3D TCG_REG_TMP)) DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8, TCGReg, tcg_out_ext8u_cond, (tcg_out_ext8u_cond(s, COND_AL, TCG_REG_TMP, arg), arg =3D TCG_REG_TMP= )) -DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16, TCGReg, tcg_out_ext16u, - (tcg_out_ext16u(s, COND_AL, TCG_REG_TMP, arg), arg =3D TCG_REG_TMP)) +DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16, TCGReg, tcg_out_ext16u_cond, + (tcg_out_ext16u_cond(s, COND_AL, TCG_REG_TMP, arg), arg =3D TCG_REG_TM= P)) DEFINE_TCG_OUT_ARG(tcg_out_arg_reg32, TCGReg, tcg_out_mov_reg, ) =20 static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg, @@ -2249,10 +2255,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_bswap32(s, COND_AL, args[0], args[1]); break; =20 - case INDEX_op_ext16u_i32: - tcg_out_ext16u(s, COND_AL, args[0], args[1]); - break; - case INDEX_op_deposit_i32: tcg_out_deposit(s, COND_AL, args[0], args[2], args[3], args[4], const_args[2]); @@ -2303,6 +2305,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_ext8u_i32: case INDEX_op_ext16s_i32: + case INDEX_op_ext16u_i32: default: g_assert_not_reached(); } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 9cbf8a90f4..920524589d 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1274,7 +1274,7 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type= , TCGReg dest, TCGReg src) tcg_out_modrm(s, OPC_MOVSBL + P_REXB_RM + rexw, dest, src); } =20 -static inline void tcg_out_ext16u(TCGContext *s, int dest, int src) +static void tcg_out_ext16u(TCGContext *s, TCGReg dest, TCGReg src) { /* movzwl */ tcg_out_modrm(s, OPC_MOVZWL, dest, src); @@ -2671,10 +2671,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, a0); break; =20 - OP_32_64(ext16u): - tcg_out_ext16u(s, a0, a1); - break; - case INDEX_op_qemu_ld_i32: tcg_out_qemu_ld(s, args, 0); break; @@ -2839,6 +2835,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_ext8u_i64: case INDEX_op_ext16s_i32: case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: default: g_assert_not_reached(); } diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index a365fbcf8f..08c2b65b19 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1246,11 +1246,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); break; =20 - case INDEX_op_ext16u_i32: - case INDEX_op_ext16u_i64: - tcg_out_ext16u(s, a0, a1); - break; - case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: tcg_out_ext32u(s, a0, a1); @@ -1618,6 +1613,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext8u_i64: case INDEX_op_ext16s_i32: case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: default: g_assert_not_reached(); } diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 9d305b9cf4..220060c821 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -569,6 +569,11 @@ static void tcg_out_ext16s(TCGContext *s, TCGType type= , TCGReg rd, TCGReg rs) tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs); } =20 +static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 526397c789..e203a01bac 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -789,7 +789,7 @@ static void tcg_out_ext16s(TCGContext *s, TCGType type,= TCGReg dst, TCGReg src) tcg_out32(s, EXTSH | RA(dst) | RS(src)); } =20 -static inline void tcg_out_ext16u(TCGContext *s, TCGReg dst, TCGReg src) +static void tcg_out_ext16u(TCGContext *s, TCGReg dst, TCGReg src) { tcg_out32(s, ANDI | SAI(src, dst, 0xffff)); } @@ -3127,6 +3127,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext8u_i64: case INDEX_op_ext16s_i32: case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: default: g_assert_not_reached(); } diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 12ee7b29af..c49decaae9 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1597,11 +1597,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_st(s, args, true); break; =20 - case INDEX_op_ext16u_i32: - case INDEX_op_ext16u_i64: - tcg_out_ext16u(s, a0, a1); - break; - case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: tcg_out_ext32u(s, a0, a1); @@ -1642,6 +1637,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext8u_i64: case INDEX_op_ext16s_i32: case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: default: g_assert_not_reached(); } diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 024867336a..0c489c2341 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1107,7 +1107,7 @@ static void tcg_out_ext16s(TCGContext *s, TCGType typ= e, TCGReg dest, TCGReg src) tcg_out_insn(s, RRE, LGHR, dest, src); } =20 -static void tgen_ext16u(TCGContext *s, TCGType type, TCGReg dest, TCGReg s= rc) +static void tcg_out_ext16u(TCGContext *s, TCGReg dest, TCGReg src) { tcg_out_insn(s, RRE, LLGHR, dest, src); } @@ -1157,7 +1157,7 @@ static void tgen_andi(TCGContext *s, TCGType type, TC= GReg dest, uint64_t val) return; } if ((val & valid) =3D=3D 0xffff) { - tgen_ext16u(s, TCG_TYPE_I64, dest, dest); + tcg_out_ext16u(s, dest, dest); return; } =20 @@ -1600,7 +1600,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, Mem= Op opc, TCGReg data, case MO_UW | MO_BSWAP: /* swapped unsigned halfword load with upper bits zeroed */ tcg_out_insn(s, RXY, LRVH, data, base, index, disp); - tgen_ext16u(s, TCG_TYPE_I64, data, data); + tcg_out_ext16u(s, data, data); break; case MO_UW: tcg_out_insn(s, RXY, LLGH, data, base, index, disp); @@ -1809,7 +1809,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) tcg_out_ext8u(s, TCG_REG_R4, data_reg); break; case MO_UW: - tgen_ext16u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg); + tcg_out_ext16u(s, TCG_REG_R4, data_reg); break; case MO_UL: tgen_ext32u(s, TCG_REG_R4, data_reg); @@ -2233,10 +2233,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, } break; =20 - case INDEX_op_ext16u_i32: - tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]); - break; - case INDEX_op_bswap16_i32: a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; tcg_out_insn(s, RRE, LRVR, a0, a1); @@ -2532,9 +2528,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_ext32s_i64: tgen_ext32s(s, args[0], args[1]); break; - case INDEX_op_ext16u_i64: - tgen_ext16u(s, TCG_TYPE_I64, args[0], args[1]); - break; case INDEX_op_extu_i32_i64: case INDEX_op_ext32u_i64: tgen_ext32u(s, args[0], args[1]); @@ -2632,6 +2625,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_ext8u_i64: case INDEX_op_ext16s_i32: case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: default: g_assert_not_reached(); } diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index e4a8bd6e27..98784f6545 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -511,6 +511,12 @@ static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TC= GReg rs) tcg_out_arithi(s, rd, rs, 0xff, ARITH_AND); } =20 +static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_arithi(s, rd, rs, 16, SHIFT_SLL); + tcg_out_arithi(s, rd, rd, 16, SHIFT_SRL); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -896,8 +902,7 @@ static void emit_extend(TCGContext *s, TCGReg r, int op) tcg_out_ext8u(s, r, r); break; case MO_16: - tcg_out_arithi(s, r, r, 16, SHIFT_SLL); - tcg_out_arithi(s, r, r, 16, SHIFT_SRL); + tcg_out_ext16u(s, r, r); break; case MO_32: tcg_out_arith(s, r, r, 0, SHIFT_SRL); @@ -1721,6 +1726,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext8u_i64: case INDEX_op_ext16s_i32: case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: default: g_assert_not_reached(); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 167f8123b1..49a83942fa 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -604,6 +604,17 @@ static void tcg_out_ext16s(TCGContext *s, TCGType type= , TCGReg rd, TCGReg rs) } } =20 +static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) +{ + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_debug_assert(TCG_TARGET_HAS_ext16u_i64); + tcg_out_op_rr(s, INDEX_op_ext16u_i64, rd, rs); + } else { + tcg_debug_assert(TCG_TARGET_HAS_ext16u_i32); + tcg_out_op_rr(s, INDEX_op_ext16u_i32, rd, rs); + } +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -762,7 +773,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */ - CASE_32_64(ext16u) /* Optional (TCG_TARGET_HAS_ext16u_*). */ CASE_64(ext32s) /* Optional (TCG_TARGET_HAS_ext32s_i64). */ CASE_64(ext32u) /* Optional (TCG_TARGET_HAS_ext32u_i64). */ CASE_64(ext_i32) @@ -845,6 +855,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext8u_i64: case INDEX_op_ext16s_i32: case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: default: g_assert_not_reached(); } --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921803; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cblZDmOFjna0XCaVbm/PEPY78XZH4SZ91Jo5RdjUH08=; b=dVJx/WUiwslD8RtiCSl7KXcZMbAgN3awP8XR6WLoWXsoNtTcUNdDdzzTBMAl6Nzd9t MDe9WsyJIRBFPK6rL6zmHEypNliXKeS3r4hGNjZHq7ISl6kgmKdmj1geaVMvoWi19eFX GuGydvbdN0PlfzeatnsFvrwU3etb22OX4P3KdTJUptBhyXsoXgoU9KQU1/HMX1H4vzVV MOZh61EZvP8hXkgn3EHoflrfaZ9IFKNvfHSNu0LNDL5VvO5APaDpq4s7FIrMu1eBbZoK cEwXKtBvIWgjmeoTVOfFBuA0AOsI5dtB+7r5XHr34hh3Si42699N4TonLELqh6uxS31x FAhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921803; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cblZDmOFjna0XCaVbm/PEPY78XZH4SZ91Jo5RdjUH08=; b=ZCDd1BCtjFoo4rzF3cTAnCzj8AzN59yHb32gcJralFjQQYzgp7d5hmaXYK9Psi1D5v Sk0mSursKlZVHAH376UL5yL4e6Ng3UoCW+KpW8DDPm33Sv2ZmVR1xl+uehUGdfJRjSWY 3JCkOazqwsCPBcGW5IKcLt9upm0WHSTwjmE/75ADJenXR3SAPRHYbrXNKJq6JX9eSQhC CWbTsN40ltiLaZewZeXIVGkCTsOmdojxLZ+FWny96jigovSTigrmidJ8ZaoFPxdpICOy wn9AvR1Jl3NIGi5pCLORTeuqQuSdXKcfGAY0VMvJyoxEVXTnfkCoLBmmOEpPHLlUjPXe g86w== X-Gm-Message-State: AAQBX9cBAWVFIT10b3ukW8IfEe84QJOlMDLBebEw/HC2bQWmOLkRN+J7 jlK7QqcJfcEGNqOTIuC29Eriw/5ucK8oi2HESU8= X-Google-Smtp-Source: AKy350Yie1Oi5Im0yfmJBPThUlmQM/Gfd1jXOw5Z5gKmP860iVNfW+VwU9Ol6iQMA1nKdQUdPKyqOw== X-Received: by 2002:a17:903:244d:b0:1a1:aa68:7e61 with SMTP id l13-20020a170903244d00b001a1aa687e61mr5749611pls.33.1680921803504; Fri, 07 Apr 2023 19:43:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 07/42] tcg: Split out tcg_out_ext32s Date: Fri, 7 Apr 2023 19:42:39 -0700 Message-Id: <20230408024314.3357414-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680921975487100001 Content-Type: text/plain; charset="utf-8" We will need a backend interface for performing 32-bit sign-extend. Use it in tcg_reg_alloc_op in the meantime. Signed-off-by: Richard Henderson --- tcg/tcg.c | 4 ++++ tcg/aarch64/tcg-target.c.inc | 9 +++++++-- tcg/arm/tcg-target.c.inc | 5 +++++ tcg/i386/tcg-target.c.inc | 5 +++-- tcg/loongarch64/tcg-target.c.inc | 2 +- tcg/mips/tcg-target.c.inc | 12 +++++++++--- tcg/ppc/tcg-target.c.inc | 5 +++-- tcg/riscv/tcg-target.c.inc | 2 +- tcg/s390x/tcg-target.c.inc | 10 +++++----- tcg/sparc64/tcg-target.c.inc | 11 ++++++++--- tcg/tci/tcg-target.c.inc | 9 ++++++++- 11 files changed, 54 insertions(+), 20 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 5b0db747e8..84aa8d639e 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -109,6 +109,7 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type, = TCGReg ret, TCGReg arg); static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg= arg); static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg); +static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g); static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); static void tcg_out_goto_tb(TCGContext *s, int which); @@ -4521,6 +4522,9 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) case INDEX_op_ext16u_i64: tcg_out_ext16u(s, new_args[0], new_args[1]); break; + case INDEX_op_ext32s_i64: + tcg_out_ext32s(s, new_args[0], new_args[1]); + break; default: if (def->flags & TCG_OPF_VECTOR) { tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op), diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index f55829e9ce..d7964734c3 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1429,6 +1429,11 @@ static void tcg_out_ext16s(TCGContext *s, TCGType ty= pe, TCGReg rd, TCGReg rn) tcg_out_sxt(s, type, MO_16, rd, rn); } =20 +static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) +{ + tcg_out_sxt(s, TCG_TYPE_I64, MO_32, rd, rn); +} + static inline void tcg_out_uxt(TCGContext *s, MemOp s_bits, TCGReg rd, TCGReg rn) { @@ -2232,7 +2237,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_bswap32_i64: tcg_out_rev(s, TCG_TYPE_I32, MO_32, a0, a1); if (a2 & TCG_BSWAP_OS) { - tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a0); + tcg_out_ext32s(s, a0, a0); } break; case INDEX_op_bswap32_i32: @@ -2251,7 +2256,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_ext_i32_i64: - case INDEX_op_ext32s_i64: tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a1); break; case INDEX_op_extu_i32_i64: @@ -2322,6 +2326,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16s_i32: case INDEX_op_ext16u_i64: case INDEX_op_ext16u_i32: + case INDEX_op_ext32s_i64: default: g_assert_not_reached(); } diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 8fa0c6cbc0..401769bdd6 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -993,6 +993,11 @@ static void tcg_out_ext16u(TCGContext *s, TCGReg rd, T= CGReg rn) tcg_out_ext16u_cond(s, COND_AL, rd, rn); } =20 +static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) +{ + g_assert_not_reached(); +} + static void tcg_out_bswap16(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn, int flags) { diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 920524589d..8bb747b81d 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1293,8 +1293,9 @@ static inline void tcg_out_ext32u(TCGContext *s, int = dest, int src) tcg_out_modrm(s, OPC_MOVL_GvEv, dest, src); } =20 -static inline void tcg_out_ext32s(TCGContext *s, int dest, int src) +static void tcg_out_ext32s(TCGContext *s, TCGReg dest, TCGReg src) { + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out_modrm(s, OPC_MOVSLQ, dest, src); } =20 @@ -2758,7 +2759,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, tcg_out_ext32u(s, a0, a1); break; case INDEX_op_ext_i32_i64: - case INDEX_op_ext32s_i64: tcg_out_ext32s(s, a0, a1); break; case INDEX_op_extrh_i64_i32: @@ -2837,6 +2837,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_ext16s_i64: case INDEX_op_ext16u_i32: case INDEX_op_ext16u_i64: + case INDEX_op_ext32s_i64: default: g_assert_not_reached(); } diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 08c2b65b19..037474510c 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1251,7 +1251,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_ext32u(s, a0, a1); break; =20 - case INDEX_op_ext32s_i64: case INDEX_op_extrl_i64_i32: case INDEX_op_ext_i32_i64: tcg_out_ext32s(s, a0, a1); @@ -1615,6 +1614,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16s_i64: case INDEX_op_ext16u_i32: case INDEX_op_ext16u_i64: + case INDEX_op_ext32s_i64: default: g_assert_not_reached(); } diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 220060c821..c57ccb6b3d 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -574,6 +574,12 @@ static void tcg_out_ext16u(TCGContext *s, TCGReg rd, T= CGReg rs) tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff); } =20 +static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); + tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -1313,7 +1319,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) /* delay slot */ if (TCG_TARGET_REG_BITS =3D=3D 64 && l->type =3D=3D TCG_TYPE_I32) { /* we always sign-extend 32-bit loads */ - tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0); + tcg_out_ext32s(s, v0, TCG_REG_V0); } else { tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO); } @@ -2287,10 +2293,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_extrh_i64_i32: tcg_out_dsra(s, a0, a1, 32); break; - case INDEX_op_ext32s_i64: case INDEX_op_ext_i32_i64: case INDEX_op_extrl_i64_i32: - tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0); + tcg_out_ext32s(s, a0, a1); break; case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: @@ -2440,6 +2445,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext8u_i64: case INDEX_op_ext16s_i32: case INDEX_op_ext16s_i64: + case INDEX_op_ext32s_i64: default: g_assert_not_reached(); } diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index e203a01bac..3084a711eb 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -794,8 +794,9 @@ static void tcg_out_ext16u(TCGContext *s, TCGReg dst, T= CGReg src) tcg_out32(s, ANDI | SAI(src, dst, 0xffff)); } =20 -static inline void tcg_out_ext32s(TCGContext *s, TCGReg dst, TCGReg src) +static void tcg_out_ext32s(TCGContext *s, TCGReg dst, TCGReg src) { + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out32(s, EXTSW | RA(dst) | RS(src)); } =20 @@ -2979,7 +2980,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_ext_i32_i64: - case INDEX_op_ext32s_i64: tcg_out_ext32s(s, args[0], args[1]); break; case INDEX_op_extu_i32_i64: @@ -3129,6 +3129,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16s_i64: case INDEX_op_ext16u_i32: case INDEX_op_ext16u_i64: + case INDEX_op_ext32s_i64: default: g_assert_not_reached(); } diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index c49decaae9..9381e113aa 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1602,7 +1602,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_ext32u(s, a0, a1); break; =20 - case INDEX_op_ext32s_i64: case INDEX_op_extrl_i64_i32: case INDEX_op_ext_i32_i64: tcg_out_ext32s(s, a0, a1); @@ -1639,6 +1638,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16s_i64: case INDEX_op_ext16u_i32: case INDEX_op_ext16u_i64: + case INDEX_op_ext32s_i64: default: g_assert_not_reached(); } diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 0c489c2341..9aff45cbfd 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1112,7 +1112,7 @@ static void tcg_out_ext16u(TCGContext *s, TCGReg dest= , TCGReg src) tcg_out_insn(s, RRE, LLGHR, dest, src); } =20 -static inline void tgen_ext32s(TCGContext *s, TCGReg dest, TCGReg src) +static void tcg_out_ext32s(TCGContext *s, TCGReg dest, TCGReg src) { tcg_out_insn(s, RRE, LGFR, dest, src); } @@ -1627,7 +1627,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, Mem= Op opc, TCGReg data, case MO_SL | MO_BSWAP: /* swapped sign-extended int load */ tcg_out_insn(s, RXY, LRV, data, base, index, disp); - tgen_ext32s(s, data, data); + tcg_out_ext32s(s, data, data); break; case MO_SL: tcg_out_insn(s, RXY, LGF, data, base, index, disp); @@ -2259,7 +2259,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, a0 =3D args[0], a1 =3D args[1], a2 =3D args[2]; tcg_out_insn(s, RRE, LRVR, a0, a1); if (a2 & TCG_BSWAP_OS) { - tgen_ext32s(s, a0, a0); + tcg_out_ext32s(s, a0, a0); } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) =3D=3D TCG_BSWAP_O= Z) { tgen_ext32u(s, a0, a0); } @@ -2525,8 +2525,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, break; =20 case INDEX_op_ext_i32_i64: - case INDEX_op_ext32s_i64: - tgen_ext32s(s, args[0], args[1]); + tcg_out_ext32s(s, args[0], args[1]); break; case INDEX_op_extu_i32_i64: case INDEX_op_ext32u_i64: @@ -2627,6 +2626,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_ext16s_i64: case INDEX_op_ext16u_i32: case INDEX_op_ext16u_i64: + case INDEX_op_ext32s_i64: default: g_assert_not_reached(); } diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 98784f6545..fef19493d0 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -517,6 +517,11 @@ static void tcg_out_ext16u(TCGContext *s, TCGReg rd, T= CGReg rs) tcg_out_arithi(s, rd, rd, 16, SHIFT_SRL); } =20 +static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_arithi(s, rd, rs, 0, SHIFT_SRA); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -1213,7 +1218,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a, TCGReg addr, =20 /* We let the helper sign-extend SB and SW, but leave SL for here. */ if (is_64 && (memop & MO_SSIZE) =3D=3D MO_SL) { - tcg_out_arithi(s, data, TCG_REG_O0, 0, SHIFT_SRA); + tcg_out_ext32s(s, data, TCG_REG_O0); } else { tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0); } @@ -1668,8 +1673,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, c =3D ARITH_UDIVX; goto gen_arith; case INDEX_op_ext_i32_i64: - case INDEX_op_ext32s_i64: - tcg_out_arithi(s, a0, a1, 0, SHIFT_SRA); + tcg_out_ext32s(s, a0, a1); break; case INDEX_op_extu_i32_i64: case INDEX_op_ext32u_i64: @@ -1728,6 +1732,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16s_i64: case INDEX_op_ext16u_i32: case INDEX_op_ext16u_i64: + case INDEX_op_ext32s_i64: default: g_assert_not_reached(); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 49a83942fa..04e162a623 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -615,6 +615,13 @@ static void tcg_out_ext16u(TCGContext *s, TCGReg rd, T= CGReg rs) } } =20 +static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); + tcg_debug_assert(TCG_TARGET_HAS_ext32s_i64); + tcg_out_op_rr(s, INDEX_op_ext32s_i64, rd, rs); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -773,7 +780,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */ - CASE_64(ext32s) /* Optional (TCG_TARGET_HAS_ext32s_i64). */ CASE_64(ext32u) /* Optional (TCG_TARGET_HAS_ext32u_i64). */ CASE_64(ext_i32) CASE_64(extu_i32) @@ -857,6 +863,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16s_i64: case INDEX_op_ext16u_i32: case INDEX_op_ext16u_i64: + case INDEX_op_ext32s_i64: default: g_assert_not_reached(); } --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921804; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VdpQxEtfVL1X7UTRNCnlp2ECby0soTQGr8Da19bvaPM=; b=XKZUyc/oUM8ciX2OKi++pq/8ONrEOzcSpCDxat/1grBKLwC3jfdOP1O79iNg7UA36Y pn6kuL7I/7j6WkfIdLNeIDh6ZS9U5H772VdyhfSlqL2fBfeGIsg37M89d61DiAreAekx 8ZRD5JG6sHrf81PXjTAgkvL+D931OTuCN4sBJzdJ11wwZSfPMWeszs0XlcU/OwkLCmlA iK0kuOjXAkbfS9m2xDCXXzt4I3MLTSI28KSfDE37iQyckxstxumowfztQCHjJoONcU+U oNIAqQk3ncB8PsQssJCIXO3D1pnj3avfS92qQ+YqjoT/vs4pQUSZ6pAC4B/Ji6bF+kGv +m0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921804; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VdpQxEtfVL1X7UTRNCnlp2ECby0soTQGr8Da19bvaPM=; b=aiCujal0krk3gt57PcNl/hdqnsMPA6wfNsTTtumXS2uJXC11e1CzTYOcMw0NYAXxJA amFJdp+2P9O8W3OX6GlOrm+yJhXWPlPScIfMVlDMSfryd9FKnos5M2zzyT9sIIfhAm0a ZvPjqJOGFRT1SC243vBy5tppM4XsmwKZw8Gklvu6VmwukkTOBy/NH7Q2a6ejmgKNCBus 4OoRmCy9SOkIOyf+YBvIN5zkKgeIjekN7tE7bpyqE/HOdFoStL9LJaR6IQt2gNz4Ly4j pdgU8FTdUpymRxeCu9JmTPRCihXbXOZGDESz59McRNzYNQJwOhXFl2Au1B4sldjEhEEY OcJg== X-Gm-Message-State: AAQBX9evsMv9adwM6umQyxBljdyUfrzQqPGhA/+a7oA9xiWXJB6zu78W FUz/O3I9BwrNUzmSqb+chpWF4q9FeItmezaoXK4= X-Google-Smtp-Source: AKy350YhKGj4p8+11lCgpBS8Cv0MbNvVe+bFGDEn/BB5oltWg7rv5N/jRn7v72vrHnoS8GW8QIg2tQ== X-Received: by 2002:a17:902:e802:b0:19c:be03:d0ba with SMTP id u2-20020a170902e80200b0019cbe03d0bamr5227595plg.18.1680921804394; Fri, 07 Apr 2023 19:43:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 08/42] tcg: Split out tcg_out_ext32u Date: Fri, 7 Apr 2023 19:42:40 -0700 Message-Id: <20230408024314.3357414-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922248751100002 Content-Type: text/plain; charset="utf-8" We will need a backend interface for performing 32-bit zero-extend. Use it in tcg_reg_alloc_op in the meantime. Signed-off-by: Richard Henderson --- tcg/tcg.c | 4 ++++ tcg/aarch64/tcg-target.c.inc | 9 +++++++-- tcg/arm/tcg-target.c.inc | 5 +++++ tcg/i386/tcg-target.c.inc | 4 ++-- tcg/loongarch64/tcg-target.c.inc | 2 +- tcg/mips/tcg-target.c.inc | 3 ++- tcg/ppc/tcg-target.c.inc | 4 +++- tcg/riscv/tcg-target.c.inc | 2 +- tcg/s390x/tcg-target.c.inc | 20 ++++++++++---------- tcg/sparc64/tcg-target.c.inc | 17 +++++++++++------ tcg/tci/tcg-target.c.inc | 9 ++++++++- 11 files changed, 54 insertions(+), 25 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 84aa8d639e..a182771c01 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -110,6 +110,7 @@ static void tcg_out_ext16s(TCGContext *s, TCGType type,= TCGReg ret, TCGReg arg); static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg); +static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g); static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); static void tcg_out_goto_tb(TCGContext *s, int which); @@ -4525,6 +4526,9 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) case INDEX_op_ext32s_i64: tcg_out_ext32s(s, new_args[0], new_args[1]); break; + case INDEX_op_ext32u_i64: + tcg_out_ext32u(s, new_args[0], new_args[1]); + break; default: if (def->flags & TCG_OPF_VECTOR) { tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op), diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index d7964734c3..bca5f03dfb 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1452,6 +1452,11 @@ static void tcg_out_ext16u(TCGContext *s, TCGReg rd,= TCGReg rn) tcg_out_uxt(s, MO_16, rd, rn); } =20 +static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rn) +{ + tcg_out_movr(s, TCG_TYPE_I32, rd, rn); +} + static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd, TCGReg rn, int64_t aimm) { @@ -2259,8 +2264,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a1); break; case INDEX_op_extu_i32_i64: - case INDEX_op_ext32u_i64: - tcg_out_movr(s, TCG_TYPE_I32, a0, a1); + tcg_out_ext32u(s, a0, a1); break; =20 case INDEX_op_deposit_i64: @@ -2327,6 +2331,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16u_i64: case INDEX_op_ext16u_i32: case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: default: g_assert_not_reached(); } diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 401769bdd6..5c48b92f83 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -998,6 +998,11 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg rd, T= CGReg rn) g_assert_not_reached(); } =20 +static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rn) +{ + g_assert_not_reached(); +} + static void tcg_out_bswap16(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn, int flags) { diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 8bb747b81d..1e9f61dbf3 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1287,7 +1287,7 @@ static void tcg_out_ext16s(TCGContext *s, TCGType typ= e, TCGReg dest, TCGReg src) tcg_out_modrm(s, OPC_MOVSWL + rexw, dest, src); } =20 -static inline void tcg_out_ext32u(TCGContext *s, int dest, int src) +static void tcg_out_ext32u(TCGContext *s, TCGReg dest, TCGReg src) { /* 32-bit mov zero extends. */ tcg_out_modrm(s, OPC_MOVL_GvEv, dest, src); @@ -2754,7 +2754,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, tcg_out_bswap64(s, a0); break; case INDEX_op_extu_i32_i64: - case INDEX_op_ext32u_i64: case INDEX_op_extrl_i64_i32: tcg_out_ext32u(s, a0, a1); break; @@ -2838,6 +2837,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_ext16u_i32: case INDEX_op_ext16u_i64: case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: default: g_assert_not_reached(); } diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 037474510c..d2511eda7a 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1246,7 +1246,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); break; =20 - case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: tcg_out_ext32u(s, a0, a1); break; @@ -1615,6 +1614,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16u_i32: case INDEX_op_ext16u_i64: case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: default: g_assert_not_reached(); } diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index c57ccb6b3d..fe90547c43 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -663,6 +663,7 @@ static void tcg_out_bswap64(TCGContext *s, TCGReg ret, = TCGReg arg) =20 static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) { + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); if (use_mips32r2_instructions) { tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); } else { @@ -2297,7 +2298,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_extrl_i64_i32: tcg_out_ext32s(s, a0, a1); break; - case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: tcg_out_ext32u(s, a0, a1); break; @@ -2446,6 +2446,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16s_i32: case INDEX_op_ext16s_i64: case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: default: g_assert_not_reached(); } diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 3084a711eb..5d25e30851 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -800,8 +800,9 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg dst, T= CGReg src) tcg_out32(s, EXTSW | RA(dst) | RS(src)); } =20 -static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src) +static void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src) { + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); tcg_out_rld(s, RLDICL, dst, src, 0, 32); } =20 @@ -3130,6 +3131,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16u_i32: case INDEX_op_ext16u_i64: case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: default: g_assert_not_reached(); } diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 9381e113aa..1d91fd19c6 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1597,7 +1597,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_st(s, args, true); break; =20 - case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: tcg_out_ext32u(s, a0, a1); break; @@ -1639,6 +1638,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16u_i32: case INDEX_op_ext16u_i64: case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: default: g_assert_not_reached(); } diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 9aff45cbfd..825dbfc523 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1117,7 +1117,7 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg dest= , TCGReg src) tcg_out_insn(s, RRE, LGFR, dest, src); } =20 -static inline void tgen_ext32u(TCGContext *s, TCGReg dest, TCGReg src) +static void tcg_out_ext32u(TCGContext *s, TCGReg dest, TCGReg src) { tcg_out_insn(s, RRE, LLGFR, dest, src); } @@ -1149,7 +1149,7 @@ static void tgen_andi(TCGContext *s, TCGType type, TC= GReg dest, uint64_t val) =20 /* Look for the zero-extensions. */ if ((val & valid) =3D=3D 0xffffffff) { - tgen_ext32u(s, dest, dest); + tcg_out_ext32u(s, dest, dest); return; } if ((val & valid) =3D=3D 0xff) { @@ -1440,7 +1440,7 @@ static void tgen_ctpop(TCGContext *s, TCGType type, T= CGReg dest, TCGReg src) /* With MIE3, and bit 0 of m4 set, we get the complete result. */ if (HAVE_FACILITY(MISC_INSN_EXT3)) { if (type =3D=3D TCG_TYPE_I32) { - tgen_ext32u(s, dest, src); + tcg_out_ext32u(s, dest, src); src =3D dest; } tcg_out_insn(s, RRFc, POPCNT, dest, src, 8); @@ -1618,7 +1618,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, Mem= Op opc, TCGReg data, case MO_UL | MO_BSWAP: /* swapped unsigned int load with upper bits zeroed */ tcg_out_insn(s, RXY, LRV, data, base, index, disp); - tgen_ext32u(s, data, data); + tcg_out_ext32u(s, data, data); break; case MO_UL: tcg_out_insn(s, RXY, LLGF, data, base, index, disp); @@ -1743,7 +1743,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg = addr_reg, MemOp opc, offsetof(CPUTLBEntry, addend)); =20 if (TARGET_LONG_BITS =3D=3D 32) { - tgen_ext32u(s, TCG_REG_R3, addr_reg); + tcg_out_ext32u(s, TCG_REG_R3, addr_reg); return TCG_REG_R3; } return addr_reg; @@ -1812,7 +1812,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) tcg_out_ext16u(s, TCG_REG_R4, data_reg); break; case MO_UL: - tgen_ext32u(s, TCG_REG_R4, data_reg); + tcg_out_ext32u(s, TCG_REG_R4, data_reg); break; case MO_UQ: tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, data_reg); @@ -1879,7 +1879,7 @@ static void tcg_prepare_user_ldst(TCGContext *s, TCGR= eg *addr_reg, TCGReg *index_reg, tcg_target_long *disp) { if (TARGET_LONG_BITS =3D=3D 32) { - tgen_ext32u(s, TCG_TMP0, *addr_reg); + tcg_out_ext32u(s, TCG_TMP0, *addr_reg); *addr_reg =3D TCG_TMP0; } if (guest_base < 0x80000) { @@ -2261,7 +2261,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, if (a2 & TCG_BSWAP_OS) { tcg_out_ext32s(s, a0, a0); } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) =3D=3D TCG_BSWAP_O= Z) { - tgen_ext32u(s, a0, a0); + tcg_out_ext32u(s, a0, a0); } break; =20 @@ -2528,8 +2528,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, tcg_out_ext32s(s, args[0], args[1]); break; case INDEX_op_extu_i32_i64: - case INDEX_op_ext32u_i64: - tgen_ext32u(s, args[0], args[1]); + tcg_out_ext32u(s, args[0], args[1]); break; =20 case INDEX_op_add2_i64: @@ -2627,6 +2626,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_ext16u_i32: case INDEX_op_ext16u_i64: case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: default: g_assert_not_reached(); } diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index fef19493d0..6464d1fb5e 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -522,6 +522,11 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg rd, T= CGReg rs) tcg_out_arithi(s, rd, rs, 0, SHIFT_SRA); } =20 +static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_arithi(s, rd, rs, 0, SHIFT_SRL); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -910,7 +915,7 @@ static void emit_extend(TCGContext *s, TCGReg r, int op) tcg_out_ext16u(s, r, r); break; case MO_32: - tcg_out_arith(s, r, r, 0, SHIFT_SRL); + tcg_out_ext32u(s, r, r); break; case MO_64: break; @@ -1134,7 +1139,7 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg = addr, int mem_index, =20 /* If the guest address must be zero-extended, do so now. */ if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_arithi(s, r0, addr, 0, SHIFT_SRL); + tcg_out_ext32u(s, r0, addr); return r0; } return addr; @@ -1231,7 +1236,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a, TCGReg addr, unsigned t_bits; =20 if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); + tcg_out_ext32u(s, TCG_REG_T1, addr); addr =3D TCG_REG_T1; } =20 @@ -1363,7 +1368,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= a, TCGReg addr, unsigned t_bits; =20 if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_arithi(s, TCG_REG_T1, addr, 0, SHIFT_SRL); + tcg_out_ext32u(s, TCG_REG_T1, addr); addr =3D TCG_REG_T1; } =20 @@ -1676,8 +1681,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_ext32s(s, a0, a1); break; case INDEX_op_extu_i32_i64: - case INDEX_op_ext32u_i64: - tcg_out_arithi(s, a0, a1, 0, SHIFT_SRL); + tcg_out_ext32u(s, a0, a1); break; case INDEX_op_extrl_i64_i32: tcg_out_mov(s, TCG_TYPE_I32, a0, a1); @@ -1733,6 +1737,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16u_i32: case INDEX_op_ext16u_i64: case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: default: g_assert_not_reached(); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 04e162a623..bc7b5a410c 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -622,6 +622,13 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg rd, T= CGReg rs) tcg_out_op_rr(s, INDEX_op_ext32s_i64, rd, rs); } =20 +static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); + tcg_debug_assert(TCG_TARGET_HAS_ext32u_i64); + tcg_out_op_rr(s, INDEX_op_ext32u_i64, rd, rs); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -780,7 +787,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */ - CASE_64(ext32u) /* Optional (TCG_TARGET_HAS_ext32u_i64). */ CASE_64(ext_i32) CASE_64(extu_i32) CASE_32_64(ctpop) /* Optional (TCG_TARGET_HAS_ctpop_*). */ @@ -864,6 +870,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16u_i32: case INDEX_op_ext16u_i64: case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: default: g_assert_not_reached(); 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Use it in tcg_reg_alloc_op in the meantime. Signed-off-by: Richard Henderson --- tcg/tcg.c | 4 ++++ tcg/aarch64/tcg-target.c.inc | 9 ++++++--- tcg/arm/tcg-target.c.inc | 5 +++++ tcg/i386/tcg-target.c.inc | 9 ++++++--- tcg/loongarch64/tcg-target.c.inc | 7 ++++++- tcg/mips/tcg-target.c.inc | 7 ++++++- tcg/ppc/tcg-target.c.inc | 9 ++++++--- tcg/riscv/tcg-target.c.inc | 7 ++++++- tcg/s390x/tcg-target.c.inc | 9 ++++++--- tcg/sparc64/tcg-target.c.inc | 9 ++++++--- tcg/tci/tcg-target.c.inc | 7 ++++++- 11 files changed, 63 insertions(+), 19 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index a182771c01..b0498170ea 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -111,6 +111,7 @@ static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TC= GReg arg); static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg); +static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g); static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); static void tcg_out_goto_tb(TCGContext *s, int which); @@ -4529,6 +4530,9 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) case INDEX_op_ext32u_i64: tcg_out_ext32u(s, new_args[0], new_args[1]); break; + case INDEX_op_ext_i32_i64: + tcg_out_exts_i32_i64(s, new_args[0], new_args[1]); + break; default: if (def->flags & TCG_OPF_VECTOR) { tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op), diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index bca5f03dfb..58596eaa4b 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1434,6 +1434,11 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg rd,= TCGReg rn) tcg_out_sxt(s, TCG_TYPE_I64, MO_32, rd, rn); } =20 +static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) +{ + tcg_out_ext32s(s, rd, rn); +} + static inline void tcg_out_uxt(TCGContext *s, MemOp s_bits, TCGReg rd, TCGReg rn) { @@ -2260,9 +2265,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; =20 - case INDEX_op_ext_i32_i64: - tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a1); - break; case INDEX_op_extu_i32_i64: tcg_out_ext32u(s, a0, a1); break; @@ -2332,6 +2334,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16u_i32: case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: default: g_assert_not_reached(); } diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 5c48b92f83..2ca25a3d81 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1003,6 +1003,11 @@ static void tcg_out_ext32u(TCGContext *s, TCGReg rd,= TCGReg rn) g_assert_not_reached(); } =20 +static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) +{ + g_assert_not_reached(); +} + static void tcg_out_bswap16(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn, int flags) { diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 1e9f61dbf3..df7c2409cd 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1299,6 +1299,11 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg des= t, TCGReg src) tcg_out_modrm(s, OPC_MOVSLQ, dest, src); } =20 +static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) +{ + tcg_out_ext32s(s, dest, src); +} + static inline void tcg_out_bswap64(TCGContext *s, int reg) { tcg_out_opc(s, OPC_BSWAP + P_REXW + LOWREGMASK(reg), 0, reg, 0); @@ -2757,9 +2762,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_extrl_i64_i32: tcg_out_ext32u(s, a0, a1); break; - case INDEX_op_ext_i32_i64: - tcg_out_ext32s(s, a0, a1); - break; case INDEX_op_extrh_i64_i32: tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32); break; @@ -2838,6 +2840,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_ext16u_i64: case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: default: g_assert_not_reached(); } diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index d2511eda7a..989632e08a 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -456,6 +456,11 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, = TCGReg arg) tcg_out_opc_addi_w(s, ret, arg, 0); } =20 +static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_ext32s(s, ret, arg); +} + static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc, TCGReg a0, TCGReg a1, TCGReg a2, bool c2, bool is_32bit) @@ -1251,7 +1256,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_extrl_i64_i32: - case INDEX_op_ext_i32_i64: tcg_out_ext32s(s, a0, a1); break; =20 @@ -1615,6 +1619,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16u_i64: case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: default: g_assert_not_reached(); } diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index fe90547c43..df36bec5c0 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -580,6 +580,11 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg rd, T= CGReg rs) tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); } =20 +static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_ext32s(s, rd, rs); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -2294,7 +2299,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_extrh_i64_i32: tcg_out_dsra(s, a0, a1, 32); break; - case INDEX_op_ext_i32_i64: case INDEX_op_extrl_i64_i32: tcg_out_ext32s(s, a0, a1); break; @@ -2447,6 +2451,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16s_i64: case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: default: g_assert_not_reached(); } diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 5d25e30851..6b4742fd7b 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -806,6 +806,11 @@ static void tcg_out_ext32u(TCGContext *s, TCGReg dst, = TCGReg src) tcg_out_rld(s, RLDICL, dst, src, 0, 32); } =20 +static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dst, TCGReg src) +{ + tcg_out_ext32s(s, dst, src); +} + static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, i= nt c) { tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c); @@ -2980,9 +2985,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_st(s, args, true); break; =20 - case INDEX_op_ext_i32_i64: - tcg_out_ext32s(s, args[0], args[1]); - break; case INDEX_op_extu_i32_i64: tcg_out_ext32u(s, args[0], args[1]); break; @@ -3132,6 +3134,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16u_i64: case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: default: g_assert_not_reached(); } diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 1d91fd19c6..7bd3b421ad 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -602,6 +602,11 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, = TCGReg arg) tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0); } =20 +static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_ext32s(s, ret, arg); +} + static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, TCGReg addr, intptr_t offset) { @@ -1602,7 +1607,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_extrl_i64_i32: - case INDEX_op_ext_i32_i64: tcg_out_ext32s(s, a0, a1); break; =20 @@ -1639,6 +1643,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16u_i64: case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: default: g_assert_not_reached(); } diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 825dbfc523..60deaa9a95 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1122,6 +1122,11 @@ static void tcg_out_ext32u(TCGContext *s, TCGReg des= t, TCGReg src) tcg_out_insn(s, RRE, LLGFR, dest, src); } =20 +static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) +{ + tcg_out_ext32s(s, dest, src); +} + static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t= val) { int msb, lsb; @@ -2524,9 +2529,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, } break; =20 - case INDEX_op_ext_i32_i64: - tcg_out_ext32s(s, args[0], args[1]); - break; case INDEX_op_extu_i32_i64: tcg_out_ext32u(s, args[0], args[1]); break; @@ -2627,6 +2629,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_ext16u_i64: case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: default: g_assert_not_reached(); } diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 6464d1fb5e..56ffc6ed91 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -527,6 +527,11 @@ static void tcg_out_ext32u(TCGContext *s, TCGReg rd, T= CGReg rs) tcg_out_arithi(s, rd, rs, 0, SHIFT_SRL); } =20 +static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_ext32s(s, rd, rs); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -1677,9 +1682,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_divu_i64: c =3D ARITH_UDIVX; goto gen_arith; - case INDEX_op_ext_i32_i64: - tcg_out_ext32s(s, a0, a1); - break; case INDEX_op_extu_i32_i64: tcg_out_ext32u(s, a0, a1); break; @@ -1738,6 +1740,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16u_i64: case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: default: g_assert_not_reached(); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index bc7b5a410c..7886f21bf5 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -629,6 +629,11 @@ static void tcg_out_ext32u(TCGContext *s, TCGReg rd, T= CGReg rs) tcg_out_op_rr(s, INDEX_op_ext32u_i64, rd, rs); } =20 +static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_ext32s(s, rd, rs); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -787,7 +792,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */ - CASE_64(ext_i32) CASE_64(extu_i32) CASE_32_64(ctpop) /* Optional (TCG_TARGET_HAS_ctpop_*). */ case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */ @@ -871,6 +875,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16u_i64: case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: default: g_assert_not_reached(); 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([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921806; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xzu39GMRV6RuI6NlIOVSyEEbNk34csPDYcvNvBnA8aU=; b=BV4QZLoD9jWd/KXOoAfWwR5QX2ZB5xwkbSayYZPtKFJA7xaXLzTS5HqJyGZPLYlOm2 dNfmSkrBjBUqD/vKNXWMPv0ZBfxpU2GmNNAhhaZpdxqKYcZoFfYW/pqwtQYtmKU6FaOL 9k+grM5btznLFtRGn10n4ASK4z4v6zk5JwwuUpfenyBGsPISlJ0koP0ZLSK9hOzK+LeW f5781+DGyR48TS2OAUabQUWlK52TxLbY2bzlt85j2Oj3IBFYwXsGnLxZ5CCbw9XMaDuc p60Pvtg7tS8bL/6+B9+3kxiUzfsngtCpnK7NS/KcZlzM/cCSHWtnoUH4cvFnBp9MP5ST R8Nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921806; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xzu39GMRV6RuI6NlIOVSyEEbNk34csPDYcvNvBnA8aU=; b=qweH5xIlzp1DyOtxhSoybYQTiUN7bOO6jwwEIjck7jUhH3CAkssq7RLo2WjLpjIbYl puHFiiZ9dqQthwrr+FdU9rnpbsfgaDWueEO4G4E+Lhp9muMI4e0RFxFxGvmlG7+tuTcT w65AIIlUglfrP1ENvJD9rz56wqB0BtUyqNMF8H9Q8IVvTDSwm3uGSwb4WQsMp08CWX2m jFGvi2ZNugXrLTKpLDsAKj8qSUx8cs0XvtJgY+B137ANFp2r1wBn+hEyCCMVK9tyY+5y qZ2j5+WAch7XNKr/NBDYnkI1JIvSG0KNDKzmuCSNk09vjvXLvVL0n8PF0dBPVNHRylu+ 9mMw== X-Gm-Message-State: AAQBX9ejOrcYgJHV2djx67NG5lcVLo+oDGBk1JLWQT82CBleihFG1uks IpHbdZYcWQbM7UGaMiQGv5yax6W2IhGD+ytRy4o= X-Google-Smtp-Source: AKy350bjlN+g2dEDL+Z3hNVyW7nM9r6v61fMZl9pFSqzL5F7FEXY6cKd1tSdEX94EpmipjKaNZB7PA== X-Received: by 2002:a17:903:68d:b0:1a5:f:a7c7 with SMTP id ki13-20020a170903068d00b001a5000fa7c7mr4317569plb.0.1680921805877; Fri, 07 Apr 2023 19:43:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 10/42] tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64 Date: Fri, 7 Apr 2023 19:42:42 -0700 Message-Id: <20230408024314.3357414-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922187159100003 Content-Type: text/plain; charset="utf-8" Since TCG_TYPE_I32 values are kept sign-extended in registers, via ".w" instructions, we need not extend if the register matches. This is already relied upon by comparisons. Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 989632e08a..b2146988be 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -458,7 +458,9 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, T= CGReg arg) =20 static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) { - tcg_out_ext32s(s, ret, arg); + if (ret !=3D arg) { + tcg_out_ext32s(s, ret, arg); + } } =20 static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc, --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680921961; cv=none; d=zohomail.com; s=zohoarc; b=gFn3Zw6PdQPIoqstJ0EbMBPYtr/rU6z835vlDEnXnsWPrmkmAGu1kYoePWlLhooCflY+VzuPLuREckIwqbtFeaSw01H0bnZ7D7NvTLTZlnQ89gzYWRDjEo+i7V/Eq803ytFmOkEA11fxeztPo96sCakIVFcz6N24prSYnpaDi0M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680921961; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2UYA/jGhRJM+9A6MoPBOmAbOd+q/t7vvHeLmOB409P8=; b=lB+H2xnI4irC+ZSs37ByyhHPwO+i43nOgqQH/26N8j0OhJrmDDLTLaqDZXF0IZq3Z8SOzLTWcS8LUCrOTGsnpkGpPQtz63U571kA6tlp9Vr1jjRx9z+WvVBObIX87Rt27sZUyG5KgJIgLjVXIUgQU/7jiwCE2MgfvmOyRLnMHnk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680921961605103.42253946901644; Fri, 7 Apr 2023 19:46:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyYM-0007O5-La; Fri, 07 Apr 2023 22:43:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyYJ-0007Ir-Kn for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:43:43 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyY4-0005dc-54 for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:43:43 -0400 Received: by mail-pj1-x102b.google.com with SMTP id c3so663876pjg.1 for ; Fri, 07 Apr 2023 19:43:27 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921806; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2UYA/jGhRJM+9A6MoPBOmAbOd+q/t7vvHeLmOB409P8=; b=u2rF4fWhJ8Ci9PeVl3IYHBgjlwfx65cS/iWcV4Yf/wusb1jy9lEIU/2jxqZYTRwQQe MNjWj1PLEWyipIp3wzsTClT5GnWvDW1v30qKJxQM4Ew+9dk/T1qLnWLPeDgnsu1pSHIJ ShlgvVC+5gcQl0Se96VPjrDHy53Im1foUBnOUNNB7mUSE12H1KBeF3ZbD82yI1vyrJjQ xALwavkLh70NHZWYybDgRq0qkfX/U2JfANvP+GkX4wLiKiHaVNAik75CwvvuJBUh0E8f OciA6Mz/z5KtKSq76AgWcA9/1E1SorIFT3AFCMv0u01PH3hU/mCGjjd6Z2beUaIt1alM 9Hbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921806; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2UYA/jGhRJM+9A6MoPBOmAbOd+q/t7vvHeLmOB409P8=; b=lkuxJ/U2Umel+QBtC7opd44qq8fp9lA0ViCTnLh7nI/IR9JZAy6lHSSESdpVkzS+2h BiQRKEfosXkIVr4czhOVQGXziG4e3x5NqXQC/fmvd5SHCiOr+HgPQ5J0PVSZjD4U5zkq YYH4e8z5AHztdKO/SvwJvRZpyv4zRMMrRlge2wOJyIrIvNbrLEsmUQaOSglNZakCqxPG g/auUVyUcMwjqlqm7KXUKCdaTjMyqpLCO9wgr5edY9Nezf3e5MzT7trWorJ+ypfGRny3 6iM34uA0k32MiB6S6lLLHGvEcAvJRlOot6fBNWZDjiUD5rAOEb5OvnGwzC0IH/OimHdw SB5Q== X-Gm-Message-State: AAQBX9d4/+B+DkV20w5Qf0HbHM/rBSDZfr199431Zr8TgdBsZeywSDDI ftjKAKu/mqEg9WTdxwtFTM6V3+cQg6CS9cdFT8Q= X-Google-Smtp-Source: AKy350Y7JQrtlrM3NuyBbmPFeS2i7QarYZzA3ZiWugdBq1ZjugNMkvOz0XDHciZlcoSOX6kKL7cRtg== X-Received: by 2002:a17:902:d192:b0:19c:e664:5e64 with SMTP id m18-20020a170902d19200b0019ce6645e64mr535056plb.2.1680921806724; Fri, 07 Apr 2023 19:43:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 11/42] tcg/mips: Conditionalize tcg_out_exts_i32_i64 Date: Fri, 7 Apr 2023 19:42:43 -0700 Message-Id: <20230408024314.3357414-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680921963399100007 Content-Type: text/plain; charset="utf-8" Since TCG_TYPE_I32 values are kept sign-extended in registers, we need not extend if the register matches. This is already relied upon by comparisons. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index df36bec5c0..2bc885e00e 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -582,7 +582,9 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TC= GReg rs) =20 static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) { - tcg_out_ext32s(s, rd, rs); + if (rd !=3D rs) { + tcg_out_ext32s(s, rd, rs); + } } =20 static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680921978; cv=none; d=zohomail.com; s=zohoarc; b=gf3QyMtBeC1zrUaS1sM5PT4usyYaGQ1PdcNG7TuoKbVbbVC5RYaq5E+pB6Bee+ZvpCXRQxkhxwXJJTesnGpjMZQCVcKUAWXxWOsYJhKhkh//qy0D9y+TXgkG9YxAg1vQyrxgbHir6M3z7gbzkfoOMHeu9hs0AAe1dM0ChH+yWGg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680921978; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wmUvCy83uzUq+qlSl4tyoYDR2G5J3ycXbuZkZjm5Y8A=; b=JQJInsS3LslkmixY71KXOAHqfMBzlyfh3fGT8MCBsmANu1jBzoUvdm2aNV1lMWdU/7b8T6Qycr4Wh3Xl0+4n/Nor796YyKvf4vivDoLk1A2d9JJFAhmoEFJ2846vWYxFKgC8HqC9+ZukBT2Jhyi8sMPqXsEnY8eF6l3qMqdfZ5E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680921978391452.38127823837397; Fri, 7 Apr 2023 19:46:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyYM-0007OI-PE; Fri, 07 Apr 2023 22:43:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyYJ-0007JK-PR for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:43:43 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyY4-0005WV-C7 for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:43:43 -0400 Received: by mail-pl1-x636.google.com with SMTP id w11so368651plp.13 for ; Fri, 07 Apr 2023 19:43:27 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921807; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wmUvCy83uzUq+qlSl4tyoYDR2G5J3ycXbuZkZjm5Y8A=; b=A2ililufGQuYTzNPqtP/V7tjyrFn2iBMD2rUjURFCQRZYVtYMCubdskWauOo8LuFcN np7l69jOAdhFdrKHd+REhe0FMB/F27dJjkvnqFHRG7q8So8U+4uv+4Y0a0YGYl9BxWwF MCN3NpXVoyCqGQKEKVfvXHNCac0C+TFSZvH/TPfe0xMpj+F1zjoGUa6O5huFEeK3S/0+ W08RfqHf9LXxbOWT83yHqviAIMphAIORCQ+NLzJhQ1fVi7IojyHa5rqD5wmNGXiZRSGP ZagNpqfwEsmQT6d/++3O9EeifezUN5W5niIn73+0bDxL/+3aUPjbPSK4EB7aMSlm3cMF 9xug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921807; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wmUvCy83uzUq+qlSl4tyoYDR2G5J3ycXbuZkZjm5Y8A=; b=ec52hjmbfXhKOZoYwSdprmTCHk3rl0Hv9DlIQk+CVmOXoRwXeWdWmL8TEl8fJdgo1o H5Pwv5fNI/aMWJ6mkowKtgW7oB/VZAfn8Ygkagoqd6qsHgA++Vhj5jAHy42CBCjg8gdM BnO0UxuVr4a0QpQ3DBHQgvzEKfMxsHz8rjochWEHh9imC/thOAYcy0Ibn/b/6KWUF33p 0IGpqWQ3EDjLbDR9dbEcY7NLbA7ApZwgvvlgIIiCLG3EluyqTYsDTBHQ/uu/+Da8t3/o ZT2TOsotu3Z+H86V0l0x65dqG74wofCkzqhzzU61a9uMcCE9DeOVen6eLvwQd+Jn292k IK+w== X-Gm-Message-State: AAQBX9enoQ4eMkTFXGMCFdkCeiBZ380fxwop08lRIA8dTqC3giHPOeC4 w72S/xb6EEPDOncU2X+5Rz7ZnTtTQAQRXlEaf7g= X-Google-Smtp-Source: AKy350bG7sgeLoY9ztiMZpZLBb8cKAcrTZWl3T97yxtlXtX/3yqlAWGl23WuqQJ/dYXp3yV//ofJKw== X-Received: by 2002:a17:902:db09:b0:1a2:8924:224a with SMTP id m9-20020a170902db0900b001a28924224amr5590006plx.25.1680921807559; Fri, 07 Apr 2023 19:43:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 12/42] tcg/riscv: Conditionalize tcg_out_exts_i32_i64 Date: Fri, 7 Apr 2023 19:42:44 -0700 Message-Id: <20230408024314.3357414-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680921980197100005 Content-Type: text/plain; charset="utf-8" Since TCG_TYPE_I32 values are kept sign-extended in registers, via "w" instructions, we need not extend if the register matches. This is already relied upon by comparisons. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 7bd3b421ad..2b9aab29ec 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -604,7 +604,9 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, T= CGReg arg) =20 static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) { - tcg_out_ext32s(s, ret, arg); + if (ret !=3D arg) { + tcg_out_ext32s(s, ret, arg); + } } =20 static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922004; cv=none; d=zohomail.com; s=zohoarc; b=WuRnmemA5rtbe8UNGIEHaKbtJIwkrqV0Jziw2EoXPgmVbE8oLoNWsgM8dwBe5ku9Dopo/0Agv+HpKaAy3RrIuP0EsV3tfuf+mnY9++KOEeabZcwcsz8aOdl9O5i8+06COafOWdO9ILaOLlF3OM4WbHzASQoZSKJlXrhvbbPeI6U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680922004; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HJD/F/y1EUzF45CHF3b0xx/2gHrD7M8qRyPe0SV4Bgk=; b=BDU9BxsPGeZsCtmQozmaaVz+wU/S4G8mPjx97Po32EFKQt5DoDl6dLkKfXo9lONuD1nIzaNbLMepFk7UEbTUk6z+lC/VHzuVLurFkbL3ttCpvCRgmV49dM6479XOUIG/MmvLjTrztENw86blB2pWoNbMn9JdgwrPSclSxoFzMfk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680922004085948.4408256604714; Fri, 7 Apr 2023 19:46:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyYP-0007Sd-JR; Fri, 07 Apr 2023 22:43:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyYM-0007OL-Ns for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:43:46 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyY5-0005Wo-BG for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:43:46 -0400 Received: by mail-pl1-x62b.google.com with SMTP id e13so56935plc.12 for ; Fri, 07 Apr 2023 19:43:28 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921808; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HJD/F/y1EUzF45CHF3b0xx/2gHrD7M8qRyPe0SV4Bgk=; b=sLPjSGVzGveX08xU1ylZ4N+/Ck+ybh/XaqRckd9x+ck+A9Rirmx5r6g73T2Mp2GnDy iZ8lfZAz4L8LuSaHIfB8a+tBbTW2hP/j71AClSLGJ8mXMEuzHpbMSBF/ljKN3BP0TIA+ f+GwWK8Osuq+KN11G534wAG5fFmPLeXTFFNNZ+toba6dQIibbQKG+0j1NMIxzWlKzJvy Qg8/9Keu0f4wO0NRs92YTlXw36muzF+KaIkfvyc6jK81rEcUbXgyOo8PNACRQ5m2hGfJ hcWcdY8Vck65aOfPWgQJZqjy+6HKYVbX37/Zoc1KIdtL/X9JUYMcuyBKSMQFnyMpIMJI DpSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921808; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HJD/F/y1EUzF45CHF3b0xx/2gHrD7M8qRyPe0SV4Bgk=; b=E3uL1VQHCgyL4Wr7mjDVChoZ8E2WhFWUog/4jh11CUilfZnUX2c+Aj+DXMV1c5n3X+ q9OAccqww99aR7PGbA8sDoTuWzfrBRMklxKaOET3/bSG9MDR48vCLv5vgJSVPr/RTWpe Zl9ANoE/WZedP5BNEtV+h/8Pa9OU0xKcaBHS0CFuwMtmCsLPFRXY+nIv2rRbieXdOevW dVGTNFXk5BpCizQHZF5n+tR4qT5GkvakkFQw5TkiV9RQkJs5N9rJTTqWPpMPLufzCHLk bmjU5/n26n8PM0jrGmipuz5NghHaX+XpmQPn4wATICY7p+pMdFt1BDaF3bCBMlPrfUJK 2cIw== X-Gm-Message-State: AAQBX9cC1cdnzdbNpbcvxCwa7peiZB0dXdOcdwHB6PJAoykl4/q+moWi S8yUwyUH84PQ1jTwnofmxRS261J51UVP0QvZVjA= X-Google-Smtp-Source: AKy350ZrN/ihVRjrKDiHgOL1is53xzBomWq7aawjhrRfx9lZdyQ7EdMFtZGuBtcLqxh0MH4qm9jcQg== X-Received: by 2002:a17:903:2309:b0:1a0:4fb2:6623 with SMTP id d9-20020a170903230900b001a04fb26623mr5707182plh.40.1680921808428; Fri, 07 Apr 2023 19:43:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 13/42] tcg: Split out tcg_out_extu_i32_i64 Date: Fri, 7 Apr 2023 19:42:45 -0700 Message-Id: <20230408024314.3357414-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922006101100003 Content-Type: text/plain; charset="utf-8" We will need a backend interface for type extension with zero. Use it in tcg_reg_alloc_op in the meantime. Signed-off-by: Richard Henderson --- tcg/tcg.c | 4 ++++ tcg/aarch64/tcg-target.c.inc | 10 ++++++---- tcg/arm/tcg-target.c.inc | 5 +++++ tcg/i386/tcg-target.c.inc | 7 ++++++- tcg/loongarch64/tcg-target.c.inc | 10 ++++++---- tcg/mips/tcg-target.c.inc | 9 ++++++--- tcg/ppc/tcg-target.c.inc | 10 ++++++---- tcg/riscv/tcg-target.c.inc | 10 ++++++---- tcg/s390x/tcg-target.c.inc | 10 ++++++---- tcg/sparc64/tcg-target.c.inc | 9 ++++++--- tcg/tci/tcg-target.c.inc | 7 ++++++- 11 files changed, 63 insertions(+), 28 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index b0498170ea..17bd6d4581 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -112,6 +112,7 @@ static void tcg_out_ext16u(TCGContext *s, TCGReg ret, T= CGReg arg); static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg); +static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g); static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); static void tcg_out_goto_tb(TCGContext *s, int which); @@ -4533,6 +4534,9 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) case INDEX_op_ext_i32_i64: tcg_out_exts_i32_i64(s, new_args[0], new_args[1]); break; + case INDEX_op_extu_i32_i64: + tcg_out_extu_i32_i64(s, new_args[0], new_args[1]); + break; default: if (def->flags & TCG_OPF_VECTOR) { tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op), diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 58596eaa4b..ca8b25865b 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1462,6 +1462,11 @@ static void tcg_out_ext32u(TCGContext *s, TCGReg rd,= TCGReg rn) tcg_out_movr(s, TCG_TYPE_I32, rd, rn); } =20 +static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) +{ + tcg_out_ext32u(s, rd, rn); +} + static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd, TCGReg rn, int64_t aimm) { @@ -2265,10 +2270,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; =20 - case INDEX_op_extu_i32_i64: - tcg_out_ext32u(s, a0, a1); - break; - case INDEX_op_deposit_i64: case INDEX_op_deposit_i32: tcg_out_dep(s, ext, a0, REG0(2), args[3], args[4]); @@ -2335,6 +2336,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: default: g_assert_not_reached(); } diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 2ca25a3d81..2135616e12 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1008,6 +1008,11 @@ static void tcg_out_exts_i32_i64(TCGContext *s, TCGR= eg rd, TCGReg rn) g_assert_not_reached(); } =20 +static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rn) +{ + g_assert_not_reached(); +} + static void tcg_out_bswap16(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn, int flags) { diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index df7c2409cd..818e7cbc3d 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1304,6 +1304,11 @@ static void tcg_out_exts_i32_i64(TCGContext *s, TCGR= eg dest, TCGReg src) tcg_out_ext32s(s, dest, src); } =20 +static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) +{ + tcg_out_ext32u(s, dest, src); +} + static inline void tcg_out_bswap64(TCGContext *s, int reg) { tcg_out_opc(s, OPC_BSWAP + P_REXW + LOWREGMASK(reg), 0, reg, 0); @@ -2758,7 +2763,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_bswap64_i64: tcg_out_bswap64(s, a0); break; - case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: tcg_out_ext32u(s, a0, a1); break; @@ -2841,6 +2845,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: default: g_assert_not_reached(); } diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index b2146988be..d83bd9de49 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -463,6 +463,11 @@ static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg= ret, TCGReg arg) } } =20 +static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_ext32u(s, ret, arg); +} + static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc, TCGReg a0, TCGReg a1, TCGReg a2, bool c2, bool is_32bit) @@ -1253,10 +1258,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); break; =20 - case INDEX_op_extu_i32_i64: - tcg_out_ext32u(s, a0, a1); - break; - case INDEX_op_extrl_i64_i32: tcg_out_ext32s(s, a0, a1); break; @@ -1622,6 +1623,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: default: g_assert_not_reached(); } diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 2bc885e00e..4789b0a40c 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -587,6 +587,11 @@ static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg= rd, TCGReg rs) } } =20 +static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_ext32u(s, rd, rs); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -2304,9 +2309,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_extrl_i64_i32: tcg_out_ext32s(s, a0, a1); break; - case INDEX_op_extu_i32_i64: - tcg_out_ext32u(s, a0, a1); - break; =20 case INDEX_op_sar_i32: i1 =3D OPC_SRAV, i2 =3D OPC_SRA; @@ -2454,6 +2456,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: default: g_assert_not_reached(); } diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 6b4742fd7b..01924fdf51 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -811,6 +811,11 @@ static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg= dst, TCGReg src) tcg_out_ext32s(s, dst, src); } =20 +static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dst, TCGReg src) +{ + tcg_out_ext32u(s, dst, src); +} + static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, i= nt c) { tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c); @@ -2985,10 +2990,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_st(s, args, true); break; =20 - case INDEX_op_extu_i32_i64: - tcg_out_ext32u(s, args[0], args[1]); - break; - case INDEX_op_setcond_i32: tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2= ], const_args[2]); @@ -3135,6 +3136,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: default: g_assert_not_reached(); } diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 2b9aab29ec..a6d352976c 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -609,6 +609,11 @@ static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg= ret, TCGReg arg) } } =20 +static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_ext32u(s, ret, arg); +} + static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, TCGReg addr, intptr_t offset) { @@ -1604,10 +1609,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_st(s, args, true); break; =20 - case INDEX_op_extu_i32_i64: - tcg_out_ext32u(s, a0, a1); - break; - case INDEX_op_extrl_i64_i32: tcg_out_ext32s(s, a0, a1); break; @@ -1646,6 +1647,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: default: g_assert_not_reached(); } diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 60deaa9a95..e17d000991 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1127,6 +1127,11 @@ static void tcg_out_exts_i32_i64(TCGContext *s, TCGR= eg dest, TCGReg src) tcg_out_ext32s(s, dest, src); } =20 +static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) +{ + tcg_out_ext32u(s, dest, src); +} + static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t= val) { int msb, lsb; @@ -2529,10 +2534,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpco= de opc, } break; =20 - case INDEX_op_extu_i32_i64: - tcg_out_ext32u(s, args[0], args[1]); - break; - case INDEX_op_add2_i64: if (const_args[4]) { if ((int64_t)args[4] >=3D 0) { @@ -2630,6 +2631,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: default: g_assert_not_reached(); } diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 56ffc6ed91..c57a8c8304 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -532,6 +532,11 @@ static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg= rd, TCGReg rs) tcg_out_ext32s(s, rd, rs); } =20 +static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_ext32u(s, rd, rs); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -1682,9 +1687,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_divu_i64: c =3D ARITH_UDIVX; goto gen_arith; - case INDEX_op_extu_i32_i64: - tcg_out_ext32u(s, a0, a1); - break; case INDEX_op_extrl_i64_i32: tcg_out_mov(s, TCG_TYPE_I32, a0, a1); break; @@ -1741,6 +1743,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: default: g_assert_not_reached(); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 7886f21bf5..48c9dbd0b4 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -634,6 +634,11 @@ static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg= rd, TCGReg rs) tcg_out_ext32s(s, rd, rs); } =20 +static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_ext32u(s, rd, rs); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -792,7 +797,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, =20 CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */ - CASE_64(extu_i32) CASE_32_64(ctpop) /* Optional (TCG_TARGET_HAS_ctpop_*). */ case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */ case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */ @@ -876,6 +880,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext32s_i64: case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: default: g_assert_not_reached(); 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([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921809; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FDeASIhXoXuX3vLvF4wYaR7o+wyDzGwiI17/AXuSlGM=; b=bX5r0PoiTGPh+kw7i5vjujE6O4dHH9iKb23m1GNMZ5EBw8thUk0VNZ5M5gKuLfMjKB ijrrv/6b8FMM4djGDY/HE2cizf2MhcX5xxATBXSQzVc4TKfJZYcfhRk70AUqmp8s4dEZ KLRollHOEjdkgFi+mbPDX9fTD1RA3dwQ1jkrKd1HzPbFLORIe3Kx+D9E2+bJeyq6lpEg u6PRVs1N8HyzdKhNQVFQLokVihNorFtpvuw2h7Ti5RjUzQY6sJtxb3O9Xwh8Hso1xVn/ Gm7KTTYugjTh/AzTxX9bOW55MkEuwXesNG4J5GnKzVwsdMexDnC3lL+nbKGb5MYNHICN JgbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921809; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FDeASIhXoXuX3vLvF4wYaR7o+wyDzGwiI17/AXuSlGM=; b=RZda/1tL3/RvwjaEtd5dfnxoDSp+e/W7sUDPTZPNKbegyAKKF5sAjgQhn6/3pVgbOZ PaxTQbK2atTqhTtd0s8s7KPbqQ37Uhkj56qRGy5+mjNXJLoeLAjhyDR7T7wxy8NHgqLH Zp4IcO7EoLTDAmrKY1fp3WdM7xkwazxsEQt5Vl1v1/Mib6qkoQFwleJ/Vd3ct9c/ieCB jq8oXiDItz0QvIbdAOkWxWFvw8lh29rhFI/YPvmYbXTWY9hvCAY/l+4HKDH8ELA/hx8r ut20WZw10S4nDGpZXJB5xxt4zp1jhuagapCbTlkw6NacEy40wzGoKvVVb5u4e8FyK+Ea fMSw== X-Gm-Message-State: AAQBX9da1ULZVpu7e2OG0g4xwo2ew2q3lsRiPYGhamr7cejLj96dIUqm XymVaTHv5yEY250ohErDr+kzwUtRwWSBoTG8BpI= X-Google-Smtp-Source: AKy350brlMqd7F1ibt7xsBb/+NvTFqDEQXuQQa/rlEhkM0CPq/wGUQjTbq5nKEDqTHr1drnE8Y8JDw== X-Received: by 2002:a17:902:c111:b0:1a2:9051:f0a3 with SMTP id 17-20020a170902c11100b001a29051f0a3mr4066030pli.24.1680921809232; Fri, 07 Apr 2023 19:43:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 14/42] tcg/i386: Conditionalize tcg_out_extu_i32_i64 Date: Fri, 7 Apr 2023 19:42:46 -0700 Message-Id: <20230408024314.3357414-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680921917167100002 Content-Type: text/plain; charset="utf-8" Since TCG_TYPE_I32 values are kept zero-extended in registers, via omission of the REXW bit, we need not extend if the register matches. This is already relied upon by qemu_{ld,st}. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 818e7cbc3d..71a2bff234 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1306,7 +1306,9 @@ static void tcg_out_exts_i32_i64(TCGContext *s, TCGRe= g dest, TCGReg src) =20 static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dest, TCGReg src) { - tcg_out_ext32u(s, dest, src); + if (dest !=3D src) { + tcg_out_ext32u(s, dest, src); + } } =20 static inline void tcg_out_bswap64(TCGContext *s, int reg) --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922347; cv=none; d=zohomail.com; s=zohoarc; b=k/DRVKO9lipO3n52jT2NoAsgL06r/Tss8QUcg05o4pGO6CcXqLj7f2LhgzSYXv3zfJ1yyZmd1V+2lQ+mWR0AG4/Y1Vx1GYQSl8teajKwVzKAvuQiGvZg21x9p3dSqKud9UrDmcz4pPrrUAUJhBQ+3DZwZODYjeAkUPYpslMFzAo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680922347; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gfrcrwTN/lp3cZCk0Pdqdg+ZowAN5o7wmPz80gOA6Ho=; b=K5nMvyWB4RswTS/jWzv+di+qexLxbC/WdUQX2RphoT6t9xx1B+pGFbRx6jSIVD5tqoNaa7xmQhxEIUpZwWPMW1xFqO9Ppj+bZRKNIJtb/ci9NnL9gUfmQShiwusPutVQI661ny+HVR5spAaX9UwVLLeE+Ws83oihHaWkLT4r/IU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16809223475171018.5176401608313; Fri, 7 Apr 2023 19:52:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyYR-0007V3-LR; Fri, 07 Apr 2023 22:43:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyYP-0007T1-Se for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:43:49 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyY7-0005fs-I0 for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:43:49 -0400 Received: by mail-pj1-x1029.google.com with SMTP id go23so3074356pjb.4 for ; Fri, 07 Apr 2023 19:43:31 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921810; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gfrcrwTN/lp3cZCk0Pdqdg+ZowAN5o7wmPz80gOA6Ho=; b=Koqj7JAs8M7ggUSCk/pAMZYUs9jHyhawDrpWcqLi0zAACONcmR8IQW2+72vLl1OH6k K6282zKRk/Cpibxm3XuOd3gAhKSdip/5i+MThUTlgz7Rlull2vS2AYpqJBxGMN6athm4 QnL1TNg0gqaM9G/L8aX9r+4gMpCezAuarN4Xn5cDWM3mNsZgRRJ0z/ZY9VMqSTUOro7o eLvHr/2M2+RtS0q2AFJGU6vqaE0W+lCkzxcAbnU81FcVIMKm/ZGjCvRqxzb1joyza5yK 8qg8dmTC+TRmLbG6tNDDDrxsv2RYc7b5cd2gg0Im3jgWxzP6s3v/FkMLMhD4l7dHET+t mhuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921810; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gfrcrwTN/lp3cZCk0Pdqdg+ZowAN5o7wmPz80gOA6Ho=; b=H6U08G+vXUoyspobLzrKPBx2hsiXNfOi+cBAZMgr0PQRnTEkCvmN8naJ3L4qxB1C5q kFXZc+70OO3nK7t30lKkZLs4qRYqoQQNr4RBNpd3a360PoiimKYOl/JiXmERgHSXDN8y T/fkoE11rFxsPHZmM4JaP8xaUxZwkuULI2LmjDcsQQZeYCq5vt3TvmU2jhnvI+8dyX+q aTZBmkYSqBiVyEzsjfua62t627uS3dG8oEMluJl8bDngDg/IQZAjHHx95Ghxn25homLf bPcaZ/6O3uzRvdnE/wOkbM82PfXH1RmGLFSs7ruzBU74DN9xr+8aetaqU/cIBSaYj5Wf n3Iw== X-Gm-Message-State: AAQBX9faAoWHt+/WxNR4gczkxm/OSQT/E0GdECKgAAvSTvkutxXfwlqj qOowddBzPBt9GlI8r+3+T6VJye+FOcGEP5ONnzE= X-Google-Smtp-Source: AKy350ZXQqYQZJ9v6CpUGZGLI3ATRUeAzAA3H2ZMso1cv1Y9um+hAnFWvMoitPo5aW9CTuEMw05vTQ== X-Received: by 2002:a17:902:f68b:b0:1a2:7d:8a74 with SMTP id l11-20020a170902f68b00b001a2007d8a74mr5447591plg.66.1680921810221; Fri, 07 Apr 2023 19:43:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 15/42] tcg: Split out tcg_out_extrl_i64_i32 Date: Fri, 7 Apr 2023 19:42:47 -0700 Message-Id: <20230408024314.3357414-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922347766100005 Content-Type: text/plain; charset="utf-8" We will need a backend interface for type truncation. For those backends that did not enable TCG_TARGET_HAS_extrl_i64_i32, use tcg_out_mov. Use it in tcg_reg_alloc_op in the meantime. Signed-off-by: Richard Henderson --- tcg/tcg.c | 4 ++++ tcg/aarch64/tcg-target.c.inc | 6 ++++++ tcg/arm/tcg-target.c.inc | 5 +++++ tcg/i386/tcg-target.c.inc | 9 ++++++--- tcg/loongarch64/tcg-target.c.inc | 10 ++++++---- tcg/mips/tcg-target.c.inc | 9 ++++++--- tcg/ppc/tcg-target.c.inc | 7 +++++++ tcg/riscv/tcg-target.c.inc | 10 ++++++---- tcg/s390x/tcg-target.c.inc | 6 ++++++ tcg/sparc64/tcg-target.c.inc | 9 ++++++--- tcg/tci/tcg-target.c.inc | 7 +++++++ 11 files changed, 65 insertions(+), 17 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 17bd6d4581..0188152c37 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -113,6 +113,7 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, T= CGReg arg); static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg); +static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g); static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); static void tcg_out_goto_tb(TCGContext *s, int which); @@ -4537,6 +4538,9 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) case INDEX_op_extu_i32_i64: tcg_out_extu_i32_i64(s, new_args[0], new_args[1]); break; + case INDEX_op_extrl_i64_i32: + tcg_out_extrl_i64_i32(s, new_args[0], new_args[1]); + break; default: if (def->flags & TCG_OPF_VECTOR) { tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op), diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index ca8b25865b..bd1fab193e 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1467,6 +1467,11 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGR= eg rd, TCGReg rn) tcg_out_ext32u(s, rd, rn); } =20 +static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) +{ + tcg_out_mov(s, TCG_TYPE_I32, rd, rn); +} + static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd, TCGReg rn, int64_t aimm) { @@ -2337,6 +2342,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: + case INDEX_op_extrl_i64_i32: default: g_assert_not_reached(); } diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 2135616e12..1820655ee3 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1013,6 +1013,11 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGR= eg rd, TCGReg rn) g_assert_not_reached(); } =20 +static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) +{ + g_assert_not_reached(); +} + static void tcg_out_bswap16(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn, int flags) { diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 71a2bff234..45b2054856 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1311,6 +1311,11 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGR= eg dest, TCGReg src) } } =20 +static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg dest, TCGReg src) +{ + tcg_out_ext32u(s, dest, src); +} + static inline void tcg_out_bswap64(TCGContext *s, int reg) { tcg_out_opc(s, OPC_BSWAP + P_REXW + LOWREGMASK(reg), 0, reg, 0); @@ -2765,9 +2770,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_bswap64_i64: tcg_out_bswap64(s, a0); break; - case INDEX_op_extrl_i64_i32: - tcg_out_ext32u(s, a0, a1); - break; case INDEX_op_extrh_i64_i32: tcg_out_shifti(s, SHIFT_SHR + P_REXW, a0, 32); break; @@ -2848,6 +2850,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: + case INDEX_op_extrl_i64_i32: default: g_assert_not_reached(); } diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index d83bd9de49..b0e076c462 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -468,6 +468,11 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg= ret, TCGReg arg) tcg_out_ext32u(s, ret, arg); } =20 +static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_ext32s(s, ret, arg); +} + static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc, TCGReg a0, TCGReg a1, TCGReg a2, bool c2, bool is_32bit) @@ -1258,10 +1263,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); break; =20 - case INDEX_op_extrl_i64_i32: - tcg_out_ext32s(s, a0, a1); - break; - case INDEX_op_extrh_i64_i32: tcg_out_opc_srai_d(s, a0, a1, 32); break; @@ -1624,6 +1625,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: + case INDEX_op_extrl_i64_i32: default: g_assert_not_reached(); } diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 4789b0a40c..f103cdb4e6 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -592,6 +592,11 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg= rd, TCGReg rs) tcg_out_ext32u(s, rd, rs); } =20 +static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_ext32s(s, rd, rs); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -2306,9 +2311,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_extrh_i64_i32: tcg_out_dsra(s, a0, a1, 32); break; - case INDEX_op_extrl_i64_i32: - tcg_out_ext32s(s, a0, a1); - break; =20 case INDEX_op_sar_i32: i1 =3D OPC_SRAV, i2 =3D OPC_SRA; @@ -2457,6 +2459,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: + case INDEX_op_extrl_i64_i32: default: g_assert_not_reached(); } diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 01924fdf51..6fd309968e 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -816,6 +816,12 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg= dst, TCGReg src) tcg_out_ext32u(s, dst, src); } =20 +static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) +{ + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); + tcg_out_mov(s, TCG_TYPE_I32, rd, rn); +} + static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, i= nt c) { tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c); @@ -3137,6 +3143,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: + case INDEX_op_extrl_i64_i32: default: g_assert_not_reached(); } diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index a6d352976c..6af5c25f02 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -614,6 +614,11 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg= ret, TCGReg arg) tcg_out_ext32u(s, ret, arg); } =20 +static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_ext32s(s, ret, arg); +} + static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, TCGReg addr, intptr_t offset) { @@ -1609,10 +1614,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_st(s, args, true); break; =20 - case INDEX_op_extrl_i64_i32: - tcg_out_ext32s(s, a0, a1); - break; - case INDEX_op_extrh_i64_i32: tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32); break; @@ -1648,6 +1649,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: + case INDEX_op_extrl_i64_i32: default: g_assert_not_reached(); } diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index e17d000991..360229cdd3 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1132,6 +1132,11 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGR= eg dest, TCGReg src) tcg_out_ext32u(s, dest, src); } =20 +static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg dest, TCGReg src) +{ + tcg_out_mov(s, TCG_TYPE_I32, dest, src); +} + static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t= val) { int msb, lsb; @@ -2632,6 +2637,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcod= e opc, case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: + case INDEX_op_extrl_i64_i32: default: g_assert_not_reached(); } diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index c57a8c8304..18ddd6bb9f 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -537,6 +537,11 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg= rd, TCGReg rs) tcg_out_ext32u(s, rd, rs); } =20 +static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_out_mov(s, TCG_TYPE_I32, rd, rs); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -1687,9 +1692,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_divu_i64: c =3D ARITH_UDIVX; goto gen_arith; - case INDEX_op_extrl_i64_i32: - tcg_out_mov(s, TCG_TYPE_I32, a0, a1); - break; case INDEX_op_extrh_i64_i32: tcg_out_arithi(s, a0, a1, 32, SHIFT_SRLX); break; @@ -1744,6 +1746,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: + case INDEX_op_extrl_i64_i32: default: g_assert_not_reached(); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 48c9dbd0b4..68531e35ec 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -639,6 +639,12 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg= rd, TCGReg rs) tcg_out_ext32u(s, rd, rs); } =20 +static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) +{ + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); + tcg_out_mov(s, TCG_TYPE_I32, rd, rs); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -881,6 +887,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext32u_i64: case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: + case INDEX_op_extrl_i64_i32: default: g_assert_not_reached(); } --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922332; cv=none; d=zohomail.com; s=zohoarc; b=bb2Fx/kvHEe1mDQnIM8PFs8gLJ3pgYBetUgius+Tr9tD+B5XXR04m1lZ850ti6Cuikt7Ds67tX7y+dBUM9ucv/1Owmm0b1WQPNeDv2+OhmyWsUg4iKlFQZxCAmDBhpwr3Mtidb32SdF3Whm7YdEbcG3E+8hK7vGO0H9BkWOQtgI= ARC-Message-Signature: i=1; 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Signed-off-by: Richard Henderson --- tcg/tcg.c | 59 ++++++++++++++++++++++++++++++++ tcg/aarch64/tcg-target.c.inc | 8 ++--- tcg/arm/tcg-target.c.inc | 16 +++------ tcg/i386/tcg-target.c.inc | 30 +++------------- tcg/loongarch64/tcg-target.c.inc | 53 +++++----------------------- tcg/ppc/tcg-target.c.inc | 38 ++++++-------------- tcg/riscv/tcg-target.c.inc | 13 ++----- tcg/s390x/tcg-target.c.inc | 19 ++-------- tcg/sparc64/tcg-target.c.inc | 32 ++++------------- 9 files changed, 100 insertions(+), 168 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 0188152c37..6fe7dd6564 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -352,6 +352,65 @@ void tcg_raise_tb_overflow(TCGContext *s) siglongjmp(s->jmp_trans, -2); } =20 +/** + * tcg_out_movext -- move and extend + * @s: tcg context + * @dst_type: integral type for destination + * @dst: destination register + * @src_type: integral type for source + * @src_ext: extension to apply to source + * @src: source register + * + * Move or extend @src into @dst, depending on @src_ext and the types. + */ +static void __attribute__((unused)) +tcg_out_movext(TCGContext *s, TCGType dst_type, TCGReg dst, + TCGType src_type, MemOp src_ext, TCGReg src) +{ + switch (src_ext) { + case MO_UB: + tcg_out_ext8u(s, dst, src); + break; + case MO_SB: + tcg_out_ext8s(s, dst_type, dst, src); + break; + case MO_UW: + tcg_out_ext16u(s, dst, src); + break; + case MO_SW: + tcg_out_ext16s(s, dst_type, dst, src); + break; + case MO_UL: + case MO_SL: + if (dst_type =3D=3D TCG_TYPE_I32) { + if (src_type =3D=3D TCG_TYPE_I32) { + tcg_out_mov(s, TCG_TYPE_I32, dst, src); + } else { + tcg_out_extrl_i64_i32(s, dst, src); + } + } else if (src_type =3D=3D TCG_TYPE_I32) { + if (src_ext & MO_SIGN) { + tcg_out_exts_i32_i64(s, dst, src); + } else { + tcg_out_extu_i32_i64(s, dst, src); + } + } else { + if (src_ext & MO_SIGN) { + tcg_out_ext32s(s, dst, src); + } else { + tcg_out_ext32u(s, dst, src); + } + } + break; + case MO_UQ: + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 64); + tcg_out_mov(s, TCG_TYPE_I64, dst, src); + break; + default: + g_assert_not_reached(); + } +} + #define C_PFX1(P, A) P##A #define C_PFX2(P, A, B) P##A##_##B #define C_PFX3(P, A, B, C) P##A##_##B##_##C diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index bd1fab193e..29bc97ed1c 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1620,7 +1620,6 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) { MemOpIdx oi =3D lb->oi; MemOp opc =3D get_memop(oi); - MemOp size =3D opc & MO_SIZE; =20 if (!reloc_pc19(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; @@ -1631,12 +1630,9 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, oi); tcg_out_adr(s, TCG_REG_X3, lb->raddr); tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); - if (opc & MO_SIGN) { - tcg_out_sxt(s, lb->type, size, lb->datalo_reg, TCG_REG_X0); - } else { - tcg_out_mov(s, size =3D=3D MO_64, lb->datalo_reg, TCG_REG_X0); - } =20 + tcg_out_movext(s, lb->type, lb->datalo_reg, + TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_X0); tcg_out_goto(s, lb->raddr); return true; } diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 1820655ee3..f865294861 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1567,17 +1567,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) =20 datalo =3D lb->datalo_reg; datahi =3D lb->datahi_reg; - switch (opc & MO_SSIZE) { - case MO_SB: - tcg_out_ext8s(s, TCG_TYPE_I32, datalo, TCG_REG_R0); - break; - case MO_SW: - tcg_out_ext16s(s, TCG_TYPE_I32, datalo, TCG_REG_R0); - break; - default: - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); - break; - case MO_UQ: + if ((opc & MO_SIZE) =3D=3D MO_64) { if (datalo !=3D TCG_REG_R1) { tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); @@ -1589,7 +1579,9 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_TMP); } - break; + } else { + tcg_out_movext(s, TCG_TYPE_I32, lb->datalo_reg, + TCG_TYPE_I32, opc & MO_SSIZE, TCG_REG_R0); } =20 tcg_out_goto(s, COND_AL, lb->raddr); diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 45b2054856..2d7c173a03 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1946,28 +1946,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) tcg_out_branch(s, 1, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 data_reg =3D l->datalo_reg; - switch (opc & MO_SSIZE) { - case MO_SB: - tcg_out_ext8s(s, l->type, data_reg, TCG_REG_EAX); - break; - case MO_SW: - tcg_out_ext16s(s, l->type, data_reg, TCG_REG_EAX); - break; -#if TCG_TARGET_REG_BITS =3D=3D 64 - case MO_SL: - tcg_out_ext32s(s, data_reg, TCG_REG_EAX); - break; -#endif - case MO_UB: - case MO_UW: - /* Note that the helpers have zero-extended to tcg_target_long. */ - case MO_UL: - tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); - break; - case MO_UQ: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX); - } else if (data_reg =3D=3D TCG_REG_EDX) { + if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { + if (data_reg =3D=3D TCG_REG_EDX) { /* xchg %edx, %eax */ tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX, 0, 0, 0); tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EAX); @@ -1975,9 +1955,9 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EDX); } - break; - default: - g_assert_not_reached(); + } else { + tcg_out_movext(s, l->type, data_reg, + TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_EAX); } =20 /* Jump to the code corresponding to next IR of qemu_st */ diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index b0e076c462..fc98b9b31b 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -893,7 +893,6 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TC= GLabelQemuLdst *l) MemOpIdx oi =3D l->oi; MemOp opc =3D get_memop(oi); MemOp size =3D opc & MO_SIZE; - TCGType type =3D l->type; =20 /* resolve label address */ if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -908,28 +907,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, T= CGLabelQemuLdst *l) =20 tcg_out_call_int(s, qemu_ld_helpers[size], false); =20 - switch (opc & MO_SSIZE) { - case MO_SB: - tcg_out_ext8s(s, type, l->datalo_reg, TCG_REG_A0); - break; - case MO_SW: - tcg_out_ext16s(s, type, l->datalo_reg, TCG_REG_A0); - break; - case MO_SL: - tcg_out_ext32s(s, l->datalo_reg, TCG_REG_A0); - break; - case MO_UL: - if (type =3D=3D TCG_TYPE_I32) { - /* MO_UL loads of i32 should be sign-extended too */ - tcg_out_ext32s(s, l->datalo_reg, TCG_REG_A0); - break; - } - /* fallthrough */ - default: - tcg_out_mov(s, type, l->datalo_reg, TCG_REG_A0); - break; - } - + tcg_out_movext(s, l->type, l->datalo_reg, + TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_A0); return tcg_out_goto(s, l->raddr); } =20 @@ -947,23 +926,8 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, T= CGLabelQemuLdst *l) /* call store helper */ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A1, l->addrlo_reg); - switch (size) { - case MO_8: - tcg_out_ext8u(s, TCG_REG_A2, l->datalo_reg); - break; - case MO_16: - tcg_out_ext16u(s, TCG_REG_A2, l->datalo_reg); - break; - case MO_32: - tcg_out_ext32u(s, TCG_REG_A2, l->datalo_reg); - break; - case MO_64: - tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_A2, l->datalo_reg); - break; - default: - g_assert_not_reached(); - break; - } + tcg_out_movext(s, size =3D=3D MO_64 ? TCG_TYPE_I32 : TCG_TYPE_I32, TCG= _REG_A2, + l->type, size, l->datalo_reg); tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, oi); tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A4, (tcg_target_long)l->raddr); =20 @@ -1140,7 +1104,7 @@ static void tcg_out_qemu_st_indexed(TCGContext *s, TC= GReg data, } } =20 -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args) +static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGType typ= e) { TCGReg addr_regl; TCGReg data_regl; @@ -1162,8 +1126,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args) tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 0); base =3D tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); tcg_out_qemu_st_indexed(s, data_regl, base, TCG_REG_TMP2, opc); - add_qemu_ldst_label(s, 0, oi, - 0, /* type param is unused for stores */ + add_qemu_ldst_label(s, 0, oi, type, data_regl, addr_regl, s->code_ptr, label_ptr); #else @@ -1602,10 +1565,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_ld(s, args, TCG_TYPE_I64); break; case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args); + tcg_out_qemu_st(s, args, TCG_TYPE_I32); break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args); + tcg_out_qemu_st(s, args, TCG_TYPE_I64); break; =20 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 6fd309968e..612ad15bda 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1970,10 +1970,6 @@ static const uint32_t qemu_stx_opc[(MO_SIZE + MO_BSW= AP) + 1] =3D { [MO_BSWAP | MO_UQ] =3D STDBRX, }; =20 -static const uint32_t qemu_exts_opc[4] =3D { - EXTSB, EXTSH, EXTSW, 0 -}; - #if defined (CONFIG_SOFTMMU) /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) @@ -2167,11 +2163,9 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4); tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3); - } else if (opc & MO_SIGN) { - uint32_t insn =3D qemu_exts_opc[opc & MO_SIZE]; - tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3)); } else { - tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3); + tcg_out_movext(s, lb->type, lo, + TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_R3); } =20 tcg_out_b(s, 0, lb->raddr); @@ -2205,25 +2199,13 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) =20 lo =3D lb->datalo_reg; hi =3D lb->datahi_reg; - if (TCG_TARGET_REG_BITS =3D=3D 32) { - switch (s_bits) { - case MO_64: - arg |=3D (TCG_TARGET_CALL_ARG_I64 =3D=3D TCG_CALL_ARG_EVEN); - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - /* FALLTHRU */ - case MO_32: - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - break; - default: - tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31); - break; - } + if (TCG_TARGET_REG_BITS =3D=3D 32 && s_bits =3D=3D MO_64) { + arg |=3D (TCG_TARGET_CALL_ARG_I64 =3D=3D TCG_CALL_ARG_EVEN); + tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); + tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); } else { - if (s_bits =3D=3D MO_64) { - tcg_out_mov(s, TCG_TYPE_I64, arg++, lo); - } else { - tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits)); - } + tcg_out_movext(s, s_bits =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I3= 2, + arg++, lb->type, s_bits, lo); } =20 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); @@ -2370,8 +2352,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) } else { insn =3D qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)]; tcg_out32(s, insn | TAB(datalo, rbase, addrlo)); - insn =3D qemu_exts_opc[s_bits]; - tcg_out32(s, insn | RA(datalo) | RS(datalo)); + tcg_out_movext(s, TCG_TYPE_REG, datalo, + TCG_TYPE_REG, opc & MO_SSIZE, datalo); } } =20 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 6af5c25f02..081782d8c6 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1081,17 +1081,8 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) /* call store helper */ tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); - tcg_out_mov(s, TCG_TYPE_PTR, a2, l->datalo_reg); - switch (s_bits) { - case MO_8: - tcg_out_ext8u(s, a2, a2); - break; - case MO_16: - tcg_out_ext16u(s, a2, a2); - break; - default: - break; - } + tcg_out_movext(s, s_bits =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, a= 2, + l->type, s_bits, l->datalo_reg); tcg_out_movi(s, TCG_TYPE_PTR, a3, oi); tcg_out_movi(s, TCG_TYPE_PTR, a4, (tcg_target_long)l->raddr); =20 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 360229cdd3..0578fce4d7 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1809,6 +1809,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) TCGReg data_reg =3D lb->datalo_reg; MemOpIdx oi =3D lb->oi; MemOp opc =3D get_memop(oi); + MemOp size =3D opc & MO_SIZE; =20 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { @@ -1819,22 +1820,8 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) if (TARGET_LONG_BITS =3D=3D 64) { tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg); } - switch (opc & MO_SIZE) { - case MO_UB: - tcg_out_ext8u(s, TCG_REG_R4, data_reg); - break; - case MO_UW: - tcg_out_ext16u(s, TCG_REG_R4, data_reg); - break; - case MO_UL: - tcg_out_ext32u(s, TCG_REG_R4, data_reg); - break; - case MO_UQ: - tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, data_reg); - break; - default: - g_assert_not_reached(); - } + tcg_out_movext(s, size =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, + TCG_REG_R4, lb->type, size, data_reg); tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, oi); tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R6, (uintptr_t)lb->raddr); tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 18ddd6bb9f..99ba0fdc2b 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -917,26 +917,6 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0) static const tcg_insn_unit *qemu_ld_trampoline[(MO_SSIZE | MO_BSWAP) + 1]; static const tcg_insn_unit *qemu_st_trampoline[(MO_SIZE | MO_BSWAP) + 1]; =20 -static void emit_extend(TCGContext *s, TCGReg r, int op) -{ - /* Emit zero extend of 8, 16 or 32 bit data as - * required by the MO_* value op; do nothing for 64 bit. - */ - switch (op & MO_SIZE) { - case MO_8: - tcg_out_ext8u(s, r, r); - break; - case MO_16: - tcg_out_ext16u(s, r, r); - break; - case MO_32: - tcg_out_ext32u(s, r, r); - break; - case MO_64: - break; - } -} - static void build_trampolines(TCGContext *s) { static void * const qemu_ld_helpers[] =3D { @@ -993,8 +973,6 @@ static void build_trampolines(TCGContext *s) } qemu_st_trampoline[i] =3D tcg_splitwx_to_rx(s->code_ptr); =20 - emit_extend(s, TCG_REG_O2, i); - /* Set the retaddr operand. */ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O4, TCG_REG_O7); =20 @@ -1341,7 +1319,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a, TCGReg addr, } =20 static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, - MemOpIdx oi) + MemOpIdx oi, bool is64) { MemOp memop =3D get_memop(oi); tcg_insn_unit *label_ptr; @@ -1367,7 +1345,9 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= a, TCGReg addr, /* TLB Miss. */ =20 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_O1, addrz); - tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_O2, data); + tcg_out_movext(s, (memop & MO_SIZE) =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_= TYPE_I32, + TCG_REG_O2, is64 ? TCG_TYPE_I64 : TCG_TYPE_I32, + memop & MO_SIZE, data); =20 func =3D qemu_st_trampoline[memop & (MO_BSWAP | MO_SIZE)]; tcg_debug_assert(func !=3D NULL); @@ -1658,8 +1638,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_ld(s, a0, a1, a2, true); break; case INDEX_op_qemu_st_i32: + tcg_out_qemu_st(s, a0, a1, a2, false); + break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, a0, a1, a2); + tcg_out_qemu_st(s, a0, a1, a2, true); break; =20 case INDEX_op_ld32s_i64: --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922306; cv=none; d=zohomail.com; s=zohoarc; b=h1sDKnIY9kKcyxWX8rjlU66dk8aSewMUWLIarXNty5G/jjS5Rrf0fMaF/VyY8RLW/sue6fDLC5VD0W/EgtdNfbFEs4BTCW0os26BYonO5aaBYTQSrIELl7gy5E3TLOPWXtB8wt8SSTdWF8AqvCaAbmwds822Jg5lIwTyddrB+qM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680922306; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LGjnlvYQSu/kSuYcDZLUvskA3987iSuGFI1KchA2Z08=; b=LbvB/y7Gvtlk9GftydF2j8FmJpthKlr++W8T/bvM2CNUyZqfmiK00jDX19HpQqfygwtP/G0ft3WNFl903tUy4jvmdKRijwnjyq5KBbXBsOnnMw/Ng2Q+yBtPPMw1ysLu5bw74toEddrf1lPTwND96dV1X1tE9wI6E44U2nzZWPk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680922306955855.3506147019389; Fri, 7 Apr 2023 19:51:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyYW-0007cL-Px; Fri, 07 Apr 2023 22:43:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyYU-0007YR-N3 for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:43:54 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyY9-0005gn-B9 for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:43:54 -0400 Received: by mail-pl1-x629.google.com with SMTP id ke16so306220plb.6 for ; Fri, 07 Apr 2023 19:43:32 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921812; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LGjnlvYQSu/kSuYcDZLUvskA3987iSuGFI1KchA2Z08=; b=Z8GtQY3SO574Z9GG/nhpRNIqhg8qs0YkjhWRnjCG9s/W6IctPyDr/W37uouC5fPkue 8LQUv7cQkSg7GLfZm47+X3QAlRoD2v/OJqAH+90c8t2CB9KWBROESSM1ffOFtCkUH2Pl xk77lh8Iy77TpeExT6r7jyUmVDDRUJMTad7MaA9tkDu4e9wzB6sh0vp5pwdXu84w9cIz CbZiLOjyW3HMNIVbMLp/O4dDLnsGS5MmcJrj7UOyNWq+bD9z+c5JqU0lXI/vbk55FOl5 zRWBUehMwVBsNOX+gEBILrlcsji7hJEkwpS6SUKbtvuBajTvA0NdEyl6YPqtng1HklPh 6M0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921812; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LGjnlvYQSu/kSuYcDZLUvskA3987iSuGFI1KchA2Z08=; b=0rqSpAg4jwgXCf+XuYQZAQYmjOj2mC2A8bWeDTScWvAL4S4nuam5/EE/BgVWtC08WF oQg7U2gyICQMSb6juCZixP6AXpayuy04VgRd6I5q+vEKiAo6LajT693Sd33vH/LFK1gW qut61shmCftScGKgDpwZVAoxWbMjrfE5Y7urfns2JlXcPEisR/p7ZzVN7sBFGEsuSGPQ Bo8zjwl0ardvI7vqK8vNYV9R2Y6tv3tGg0MKN1QRGyyDTffiZqtUW2SCQRWqZna7ilqQ Um6xbd6Cq0y8JNX8zqQozyCUCC/m2yq7bIYCL9z8VEwYMZXR+MxSq5Tza19Hbz5RHspP GMoQ== X-Gm-Message-State: AAQBX9d+3lAZjT3+SWYluoHfjabD/GeSX3CDpNRKFgqJwlHU2T+MbYpx sQm7LEFuCT1I2iZS10OLipQdf3yCIAYDq7i7pcQ= X-Google-Smtp-Source: AKy350a7iCus5eudFdMASYcHzWNnWNw/aVLcESLg+LDMuFcG2ge4n2ec3/mRiORhkAQTpu/91ik52Q== X-Received: by 2002:a17:903:110f:b0:19e:8088:b852 with SMTP id n15-20020a170903110f00b0019e8088b852mr5432193plh.10.1680921811941; Fri, 07 Apr 2023 19:43:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 17/42] tcg: Introduce tcg_out_xchg Date: Fri, 7 Apr 2023 19:42:49 -0700 Message-Id: <20230408024314.3357414-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922309029100003 Content-Type: text/plain; charset="utf-8" We will want a backend interface for register swapping. This is only properly defined for x86; all others get a stub version that always indicates failure. Signed-off-by: Richard Henderson --- tcg/tcg.c | 2 ++ tcg/aarch64/tcg-target.c.inc | 5 +++++ tcg/arm/tcg-target.c.inc | 5 +++++ tcg/i386/tcg-target.c.inc | 8 ++++++++ tcg/loongarch64/tcg-target.c.inc | 5 +++++ tcg/mips/tcg-target.c.inc | 5 +++++ tcg/ppc/tcg-target.c.inc | 5 +++++ tcg/riscv/tcg-target.c.inc | 5 +++++ tcg/s390x/tcg-target.c.inc | 5 +++++ tcg/sparc64/tcg-target.c.inc | 5 +++++ tcg/tci/tcg-target.c.inc | 5 +++++ 11 files changed, 55 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index 6fe7dd6564..d82d99e1b0 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -115,6 +115,8 @@ static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg = ret, TCGReg arg); static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g); +static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) + __attribute__((unused)); static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); static void tcg_out_goto_tb(TCGContext *s, int which); static void tcg_out_op(TCGContext *s, TCGOpcode opc, diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 29bc97ed1c..4ec3cf3172 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1106,6 +1106,11 @@ static void tcg_out_movi(TCGContext *s, TCGType type= , TCGReg rd, tcg_out_insn(s, 3305, LDR, 0, rd); } =20 +static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) +{ + return false; +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index f865294861..4a5d57a41c 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2607,6 +2607,11 @@ static void tcg_out_movi(TCGContext *s, TCGType type, tcg_out_movi32(s, COND_AL, ret, arg); } =20 +static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) +{ + return false; +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 2d7c173a03..7d6bf30747 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -460,6 +460,7 @@ static bool tcg_target_const_match(int64_t val, TCGType= type, int ct) #define OPC_VPTERNLOGQ (0x25 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) #define OPC_VZEROUPPER (0x77 | P_EXT) #define OPC_XCHG_ax_r32 (0x90) +#define OPC_XCHG_EvGv (0x87) =20 #define OPC_GRP3_Eb (0xf6) #define OPC_GRP3_Ev (0xf7) @@ -1078,6 +1079,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } =20 +static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) +{ + int rexw =3D type =3D=3D TCG_TYPE_I32 ? 0 : P_REXW; + tcg_out_modrm(s, OPC_XCHG_EvGv + rexw, r1, r2); + return true; +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index fc98b9b31b..0940788c6f 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -419,6 +419,11 @@ static void tcg_out_addi(TCGContext *s, TCGType type, = TCGReg rd, } } =20 +static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) +{ + return false; +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index f103cdb4e6..a83ebe8729 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -597,6 +597,11 @@ static void tcg_out_extrl_i64_i32(TCGContext *s, TCGRe= g rd, TCGReg rs) tcg_out_ext32s(s, rd, rs); } =20 +static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) +{ + return false; +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 612ad15bda..d3e547998f 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1153,6 +1153,11 @@ static void tcg_out_movi(TCGContext *s, TCGType type= , TCGReg ret, } } =20 +static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) +{ + return false; +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 081782d8c6..266fe1433d 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -561,6 +561,11 @@ static void tcg_out_movi(TCGContext *s, TCGType type, = TCGReg rd, tcg_out_opc_imm(s, OPC_LD, rd, rd, 0); } =20 +static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) +{ + return false; +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 0578fce4d7..b399798664 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1076,6 +1076,11 @@ static inline bool tcg_out_sti(TCGContext *s, TCGTyp= e type, TCGArg val, return false; } =20 +static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) +{ + return false; +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 99ba0fdc2b..086981f097 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -542,6 +542,11 @@ static void tcg_out_extrl_i64_i32(TCGContext *s, TCGRe= g rd, TCGReg rs) tcg_out_mov(s, TCG_TYPE_I32, rd, rs); } =20 +static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) +{ + return false; +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 68531e35ec..4cf03a579c 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -645,6 +645,11 @@ static void tcg_out_extrl_i64_i32(TCGContext *s, TCGRe= g rd, TCGReg rs) tcg_out_mov(s, TCG_TYPE_I32, rd, rs); } =20 +static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) +{ + return false; +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922239; cv=none; d=zohomail.com; s=zohoarc; b=jkQDgKluuc7+EX2G8w5c77OGrNCYDONyWK8Ef3ky3zEJbO1GtVdGChlL4SW/RYM0WIMCyvCBgX6gwNzWFUDjxVTZHRUbkNGykXlPn5Jo70ilwcmG1LCTg3KpAda3Y+KerpjqzA6Sk5TVcoqHamu7YgPkUPFat4sa/6peMTS5G6M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680922239; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hlH9Syu5nBco3hVib/PJ96sBJ5uHmafkdc2luPh0/Cc=; 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([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921812; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hlH9Syu5nBco3hVib/PJ96sBJ5uHmafkdc2luPh0/Cc=; b=oyMP87kLU53OJi80NV9nSKfQvn3DkDtLju5WKWBQJrf8WGcM9PrpEArmw/MaQVOZJN t5VbhOkWanFrOifO8SmWlo81VxscNmxh/COmCd9UOFv6ogaJZAhiCD/CjnBjyvrc0AMc Yq6Rm0G+rnEz/t5uf8ldEFgLkHi9qxljKufGcKwSmx7vqc+t3lteltcv8dLVt6bMQR3S +nc+3VpmcyntP6kOdhHH/cI8drPFylTs7pJISWqxrUsDboVPNq7ljEB/Q/xGe61c9qfl u2quGFvURkYuHMZbUZizcj+fwS2l8saewHODbYoM/3++XHjETh6yJL+POJt4Vk0vrhqS aygg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921812; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hlH9Syu5nBco3hVib/PJ96sBJ5uHmafkdc2luPh0/Cc=; b=yxGKFQ7xeUspH2tiOF0H7qKarUs3xF4/QHmS4VbRU08ivQUDgjM7maACq3yMzsx0oO ZQIq/ex4OxCMd7+Z4EEWQfGcKeDAuVP5jytOJwMHAk399To5kiNinLxfXrOKvT9sdYtX 0Tz4aMsi51FPLn11yJEUua5RVUU+9B4wSRblbvlHhr6j2uguy9WWQemupj4qBWomivPh m6R3NtmFUvx1sX14J6mjn9tQJNQzA39xBFvDWVXUFVAtD0mxy0425yPiEz4ALT3dYnO6 3fOkwMUFFGRBbiEsLSEZWP/dIN1S0S+DXVpsxQa1j/jnHTD0VDKpYiLjNcHV3DbTXtpL QRmw== X-Gm-Message-State: AAQBX9fiec1Rdv07lUQ9K5Vze0sSLNQ7joS5wvU9wXENSg4H+rvhmy7i +ZeCeCLx7EVTPivgX/ASNjRQA8R6NGYLp4FVrdc= X-Google-Smtp-Source: AKy350bA430SzBtT7wrFMelu4U2c7uri8N1uo0MLGz2dkSmghCFxWWnF8o5fENEZ6rn7llbvCKxwzA== X-Received: by 2002:a17:903:2310:b0:19e:ecaf:c4b4 with SMTP id d16-20020a170903231000b0019eecafc4b4mr6382021plh.4.1680921812651; Fri, 07 Apr 2023 19:43:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 18/42] tcg: Introduce tcg_out_movext2 Date: Fri, 7 Apr 2023 19:42:50 -0700 Message-Id: <20230408024314.3357414-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922240618100001 Content-Type: text/plain; charset="utf-8" This is common code in most qemu_{ld,st} slow paths, moving two registers when there may be overlap between sources and destinations. At present, this is only used by 32-bit hosts for 64-bit data, but will shortly be used for more than that. Signed-off-by: Richard Henderson --- tcg/tcg.c | 50 +++++++++++++++++++++++++++++++++++---- tcg/arm/tcg-target.c.inc | 34 +++++++------------------- tcg/i386/tcg-target.c.inc | 16 ++++--------- 3 files changed, 59 insertions(+), 41 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index d82d99e1b0..1c11f15bce 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -115,8 +115,7 @@ static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg = ret, TCGReg arg); static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg); static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_lon= g); -static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) - __attribute__((unused)); +static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2= ); static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); static void tcg_out_goto_tb(TCGContext *s, int which); static void tcg_out_op(TCGContext *s, TCGOpcode opc, @@ -365,9 +364,8 @@ void tcg_raise_tb_overflow(TCGContext *s) * * Move or extend @src into @dst, depending on @src_ext and the types. */ -static void __attribute__((unused)) -tcg_out_movext(TCGContext *s, TCGType dst_type, TCGReg dst, - TCGType src_type, MemOp src_ext, TCGReg src) +static void tcg_out_movext(TCGContext *s, TCGType dst_type, TCGReg dst, + TCGType src_type, MemOp src_ext, TCGReg src) { switch (src_ext) { case MO_UB: @@ -413,6 +411,48 @@ tcg_out_movext(TCGContext *s, TCGType dst_type, TCGReg= dst, } } =20 +/** + * tcg_out_movext2 -- move and extend two pair + * @s: tcg context + * @d1_type: integral type for destination + * @d1: destination register + * @s1_type: integral type for source + * @s1_ext: extension to apply to source + * @s1: source register + * @d2_type: integral type for destination + * @d2: destination register + * @s2_type: integral type for source + * @s2_ext: extension to apply to source + * @s2: source register + * @scratch: temporary register, or -1 for none + * + * As tcg_out_movext, for both s1->d1 and s2->d2, caring for overlap + * between the sources and destinations. + */ +static void __attribute__((unused)) +tcg_out_movext2(TCGContext *s, TCGType d1_type, TCGReg d1, TCGType s1_type, + MemOp s1_ext, TCGReg s1, TCGType d2_type, TCGReg d2, + TCGType s2_type, MemOp s2_ext, TCGReg s2, int scratch) +{ + if (d1 !=3D s2) { + tcg_out_movext(s, d1_type, d1, s1_type, s1_ext, s1); + tcg_out_movext(s, d2_type, d2, s2_type, s2_ext, s2); + return; + } + if (d2 =3D=3D s1) { + if (tcg_out_xchg(s, MAX(s1_type, s2_type), s1, s2)) { + /* The data is now in the correct registers, now extend. */ + s1 =3D d1, s2 =3D d2; + } else { + tcg_debug_assert(scratch >=3D 0); + tcg_out_mov(s, s1_type, scratch, s1); + s1 =3D scratch; + } + } + tcg_out_movext(s, d2_type, d2, s2_type, s2_ext, s2); + tcg_out_movext(s, d1_type, d1, s1_type, s1_ext, s1); +} + #define C_PFX1(P, A) P##A #define C_PFX2(P, A, B) P##A##_##B #define C_PFX3(P, A, B, C) P##A##_##B##_##C diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 4a5d57a41c..bad1e6d399 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1545,7 +1545,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, MemOpIdx oi, =20 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGReg argreg, datalo, datahi; + TCGReg argreg; MemOpIdx oi =3D lb->oi; MemOp opc =3D get_memop(oi); =20 @@ -1565,20 +1565,11 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) /* Use the canonical unsigned helpers and minimize icache usage. */ tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); =20 - datalo =3D lb->datalo_reg; - datahi =3D lb->datahi_reg; if ((opc & MO_SIZE) =3D=3D MO_64) { - if (datalo !=3D TCG_REG_R1) { - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); - tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); - } else if (datahi !=3D TCG_REG_R0) { - tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_R0); - } else { - tcg_out_mov_reg(s, COND_AL, TCG_REG_TMP, TCG_REG_R0); - tcg_out_mov_reg(s, COND_AL, datahi, TCG_REG_R1); - tcg_out_mov_reg(s, COND_AL, datalo, TCG_REG_TMP); - } + tcg_out_movext2(s, TCG_TYPE_I32, lb->datalo_reg, + TCG_TYPE_I32, MO_UL, TCG_REG_R0, + TCG_TYPE_I32, lb->datahi_reg, + TCG_TYPE_I32, MO_UL, TCG_REG_R1, TCG_REG_TMP); } else { tcg_out_movext(s, TCG_TYPE_I32, lb->datalo_reg, TCG_TYPE_I32, opc & MO_SSIZE, TCG_REG_R0); @@ -1663,17 +1654,10 @@ static bool tcg_out_fail_alignment(TCGContext *s, T= CGLabelQemuLdst *l) =20 if (TARGET_LONG_BITS =3D=3D 64) { /* 64-bit target address is aligned into R2:R3. */ - if (l->addrhi_reg !=3D TCG_REG_R2) { - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, l->addrlo_reg); - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, l->addrhi_reg); - } else if (l->addrlo_reg !=3D TCG_REG_R3) { - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, l->addrhi_reg); - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, l->addrlo_reg); - } else { - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R1, TCG_REG_R2); - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R2, TCG_REG_R3); - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R3, TCG_REG_R1); - } + tcg_out_movext2(s, TCG_TYPE_I32, TCG_REG_R2, + TCG_TYPE_I32, MO_UL, l->addrlo_reg, + TCG_TYPE_I32, TCG_REG_R3, + TCG_TYPE_I32, MO_UL, l->addrhi_reg, TCG_REG_TMP); } else { tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R1, l->addrlo_reg); } diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 7d6bf30747..54465c7f46 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1916,7 +1916,6 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) { MemOpIdx oi =3D l->oi; MemOp opc =3D get_memop(oi); - TCGReg data_reg; tcg_insn_unit **label_ptr =3D &l->label_ptr[0]; =20 /* resolve label address */ @@ -1953,18 +1952,13 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) =20 tcg_out_branch(s, 1, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 - data_reg =3D l->datalo_reg; if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { - if (data_reg =3D=3D TCG_REG_EDX) { - /* xchg %edx, %eax */ - tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX, 0, 0, 0); - tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EAX); - } else { - tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); - tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_EDX); - } + tcg_out_movext2(s, TCG_TYPE_I32, l->datalo_reg, + TCG_TYPE_I32, MO_UL, TCG_REG_EAX, + TCG_TYPE_I32, l->datahi_reg, + TCG_TYPE_I32, MO_UL, TCG_REG_EDX, -1); } else { - tcg_out_movext(s, l->type, data_reg, + tcg_out_movext(s, l->type, l->datalo_reg, TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_EAX); } =20 --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922222; cv=none; d=zohomail.com; s=zohoarc; b=HSE/N3NW5nArcR6cIW9LreiSRLdcQ88mkKIGy1v9C7zdwDhsK6S7sJOw2l7KqtCKOLEeVfihIwk2zbAE4JaFql4XU0I1SoW9X/I3LsxjFk0JLDzuftkXf92k3HdkU4MJC/j3z/HhOaoi+S2/a9S9+seTG8B6RCybiHdgc7e/6F8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680922222; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fIirSFwi2yILi+El/t2TPjJhZKpm7okvdpXO8dD7jMw=; b=HxGhSc6Rng3XfVGkrp+5eJZWHTCRkigM/M7Cjvpl5Sx4fipEmF761UAyMDoDM+KEcYMw+WCgJeNaxZCxr4eYBWYSdGCQPMKXQV7Bv5g3CzWxF0qf9vqziB6uDuwaKF1VkVIAVJriDWu9OxCAc/iegqR66vDGYHgrZABvdo9u1Q4= ARC-Authentication-Results: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922223152100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg-ldst.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/tcg/tcg-ldst.c.inc b/tcg/tcg-ldst.c.inc index 6c6848d034..403cbb0f06 100644 --- a/tcg/tcg-ldst.c.inc +++ b/tcg/tcg-ldst.c.inc @@ -72,6 +72,7 @@ static inline TCGLabelQemuLdst *new_ldst_label(TCGContext= *s) { TCGLabelQemuLdst *l =3D tcg_malloc(sizeof(*l)); =20 + memset(l, 0, sizeof(*l)); QSIMPLEQ_INSERT_TAIL(&s->ldst_labels, l, next); =20 return l; --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680922249144527.8499103463714; Fri, 7 Apr 2023 19:50:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyYb-0007k9-Qy; Fri, 07 Apr 2023 22:44:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyYZ-0007h3-NO for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:43:59 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyYB-0005iR-Gq for qemu-devel@nongnu.org; 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Clean things up by using type throughout. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/i386/tcg-target.c.inc | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 54465c7f46..ff4062ef54 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1886,8 +1886,8 @@ static inline void tcg_out_tlb_load(TCGContext *s, TC= GReg addrlo, TCGReg addrhi, * Record the context of a call to the out of line helper code for the slo= w path * for a load or store, so that we can later generate the correct helper c= ode */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64, - MemOpIdx oi, +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, + TCGType type, MemOpIdx oi, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addrhi, tcg_insn_unit *raddr, @@ -1897,7 +1897,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, bool is_64, =20 label->is_ld =3D is_ld; label->oi =3D oi; - label->type =3D is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32; + label->type =3D type; label->datalo_reg =3D datalo; label->datahi_reg =3D datahi; label->addrlo_reg =3D addrlo; @@ -2151,11 +2151,10 @@ static inline int setup_guest_base_seg(void) =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, TCGReg base, int index, intptr_t ofs, - int seg, bool is64, MemOp memop) + int seg, TCGType type, MemOp memop) { - TCGType type =3D is64 ? TCG_TYPE_I64 : TCG_TYPE_I32; bool use_movbe =3D false; - int rexw =3D is64 * P_REXW; + int rexw =3D (type =3D=3D TCG_TYPE_I32 ? 0 : P_REXW); int movop =3D OPC_MOVL_GvEv; =20 /* Do big-endian loads with movbe. */ @@ -2248,7 +2247,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, /* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and EAX. It will be useful once fixed registers globals are less common. */ -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) +static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGType d_t= ype) { TCGReg datalo, datahi, addrlo; TCGReg addrhi __attribute__((unused)); @@ -2262,7 +2261,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) #endif =20 datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is64 ? *args++ : 0); + datahi =3D TCG_TARGET_REG_BITS =3D=3D 64 || d_type =3D=3D TCG_TYPE_I32= ? 0 : *args++; addrlo =3D *args++; addrhi =3D (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); oi =3D *args++; @@ -2275,10 +2274,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is64) label_ptr, offsetof(CPUTLBEntry, addr_read)); =20 /* TLB Hit. */ - tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, is64, = opc); + tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, d_type= , opc); =20 /* Record the current context of a load into ldst label */ - add_qemu_ldst_label(s, true, is64, oi, datalo, datahi, addrlo, addrhi, + add_qemu_ldst_label(s, true, d_type, oi, datalo, datahi, addrlo, addrh= i, s->code_ptr, label_ptr); #else a_bits =3D get_alignment_bits(opc); @@ -2288,7 +2287,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) =20 tcg_out_qemu_ld_direct(s, datalo, datahi, addrlo, x86_guest_base_index, x86_guest_base_offset, x86_guest_base_seg, - is64, opc); + d_type, opc); #endif } =20 @@ -2344,7 +2343,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg datalo, TCGReg datahi, } } =20 -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) +static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGType d_t= ype) { TCGReg datalo, datahi, addrlo; TCGReg addrhi __attribute__((unused)); @@ -2358,7 +2357,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) #endif =20 datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is64 ? *args++ : 0); + datahi =3D TCG_TARGET_REG_BITS =3D=3D 64 || d_type =3D=3D TCG_TYPE_I32= ? 0 : *args++; addrlo =3D *args++; addrhi =3D (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0); oi =3D *args++; @@ -2374,7 +2373,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, -1, 0, 0, opc); =20 /* Record the current context of a store into ldst label */ - add_qemu_ldst_label(s, false, is64, oi, datalo, datahi, addrlo, addrhi, + add_qemu_ldst_label(s, false, d_type, oi, datalo, datahi, addrlo, addr= hi, s->code_ptr, label_ptr); #else a_bits =3D get_alignment_bits(opc); @@ -2672,17 +2671,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, 0); + tcg_out_qemu_ld(s, args, TCG_TYPE_I32); break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, 1); + tcg_out_qemu_ld(s, args, TCG_TYPE_I64); break; case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st8_i32: - tcg_out_qemu_st(s, args, 0); + tcg_out_qemu_st(s, args, TCG_TYPE_I32); break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, 1); + tcg_out_qemu_st(s, args, TCG_TYPE_I64); break; =20 OP_32_64(mulu2): --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922186; cv=none; d=zohomail.com; s=zohoarc; b=Te1qkAWI8VTyq3rufDWaMpeJ3o18sXfDvAheMwQDMXgq1yS6oc/umCgyVs8KDIa04BHverVmaaNiWsSf9jBSMfJNNHnfKStsFTxE7FuKLQ8iaW+pGEkJzbZ0aHhNxeimBqRIv1CWAHgGeXP/YXJabXnJJxQmmTgCAQ4dl+/KsI0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680922186; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=a+sskExgwdL7kNpVsak9SGGYO2z60XgotlxGnsJ8eQ4=; b=a1H5U2DjufgFRyZezMEON4WInhnuWCphDtznnjJeRn5LF4ssQNqZr4KkEG2G25DoIyAwN8sXzaUFcG5JlIEVLGltydJzdhQ2ftYAdGfcqlwyBnoERnBOP6LQ5b4QZY1NkZ8K32FAhkp5Yp9u52vxAKv97AGN5eNHIMG2GfbXQg8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680922186610250.47352377574646; Fri, 7 Apr 2023 19:49:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyYc-0007l9-Bn; Fri, 07 Apr 2023 22:44:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyYa-0007j8-VG for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:00 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyYB-0005Zj-V7 for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:00 -0400 Received: by mail-pl1-x62d.google.com with SMTP id e13so57047plc.12 for ; Fri, 07 Apr 2023 19:43:35 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921815; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a+sskExgwdL7kNpVsak9SGGYO2z60XgotlxGnsJ8eQ4=; b=NMg+zWyTpPnkv92xpy0TqsMuGsnq389StBGMoJoeS6T6KNlye/fDUkgTavsroY39TD A62SNHueP0v7lyRqAFEbUNTfIpta5S33ghZcF63820J5W0frNqRiZV4SEzC4OiGXpKas Oaf9wPpFwB2YaiMZMCqa0oKvavvyvgX3FEhZPToI5fGLKIIqRdq1YpzJuZs1qD7GTZTs z0QSARu+3rw422oa0wiuclLHysBH3AW7Qohp6WGl+nDKAmR8/6j0WhwjDimHiAQGyEoW 59xSWHLd1svgnao9scC/kX6VYid34lI9NhOtpD2SwOwrlm8d+k48UIYjR9sXHolcBbJ6 WUrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921815; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a+sskExgwdL7kNpVsak9SGGYO2z60XgotlxGnsJ8eQ4=; b=zTb6Y6WYHGCzNxPCeN12aoK+ZP1LTYqEAXHfM+ZwB8uqV9Dj7+/a68fCc3nglo0mvf bX9CDGb27JRkljC5NdAOX3kgxtKQyV1MIJ+N098Soaj4C5pOFiAuqLX9o4AgBhgwzbfN LlPchIwlGwqvUcLvsKnfDIFpQe0x1r9CTa6ULZBYGnWv2lTPTUzi6TUS84dL5qKiHWRh gztW6OoHV/ax1y7bzR50UHIYWokpiCo55Yu9gX+y4tQlPv3h/CSwg/2Qsqy1G16b/7yA W90XOXEmCX/hPQk6KYWOpfNZStZHEwq8LvsAPQywJgkNhKJ+zZES8uGgm5iNAdVtPx3Z iTlA== X-Gm-Message-State: AAQBX9fW7OzMgkb/rROjVcM/X/1oEGTGeObLZ6cjUxZuGYM4/RWfrIDJ xrYyOT8QXEJYwGT347PthjSGFD0X8uY7D6NfjGU= X-Google-Smtp-Source: AKy350awwjSiY8RSX2bTqCLvdx6e895lge41ckLsI/hcWe/6IeIXLY3F5D8VrmG65dlKWQTtItz7bA== X-Received: by 2002:a17:902:d4c5:b0:1a5:1471:e397 with SMTP id o5-20020a170902d4c500b001a51471e397mr5209765plg.61.1680921815138; Fri, 07 Apr 2023 19:43:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 21/42] tcg/aarch64: Rename ext to d_type in tcg_out_qemu_ld Date: Fri, 7 Apr 2023 19:42:53 -0700 Message-Id: <20230408024314.3357414-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922187212100005 Content-Type: text/plain; charset="utf-8" The new name is slightly more descritive as "data type", where "extend", despite the c type, sounds like a bool. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/aarch64/tcg-target.c.inc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 4ec3cf3172..40122e1471 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1851,7 +1851,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, Mem= Op memop, } =20 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, - MemOpIdx oi, TCGType ext) + MemOpIdx oi, TCGType d_type) { MemOp memop =3D get_memop(oi); const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; @@ -1864,9 +1864,9 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a_reg, TCGReg addr_reg, tcg_insn_unit *label_ptr; =20 tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1); - tcg_out_qemu_ld_direct(s, memop, ext, data_reg, + tcg_out_qemu_ld_direct(s, memop, d_type, data_reg, TCG_REG_X1, otype, addr_reg); - add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg, + add_qemu_ldst_label(s, true, oi, d_type, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ unsigned a_bits =3D get_alignment_bits(memop); @@ -1874,10 +1874,10 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, tcg_out_test_alignment(s, true, addr_reg, a_bits); } if (USE_GUEST_BASE) { - tcg_out_qemu_ld_direct(s, memop, ext, data_reg, + tcg_out_qemu_ld_direct(s, memop, d_type, data_reg, TCG_REG_GUEST_BASE, otype, addr_reg); } else { - tcg_out_qemu_ld_direct(s, memop, ext, data_reg, + tcg_out_qemu_ld_direct(s, memop, d_type, data_reg, addr_reg, TCG_TYPE_I64, TCG_REG_XZR); } #endif /* CONFIG_SOFTMMU */ --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922196; cv=none; d=zohomail.com; s=zohoarc; b=PSOLK/U4wQhPM6cHfl9jCStiJlCUOc3x4EqLQyWdRr7lTDHzcK471zFzQRzDdSGkmuwTXmpe7j+aUYgDoLDVfBZcbqYq5BCZA3nzyhCytPsIS/zxDXyh56a9dA652ObFlKJL0GnzOYHq48VKa6b9w1VS9thzozQmksT+KP8eLJw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680922196; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eotj0MrHKLP1v2S4T/0WUNCjwFrcd26O8tCK+46bnIc=; b=Uor1PvlrMU3HFa/fvMJnzvIjM3zsFvJJ3h7ZWzGLI1u4D7cv8VeP2181Oe6VSuOzUBQugDJ21BwesNHg0AS08ZRmKXqeVmpSG3uJNevCNyEaSet11F8ZvW2yRmmmwDCJuMql0aI/dd80IOtNq+6Jj7Rn5ZtfZ44kLHNm0bMfrig= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168092219635813.208446594817133; Fri, 7 Apr 2023 19:49:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyYe-0007nl-MO; Fri, 07 Apr 2023 22:44:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyYc-0007lT-LB for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:02 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyYD-0005jQ-BW for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:02 -0400 Received: by mail-pj1-x102e.google.com with SMTP id v9so5046522pjk.0 for ; Fri, 07 Apr 2023 19:43:36 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eotj0MrHKLP1v2S4T/0WUNCjwFrcd26O8tCK+46bnIc=; b=uojDrGl3eBNqzY5LM9a1aMvyIB1I/hWsByM81JC12eAyd5BoqzrCT5BChoHq7dcm0Y uCx6eIiIvNrMi+8kRfadXvogKYZE4luZi9tEhRCt/wAkO435ld0GTwT2EBTHYwIoHmn+ 1hisCidySMHAdRwmjRkdUrz3U3lA3+rx8qlM+Nd2EJFSTBwQ+9mnAHZYUxNJDy5qzVv2 xXQkGXFeSYVB6z+czETKxlozaWXxs6rsWjWxOfOeD/iWE//tNbZaPNOkKkyl0ZLk//s+ amg8AEQ6WhtpGGybh5e245WB9UUZiVDo2AzxsDLmNyHxS/+Qp+se6w4TorJ2ZDrvoWS9 Tymw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eotj0MrHKLP1v2S4T/0WUNCjwFrcd26O8tCK+46bnIc=; b=fA3QYAvOSTdoKsrlBvy9fJJgWfpuGZJnk0wx1YPPFpyW6aPzenh74ZtiZmclIePQsP KaAg3XqcOwIjZw//mEUl6w2uB1WzwwFLInGuyDb1zUBiEqlz621mmRjiRhkoRcfyeiVy Z4fY9A085IP36HY4kkHe1U+qIOcvRhrAKHkKz/CZYNn6+H++LDJ8623kAI7pa8Ha/YKf UQ/1wPaHZVdUCWtptp1NhCLBrHeJcDpJWKVd18yyDS4q7IJmJSRLRz3D06nLUtkBN4Yd 3Zfb0waewd7cg382/Twf137ugpbU8Kyd98T5IYA+IdWub2gYEyN7Pb0xtGUpWlnQXgI3 5yEA== X-Gm-Message-State: AAQBX9fvTCKgtIdyOrTOhT6LDheH9vVM++gxMxfazZHz37HOfh/gxS6A G+1eka663pHRxLQA0wB/AaVAzUR22XPV9IMDskE= X-Google-Smtp-Source: AKy350bCKI5ayzFWMaJIapVTsafkgaKUZ3RSW0zFbrTneZu5N7Jvatqy6OUjOr/aU/dx4uC+zk3yiA== X-Received: by 2002:a17:902:f291:b0:19c:d7a9:8be1 with SMTP id k17-20020a170902f29100b0019cd7a98be1mr3829634plc.61.1680921815975; Fri, 07 Apr 2023 19:43:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 22/42] tcg/aarch64: Pass TGType to tcg_out_qemu_st Date: Fri, 7 Apr 2023 19:42:54 -0700 Message-Id: <20230408024314.3357414-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922198414100005 Content-Type: text/plain; charset="utf-8" This evens out the interface to match tcg_out_qemu_ld, and makes the argument to add_qemu_ldst_label less obscure. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 40122e1471..f8d3ef4714 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1884,7 +1884,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a_reg, TCGReg addr_reg, } =20 static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, - MemOpIdx oi) + MemOpIdx oi, TCGType d_type) { MemOp memop =3D get_memop(oi); const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; @@ -1899,8 +1899,8 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= a_reg, TCGReg addr_reg, tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0); tcg_out_qemu_st_direct(s, memop, data_reg, TCG_REG_X1, otype, addr_reg); - add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)=3D=3D MO_64, - data_reg, addr_reg, s->code_ptr, label_ptr); + add_qemu_ldst_label(s, false, oi, d_type, data_reg, addr_reg, + s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ unsigned a_bits =3D get_alignment_bits(memop); if (a_bits) { @@ -2249,7 +2249,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, REG0(0), a1, a2); + tcg_out_qemu_st(s, REG0(0), a1, a2, ext); break; =20 case INDEX_op_bswap64_i64: --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680922292693490.68023340265995; Fri, 7 Apr 2023 19:51:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyYf-0007ol-H1; Fri, 07 Apr 2023 22:44:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyYd-0007n0-OX for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:03 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyYE-0005k4-3x for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:03 -0400 Received: by mail-pl1-x62a.google.com with SMTP id w11so368805plp.13 for ; Fri, 07 Apr 2023 19:43:37 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921817; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HILSA4FGaRdNKn9uDo5A96FpFkUHaWEI+nrm0ay0YIU=; b=T8Sfhn0B336VqWRI8Cj7nE2BiBs7knfZv18eWruZ5znf0s5mJ2WLjMrbraAjXi8Pxd y9lmdTvPxNCui/aN3MGkzR9Ovs6GSsx/7dJpXlCWEUJ06AW2eTHVw0C8FcSgNF3cGUAB uWRLtjFkBysuUBswyru4Jj3/k/WBSpo356U77eM0gCfxB5FcRUg659zhTxasKp0ktLbb aeC2HReS2c8VF3NO9j7F7/ByGegNBIDGkIRqxvE/i+V5j6uHrIeE+CVZ5QCmHjVqjAYa MBs+5fnXHnnmQM1orRxEsfSIRs54wP9GD1314IeHViMcWCpaC/pPja50CfWOq0LvO1Zn BMGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921817; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HILSA4FGaRdNKn9uDo5A96FpFkUHaWEI+nrm0ay0YIU=; b=2AMmXLilzgHwWNFgeQtR7ddH1d64N6PJr0IQ1oMmIUOmQB5UDOtsgoeaHl5WedDbMv y7Th6E5y+Kxj4NFUNJEagT2s8Dl+WRP7D+pXp/LZgtxt421SRgNLjdScUw6dB8nXcG1/ btEpRPp3GxXQF1se8FpdoO579XDd+744TmEblmeD4ppJUB1pS4zz0CK8Ta7dIjbQvkQL PmDnV/YaWTmxFZ+639lkE0E41b1bY6l17Qfupi+E/psBjhzByG4Zs0dZHyHKwlv5CCH5 Np2w1oU0gSWSiHxTpe41GifSYcM5DbO28n0LpkGPiZqvcGreQ6jhKkI7S9VBdPgR4Jug g0YQ== X-Gm-Message-State: AAQBX9ep1EL2S03OyPVlHClZ2l977VKAoe3NtoH5YbNx302CLew4APO4 IIHK9UZztJZbAUNtFsCjPsQSOCcF9wB4nZ4aGEw= X-Google-Smtp-Source: AKy350Y8kc/xv/qfi5xW9l5zh0E5CuU5+zjtfnXJOYxpyNXQVf7B9SMHV2dShYDqMEcPYU6fQQZ2qQ== X-Received: by 2002:a17:903:230b:b0:1a1:b5e3:7db4 with SMTP id d11-20020a170903230b00b001a1b5e37db4mr5202003plh.18.1680921816698; Fri, 07 Apr 2023 19:43:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 23/42] tcg/arm: Use TCGType not bool is_64 in tcg_out_qemu_{ld, st} Date: Fri, 7 Apr 2023 19:42:55 -0700 Message-Id: <20230408024314.3357414-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1680922294791100003 Content-Type: text/plain; charset="utf-8" We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index bad1e6d399..9bf831223a 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1526,15 +1526,17 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addrlo, TCGReg addrhi, /* Record the context of a call to the out of line helper code for the slow path for a load or store, so that we can later generate the correct helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, - TCGReg datalo, TCGReg datahi, TCGReg addrl= o, - TCGReg addrhi, tcg_insn_unit *raddr, +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGType type, + MemOpIdx oi, TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + tcg_insn_unit *raddr, tcg_insn_unit *label_ptr) { TCGLabelQemuLdst *label =3D new_ldst_label(s); =20 label->is_ld =3D is_ld; label->oi =3D oi; + label->type =3D type; label->datalo_reg =3D datalo; label->datahi_reg =3D datahi; label->addrlo_reg =3D addrlo; @@ -1788,7 +1790,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, Mem= Op opc, TCGReg datalo, } #endif =20 -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) +static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGType d_t= ype) { TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); MemOpIdx oi; @@ -1802,7 +1804,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) #endif =20 datalo =3D *args++; - datahi =3D (is64 ? *args++ : 0); + datahi =3D (d_type =3D=3D TCG_TYPE_I32 ? 0 : *args++); addrlo =3D *args++; addrhi =3D (TARGET_LONG_BITS =3D=3D 64 ? *args++ : 0); oi =3D *args++; @@ -1819,7 +1821,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) =20 tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend, true); =20 - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, + add_qemu_ldst_label(s, true, oi, d_type, datalo, datahi, addrlo, addrh= i, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ a_bits =3D get_alignment_bits(opc); @@ -1910,7 +1912,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, Mem= Op opc, TCGReg datalo, } #endif =20 -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) +static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGType d_t= ype) { TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); MemOpIdx oi; @@ -1924,7 +1926,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) #endif =20 datalo =3D *args++; - datahi =3D (is64 ? *args++ : 0); + datahi =3D (d_type =3D=3D TCG_TYPE_I32 ? 0 : *args++); addrlo =3D *args++; addrhi =3D (TARGET_LONG_BITS =3D=3D 64 ? *args++ : 0); oi =3D *args++; @@ -1941,7 +1943,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) label_ptr =3D s->code_ptr; tcg_out_bl_imm(s, COND_NE, 0); =20 - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, + add_qemu_ldst_label(s, false, oi, d_type, datalo, datahi, addrlo, addr= hi, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ a_bits =3D get_alignment_bits(opc); @@ -2237,16 +2239,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, 0); + tcg_out_qemu_ld(s, args, TCG_TYPE_I32); break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, 1); + tcg_out_qemu_ld(s, args, TCG_TYPE_I64); break; case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, 0); + tcg_out_qemu_st(s, args, TCG_TYPE_I32); break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, 1); + tcg_out_qemu_st(s, args, TCG_TYPE_I64); break; =20 case INDEX_op_bswap16_i32: --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680922196951267.8532715661685; Fri, 7 Apr 2023 19:49:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyYh-0007rH-86; Fri, 07 Apr 2023 22:44:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyYf-0007oz-QZ for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:05 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyYF-0005kl-5z for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:05 -0400 Received: by mail-pj1-x1033.google.com with SMTP id r7-20020a17090b050700b002404be7920aso42932886pjz.5 for ; Fri, 07 Apr 2023 19:43:38 -0700 (PDT) Received: from stoup.. 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Clean things up by using type throughout. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/mips/tcg-target.c.inc | 56 +++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 29 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index a83ebe8729..568cfe7728 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1479,7 +1479,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) #endif /* SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, - TCGReg base, MemOp opc, bool is_64) + TCGReg base, MemOp opc, TCGType type) { switch (opc & (MO_SSIZE | MO_BSWAP)) { case MO_UB: @@ -1503,7 +1503,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, tcg_out_opc_imm(s, OPC_LH, lo, base, 0); break; case MO_UL | MO_BSWAP: - if (TCG_TARGET_REG_BITS =3D=3D 64 && is_64) { + if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64) { if (use_mips32r2_instructions) { tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); tcg_out_bswap32(s, lo, lo, TCG_BSWAP_IZ | TCG_BSWAP_OZ); @@ -1528,7 +1528,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, } break; case MO_UL: - if (TCG_TARGET_REG_BITS =3D=3D 64 && is_64) { + if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64) { tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); break; } @@ -1583,7 +1583,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, } =20 static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, - TCGReg base, MemOp opc, bool is_64) + TCGReg base, MemOp opc, TCGType type) { const MIPSInsn lw1 =3D MIPS_BE ? OPC_LWL : OPC_LWR; const MIPSInsn lw2 =3D MIPS_BE ? OPC_LWR : OPC_LWL; @@ -1623,7 +1623,7 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TC= GReg lo, TCGReg hi, case MO_UL: tcg_out_opc_imm(s, lw1, lo, base, 0); tcg_out_opc_imm(s, lw2, lo, base, 3); - if (TCG_TARGET_REG_BITS =3D=3D 64 && is_64 && !sgn) { + if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64 && != sgn) { tcg_out_ext32u(s, lo, lo); } break; @@ -1634,18 +1634,18 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, = TCGReg lo, TCGReg hi, tcg_out_opc_imm(s, lw1, lo, base, 0); tcg_out_opc_imm(s, lw2, lo, base, 3); tcg_out_bswap32(s, lo, lo, - TCG_TARGET_REG_BITS =3D=3D 64 && is_64 + TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D T= CG_TYPE_I64 ? (sgn ? TCG_BSWAP_OS : TCG_BSWAP_OZ) : 0); } else { const tcg_insn_unit *subr =3D - (TCG_TARGET_REG_BITS =3D=3D 64 && is_64 && !sgn + (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I64= && !sgn ? bswap32u_addr : bswap32_addr); =20 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0); tcg_out_bswap_subr(s, subr); /* delay slot */ tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 3); - tcg_out_mov(s, is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, lo, TCG_TM= P3); + tcg_out_mov(s, type, lo, TCG_TMP3); } break; =20 @@ -1702,7 +1702,7 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TC= GReg lo, TCGReg hi, } } =20 -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGType d_t= ype) { TCGReg addr_regl, addr_regh __attribute__((unused)); TCGReg data_regl, data_regh; @@ -1716,7 +1716,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) TCGReg base =3D TCG_REG_A0; =20 data_regl =3D *args++; - data_regh =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); + data_regh =3D (TCG_TARGET_REG_BITS =3D=3D 64 || d_type =3D=3D TCG_TYPE= _I32 + ? 0 : *args++); addr_regl =3D *args++; addr_regh =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); oi =3D *args++; @@ -1731,14 +1732,12 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is_64) #if defined(CONFIG_SOFTMMU) tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1); if (use_mips32r6_instructions || a_bits >=3D s_bits) { - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, d_type); } else { - tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is_64); + tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, d_type= ); } - add_qemu_ldst_label(s, 1, oi, - (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_regl, data_regh, addr_regl, addr_regh, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, true, oi, d_type, data_regl, data_regh, + addr_regl, addr_regh, s->code_ptr, label_ptr); #else if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { tcg_out_ext32u(s, base, addr_regl); @@ -1755,15 +1754,15 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is_64) if (a_bits) { tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); } - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, d_type); } else { if (a_bits && a_bits !=3D s_bits) { tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); } if (a_bits >=3D s_bits) { - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_= 64); + tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, d_t= ype); } else { - tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is= _64); + tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, d_= type); } } #endif @@ -1902,7 +1901,7 @@ static void tcg_out_qemu_st_unalign(TCGContext *s, TC= GReg lo, TCGReg hi, g_assert_not_reached(); } } -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGType d_t= ype) { TCGReg addr_regl, addr_regh __attribute__((unused)); TCGReg data_regl, data_regh; @@ -1915,7 +1914,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) TCGReg base =3D TCG_REG_A0; =20 data_regl =3D *args++; - data_regh =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); + data_regh =3D (TCG_TARGET_REG_BITS =3D=3D 64 || d_type =3D=3D TCG_TYPE= _I32 + ? 0 : *args++); addr_regl =3D *args++; addr_regh =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); oi =3D *args++; @@ -1934,10 +1934,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCG= Arg *args, bool is_64) } else { tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc); } - add_qemu_ldst_label(s, 0, oi, - (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_regl, data_regh, addr_regl, addr_regh, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, false, oi, d_type, data_regl, data_regh, + addr_regl, addr_regh, s->code_ptr, label_ptr); #else if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { tcg_out_ext32u(s, base, addr_regl); @@ -2425,16 +2423,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, false); + tcg_out_qemu_ld(s, args, TCG_TYPE_I32); break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, true); + tcg_out_qemu_ld(s, args, TCG_TYPE_I64); break; case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, false); + tcg_out_qemu_st(s, args, TCG_TYPE_I32); break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, true); + tcg_out_qemu_st(s, args, TCG_TYPE_I64); break; =20 case INDEX_op_add2_i32: --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680922252599860.6516324787254; Fri, 7 Apr 2023 19:50:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyYi-0007t7-3g; Fri, 07 Apr 2023 22:44:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyYg-0007pP-Ab for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:06 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyYF-0005YH-Gc for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:06 -0400 Received: by mail-pj1-x102f.google.com with SMTP id d22-20020a17090a111600b0023d1b009f52so2769548pja.2 for ; Fri, 07 Apr 2023 19:43:38 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921818; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kRhYzkFI7SReCS0UgAbm5E5KG3teujgs6bUm8xjSxNw=; b=vNYqaR0g9IXdZYfDXEptsNtr9u4Jj5OyU2IN6tO/mh4epKWvXhNTQvNjjcaK86lRek kclVimXZ9nlen18a84FE5qnXqQd4kVf6W8daJxEyN+41EbGHRvfrrm2iy5QDnCn7WFSz vIFPdPXB3+epG+mdS/HymN4Z7DUW5xXKVUMTU9rC7TSjgcrMrVF5/IvXrLqexO6G+8fV SynCfezLuYBfU5QECBaV/UeN2zI/jAR3ge8tgr5/e93y+guLE6qUvVQNfSLtt8TSjAJm t4A+Oq+vKWIn6/ma6Khm8BxbLPqFAbvwF/Ux93TAvOWEmdeRs5GSK/xYqytQXW6a/Arl SJ1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921818; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kRhYzkFI7SReCS0UgAbm5E5KG3teujgs6bUm8xjSxNw=; b=Obf6DWZwBRUAdhBiQpsAorcrOJRX/wpIQrax0m45Y/pCxDclh9qeuOLi4JLraUBGNN x81pw1Tk5LMGQZ+86K6cgXtLNEzVPC/sppcGoMkSBw84VCoa8TfhdTkqFCPTYARjbk7O JpTDKQThgFvDCl73FE8HS7qI/B6K5LoNTUw1GIKqpU0iNMP0Od+WAhUUJ4FiJ4wLLULI w8WK3zZhTTLmjAfAe4SU3yaqBXG9TjATvWVt6Sfu5fXk/t3u/IY7f8p8PApynrC12m/H +f/n+s9vd2ANe8a3nW5AQElyyZW8i5mSqy5rIB8UmEZs4btbcsxtInTLqJE2HaaHqfbU U2/Q== X-Gm-Message-State: AAQBX9ecnyzQDnvstqL2Iu6ZHxutcmWdzXeRCyy47GxFoaQBFeKRWS1d 7XlzOavZUGHCCOgqaduUjiG0d1fLMmsmrBY3mgo= X-Google-Smtp-Source: AKy350Zv9u9Ei+8sqeDL+BJvO3pEnrU2Z2q0DrKXcJKaV+9zrw6TW+VIFU0X05Z9g7OeD5W9gvjvZQ== X-Received: by 2002:a17:903:22c3:b0:1a1:ae8d:1379 with SMTP id y3-20020a17090322c300b001a1ae8d1379mr6442419plg.7.1680921818613; Fri, 07 Apr 2023 19:43:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 25/42] tcg/ppc: Use TCGType not bool is_64 in tcg_out_qemu_{ld, st} Date: Fri, 7 Apr 2023 19:42:57 -0700 Message-Id: <20230408024314.3357414-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1680922254739100007 Content-Type: text/plain; charset="utf-8" We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/ppc/tcg-target.c.inc | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index d3e547998f..7c33404bd6 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2117,7 +2117,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp o= pc, /* Record the context of a call to the out of line helper code for the slow path for a load or store, so that we can later generate the correct helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, + TCGType type, MemOpIdx oi, TCGReg datalo_reg, TCGReg datahi_reg, TCGReg addrlo_reg, TCGReg addrhi_reg, tcg_insn_unit *raddr, tcg_insn_unit *lptr) @@ -2125,6 +2126,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, MemOpIdx oi, TCGLabelQemuLdst *label =3D new_ldst_label(s); =20 label->is_ld =3D is_ld; + label->type =3D type; label->oi =3D oi; label->datalo_reg =3D datalo_reg; label->datahi_reg =3D datahi_reg; @@ -2287,7 +2289,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) =20 #endif /* SOFTMMU */ =20 -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGType d_t= ype) { TCGReg datalo, datahi, addrlo, rbase; TCGReg addrhi __attribute__((unused)); @@ -2301,7 +2303,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) #endif =20 datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); + datahi =3D TCG_TARGET_REG_BITS =3D=3D 64 || d_type =3D=3D TCG_TYPE_I32= ? 0 : *args++; addrlo =3D *args++; addrhi =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); oi =3D *args++; @@ -2363,12 +2365,12 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is_64) } =20 #ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, + add_qemu_ldst_label(s, true, d_type, oi, datalo, datahi, addrlo, addrh= i, s->code_ptr, label_ptr); #endif } =20 -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGType d_t= ype) { TCGReg datalo, datahi, addrlo, rbase; TCGReg addrhi __attribute__((unused)); @@ -2382,7 +2384,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) #endif =20 datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); + datahi =3D TCG_TARGET_REG_BITS =3D=3D 64 || d_type =3D=3D TCG_TYPE_I32= ? 0 : *args++; addrlo =3D *args++; addrhi =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); oi =3D *args++; @@ -2436,7 +2438,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) } =20 #ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, + add_qemu_ldst_label(s, false, d_type, oi, datalo, datahi, addrlo, addr= hi, s->code_ptr, label_ptr); #endif } @@ -2971,16 +2973,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, false); + tcg_out_qemu_ld(s, args, TCG_TYPE_I32); break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, true); + tcg_out_qemu_ld(s, args, TCG_TYPE_I64); break; case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, false); + tcg_out_qemu_st(s, args, TCG_TYPE_I32); break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, true); + tcg_out_qemu_st(s, args, TCG_TYPE_I64); break; =20 case INDEX_op_setcond_i32: --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922008; cv=none; d=zohomail.com; s=zohoarc; b=cuCas6u2K/K+3JENeOatJ5i36J2WLupmECCHO/oYHBmWJRjlG2bp51GgiJZFxSMbswj4bY7LihNP1xTiNQYZ6nULzJ+xFkVhfzC/xSkB1pG+UlLkmMCS2Scs90BJ6cmrS9ftmxU8DTXvaaW6lUynIqxNo+mhGr/3wIcmI7SyXQk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680922008; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=v1FKEPnLDJAj/yYVllIJiIXirCKiRcnvS7tDELskOLA=; b=VC01dDAwOWrb6jkGOnF5mmx9376IcSRtzkAsJ9aowLHqrieYBJa45jfvbIe8UGCv6A3Krqfn2W3mGhqPeqVcbL1HPhchZbwCuoyHJYLZz1GKJHI39fj0pXEkW+Xqs37bRB+vHAUN2DPlvO7t8uTjH5bObVBjABUjGJgD6kURTj0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168092200815844.997196076921; Fri, 7 Apr 2023 19:46:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyYj-0007w3-RV; Fri, 07 Apr 2023 22:44:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyYi-0007uV-OB for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:08 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyYG-0005mA-Q9 for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:08 -0400 Received: by mail-pj1-x1033.google.com with SMTP id v9so5046585pjk.0 for ; Fri, 07 Apr 2023 19:43:40 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921819; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v1FKEPnLDJAj/yYVllIJiIXirCKiRcnvS7tDELskOLA=; b=DHujcaH32y4Zna1dz1MkOyyv60Bg2NPIiAmQwTOSqaG7Pxbg7U1TjILh0iD0xt5Y5x cEwwRReqyIEt3rgWzw0iPhMEpb1LgSQp9mflVoRvY9j0B8M13zv6ZQWdJEG33UWE0y9A yGniyV8PORKD8TKFNhr5ZDQWE2IhFTQVH8u10+17MDdIYTI8it2l6eb5j4rqgAjidndq mSNnOwiMhL77omghATzozmADNTa6pMYIoaClcmVlxgWhByDTlMfB056P2LHxk0SlsD6O WigdbRwFa5+poGkgSvne7Rx6ulDwQfbmzz1s2xHI8smtaAnMBFVe+Q6iUJfEs/SDf0cK tr8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921819; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v1FKEPnLDJAj/yYVllIJiIXirCKiRcnvS7tDELskOLA=; b=bC5yI+SI9KQLTZFOuWSrCa02iLnmVm77QxLlocZpynxCJrtrLRftCa4TUEZOCF0Og2 iquirvbBdsJlEaa/o42muDkSk0SqwIVkpSAwb9R2adO186B7P1oMpW9FHVgWedSB/QkN Wu7QurVqdxWLD7xLo7y0dT3pkbXIXMzggyP/YxUSFub7ZjaLo2AmNO28hhfGs6SymOaP gDK41HmT9Vt0TynuC3bTGrOtDVSmJ9SGXN4xwEhk5i2nyHmee70PaGh9I1cI7ZWw20Ip C3kqA9v9mGMlqy0xTjHexAekb8yvHBAU1CKuyTbkpj4rpL+7eZ/d9/Aw2wxQOsQ2Cf7T IJqQ== X-Gm-Message-State: AAQBX9cfbiyotbBhDvU/vq94CNCzWjdN3+Y9DtwoSnQKHGdNZRV0RHMo /XJhrju2zBR6gnPOJ+lpaC9XqjGuJSiHzvqkldk= X-Google-Smtp-Source: AKy350an2vdxuMoVx8+aJxwgsk/mHnxgVuYN2zCC151wngoMwdnzsZjt/zYFhXxxunHxmqF8yXBbcA== X-Received: by 2002:a17:902:da8a:b0:1a0:5524:eb8e with SMTP id j10-20020a170902da8a00b001a05524eb8emr5964539plx.68.1680921819421; Fri, 07 Apr 2023 19:43:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 26/42] tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st} Date: Fri, 7 Apr 2023 19:42:58 -0700 Message-Id: <20230408024314.3357414-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922009638100003 Content-Type: text/plain; charset="utf-8" We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/s390x/tcg-target.c.inc | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index b399798664..77dcdd7c0f 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1770,13 +1770,14 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addr_reg, MemOp opc, } =20 static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, - TCGReg data, TCGReg addr, + TCGType type, TCGReg data, TCGReg addr, tcg_insn_unit *raddr, tcg_insn_unit *label= _ptr) { TCGLabelQemuLdst *label =3D new_ldst_label(s); =20 label->is_ld =3D is_ld; label->oi =3D oi; + label->type =3D type; label->datalo_reg =3D data; label->addrlo_reg =3D addr; label->raddr =3D tcg_splitwx_to_rx(raddr); @@ -1900,7 +1901,7 @@ static void tcg_prepare_user_ldst(TCGContext *s, TCGR= eg *addr_reg, #endif /* CONFIG_SOFTMMU */ =20 static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_re= g, - MemOpIdx oi) + MemOpIdx oi, TCGType d_type) { MemOp opc =3D get_memop(oi); #ifdef CONFIG_SOFTMMU @@ -1916,7 +1917,8 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg dat= a_reg, TCGReg addr_reg, =20 tcg_out_qemu_ld_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0); =20 - add_qemu_ldst_label(s, 1, oi, data_reg, addr_reg, s->code_ptr, label_p= tr); + add_qemu_ldst_label(s, 1, oi, d_type, data_reg, addr_reg, + s->code_ptr, label_ptr); #else TCGReg index_reg; tcg_target_long disp; @@ -1931,7 +1933,7 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg dat= a_reg, TCGReg addr_reg, } =20 static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_re= g, - MemOpIdx oi) + MemOpIdx oi, TCGType d_type) { MemOp opc =3D get_memop(oi); #ifdef CONFIG_SOFTMMU @@ -1947,7 +1949,8 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg dat= a_reg, TCGReg addr_reg, =20 tcg_out_qemu_st_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0); =20 - add_qemu_ldst_label(s, 0, oi, data_reg, addr_reg, s->code_ptr, label_p= tr); + add_qemu_ldst_label(s, 0, oi, d_type, data_reg, addr_reg, + s->code_ptr, label_ptr); #else TCGReg index_reg; tcg_target_long disp; @@ -2307,13 +2310,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpc= ode opc, break; =20 case INDEX_op_qemu_ld_i32: - /* ??? Technically we can use a non-extending instruction. */ + tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I32); + break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args[0], args[1], args[2]); + tcg_out_qemu_ld(s, args[0], args[1], args[2], TCG_TYPE_I64); break; case INDEX_op_qemu_st_i32: + tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I32); + break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args[0], args[1], args[2]); + tcg_out_qemu_st(s, args[0], args[1], args[2], TCG_TYPE_I64); break; =20 case INDEX_op_ld16s_i64: --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922252; cv=none; d=zohomail.com; s=zohoarc; b=Iejz2Z79v0nomn9bs8USSgDOr++KBTxbTsv7482x49RLnbMI7mFilX/6pYj98cJ3s5Ij6BOnW+fyn4HHjmNa3E6gf+1B6Nc+FTj1ThwSWJBrYZGBGHvg4AgdtDCgG5tPDsfuX/QJoAcFRwuytpWyNb0/Wu2joW2CY+N0pnL3T3g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680922252; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gWNFlfZGMhS6B+KGVOyjjirk7RtDUuySYtzYO/fgGBY=; b=TXzZDHgVNJPXFtb1HT3tPHvvXrMqzrIwW8iHcNKcEpl1PvPzULiYZIj5BqqhF/HoZQH+UZsop/NaeBhal1SolgknXQ0XbYNVE8y2wbO3drMQkxKo3L4whKDhY7ZzoXAdk1ZlUAvoMFuiCBxZA4HjLymxrI8AN4SB8A4Iro0mm2o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680922252738827.4570949182842; Fri, 7 Apr 2023 19:50:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyYm-0007yk-UL; Fri, 07 Apr 2023 22:44:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyYl-0007xc-IV for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:11 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyYH-0005Wl-Cs for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:10 -0400 Received: by mail-pl1-x62f.google.com with SMTP id n14so25486168plc.8 for ; Fri, 07 Apr 2023 19:43:40 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921820; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gWNFlfZGMhS6B+KGVOyjjirk7RtDUuySYtzYO/fgGBY=; b=UgZdWMIZXN3ZycXYKAa5S9877xwVbRZRQ+O/eDA/iILke4045+MgfErNcQx3K0/qed OdY7x4Fypxvtm5TFZpC/+dSy3UCMxsSp+5Ch/poVvf7Oo0rJEjF+IG7Z3e2FdXYsQ/c1 GYRJXSVafjyfn+sJA2SUj4JlRLQnALuJve1Q9FKl5dEOBan96tipGRwzCwhgSZJ00I/R eEG3A4iP9vVn7wGE1INfi8V+sjHmxTJBAlsOAwX1qec9jRFvDWkUFqrVsSNvV+GbFjZb uXrKrzUZIcxJOshUrxucZ9xUjAmlGfePae61ZMLUs+BDris71MYkIcsMTDBj3L5YRMl/ he3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921820; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gWNFlfZGMhS6B+KGVOyjjirk7RtDUuySYtzYO/fgGBY=; b=Y9GU+w9aKONpbnBq03KyhLRis0X9giJH+wd9Jec88PXfo2F7xAYIaZuDCltNsKEqJM h26XBGwABEcy4j8Gkh9jxqoF21yfjVHHyzCT5o/ZtiZFD8huKP3QGNefxQ47RtmDbSNB OGYYNSd/dKaX3XMRdEX0yH4w47j1NQ8VUhY+bGXF0javZRo2goZIbZ+c8EU3hzPjeZSR SJs2b2D86LQgtpCWutbnqVtBC67UWRSSNAgCHg+GnT4RaLGJdYCTrZHp/PEjx10BXqJh E47xHGkxGMbkfO0harDW8WMGiV5f7C4eSuVU6mmLT5VPG0piTWRTow2E4PNMW+1Y6rZW sk8Q== X-Gm-Message-State: AAQBX9dlMlV6z7tYUn3inOkZ5IL6aZLyZ+Od9z2bgPqr4LRzjsdaIX94 ULOVWt/W7pRj3dMkhfvJPc5MeI/293/IbMtRIJc= X-Google-Smtp-Source: AKy350b6cLo2eUXC5P7vr/nwfAhTR9AOk900hlf2tYOpzhPSqawnrC5R2NEBllvpCiqQZjgRpLPv0g== X-Received: by 2002:a17:902:da87:b0:1a1:241a:9bd0 with SMTP id j7-20020a170902da8700b001a1241a9bd0mr4345592plx.5.1680921820299; Fri, 07 Apr 2023 19:43:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 27/42] tcg/riscv: Require TCG_TARGET_REG_BITS == 64 Date: Fri, 7 Apr 2023 19:42:59 -0700 Message-Id: <20230408024314.3357414-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922253351100002 Content-Type: text/plain; charset="utf-8" The port currently does not support "oversize" guests, which means riscv32 can only target 32-bit guests. We will soon be building TCG once for all guests. This implies that we can only support riscv64. Since all Linux distributions target riscv64 not riscv32, this is not much of a restriction and simplifies the code. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 6 - tcg/riscv/tcg-target.h | 22 ++-- tcg/riscv/tcg-target.c.inc | 206 ++++++++++----------------------- 3 files changed, 72 insertions(+), 162 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index cf0ac4d751..c11710d117 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -13,18 +13,12 @@ C_O0_I1(r) C_O0_I2(LZ, L) C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) -C_O0_I3(LZ, L, L) -C_O0_I3(LZ, LZ, L) -C_O0_I4(LZ, LZ, L, L) C_O0_I4(rZ, rZ, rZ, rZ) C_O1_I1(r, L) C_O1_I1(r, r) -C_O1_I2(r, L, L) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) C_O1_I2(r, rZ, rN) C_O1_I2(r, rZ, rZ) C_O1_I4(r, rZ, rZ, rZ, rZ) -C_O2_I1(r, r, L) -C_O2_I2(r, r, L, L) C_O2_I4(r, r, rZ, rZ, rM, rM) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 0deb33701f..dddf2486c1 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -25,11 +25,14 @@ #ifndef RISCV_TCG_TARGET_H #define RISCV_TCG_TARGET_H =20 -#if __riscv_xlen =3D=3D 32 -# define TCG_TARGET_REG_BITS 32 -#elif __riscv_xlen =3D=3D 64 -# define TCG_TARGET_REG_BITS 64 +/* + * We don't support oversize guests. + * Since we will only build tcg once, this in turn requires a 64-bit host. + */ +#if __riscv_xlen !=3D 64 +#error "unsupported code generation mode" #endif +#define TCG_TARGET_REG_BITS 64 =20 #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 20 @@ -83,13 +86,8 @@ typedef enum { #define TCG_TARGET_STACK_ALIGN 16 #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL -#if TCG_TARGET_REG_BITS =3D=3D 32 -#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN -#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN -#else #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL -#endif #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 /* optional instructions */ @@ -106,8 +104,8 @@ typedef enum { #define TCG_TARGET_HAS_sub2_i32 1 #define TCG_TARGET_HAS_mulu2_i32 0 #define TCG_TARGET_HAS_muls2_i32 0 -#define TCG_TARGET_HAS_muluh_i32 (TCG_TARGET_REG_BITS =3D=3D 32) -#define TCG_TARGET_HAS_mulsh_i32 (TCG_TARGET_REG_BITS =3D=3D 32) +#define TCG_TARGET_HAS_muluh_i32 0 +#define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_ext8s_i32 1 #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 1 @@ -128,7 +126,6 @@ typedef enum { #define TCG_TARGET_HAS_setcond2 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 #define TCG_TARGET_HAS_movcond_i64 0 #define TCG_TARGET_HAS_div_i64 1 #define TCG_TARGET_HAS_rem_i64 1 @@ -165,7 +162,6 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 -#endif =20 #define TCG_TARGET_DEFAULT_MO (0) =20 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 266fe1433d..1edc3b1c4d 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -137,15 +137,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKi= nd kind, int slot) #define SOFTMMU_RESERVE_REGS 0 #endif =20 - -static inline tcg_target_long sextreg(tcg_target_long val, int pos, int le= n) -{ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - return sextract32(val, pos, len); - } else { - return sextract64(val, pos, len); - } -} +#define sextreg sextract64 =20 /* test if a constant matches the constraint */ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) @@ -235,7 +227,6 @@ typedef enum { OPC_XOR =3D 0x4033, OPC_XORI =3D 0x4013, =20 -#if TCG_TARGET_REG_BITS =3D=3D 64 OPC_ADDIW =3D 0x1b, OPC_ADDW =3D 0x3b, OPC_DIVUW =3D 0x200503b, @@ -250,23 +241,6 @@ typedef enum { OPC_SRLIW =3D 0x501b, OPC_SRLW =3D 0x503b, OPC_SUBW =3D 0x4000003b, -#else - /* Simplify code throughout by defining aliases for RV32. */ - OPC_ADDIW =3D OPC_ADDI, - OPC_ADDW =3D OPC_ADD, - OPC_DIVUW =3D OPC_DIVU, - OPC_DIVW =3D OPC_DIV, - OPC_MULW =3D OPC_MUL, - OPC_REMUW =3D OPC_REMU, - OPC_REMW =3D OPC_REM, - OPC_SLLIW =3D OPC_SLLI, - OPC_SLLW =3D OPC_SLL, - OPC_SRAIW =3D OPC_SRAI, - OPC_SRAW =3D OPC_SRA, - OPC_SRLIW =3D OPC_SRLI, - OPC_SRLW =3D OPC_SRL, - OPC_SUBW =3D OPC_SUB, -#endif =20 OPC_FENCE =3D 0x0000000f, OPC_NOP =3D OPC_ADDI, /* nop =3D addi r0,r0,0 */ @@ -500,7 +474,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, T= CGReg rd, tcg_target_long lo, hi, tmp; int shift, ret; =20 - if (TCG_TARGET_REG_BITS =3D=3D 64 && type =3D=3D TCG_TYPE_I32) { + if (type =3D=3D TCG_TYPE_I32) { val =3D (int32_t)val; } =20 @@ -511,7 +485,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, T= CGReg rd, } =20 hi =3D val - lo; - if (TCG_TARGET_REG_BITS =3D=3D 32 || val =3D=3D (int32_t)val) { + if (val =3D=3D (int32_t)val) { tcg_out_opc_upper(s, OPC_LUI, rd, hi); if (lo !=3D 0) { tcg_out_opc_imm(s, OPC_ADDIW, rd, rd, lo); @@ -519,7 +493,6 @@ static void tcg_out_movi(TCGContext *s, TCGType type, T= CGReg rd, return; } =20 - /* We can only be here if TCG_TARGET_REG_BITS !=3D 32 */ tmp =3D tcg_pcrel_diff(s, (void *)val); if (tmp =3D=3D (int32_t)tmp) { tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); @@ -668,15 +641,15 @@ static void tcg_out_ldst(TCGContext *s, RISCVInsn opc= , TCGReg data, static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { - bool is32bit =3D (TCG_TARGET_REG_BITS =3D=3D 32 || type =3D=3D TCG_TYP= E_I32); - tcg_out_ldst(s, is32bit ? OPC_LW : OPC_LD, arg, arg1, arg2); + RISCVInsn insn =3D type =3D=3D TCG_TYPE_I32 ? OPC_LW : OPC_LD; + tcg_out_ldst(s, insn, arg, arg1, arg2); } =20 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { - bool is32bit =3D (TCG_TARGET_REG_BITS =3D=3D 32 || type =3D=3D TCG_TYP= E_I32); - tcg_out_ldst(s, is32bit ? OPC_SW : OPC_SD, arg, arg1, arg2); + RISCVInsn insn =3D type =3D=3D TCG_TYPE_I32 ? OPC_SW : OPC_SD; + tcg_out_ldst(s, insn, arg, arg1, arg2); } =20 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, @@ -853,20 +826,18 @@ static void tcg_out_call_int(TCGContext *s, const tcg= _insn_unit *arg, bool tail) if (offset =3D=3D sextreg(offset, 0, 20)) { /* short jump: -2097150 to 2097152 */ tcg_out_opc_jump(s, OPC_JAL, link, offset); - } else if (TCG_TARGET_REG_BITS =3D=3D 32 || offset =3D=3D (int32_t)off= set) { + } else if (offset =3D=3D (int32_t)offset) { /* long jump: -2147483646 to 2147483648 */ tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0); tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0); ret =3D reloc_call(s->code_ptr - 2, arg); tcg_debug_assert(ret =3D=3D true); - } else if (TCG_TARGET_REG_BITS =3D=3D 64) { + } else { /* far jump: 64-bit */ tcg_target_long imm =3D sextreg((tcg_target_long)arg, 0, 12); tcg_target_long base =3D (tcg_target_long)arg - imm; tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base); tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm); - } else { - g_assert_not_reached(); } } =20 @@ -942,9 +913,6 @@ static void * const qemu_st_helpers[MO_SIZE + 1] =3D { #endif }; =20 -/* We don't support oversize guests */ -QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); - /* We expect to use a 12-bit negative offset from ENV. */ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); @@ -956,8 +924,7 @@ static void tcg_out_goto(TCGContext *s, const tcg_insn_= unit *target) tcg_debug_assert(ok); } =20 -static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrl, - TCGReg addrh, MemOpIdx oi, +static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, MemOpIdx oi, tcg_insn_unit **label_ptr, bool is_load) { MemOp opc =3D get_memop(oi); @@ -973,7 +940,7 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg ad= drl, tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs); =20 - tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addrl, + tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); @@ -992,10 +959,10 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg = addrl, /* Clear the non-page, non-alignment bits from the address. */ compare_mask =3D (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - = 1); if (compare_mask =3D=3D sextreg(compare_mask, 0, 12)) { - tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addrl, compare_mask); + tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr, compare_mask); } else { tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); - tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addrl); + tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr); } =20 /* Compare masked address with the TLB entry. */ @@ -1003,29 +970,26 @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg= addrl, tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); =20 /* TLB Hit - translate address using addend. */ - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP0, addrl); - addrl =3D TCG_REG_TMP0; + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_ext32u(s, TCG_REG_TMP0, addr); + addr =3D TCG_REG_TMP0; } - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl); + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addr); return TCG_REG_TMP0; } =20 static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, - TCGType ext, - TCGReg datalo, TCGReg datahi, - TCGReg addrlo, TCGReg addrhi, - void *raddr, tcg_insn_unit **label_ptr) + TCGType data_type, TCGReg data_reg, + TCGReg addr_reg, void *raddr, + tcg_insn_unit **label_ptr) { TCGLabelQemuLdst *label =3D new_ldst_label(s); =20 label->is_ld =3D is_ld; label->oi =3D oi; - label->type =3D ext; - label->datalo_reg =3D datalo; - label->datahi_reg =3D datahi; - label->addrlo_reg =3D addrlo; - label->addrhi_reg =3D addrhi; + label->type =3D data_type; + label->datalo_reg =3D data_reg; + label->addrlo_reg =3D addr_reg; label->raddr =3D tcg_splitwx_to_rx(raddr); label->label_ptr[0] =3D label_ptr[0]; } @@ -1039,11 +1003,6 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) TCGReg a2 =3D tcg_target_call_iarg_regs[2]; TCGReg a3 =3D tcg_target_call_iarg_regs[3]; =20 - /* We don't support oversize guests */ - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - g_assert_not_reached(); - } - /* resolve label address */ if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; @@ -1073,11 +1032,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) TCGReg a3 =3D tcg_target_call_iarg_regs[3]; TCGReg a4 =3D tcg_target_call_iarg_regs[4]; =20 - /* We don't support oversize guests */ - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - g_assert_not_reached(); - } - /* resolve label address */ if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; @@ -1146,7 +1100,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) =20 #endif /* CONFIG_SOFTMMU */ =20 -static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, +static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val, TCGReg base, MemOp opc, bool is_64) { /* Byte swapping is left to middle-end expansion. */ @@ -1154,37 +1108,28 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg lo, TCGReg hi, =20 switch (opc & (MO_SSIZE)) { case MO_UB: - tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); + tcg_out_opc_imm(s, OPC_LBU, val, base, 0); break; case MO_SB: - tcg_out_opc_imm(s, OPC_LB, lo, base, 0); + tcg_out_opc_imm(s, OPC_LB, val, base, 0); break; case MO_UW: - tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); + tcg_out_opc_imm(s, OPC_LHU, val, base, 0); break; case MO_SW: - tcg_out_opc_imm(s, OPC_LH, lo, base, 0); + tcg_out_opc_imm(s, OPC_LH, val, base, 0); break; case MO_UL: - if (TCG_TARGET_REG_BITS =3D=3D 64 && is_64) { - tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); + if (is_64) { + tcg_out_opc_imm(s, OPC_LWU, val, base, 0); break; } /* FALLTHRU */ case MO_SL: - tcg_out_opc_imm(s, OPC_LW, lo, base, 0); + tcg_out_opc_imm(s, OPC_LW, val, base, 0); break; case MO_UQ: - /* Prefer to load from offset 0 first, but allow for overlap. */ - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_opc_imm(s, OPC_LD, lo, base, 0); - } else if (lo !=3D base) { - tcg_out_opc_imm(s, OPC_LW, lo, base, 0); - tcg_out_opc_imm(s, OPC_LW, hi, base, 4); - } else { - tcg_out_opc_imm(s, OPC_LW, hi, base, 4); - tcg_out_opc_imm(s, OPC_LW, lo, base, 0); - } + tcg_out_opc_imm(s, OPC_LD, val, base, 0); break; default: g_assert_not_reached(); @@ -1193,8 +1138,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, =20 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) { - TCGReg addr_regl, addr_regh __attribute__((unused)); - TCGReg data_regl, data_regh; + TCGReg addr_reg, data_reg; MemOpIdx oi; MemOp opc; #if defined(CONFIG_SOFTMMU) @@ -1204,27 +1148,23 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is_64) #endif TCGReg base; =20 - data_regl =3D *args++; - data_regh =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); - addr_regl =3D *args++; - addr_regh =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); + data_reg =3D *args++; + addr_reg =3D *args++; oi =3D *args++; opc =3D get_memop(oi); =20 #if defined(CONFIG_SOFTMMU) - base =3D tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1); - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); - add_qemu_ldst_label(s, 1, oi, - (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_regl, data_regh, addr_regl, addr_regh, - s->code_ptr, label_ptr); + base =3D tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1); + tcg_out_qemu_ld_direct(s, data_reg, base, opc, is_64); + add_qemu_ldst_label(s, 1, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), + data_reg, addr_reg, s->code_ptr, label_ptr); #else a_bits =3D get_alignment_bits(opc); if (a_bits) { - tcg_out_test_alignment(s, true, addr_regl, a_bits); + tcg_out_test_alignment(s, true, addr_reg, a_bits); } - base =3D addr_regl; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + base =3D addr_reg; + if (TARGET_LONG_BITS =3D=3D 32) { tcg_out_ext32u(s, TCG_REG_TMP0, base); base =3D TCG_REG_TMP0; } @@ -1232,11 +1172,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is_64) tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base= ); base =3D TCG_REG_TMP0; } - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + tcg_out_qemu_ld_direct(s, data_reg, base, opc, is_64); #endif } =20 -static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, +static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg val, TCGReg base, MemOp opc) { /* Byte swapping is left to middle-end expansion. */ @@ -1244,21 +1184,16 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg lo, TCGReg hi, =20 switch (opc & (MO_SSIZE)) { case MO_8: - tcg_out_opc_store(s, OPC_SB, base, lo, 0); + tcg_out_opc_store(s, OPC_SB, base, val, 0); break; case MO_16: - tcg_out_opc_store(s, OPC_SH, base, lo, 0); + tcg_out_opc_store(s, OPC_SH, base, val, 0); break; case MO_32: - tcg_out_opc_store(s, OPC_SW, base, lo, 0); + tcg_out_opc_store(s, OPC_SW, base, val, 0); break; case MO_64: - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_out_opc_store(s, OPC_SD, base, lo, 0); - } else { - tcg_out_opc_store(s, OPC_SW, base, lo, 0); - tcg_out_opc_store(s, OPC_SW, base, hi, 4); - } + tcg_out_opc_store(s, OPC_SD, base, val, 0); break; default: g_assert_not_reached(); @@ -1267,8 +1202,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= Reg lo, TCGReg hi, =20 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) { - TCGReg addr_regl, addr_regh __attribute__((unused)); - TCGReg data_regl, data_regh; + TCGReg addr_reg, data_reg; MemOpIdx oi; MemOp opc; #if defined(CONFIG_SOFTMMU) @@ -1278,27 +1212,23 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg *args, bool is_64) #endif TCGReg base; =20 - data_regl =3D *args++; - data_regh =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); - addr_regl =3D *args++; - addr_regh =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); + data_reg =3D *args++; + addr_reg =3D *args++; oi =3D *args++; opc =3D get_memop(oi); =20 #if defined(CONFIG_SOFTMMU) - base =3D tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0); - tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); - add_qemu_ldst_label(s, 0, oi, - (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_regl, data_regh, addr_regl, addr_regh, - s->code_ptr, label_ptr); + base =3D tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0); + tcg_out_qemu_st_direct(s, data_reg, base, opc); + add_qemu_ldst_label(s, 0, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), + data_reg, addr_reg, s->code_ptr, label_ptr); #else a_bits =3D get_alignment_bits(opc); if (a_bits) { - tcg_out_test_alignment(s, false, addr_regl, a_bits); + tcg_out_test_alignment(s, false, addr_reg, a_bits); } - base =3D addr_regl; - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + base =3D addr_reg; + if (TARGET_LONG_BITS =3D=3D 32) { tcg_out_ext32u(s, TCG_REG_TMP0, base); base =3D TCG_REG_TMP0; } @@ -1306,7 +1236,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base= ); base =3D TCG_REG_TMP0; } - tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + tcg_out_qemu_st_direct(s, data_reg, base, opc); #endif } =20 @@ -1755,19 +1685,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) return C_O1_I4(r, rZ, rZ, rZ, rZ); =20 case INDEX_op_qemu_ld_i32: - return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS - ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); - case INDEX_op_qemu_st_i32: - return (TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS - ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L)); case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O2_I1(r, r,= L) - : C_O2_I2(r, r, L, L)); + return C_O1_I1(r, L); + case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(LZ, L) - : TARGET_LONG_BITS <=3D TCG_TARGET_REG_BITS ? C_O0_I3(LZ, L= Z, L) - : C_O0_I4(LZ, LZ, L, L)); + return C_O0_I2(LZ, L); =20 default: g_assert_not_reached(); @@ -1843,9 +1765,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) static void tcg_target_init(TCGContext *s) { tcg_target_available_regs[TCG_TYPE_I32] =3D 0xffffffff; - if (TCG_TARGET_REG_BITS =3D=3D 64) { - tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffff; - } + tcg_target_available_regs[TCG_TYPE_I64] =3D 0xffffffff; =20 tcg_target_call_clobber_regs =3D -1u; tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922035; cv=none; d=zohomail.com; s=zohoarc; b=g8dv2yRQfaZAqHzTZQQprGosbZ5WkUgVvlSQ7vKL1OZVIYwR0PoRXVRdbW8SakSDEJTAepyHNj7ISTS9ZaHe8eVLFaqK+xqvRLNh4SVEx1kXTGySbaeeteDfnSMB8Jl+QDnAzo2NWm6fkYOo1m0Y5HejvdaDbLeIjsllOuGQsjc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680922035; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=itgWaBLjY7YmpUAGU9DqCqqdDqlcaLKLhIh9EK1HPyA=; b=hsorD2XLSNRlZkXvX9mC57MVPkD82XFJKcjytxKYjfec+ZB1OsytOOJDMKp3PQE0JKfB+355jrKGDjNWurb6cPes6wFWCRLuKiVoG5SG609wCEyqACUAUe62v8HJBcWhLh59hrqg0eaPlGiDDuE0+x9M3ua759sA/QXVrtkkMbo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680922035878204.21459439264436; Fri, 7 Apr 2023 19:47:15 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyYo-00081r-3N; Fri, 07 Apr 2023 22:44:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyYm-0007yM-Aj for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:12 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyYH-0005af-Ti for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:11 -0400 Received: by mail-pj1-x1033.google.com with SMTP id pc4-20020a17090b3b8400b0024676052044so338489pjb.1 for ; Fri, 07 Apr 2023 19:43:41 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921821; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=itgWaBLjY7YmpUAGU9DqCqqdDqlcaLKLhIh9EK1HPyA=; b=A3m5gDP/fp4WQcYuGjaskJmDlmST40OikRcTFfrXBJDwXgP+Mifv7W0SrS20Zp1lfz X533Rlb81tvnqhLi9nEKrRPrJaGwdqbe/xJtpNbMJmye6rM4IZQc8jZ47H1Gu7kl0UuH vzKKOkC9nW8MIZTPmd3wy3bArqPOINnJhG909AqSE6PiPlz+XJTF9/AAWOm525pKTQd9 2ykyfK9FDgjRyE2NdZdmJUs/yI+Bu81mdpjYLwWVq7UEdTD8cDgXRhPKs6n7sZLC5tGF qeTIc9qAHGpdeTFWNJvSAKIlHbEMZ6taZgnDdwHvhiY0kvpt10uuC9Ym2vrdJ1cmCb3p ABhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921821; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=itgWaBLjY7YmpUAGU9DqCqqdDqlcaLKLhIh9EK1HPyA=; b=e+b8gv0C7oo2Y2SfA+MIJot24CZ81dp29PSGFfCU749HcK58oxDDbVGoLiu3aF3m/Q zjQ00HRTcAwVjUq/PrySK5HRKpR3b7JQHrCE7sXwGSWfniim7wIZtmcJ0Y324oSFMUW3 3nLVwJ8wFD7GjbFDigcHit7pejbEYietRC/o/NghXZiqmTH2+wOhBkXZZW+APByZZyrJ QmM8ak2JfKWDF68G+ajr1btdlsaA/1th7SgvZ9uv51PWAsCkQ9VfDlcaxceUhw9PcYgq Sykn4g7zh8QNn3objlBP2znoMlYjJZdbVOl5jtvPv+kPjFSLqdIv/JQn74364AxqDVwl VKXw== X-Gm-Message-State: AAQBX9fcmnpyIQloDlH9W7q+kufbMbGXTozDL8awMyTcKFUzlEdnpVKY tctXPZfftchU31nidDC9KwMahDBM1//WKM4oxCM= X-Google-Smtp-Source: AKy350bgsRM2mC8eWd97WrYw8nAhZdo2tY47fh7azTjIBl0VEsIr/RI98ss7WNm4zEzf5tMZkTPUbQ== X-Received: by 2002:a17:902:d50c:b0:1a5:254b:e85b with SMTP id b12-20020a170902d50c00b001a5254be85bmr1464760plg.34.1680921821117; Fri, 07 Apr 2023 19:43:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 28/42] tcg/riscv: Expand arguments to tcg_out_qemu_{ld,st} Date: Fri, 7 Apr 2023 19:43:00 -0700 Message-Id: <20230408024314.3357414-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922037690100003 Content-Type: text/plain; charset="utf-8" Now that the host is always 64-bit, the address and data operands are always one operand each. In addition, change to using TCGType to describe the data operand. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 47 +++++++++++++++----------------------- 1 file changed, 18 insertions(+), 29 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 1edc3b1c4d..6059802d9a 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1101,7 +1101,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) #endif /* CONFIG_SOFTMMU */ =20 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val, - TCGReg base, MemOp opc, bool is_64) + TCGReg base, MemOp opc, TCGType type) { /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((opc & MO_BSWAP) =3D=3D 0); @@ -1120,7 +1120,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= Reg val, tcg_out_opc_imm(s, OPC_LH, val, base, 0); break; case MO_UL: - if (is_64) { + if (type =3D=3D TCG_TYPE_I64) { tcg_out_opc_imm(s, OPC_LWU, val, base, 0); break; } @@ -1136,11 +1136,10 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGReg val, } } =20 -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, + MemOpIdx oi, TCGType d_type) { - TCGReg addr_reg, data_reg; - MemOpIdx oi; - MemOp opc; + MemOp opc =3D get_memop(oi); #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[1]; #else @@ -1148,16 +1147,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is_64) #endif TCGReg base; =20 - data_reg =3D *args++; - addr_reg =3D *args++; - oi =3D *args++; - opc =3D get_memop(oi); - #if defined(CONFIG_SOFTMMU) base =3D tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1); - tcg_out_qemu_ld_direct(s, data_reg, base, opc, is_64); - add_qemu_ldst_label(s, 1, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_reg, addr_reg, s->code_ptr, label_ptr); + tcg_out_qemu_ld_direct(s, data_reg, base, opc, d_type); + add_qemu_ldst_label(s, true, oi, d_type, data_reg, addr_reg, + s->code_ptr, label_ptr); #else a_bits =3D get_alignment_bits(opc); if (a_bits) { @@ -1172,7 +1166,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base= ); base =3D TCG_REG_TMP0; } - tcg_out_qemu_ld_direct(s, data_reg, base, opc, is_64); + tcg_out_qemu_ld_direct(s, data_reg, base, opc, d_type); #endif } =20 @@ -1200,11 +1194,10 @@ static void tcg_out_qemu_st_direct(TCGContext *s, T= CGReg val, } } =20 -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, + MemOpIdx oi, TCGType d_type) { - TCGReg addr_reg, data_reg; - MemOpIdx oi; - MemOp opc; + MemOp opc =3D get_memop(oi); #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[1]; #else @@ -1212,16 +1205,12 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg *args, bool is_64) #endif TCGReg base; =20 - data_reg =3D *args++; - addr_reg =3D *args++; - oi =3D *args++; - opc =3D get_memop(oi); =20 #if defined(CONFIG_SOFTMMU) base =3D tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0); tcg_out_qemu_st_direct(s, data_reg, base, opc); - add_qemu_ldst_label(s, 0, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - data_reg, addr_reg, s->code_ptr, label_ptr); + add_qemu_ldst_label(s, false, oi, d_type, data_reg, addr_reg, + s->code_ptr, label_ptr); #else a_bits =3D get_alignment_bits(opc); if (a_bits) { @@ -1528,16 +1517,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, false); + tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, true); + tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); break; case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, false); + tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, true); + tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); break; =20 case INDEX_op_extrh_i64_i32: --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922188; cv=none; d=zohomail.com; s=zohoarc; b=XKbCb48SOJsxTfSg3Y62mRixgdWQzEMdj7+/V0B1mAbbX/eXgzUaM7lpiYWmPbnTsBt76JzfhkYsUYY6hMtyAo5OU5C85Uvl8q3jpHl5aWl+K8edhrsWE3YxTD4caVAPLbsVkqV7o9aZECNH42zduxQ1G/uD+GvWtbTcqR7I4b4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680922188; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xHwCzrWrjIn4aTCJiRqtc9aUATfCI30+ZXph55J2XuY=; b=F3+AHGZOfSwww8qYyDhkhQN4igHo//sY6sRW4KhtYxBctc71lOGIOc5jTf7+ZOECew12ukWLcLapGss0U2cyy378y5XyQaB9WSUUJ2Lhpt3lKmp/MaRIUTXs6xWff/D4m+NNjm2iFQ4OVWDH5wpl+STrAE6P17fGc9SJHXVb8Pk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168092218832486.96245420784555; Fri, 7 Apr 2023 19:49:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyYr-00086e-GB; Fri, 07 Apr 2023 22:44:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyYo-00082C-5I for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:14 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyYI-0005XC-Ue for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:13 -0400 Received: by mail-pj1-x102d.google.com with SMTP id d22-20020a17090a111600b0023d1b009f52so2769605pja.2 for ; Fri, 07 Apr 2023 19:43:42 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921822; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xHwCzrWrjIn4aTCJiRqtc9aUATfCI30+ZXph55J2XuY=; b=rbnmPVRIZ/bZxKYCnI476FDVMdNONDO7jTioSCjCKdJ0qeyAni86VwohJFRA0hQDTt 0LqUVAU/D1w1llI4kDOCpzVFY+4MBG0/GfUOwJjby66QEW2gO8n38lYNZlYKeAk8ESHB MSpogYUzah64ec4zyrf5NgWHVTP8xjBN3BV+xKIfBEx9QXHXWWQZOf1Q+BLIk+lu4O0T HtcEGWcjiDXf99mcD43kl/5IyEf51XD4OdcrBrMGES45B04Yg5IJ0fyCOisjNwbyLKHk UPzU6yCbRVsCZBaa0X5vldrp93ygfpWpf5YV23KnQOPq7p5MHYA8TnfPbqASdXOsn/sQ HQWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921822; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xHwCzrWrjIn4aTCJiRqtc9aUATfCI30+ZXph55J2XuY=; b=rGRGaLLu04hcM2zire7Y1VIpoHZ+yzAi+sItZHlhjICshQ540m5VeNFWG0/8RQZ94y 9fvkB31dlTpci7JbpmU7YUEJbnio46lA3WCc8Z8XloZbwD8+8QUHfF+GaXypDYtbrVAa eoRCeoraGu3tJsSGd9y6dXt+T6lkkgWmfsqmVB7XQI6QW7BrWv1SHFMIUM6lG5iYLmsv bTD8jyERCOqXs3mM08TOC+qzVqboDTP93l+OSQ/bStFyhoAJUkpddvdspbHTZBcv3EAT gvszd2pXk/vJiHF1fv3/MCndzfn2uD/FZF+k+Z18cGD2YXf0vSWrDDam6vdMjezmhJdP fbKA== X-Gm-Message-State: AAQBX9eX1fc0BkxTBrIsc73zdm8uUuIe4e9IQaQ2z6/nXglCcfjj1m1+ d+F/bTyv6Fr7u9XpzyPS5QQDDIEY6AEVnNgZGXk= X-Google-Smtp-Source: AKy350YoEmvWjfZsr2qAU0aeuUZSJm3mdDlzZ5ZULk+3EMlIEIFmDgGaLAPWqKA53WxDF33bPxav2A== X-Received: by 2002:a17:903:2347:b0:1a2:a298:6f65 with SMTP id c7-20020a170903234700b001a2a2986f65mr5875721plh.2.1680921822089; Fri, 07 Apr 2023 19:43:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 29/42] tcg: Move TCGLabelQemuLdst to tcg.c Date: Fri, 7 Apr 2023 19:43:01 -0700 Message-Id: <20230408024314.3357414-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922190353100015 Content-Type: text/plain; charset="utf-8" This will shortly be used by sparc64 without also using TCG_TARGET_NEED_LDST_LABELS. Signed-off-by: Richard Henderson --- tcg/tcg.c | 13 +++++++++++++ tcg/tcg-ldst.c.inc | 14 -------------- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 1c11f15bce..647af6c210 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -94,6 +94,19 @@ typedef struct QEMU_PACKED { DebugFrameFDEHeader fde; } DebugFrameHeader; =20 +typedef struct TCGLabelQemuLdst { + bool is_ld; /* qemu_ld: true, qemu_st: false */ + MemOpIdx oi; + TCGType type; /* result type of a load */ + TCGReg addrlo_reg; /* reg index for low word of guest virtual add= r */ + TCGReg addrhi_reg; /* reg index for high word of guest virtual ad= dr */ + TCGReg datalo_reg; /* reg index for low word to be loaded or stor= ed */ + TCGReg datahi_reg; /* reg index for high word to be loaded or sto= red */ + const tcg_insn_unit *raddr; /* addr of the next IR of qemu_ld/st IR = */ + tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */ + QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next; +} TCGLabelQemuLdst; + static void tcg_register_jit_int(const void *buf, size_t size, const void *debug_frame, size_t debug_frame_size) diff --git a/tcg/tcg-ldst.c.inc b/tcg/tcg-ldst.c.inc index 403cbb0f06..ffada04af0 100644 --- a/tcg/tcg-ldst.c.inc +++ b/tcg/tcg-ldst.c.inc @@ -20,20 +20,6 @@ * THE SOFTWARE. */ =20 -typedef struct TCGLabelQemuLdst { - bool is_ld; /* qemu_ld: true, qemu_st: false */ - MemOpIdx oi; - TCGType type; /* result type of a load */ - TCGReg addrlo_reg; /* reg index for low word of guest virtual add= r */ - TCGReg addrhi_reg; /* reg index for high word of guest virtual ad= dr */ - TCGReg datalo_reg; /* reg index for low word to be loaded or stor= ed */ - TCGReg datahi_reg; /* reg index for high word to be loaded or sto= red */ - const tcg_insn_unit *raddr; /* addr of the next IR of qemu_ld/st IR = */ - tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */ - QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next; -} TCGLabelQemuLdst; - - /* * Generate TB finalization at the end of block */ --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680921978; cv=none; d=zohomail.com; s=zohoarc; b=IQhCg5EmZNa+wkLhgnNooKGJRXWryGNaLXKAjbLK0vBS9RBrOiHj0lxef+w4lcH/mAhN/+3VL55pEMHMdwUGAci+OCAv7JOJsn2vtCEupXBmI/LE7piDd1b6+oe9N83tRh+P8kWBPm18JUPgCks3oRkVp9Xw5hlvdI5EHprwhVI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680921978; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Fikhi3gCqQLepVdiebyP4Nz6/eKR4M1XIM/mRlVy6L8=; b=kS/fS7Pt7DZ3r5opUn9ILTzyu6FqiMahJlxtOj8rHwMliHzWvOhtzshqGKt1pDq01jKvuJap0pAaGrdSUPWApad1M0UNpvBCn3WrtcxOg/w8cM7ZeIJnkdJueyIrqEmYAs0WFglczl4dQlsTLeBYndSLEJFTu0QwrVjEKHfc/Sc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680921978451387.0979854928895; Fri, 7 Apr 2023 19:46:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyZM-0000ct-CS; Fri, 07 Apr 2023 22:44:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyYy-0008B0-F6 for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:24 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyYK-0005p5-Si for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:23 -0400 Received: by mail-pl1-x631.google.com with SMTP id ke16so306421plb.6 for ; Fri, 07 Apr 2023 19:43:44 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921823; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Fikhi3gCqQLepVdiebyP4Nz6/eKR4M1XIM/mRlVy6L8=; b=rBpKPWh12q7OkfZ/f6EzwLY2eKAnj3ljIlA3CrInsoUnncfeoyP1HPAn903Wy5dZzG ZmaNptL02yqjvM9laaTgp4B+mF62TwBKOPGWwZdlWB9ctHnZHt2iZwk7MdASj6w/qwRG EWkMEy24UvIDnjL87Nb627aRN5INtk/gEpIADGf+hpKSRQjzVgUtVtvUvfIZv3occAmP r2Z33IIal80UNgd352Hs5x5mvGlQS0VM+XpRcJUyYpfRzf2+raLf5MXMWBvUGe5oJtfL qLTaIsG+Dhux5aIEbkkRA7Xkpon81x3BPeGKxP52TJJsOTX+2K76EC7KXGPVzFBE1CSl K5tQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921823; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Fikhi3gCqQLepVdiebyP4Nz6/eKR4M1XIM/mRlVy6L8=; b=LrP1iOOcyjeT2Uo8iL4vbADZ+shC3rubRP/jelMuAVCLD7VU0WUW2bJ9T/+eHZJiBv hgy+mKOZQWKHgiuBusgwSsfZeqd4M+AlIcH/XOIqhncX9vQ+tGgFLo87wjN30RMdnFqa x9FuYiQuzD1/9eRiSR2GlpRqiA4IKL5wLTSCSntMxvmwojFbUHwNYSmFgfvkK//9S3LT KRGJlLVKDpe9NUgiCGf1QqFinFJxYrSkeV845EK1EgM/VhZ0wTubWuScJ3dWJhYhd9oQ ryXctAL19+oJpeaOO4XEwPayDVXg6Wuh5hHWgeoYdeEmWj8iaLt9wKo7430dcLLjds3w KEdA== X-Gm-Message-State: AAQBX9czIQqZJ+M3ZG5Hd9vndx+II1WjbRDJNIGj8EQNFyJ8RwH5c9Wt 88C8Zyw2DwRHx+/y9X5XZOxxGGFsYnbkjskyJ/w= X-Google-Smtp-Source: AKy350a1118tnW4EXtTLNmh0WUK/Rka8gm9KpG1abJn6VpVg6vur8c4DFCxwptIr2x9SbMvcqg5HoQ== X-Received: by 2002:a17:902:c94e:b0:19e:8267:9590 with SMTP id i14-20020a170902c94e00b0019e82679590mr5906808pla.41.1680921823161; Fri, 07 Apr 2023 19:43:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 30/42] tcg: Introduce tcg_out_ld_helper_args Date: Fri, 7 Apr 2023 19:43:02 -0700 Message-Id: <20230408024314.3357414-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680921980238100007 Content-Type: text/plain; charset="utf-8" Centralize the logic to call the helper_ldN_mmu functions. This loses out slightly on mips by not filling the delay slot, but the result is more maintainable. Signed-off-by: Richard Henderson --- tcg/tcg.c | 187 +++++++++++++++++++++++++++++++ tcg/aarch64/tcg-target.c.inc | 8 +- tcg/arm/tcg-target.c.inc | 13 +-- tcg/i386/tcg-target.c.inc | 30 +---- tcg/loongarch64/tcg-target.c.inc | 12 +- tcg/mips/tcg-target.c.inc | 15 +-- tcg/ppc/tcg-target.c.inc | 41 +++---- tcg/riscv/tcg-target.c.inc | 15 +-- tcg/s390x/tcg-target.c.inc | 14 +-- 9 files changed, 220 insertions(+), 115 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 647af6c210..e67b80aeeb 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -180,6 +180,10 @@ static bool tcg_target_const_match(int64_t val, TCGTyp= e type, int ct); #ifdef TCG_TARGET_NEED_LDST_LABELS static int tcg_out_ldst_finalize(TCGContext *s); #endif +static int tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *l, + void (*ra_gen)(TCGContext *s, TCGReg r), + int ra_reg, int scratch_reg) + __attribute__((unused)); =20 TCGContext tcg_init_ctx; __thread TCGContext *tcg_ctx; @@ -4973,6 +4977,189 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp= *op) } } =20 +/* Wrapper to prevent -Wtype-limits errors for i386, where ARRAY_SIZE =3D= =3D 0. */ +static inline bool in_iarg_reg(unsigned arg) +{ + unsigned max =3D ARRAY_SIZE(tcg_target_call_iarg_regs); + return max !=3D 0 && arg < max; +} + +static void tcg_out_helper_arg(TCGContext *s, TCGType d_type, unsigned d_a= rg, + TCGType s_type, MemOp s_mo, TCGReg s_reg, + int scratch_reg) +{ + if (TCG_TARGET_CALL_ARG_I32 =3D=3D TCG_CALL_ARG_EXTEND) { + d_type =3D TCG_TYPE_REG; + } + + if (in_iarg_reg(d_arg)) { + tcg_out_movext(s, d_type, tcg_target_call_iarg_regs[d_arg], + s_type, s_mo, s_reg); + return; + } + + /* The argument is going onto the stack; extend into scratch. */ + if ((s_mo & MO_SIZE) < (d_type =3D=3D TCG_TYPE_I32 ? MO_32 : MO_64)) { + tcg_debug_assert(scratch_reg >=3D 0); + tcg_out_movext(s, d_type, scratch_reg, s_type, s_mo, s_reg); + s_reg =3D scratch_reg; + } + tcg_out_st(s, TCG_TYPE_REG, s_reg, TCG_REG_CALL_STACK, + TCG_TARGET_CALL_STACK_OFFSET + + d_arg * sizeof(tcg_target_long)); +} + +static void tcg_out_helper_arg_im(TCGContext *s, TCGType d_type, + unsigned d_arg, tcg_target_long imm, + int scratch_reg) +{ + intptr_t ofs; + + if (TCG_TARGET_CALL_ARG_I32 =3D=3D TCG_CALL_ARG_EXTEND) { + d_type =3D TCG_TYPE_REG; + } + if (in_iarg_reg(d_arg)) { + tcg_out_movi(s, d_type, tcg_target_call_iarg_regs[d_arg], imm); + return; + } + + ofs =3D TCG_TARGET_CALL_STACK_OFFSET + d_arg * sizeof(tcg_target_long); + if (tcg_out_sti(s, TCG_TYPE_REG, imm, TCG_REG_CALL_STACK, ofs)) { + return; + } + + tcg_debug_assert(scratch_reg >=3D 0); + tcg_out_movi(s, d_type, scratch_reg, imm); + tcg_out_st(s, TCG_TYPE_REG, scratch_reg, TCG_REG_CALL_STACK, ofs); +} + +static int tcg_out_helper_arg_ra(TCGContext *s, unsigned d_arg, + void (*ra_gen)(TCGContext *s, TCGReg r), + int ra_reg, uintptr_t ra_imm, + int scratch_reg) +{ + intptr_t ofs; + + if (in_iarg_reg(d_arg)) { + TCGReg d_reg =3D tcg_target_call_iarg_regs[d_arg]; + + if (ra_reg >=3D 0) { + tcg_out_mov(s, TCG_TYPE_PTR, d_reg, ra_reg); + } else if (ra_gen) { + ra_gen(s, d_reg); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, d_reg, ra_imm); + } + return d_reg; + } + + ofs =3D TCG_TARGET_CALL_STACK_OFFSET + d_arg * sizeof(tcg_target_long); + if (ra_reg < 0) { + if (ra_gen) { + tcg_debug_assert(scratch_reg >=3D 0); + ra_gen(s, scratch_reg); + } else if (scratch_reg >=3D 0) { + tcg_out_movi(s, TCG_TYPE_PTR, scratch_reg, ra_imm); + } else { + bool ok =3D tcg_out_sti(s, TCG_TYPE_REG, ra_imm, + TCG_REG_CALL_STACK, ofs); + tcg_debug_assert(ok); + return -1; + } + ra_reg =3D scratch_reg; + } + tcg_out_st(s, TCG_TYPE_REG, ra_reg, TCG_REG_CALL_STACK, ofs); + return ra_reg; +} + +/* + * Poor man's topological sort on 2 source+destination register pairs. + * This is a simplified version of tcg_out_movext2 for 32-bit hosts. + */ +static void tcg_out_mov_32x2(TCGContext *s, TCGReg d1, TCGReg s1, + TCGReg d2, TCGReg s2, int t1) +{ + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); + + if (d1 !=3D s2) { + tcg_out_mov(s, TCG_TYPE_I32, d1, s1); + tcg_out_mov(s, TCG_TYPE_I32, d2, s2); + return; + } + if (d2 =3D=3D s1) { + if (tcg_out_xchg(s, TCG_TYPE_I32, d1, d2)) { + return; + } + tcg_debug_assert(t1 >=3D 0); + tcg_out_mov(s, TCG_TYPE_I32, t1, s1); + s1 =3D t1; + } + tcg_out_mov(s, TCG_TYPE_I32, d2, s2); + tcg_out_mov(s, TCG_TYPE_I32, d1, s1); +} + +static void tcg_out_helper_arg_32x2(TCGContext *s, unsigned d_arg, + TCGReg lo_reg, TCGReg hi_reg, + int scratch_reg) +{ + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); + + if (in_iarg_reg(d_arg + 1)) { + TCGReg lo_arg =3D tcg_target_call_iarg_regs[d_arg + HOST_BIG_ENDIA= N]; + TCGReg hi_arg =3D tcg_target_call_iarg_regs[d_arg + !HOST_BIG_ENDI= AN]; + + tcg_out_mov_32x2(s, lo_arg, lo_reg, hi_arg, hi_reg, scratch_reg); + return; + } + + /* At present, all 32-bit hosts will not split 64-bit args. */ + tcg_debug_assert(!in_iarg_reg(d_arg)); + + tcg_out_st(s, TCG_TYPE_I32, HOST_BIG_ENDIAN ? hi_reg : lo_reg, + TCG_REG_CALL_STACK, + TCG_TARGET_CALL_STACK_OFFSET + d_arg * 4); + tcg_out_st(s, TCG_TYPE_I32, HOST_BIG_ENDIAN ? lo_reg : hi_reg, + TCG_REG_CALL_STACK, + TCG_TARGET_CALL_STACK_OFFSET + (d_arg + 1) * 4); +} + +static int tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *l, + void (*ra_gen)(TCGContext *s, TCGReg r), + int ra_reg, int scratch_reg) +{ + /* This is the type of the helper_ldX_mmu 'addr' argument. */ + TCGType a_type =3D TARGET_LONG_BITS =3D=3D 32 ? TCG_TYPE_I32 : TCG_TYP= E_I64; + MemOp a_mo =3D TARGET_LONG_BITS =3D=3D 32 ? MO_32 : MO_64; + MemOp p_mo =3D sizeof(void *) =3D=3D 4 ? MO_32 : MO_64; + /* Begin by skipping the env argument. */ + int arg =3D 1; + + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_helper_arg(s, a_type, arg, a_type, a_mo, + l->addrlo_reg, scratch_reg); + arg++; + } else { + if (TCG_TARGET_CALL_ARG_I64 =3D=3D TCG_CALL_ARG_EVEN) { + arg +=3D arg & 1; + } + tcg_out_helper_arg_32x2(s, arg, l->addrlo_reg, l->addrhi_reg, + scratch_reg); + arg +=3D 2; + } + + /* Handle env. */ + tcg_out_helper_arg(s, TCG_TYPE_PTR, 0, + TCG_TYPE_PTR, p_mo, TCG_AREG0, scratch_reg); + + /* Handle oi. */ + tcg_out_helper_arg_im(s, TCG_TYPE_I32, arg, l->oi, scratch_reg); + arg++; + + /* Handle ra. Return any register holding it for use by tail call. */ + return tcg_out_helper_arg_ra(s, arg, ra_gen, ra_reg, + (uintptr_t)l->raddr, scratch_reg); +} + #ifdef CONFIG_PROFILER =20 /* avoid copy/paste errors */ diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index f8d3ef4714..f983900669 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1623,17 +1623,13 @@ static void * const qemu_st_helpers[MO_SIZE + 1] = =3D { =20 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc19(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); - tcg_out_mov(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X1, lb->addrlo_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, oi); - tcg_out_adr(s, TCG_REG_X3, lb->raddr); + tcg_out_ld_helper_args(s, lb, NULL, -1, -1); tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); =20 tcg_out_movext(s, lb->type, lb->datalo_reg, diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 9bf831223a..b187d5b28f 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1547,22 +1547,13 @@ static void add_qemu_ldst_label(TCGContext *s, bool= is_ld, TCGType type, =20 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGReg argreg; - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - argreg =3D tcg_out_arg_reg32(s, TCG_REG_R0, TCG_AREG0); - if (TARGET_LONG_BITS =3D=3D 64) { - argreg =3D tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi= _reg); - } else { - argreg =3D tcg_out_arg_reg32(s, argreg, lb->addrlo_reg); - } - argreg =3D tcg_out_arg_imm32(s, argreg, oi); - argreg =3D tcg_out_arg_reg32(s, argreg, TCG_REG_R14); + tcg_out_ld_helper_args(s, lb, NULL, TCG_REG_R14, TCG_REG_TMP); =20 /* Use the canonical unsigned helpers and minimize icache usage. */ tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE]); diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index ff4062ef54..219dc08690 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1914,8 +1914,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, */ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(l->oi); tcg_insn_unit **label_ptr =3D &l->label_ptr[0]; =20 /* resolve label address */ @@ -1924,32 +1923,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); } =20 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - int ofs =3D 0; - - tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); - ofs +=3D 4; - - tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - } - - tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs); - ofs +=3D 4; - - tcg_out_sti(s, TCG_TYPE_PTR, (uintptr_t)l->raddr, TCG_REG_ESP, ofs= ); - } else { - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); - /* The second argument is already loaded with addrlo. */ - tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], oi); - tcg_out_movi(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[3], - (uintptr_t)l->raddr); - } - + tcg_out_ld_helper_args(s, l, NULL, -1, -1); tcg_out_branch(s, 1, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 0940788c6f..a0ef830179 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -895,9 +895,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_l= d, MemOpIdx oi, =20 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - MemOp size =3D opc & MO_SIZE; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -905,12 +903,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, T= CGLabelQemuLdst *l) } =20 /* call load helper */ - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A1, l->addrlo_reg); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A2, oi); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, (tcg_target_long)l->raddr); - - tcg_out_call_int(s, qemu_ld_helpers[size], false); + tcg_out_ld_helper_args(s, l, NULL, -1, -1); + tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE], false); =20 tcg_out_movext(s, l->type, l->datalo_reg, TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_A0); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 568cfe7728..9723163b97 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1298,10 +1298,8 @@ static void add_qemu_ldst_label(TCGContext *s, int i= s_ld, MemOpIdx oi, static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { const tcg_insn_unit *tgt_rx =3D tcg_splitwx_to_rx(s->code_ptr); - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(l->oi); TCGReg v0; - int i; =20 /* resolve label address */ if (!reloc_pc16(l->label_ptr[0], tgt_rx) @@ -1310,17 +1308,10 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) return false; } =20 - i =3D 1; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - i =3D tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); - } else { - i =3D tcg_out_call_iarg_reg(s, i, l->addrlo_reg); - } - i =3D tcg_out_call_iarg_imm(s, i, oi); - i =3D tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr); + tcg_out_ld_helper_args(s, l, NULL, -1, TCG_TMP0); tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], fals= e); /* delay slot */ - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); + tcg_out_nop(s); =20 v0 =3D l->datalo_reg; if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 7c33404bd6..e54ebde104 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -23,8 +23,6 @@ */ =20 #include "elf.h" -#include "../tcg-pool.c.inc" -#include "../tcg-ldst.c.inc" =20 /* * Standardize on the _CALL_FOO symbols used by GCC: @@ -58,6 +56,9 @@ #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL =20 +#include "../tcg-pool.c.inc" +#include "../tcg-ldst.c.inc" + /* For some memory operations, we need a scratch that isn't R0. For the A= IX calling convention, we can re-use the TOC register since we'll be reloa= ding it at every call. Otherwise R12 will do nicely as neither a call-saved @@ -2136,42 +2137,30 @@ static void add_qemu_ldst_label(TCGContext *s, bool= is_ld, label->label_ptr[0] =3D lptr; } =20 +static void tcg_out_mflr(TCGContext *s, TCGReg dst) +{ + tcg_out32(s, MFSPR | RT(dst) | LR); +} + static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); - TCGReg hi, lo, arg =3D TCG_REG_R3; + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); - - lo =3D lb->addrlo_reg; - hi =3D lb->addrhi_reg; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - arg |=3D (TCG_TARGET_CALL_ARG_I64 =3D=3D TCG_CALL_ARG_EVEN); - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - } else { - /* If the address needed to be zero-extended, we'll have already - placed it in R4. The only remaining case is 64-bit guest. */ - tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); - } - - tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); - tcg_out32(s, MFSPR | RT(arg) | LR); + tcg_out_ld_helper_args(s, lb, tcg_out_mflr, -1, TCG_REG_TMP1); =20 tcg_out_call_int(s, LK, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 - lo =3D lb->datalo_reg; - hi =3D lb->datahi_reg; if (TCG_TARGET_REG_BITS =3D=3D 32 && (opc & MO_SIZE) =3D=3D MO_64) { - tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4); - tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3); + tcg_out_movext2(s, TCG_TYPE_I32, lb->datahi_reg, + TCG_TYPE_I32, MO_UL, TCG_REG_R3, + TCG_TYPE_I32, lb->datalo_reg, + TCG_TYPE_I32, MO_UL, TCG_REG_R4, TCG_REG_TMP1); } else { - tcg_out_movext(s, lb->type, lo, + tcg_out_movext(s, lb->type, lb->datalo_reg, TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_R3); } =20 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 6059802d9a..e643a83d0d 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -996,12 +996,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_= ld, MemOpIdx oi, =20 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - TCGReg a0 =3D tcg_target_call_iarg_regs[0]; - TCGReg a1 =3D tcg_target_call_iarg_regs[1]; - TCGReg a2 =3D tcg_target_call_iarg_regs[2]; - TCGReg a3 =3D tcg_target_call_iarg_regs[3]; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -1009,13 +1004,9 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) } =20 /* call load helper */ - tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); - tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); - tcg_out_movi(s, TCG_TYPE_PTR, a2, oi); - tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr); - + tcg_out_ld_helper_args(s, l, NULL, -1, TCG_REG_TMP0); tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); - tcg_out_mov(s, (opc & MO_SIZE) =3D=3D MO_64, l->datalo_reg, a0); + tcg_out_mov(s, (opc & MO_SIZE) =3D=3D MO_64, l->datalo_reg, TCG_REG_A0= ); =20 tcg_out_goto(s, l->raddr); return true; diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 77dcdd7c0f..a81c771196 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1786,24 +1786,16 @@ static void add_qemu_ldst_label(TCGContext *s, bool= is_ld, MemOpIdx oi, =20 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGReg addr_reg =3D lb->addrlo_reg; - TCGReg data_reg =3D lb->datalo_reg; - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(lb->oi); =20 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg); - } - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, oi); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R5, (uintptr_t)lb->raddr); + tcg_out_ld_helper_args(s, lb, NULL, -1, -1); tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]); - tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R2); + tcg_out_mov(s, TCG_TYPE_I64, lb->datalo_reg, TCG_REG_R2); =20 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); return true; --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921824; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0kMYkgC6gxFnjP17fEzYh5Pm8QnRqJDbIA3PjSDC28Y=; b=Wkp3elV7ApVyCFwy+o08LeWwUh6tdHs3dPllaIfDWnErqoU6hF0aGxVjT196g+NmNm I1pMWjinMMk5d+BP4+l8IenQcon4pk7jzttre3HrVzfFbTFvNBIA8ggXYb1P23Ixe6/h Ng5+B699/IRBRNN+M4IK1A5iDQ0/JAokb15IEi8fXJezPyrsnao7KOwirQ8ejz9XUqWQ uG/OXTcFhnNBGmud1xGfeLVFNR1q1pvbSiQz8sK7SISiE1SQ+TV4GFiqElZoUcLVxtB0 6qFJB/pEbNUgP6nqlrjN5jCtOZlUgUTMIx9EYJuH6vXyfUaqk7eCHlsdX8M3i0RX6AqM +QAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921824; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0kMYkgC6gxFnjP17fEzYh5Pm8QnRqJDbIA3PjSDC28Y=; b=XwbXA5WZ2emeJSdgjIqwG8mLgP1xyrtegmYPo20ZZvlJBFlbUvKO4mhJ5X28m/49Mp v0DOr0HHHU5Ct8jXVyqsWqN8hG93/kM9X0drp5h86AGvEEwdXykmrSXiGMqDDwuC2NHL PwazCaNKZnLiMQrofL8rh4xdYCTKfCk+5gLQstRHuqCqPU6AdGzMUn9IPc6A9n0FqQzu q6uGLMAjXhJbe8e6HX+Im15/rgxabpa6gIHXat9aDBEeNrXwHdvhdCCu49xsMLZKiekU PlDwiTAFkO1NMTlgfPi6wfxlQIu3eyu2NHwBDIh2Nut5SZgDFxtOc3ou9Y3TTnphuTA8 2qzw== X-Gm-Message-State: AAQBX9fGZS5AVGpt3GsjsUGGVfFPIdICsRfu153bcNAjnKS0Zklf6wi5 ALYVnbVAjsIMakApmV+OYorWdR4IMI+9vPNO3dU= X-Google-Smtp-Source: AKy350a4tII6yiAwF+SThikNpbeIFLMkfG1L5mZBdiWue3vhJcJWiQOSqQj1zJyM2xWnjEjna1SsIQ== X-Received: by 2002:a17:90a:198:b0:235:9d0c:6e3f with SMTP id 24-20020a17090a019800b002359d0c6e3fmr4826427pjc.31.1680921824181; Fri, 07 Apr 2023 19:43:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 31/42] tcg: Introduce tcg_out_st_helper_args Date: Fri, 7 Apr 2023 19:43:03 -0700 Message-Id: <20230408024314.3357414-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922013660100003 Content-Type: text/plain; charset="utf-8" Centralize the logic to call the helper_stN_mmu functions. Signed-off-by: Richard Henderson --- tcg/tcg.c | 189 ++++++++++++++++++++++++++++++- tcg/aarch64/tcg-target.c.inc | 24 ++-- tcg/arm/tcg-target.c.inc | 106 ++--------------- tcg/i386/tcg-target.c.inc | 51 +-------- tcg/loongarch64/tcg-target.c.inc | 11 +- tcg/mips/tcg-target.c.inc | 109 ++---------------- tcg/ppc/tcg-target.c.inc | 40 ++----- tcg/riscv/tcg-target.c.inc | 18 +-- tcg/s390x/tcg-target.c.inc | 15 +-- 9 files changed, 229 insertions(+), 334 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index e67b80aeeb..bd6676be69 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -184,6 +184,11 @@ static int tcg_out_ld_helper_args(TCGContext *s, const= TCGLabelQemuLdst *l, void (*ra_gen)(TCGContext *s, TCGReg r), int ra_reg, int scratch_reg) __attribute__((unused)); +static int tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *l, + void (*ra_gen)(TCGContext *s, TCGReg r), + int ra_reg, int t1_reg, + int t2_reg, int t3_reg) + __attribute__((unused)); =20 TCGContext tcg_init_ctx; __thread TCGContext *tcg_ctx; @@ -5073,8 +5078,8 @@ static int tcg_out_helper_arg_ra(TCGContext *s, unsig= ned d_arg, } =20 /* - * Poor man's topological sort on 2 source+destination register pairs. - * This is a simplified version of tcg_out_movext2 for 32-bit hosts. + * Poor man's topological sort on up to 4 source+destination register pair= s. + * This first is a simplified version of tcg_out_movext2 for 32-bit hosts. */ static void tcg_out_mov_32x2(TCGContext *s, TCGReg d1, TCGReg s1, TCGReg d2, TCGReg s2, int t1) @@ -5098,6 +5103,67 @@ static void tcg_out_mov_32x2(TCGContext *s, TCGReg d= 1, TCGReg s1, tcg_out_mov(s, TCG_TYPE_I32, d1, s1); } =20 +static void tcg_out_mov_32x3(TCGContext *s, TCGReg d1, TCGReg s1, + TCGReg d2, TCGReg s2, + TCGReg d3, TCGReg s3, int t1, int t2) +{ + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); + tcg_debug_assert(t2 >=3D 0); + + if (d1 !=3D s2 && d1 !=3D s3) { + tcg_out_mov(s, TCG_TYPE_I32, d1, s1); + tcg_out_mov_32x2(s, d3, s3, d2, s2, t1); + return; + } + if (d2 !=3D s1 && d2 !=3D s3) { + tcg_out_mov(s, TCG_TYPE_I32, d2, s2); + tcg_out_mov_32x2(s, d1, s1, d3, s3, t1); + return; + } + if (d3 !=3D s1 && d3 !=3D s2) { + tcg_out_mov(s, TCG_TYPE_I32, d3, s3); + tcg_out_mov_32x2(s, d1, s1, d2, s2, t1); + return; + } + tcg_out_mov(s, TCG_TYPE_I32, t2, s3); + tcg_out_mov_32x2(s, d1, s1, d2, s2, t1); + tcg_out_mov(s, TCG_TYPE_I32, d3, t2); +} + +static void tcg_out_mov_32x4(TCGContext *s, TCGReg d1, TCGReg s1, + TCGReg d2, TCGReg s2, + TCGReg d3, TCGReg s3, + TCGReg d4, TCGReg s4, + int t1, int t2, int t3) +{ + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); + tcg_debug_assert(t3 >=3D 0); + + if (d1 !=3D s2 && d1 !=3D s3 && d1 !=3D s4) { + tcg_out_mov(s, TCG_TYPE_I32, d1, s1); + tcg_out_mov_32x3(s, d4, s4, d2, s2, d3, s3, t1, t2); + return; + } + if (d2 !=3D s1 && d2 !=3D s3 && d2 !=3D s4) { + tcg_out_mov(s, TCG_TYPE_I32, d2, s2); + tcg_out_mov_32x3(s, d1, s1, d4, s4, d3, s3, t1, t2); + return; + } + if (d3 !=3D s1 && d3 !=3D s2 && d3 !=3D s4) { + tcg_out_mov(s, TCG_TYPE_I32, d3, s3); + tcg_out_mov_32x3(s, d1, s1, d2, s2, d4, s4, t1, t2); + return; + } + if (d4 !=3D s1 && d4 !=3D s2 && d4 !=3D s3) { + tcg_out_mov(s, TCG_TYPE_I32, d4, s4); + tcg_out_mov_32x3(s, d1, s1, d2, s2, d3, s3, t1, t2); + return; + } + tcg_out_mov(s, TCG_TYPE_I32, t3, s4); + tcg_out_mov_32x3(s, d1, s1, d2, s2, d3, s3, t1, t2); + tcg_out_mov(s, TCG_TYPE_I32, d4, t3); +} + static void tcg_out_helper_arg_32x2(TCGContext *s, unsigned d_arg, TCGReg lo_reg, TCGReg hi_reg, int scratch_reg) @@ -5160,6 +5226,125 @@ static int tcg_out_ld_helper_args(TCGContext *s, co= nst TCGLabelQemuLdst *l, (uintptr_t)l->raddr, scratch_reg); } =20 +static int tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *l, + void (*ra_gen)(TCGContext *s, TCGReg r), + int ra_reg, int t1_reg, + int t2_reg, int t3_reg) +{ + MemOp size =3D get_memop(l->oi) & MO_SIZE; + /* These are the types of the helper_stX_mmu 'addr' and 'val' argument= s. */ + TCGType a_type =3D TARGET_LONG_BITS =3D=3D 32 ? TCG_TYPE_I32 : TCG_TYP= E_I64; + TCGType d_type =3D size =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32; + MemOp a_mo =3D TARGET_LONG_BITS =3D=3D 32 ? MO_32 : MO_64; + MemOp p_mo =3D sizeof(void *) =3D=3D 4 ? MO_32 : MO_64; + /* Begin by skipping the env argument. */ + int arg =3D 1; + int a_arg, d_arg; + + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + a_arg =3D arg++; + } else { + if (TCG_TARGET_CALL_ARG_I64 =3D=3D TCG_CALL_ARG_EVEN) { + arg +=3D arg & 1; + } + a_arg =3D arg; + arg +=3D 2; + } + if (TCG_TARGET_REG_BITS =3D=3D 64 || d_type =3D=3D TCG_TYPE_I32) { + d_arg =3D arg++; + } else { + if (TCG_TARGET_CALL_ARG_I64 =3D=3D TCG_CALL_ARG_EVEN) { + arg +=3D arg & 1; + } + d_arg =3D arg; + arg +=3D 2; + } + + if (arg =3D=3D 3) { + /* Two simple arguments. */ + if (in_iarg_reg(d_arg)) { + /* Both arguments are in registers. */ + if (TCG_TARGET_CALL_ARG_I32 =3D=3D TCG_CALL_ARG_EXTEND) { + a_type =3D TCG_TYPE_REG; + d_type =3D TCG_TYPE_REG; + } + tcg_out_movext2(s, a_type, tcg_target_call_iarg_regs[a_arg], + a_type, a_mo, l->addrlo_reg, + d_type, tcg_target_call_iarg_regs[d_arg], + l->type, size, l->datalo_reg, + t1_reg); + } else { + /* At least data argument is on the stack. */ + tcg_out_helper_arg(s, d_type, d_arg, l->type, size, + l->datalo_reg, t1_reg); + tcg_out_helper_arg(s, a_type, arg, a_type, a_mo, + l->addrlo_reg, t1_reg); + } + } else if (!in_iarg_reg(d_arg)) { + /* + * The data registers are on the stack. Store them first so that + * we are sure they are out of the way of the address registers. + */ + if (size !=3D MO_64) { + tcg_out_helper_arg(s, TCG_TYPE_I32, d_arg, TCG_TYPE_I32, + size, l->datalo_reg, t1_reg); + } else { + tcg_out_helper_arg_32x2(s, d_arg, l->datalo_reg, + l->datahi_reg, t1_reg); + } + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_helper_arg(s, a_type, a_arg, a_type, a_mo, + l->addrlo_reg, t1_reg); + } else { + tcg_out_helper_arg_32x2(s, d_arg, l->addrlo_reg, + l->addrhi_reg, t1_reg); + } + } else { + tcg_debug_assert(arg <=3D ARRAY_SIZE(tcg_target_call_iarg_regs)); + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_debug_assert(d_type =3D=3D TCG_TYPE_I64); + TCGReg a =3D tcg_target_call_iarg_regs[a_arg]; + TCGReg dl =3D tcg_target_call_iarg_regs[d_arg + HOST_BIG_ENDIA= N]; + TCGReg dh =3D tcg_target_call_iarg_regs[d_arg + !HOST_BIG_ENDI= AN]; + + tcg_out_mov_32x3(s, a, l->addrlo_reg, + dl, l->datalo_reg, + dh, l->datahi_reg, t1_reg, t2_reg); + } else if (d_type =3D=3D TCG_TYPE_I32) { + TCGReg al =3D tcg_target_call_iarg_regs[a_arg + HOST_BIG_ENDIA= N]; + TCGReg ah =3D tcg_target_call_iarg_regs[a_arg + !HOST_BIG_ENDI= AN]; + TCGReg d =3D tcg_target_call_iarg_regs[d_arg]; + + tcg_out_mov_32x3(s, al, l->addrlo_reg, + ah, l->addrhi_reg, + d, l->datalo_reg, t1_reg, t2_reg); + } else { + TCGReg al =3D tcg_target_call_iarg_regs[a_arg + HOST_BIG_ENDIA= N]; + TCGReg ah =3D tcg_target_call_iarg_regs[a_arg + !HOST_BIG_ENDI= AN]; + TCGReg dl =3D tcg_target_call_iarg_regs[d_arg + HOST_BIG_ENDIA= N]; + TCGReg dh =3D tcg_target_call_iarg_regs[d_arg + !HOST_BIG_ENDI= AN]; + + tcg_out_mov_32x4(s, al, l->addrlo_reg, + ah, l->addrhi_reg, + dl, l->datalo_reg, + dh, l->datahi_reg, + t1_reg, t2_reg, t3_reg); + } + } + + /* Handle env. Always the first argument. */ + tcg_out_helper_arg(s, TCG_TYPE_PTR, 0, + TCG_TYPE_PTR, p_mo, TCG_AREG0, t1_reg); + + /* Handle oi. */ + tcg_out_helper_arg_im(s, TCG_TYPE_I32, arg, l->oi, t1_reg); + arg++; + + /* Handle ra. Return any register holding it for use by tail call. */ + return tcg_out_helper_arg_ra(s, arg, ra_gen, ra_reg, + (uintptr_t)l->raddr, t1_reg); +} + #ifdef CONFIG_PROFILER =20 /* avoid copy/paste errors */ diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index f983900669..e1430f3a55 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1580,13 +1580,6 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext,= TCGReg d, } } =20 -static void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target) -{ - ptrdiff_t offset =3D tcg_pcrel_diff(s, target); - tcg_debug_assert(offset =3D=3D sextract64(offset, 0, 21)); - tcg_out_insn(s, 3406, ADR, rd, offset); -} - #ifdef CONFIG_SOFTMMU /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * MemOpIdx oi, uintptr_t ra) @@ -1640,19 +1633,13 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); - MemOp size =3D opc & MO_SIZE; + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc19(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0); - tcg_out_mov(s, TARGET_LONG_BITS =3D=3D 64, TCG_REG_X1, lb->addrlo_reg); - tcg_out_mov(s, size =3D=3D MO_64, TCG_REG_X2, lb->datalo_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, oi); - tcg_out_adr(s, TCG_REG_X4, lb->raddr); + tcg_out_st_helper_args(s, lb, NULL, -1, TCG_REG_TMP, -1, -1); tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE]); tcg_out_goto(s, lb->raddr); return true; @@ -1764,6 +1751,13 @@ static void tcg_out_test_alignment(TCGContext *s, bo= ol is_ld, TCGReg addr_reg, label->raddr =3D tcg_splitwx_to_rx(s->code_ptr); } =20 +static void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target) +{ + ptrdiff_t offset =3D tcg_pcrel_diff(s, target); + tcg_debug_assert(offset =3D=3D sextract64(offset, 0, 21)); + tcg_out_insn(s, 3406, ADR, rd, offset); +} + static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) { if (!reloc_pc19(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index b187d5b28f..64fb5a1c27 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -690,8 +690,8 @@ tcg_out_ldrd_rwb(TCGContext *s, ARMCond cond, TCGReg rt= , TCGReg rn, TCGReg rm) tcg_out_memop_r(s, cond, INSN_LDRD_REG, rt, rn, rm, 1, 1, 1); } =20 -static void tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, - TCGReg rn, int imm8) +static void __attribute__((unused)) +tcg_out_strd_8(TCGContext *s, ARMCond cond, TCGReg rt, TCGReg rn, int imm8) { tcg_out_memop_8(s, cond, INSN_STRD_IMM, rt, rn, imm8, 1, 0); } @@ -969,28 +969,16 @@ static void tcg_out_ext8u(TCGContext *s, TCGReg rd, T= CGReg rn) tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn, 0xff); } =20 -static void __attribute__((unused)) -tcg_out_ext8u_cond(TCGContext *s, ARMCond cond, TCGReg rd, TCGReg rn) -{ - tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn, 0xff); -} - static void tcg_out_ext16s(TCGContext *s, TCGType t, TCGReg rd, TCGReg rn) { /* sxth */ tcg_out32(s, 0x06bf0070 | (COND_AL << 28) | (rd << 12) | rn); } =20 -static void tcg_out_ext16u_cond(TCGContext *s, ARMCond cond, - TCGReg rd, TCGReg rn) -{ - /* uxth */ - tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | rn); -} - static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) { - tcg_out_ext16u_cond(s, COND_AL, rd, rn); + /* uxth */ + tcg_out32(s, 0x06ff0070 | (COND_AL << 28) | (rd << 12) | rn); } =20 static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rn) @@ -1375,58 +1363,6 @@ static void * const qemu_st_helpers[MO_SIZE + 1] =3D= { #endif }; =20 -/* Helper routines for marshalling helper function arguments into - * the correct registers and stack. - * argreg is where we want to put this argument, arg is the argument itsel= f. - * Return value is the updated argreg ready for the next call. - * Note that argreg 0..3 is real registers, 4+ on stack. - * - * We provide routines for arguments which are: immediate, 32 bit - * value in register, 16 and 8 bit values in register (which must be zero - * extended before use) and 64 bit value in a lo:hi register pair. - */ -#define DEFINE_TCG_OUT_ARG(NAME, ARGTYPE, MOV_ARG, EXT_ARG) = \ -static TCGReg NAME(TCGContext *s, TCGReg argreg, ARGTYPE arg) = \ -{ = \ - if (argreg < 4) { = \ - MOV_ARG(s, COND_AL, argreg, arg); = \ - } else { = \ - int ofs =3D (argreg - 4) * 4; = \ - EXT_ARG; = \ - tcg_debug_assert(ofs + 4 <=3D TCG_STATIC_CALL_ARGS_SIZE); = \ - tcg_out_st32_12(s, COND_AL, arg, TCG_REG_CALL_STACK, ofs); = \ - } = \ - return argreg + 1; = \ -} - -DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32, uint32_t, tcg_out_movi32, - (tcg_out_movi32(s, COND_AL, TCG_REG_TMP, arg), arg =3D TCG_REG_TMP)) -DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8, TCGReg, tcg_out_ext8u_cond, - (tcg_out_ext8u_cond(s, COND_AL, TCG_REG_TMP, arg), arg =3D TCG_REG_TMP= )) -DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16, TCGReg, tcg_out_ext16u_cond, - (tcg_out_ext16u_cond(s, COND_AL, TCG_REG_TMP, arg), arg =3D TCG_REG_TM= P)) -DEFINE_TCG_OUT_ARG(tcg_out_arg_reg32, TCGReg, tcg_out_mov_reg, ) - -static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg, - TCGReg arglo, TCGReg arghi) -{ - /* 64 bit arguments must go in even/odd register pairs - * and in 8-aligned stack slots. - */ - if (argreg & 1) { - argreg++; - } - if (argreg >=3D 4 && (arglo & 1) =3D=3D 0 && arghi =3D=3D arglo + 1) { - tcg_out_strd_8(s, COND_AL, arglo, - TCG_REG_CALL_STACK, (argreg - 4) * 4); - return argreg + 2; - } else { - argreg =3D tcg_out_arg_reg32(s, argreg, arglo); - argreg =3D tcg_out_arg_reg32(s, argreg, arghi); - return argreg; - } -} - #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS) =20 /* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ @@ -1574,42 +1510,14 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGReg argreg, datalo, datahi; - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - argreg =3D TCG_REG_R0; - argreg =3D tcg_out_arg_reg32(s, argreg, TCG_AREG0); - if (TARGET_LONG_BITS =3D=3D 64) { - argreg =3D tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi= _reg); - } else { - argreg =3D tcg_out_arg_reg32(s, argreg, lb->addrlo_reg); - } - - datalo =3D lb->datalo_reg; - datahi =3D lb->datahi_reg; - switch (opc & MO_SIZE) { - case MO_8: - argreg =3D tcg_out_arg_reg8(s, argreg, datalo); - break; - case MO_16: - argreg =3D tcg_out_arg_reg16(s, argreg, datalo); - break; - case MO_32: - default: - argreg =3D tcg_out_arg_reg32(s, argreg, datalo); - break; - case MO_64: - argreg =3D tcg_out_arg_reg64(s, argreg, datalo, datahi); - break; - } - - argreg =3D tcg_out_arg_imm32(s, argreg, oi); - argreg =3D tcg_out_arg_reg32(s, argreg, TCG_REG_R14); + tcg_out_st_helper_args(s, lb, NULL, TCG_REG_R14, + TCG_REG_TMP, TCG_REG_R0, -1); =20 /* Tail-call to the helper, which will return to the fast path. */ tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & MO_SIZE]); diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 219dc08690..277d99b79c 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1946,9 +1946,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) */ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; + MemOp opc =3D get_memop(l->oi); tcg_insn_unit **label_ptr =3D &l->label_ptr[0]; TCGReg retaddr; =20 @@ -1958,51 +1956,8 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4); } =20 - if (TCG_TARGET_REG_BITS =3D=3D 32) { - int ofs =3D 0; - - tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs); - ofs +=3D 4; - - tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - } - - tcg_out_st(s, TCG_TYPE_I32, l->datalo_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - - if (s_bits =3D=3D MO_64) { - tcg_out_st(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_ESP, ofs); - ofs +=3D 4; - } - - tcg_out_sti(s, TCG_TYPE_I32, oi, TCG_REG_ESP, ofs); - ofs +=3D 4; - - retaddr =3D TCG_REG_EAX; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, ofs); - } else { - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_ARE= G0); - /* The second argument is already loaded with addrlo. */ - tcg_out_mov(s, (s_bits =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), - tcg_target_call_iarg_regs[2], l->datalo_reg); - tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], oi); - - if (ARRAY_SIZE(tcg_target_call_iarg_regs) > 4) { - retaddr =3D tcg_target_call_iarg_regs[4]; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - } else { - retaddr =3D TCG_REG_RAX; - tcg_out_movi(s, TCG_TYPE_PTR, retaddr, (uintptr_t)l->raddr); - tcg_out_st(s, TCG_TYPE_PTR, retaddr, TCG_REG_ESP, - TCG_TARGET_CALL_STACK_OFFSET); - } - } + retaddr =3D tcg_out_st_helper_args(s, l, NULL, -1, TCG_REG_EAX, -1, -1= ); + tcg_debug_assert(retaddr >=3D 0); =20 /* "Tail call" to the helper, with the return address back inline. */ tcg_out_push(s, retaddr); diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index a0ef830179..fb092330d4 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -913,8 +913,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TC= GLabelQemuLdst *l) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(l->oi); MemOp size =3D opc & MO_SIZE; =20 /* resolve label address */ @@ -923,13 +922,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, T= CGLabelQemuLdst *l) } =20 /* call store helper */ - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A1, l->addrlo_reg); - tcg_out_movext(s, size =3D=3D MO_64 ? TCG_TYPE_I32 : TCG_TYPE_I32, TCG= _REG_A2, - l->type, size, l->datalo_reg); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, oi); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A4, (tcg_target_long)l->raddr); - + tcg_out_st_helper_args(s, l, NULL, -1, TCG_REG_TMP0, -1, -1); tcg_out_call_int(s, qemu_st_helpers[size], false); =20 return tcg_out_goto(s, l->raddr); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 9723163b97..1206bda502 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1115,72 +1115,6 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_BS= WAP) + 1] =3D { [MO_BEUQ] =3D helper_be_stq_mmu, }; =20 -/* Helper routines for marshalling helper function arguments into - * the correct registers and stack. - * I is where we want to put this argument, and is updated and returned - * for the next call. ARG is the argument itself. - * - * We provide routines for arguments which are: immediate, 32 bit - * value in register, 16 and 8 bit values in register (which must be zero - * extended before use) and 64 bit value in a lo:hi register pair. - */ - -static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg) -{ - if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { - tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg); - } else { - /* For N32 and N64, the initial offset is different. But there - we also have 8 argument register so we don't run out here. */ - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); - tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i); - } - return i + 1; -} - -static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg) -{ - TCGReg tmp =3D TCG_TMP0; - if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { - tmp =3D tcg_target_call_iarg_regs[i]; - } - tcg_out_ext8u(s, tmp, arg); - return tcg_out_call_iarg_reg(s, i, tmp); -} - -static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg) -{ - TCGReg tmp =3D TCG_TMP0; - if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { - tmp =3D tcg_target_call_iarg_regs[i]; - } - tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff); - return tcg_out_call_iarg_reg(s, i, tmp); -} - -static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg) -{ - TCGReg tmp =3D TCG_TMP0; - if (arg =3D=3D 0) { - tmp =3D TCG_REG_ZERO; - } else { - if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { - tmp =3D tcg_target_call_iarg_regs[i]; - } - tcg_out_movi(s, TCG_TYPE_REG, tmp, arg); - } - return tcg_out_call_iarg_reg(s, i, tmp); -} - -static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg = ah) -{ - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); - i =3D (i + 1) & ~1; - i =3D tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al)); - i =3D tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah)); - return i; -} - /* We expect to use a 16-bit negative offset from ENV. */ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); @@ -1343,10 +1277,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { const tcg_insn_unit *tgt_rx =3D tcg_splitwx_to_rx(s->code_ptr); - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; - int i; + MemOp opc =3D get_memop(l->oi); + int ra; =20 /* resolve label address */ if (!reloc_pc16(l->label_ptr[0], tgt_rx) @@ -1355,41 +1287,14 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) return false; } =20 - i =3D 1; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - i =3D tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); - } else { - i =3D tcg_out_call_iarg_reg(s, i, l->addrlo_reg); - } - switch (s_bits) { - case MO_8: - i =3D tcg_out_call_iarg_reg8(s, i, l->datalo_reg); - break; - case MO_16: - i =3D tcg_out_call_iarg_reg16(s, i, l->datalo_reg); - break; - case MO_32: - i =3D tcg_out_call_iarg_reg(s, i, l->datalo_reg); - break; - case MO_64: - if (TCG_TARGET_REG_BITS =3D=3D 32) { - i =3D tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_re= g); - } else { - i =3D tcg_out_call_iarg_reg(s, i, l->datalo_reg); - } - break; - default: - g_assert_not_reached(); - } - i =3D tcg_out_call_iarg_imm(s, i, oi); + /* Since o32 only has 4 argument registers, we will only need one temp= . */ + ra =3D tcg_out_st_helper_args(s, l, NULL, -1, TCG_TMP0, -1, -1); + tcg_debug_assert(ra >=3D 0); =20 - /* Tail call to the store helper. Thus force the return address - computation to take place in the return address register. */ - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr); - i =3D tcg_out_call_iarg_reg(s, i, TCG_REG_RA); + /* Tail call to the store helper. */ tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true); /* delay slot */ - tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_RA, ra); return true; } =20 diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index e54ebde104..383464b408 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2170,42 +2170,20 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; - TCGReg hi, lo, arg =3D TCG_REG_R3; + MemOp opc =3D get_memop(lb->oi); =20 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); - - lo =3D lb->addrlo_reg; - hi =3D lb->addrhi_reg; - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - arg |=3D (TCG_TARGET_CALL_ARG_I64 =3D=3D TCG_CALL_ARG_EVEN); - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - } else { - /* If the address needed to be zero-extended, we'll have already - placed it in R4. The only remaining case is 64-bit guest. */ - tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); - } - - lo =3D lb->datalo_reg; - hi =3D lb->datahi_reg; - if (TCG_TARGET_REG_BITS =3D=3D 32 && s_bits =3D=3D MO_64) { - arg |=3D (TCG_TARGET_CALL_ARG_I64 =3D=3D TCG_CALL_ARG_EVEN); - tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); - tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); - } else { - tcg_out_movext(s, s_bits =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I3= 2, - arg++, lb->type, s_bits, lo); - } - - tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); - tcg_out32(s, MFSPR | RT(arg) | LR); + /* + * For the purposes of ppc32 sorting 4 input registers into 4 argument + * registers, there is an outside chance we would require 3 temps. + * Because of constraints, no inputs are in r3, and env will not be + * placed into r3 until after the sorting is done, and is thus free. + */ + tcg_out_st_helper_args(s, lb, tcg_out_mflr, -1, TCG_REG_TMP1, + TCG_REG_R0, TCG_REG_R3); =20 tcg_out_call_int(s, LK, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index e643a83d0d..ab70aa71a8 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1014,14 +1014,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { - MemOpIdx oi =3D l->oi; - MemOp opc =3D get_memop(oi); - MemOp s_bits =3D opc & MO_SIZE; - TCGReg a0 =3D tcg_target_call_iarg_regs[0]; - TCGReg a1 =3D tcg_target_call_iarg_regs[1]; - TCGReg a2 =3D tcg_target_call_iarg_regs[2]; - TCGReg a3 =3D tcg_target_call_iarg_regs[3]; - TCGReg a4 =3D tcg_target_call_iarg_regs[4]; + MemOp opc =3D get_memop(l->oi); =20 /* resolve label address */ if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { @@ -1029,13 +1022,8 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *l) } =20 /* call store helper */ - tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); - tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); - tcg_out_movext(s, s_bits =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, a= 2, - l->type, s_bits, l->datalo_reg); - tcg_out_movi(s, TCG_TYPE_PTR, a3, oi); - tcg_out_movi(s, TCG_TYPE_PTR, a4, (tcg_target_long)l->raddr); - + tcg_out_st_helper_args(s, l, NULL, -1, TCG_REG_TMP0, + TCG_REG_TMP1, TCG_REG_TMP2); tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); =20 tcg_out_goto(s, l->raddr); diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index a81c771196..7d6cb30a06 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1803,25 +1803,14 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) =20 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { - TCGReg addr_reg =3D lb->addrlo_reg; - TCGReg data_reg =3D lb->datalo_reg; - MemOpIdx oi =3D lb->oi; - MemOp opc =3D get_memop(oi); - MemOp size =3D opc & MO_SIZE; + MemOp opc =3D get_memop(lb->oi); =20 if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) { return false; } =20 - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0); - if (TARGET_LONG_BITS =3D=3D 64) { - tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg); - } - tcg_out_movext(s, size =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, - TCG_REG_R4, lb->type, size, data_reg); - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, oi); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R6, (uintptr_t)lb->raddr); + tcg_out_st_helper_args(s, lb, NULL, -1, TCG_TMP0, -1, -1); tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr); --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922259; cv=none; d=zohomail.com; s=zohoarc; b=JQ0z+bUXBf+AknbbuIEczI42rarm/s6GUJJWLrrQoqhdBz4V1RfNHbRFsbuFMuCBBtJVwxXnORhZ5eFGKLtSqeHuPX2YVa8VjRzDa9RoLB6xzShj4zZeJJboXo5pDkPxB10MpHlBnd2effJICdUzqPcL/vDC8jMw8d6S470EF8M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680922259; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+GZA6jV7eBzSRqSRmN5wL/3PVRb3+/abjeojXmp8C2g=; b=AYkxXxQUsSRp65q5MArUk/eyYkW4oA52hFYF0T0qUytwXkwMEO0Rd6p5HG05eBA6jfH1DAXu+GzLQ15OaAFI/XtCthWajD58brUHH3hv4rf9Tls7i+T0KR3p7ELEVnh/bHsHTQvqH9ukCrQBCEklJ17jTQjwn6qJatC6W3Eh4xU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680922259659280.72848632210366; Fri, 7 Apr 2023 19:50:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyZI-00009i-P1; Fri, 07 Apr 2023 22:44:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyYy-0008B6-D3 for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:24 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyYL-0005cw-VH for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:23 -0400 Received: by mail-pj1-x1036.google.com with SMTP id pc4-20020a17090b3b8400b0024676052044so338546pjb.1 for ; Fri, 07 Apr 2023 19:43:45 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921825; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+GZA6jV7eBzSRqSRmN5wL/3PVRb3+/abjeojXmp8C2g=; b=oAbeF1UpgJiNW5ejl+5id4wq1CAvZ3hZFkLA5yT1AsbjgFVeaCM2m0/aBGVq5rl92Q FxWfF9ksp9oO7NaGMcGJvFfA9alY0i5cD7cFCaZmO2/0hcJR0FJgIyvpAYEU+MCpWS9o s8PP3dvrzLx22EHIcFFM5elnSnkl0hrZwtV2IdvGf7fzkigv2i2v6QQ8Ga/s+Liesv1k 4RdjkNfaMGo/u8RKhD9j76z7wqKyjZwdmTe8KuJmz8wpPsYHNwiuT5F6iBOcfvKsaNIL iEoNscgN6bqWMfFTp/lGsSY9yVm52DwMdNLLa+c/GN1supUeE/A4IkLnAtkcOUbNNzoW D50A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921825; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+GZA6jV7eBzSRqSRmN5wL/3PVRb3+/abjeojXmp8C2g=; b=MnJP7ce19GvpC/TKv2S7RF1Tviuol2hMe7feeUQtv/khyPSi/u46uWehLgncLYtbnM z9ISspBgXMQfvEzSkbo19zgidBu9mHGX49ZzhDFftka3fYnPv0SgwfjH4jDgPa/Mp/U0 IWGHcPIAbA5v9sPKdMTG8qeUmJA/JvDQ0aX5DfDXUsZ4RjoW9kVkBobKUsFfxM7xEjOq 3gNa2Vw/OiklOO92XjfBR9qyQ+N4CZj1pgtIRljKcTHT9oiGhv9wHILPOjHihqNYYYdD DjsaDYWmUg+sSJnPbK7OH/Zvctwbvg+HAeBzWDehNlMjSsnQEnKFOk5IhZAz72QLro9m Ar4g== X-Gm-Message-State: AAQBX9csbBfWdlJ7rronF2ZZNiQGjarJmCXXUCudERR43AizyAru7oPe zonaY4jrqxXRRDrNKTh/uehZgBd+2a76Po5APu0= X-Google-Smtp-Source: AKy350Z5MqMyoUTwrKydZAbH7ZV9PQsvU7KRlEm4/LwvE1DeKBZtZh89fkCpiuBdW9fMJM36dehx+Q== X-Received: by 2002:a17:903:784:b0:19f:3b86:4710 with SMTP id kn4-20020a170903078400b0019f3b864710mr537347plb.49.1680921825067; Fri, 07 Apr 2023 19:43:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 32/42] tcg/loongarch64: Simplify constraints on qemu_ld/st Date: Fri, 7 Apr 2023 19:43:04 -0700 Message-Id: <20230408024314.3357414-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922260657100001 Content-Type: text/plain; charset="utf-8" The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 2 -- tcg/loongarch64/tcg-target-con-str.h | 1 - tcg/loongarch64/tcg-target.c.inc | 23 ++++------------------- 3 files changed, 4 insertions(+), 22 deletions(-) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-tar= get-con-set.h index 172c107289..c2bde44613 100644 --- a/tcg/loongarch64/tcg-target-con-set.h +++ b/tcg/loongarch64/tcg-target-con-set.h @@ -17,9 +17,7 @@ C_O0_I1(r) C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) -C_O0_I2(LZ, L) C_O1_I1(r, r) -C_O1_I1(r, L) C_O1_I2(r, r, rC) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) diff --git a/tcg/loongarch64/tcg-target-con-str.h b/tcg/loongarch64/tcg-tar= get-con-str.h index 541ff47fa9..6e9ccca3ad 100644 --- a/tcg/loongarch64/tcg-target-con-str.h +++ b/tcg/loongarch64/tcg-target-con-str.h @@ -14,7 +14,6 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) -REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index fb092330d4..d5063b035d 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -133,18 +133,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKi= nd kind, int slot) #define TCG_CT_CONST_C12 0x1000 #define TCG_CT_CONST_WSZ 0x2000 =20 -#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) -/* - * For softmmu, we need to avoid conflicts with the first 5 - * argument registers to call the helper. Some of these are - * also used for the tlb lookup. - */ -#ifdef CONFIG_SOFTMMU -#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5) -#else -#define SOFTMMU_RESERVE_REGS 0 -#endif - +#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) =20 static inline tcg_target_long sextreg(tcg_target_long val, int pos, int le= n) { @@ -1599,16 +1588,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) case INDEX_op_st32_i64: case INDEX_op_st_i32: case INDEX_op_st_i64: + case INDEX_op_qemu_st_i32: + case INDEX_op_qemu_st_i64: return C_O0_I2(rZ, r); =20 case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: return C_O0_I2(rZ, rZ); =20 - case INDEX_op_qemu_st_i32: - case INDEX_op_qemu_st_i64: - return C_O0_I2(LZ, L); - case INDEX_op_ext8s_i32: case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: @@ -1644,11 +1631,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOp= code op) case INDEX_op_ld32u_i64: case INDEX_op_ld_i32: case INDEX_op_ld_i64: - return C_O1_I1(r, r); - case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return C_O1_I1(r, L); + return C_O1_I1(r, r); =20 case INDEX_op_andc_i32: case INDEX_op_andc_i64: --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922188; cv=none; d=zohomail.com; s=zohoarc; b=MTzDTVhfpkKsusYrplF9JMFAjILf1s7NwTly1HKTL8qYtMMkMne9p6osJGnrzdvZV30t217gvU0ZtYpSslwpuPjDpvsQXUegufabQ4hhheD3lSTGs9rVGFFl+hTBy8WJ4fMWdfvsR0KhYxLiJ6HecWOC08XC++AfHBfaCH8sCsg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680922188; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KhrCHLGVho5MP5YRsKBSeSmutLAxr0EB2DHCqq7DAR8=; b=mP5PQIBytQCBWO7z2LEjJumXm2771wxgghkJie3M9HVg4x0OKPvBMAuwfNEvvQna8PGmywjtEQQD6lZDwt1yvKLmaso+J5myxWRc4fIAguRjTFWT+OM6RPDAFjNyTcDlde87i4l8+c366LPEislKNvJMgVNI6/9f6Lf2iMPoewU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680922188266748.7623032813337; Fri, 7 Apr 2023 19:49:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyZU-0001kf-RJ; Fri, 07 Apr 2023 22:44:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyZ1-0008R1-MX for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:29 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyYN-0005qe-BP for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:27 -0400 Received: by mail-pj1-x1036.google.com with SMTP id d22-20020a17090a111600b0023d1b009f52so2769663pja.2 for ; Fri, 07 Apr 2023 19:43:46 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921826; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KhrCHLGVho5MP5YRsKBSeSmutLAxr0EB2DHCqq7DAR8=; b=be1AYLH6IkUkB3G9geWmp/NWW7SGCrcrHX2jzr2MpqaS5939PogY1wnmZdIe/lHTla gV1ttB8A7HVxeyNBHYr4MRd+NxdoEmf1YNup04fjpTnYatMeEW7F874JQiFv4EZZMzy6 Mb1+yyeXGxeGRo6zPbDQ6R6XVAP3uhP3GzaRYGIObfysBwE0YjPtofqaBUlSQKvj8fJ0 kRKICwiqSh7h8ktHZBrsXvHZSgwHmdSlqmhYi9AQ+X3asuHQYulGAkPMv036tfzje0p4 aAoxfa2F5VI4hNMyW7I557UxpFFPCfRyEACo2M+GRUnom992eLbwiVh+76TDoRXZZ+D7 BM/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921826; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KhrCHLGVho5MP5YRsKBSeSmutLAxr0EB2DHCqq7DAR8=; b=LQmg8xrHx0jE6eqLfiNU4lSxjjGpum9TMRuVxQ01adbuNBQ98fmqrmDhG5ISmCLPef PqBxzHebBYlmRKCiOKeJkDIgJFKgsiGx0fiN6imuOtW/MOcbX7PSwcsFGivZpfNsWpys tMBmZb5aNay5hX2wjNPZ5ppZer7QGsj/weGlNMZSoXVYe96Lywc8oNg/+nWzZMHa9dS7 tlicG+EyDgKpNTHhfo3XNiU8EZz7Ey8vuhVIJzdoUyX0rF3tL0jbM7EBMTGM/6kqqe4h 3zhHv0/BYFMmIHPpj0lhOppPOW7hIl3Hq07s35ZtMgUeSDZtNB8b9AR8P/+MG1hc99TQ l7Ig== X-Gm-Message-State: AAQBX9efKB6+Cagipu7mRu42SRXEEHZ35c32y2RFPAoEnFHJDb7UAmAI 437kEgiS5ZGieVhagufcYJW8KA5deAjJRW3HsBc= X-Google-Smtp-Source: AKy350b5vpAUO+oLp5euFIaKap9yZSJHtnwM0rrmU+Lkhy0SFGozObBB8EVnaEp+Lu6sPA+Q1R3dzg== X-Received: by 2002:a17:90b:4f90:b0:240:5397:bd91 with SMTP id qe16-20020a17090b4f9000b002405397bd91mr1154649pjb.4.1680921825888; Fri, 07 Apr 2023 19:43:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 33/42] tcg/mips: Reorg tcg_out_tlb_load Date: Fri, 7 Apr 2023 19:43:05 -0700 Message-Id: <20230408024314.3357414-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922189053100009 Content-Type: text/plain; charset="utf-8" Compare the address vs the tlb entry with sign-extended values. This simplifies the page+alignment mask constant, and the generation of the last byte address for the misaligned test. Move the tlb addend load up, and the zero-extension down. This frees up a register, which allows us to drop the 'base' parameter, with which the caller was giving us a 5th temporary. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 90 ++++++++++++++++++++------------------- 1 file changed, 46 insertions(+), 44 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 1206bda502..16b9d09959 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -370,6 +370,8 @@ typedef enum { ALIAS_PADDI =3D sizeof(void *) =3D=3D 4 ? OPC_ADDIU : OPC_DADDIU, ALIAS_TSRL =3D TARGET_LONG_BITS =3D=3D 32 || TCG_TARGET_REG_BITS = =3D=3D 32 ? OPC_SRL : OPC_DSRL, + ALIAS_TADDI =3D TARGET_LONG_BITS =3D=3D 32 || TCG_TARGET_REG_BITS = =3D=3D 32 + ? OPC_ADDIU : OPC_DADDIU, } MIPSInsn; =20 /* @@ -1121,12 +1123,12 @@ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); =20 /* * Perform the tlb comparison operation. - * The complete host address is placed in BASE. * Clobbers TMP0, TMP1, TMP2, TMP3. + * Returns the register containing the complete host address. */ -static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, - TCGReg addrh, MemOpIdx oi, - tcg_insn_unit *label_ptr[2], bool is_load) +static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrl, TCGReg addrh, + MemOpIdx oi, bool is_load, + tcg_insn_unit *label_ptr[2]) { MemOp opc =3D get_memop(oi); unsigned a_bits =3D get_alignment_bits(opc); @@ -1140,7 +1142,6 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg ba= se, TCGReg addrl, int add_off =3D offsetof(CPUTLBEntry, addend); int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - target_ulong tlb_mask; =20 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); @@ -1158,15 +1159,12 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg = base, TCGReg addrl, if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); } else { - tcg_out_ldst(s, (TARGET_LONG_BITS =3D=3D 64 ? OPC_LD - : TCG_TARGET_REG_BITS =3D=3D 64 ? OPC_LWU : OPC_L= W), - TCG_TMP0, TCG_TMP3, cmp_off); + tcg_out_ld(s, TCG_TYPE_TL, TCG_TMP0, TCG_TMP3, cmp_off); } =20 - /* Zero extend a 32-bit guest address for a 64-bit host. */ - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addrl); - addrl =3D base; + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + /* Load the tlb addend for the fast path. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); } =20 /* @@ -1174,18 +1172,18 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg = base, TCGReg addrl, * For unaligned accesses, compare against the end of the access to * verify that it does not cross a page boundary. */ - tlb_mask =3D (target_ulong)TARGET_PAGE_MASK | a_mask; - tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, tlb_mask); - if (a_mask >=3D s_mask) { - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); - } else { - tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP2, addrl, s_mask - a_mask); + tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, TARGET_PAGE_MASK | a_mask); + if (a_mask < s_mask) { + tcg_out_opc_imm(s, ALIAS_TADDI, TCG_TMP2, addrl, s_mask - a_mask); tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); + } else { + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); } =20 - if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { - /* Load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); + /* Zero extend a 32-bit guest address for a 64-bit host. */ + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_TMP2, addrl); + addrl =3D TCG_TMP2; } =20 label_ptr[0] =3D s->code_ptr; @@ -1197,14 +1195,15 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg = base, TCGReg addrl, tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); =20 /* Load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); =20 label_ptr[1] =3D s->code_ptr; tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0); } =20 /* delay slot */ - tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl); + tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, addrl); + return TCG_TMP3; } =20 static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, @@ -1606,10 +1605,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCG= Arg *args, TCGType d_type) MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[2]; -#else #endif unsigned a_bits, s_bits; - TCGReg base =3D TCG_REG_A0; + TCGReg base; =20 data_regl =3D *args++; data_regh =3D (TCG_TARGET_REG_BITS =3D=3D 64 || d_type =3D=3D TCG_TYPE= _I32 @@ -1626,7 +1624,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, TCGType d_type) * system to support misaligned memory accesses. */ #if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1); + base =3D tcg_out_tlb_load(s, addr_regl, addr_regh, oi, true, label_ptr= ); if (use_mips32r6_instructions || a_bits >=3D s_bits) { tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, d_type); } else { @@ -1635,16 +1633,18 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, TCGType d_type) add_qemu_ldst_label(s, true, oi, d_type, data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else + base =3D addr_regl; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addr_regl); - addr_regl =3D base; + tcg_out_ext32u(s, TCG_TMP0, addr_regl); + base =3D TCG_TMP0; } - if (guest_base =3D=3D 0 && data_regl !=3D addr_regl) { - base =3D addr_regl; - } else if (guest_base =3D=3D (int16_t)guest_base) { - tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); - } else { - tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl= ); + if (guest_base) { + if (guest_base =3D=3D (int16_t)guest_base) { + tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP0, base, guest_base); + } else { + tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_GUEST_BASE_REG, b= ase); + } + base =3D TCG_TMP0; } if (use_mips32r6_instructions) { if (a_bits) { @@ -1807,7 +1807,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, TCGType d_type) tcg_insn_unit *label_ptr[2]; #endif unsigned a_bits, s_bits; - TCGReg base =3D TCG_REG_A0; + TCGReg base; =20 data_regl =3D *args++; data_regh =3D (TCG_TARGET_REG_BITS =3D=3D 64 || d_type =3D=3D TCG_TYPE= _I32 @@ -1824,7 +1824,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, TCGType d_type) * system to support misaligned memory accesses. */ #if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0); + base =3D tcg_out_tlb_load(s, addr_regl, addr_regh, oi, false, label_pt= r); if (use_mips32r6_instructions || a_bits >=3D s_bits) { tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); } else { @@ -1833,16 +1833,18 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg *args, TCGType d_type) add_qemu_ldst_label(s, false, oi, d_type, data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else + base =3D addr_regl; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addr_regl); - addr_regl =3D base; + tcg_out_ext32u(s, TCG_TMP0, addr_regl); + base =3D TCG_TMP0; } - if (guest_base =3D=3D 0) { - base =3D addr_regl; - } else if (guest_base =3D=3D (int16_t)guest_base) { - tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); - } else { - tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl= ); + if (guest_base) { + if (guest_base =3D=3D (int16_t)guest_base) { + tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP0, base, guest_base); + } else { + tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_GUEST_BASE_REG, b= ase); + } + base =3D TCG_TMP0; } if (use_mips32r6_instructions) { if (a_bits) { --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922041; cv=none; d=zohomail.com; s=zohoarc; b=UleaaVVTOVg6CECM+J3X+9qxfUSgiQdLS7p3JikL5pD9xQjpCRlZFj6PnEKkhXAPhB8sQfHmEjclp8MjB8Wx89NzcdKkbTv53TNZLyPw5cIrwzOejFOinxW+Hodh8Mebr60d9j9oMQLCHtqhhaO/FBoh0CxSZmzY8J69sd9yQLE= ARC-Message-Signature: i=1; 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([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921826; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZD8D6s1mTsZ3Wn5qEWwRrv84r6pcuNTBrq2RsXDvc+c=; b=W/91gidsjvoXEE+rAUGpm233QgUDJr99+R+jskgo5ZQc93gfApAewQRXLZK6LDTdYk qpDE5rxsVYuutImUDTZRYZ/o7gK0OEPFp+/435LDZ41sArWVpEu1zPFaJZPnbVFTFYFT DvWTgZYAgOzT2BgU99KSbI9pxil002qQ2AyZL9UnGgmweR3O2jnYx93g6KtNVadY7rNi EFLhbqWwWlZ2DLsrz+VgEHjKpl/J3jGG/J+dE75S8EZoiyYX0oSYRbJF6zftRneVkwnN hGSlHckhALxBhBpNxdutE0jfpw6NOCMcHAQXx/0GQ951cqG5ZJPrltXFkj5URMcXUpys +Ozw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921827; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZD8D6s1mTsZ3Wn5qEWwRrv84r6pcuNTBrq2RsXDvc+c=; b=WMlyek5g4mMqm8M7u/vVV6Ot1/J6hiNDaomkTPf1+QWgoOVe7mTYc2IluIp8jkWyrR UO19gtdhAn/I7tz0dgG4che9IebxjlAcjoqKMe8kWcHk/qGjb4fa/qhWvtPFcWeuDRXd 1E2HWelhu1CPE4LkIejlqBUhSOjSoHX4/z+23gKVT5whJguuBzzytRO8FuPXA6DeKHIA uZxOOnEGXxQawLB0ku0yZ1J+Y9P7qkLTxuq/0JId3ifVhUaypMb9tM3iuwWEakuP/9IE Mm2NtFPTKXlsP2UD1t29W0eqpYsZtv59epcOqmE9IggswX+puFY1BImBegzzOOw7tTei aPJw== X-Gm-Message-State: AAQBX9fOR/D9VNa2tHnmC4gU7ZciRV6eBN8lLw4Fg7WAq0RzSgUKzrUt uEMtJV39bqQo2TNdx6G0XlhpW8Jusn5OXt8mtjs= X-Google-Smtp-Source: AKy350bYNHVDZn72PaAGNatHFRmz0FB36y1WlIRW+4D9NPfII8ivn04GS/qcb0kKAm97FO8mKykzUQ== X-Received: by 2002:a17:903:2281:b0:1a1:b15a:d916 with SMTP id b1-20020a170903228100b001a1b15ad916mr6006834plh.3.1680921826681; Fri, 07 Apr 2023 19:43:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 34/42] tcg/mips: Simplify constraints on qemu_ld/st Date: Fri, 7 Apr 2023 19:43:06 -0700 Message-Id: <20230408024314.3357414-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922041752100003 Content-Type: text/plain; charset="utf-8" The softmmu tlb uses TCG_REG_TMP[0-3], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-con-set.h | 13 +++++-------- tcg/mips/tcg-target-con-str.h | 2 -- tcg/mips/tcg-target.c.inc | 30 ++++++++---------------------- 3 files changed, 13 insertions(+), 32 deletions(-) diff --git a/tcg/mips/tcg-target-con-set.h b/tcg/mips/tcg-target-con-set.h index fe3e868a2f..864034f468 100644 --- a/tcg/mips/tcg-target-con-set.h +++ b/tcg/mips/tcg-target-con-set.h @@ -12,15 +12,13 @@ C_O0_I1(r) C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) -C_O0_I2(SZ, S) -C_O0_I3(SZ, S, S) -C_O0_I3(SZ, SZ, S) +C_O0_I3(rZ, r, r) +C_O0_I3(rZ, rZ, r) C_O0_I4(rZ, rZ, rZ, rZ) -C_O0_I4(SZ, SZ, S, S) -C_O1_I1(r, L) +C_O0_I4(rZ, rZ, r, r) C_O1_I1(r, r) C_O1_I2(r, 0, rZ) -C_O1_I2(r, L, L) +C_O1_I2(r, r, r) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) C_O1_I2(r, r, rIK) @@ -30,7 +28,6 @@ C_O1_I2(r, rZ, rN) C_O1_I2(r, rZ, rZ) C_O1_I4(r, rZ, rZ, rZ, 0) C_O1_I4(r, rZ, rZ, rZ, rZ) -C_O2_I1(r, r, L) -C_O2_I2(r, r, L, L) +C_O2_I1(r, r, r) C_O2_I2(r, r, r, r) C_O2_I4(r, r, rZ, rZ, rN, rN) diff --git a/tcg/mips/tcg-target-con-str.h b/tcg/mips/tcg-target-con-str.h index e4b2965c72..413c280a7a 100644 --- a/tcg/mips/tcg-target-con-str.h +++ b/tcg/mips/tcg-target-con-str.h @@ -9,8 +9,6 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) -REGS('L', ALL_QLOAD_REGS) -REGS('S', ALL_QSTORE_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 16b9d09959..34908c799a 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -176,20 +176,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, #define TCG_CT_CONST_WSZ 0x2000 /* word size */ =20 #define ALL_GENERAL_REGS 0xffffffffu -#define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0)) - -#ifdef CONFIG_SOFTMMU -#define ALL_QLOAD_REGS \ - (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2)) -#define ALL_QSTORE_REGS \ - (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \ - ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \ - : (1 << TCG_REG_A1))) -#else -#define ALL_QLOAD_REGS NOA0_REGS -#define ALL_QSTORE_REGS NOA0_REGS -#endif - =20 static bool is_p2m1(tcg_target_long val) { @@ -2488,18 +2474,18 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_qemu_ld_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); + ? C_O1_I1(r, r) : C_O1_I2(r, r, r)); case INDEX_op_qemu_st_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S)); + ? C_O0_I2(rZ, r) : C_O0_I3(rZ, r, r)); case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) - : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(r, r, L) - : C_O2_I2(r, r, L, L)); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) + : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(r, r, r) + : C_O2_I2(r, r, r, r)); case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(SZ, S) - : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(SZ, SZ, S) - : C_O0_I4(SZ, SZ, S, S)); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(rZ, r) + : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(rZ, rZ, r) + : C_O0_I4(rZ, rZ, r, r)); =20 default: g_assert_not_reached(); --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922078; cv=none; d=zohomail.com; s=zohoarc; b=GDG/7BaTiLoIBU5Vseanv7Ale0aK0gINnxlvyvJzYcqdBagCN08cfKoERFoc8/ayy9X3PXItCvaE16Rdq7FMgCji6qViYRdB1RKZfUo20GwmR/3pKyaBEpGz2MZoPo6jwlt2hZBalTHk2bho4ovEBue5OPdhlniuky9gkJNgF9k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680922078; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mz8kJeRhmTsi9fcghAqDVd5txMxvTf7rUjSQ1DhbH08=; b=Uh7R4Me18mWJojHHiKg4zRgA+0HmXj7Y8F03mQRtzLsHsV1iNsQ3WwfYnmKVescgYvFCcllemaGzj5npDU/xN5Fa17yuhN1M49H/QHQ9UsOK1D1vpAX6I8epTHyHY4n8yGgqWiyCKlbTNvcEYBMDtOJTVOaXK8uQxw+YFSyYDe4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680922078876235.7823463977163; Fri, 7 Apr 2023 19:47:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyZN-0000n8-Km; Fri, 07 Apr 2023 22:44:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyZ4-0008Sq-NS for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:31 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyYP-0005rw-79 for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:30 -0400 Received: by mail-pj1-x102a.google.com with SMTP id c10-20020a17090abf0a00b0023d1bbd9f9eso2853427pjs.0 for ; Fri, 07 Apr 2023 19:43:48 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921827; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mz8kJeRhmTsi9fcghAqDVd5txMxvTf7rUjSQ1DhbH08=; b=S+GDurDA0VvnMmpRdUOsGLgiffJkRryZzWtd1MP3foxG6NHE+IbWC2ezV+kptgEWgP zkQg93D0eGpWjb6jmUjsMbVw09P5pl+F8yrn+cc60qg6RjDI0USXvD9ysI2a5HQC5QrL mdIeYaM6m1mRoCOCx77x218Ag01boE8+XxqOpqWPG1lDEzAHul9tla4YDNUY+uZp4rW/ 7lU9H6b16KPmiS2UG3k2Ha14obSWM+RjCkh9hn+FMyIpzvbKFOvEfTMufNkJgIItygIV QyLhkbYbJwB0MimIusH+1ipG5+1Lz48DVCqqPUdXs++KCfV64Y8eC7o3cjpR6+2LhXQb ZLWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921827; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mz8kJeRhmTsi9fcghAqDVd5txMxvTf7rUjSQ1DhbH08=; b=iqRWAKnWr1tol72ahTUl9RN8kppw7btO3akc1wkjywXtPgJYwlJvqJdrQiKHQBFulz gJmnh3dypBiRNp1XV7BQl96MRXezCZ0LsMQhwDJkTVWwfLb5w2LhQ0G01Az6tlvShaHg ANHO4fNsadJooxVxrMDCYNgHp0TZXxod++y8JRl9mgy67raNNoB5DvybdaO4YSLyeOB+ 2b3e1UoutlgFbIljDP0pjAIgl+CHI9TV5h9YVvgEhZq9RkxAJmHiT0IT3GCHY1elE3Xd oji4yz0l1/zPSX88Cux1bO6e3VgOoCuq1tnZn3ru8S7f9c7H2iNeAIhYk0Wxa8PK+8G+ n0xg== X-Gm-Message-State: AAQBX9dlJRdE629TyUbY3IJH5LFFa2rrJ1LD0WxmdAylt5uD0k75Yrkg IQftXE2ctGP/WDfsr3vVRT30R2Ljc8fGgQseoSU= X-Google-Smtp-Source: AKy350YOsf3LhOd/mYTrjlSELJ48+yCmHCX1Sd1+3As1ILH0gxLeRdlDdGIFD2Su+z8d4HXfc/Taew== X-Received: by 2002:a17:90b:1d11:b0:23d:158c:a60c with SMTP id on17-20020a17090b1d1100b0023d158ca60cmr4578828pjb.44.1680921827490; Fri, 07 Apr 2023 19:43:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 35/42] tcg/ppc: Reorg tcg_out_tlb_read Date: Fri, 7 Apr 2023 19:43:07 -0700 Message-Id: <20230408024314.3357414-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922080629100003 Content-Type: text/plain; charset="utf-8" Allocate TCG_REG_TMP2. Use R0, TMP1, TMP2 instead of any of the normally allocated registers for the tlb load. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 83 +++++++++++++++++++++++----------------- 1 file changed, 48 insertions(+), 35 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 383464b408..7195c0b817 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -68,6 +68,7 @@ #else # define TCG_REG_TMP1 TCG_REG_R12 #endif +#define TCG_REG_TMP2 TCG_REG_R11 =20 #define TCG_VEC_TMP1 TCG_REG_V0 #define TCG_VEC_TMP2 TCG_REG_V1 @@ -2007,10 +2008,11 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_B= SWAP) + 1] =3D { QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); =20 -/* Perform the TLB load and compare. Places the result of the comparison - in CR7, loads the addend of the TLB into R3, and returns the register - containing the guest address (zero-extended into R4). Clobbers R0 and = R2. */ - +/* + * Perform the TLB load and compare. Places the result of the comparison + * in CR7, loads the addend of the TLB into TMP1, and returns the register + * containing the guest address (zero-extended into TMP2). Clobbers R0. + */ static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc, TCGReg addrlo, TCGReg addrhi, int mem_index, bool is_read) @@ -2026,40 +2028,44 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp= opc, unsigned a_bits =3D get_alignment_bits(opc); =20 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_AREG0, table_off); =20 /* Extract the page index, shifted into place for tlb index. */ if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_shri32(s, TCG_REG_TMP1, addrlo, + tcg_out_shri32(s, TCG_REG_R0, addrlo, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); } else { - tcg_out_shri64(s, TCG_REG_TMP1, addrlo, + tcg_out_shri64(s, TCG_REG_R0, addrlo, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); } - tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1)); + tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0)); =20 - /* Load the TLB comparator. */ + /* Load the (low part) TLB comparator into TMP2. */ if (cmp_off =3D=3D 0 && TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { uint32_t lxu =3D (TCG_TARGET_REG_BITS =3D=3D 32 || TARGET_LONG_BIT= S =3D=3D 32 ? LWZUX : LDUX); - tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4)); + tcg_out32(s, lxu | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2)); } else { - tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4)); + tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2)); if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off = + 4); - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, + TCG_REG_TMP1, cmp_off + 4); } else { - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off); + tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off= ); } } =20 - /* Load the TLB addend for use on the fast path. Do this asap - to minimize any load use delay. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, - offsetof(CPUTLBEntry, addend)); + /* + * Load the TLB addend for use on the fast path. + * Do this asap to minimize any load use delay. + */ + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, + offsetof(CPUTLBEntry, addend)); + } =20 - /* Clear the non-page, non-alignment bits from the address */ + /* Clear the non-page, non-alignment bits from the address into R0. */ if (TCG_TARGET_REG_BITS =3D=3D 32) { /* We don't support unaligned accesses on 32-bits. * Preserve the bottom bits and thus trigger a comparison @@ -2090,9 +2096,6 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp o= pc, if (TARGET_LONG_BITS =3D=3D 32) { tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); - /* Zero-extend the address for use in the final address. */ - tcg_out_ext32u(s, TCG_REG_R4, addrlo); - addrlo =3D TCG_REG_R4; } else if (a_bits =3D=3D 0) { tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS= ); } else { @@ -2102,16 +2105,27 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp= opc, } } =20 + /* Full or low part comparison into cr7. */ + tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 0, 7, TCG_TYPE_I= 32); + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, - 0, 7, TCG_TYPE_I32); - tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32= ); + /* High part comparison into cr6. */ + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R0, TCG_REG_TMP1, cmp_off); + tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, addrhi, 0, 6, TCG_TYPE_I32= ); + + /* Load addend, deferred for this case. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, + offsetof(CPUTLBEntry, addend)); + + /* Combine comparisons into cr7. */ tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); - } else { - tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, - 0, 7, TCG_TYPE_TL); } =20 + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + /* Zero-extend the address for use in the final address. */ + tcg_out_ext32u(s, TCG_REG_TMP2, addrlo); + return TCG_REG_TMP2; + } return addrlo; } =20 @@ -2179,11 +2193,9 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s,= TCGLabelQemuLdst *lb) /* * For the purposes of ppc32 sorting 4 input registers into 4 argument * registers, there is an outside chance we would require 3 temps. - * Because of constraints, no inputs are in r3, and env will not be - * placed into r3 until after the sorting is done, and is thus free. */ tcg_out_st_helper_args(s, lb, tcg_out_mflr, -1, TCG_REG_TMP1, - TCG_REG_R0, TCG_REG_R3); + TCG_REG_TMP2, TCG_REG_R0); =20 tcg_out_call_int(s, LK, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); =20 @@ -2285,7 +2297,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, TCGType d_type) label_ptr =3D s->code_ptr; tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); =20 - rbase =3D TCG_REG_R3; + rbase =3D TCG_REG_TMP1; #else /* !CONFIG_SOFTMMU */ a_bits =3D get_alignment_bits(opc); if (a_bits) { @@ -2366,7 +2378,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, TCGType d_type) label_ptr =3D s->code_ptr; tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); =20 - rbase =3D TCG_REG_R3; + rbase =3D TCG_REG_TMP1; #else /* !CONFIG_SOFTMMU */ a_bits =3D get_alignment_bits(opc); if (a_bits) { @@ -3934,7 +3946,8 @@ static void tcg_target_init(TCGContext *s) #if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS =3D=3D 64 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ #endif - tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */ + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1); tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2); if (USE_REG_TB) { --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921828; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h7T6BCs08xsWhjirpyWfdNuX6EmPKpgX+sbsQPFTCEs=; b=nGQX48TJNDiSuqHWv/0uj7cUucF5+Ija8/ftVm6no7sbUp58zURB2Je8Yy01TsVkt1 x+O4q01fLFWNYUXJFoPY7oOKNovS9kATa3fSegfq3a5128YveroaXiPa2iM3yzIs3Hum Ry8SIHnXDSvQaBH9BaNFs/FtKX3TSgdrb3SJKihxJ2ETZOev/4XQMedwEsrTMaolQWYD 3CICSfy73NFZqYWDv/07INJ2qkinHqUSjdk7MOPuiOaCr+K2vlyNa5OdZ0xC0jK+cV7j 96chaS/kJv1j5kGRxN1cBsdtX9cM8fe4ep8tx39MxER2URd9ZsZynjhLfMWeDadfRK4e ma2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921828; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h7T6BCs08xsWhjirpyWfdNuX6EmPKpgX+sbsQPFTCEs=; b=AT1mfAVubpp+qxs3VPtb7wTH2EEeiQ8PMiSGTiLWW3SZv3MsV3HIn5BGdLB2iiZTFF +arFlfeVvaCtwSdEwsYl2L/fpTsrElyGhWq6EX6kdf95nW9mKpJDtlqjNmuzpnOWJk1E cQ36CZCFwd6xE2qZrZTsHlXAUC1OUxEFaEUFuYg5E7RhcIjASwunBNxzg4JD1eTEIZmn simnp+uLr1umUWZBdSdGGmXCHj6vyLF3s2TTU5E2dkz+uyDzbyUONW/T2hJv716IkZoQ fSxsLPxxJgoUOlDIE3JO4hB3SLB1Jqv+LvGHSvrvN9mbeTtSd2NTBjTVzEhP5t0Vew2s rdcw== X-Gm-Message-State: AAQBX9dLJ7+UzDqldc7wQHxCs9pjSUJrqDW92dXwQg1ObQhb7a7gHXJD 4e+8KmSLftnBNPY2SiIRBgmGGuUJqc7XsqD0px4= X-Google-Smtp-Source: AKy350aGv0M25UkLGwk0Ifo3s4EMdr5QNRJ3yzcwn8pupvQ9Z8l5LD90Bzyyu7OxiS1WFZKeIbsVqg== X-Received: by 2002:a17:902:f213:b0:1a5:2592:89c6 with SMTP id m19-20020a170902f21300b001a5259289c6mr993185plc.29.1680921828586; Fri, 07 Apr 2023 19:43:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 36/42] tcg/ppc: Adjust constraints on qemu_ld/st Date: Fri, 7 Apr 2023 19:43:08 -0700 Message-Id: <20230408024314.3357414-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922347184100003 Content-Type: text/plain; charset="utf-8" The softmmu tlb uses TCG_REG_{TMP1,TMP2,R0}, not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h | 11 ++++------- tcg/ppc/tcg-target-con-str.h | 2 -- tcg/ppc/tcg-target.c.inc | 32 ++++++++++---------------------- 3 files changed, 14 insertions(+), 31 deletions(-) diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h index a1a345883d..f206b29205 100644 --- a/tcg/ppc/tcg-target-con-set.h +++ b/tcg/ppc/tcg-target-con-set.h @@ -12,18 +12,15 @@ C_O0_I1(r) C_O0_I2(r, r) C_O0_I2(r, ri) -C_O0_I2(S, S) C_O0_I2(v, r) -C_O0_I3(S, S, S) +C_O0_I3(r, r, r) C_O0_I4(r, r, ri, ri) -C_O0_I4(S, S, S, S) -C_O1_I1(r, L) +C_O0_I4(r, r, r, r) C_O1_I1(r, r) C_O1_I1(v, r) C_O1_I1(v, v) C_O1_I1(v, vr) C_O1_I2(r, 0, rZ) -C_O1_I2(r, L, L) C_O1_I2(r, rI, ri) C_O1_I2(r, rI, rT) C_O1_I2(r, r, r) @@ -36,7 +33,7 @@ C_O1_I2(v, v, v) C_O1_I3(v, v, v, v) C_O1_I4(r, r, ri, rZ, rZ) C_O1_I4(r, r, r, ri, ri) -C_O2_I1(L, L, L) -C_O2_I2(L, L, L, L) +C_O2_I1(r, r, r) +C_O2_I2(r, r, r, r) C_O2_I4(r, r, rI, rZM, r, r) C_O2_I4(r, r, r, r, rI, rZM) diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h index 298ca20d5b..f3bf030bc3 100644 --- a/tcg/ppc/tcg-target-con-str.h +++ b/tcg/ppc/tcg-target-con-str.h @@ -14,8 +14,6 @@ REGS('A', 1u << TCG_REG_R3) REGS('B', 1u << TCG_REG_R4) REGS('C', 1u << TCG_REG_R5) REGS('D', 1u << TCG_REG_R6) -REGS('L', ALL_QLOAD_REGS) -REGS('S', ALL_QSTORE_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 7195c0b817..dc4e88db8e 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -93,18 +93,6 @@ #define ALL_GENERAL_REGS 0xffffffffu #define ALL_VECTOR_REGS 0xffffffff00000000ull =20 -#ifdef CONFIG_SOFTMMU -#define ALL_QLOAD_REGS \ - (ALL_GENERAL_REGS & \ - ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5))) -#define ALL_QSTORE_REGS \ - (ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \ - (1 << TCG_REG_R5) | (1 << TCG_REG_R6))) -#else -#define ALL_QLOAD_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3)) -#define ALL_QSTORE_REGS ALL_QLOAD_REGS -#endif - TCGPowerISA have_isa; static bool have_isel; bool have_altivec; @@ -3780,23 +3768,23 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_qemu_ld_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O1_I1(r, L) - : C_O1_I2(r, L, L)); + ? C_O1_I1(r, r) + : C_O1_I2(r, r, r)); =20 case INDEX_op_qemu_st_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O0_I2(S, S) - : C_O0_I3(S, S, S)); + ? C_O0_I2(r, r) + : C_O0_I3(r, r, r)); =20 case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) - : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(L, L, L) - : C_O2_I2(L, L, L, L)); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) + : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(r, r, r) + : C_O2_I2(r, r, r, r)); =20 case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(S, S) - : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(S, S, S) - : C_O0_I4(S, S, S, S)); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(r, r) + : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(r, r, r) + : C_O0_I4(r, r, r, r)); =20 case INDEX_op_add_vec: case INDEX_op_sub_vec: --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922020; cv=none; d=zohomail.com; s=zohoarc; b=Z7nj8fhYRup3z+7Vg1+r6WhBWburw8i42oN+9xgtSntLyvHhUx8z6NnfU6BvYtf9VcTC5eFC7KyVXDsqjAbMcY0Na3O/X/CBo9a7I1v7o8TzO8C4Jju+5mVCeSd6A4WIWlkS3oMvlzT3Z3+tFV41nx1wse5NYO7Q1VKruDz26tU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680922020; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7nPBJFUV0lX54ZMpUCSnQezprz128nst/H5IYSZCsHw=; b=gdMw3G6Gr3RT1tuWbXomJchKHOJhXIQ27DtXwwYUjnfqic1bGU5VFvz5qSWIT7iOzRitFP9MuGr5hJ8XJCcqLbfb2Hx4FpAhAjDPOhxjxPEb8Xn0gb9jdaylF8WGuQ801dTh2DALbGYQutgplsfkUDUZoECZOoBjDLm8q068a5E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680922020980977.774958839482; Fri, 7 Apr 2023 19:47:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyZP-00013n-DS; Fri, 07 Apr 2023 22:44:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyZ6-0008Vd-EE for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:35 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyYR-0005sw-3F for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:32 -0400 Received: by mail-pl1-x634.google.com with SMTP id h24so511879plr.1 for ; Fri, 07 Apr 2023 19:43:50 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921829; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7nPBJFUV0lX54ZMpUCSnQezprz128nst/H5IYSZCsHw=; b=TiS/X/9z9vAJ/AtN9LcuqJIn24hK/cJn0T0PsWujj1S3NELmozS0gYIje3V4giix8p dyVCe/9d9Y/v+E93aJA0ZyJSqDYRY3DYYvKoSWOmuLJLEo+0YIqBI1EpmpZ0Qa7ImuKu sc9EBXYaWug5Z7whvvZFeb40QoyH+2v3Zre5HfUcekxIb8VlSmrd6oeO35D/DGQk36eL qSTQfBKTbFAx93uhYwm0vC80EH4i/DFxxxFIJ2BcxWm8ly24t+dtAFbX8TARZbZ23Mld fY1AtLxDLkJ9uP9/m1G/duCoUxrekaiGD5Swi6rB/fAZvnVSgHnUZftMKqv4v+c7yyXT 8Acw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921829; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7nPBJFUV0lX54ZMpUCSnQezprz128nst/H5IYSZCsHw=; b=eyTLU1S35Ps2m+pD5FcKNLWwAV5BOjWKOE0sS4DN0XHNAeRBVy85IabuAGQUxhaRFS OJnP2EqwKj5HXPnuD6Fj1US0KnyTFPEIgr+0/axT7Lyx8vgi4b/+ZR6cxLQnEnIA7+1I 36kjZTwkJiHUB4PMmNvRCMpuktIUgwE4CJZYH1nrFFX4BAjCck7yyvam9a3YNgLOILh7 /gDM7LsGcqQ8WS25f2L7NklAj9LnKqsI82kpRVHi6YsnPIHUpOOXuicrOGsOiVgRqmFe ZeYSgAMedIqm/degeZ6bQ9s3lIE28mdVpLGu5hIQ9kBfLUG8lYK8DPrw77RH2Km0myw/ vEkw== X-Gm-Message-State: AAQBX9dPYtXTwr1sE6Yx61jBrt0OT+u2M7sHDxVQYBhicOHTgvni7Jy8 ThPE1g1BIzJg2pftGvP/k1Bcm3hQMfyUNsPV+jE= X-Google-Smtp-Source: AKy350YKdtVvB+Swi+dxev+Yib3LVfkuU3Kb8v59yfk8fKFQ0eZYUD1YXMB3Z+eKzp2a/J7sjYXmag== X-Received: by 2002:a17:903:228d:b0:1a1:f5dd:2dde with SMTP id b13-20020a170903228d00b001a1f5dd2ddemr656762plh.44.1680921829385; Fri, 07 Apr 2023 19:43:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 37/42] tcg/ppc: Remove unused constraints A, B, C, D Date: Fri, 7 Apr 2023 19:43:09 -0700 Message-Id: <20230408024314.3357414-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922021620100002 Content-Type: text/plain; charset="utf-8" These constraints have not been used for quite some time. Fixes: 77b73de67632 ("Use rem/div[u]_i32 drop div[u]2_i32") Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-str.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h index f3bf030bc3..9dcbc3df50 100644 --- a/tcg/ppc/tcg-target-con-str.h +++ b/tcg/ppc/tcg-target-con-str.h @@ -10,10 +10,6 @@ */ REGS('r', ALL_GENERAL_REGS) REGS('v', ALL_VECTOR_REGS) -REGS('A', 1u << TCG_REG_R3) -REGS('B', 1u << TCG_REG_R4) -REGS('C', 1u << TCG_REG_R5) -REGS('D', 1u << TCG_REG_R6) =20 /* * Define constraint letters for constants: --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922224; cv=none; d=zohomail.com; s=zohoarc; b=BVi8KssipMa5H5fKRDkVJJtiO+SuSmajRg10d6TQCeI6CZL7OZbisY04knovrUq4mfC+AG8RQeCxDtAQDXGSArnoftIil/nPgBobtr4noxL764F3qCGkt2K9olKCQZ01m0FoDQSzutaT9fayM1EE92wRwHYJFB7UTDmNw4CDlXU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680922224; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=u3QvbuMmLJFN66+AgerJ4hDVUqG975uEhSCFouk7XB4=; b=Uxpec4x1m5tdfTKY89rrncxDtkMWhc7Lb5SXSHFvkM7JHTY2EradWGWxN9gHGMTS3jCIimVl7uvNXHJfsajAJ2LlpSGcvKHlvf0kvXLJr/YYZy4i6OZu3c5HZzPd3vTOwAd72Fi/F8l91X2JfiJT6Cccxrv4hosdu1CH+EKav/k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16809222245861011.1098045954384; Fri, 7 Apr 2023 19:50:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyZT-0001Zf-7W; Fri, 07 Apr 2023 22:44:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyZB-0000BT-Or for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:44 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyYb-0005ft-GC for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:44:37 -0400 Received: by mail-pj1-x1029.google.com with SMTP id v9so5046771pjk.0 for ; Fri, 07 Apr 2023 19:43:50 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921830; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u3QvbuMmLJFN66+AgerJ4hDVUqG975uEhSCFouk7XB4=; b=ZdSWsa6ERlfHiTwam0IQTYjTL62Eq74YZIMXCeXBvP/ME89ZlRUlqB5ZFbNJbov+ZE Q+1LDauE8R/aoEm/zXUFr5e1Fxq62FVH+RSJo/Zkmy85AyNU+Xv5midE3bZJLqlOLPsX R5qwJ9id6YPcJpTvGNNV/6oda6uPWUuKBFE6Kd+rUIowu6FTFMLUavvHTcUa3qbU/J/c pvXg5PV/0VGP/fUSbAjM273gK+FaKTrqBCjxe+Ghqes88VS5CV6YNWO+2AnonpPbm069 JABdgPdYNXOCSRjcsF0ArTCnDxYIAAqcgp0irOu4jdPTmXWuOmQGUkyz+2WcN1/vAd/3 /4Dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921830; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u3QvbuMmLJFN66+AgerJ4hDVUqG975uEhSCFouk7XB4=; b=qx0AAKd2+ZdhM5fkJraMdZGDZ77Ku2iShZ5DFLxVTny45Kt1BFjQW2SWkE5CDPAvtk wJWmxR2n1x6b8IpjUuODqMl6VFhSW+Zk7yJ97/iA9rJuxAcetJunewvDnOfsSUHz+kL4 CrYyFhC7AkQVQDIV1RNQTq0q9JmvASQDox0eDHacl7srthm4O6xKngk9GyKDYRQnC8Jk fRDg5+nLKxZi9qPtljre/d6Po4m9UGoV82xBfSX25a8HWymwGhDW6NYtBZiBcIwAif/D qCRKGmr5HCUlavgaAwsjYzb4ImL6uQDLcV1t3sQzN7yqTwsZNjE5vb+PjLvjV6ZdJgdW /xMw== X-Gm-Message-State: AAQBX9edZQSNIPgLqwH7lGHqxxKNLeE3pur8+0Ce/Wj7r0QEY3YONnKo WwSF6yqm4xuQfJr0vTQnJ7k9ZNybD42IWjEEItE= X-Google-Smtp-Source: AKy350avgOZzqLI0Z4wOlxccbqMIa01nBBS+jFX/TE/+7qVLZl3AyexzbX/1iI9oW1adtGPYCuPfZA== X-Received: by 2002:a17:902:ec83:b0:1a1:dd05:39fe with SMTP id x3-20020a170902ec8300b001a1dd0539femr823556plg.4.1680921830263; Fri, 07 Apr 2023 19:43:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 38/42] tcg/riscv: Simplify constraints on qemu_ld/st Date: Fri, 7 Apr 2023 19:43:10 -0700 Message-Id: <20230408024314.3357414-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922226667100007 Content-Type: text/plain; charset="utf-8" The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 2 -- tcg/riscv/tcg-target-con-str.h | 1 - tcg/riscv/tcg-target.c.inc | 16 +++------------- 3 files changed, 3 insertions(+), 16 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index c11710d117..1a8b8e9f2b 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -10,11 +10,9 @@ * tcg-target-con-str.h; the constraint combination is inclusive or. */ C_O0_I1(r) -C_O0_I2(LZ, L) C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) C_O0_I4(rZ, rZ, rZ, rZ) -C_O1_I1(r, L) C_O1_I1(r, r) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h index 8d8afaee53..6f1cfb976c 100644 --- a/tcg/riscv/tcg-target-con-str.h +++ b/tcg/riscv/tcg-target-con-str.h @@ -9,7 +9,6 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) -REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index ab70aa71a8..45a4bc3714 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -125,17 +125,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKi= nd kind, int slot) #define TCG_CT_CONST_N12 0x400 #define TCG_CT_CONST_M12 0x800 =20 -#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) -/* - * For softmmu, we need to avoid conflicts with the first 5 - * argument registers to call the helper. Some of these are - * also used for the tlb lookup. - */ -#ifdef CONFIG_SOFTMMU -#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5) -#else -#define SOFTMMU_RESERVE_REGS 0 -#endif +#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) =20 #define sextreg sextract64 =20 @@ -1654,10 +1644,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return C_O1_I1(r, L); + return C_O1_I1(r, r); case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i64: - return C_O0_I2(LZ, L); + return C_O0_I2(rZ, r); =20 default: g_assert_not_reached(); --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922338; cv=none; d=zohomail.com; s=zohoarc; b=Sq3chuXF1lxf9fKyl6q0vfkES5m0aSV0BY1xjekevC0u+AUJY2rUciNPJGg5tmXTL/BoFWDWwDY7TWNGD1ZiquGKFC6sN8kI1eWOJP30zxxuE8hH+l93LDQZPHphPjR0YfVooSeUdYjYu3DXmpeJGxRx1uuCqWVoaWGRWVCeY2A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680922338; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=U3GgpyquLQob+XRXyWgnv31s/PrsIm2aDbl8H8cAcdI=; b=FV6+gNwaqlIkr0AorGemyzHOMefzN/bDUWiI4pI0yb1Fggi0QCdPHAPC9OZKrCdAVr01kUy1OYyxngPKVs9RSyMNJ59mgJT1tEIqlVMirM01eu1zMMkw54tYBj6udwdR8w+Y/170dhUak8Nk/DJUDf2TulIf92VliluUnKGYZZM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16809223388705.300336076034; Fri, 7 Apr 2023 19:52:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkybV-0003eY-GN; Fri, 07 Apr 2023 22:47:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkybQ-00034c-Ln for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:46:56 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkybN-0007mW-1H for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:46:56 -0400 Received: by mail-pl1-x631.google.com with SMTP id la3so205459plb.11 for ; Fri, 07 Apr 2023 19:46:52 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id k16-20020a170902761000b0019aa8149cc9sm3551981pll.35.2023.04.07.19.46.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:46:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680922011; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=U3GgpyquLQob+XRXyWgnv31s/PrsIm2aDbl8H8cAcdI=; b=l63T0M/V0iYGfYGWtNcXzE4Gt1VySSif84TJXZrITNNiJd49pcV85U/uX6922iUN4M UkFVfZhx9NZrohCaUZERwV3RS7A8ELtiPWt8TuSg1/JxnCIcs3dXzlpg1vQxR1A0cY3O MEHvia/+AMIRsE3NCQp2F/6YAXQA92LEVXIIAAA+QvnFa1nOlguuZYagIJF2UEb2ElK/ BO3uiV0KDg79C8vS+OHABK7G9NjlMVuviqbOV1FcMIOG+OY0kItBs2A1l5Mo3JrCkTyc 9rvuM/is0LPtqE95FzfUlzpPN2In8XjHpbt4PgznB698mN1hpv8SHLOn+pfZkbJcrtc3 lYLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680922011; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U3GgpyquLQob+XRXyWgnv31s/PrsIm2aDbl8H8cAcdI=; b=2dVUNut88PNiTVeTxMwovFvyC2TSBEx7njIOLQMqNqV2KLwg54rn536g2VibSRKWke AN8UpUwAf8pKgGZVtw8aUD5vHKDDkKTQ2Y0HAqB73TbIpaMP0LBEv5DS3xk9QJPg3CVE 19me8vlbL8uXRX2P62u+an3NgrlCy97roN/2acsC9z8Jl1vnUMURQPHNTJwlYWl1P170 UhR4iNPLsoSwEDfgBOeEHz8zLdrfhwosayTQwyRifwvlLbFpiNTiLp2XRt2bhnJYJC0k rUeh4UluIfFHGCq4//EqWipKMD+f6mYsunztXjJiIGour94rZrXoMFeIRzQPGuRf/J1X vOLg== X-Gm-Message-State: AAQBX9c8QLln2whY7PrgQ1b+iQMXhNBqRaYKuYdLj/aLEy4Z+OtT2DK2 8WzMwkyRIekIVO8KZHAVld1gyC0gnhaNvh6cqMQ= X-Google-Smtp-Source: AKy350YDKKgt8izzlMeQ/HgUizkAM5xC4rBi5aZ+ZFsb/X4WNTIurMkClVGfBEW67Ly1wEPHbGJwsQ== X-Received: by 2002:a17:902:e0d4:b0:1a1:d655:1ce4 with SMTP id e20-20020a170902e0d400b001a1d6551ce4mr3891401pla.38.1680922011406; Fri, 07 Apr 2023 19:46:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 39/42] tcg/s390x: Use ALGFR in constructing host address for qemu_ld/st Date: Fri, 7 Apr 2023 19:43:11 -0700 Message-Id: <20230408024314.3357414-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922339089100001 Content-Type: text/plain; charset="utf-8" Rather than zero-extend the guest address into a register, use an add instruction which zero-extends the second input. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 7d6cb30a06..b53eb70f24 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -149,6 +149,7 @@ typedef enum S390Opcode { RRE_ALGR =3D 0xb90a, RRE_ALCR =3D 0xb998, RRE_ALCGR =3D 0xb988, + RRE_ALGFR =3D 0xb91a, RRE_CGR =3D 0xb920, RRE_CLGR =3D 0xb921, RRE_DLGR =3D 0xb987, @@ -1716,8 +1717,10 @@ static void tcg_out_qemu_st_direct(TCGContext *s, Me= mOp opc, TCGReg data, QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); =20 -/* Load and compare a TLB entry, leaving the flags set. Loads the TLB - addend into R2. Returns a register with the santitized guest address. = */ +/* + * Load and compare a TLB entry, leaving the flags set. + * Loads the TLB addend and returns the register. + */ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc, int mem_index, bool is_ld) { @@ -1761,12 +1764,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg= addr_reg, MemOp opc, =20 tcg_out_insn(s, RXY, LG, TCG_REG_R2, TCG_REG_R2, TCG_REG_NONE, offsetof(CPUTLBEntry, addend)); - - if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_ext32u(s, TCG_REG_R3, addr_reg); - return TCG_REG_R3; - } - return addr_reg; + return TCG_REG_R2; } =20 static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, @@ -1888,16 +1886,20 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg d= ata_reg, TCGReg addr_reg, #ifdef CONFIG_SOFTMMU unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; - TCGReg base_reg; + TCGReg addend; =20 - base_reg =3D tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1); + addend =3D tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1); =20 tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); label_ptr =3D s->code_ptr; s->code_ptr +=3D 1; =20 - tcg_out_qemu_ld_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0); - + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_insn(s, RRE, ALGFR, addend, addr_reg); + tcg_out_qemu_ld_direct(s, opc, data_reg, addend, TCG_REG_NONE, 0); + } else { + tcg_out_qemu_ld_direct(s, opc, data_reg, addend, addr_reg, 0); + } add_qemu_ldst_label(s, 1, oi, d_type, data_reg, addr_reg, s->code_ptr, label_ptr); #else @@ -1920,16 +1922,20 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg d= ata_reg, TCGReg addr_reg, #ifdef CONFIG_SOFTMMU unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; - TCGReg base_reg; + TCGReg addend; =20 - base_reg =3D tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0); + addend =3D tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0); =20 tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); label_ptr =3D s->code_ptr; s->code_ptr +=3D 1; =20 - tcg_out_qemu_st_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0); - + if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_insn(s, RRE, ALGFR, addend, addr_reg); + tcg_out_qemu_st_direct(s, opc, data_reg, addend, TCG_REG_NONE, 0); + } else { + tcg_out_qemu_st_direct(s, opc, data_reg, addend, addr_reg, 0); + } add_qemu_ldst_label(s, 0, oi, d_type, data_reg, addr_reg, s->code_ptr, label_ptr); #else --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922355; cv=none; d=zohomail.com; s=zohoarc; b=N8CDOcxGQuJ/TR4CFOb9q4AGysNNqZgwJMkUZ9kFdkQ3j36U2C3VJbv0iqohdWZ1vF4YIp0zaVfU0nErFnicR/bkSKIUy387eVrmT92Ynnxl94+nF42n8ioREj64a/0n4G5ZWZo0o9tKegwLwoQmXLqd3/W0yMlhm7Y95VkQcIE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680922355; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SrQW4Aeu2V1q+r0Fl22IATDZGwActs9RT4mXhJ6VIuc=; b=i4CY+vnU218BfOBJsnYhm9IUM0aoETEGW4Mf0+cAiiMFrEo5Ak+iThONt0XNs9mZ/bLQsdi5xZCHXy7Kguhpwkisr4eqqv20pIB3RVBvQ5XyYv/T21KfFaXRLDAOgYEwmEW2vqKcc7912YRNy8miD1mK7lKiLpR/e2uMirzvOY4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680922355810673.9353960815497; Fri, 7 Apr 2023 19:52:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkybV-0003i5-PU; Fri, 07 Apr 2023 22:47:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkybQ-00034l-Mh for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:46:56 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkybN-0007n4-W9 for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:46:56 -0400 Received: by mail-pl1-x635.google.com with SMTP id p8so429002plk.9 for ; Fri, 07 Apr 2023 19:46:53 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id k16-20020a170902761000b0019aa8149cc9sm3551981pll.35.2023.04.07.19.46.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:46:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680922012; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SrQW4Aeu2V1q+r0Fl22IATDZGwActs9RT4mXhJ6VIuc=; b=qbbHNMaoBsurhe1dnFYCc9EFptqz22KzTJkIyFB5L4GQLTlM7FctU/qH4WSmWhnsXe HBiQmPOYb6l3j83ZDqdTiI8HN23csCdgJJDkIhpkUDnQa6Z6SK6+SHoXv9T+R1Yhg3WZ fdwNpGcx0nv/x5c0txfi5yFhLYM0s+vADpXVzzp5kcKUONc16A4Af5v8RjoNurCvJ45f NPu+KBTgvTfqGZedJ2vq9SWDluMz43OtpZg19hk4aC030t41YSRknpjec6YsdR1iBKhP /Rl/9Ea6UJqAtU0qnOQU/eLcasEqGnsOiheJ5G5tRTXEzyM5YzFRWnj8tT+Khp4EIyRS N21Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680922012; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SrQW4Aeu2V1q+r0Fl22IATDZGwActs9RT4mXhJ6VIuc=; b=2Mw76KSq0rTXeqpaHWMHGUuAWLexdRQZPVZWCOdohaSaOF3axZax/WP0euPd/Ev+L/ bujdvxVr8DckRFNcTuYhQnNa7GxemTn+3vyP7Ab/oE473NlKrg/YoNo4/VjB6PAWsDuR C3YHVB38vA4KAjn+hFbI1YeSLZXJeEOLDFxlw+FKqBO4TN4nEcypdWDfoCUbgkN3Hjmv a7ZWwl0L3AivcefdqhGXqvdw+Y6gL5nNHyIENcCyIvNlCpoNgTfAoWTC12s97Fx172zf NCS3lCI31+EkkD/XqWGv9wqv3kk8FC2uNhwXP569zMs19rAMjvmyiHV5Fgy62pBhqrcS 8ZqA== X-Gm-Message-State: AAQBX9eBkSW+C0maSSIZfjcdmClzGDuoCLyL7VH5goe5HD3ySjo4UsuI FhGZjU5t4YWP7sijlctl8SFhhp6Xf4+4pmx6TLA= X-Google-Smtp-Source: AKy350YqAe155VuDs32Nbfl/J3fiWy0APgFnJ3s2WHtBTxYs/wzy6xb/r0nWcz+XmprpAnImcwgZPw== X-Received: by 2002:a17:902:d50a:b0:1a1:e39c:d4d1 with SMTP id b10-20020a170902d50a00b001a1e39cd4d1mr497509plg.67.1680922012334; Fri, 07 Apr 2023 19:46:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 40/42] tcg/s390x: Simplify constraints on qemu_ld/st Date: Fri, 7 Apr 2023 19:43:12 -0700 Message-Id: <20230408024314.3357414-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922357002100001 Content-Type: text/plain; charset="utf-8" Adjust the softmmu tlb to use R0+R1, not any of the normally available registers. Since we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 2 -- tcg/s390x/tcg-target-con-str.h | 1 - tcg/s390x/tcg-target.c.inc | 36 ++++++++++++---------------------- 3 files changed, 12 insertions(+), 27 deletions(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index 15f1c55103..ecc079bb6d 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -10,12 +10,10 @@ * tcg-target-con-str.h; the constraint combination is inclusive or. */ C_O0_I1(r) -C_O0_I2(L, L) C_O0_I2(r, r) C_O0_I2(r, ri) C_O0_I2(r, rA) C_O0_I2(v, r) -C_O1_I1(r, L) C_O1_I1(r, r) C_O1_I1(v, r) C_O1_I1(v, v) diff --git a/tcg/s390x/tcg-target-con-str.h b/tcg/s390x/tcg-target-con-str.h index 6fa64a1ed6..25675b449e 100644 --- a/tcg/s390x/tcg-target-con-str.h +++ b/tcg/s390x/tcg-target-con-str.h @@ -9,7 +9,6 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) -REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) REGS('v', ALL_VECTOR_REGS) REGS('o', 0xaaaa) /* odd numbered general regs */ =20 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index b53eb70f24..64033fb957 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -44,18 +44,6 @@ #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16) #define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) =20 -/* - * For softmmu, we need to avoid conflicts with the first 3 - * argument registers to perform the tlb lookup, and to call - * the helper function. - */ -#ifdef CONFIG_SOFTMMU -#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_R2, 3) -#else -#define SOFTMMU_RESERVE_REGS 0 -#endif - - /* Several places within the instruction set 0 means "no register" rather than TCG_REG_R0. */ #define TCG_REG_NONE 0 @@ -1734,10 +1722,10 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addr_reg, MemOp opc, int ofs, a_off; uint64_t tlb_mask; =20 - tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE, + tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - tcg_out_insn(s, RXY, NG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, mask_off= ); - tcg_out_insn(s, RXY, AG, TCG_REG_R2, TCG_AREG0, TCG_REG_NONE, table_of= f); + tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_off); + tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_off); =20 /* For aligned accesses, we check the first byte and include the align= ment bits within the address. For unaligned access, we check that we do= n't @@ -1745,10 +1733,10 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addr_reg, MemOp opc, a_off =3D (a_bits >=3D s_bits ? 0 : s_mask - a_mask); tlb_mask =3D (uint64_t)TARGET_PAGE_MASK | a_mask; if (a_off =3D=3D 0) { - tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask); + tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); } else { - tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off); - tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask); + tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off); + tgen_andi(s, TCG_TYPE_TL, TCG_REG_R0, tlb_mask); } =20 if (is_ld) { @@ -1757,14 +1745,14 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGRe= g addr_reg, MemOp opc, ofs =3D offsetof(CPUTLBEntry, addr_write); } if (TARGET_LONG_BITS =3D=3D 32) { - tcg_out_insn(s, RX, C, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs); + tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); } else { - tcg_out_insn(s, RXY, CG, TCG_REG_R3, TCG_REG_R2, TCG_REG_NONE, ofs= ); + tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); } =20 - tcg_out_insn(s, RXY, LG, TCG_REG_R2, TCG_REG_R2, TCG_REG_NONE, + tcg_out_insn(s, RXY, LG, TCG_TMP0, TCG_TMP0, TCG_REG_NONE, offsetof(CPUTLBEntry, addend)); - return TCG_REG_R2; + return TCG_TMP0; } =20 static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, @@ -3181,10 +3169,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: - return C_O1_I1(r, L); + return C_O1_I1(r, r); case INDEX_op_qemu_st_i64: case INDEX_op_qemu_st_i32: - return C_O0_I2(L, L); + return C_O0_I2(r, r); =20 case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922362; cv=none; d=zohomail.com; s=zohoarc; b=SP22RNnVOeycV6MwOgBzI2DWWVetSidDp/FsN/NAwWLsqwLxnNS4hj4O82WeeHqyuACOUr2GkwmmWqD+ZkhNIIACLD8I9VqyTZsGhVlsDOGt/kZ7/Mmv1Cj6Avfh9X2VZV65WHafIaZVDy2Y5LrcMpgwlvaenJQUGz/B4ULGHUs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680922362; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=U3GQzefZ28zb/sjvcPHPQ2WB6aIN+aVY6R/9kd6URaA=; b=HuSw0IS/ow6DLvN5Ki6irDcqGKh5Vr6I/LjaWecoS0GDNkZWicRO3TPoJnMsGwUjJszfkZ+bO61y/fLL5nF7oUJBa8f1zTD4+g9mxcwlLOcqbhxAp1LTeHFahjIlfBX1zffXC7CuTqg6opl/rE/e95W8HZax5Io4m2iZradKE8E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680922362636429.3092824901365; Fri, 7 Apr 2023 19:52:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkybT-0003S4-Qa; Fri, 07 Apr 2023 22:46:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkybS-0003DN-1Z for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:46:58 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkybO-0007nV-LW for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:46:57 -0400 Received: by mail-pl1-x632.google.com with SMTP id ke16so309557plb.6 for ; Fri, 07 Apr 2023 19:46:54 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id k16-20020a170902761000b0019aa8149cc9sm3551981pll.35.2023.04.07.19.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:46:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680922013; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=U3GQzefZ28zb/sjvcPHPQ2WB6aIN+aVY6R/9kd6URaA=; b=z6r62+fR/fU9gnjqCuewDYj2jsptEwsSt4+1T3QR6Pttrr7zcQPPNZZmje0/TBUugf 9BkCKiFn99uTcUMXUYS1MrzZUMTbsIipo5TqrX4p7VSyZYtZe/or8P9wusfJN2QpeM4p HfSL3YGo6j1AtrKOzMeWUwLl2TmJLfGvJyQVzc5+C9H8YrGgphA/D80LHTgE7ApfbVwG nijMPLraV/rKqToM6REOgwYIoHIQ5bpCrRpx6y6AsoXRPBwP4Dspaky1pHirQ1CalHE4 nh0NzDTIRXSwqGV4zu2BlkgNO3fKHmvBzOz2U7EIqr9bR6m6zLI1CPZzrDceOLIJqvjG umJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680922013; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U3GQzefZ28zb/sjvcPHPQ2WB6aIN+aVY6R/9kd6URaA=; b=i7thvEvS4ftW+edAfDzpVrQp4mQfZuLUdVsHeI6SOGY9RB/0qqAXUOzL55aM70hKY2 OCYtg7f1xXxb3xvKCUQa9bOyx7OmQuEcv5H8PYzJ4JO1lrasmsI1DAqiepMUSzpOdHH7 8hPNFkogoIVBVPWJRat4OsOEj64u71zMcBvTFnUDmTuOW0IUlhNC7lYQ73LeWVyZh6xf r43nUWuTkRvr9m9ySoM8pClxbj/qgFDYbX7BV59u+b0kLBc4X09iAmOU7ySSfBbi70/9 DgBZzuh9AFs+YMkP04hBHK5MohSaCbGVEYSFRQT4ITzykgPXXdPfHAvnLKgtKLPnUglF sBYg== X-Gm-Message-State: AAQBX9fYGfJaV6x1O8aTs+oDkHHsp1jtVzDKTOR/O5einuyow2dJzavY VnCf/dyZP37J/K719Ttj/9iM+SNbrWUtYGzFpnw= X-Google-Smtp-Source: AKy350Z3kpXNpfENXndLFsh9hxlTB3fKZ0TROt4ee7btuDEa2E+aC2Wxzraq+AdjO1zNy25YLMoZZw== X-Received: by 2002:a17:902:d50a:b0:1a1:e39c:d4d1 with SMTP id b10-20020a170902d50a00b001a1e39cd4d1mr497545plg.67.1680922013184; Fri, 07 Apr 2023 19:46:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 41/42] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return Date: Fri, 7 Apr 2023 19:43:13 -0700 Message-Id: <20230408024314.3357414-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922363773100001 Content-Type: text/plain; charset="utf-8" In tcg_canonicalize_memop, we remove MO_SIGN from MO_32 operations with TCG_TYPE_I32. Thus this is never set. We already have an identical test just above which does not include is_64 Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 086981f097..f3e5e856d6 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1220,7 +1220,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a, TCGReg addr, tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_O2, oi); =20 /* We let the helper sign-extend SB and SW, but leave SL for here. */ - if (is_64 && (memop & MO_SSIZE) =3D=3D MO_SL) { + if ((memop & MO_SSIZE) =3D=3D MO_SL) { tcg_out_ext32s(s, data, TCG_REG_O0); } else { tcg_out_mov(s, TCG_TYPE_REG, data, TCG_REG_O0); --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680922195; cv=none; d=zohomail.com; s=zohoarc; b=MPaaHa9efEMxTpzqRJJ7JwTz1oZiB1Td9nAcoMY/2V2qZc+qAeHPKpb8RlwtyHE6peEYmuAVM6wcU/crmg7jjOX/Rq2T94cvkIGkZXNXEXM38QNXsBnmOJr/Vt7fvkVBgl02Mcj57STF43ocvcdJRs1qLpROu8jjoe7vTj2qEF8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680922195; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=i9b6w9gWvCthNszMWt3+LpRjnTOnldmnZfV8N9JLl1Q=; b=jUfM6xiXyVNI82ANL27j+08SC6xaZy+l6AOSiEcWNgKaaccD6sgIsANnTLd1u0a+8E8OCCccr+s4EDq6p73eI9WLxI95MozaD7Wy8BVL12eyjE5KzL2K6X2UC6DsGJHIIwoVZws5tPeGgTkbhycRsnVFLDiHYcB5y7k5DIk007A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680922195413409.21190612904707; Fri, 7 Apr 2023 19:49:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkybZ-000486-JI; Fri, 07 Apr 2023 22:47:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkybT-0003RK-N6 for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:46:59 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkybP-0007o1-Dt for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:46:59 -0400 Received: by mail-pj1-x1029.google.com with SMTP id r21-20020a17090aa09500b0024663a79050so1799886pjp.4 for ; Fri, 07 Apr 2023 19:46:54 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id k16-20020a170902761000b0019aa8149cc9sm3551981pll.35.2023.04.07.19.46.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:46:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680922014; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=i9b6w9gWvCthNszMWt3+LpRjnTOnldmnZfV8N9JLl1Q=; b=mNqwgYQxaqFP05iSLGzuLd83cPZq4R+/hfCKIZS9ZdZ9yoYtHZYv8AutYLN8pLpMJA JoEsqJXY2DGdoXMQvpNu+LEzuhoo/yIrL8eZdsj3MhiQ0b5yuJ5h94tu+1J/GGbYt0ou Lz7YACRgSDN/Lton69PVNJuBrbheW+KRiw3Rt4Ze5QWFaS9cqM7hoxCDx3rL9xXRQule jKieLkzOY79x1yPVsVdY2nDfgTi+O/5V8VQuFmDAHmLEO/ujNTaMxsOnfITIUa+MpMqV lm+4bA8322Vk2iJ7heiwVRQwpl99Uxe/zW/VIlqfF3xHRZfzjby1aze25vlLUJUPaA0l Mn6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680922014; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i9b6w9gWvCthNszMWt3+LpRjnTOnldmnZfV8N9JLl1Q=; b=pjtlwiDpK6z6JdPJM0cNbeouyyYGM3pjB9yh9gwS0HKtBy2tpQx0mK62y1v0AyTIDE YS0Gfn7NGO6bIehlFLxr/UVjnak/u7dzELcb7P8HQSZ8Xjl9i16hRiFslm3sLkQaLfNj T5bH/iKWxfbvVuY7PzAFm4VsuKkxaEg1TnAvNPxqmC1whLm0FyASckck3EMZCtJGYfP6 BCTxejNrbfB/hUb4unI2RYn5Ed00RSeN9iTMtd9NgFkCklmCfVGw4yk016fJ14NXsQUC dY61XzyK+b6yEOqIntP89PHGB9T7itzKxvg+qCmQSRgL0OdFCOWviuuIHzZE/GTW5zBr mH+w== X-Gm-Message-State: AAQBX9eeYXhlImIiOiSuKQCcw0uYLIpyuVfB60P/Arka5k1BcDLKP625 U12MXO0673qw6IhM8SHoqU2FEYu38qV/mj7muxY= X-Google-Smtp-Source: AKy350afekGrs4Ilr5JSxEjrIeMg3QO5lc9jGk4llK0z0wI8yIvW6lzOaKbnr5QBDXk8HNSgbarVXw== X-Received: by 2002:a17:902:ce8e:b0:1a2:56f4:d369 with SMTP id f14-20020a170902ce8e00b001a256f4d369mr793479plg.19.1680922014054; Fri, 07 Apr 2023 19:46:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 42/42] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st} Date: Fri, 7 Apr 2023 19:43:14 -0700 Message-Id: <20230408024314.3357414-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922197032100003 Content-Type: text/plain; charset="utf-8" We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index f3e5e856d6..05fc65faac 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1178,7 +1178,7 @@ static const int qemu_st_opc[(MO_SIZE | MO_BSWAP) + 1= ] =3D { }; =20 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, - MemOpIdx oi, bool is_64) + MemOpIdx oi, TCGType d_type) { MemOp memop =3D get_memop(oi); tcg_insn_unit *label_ptr; @@ -1324,7 +1324,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a, TCGReg addr, } =20 static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, - MemOpIdx oi, bool is64) + MemOpIdx oi, TCGType d_type) { MemOp memop =3D get_memop(oi); tcg_insn_unit *label_ptr; @@ -1351,8 +1351,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= a, TCGReg addr, =20 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_O1, addrz); tcg_out_movext(s, (memop & MO_SIZE) =3D=3D MO_64 ? TCG_TYPE_I64 : TCG_= TYPE_I32, - TCG_REG_O2, is64 ? TCG_TYPE_I64 : TCG_TYPE_I32, - memop & MO_SIZE, data); + TCG_REG_O2, d_type, memop & MO_SIZE, data); =20 func =3D qemu_st_trampoline[memop & (MO_BSWAP | MO_SIZE)]; tcg_debug_assert(func !=3D NULL); @@ -1637,16 +1636,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, a0, a1, a2, false); + tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, a0, a1, a2, true); + tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); break; case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, a0, a1, a2, false); + tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, a0, a1, a2, true); + tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); break; =20 case INDEX_op_ld32s_i64: --=20 2.34.1 From nobody Wed May 15 20:26:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1680921906; cv=none; d=zohomail.com; s=zohoarc; b=JTeE62Np2afKjQj7ZvqLvAYxRGrRYZK9iP7KlTzP2qrhXpYI5E59f/MdIdhMTbJP79D8WR7edn+fH+qR1r83qPPWlY0YgbLpvKQ9RNYh5xkm82g1B+SUWRuTs5U9qd1Dv9u7apuljQ6RzYKQ0HeyS/kAfB9oyQlqpNmKGgJnGaU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680921906; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rcNEhGFLchqZMB3huLw45XXaPWISEFJfrSvpuPV2BPc=; b=VUHEWD1vZxoib8jsTLOW6wPaTMHHku6344azH0/ewS8imCI3uNgiI2cgPfOv+zgYEI4sBc/NjKyDFhGqu3IcbpIJO2NdVuyKJPqO3qLVnqXzwjIor2Z7lvtnEVM3XL/WEr6L/hwV48aBNpLRZc+JNNahASfwYGMQX5XR+zoQ1iI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680921906027332.61476310660396; Fri, 7 Apr 2023 19:45:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkyXz-0006x1-Gn; Fri, 07 Apr 2023 22:43:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkyXy-0006vM-6U for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:43:22 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkyXt-0005Wo-MQ for qemu-devel@nongnu.org; Fri, 07 Apr 2023 22:43:21 -0400 Received: by mail-pl1-x62b.google.com with SMTP id e13so56707plc.12 for ; Fri, 07 Apr 2023 19:43:17 -0700 (PDT) Received: from stoup.. ([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921796; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rcNEhGFLchqZMB3huLw45XXaPWISEFJfrSvpuPV2BPc=; b=Ea1zZYA0y6DU1+Jpk3XYzqWFvMO+AsIyzT5p0CZL7dUA/MpgPrTLPHQlxxWoNkempS X9MT4q+4VuYPzo7OcJXGP+PTuDdVH8riWLRr7CtGHbkafQ47ETQOHtsnRl59TPodpW6I EPOSlxf/IAmKkoofGDfUiPNIPv5T5i1lPES3JqOIfHWb+vpehaBEeqMvFXytmlRQzsGB jcl6KmkbAjr8P2bjBz1ZwFWy/rVJdU0q5YFOiadGHD4HzrIE/okBTXSJ8SIHHzBbJD58 d/sUkyq/0D54H27FNVV4jwZz75Kn3T1hn5YvNJs+WblO/fIKuemmmpW3g/YjkSa/NRwP aGyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921796; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rcNEhGFLchqZMB3huLw45XXaPWISEFJfrSvpuPV2BPc=; b=nVPZCqTF8+F4Hcf/OA4wmH4p7Mm0EulqnhGHN4UVV3OfvEsGX5JzGMnIHPKJmloyPO DKC5qdaaxMrC6FrQwUv51MnsxBPJTYEKKQYetX8rCT/s/0myJzTam1enuRUZl5foGftj lyYweRu/9qmiw7kQeuB9bFFSkU6CJQPL13Y2xMGqmrAlIOkCtQ6b8GzyNff9UVfY6gBa Eif9SwyUoIHcpdEKN9qubHiAxaMXB2TpvqsE+Z3cviShy2V9BaQwTxX19SzYh9psPesd JnCYO/4IRBBoB5ktKwg9QYmQR5n5j/ZQw1iQohLzmiZo8UuKxb0B0SOLXcFhoVdhxL4h Z4nw== X-Gm-Message-State: AAQBX9d1G9tgw6upGTnrABoWjp7WawgMJSvUzicB7VJ1tfcxPuJU/D/q 9KtfO+amNgflQZKIlrLF0ffvB7IMhbS6oYcKfPI= X-Google-Smtp-Source: AKy350Yhn0srUEmNpjRdUNHsBk0rxPoNMgBroWV9RbErYZ5rsf/orDoLJWpM25sEP7TyIe9HbSzmEg== X-Received: by 2002:a17:902:f94d:b0:1a1:f95a:2505 with SMTP id kx13-20020a170902f94d00b001a1f95a2505mr8481645plb.29.1680921796286; Fri, 07 Apr 2023 19:43:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH for-8.0] tcg/i386: Adjust assert in tcg_out_addi_ptr Date: Fri, 7 Apr 2023 19:42:32 -0700 Message-Id: <20230408024314.3357414-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680921907209100001 Content-Type: text/plain; charset="utf-8" We can arrive here on _WIN64 because Int128 is passed by reference. Change the assert to check that the immediate is in range, instead of attempting to check the host ABI. Fixes: 6a6d772e30d ("tcg: Introduce tcg_out_addi_ptr") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1581 Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 4444eb9234..5a151fe64a 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1082,7 +1082,7 @@ static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd= , TCGReg rs, tcg_target_long imm) { /* This function is only used for passing structs by reference. */ - tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); + tcg_debug_assert(imm =3D=3D (int32_t)imm); tcg_out_modrm_offset(s, OPC_LEA, rd, rs, imm); } =20 --=20 2.34.1