From nobody Wed May 15 04:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680804289; cv=none; d=zohomail.com; s=zohoarc; b=gRcwb0mAZiSH3eDrtOiXhNTplN+JFnugLPUdPMnbcPGdnEEykRfOK9THIr6Td1+UgdyzCCT7185oGrLX6+Hjd+auq62RoQO2birbyNanfVqDNtRBgeIaudbm7OLvjfU+i0pGFfzf9xFkad66klTFDarpA+SlDKsHL+joVRHCPKo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680804289; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zfsRr9xhp36UswUhHh+RTCS39W4vDYCkTwWBjY7Jfk8=; b=nE2JE4KAS6pqYWaDZXvAsWFWPo1ZUlMhG7twP+BWGwb+BG3tzPGwhn9np8XuoEblHpnkC1H+HyGbPY8gM6Lao1D+pCDYxnzfa4nMmgOJTHwU4hfO8OJbs1ldmdQPuO27SAzjNmd6VrAqKT+09gyobV8Y9TKC1awss5mOjAKbWVQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680804289646605.9485514848316; Thu, 6 Apr 2023 11:04:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkTxv-0000ts-Mv; Thu, 06 Apr 2023 14:04:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkTxt-0000st-JZ for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:05 -0400 Received: from mail-oa1-x2e.google.com ([2001:4860:4864:20::2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkTxr-0000a4-PK for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:05 -0400 Received: by mail-oa1-x2e.google.com with SMTP id 586e51a60fabf-17aceccdcf6so43189657fac.9 for ; Thu, 06 Apr 2023 11:04:03 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.03.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804242; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zfsRr9xhp36UswUhHh+RTCS39W4vDYCkTwWBjY7Jfk8=; b=hf8QPKi4psUYIb0u0N+TlZJCKPevliqv5IOYYDpNUo59WXOUgiVkbUvcZO3uHxL7kL tAVQSx+uu4bot4XUgCJlktGRUu0XXYD8lbaw6dp1EeAXqYyoQdesEV/pB5W3r7tL2G8V d4SAOPWiCW0e3fpdHNB8fQGB+GtPuznrUn0QNaNaIu3tGbNUPCd5IIF5GSh9Gpu0k1nZ C0LlDAD8hkhBIlRHg+vVGhtvIzjPk1kUJZc97Ghr9ZIHXPIKdFQjZFjFnTIyE4ySJcsO sQ3EN5CdmiVo48RLE5jjBc5rMqZrno8+Rezgmv21/7THeSh/lUrEbTeVWMcIiFfq3i2d e/3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804242; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zfsRr9xhp36UswUhHh+RTCS39W4vDYCkTwWBjY7Jfk8=; b=BcygcgLL3V9JzKOxpACMoRk9F4vIMdEUOj2BszUKJYvhCHXSTQMh6hqiaTdnqfBugx HAmcKv2E1KMLxd3OzwSOloAQyLCEo3rBKYsCsGvFmQzShQZE1C8G0gZQWwWAJMb8iqCM 9gO4LZ1ZypqL4DTbqpv2TgPbOfYhqILYeM/FKyriog3T7KHAESu2KpZ8oOcbNAuI1t1p PGULVHrJu2BhymXMF0uEzNSyh3NDnzvsbSdZf4GmRoX1OXH9N1nPOVl6orF/6JMs6Vp1 k68kYffAk9+yiSjiYBJzkba6ukF5xuFYWIModkQirmmHLN0A4kLeI6OgCH3GSb0BO7dx qXpw== X-Gm-Message-State: AAQBX9c5oi3LNg7znhr9vCf9kcFbYzfxlC/e2rxWPcLVxzT3EXhag667 bwXvUUd/tcgyz8qsNfcwJY31LP0YCIdHeQPfnH8= X-Google-Smtp-Source: AKy350ZzCZ14E5NfaFJ0SI72dL3JIxdxob6wdw+mLUt0Ndjj5vG/QcMr/VujghVWX0ix8v/9FShaCg== X-Received: by 2002:a05:6870:63a1:b0:17e:99b9:c238 with SMTP id t33-20020a05687063a100b0017e99b9c238mr125158oap.18.1680804242226; Thu, 06 Apr 2023 11:04:02 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 01/20] target/riscv: sync env->misa_ext* with cpu->cfg in realize() Date: Thu, 6 Apr 2023 15:03:32 -0300 Message-Id: <20230406180351.570807-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804291136100003 Content-Type: text/plain; charset="utf-8" When riscv_cpu_realize() starts we're guaranteed to have cpu->cfg.ext_N properties updated. The same can't be said about env->misa_ext*, since the user might enable/disable MISA extensions in the command line, and env->misa_ext* won't caught these changes. The current solution is to sync everything at the end of validate_set_extensions(), checking every cpu->cfg.ext_N value to do a set_misa() in the end. The last change we're making in the MISA cfg flags are in the G extension logic, enabling IMAFG if cpu->cfg_ext.g is enabled. Otherwise we're not making any changes in MISA bits ever since realize() starts. There's no reason to postpone misa_ext updates until the end of the validation. Let's do it earlier, during realize(), in a new helper called riscv_cpu_sync_misa_cfg(). If cpu->cfg.ext_g is enabled, do it again by updating env->misa_ext* directly. This is a pre-requisite to allow riscv_cpu_validate_set_extensions() to use riscv_has_ext() instead of cpu->cfg.ext_N to validate the MISA extensions, which is our end goal here. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 94 +++++++++++++++++++++++++++------------------- 1 file changed, 56 insertions(+), 38 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cb68916fce..66de3bb33f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -811,12 +811,11 @@ static void riscv_cpu_disas_set_info(CPUState *s, dis= assemble_info *info) =20 /* * Check consistency between chosen extensions while setting - * cpu->cfg accordingly, doing a set_misa() in the end. + * cpu->cfg accordingly. */ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; - uint32_t ext =3D 0; =20 /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && @@ -831,6 +830,9 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) cpu->cfg.ext_d =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; + + env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; + env->misa_ext_mask =3D env->misa_ext; } =20 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { @@ -1022,39 +1024,8 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) cpu->cfg.ext_zksh =3D true; } =20 - if (cpu->cfg.ext_i) { - ext |=3D RVI; - } - if (cpu->cfg.ext_e) { - ext |=3D RVE; - } - if (cpu->cfg.ext_m) { - ext |=3D RVM; - } - if (cpu->cfg.ext_a) { - ext |=3D RVA; - } - if (cpu->cfg.ext_f) { - ext |=3D RVF; - } - if (cpu->cfg.ext_d) { - ext |=3D RVD; - } - if (cpu->cfg.ext_c) { - ext |=3D RVC; - } - if (cpu->cfg.ext_s) { - ext |=3D RVS; - } - if (cpu->cfg.ext_u) { - ext |=3D RVU; - } - if (cpu->cfg.ext_h) { - ext |=3D RVH; - } if (cpu->cfg.ext_v) { int vext_version =3D VEXT_VERSION_1_00_0; - ext |=3D RVV; if (!is_power_of_2(cpu->cfg.vlen)) { error_setg(errp, "Vector extension VLEN must be power of 2"); @@ -1092,11 +1063,6 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) } set_vext_version(env, vext_version); } - if (cpu->cfg.ext_j) { - ext |=3D RVJ; - } - - set_misa(env, env->misa_mxl, ext); } =20 #ifndef CONFIG_USER_ONLY @@ -1181,6 +1147,50 @@ static void riscv_cpu_finalize_features(RISCVCPU *cp= u, Error **errp) #endif } =20 +static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) +{ + uint32_t ext =3D 0; + + if (riscv_cpu_cfg(env)->ext_i) { + ext |=3D RVI; + } + if (riscv_cpu_cfg(env)->ext_e) { + ext |=3D RVE; + } + if (riscv_cpu_cfg(env)->ext_m) { + ext |=3D RVM; + } + if (riscv_cpu_cfg(env)->ext_a) { + ext |=3D RVA; + } + if (riscv_cpu_cfg(env)->ext_f) { + ext |=3D RVF; + } + if (riscv_cpu_cfg(env)->ext_d) { + ext |=3D RVD; + } + if (riscv_cpu_cfg(env)->ext_c) { + ext |=3D RVC; + } + if (riscv_cpu_cfg(env)->ext_s) { + ext |=3D RVS; + } + if (riscv_cpu_cfg(env)->ext_u) { + ext |=3D RVU; + } + if (riscv_cpu_cfg(env)->ext_h) { + ext |=3D RVH; + } + if (riscv_cpu_cfg(env)->ext_v) { + ext |=3D RVV; + } + if (riscv_cpu_cfg(env)->ext_j) { + ext |=3D RVJ; + } + + env->misa_ext =3D env->misa_ext_mask =3D ext; +} + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -1216,6 +1226,14 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) set_priv_version(env, priv_version); } =20 + /* + * We can't be sure of whether we set defaults during cpu_init() + * or whether the user enabled/disabled some bits via cpu->cfg + * flags. Sync env->misa_ext with cpu->cfg now to allow us to + * use just env->misa_ext later. + */ + riscv_cpu_sync_misa_cfg(env); + /* Force disable extensions if priv spec version does not match */ for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && --=20 2.39.2 From nobody Wed May 15 04:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680804479; cv=none; d=zohomail.com; s=zohoarc; b=eAQoCG6JDtQlPDe22L/e5ydsySyYUrSoEWMWyCcojg0/mWO420xKA5nn+X8Zuy2LfsrFauVvY1fW2UxyOBvrsQxX83LfpsxVTQojc27HHpHN+W19dz6B+qt7GOa201CqfsvklcF8TdfQ99Df3B3jdu/hPIlAh9Hia0NasmnHGpo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680804479; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ufyvyScFDwHTPmPsfLa8yROo1ql9YOF/CnHfsvDkUMU=; b=jbVDsZInzuZtjN2i+selAKiyiBvFQ6ajcDlRrfIfJRKvdTlsVHCcPtFrYLhPR9o4ixD7xW87Q+Ud6DkZwrIecZKo2BEk17H8WPzAV8KCK0TgSRPa4Hef2k3GW34iNQa9iwSpQTReG0HeqUY1tpErHHOKaq8imJ5ZDO4LfVwT+Hk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680804479521139.15043207768554; Thu, 6 Apr 2023 11:07:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkTxx-0000ui-Ou; Thu, 06 Apr 2023 14:04:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkTxw-0000uP-1k for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:08 -0400 Received: from mail-oa1-x2e.google.com ([2001:4860:4864:20::2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkTxu-0000a4-F7 for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:07 -0400 Received: by mail-oa1-x2e.google.com with SMTP id 586e51a60fabf-17aceccdcf6so43189804fac.9 for ; Thu, 06 Apr 2023 11:04:06 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804245; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ufyvyScFDwHTPmPsfLa8yROo1ql9YOF/CnHfsvDkUMU=; b=X0KW4LQ6OysqUHobZwQ3GKGy1zzzyWao4RA1yJEL2mUogk9d1dOnf9Xj+2woDtH+j2 lAF029ApLDIMNHD3TF3shkU/G4/qoiDn3RtbZW+WzYsdr/TahnyzYMuv1wQgaloTZapx IBOiL3Xw9yJ/jMY1wbkoaQ6krlDyEDaLpkbfO7+ogTpfrUdnz3zOueCDijQnRps1+MnO tTAzK0VFPRtd1CryiRqZy++IH/B60pAQXhvgcSvm9D9Nrbj9F2Vc8MlH8jvwA6HhQgcO TxWkfV+W/cvZ3yIvtrtqDM2Qjw3Gt2a1Ay7Im66PNl5Nd+RZLvETu58TBJ6NiGApwSZC nZng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804245; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ufyvyScFDwHTPmPsfLa8yROo1ql9YOF/CnHfsvDkUMU=; b=4YIYU9h7sNsY9Ah6eO9fnFFQsjJyz4bKlJUXP+Y4nUXeW4qjdMR/mvG9NgPvOwTBv7 xFw9AcPsLng/y0tHpI6I9X7si6Txlc5wjLRok/kMN3+oJkn2G68rlNQF5yXAk7dpgeDd USo8J9PCgc4WDdtedF87BYpPR4+r3JmBzfInYL95N2jAoyPiQj23+fEZPYyqvrgQKyW1 a//wnDFFTmA3Fh1GSiMcbgV8VQSaQtHcuIU/2YKJmx2EVtFnvqQhxc3Euiq+LPG6uH5W CgplDil7+pQk3Wrw0u0uM0G2iKfjpRDyTg2r6uJWm3PMMPH3KIPfIjCZDfeUdHMcIAlH 3NIA== X-Gm-Message-State: AAQBX9dMGH/wo1EDldhuc5bMjSygBpQnGrVuiuf7Y6f/UMlZDRP+HBkF 2+X1ntUQBe+2IIa6IuQm/kTeKypPpfMklxVNsRc= X-Google-Smtp-Source: AKy350YIGovIxwIiR1g/r+9m6MrpmXFXEBL7KyQ3GuIxwrKVLhZVxLiplqEqwv+Qv1j3729zyqPe5g== X-Received: by 2002:a05:6871:9b:b0:177:9e9e:ff47 with SMTP id u27-20020a056871009b00b001779e9eff47mr143565oaa.17.1680804245497; Thu, 06 Apr 2023 11:04:05 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 02/20] target/riscv: remove MISA properties from isa_edata_arr[] Date: Thu, 6 Apr 2023 15:03:33 -0300 Message-Id: <20230406180351.570807-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804480003100005 Content-Type: text/plain; charset="utf-8" The code that disables extensions if there's a priv version mismatch uses cpu->cfg.ext_N properties to do its job. We're aiming to not rely on cpu->cfg.ext_N props for MISA bits. Split the MISA related verifications in a new function, removing it from isa_edata_arr[]. We're also erroring it out instead of disabling, making the cpu_init() function responsible for running an adequate priv spec for the MISA extensions it wants to use. Note that the RVV verification is being ignored since we're always have at least PRIV_VERSION_1_10_0. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 66de3bb33f..ed8f36c649 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -72,10 +72,11 @@ struct isa_ext_data { * 4. Non-standard extensions (starts with 'X') must be listed after all * standard extensions. They must be separated from other multi-letter * extensions by an underscore. + * + * Single letter extensions are checked in riscv_cpu_validate_misa_priv() + * instead. */ static const struct isa_ext_data isa_edata_arr[] =3D { - ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), - ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v), ISA_EXT_DATA_ENTRY(zicbom, true, PRIV_VERSION_1_12_0, ext_icbom), ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz), ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond), @@ -1191,6 +1192,14 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *e= nv) env->misa_ext =3D env->misa_ext_mask =3D ext; } =20 +static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) +{ + if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { + error_setg(errp, "H extension requires priv spec 1.12.0"); + return; + } +} + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -1234,6 +1243,12 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) */ riscv_cpu_sync_misa_cfg(env); =20 + riscv_cpu_validate_misa_priv(env, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + /* Force disable extensions if priv spec version does not match */ for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && --=20 2.39.2 From nobody Wed May 15 04:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680804389; cv=none; d=zohomail.com; s=zohoarc; b=LyjkP1yK7YXGsJgm9j66E+CVGtqCGH0dZEsPktATdCbnHicY6D53LW52yw+LyLVDQ4BnxH8RQE6fXZ12cUp0yD33/AodJN13i/TBbRj/YUxwr+736aGhRPCSmcXcroIyLPWl2yH8J6H7jdarTJphaaqkrJnwDphWufbumauAhuQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680804389; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Icj8LJrcjPq3IF6xteJO3s06K22LZ2lAQ/eG3IMJq7M=; b=JtD3YJg/EHdDgM8oHXK4EJ3U2X9wnNBQ0pIFUnzJakbEVGsBVM0VvD7e/EsDT0iCRrbzhZpimTb3uJRG3tlq8n4ghAYBzODwOwPKGr0pVPXnnBY5Ft5F4z1X9RJBhCMEGbmKLoodc1KBoe53QTNWbRtjgGAk1IiIl3eo7iErZG4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680804389893699.9522507112172; Thu, 6 Apr 2023 11:06:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkTy4-0000yk-Rd; Thu, 06 Apr 2023 14:04:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkTy2-0000yC-BP for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:14 -0400 Received: from mail-oa1-x32.google.com ([2001:4860:4864:20::32]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkTxz-0000an-1r for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:13 -0400 Received: by mail-oa1-x32.google.com with SMTP id 586e51a60fabf-17e140619fdso43206782fac.11 for ; Thu, 06 Apr 2023 11:04:09 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804249; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Icj8LJrcjPq3IF6xteJO3s06K22LZ2lAQ/eG3IMJq7M=; b=Lcr9cnXN5CaX7rTPcS2q68stKp58dDvKzIYEayC3nDziSKZ7DB425p3DjSDjFDadD2 CSDclfdwoq3Nqy5IL1ZrgLo8rkBQoNR+C6Zsfw1ab8fF7Bqrd0E9xxEOocycA5saYg69 TJmt+pPUnvH0WFiCmNH+OQ+1VRoBqRIP0Q0B6vUPlPMMSOnkGvRySNPkOKE+xG88bP9L ZZ4MdtXu48CW8//GjJyNgKn0WKbU4wLB4hfVI48NYBMlIPWZ/+688KALrp/Aw0KCCrV5 8v55w7qF+EUcN/0cs66ZcKxI35K5mHy16cIqwDcAaHH75lg4MCFZlzEQ9fWfnslPhI8+ 59LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804249; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Icj8LJrcjPq3IF6xteJO3s06K22LZ2lAQ/eG3IMJq7M=; b=ZCJ7jdZHIK2vCqOY/sOCmexSvgRRbEGlyQOhVFD/1iv6kBNwkbWjcxKLk+rJBMqPHC T9LW9LQXptSn8j/nGCHqshI7kN+gI+k2872wjfVurB+QD0PlCgcACO4F7i67Ah58zD5o bRdIvv2N/HxEeGMOQfC9OoZMQBjC0ykrmAulGaLrPA3UOmnz2/KfNzmH56+MaqQXmjeB FdgNXCYzr7NMk5rQ/DFQmv2Adr+3zKy6eXbjl7jRyWpamtbHP52bP9+ssNQE7IjDJNUJ h4DVnPYMcbgsHJbAIoLEEbxilpequCOLBDdy6NyubeilGNb1EOMiOwzkyjTwVrO4uqgT z0KA== X-Gm-Message-State: AAQBX9f5ueVRrFNW7I9tKxXfbykwPT7oyqNIbtVz2h1EZwYIOZAognhL Oe/2nhWqa5bsqAMuwHN9LWohw+QFiG6nDhLtDGA= X-Google-Smtp-Source: AKy350ZZeMogHyo9jc5OMBPdcNnmksJBx8mBfNGD3YWd7EM62yocaHXGThs5faYTr9BaIsTj3wIIHA== X-Received: by 2002:a05:6870:148c:b0:183:fc80:7362 with SMTP id k12-20020a056870148c00b00183fc807362mr159165oab.2.1680804248816; Thu, 06 Apr 2023 11:04:08 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 03/20] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data Date: Thu, 6 Apr 2023 15:03:34 -0300 Message-Id: <20230406180351.570807-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804392160100003 Content-Type: text/plain; charset="utf-8" We don't have MISA extensions in isa_edata_arr[] anymore. Remove the redundant 'multi_letter' field from isa_ext_data. Suggested-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 132 ++++++++++++++++++++++----------------------- 1 file changed, 65 insertions(+), 67 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ed8f36c649..fbf612292a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -48,13 +48,12 @@ static const char riscv_single_letter_exts[] =3D "IEMAF= DQCPVH"; =20 struct isa_ext_data { const char *name; - bool multi_letter; int min_version; int ext_enable_offset; }; =20 -#define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ - {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} +#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ + {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} =20 /* * Here are the ordering rules of extension naming defined by RISC-V @@ -77,68 +76,68 @@ struct isa_ext_data { * instead. */ static const struct isa_ext_data isa_edata_arr[] =3D { - ISA_EXT_DATA_ENTRY(zicbom, true, PRIV_VERSION_1_12_0, ext_icbom), - ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz), - ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond), - ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), - ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), - ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintp= ause), - ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), - ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh), - ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_11_0, ext_zfhmin), - ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), - ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), - ISA_EXT_DATA_ENTRY(zca, true, PRIV_VERSION_1_12_0, ext_zca), - ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb), - ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf), - ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd), - ISA_EXT_DATA_ENTRY(zce, true, PRIV_VERSION_1_12_0, ext_zce), - ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp), - ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt), - ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), - ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), - ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), - ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), - ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), - ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), - ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), - ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), - ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), - ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), - ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), - ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), - ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), - ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), - ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), - ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), - ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), - ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_10_0, ext_zve32f), - ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_10_0, ext_zve64f), - ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_10_0, ext_zve64d), - ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh), - ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin), - ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), - ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), - ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), - ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), - ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), - ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), - ISA_EXT_DATA_ENTRY(svadu, true, PRIV_VERSION_1_12_0, ext_svadu), - ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), - ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), - ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), - ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), - ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), - ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), - ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo= ), - ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xthea= dcondmov), - ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xthea= dfmemidx), - ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv= ), - ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac= ), - ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xthead= memidx), - ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xthea= dmempair), - ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsy= nc), - ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVe= ntanaCondOps), + ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), + ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), + ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), + ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), + ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), + ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), + ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), + ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh), + ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin), + ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx), + ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx), + ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca), + ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb), + ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf), + ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd), + ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce), + ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp), + ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt), + ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba), + ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb), + ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc), + ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb), + ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc), + ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx), + ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs), + ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk), + ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn), + ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd), + ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne), + ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh), + ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr), + ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks), + ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), + ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), + ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), + ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), + ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), + ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), + ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), + ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), + ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), + ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), + ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), + ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), + ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), + ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), + ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), + ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), + ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), + ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), + ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), + ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo), + ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondm= ov), + ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemi= dx), + ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv), + ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac), + ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx= ), + ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempa= ir), + ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), + ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaC= ondOps), }; =20 static bool isa_ext_is_enabled(RISCVCPU *cpu, @@ -1741,8 +1740,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char = **isa_str, int i; =20 for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_edata_arr[i].multi_letter && - isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { + if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { new =3D g_strconcat(old, "_", isa_edata_arr[i].name, NULL); g_free(old); old =3D new; --=20 2.39.2 From nobody Wed May 15 04:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680804289; cv=none; d=zohomail.com; s=zohoarc; b=aTgd8hkYKI3W10z3qt61XXL02Gb2LHKSo8Se/Tk4xjQxfWHWTnvkV9PUQqEPZK4qXXCnf+okDv5VnMAN1VVZ401whA16dLShEGjUQB97fN3uHeBgy95vTk85OqbGV1mlhIH8TKiwq5uiFLltZiwHcXWeokru3YaOBPTgRN6lV/A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680804289; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gwHVgVMzQCDJB5vK9WQl9LSOsUrvo+0sTqi3vha+yuc=; b=TwY6dqx2yXZkmTXOivZs738R8E9Kfb9C7wbKJf0daSxtcLJcNMcFFdOqbtr9sTgR3yLnb0pq+7lOI0DUmAhapmIqZXUpAbujXXgZQPRHQvyZQHdaM4QNx267O3OCJnduV4yocbwckdzPti9VpwIehxc+/d2RhV6uWhjDh8ON/dY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680804289696212.02881735108917; Thu, 6 Apr 2023 11:04:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkTy9-00010A-2N; Thu, 06 Apr 2023 14:04:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkTy6-0000z9-Ks for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:18 -0400 Received: from mail-oa1-x32.google.com ([2001:4860:4864:20::32]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkTy2-0000bw-OJ for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:17 -0400 Received: by mail-oa1-x32.google.com with SMTP id 586e51a60fabf-17aeb49429eso43236735fac.6 for ; Thu, 06 Apr 2023 11:04:13 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804251; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gwHVgVMzQCDJB5vK9WQl9LSOsUrvo+0sTqi3vha+yuc=; b=DTXmvRgXSEvpFJQOqLZYVBX/ts9TEra3l2MGUbsghhb3eSf2bdKFVYKhLzrco3yNUn OCv15cmPfHgc0FTjkfP+t/xoBTKdFQrflIlpb1dKl+IdIlWLx0gmSIf+mamnlCZiNAXl g02IJ7atjh+Svasy/U/TMoQXXWxbCBZ1pzqwaBDTFx7qoUmIqj0DECfvnz3Wlo9V1a5p 44KiZXwDyFZr1VL6JmYaJfjYR6t2E6k7BBlkDWfwH2DwU+Lij2vDYb//U4TzuX5XyC4m bq8Q9jvl/ZWtdrdltFvu979W9zfBP3n4td2EWw/qhJGzZlFknWSGU2F/ohQ9XGv1Zn+o fwNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804251; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gwHVgVMzQCDJB5vK9WQl9LSOsUrvo+0sTqi3vha+yuc=; b=JNevIeIAxYRrGJg2tjPlrUJWaqTxe/71aK+RRoWWZznV6L4awu0iGXRCZ2o/02HBee JEZw5iVmlbVd+EJsAF6ZDpkD6xzVPBxIcLottWr2JHPCJa2h9myIzMWmUU+h8K/wn6PG Le2UmwWHKckDRhF6AzyVU7bdL/zkWmeX7lGxfnbH1NiQC6ojUS0IPAecPaRvjInZEgEs CEQOka58dhRhmrCWSnrP9DS620gx1OHr375LMBcQJtZ5z5iQHUCntsBc0sz8iXAWvi83 kQgWVuFcKCwtBObu3NcR+twuXCgYto2U0vPt4bTts1ev7OZeuK99vlZ4/1vhfWNVGICF /jsQ== X-Gm-Message-State: AAQBX9d/4gQsZ5yExFUz+vPHZ1Jqh77IXTK/Q8tyMJYdSxfhjv9I2BK4 pYnvifK+QchKv1VDoW+ApD59PzcYMnYprhLMB8U= X-Google-Smtp-Source: AKy350bhtC6sNMMXK21aUubXjurcLlK9TseVKcRt93Vaxct6/fJnFvC5CGkY1DUhz7tZyRWRccbvjQ== X-Received: by 2002:a05:6870:2196:b0:177:9040:d236 with SMTP id l22-20020a056870219600b001779040d236mr106267oae.28.1680804251714; Thu, 06 Apr 2023 11:04:11 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 04/20] target/riscv: introduce riscv_cpu_add_misa_properties() Date: Thu, 6 Apr 2023 15:03:35 -0300 Message-Id: <20230406180351.570807-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804290904100001 Content-Type: text/plain; charset="utf-8" Ever since RISCVCPUConfig got introduced users are able to set CPU extensio= ns in the command line. User settings are reflected in the cpu->cfg object for later use. These properties are used in the target/riscv/cpu.c code, most notably in riscv_cpu_validate_set_extensions(), where most of our realize time validations are made. And then there's env->misa_ext, the field where the MISA extensions are set, that is read everywhere else. We need to keep env->misa_ext updated with cpu->cfg settings, since our validations rely on it, forcing us to make register_cpu_props() write cpu->cfg.ext_N flags to cover for named CPUs that aren't used named properties but also needs to go through the same validation steps. Failing to so will make those name CPUs fail validation (see c66ffcd5358b for more info). Not only that, but we also need to sync env->misa_ext with cpu->cfg again during realize() time to catch any change the user might have done, since the rest of the code relies on that. Making cpu->cfg.ext_N and env->misa_ext reflect each other is not needed. What we want is a way for users to enable/disable MISA extensions, and there's nothing stopping us from letting the user write env->misa_ext directly. Here are the artifacts that will enable us to do that: - RISCVCPUMisaExtConfig will declare each MISA property; - cpu_set_misa_ext_cfg() is the setter for each property. We'll write env->misa_ext and env->misa_ext_mask with the appropriate misa_bit; cutting off cpu->cfg.ext_N from the logic; - cpu_get_misa_ext_cfg() is a getter that will retrieve the current val of the property based on env->misa_ext; - riscv_cpu_add_misa_properties() will be called in register_cpu_props() to init all MISA properties from the misa_ext_cfgs[] array. With this infrastructure we'll start to get rid of each cpu->cfg.ext_N attribute in the next patches. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fbf612292a..3b234a03d0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1453,6 +1453,69 @@ static void riscv_cpu_init(Object *obj) #endif /* CONFIG_USER_ONLY */ } =20 +typedef struct RISCVCPUMisaExtConfig { + const char *name; + const char *description; + target_ulong misa_bit; + bool enabled; +} RISCVCPUMisaExtConfig; + +static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + const RISCVCPUMisaExtConfig *misa_ext_cfg =3D opaque; + target_ulong misa_bit =3D misa_ext_cfg->misa_bit; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + if (value) { + env->misa_ext |=3D misa_bit; + env->misa_ext_mask |=3D misa_bit; + } else { + env->misa_ext &=3D ~misa_bit; + env->misa_ext_mask &=3D ~misa_bit; + } +} + +static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + const RISCVCPUMisaExtConfig *misa_ext_cfg =3D opaque; + target_ulong misa_bit =3D misa_ext_cfg->misa_bit; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + bool value; + + value =3D env->misa_ext & misa_bit; + + visit_type_bool(v, name, &value, errp); +} + +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D {}; + +static void riscv_cpu_add_misa_properties(Object *cpu_obj) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { + const RISCVCPUMisaExtConfig *misa_cfg =3D &misa_ext_cfgs[i]; + + object_property_add(cpu_obj, misa_cfg->name, "bool", + cpu_get_misa_ext_cfg, + cpu_set_misa_ext_cfg, + NULL, (void *)misa_cfg); + object_property_set_description(cpu_obj, misa_cfg->name, + misa_cfg->description); + object_property_set_bool(cpu_obj, misa_cfg->name, + misa_cfg->enabled, NULL); + } +} + static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), @@ -1599,6 +1662,8 @@ static void register_cpu_props(Object *obj) return; } =20 + riscv_cpu_add_misa_properties(obj); + for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } --=20 2.39.2 From nobody Wed May 15 04:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680804476; cv=none; d=zohomail.com; s=zohoarc; b=nmqfDqt/5d9cs8kQODSJCGb/j3Y26CFeyKyMmOb1/xc1AbMFl4Zv85GK/7QYresHkNCg8KXtx74LI93Nmuw+PV4s6tOuc2rGzRRV6fKOMh+ztWGL+zCrJTNH2+k3uFbPXksklu7Lqy1NufQROK3MnD+2nDq3oyx/E4/g6VuIyfw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680804476; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2W7bGVL35Yc0UFJ+sEGELn4vLTKReJQVA0yDUn5MBBM=; b=AzrTaD7nFd3tPP1Ca+BwE4eMg64hQ3SKt80x44FX6dDQpGOZ0CJaaVSEYA2lFIfrKQeQJiNOCmRy5tDVqikWXO0DOQVF+wIODR/hHjGO6Cw23hNAxWIGB9uXd7Sdi42oo2cPGxAljwA9HvY/Ttuy7gpxUVrt95Kne6jyhUiHsmo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680804476265415.0710105238668; Thu, 6 Apr 2023 11:07:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkTyA-00010U-K3; Thu, 06 Apr 2023 14:04:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkTy8-000102-LL for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:20 -0400 Received: from mail-oa1-x2e.google.com ([2001:4860:4864:20::2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkTy6-0000cV-KG for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:20 -0400 Received: by mail-oa1-x2e.google.com with SMTP id 586e51a60fabf-17fcc07d6c4so29154669fac.8 for ; Thu, 06 Apr 2023 11:04:17 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804255; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2W7bGVL35Yc0UFJ+sEGELn4vLTKReJQVA0yDUn5MBBM=; b=SMHpaWSFqtU91jTW6Cl0C/3keH5J8sTNOlKTldTOCG+iIMLpAE+7IbisP6VHx2LRwb vZKc/xeDoNTP6HsF1FSdDx+3PVIv0rYZE9rI+fBqfJq/W5ihh2rlhHRtyGxy4T66oP9n XkRZTFwlBfMHJD6s9uRxOAU6G7MtECJzXIE5s7QCQaMSPs98e08cv81vnJq+DZUVAtQ8 GMTrRa0PVO/nK5A/cruIlR7TqqyOqVNaT9RXi7MUjxGCG2iluaXtoOxRuOjL+IiZ/Pl0 kI/XJ69JNzqd+dh9A7PFPsh8Epr7e53a2XsX4DL7xgM3YjvWc0ajG7lRVcWknrcuwl6l Jv8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804255; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2W7bGVL35Yc0UFJ+sEGELn4vLTKReJQVA0yDUn5MBBM=; b=oqTigdPsVMQVARU2TAVZ/OyE5E/zjxWySpp2fTgqG+ZX9ax8UkXpIsmrSwRL/Thcdt /lp/8MP2eFAZDS1Py1cUjFSBvQccOItcAOUIya8siGeHIQf/6NWH4j9IeoULlmf37TfD g27MB31catBMOHu9sMyUGUPgPjeasiNJAZGq2K3NLU9QfmXsTa05iFLlnrKBxSs/6IbT Ae5NJb4lbbez3+Do0FrW+J+8ftIGyL3EWHxrqTr0barIYJAsHLxlohk1aM86SgVe+4wn NivbKk9q4JbFna3HMswPj+4qAA2uZGrZh7/lVzX+dFUQxVsGYrkzG6aQ+RqmolDsozXN 5ovw== X-Gm-Message-State: AAQBX9dPwDmiamr6c6e5cAKJEneaF8vCyUaiaPRPurfqqnSJh5VgtoOK X8lwTVJgwNTKPDMuLbmMHFaiup5IeGnMdywewUo= X-Google-Smtp-Source: AKy350ZIvOyYqFqw03bZ15Nan5w7+1SyMWfxL3XFP9qdyPey6THgp/j8Pzca0TJH9p172s8ZnL8A2w== X-Received: by 2002:a05:6870:911f:b0:183:c9a0:ef36 with SMTP id o31-20020a056870911f00b00183c9a0ef36mr64998oae.40.1680804255245; Thu, 06 Apr 2023 11:04:15 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 05/20] target/riscv: remove cpu->cfg.ext_a Date: Thu, 6 Apr 2023 15:03:36 -0300 Message-Id: <20230406180351.570807-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804478190100003 Content-Type: text/plain; charset="utf-8" Create a new "a" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVA. Instances of cpu->cfg.ext_a and similar are replaced with riscv_has_ext(env, RVA). Remove the old "a" property and 'ext_a' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 16 ++++++++-------- target/riscv/cpu.h | 1 - 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3b234a03d0..3770fd4f6f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -819,13 +819,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) =20 /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && - cpu->cfg.ext_a && cpu->cfg.ext_f && - cpu->cfg.ext_d && + riscv_has_ext(env, RVA) && + cpu->cfg.ext_f && cpu->cfg.ext_d && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); cpu->cfg.ext_i =3D true; cpu->cfg.ext_m =3D true; - cpu->cfg.ext_a =3D true; cpu->cfg.ext_f =3D true; cpu->cfg.ext_d =3D true; cpu->cfg.ext_icsr =3D true; @@ -869,7 +868,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { + if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { error_setg(errp, "Zawrs extension requires A extension"); return; } @@ -1160,7 +1159,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_cpu_cfg(env)->ext_m) { ext |=3D RVM; } - if (riscv_cpu_cfg(env)->ext_a) { + if (riscv_has_ext(env, RVA)) { ext |=3D RVA; } if (riscv_cpu_cfg(env)->ext_f) { @@ -1496,7 +1495,10 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visito= r *v, const char *name, visit_type_bool(v, name, &value, errp); } =20 -static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D {}; +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { + {.name =3D "a", .description =3D "Atomic instructions", + .misa_bit =3D RVA, .enabled =3D true}, +}; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) { @@ -1522,7 +1524,6 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), - DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), @@ -1645,7 +1646,6 @@ static void register_cpu_props(Object *obj) cpu->cfg.ext_i =3D misa_ext & RVI; cpu->cfg.ext_e =3D misa_ext & RVE; cpu->cfg.ext_m =3D misa_ext & RVM; - cpu->cfg.ext_a =3D misa_ext & RVA; cpu->cfg.ext_f =3D misa_ext & RVF; cpu->cfg.ext_d =3D misa_ext & RVD; cpu->cfg.ext_v =3D misa_ext & RVV; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cbf3de2708..1d1a17d85b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -426,7 +426,6 @@ struct RISCVCPUConfig { bool ext_e; bool ext_g; bool ext_m; - bool ext_a; bool ext_f; bool ext_d; bool ext_c; --=20 2.39.2 From nobody Wed May 15 04:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680804327; cv=none; d=zohomail.com; s=zohoarc; b=Ap5IflnBHuUqZJ4q278ONL0s8/yvWSQ24Pl4OSF4WLPZm+ESMLDoB6hWgNGYk77KanKvSuSjD1ZQMvwz6veYmwNN6RhD4rGQciDcZVvgU58wcoLTrfnHmS2Rkntr8X5mQzWE4UWSIfV1nws4nWteGwcekz0lNUfvXuRTDIhHURU= ARC-Message-Signature: i=1; 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([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804258; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=U1J6FTvFFpDwL9i7EaiFwf0EbrXineCdby9XYALskoQ=; b=pGog8+EF/hKw/3gtveZzd8DvP6fr30K6C65ANRZBvHWj1R18KrRIWGveuDvtguhCoE 3E/nHmf2B+8PX/K0quIN0/ADDtghR8yOXepzSHR+gnDpwCO95Eo61nhrn7uFKwnSfYwr 03OLxB1PyUjGEO6zjaDmu+phvH+KV3Ml+Ra+PZlXFayZtt6GlD9mHosWNx4efzozNawC DKjZSqL0TG4whkjwn+9Tnydhv0pxAhBwrW7NQ9YcTmrpN/kTdvYmgOszJZoaDgPlp7ez qjDHRkbbDtJff97Buap0zJoQBbawlrkVIoJ6SSPhAEE7CJQQJrHAM2lv9tqVEmTVlW32 PHrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804258; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U1J6FTvFFpDwL9i7EaiFwf0EbrXineCdby9XYALskoQ=; b=iSUUyGc8kpmi6TJHoMrxtS0GgkcqF20O/qmHbDom+iE3Mf7lCtHThgD8vsYG9hdP+g ICoeCyAjZ+oFob9XzR0WRAycQ7o+kocvRWztcapsvKOs0y2Z3tyGiYzQbHh/GLhyeBAv QNzOWpebg9rQysRjCvTWDkfdlh9N7ZhdZNpk0q+nBmoAT93OJSMq96BzBTvlWusAId7j 6y0HZFT/B9Bz+hmxkV8h4THO0KRpmcXfmazhI89jMFu8aJV/t/kArb4Ns6AwbCz/y8hM 1bAThEAoY96742fk6mzy6rOUls9v+R+zOI8FjhB9EK4by6eHegouH0T9nVU/yNFB4DJA pLlQ== X-Gm-Message-State: AAQBX9fT9vMe2pkM9Cwg2K2jT5dR0YFSryvtkOr6DAw5aqAid0tzj+nu h3OoOqtr2vRQwLM9FM/G6nwAAsNmdGt1SuRAQUY= X-Google-Smtp-Source: AKy350ae4SLV4apv+M+OB7lO2pGIajUQA7udOmjAhAl84M+Mp/6srLgqXT00J1ELFDY40CFdbCfJoA== X-Received: by 2002:a05:6870:a11a:b0:177:b64e:517f with SMTP id m26-20020a056870a11a00b00177b64e517fmr148632oae.20.1680804258356; Thu, 06 Apr 2023 11:04:18 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 06/20] target/riscv: remove cpu->cfg.ext_c Date: Thu, 6 Apr 2023 15:03:37 -0300 Message-Id: <20230406180351.570807-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804328464100007 Content-Type: text/plain; charset="utf-8" Create a new "c" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVC. Instances of cpu->cfg.ext_c and similar are replaced with riscv_has_ext(env, RVC). Remove the old "c" property and 'ext_c' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 9 ++++----- target/riscv/cpu.h | 1 - 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3770fd4f6f..2e00b8f20a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -407,7 +407,6 @@ static void rv64_thead_c906_cpu_init(Object *obj) set_priv_version(env, PRIV_VERSION_1_11_0); =20 cpu->cfg.ext_g =3D true; - cpu->cfg.ext_c =3D true; cpu->cfg.ext_u =3D true; cpu->cfg.ext_s =3D true; cpu->cfg.ext_icsr =3D true; @@ -957,7 +956,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) } } =20 - if (cpu->cfg.ext_c) { + if (riscv_has_ext(env, RVC)) { cpu->cfg.ext_zca =3D true; if (cpu->cfg.ext_f && env->misa_mxl_max =3D=3D MXL_RV32) { cpu->cfg.ext_zcf =3D true; @@ -1168,7 +1167,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_cpu_cfg(env)->ext_d) { ext |=3D RVD; } - if (riscv_cpu_cfg(env)->ext_c) { + if (riscv_has_ext(env, RVC)) { ext |=3D RVC; } if (riscv_cpu_cfg(env)->ext_s) { @@ -1498,6 +1497,8 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor= *v, const char *name, static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { {.name =3D "a", .description =3D "Atomic instructions", .misa_bit =3D RVA, .enabled =3D true}, + {.name =3D "c", .description =3D "Compressed instructions", + .misa_bit =3D RVC, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1526,7 +1527,6 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), - DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), @@ -1649,7 +1649,6 @@ static void register_cpu_props(Object *obj) cpu->cfg.ext_f =3D misa_ext & RVF; cpu->cfg.ext_d =3D misa_ext & RVD; cpu->cfg.ext_v =3D misa_ext & RVV; - cpu->cfg.ext_c =3D misa_ext & RVC; cpu->cfg.ext_s =3D misa_ext & RVS; cpu->cfg.ext_u =3D misa_ext & RVU; cpu->cfg.ext_h =3D misa_ext & RVH; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1d1a17d85b..9a3847329c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -428,7 +428,6 @@ struct RISCVCPUConfig { bool ext_m; bool ext_f; bool ext_d; - bool ext_c; bool ext_s; bool ext_u; bool ext_h; --=20 2.39.2 From nobody Wed May 15 04:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680804496; cv=none; d=zohomail.com; s=zohoarc; b=lU65Rk4CuyZ6xGZ/MEcN6lVUocxTAD/WKxeOvfFnBjcHT52iflXwTPiWs/8y1oZhwdIIcFBE9bAdV57cGyMZ9jhhnzc3KruWzB2xwqh4Z23k6eFspsUnu79fWyvc2dP0NS2sW+stYB08x4kUtTq3Qji4VTnewUIcPIVzxxYhSOU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680804496; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=B9x0iEmvZZnGbXL5Z/nMToKlOj5c7ZztL5LLqrRttDI=; b=BY7DS8CSpMF2U7vQt41YzbLeNPwIzLg8Fc2rBwyL4pBwEt5LYfHpd0H/IMwm2AiY8CiTTfxsnDBnH0tZ9QE+16zByJLaqQvSV8I6aGsIwdRgppcgyZBpahj/hbh6yhjz50c8OQZsvJ0lU9qUzECrEE1rmL5mjavvxuiqdSF7aQE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680804496741623.3209934347716; Thu, 6 Apr 2023 11:08:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkTyH-00012a-UU; Thu, 06 Apr 2023 14:04:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkTyD-00011b-RT for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:27 -0400 Received: from mail-oa1-x2e.google.com ([2001:4860:4864:20::2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkTyA-0000dq-T0 for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:24 -0400 Received: by mail-oa1-x2e.google.com with SMTP id 586e51a60fabf-17aaa51a911so43227930fac.5 for ; Thu, 06 Apr 2023 11:04:22 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804261; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B9x0iEmvZZnGbXL5Z/nMToKlOj5c7ZztL5LLqrRttDI=; b=HSYaYqj72PYQurYdg8h3Cw4jrdp9mLmRnDuyUESiqpjihn0fmCPJImoGPCN1FF0L+d 96ivhaQgbGzTelS8mGCWGzyMCJSu0kEdgdF5Lv23wmqmB4beidMvyy6NQRaS+I6772qi u8WmCzMsUlLWbazYsHAG8UYnmwXa2hqKKwaZenyvUDcLi01X8ieGxZSTWLrVxRj143WV KIGnhg95zJNssuLz+wFkjaOII+T37QKYZldKYVYvT8dEYzrcxP5ephGoLylia1s5TEyJ W0ydtauQajgjnMaTuQ1ICQF8ctQqbQnJhnYCCc71+EvU11AA+rSeL+PwZCFdsS3xDJmY +LHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804261; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B9x0iEmvZZnGbXL5Z/nMToKlOj5c7ZztL5LLqrRttDI=; b=Zj2SChyrRHDXSL4Ue6wyuwMutt7Lxi5FZg6ZkPMhl2fRr0Rw8UZdsL/9cRJ7jI7FvD ViOo7UDbgyy94BYq9N1HgfEoX33RQ2+Q0IL0UIT3TJ0lLk6dJgOHA1co+nM52QFCLgkw uwJU3CqGRp2oU0D5QsP87Pcm24HkgiMMZx753WJdMPr/p3loO+0r32ZYtVJSWey8iQCT eK1WVJ9XrF6lVd1v9r+qrK6WN97Y3rJDZ7qwXiZI1lfP/+LCBYBRRpo9DhyVlUf9kLd/ WQD4v0Tvth6DCFLRMBjE2xTj0okU6C+cABI91ZSQ4R8LnpkJ3BBKpDPiGt7xnwEEsnWO LIqg== X-Gm-Message-State: AAQBX9eToKa7g/Th0CjdQBjgbYiNfG91LY830HW6/GfN4eMtt0TXyQTQ XkpzUoNeJ6VrFtAKE6HARi9LXbm+510zHs6bHzA= X-Google-Smtp-Source: AKy350a9oJARNDAXB6dNJKIcFrGpxSsjMXGzsmmS45gnhD/WOhR9oYDqVVv3XthPM27e+wi8Wf6jAA== X-Received: by 2002:a05:6870:b619:b0:183:e8b2:92f6 with SMTP id cm25-20020a056870b61900b00183e8b292f6mr94474oab.27.1680804261483; Thu, 06 Apr 2023 11:04:21 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 07/20] target/riscv: remove cpu->cfg.ext_d Date: Thu, 6 Apr 2023 15:03:38 -0300 Message-Id: <20230406180351.570807-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804498806100003 Content-Type: text/plain; charset="utf-8" Create a new "d" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVD. Instances of cpu->cfg.ext_d and similar are replaced with riscv_has_ext(env, RVD). Remove the old "d" property and 'ext_d' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 17 ++++++++--------- target/riscv/cpu.h | 1 - 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2e00b8f20a..5bb03e2ee5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -819,13 +819,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && riscv_has_ext(env, RVA) && - cpu->cfg.ext_f && cpu->cfg.ext_d && + cpu->cfg.ext_f && riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); cpu->cfg.ext_i =3D true; cpu->cfg.ext_m =3D true; cpu->cfg.ext_f =3D true; - cpu->cfg.ext_d =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; =20 @@ -881,7 +880,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { + if (riscv_has_ext(env, RVD) && !cpu->cfg.ext_f) { error_setg(errp, "D extension requires F extension"); return; } @@ -901,7 +900,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) cpu->cfg.ext_zve32f =3D true; } =20 - if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) { + if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { error_setg(errp, "Zve64d/V extensions require D extension"); return; } @@ -961,7 +960,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) if (cpu->cfg.ext_f && env->misa_mxl_max =3D=3D MXL_RV32) { cpu->cfg.ext_zcf =3D true; } - if (cpu->cfg.ext_d) { + if (riscv_has_ext(env, RVD)) { cpu->cfg.ext_zcd =3D true; } } @@ -976,7 +975,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) { + if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { error_setg(errp, "Zcd extension requires D extension"); return; } @@ -1164,7 +1163,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_cpu_cfg(env)->ext_f) { ext |=3D RVF; } - if (riscv_cpu_cfg(env)->ext_d) { + if (riscv_has_ext(env, RVD)) { ext |=3D RVD; } if (riscv_has_ext(env, RVC)) { @@ -1499,6 +1498,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVA, .enabled =3D true}, {.name =3D "c", .description =3D "Compressed instructions", .misa_bit =3D RVC, .enabled =3D true}, + {.name =3D "d", .description =3D "Double-precision float point", + .misa_bit =3D RVD, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1526,7 +1527,6 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), - DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), @@ -1647,7 +1647,6 @@ static void register_cpu_props(Object *obj) cpu->cfg.ext_e =3D misa_ext & RVE; cpu->cfg.ext_m =3D misa_ext & RVM; cpu->cfg.ext_f =3D misa_ext & RVF; - cpu->cfg.ext_d =3D misa_ext & RVD; cpu->cfg.ext_v =3D misa_ext & RVV; cpu->cfg.ext_s =3D misa_ext & RVS; cpu->cfg.ext_u =3D misa_ext & RVU; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9a3847329c..fba5e9a33c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -427,7 +427,6 @@ struct RISCVCPUConfig { bool ext_g; bool ext_m; bool ext_f; - bool ext_d; bool ext_s; bool ext_u; bool ext_h; --=20 2.39.2 From nobody Wed May 15 04:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680804384; cv=none; d=zohomail.com; s=zohoarc; b=e8mnv3WYtp2Yww4ezUvk3jTH/CeGDS0U7BpT0sTzt6w6hQSShRtJIN4icvK/BOlF4HVuTR6CGWv1Wr+mzCGqceVluJzg3Gnvvt+xy3o9Z89kTYq4aaLkNu44l1BeXC4Fkvi2N+lABxiRtR4Gqx1bA+xOm63cH10pTsojv61kN8M= ARC-Message-Signature: i=1; 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([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804265; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w4z24gtDXDugF/zsUCpawt2hpra7MWomBPWmPIVOu3U=; b=o7RCUMljqcUNkavvT5acNcbWGWpzDnYaGnNm6/DGFmJA9UC9o4r0mY39+D59liDzXb VBsyY8fM2lVES4nuzhFb0L0XSez+84FMKWY3svTwIvOFmQh+u8OeGBuwHd7LCsnIOeFi 0F82j6HyFI5L6/j/MvQ0JhpDiqLmD6xTYzJk0V24ADefwClNI21HFmeuB53acHisiau9 OXaLBt1iKYbmta+OFK7aVCAgtfo7OMp37/dD4AVp91pawdAnh/OSsJlVcK/+1dTfkVVm FrH1NbRmI3E7zocXFccxkqPOSzeGznZDs7CcRDONEcg2XNdZfHr7XSfuitspXJN9od+Z Sc6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804265; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w4z24gtDXDugF/zsUCpawt2hpra7MWomBPWmPIVOu3U=; b=lX6ql19lr5kPwvIRhUdfII87xvnQIFo/hKReVtJo6SHqAQ4iTl6t+tYlK/9QA/pFnU xN/+hcJyRZQQpvY3MatGPQupDKK/67cOwlSY/iMOrgAybg+QdjT8x8JgvvxpTDLeg5jQ 5MUVJbE8edwuf87Ok5exO9Lw3MEuyI/S6kwrcJswRuL5WkKi/oexkgntkaN+qdQX9E9d J/fa5kei9F2X5Gv45hJycGIIGriKlXN0N89uF8Q72oNhtNnLGbu76yer7K/C8MGm1VW6 VRalhOA1fxgJd2yEjoJ5EqvvGqRKwJLMrsw2SSR3/o84AAVBHD+k3xAdTiOWsMpzCDsq 3woA== X-Gm-Message-State: AAQBX9c0h891D5USUIJv/mRM4TPNDF+vDZyEjLr/FXfcZC024+lNX5Nt sqNZnGnOFiwFjbQWM2V2YnDfx9vBuLbjlxefBbc= X-Google-Smtp-Source: AKy350bTilafw94sdVe0NAK2ycTKhU5y2z2ULa8B+xP+oeahKfIECnAdHjzIrG0JaFY7sKpUnkcUyQ== X-Received: by 2002:a05:6870:d189:b0:17a:a7f3:e591 with SMTP id a9-20020a056870d18900b0017aa7f3e591mr91524oac.26.1680804264750; Thu, 06 Apr 2023 11:04:24 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 08/20] target/riscv: remove cpu->cfg.ext_f Date: Thu, 6 Apr 2023 15:03:39 -0300 Message-Id: <20230406180351.570807-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804384815100001 Content-Type: text/plain; charset="utf-8" Create a new "f" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVF. Instances of cpu->cfg.ext_f and similar are replaced with riscv_has_ext(env, RVF). Remove the old "f" property and 'ext_f' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 26 +++++++++++++------------- target/riscv/cpu.h | 1 - 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5bb03e2ee5..715cbca1b3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -819,12 +819,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && riscv_has_ext(env, RVA) && - cpu->cfg.ext_f && riscv_has_ext(env, RVD) && + riscv_has_ext(env, RVF) && + riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); cpu->cfg.ext_i =3D true; cpu->cfg.ext_m =3D true; - cpu->cfg.ext_f =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; =20 @@ -861,7 +861,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { + if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) { error_setg(errp, "F extension requires Zicsr"); return; } @@ -875,12 +875,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) cpu->cfg.ext_zfhmin =3D true; } =20 - if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) { + if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { error_setg(errp, "Zfh/Zfhmin extensions require F extension"); return; } =20 - if (riscv_has_ext(env, RVD) && !cpu->cfg.ext_f) { + if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { error_setg(errp, "D extension requires F extension"); return; } @@ -905,7 +905,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) { + if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { error_setg(errp, "Zve32f/Zve64f extensions require F extension"); return; } @@ -938,7 +938,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) error_setg(errp, "Zfinx extension requires Zicsr"); return; } - if (cpu->cfg.ext_f) { + if (riscv_has_ext(env, RVF)) { error_setg(errp, "Zfinx cannot be supported together with F extensio= n"); return; @@ -950,14 +950,14 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) cpu->cfg.ext_zcb =3D true; cpu->cfg.ext_zcmp =3D true; cpu->cfg.ext_zcmt =3D true; - if (cpu->cfg.ext_f && env->misa_mxl_max =3D=3D MXL_RV32) { + if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { cpu->cfg.ext_zcf =3D true; } } =20 if (riscv_has_ext(env, RVC)) { cpu->cfg.ext_zca =3D true; - if (cpu->cfg.ext_f && env->misa_mxl_max =3D=3D MXL_RV32) { + if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { cpu->cfg.ext_zcf =3D true; } if (riscv_has_ext(env, RVD)) { @@ -970,7 +970,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) { + if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { error_setg(errp, "Zcf extension requires F extension"); return; } @@ -1160,7 +1160,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVA)) { ext |=3D RVA; } - if (riscv_cpu_cfg(env)->ext_f) { + if (riscv_has_ext(env, RVF)) { ext |=3D RVF; } if (riscv_has_ext(env, RVD)) { @@ -1500,6 +1500,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVC, .enabled =3D true}, {.name =3D "d", .description =3D "Double-precision float point", .misa_bit =3D RVD, .enabled =3D true}, + {.name =3D "f", .description =3D "Single-precision float point", + .misa_bit =3D RVF, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1526,7 +1528,6 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), - DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), @@ -1646,7 +1647,6 @@ static void register_cpu_props(Object *obj) cpu->cfg.ext_i =3D misa_ext & RVI; cpu->cfg.ext_e =3D misa_ext & RVE; cpu->cfg.ext_m =3D misa_ext & RVM; - cpu->cfg.ext_f =3D misa_ext & RVF; cpu->cfg.ext_v =3D misa_ext & RVV; cpu->cfg.ext_s =3D misa_ext & RVS; cpu->cfg.ext_u =3D misa_ext & RVU; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index fba5e9a33c..e5680b0709 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -426,7 +426,6 @@ struct RISCVCPUConfig { bool ext_e; bool ext_g; bool ext_m; - bool ext_f; bool ext_s; bool ext_u; bool ext_h; --=20 2.39.2 From nobody Wed May 15 04:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680804504; cv=none; d=zohomail.com; s=zohoarc; b=oJUDctTdRkSw9vT73wpmq1j67EDE7nf57KhtArba0Rkukqv5OpSfGjPaAQHBJuW7W7rPm6j5t5pFgYP0ACkYAYSUZpU2iitw7AHOIMEvXfb68x+dPOO+OccKl5nRVQ7QgE7vgcNriBq3CsO65Uutr9w2D+gO5cUmDym0+hHyLrk= ARC-Message-Signature: i=1; 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([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804267; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x17gQvU5jjV/8z4M540QkhyEwhpbTSgb9uB+N0XU/Ck=; b=KAnX5UhBHO3RUbo2A+K9/2oQ9BbpMlYTHJvvAunZHFZbcEEY3fOGJ24Idka/kNkJ9b YOW+95eiQRJko3KN+UX+hdP5acWag5r+MH3bmzifsfapOeUDJ3jl2XNW5BLpxQE3EiA9 vPF0MiWjpDlm7AYOG/Mw3VE5QFMQpjSnWoU9z9CA1IWRVCbrNMhnzzESEWTb0r87Us2j D5el3EEjpecuHZm0iqcwL1ajrP0JF+gvcZKUzG4Zh1ZtYSAlT9TY8mIQ135liB2+i9CI iPMlMV9pY3vx1pggTEuhyd6k0hG3BLbR16LqCTzVQc9KAgh/1cMCH5LEnS2eseVE6yXU 9pdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804267; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x17gQvU5jjV/8z4M540QkhyEwhpbTSgb9uB+N0XU/Ck=; b=IyXF2F3a2Xf5Te+cnLmghyX8t64GR8GqRVw2p6qzcpUpf3ZpHvqKxYkCvZHUgnWJS8 uJVKMCB+gMCMn6xfvf2pMPxMMz1Dpb+X+kbLR/B13TwrplReCLqnA23JYLhiLg91aQ5r /KdwfaNBZKEkojb/oMZCkitpMxB+YpGi5A0+zv4rjLzvJVar+ghBQhVx5sxbp1eEoefE DJHwnGIvE4zS7M1phTbXLW8Fxaazg81xCZ/koJajs1fny382XsJW6d7RQ2ma9Rlp64O/ w2kihmPQHNueR4azdVMcE7aav3xulSJddXVYWtdMeXeOzA20uQoRd17XdNHXRNxkEson jhhg== X-Gm-Message-State: AAQBX9fzxK73rCfTtEN24KEX2j9NPhcmXRgs+KVXMWj6dnaTxMJ1BZfn NbTExEjpzCYkubCynDhZ6IFxLNEmoClavMEQrPA= X-Google-Smtp-Source: AKy350Ztt4xEFUekq3+eab/6aUEff3n5RfalIvy31Zn/EqftzJhEoOSfH4L//Y5xdUW8fy/VdeUeVw== X-Received: by 2002:a05:6870:e243:b0:17d:1f3:3016 with SMTP id d3-20020a056870e24300b0017d01f33016mr3631243oac.5.1680804267754; Thu, 06 Apr 2023 11:04:27 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 09/20] target/riscv: remove cpu->cfg.ext_i Date: Thu, 6 Apr 2023 15:03:40 -0300 Message-Id: <20230406180351.570807-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804504887100003 Content-Type: text/plain; charset="utf-8" Create a new "i" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVI. Instances of cpu->cfg.ext_i and similar are replaced with riscv_has_ext(env, RVI). Remove the old "i" property and 'ext_i' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 15 +++++++-------- target/riscv/cpu.h | 1 - 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 715cbca1b3..f082748569 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -817,13 +817,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) CPURISCVState *env =3D &cpu->env; =20 /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && + if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m && riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_i =3D true; cpu->cfg.ext_m =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; @@ -832,13 +831,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) env->misa_ext_mask =3D env->misa_ext; } =20 - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { + if (riscv_has_ext(env, RVI) && cpu->cfg.ext_e) { error_setg(errp, "I and E extensions are incompatible"); return; } =20 - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { + if (!riscv_has_ext(env, RVI) && !cpu->cfg.ext_e) { error_setg(errp, "Either I or E extension must be set"); return; @@ -850,7 +849,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { + if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) { error_setg(errp, "H depends on an I base integer ISA with 32 x registers= "); return; @@ -1148,7 +1147,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) { uint32_t ext =3D 0; =20 - if (riscv_cpu_cfg(env)->ext_i) { + if (riscv_has_ext(env, RVI)) { ext |=3D RVI; } if (riscv_cpu_cfg(env)->ext_e) { @@ -1502,6 +1501,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVD, .enabled =3D true}, {.name =3D "f", .description =3D "Single-precision float point", .misa_bit =3D RVF, .enabled =3D true}, + {.name =3D "i", .description =3D "Base integer instruction set", + .misa_bit =3D RVI, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1524,7 +1525,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) =20 static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ - DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), @@ -1644,7 +1644,6 @@ static void register_cpu_props(Object *obj) * later on. */ if (cpu->env.misa_ext !=3D 0) { - cpu->cfg.ext_i =3D misa_ext & RVI; cpu->cfg.ext_e =3D misa_ext & RVE; cpu->cfg.ext_m =3D misa_ext & RVM; cpu->cfg.ext_v =3D misa_ext & RVV; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e5680b0709..479b654d54 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -422,7 +422,6 @@ typedef struct { } RISCVSATPMap; =20 struct RISCVCPUConfig { - bool ext_i; bool ext_e; bool ext_g; bool ext_m; --=20 2.39.2 From nobody Wed May 15 04:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804270; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G0KZB43953rDZ9eEo49cyVU/G2AGYXUmxjvTZ9fuOiE=; b=ZanHvbzheepU/K8NnOqtU0AwsMJBNTwj51bw9Ppm0mzZVkeHaCkGzlKp2t22lnO24f PjlNSb/VlHmQY/DXV1AzU32S2ghS/t1Qsz0/fizV4+T+hK1vuPAjS/ovw+yZ1VZsSs6w RBuVeblnzv/iakNucWIAW/0hntGN6uuUchSMtaBa7d8+R6uHaXmtYau7wutf3ip32Lus mZ3yulh1I1sy8VbBjMukhp7m32DYDAZ3rASF7rB1TTaozywq4m++VOhajIS4orO3ac8y IAQ/2oVEtBR05/YyAJVP29tHcka1SjAJNk/ZQZ6D+Nwme3xElPF9ZyWDUpXPukCZXpC8 D28w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804270; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G0KZB43953rDZ9eEo49cyVU/G2AGYXUmxjvTZ9fuOiE=; b=FTjvOQLPsD2NIfK4SfrKIOQJczkbqjbq0rbo2qIsTr7z4zpLWFxIZpdtUW3EnfyOU1 or8DwDY9ZJVBxPE+6A2gvVLUecO1B2Pqm4y1Yd7QS77ZVkxa6yVllRUhXxET5NOp45XE wsluJX0cpekKhdJKFnEw+2n9tEfyJy+nHAfM3j9SKWkgfTUfmppkI8fs+6tilVKHDT8h w+eZa+IgeqSOSDIvwiHfcy8y4zdehGYDmkREKehA2JWAao4VlUBb6IY+4z0Mh73Y03lE QGDLrcnv/ounPj7k6AKzK3T2yuYEYnIJgynZeuVIqx9Cq+7mu6YCPpFZ6jKBahN9xvE6 7jNQ== X-Gm-Message-State: AAQBX9cFgjZwRqHNyAyqV+1jn/iugi/luKDYeOlOhDBxpXD0HPNWQVKh 8+HENJXro3wkoXfBnMIy8RqdzRiOCW0LX/HJAXk= X-Google-Smtp-Source: AKy350ZCdTvJ5Qyqrowl6qosW0Msq8sRyClbKlZWpmvsMNq/LqofBoEyuETZBmRTuPKLOLRqi5BuNQ== X-Received: by 2002:a05:6870:961d:b0:177:7dae:42e0 with SMTP id d29-20020a056870961d00b001777dae42e0mr44191oaq.58.1680804270604; Thu, 06 Apr 2023 11:04:30 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 10/20] target/riscv: remove cpu->cfg.ext_e Date: Thu, 6 Apr 2023 15:03:41 -0300 Message-Id: <20230406180351.570807-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804371957100003 Content-Type: text/plain; charset="utf-8" Create a new "e" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVE. Instances of cpu->cfg.ext_e and similar are replaced with riscv_has_ext(env, RVE). Remove the old "e" property and 'ext_e' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 10 +++++----- target/riscv/cpu.h | 1 - target/riscv/insn_trans/trans_rvzce.c.inc | 2 +- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f082748569..33db4fa4b2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -831,13 +831,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) env->misa_ext_mask =3D env->misa_ext; } =20 - if (riscv_has_ext(env, RVI) && cpu->cfg.ext_e) { + if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { error_setg(errp, "I and E extensions are incompatible"); return; } =20 - if (!riscv_has_ext(env, RVI) && !cpu->cfg.ext_e) { + if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { error_setg(errp, "Either I or E extension must be set"); return; @@ -1150,7 +1150,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVI)) { ext |=3D RVI; } - if (riscv_cpu_cfg(env)->ext_e) { + if (riscv_has_ext(env, RVE)) { ext |=3D RVE; } if (riscv_cpu_cfg(env)->ext_m) { @@ -1503,6 +1503,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVF, .enabled =3D true}, {.name =3D "i", .description =3D "Base integer instruction set", .misa_bit =3D RVI, .enabled =3D true}, + {.name =3D "e", .description =3D "Base integer instruction set (embedd= ed)", + .misa_bit =3D RVE, .enabled =3D false}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1525,7 +1527,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) =20 static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ - DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), @@ -1644,7 +1645,6 @@ static void register_cpu_props(Object *obj) * later on. */ if (cpu->env.misa_ext !=3D 0) { - cpu->cfg.ext_e =3D misa_ext & RVE; cpu->cfg.ext_m =3D misa_ext & RVM; cpu->cfg.ext_v =3D misa_ext & RVV; cpu->cfg.ext_s =3D misa_ext & RVS; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 479b654d54..2b42de60b1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -422,7 +422,6 @@ typedef struct { } RISCVSATPMap; =20 struct RISCVCPUConfig { - bool ext_e; bool ext_g; bool ext_m; bool ext_s; diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_= trans/trans_rvzce.c.inc index d75acbc4a6..a727169a4b 100644 --- a/target/riscv/insn_trans/trans_rvzce.c.inc +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -117,7 +117,7 @@ static uint32_t decode_push_pop_list(DisasContext *ctx,= target_ulong rlist) { uint32_t reg_bitmap =3D 0; =20 - if (ctx->cfg_ptr->ext_e && rlist > 6) { + if (has_ext(ctx, RVE) && rlist > 6) { return 0; } =20 --=20 2.39.2 From nobody Wed May 15 04:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804273; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kV7z09+98ddMxW+lPuQeVv6kSGaKTK/aK1AU+q2WtVg=; b=Kc2V2GluUYxAHaM2MKAM7W7YcaF9LBCB0VP8U6/Xz23vrxV7CbGe+wprANq8TLWRVr Sav8M6JkuoMKUA0HmegQ+JBB9W57s98KwmP8zdF0Xi9RHgstVMf0XApYwR/dULz///zc Vbb1XznUWqdMNK+vP5/eidZWC85mTW1lQ5PdSssOuyk6y/C2rRcN2v8VSKXtksiqmewK 8xT3Qa3uPb199w9DjZXOtqb6d96WzY7P+apTosKZDT5nYxu+uK0GVYFJYJBV96yeKdUw fl5hJkYDY08fZmCNMRd2XdphyXnhqzrSkcGPLkScMQnA9U6v7Wcwp+eV3fxCYjIqAm7C ba6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804273; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kV7z09+98ddMxW+lPuQeVv6kSGaKTK/aK1AU+q2WtVg=; b=5qmX9i/gHDSPTXZhfqeLZu1JTar345pz3nB1xkC4w4i+LXmVGmuj+7Fe3Pxlq1tXU7 BXjfC9XheeJSB6kl9DKYNSzzEUJcBy8EeeBIDy7gmg11kKFmQjmMuDQeilrPH2FvO0EF l5zMbAMfU92SAeqmest4EISYKWb9Vr8W+c87CLOk9RilMqMc0cN0AYh9TXNc70v+NPJY 4NTXYCI036NaVaZz+5N9txLqUS7/iAy8fPW+0WDURFaLsoBpccE5VQJANY2UaX6Zmlpu 9Ks7XGwKn94UPzLFltDO47KDpqnXV1Bardm/JHJMGASxRilfy8regKluy5CC2r2z9jhG kAOA== X-Gm-Message-State: AAQBX9eWbH5lgWUKNLctfktqvCH9tIAijcLDJFXVsnoFLmMdPdWCT7gi D/F+EIYqiC3OmuDT/p/FIPzba+aX+x5+ZAkAVYo= X-Google-Smtp-Source: AKy350YV90xy+hlW+GBPL8Fm7T+FEq4HIs8ZCtkBbRtEByD9QtN90D2Biavx8j6Gz7eJAPznvKbWiA== X-Received: by 2002:a05:6870:b489:b0:176:53a1:b65c with SMTP id y9-20020a056870b48900b0017653a1b65cmr148750oap.11.1680804273439; Thu, 06 Apr 2023 11:04:33 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 11/20] target/riscv: remove cpu->cfg.ext_m Date: Thu, 6 Apr 2023 15:03:42 -0300 Message-Id: <20230406180351.570807-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804449889100001 Content-Type: text/plain; charset="utf-8" Create a new "m" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVM. Instances of cpu->cfg.ext_m and similar are replaced with riscv_has_ext(env, RVM). Remove the old "m" property and 'ext_m' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 10 +++++----- target/riscv/cpu.h | 1 - 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 33db4fa4b2..24640450c7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -817,13 +817,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) CPURISCVState *env =3D &cpu->env; =20 /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m && + if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && + riscv_has_ext(env, RVM) && riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_m =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; =20 @@ -1153,7 +1153,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVE)) { ext |=3D RVE; } - if (riscv_cpu_cfg(env)->ext_m) { + if (riscv_has_ext(env, RVM)) { ext |=3D RVM; } if (riscv_has_ext(env, RVA)) { @@ -1505,6 +1505,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVI, .enabled =3D true}, {.name =3D "e", .description =3D "Base integer instruction set (embedd= ed)", .misa_bit =3D RVE, .enabled =3D false}, + {.name =3D "m", .description =3D "Integer multiplication and division", + .misa_bit =3D RVM, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1528,7 +1530,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), - DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), @@ -1645,7 +1646,6 @@ static void register_cpu_props(Object *obj) * later on. */ if (cpu->env.misa_ext !=3D 0) { - cpu->cfg.ext_m =3D misa_ext & RVM; cpu->cfg.ext_v =3D misa_ext & RVV; cpu->cfg.ext_s =3D misa_ext & RVS; cpu->cfg.ext_u =3D misa_ext & RVU; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2b42de60b1..71540a33ec 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -423,7 +423,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_m; bool ext_s; bool ext_u; bool ext_h; --=20 2.39.2 From nobody Wed May 15 04:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680804331; cv=none; d=zohomail.com; s=zohoarc; b=Unk7lOm4fKo8TSvLJD3SUBenf8z1SNSTKdwhyph9iobfDyat+8BYMeIJdxVGtIZOH80PLxBAY5WfMkdVMg46eV86whtGJ6/YT+GkuejPAi8GVVBzGI2Jp+B28fGPjbcLa6I5/zPJ5zciZeX5wfEDGWzr6ea+jl+JG+TcXMscJBo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680804331; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=U+T787wtOE0aKK/i9r0lVaLXC3vz5Uj8Ub6gpP1wvpc=; b=PlypfuWy0ZRzKStTAeiuwesRLMe2DnxddeuPQZs9Jrsah3/ojBI7lCIcJmr3wpcTXSZWVOFKkuPxkyu7aeCuFcGNQoSHfcnbttmedqECEqr+nQ0B+dboJrPKd0UwLYpDexG7dYxfdkvS/UUKGJlbcdk7SmKx9+/gKw7npk1sDUY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680804331228661.7849980269823; Thu, 6 Apr 2023 11:05:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkTyU-0001B0-VG; Thu, 06 Apr 2023 14:04:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkTyT-00018d-Aj for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:41 -0400 Received: from mail-oa1-x32.google.com ([2001:4860:4864:20::32]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkTyQ-0000gf-Ld for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:40 -0400 Received: by mail-oa1-x32.google.com with SMTP id 586e51a60fabf-17683b570b8so43185910fac.13 for ; Thu, 06 Apr 2023 11:04:37 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804276; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=U+T787wtOE0aKK/i9r0lVaLXC3vz5Uj8Ub6gpP1wvpc=; b=SLbCBQ69U+qxBXQDw8MOYxVAPsdM/NiWvWllf7T9JK1ZfJO3+fn4srDJKyBGmLcwPU 8/7a/UqsixM8tLBS8T2J2ywSGO8ky9DXU7MGJBLi5q1HwUY+KarpxfuV24FAP+owX8gE GFszm2oV4tIu6HguAHWdO/MlXow+19QldreKoJp8d95mC8NjkHfI4iOavFJaCt7kKxkS mxFQ175Hu+8NjNhydVLMu8AiY3FXYCyJdvhC0jJb14cy2JOxtpk/9O95x1qasXCurp+N RJMBA2rVKET1OBTILt0GgHdWbl8vjZ/FiT2Al1mY1TYjqPY4tnTSq5vnXwO33r7N/w5b /yMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804276; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U+T787wtOE0aKK/i9r0lVaLXC3vz5Uj8Ub6gpP1wvpc=; b=y2VdmmDqRcPJQnejIziGPFx/5mG2X3sXtIFnEAYkRdDOv/BYDXZIDSS1SFncpHtTqc 4wGlBfb9bH2iDrhOkWQ6MecakSMhD4n9q5Y6oaJvGmoyyLvuiAerWvjCerhVlAb9hNXD 3/UGowldC7n9TpFRAC4KCBQbs4Ucvne4+UY1Mm1sgttcEhBhDhU48y5omPZ3MKAxfSCL NTlfZ5jXVRa1UUzDDaAk8iaJfdgZbmE3DXe8AhxKys57EdJkPzkdyQxnuuBRE9+UJwPF 5iBCJnZp0Cw8GywEVXMWIJtE+qqPQcC0z/7vyylWYtsPyYYgafL2krBrksNdLjRMfaRj aDkg== X-Gm-Message-State: AAQBX9ck8m16pJSBOhlFBB4pS3nYm08x3F/mbY+ui16DUJxdP//DiEaw MhmHfKtOw5QMhnQXXgHCuJwkOsrx4jeiiNdsxDQ= X-Google-Smtp-Source: AKy350bBE9AT8SirlNtzlBjD4CY64hopTMa3Venn4ROjpxttxnwJoG+8+wqSt+uKbbxKi38FlWvnSQ== X-Received: by 2002:a05:6870:9687:b0:183:f65c:8c41 with SMTP id o7-20020a056870968700b00183f65c8c41mr947425oaq.15.1680804276431; Thu, 06 Apr 2023 11:04:36 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 12/20] target/riscv: remove cpu->cfg.ext_s Date: Thu, 6 Apr 2023 15:03:43 -0300 Message-Id: <20230406180351.570807-13-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804331685100013 Content-Type: text/plain; charset="utf-8" Create a new "s" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVS. Instances of cpu->cfg.ext_s and similar are replaced with riscv_has_ext(env, RVS). Remove the old "s" property and 'ext_s' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 11 +++++------ target/riscv/cpu.h | 1 - 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 24640450c7..cded82ac7a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -408,7 +408,6 @@ static void rv64_thead_c906_cpu_init(Object *obj) =20 cpu->cfg.ext_g =3D true; cpu->cfg.ext_u =3D true; - cpu->cfg.ext_s =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_zfh =3D true; cpu->cfg.mmu =3D true; @@ -843,7 +842,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { + if (riscv_has_ext(env, RVS) && !cpu->cfg.ext_u) { error_setg(errp, "Setting S extension without U extension is illegal"); return; @@ -855,7 +854,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { + if (cpu->cfg.ext_h && !riscv_has_ext(env, RVS)) { error_setg(errp, "H extension implicitly requires S-mode"); return; } @@ -1168,7 +1167,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVC)) { ext |=3D RVC; } - if (riscv_cpu_cfg(env)->ext_s) { + if (riscv_has_ext(env, RVS)) { ext |=3D RVS; } if (riscv_cpu_cfg(env)->ext_u) { @@ -1507,6 +1506,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVE, .enabled =3D false}, {.name =3D "m", .description =3D "Integer multiplication and division", .misa_bit =3D RVM, .enabled =3D true}, + {.name =3D "s", .description =3D "Supervisor-level instructions", + .misa_bit =3D RVS, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1530,7 +1531,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), - DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), @@ -1647,7 +1647,6 @@ static void register_cpu_props(Object *obj) */ if (cpu->env.misa_ext !=3D 0) { cpu->cfg.ext_v =3D misa_ext & RVV; - cpu->cfg.ext_s =3D misa_ext & RVS; cpu->cfg.ext_u =3D misa_ext & RVU; cpu->cfg.ext_h =3D misa_ext & RVH; cpu->cfg.ext_j =3D misa_ext & RVJ; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 71540a33ec..8b8e541e5f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -423,7 +423,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_s; bool ext_u; bool ext_h; bool ext_j; --=20 2.39.2 From nobody Wed May 15 04:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680804479; cv=none; d=zohomail.com; s=zohoarc; b=C7FvxDkS3yWvipUHYI2Hf/iUo4b+wEMxLEC4gRH4JTHF2TmrB1KRwrUrxpe91AKo1E45BapW7UB93UvAcvYtElsfPWwev9W0SCdFmKxCfrZhsNH3pP2EQGhhsmdNloJ5F4uf9bdVWaR4n3vM535ITB0WgpV3msfeevqTIdsM7TQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680804479; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YMcBcOMKiOCRPkvJPsLKtCK2KcBHaIOtwtePnGbSRc8=; b=XN0BfvPuiTGqT36JM/bOeiLNR/n+Z2pmzzG3nu1mlhZn+ztvoyK8Z5rq1VA/c0n4iOCHk1PxG3FvKlPK1BqcSNzccvlI2YaAb8f1lRtoLE5E5/4wE/6+YzubkZS4Q4VZqzUVFI4IsZgHKOzJsZcY8HOgRNcg3O9ySofaKYKNOes= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680804479056127.72416773566988; Thu, 6 Apr 2023 11:07:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkTyV-0001BA-Lh; Thu, 06 Apr 2023 14:04:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkTyU-0001Aa-Mj for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:42 -0400 Received: from mail-oa1-x35.google.com ([2001:4860:4864:20::35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkTyT-0000cy-2v for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:42 -0400 Received: by mail-oa1-x35.google.com with SMTP id 586e51a60fabf-17e140619fdso43208683fac.11 for ; Thu, 06 Apr 2023 11:04:40 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804279; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YMcBcOMKiOCRPkvJPsLKtCK2KcBHaIOtwtePnGbSRc8=; b=E1CZpAU1YW74/bnzn5qMCtHYhaujTVT1Lp7E9R28/rSFaLrLfj9O1cqCej0J9dRaAY VMMtrXhakmjHyZq9zKvrmfkvojg+XrhJoiT7m2sVJAuiF5Jkd+M78CdaEOCtI0sbPWJW SZcfqbyk2apEE59yfnUnL90+QFAMIpYvbTBg52acIXrDWa9dtOhevufR7qwx4ykJYAF4 b8/jdF7ErJQX8oxhHYyQl1y31q0DuKM3pl+omwRjKmYF22v0xvpDl0VFKeyGeOvGh502 oyEu9zKR+67BXZlzBDxiKWUJhBFlVwn8cj4CreVTHAXQMgikGmH54OARhitWK4tdiNN6 wiAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804279; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YMcBcOMKiOCRPkvJPsLKtCK2KcBHaIOtwtePnGbSRc8=; b=XX+PSNA64/6uAN2ySezrq1a7KmEoFqSwDFfJ+fEON9efydEVdLDBy0hXLgGcOzPIN7 rxENYyYaW/LyU4Xjn2poHWGOjLVFzL2eKgL55hgMQRp33UHEUUpEGw0lPfC3EbWS1INN EpE+Wq7tWIEOdDc6ZE0CqVZAVzbptwNOcoJ+6iW33GfOaDkzNnenDqKUVV5Vj0zS9360 IHdnzyzlhUhkVH47J2dfwd3hJiwMyBC6HzVIKv4Hazwqsxw5i17N6JJh57/PBIihtTIR 7fBercTjK5efoZzqBxgWGID/cNT+3vTSD4So+XiS5LfIRYBra6bkUhJk6aK1WyZLz9mN w75w== X-Gm-Message-State: AAQBX9c9aH1s3m6MmFQW+SeTZLGct6b4lnCe0VbEqcSfJf0b6Du/iTYC gD5PxklyqklbUORg05as1agwleFvgKFbEAEIaEk= X-Google-Smtp-Source: AKy350ZzYfkdX+WYEw1EjhI0IFuZ+CYVtiv8DjhzRagzHvnQ5aQXidCHVaFxfhVY9UONbVbuaRMF3A== X-Received: by 2002:a05:6870:968f:b0:177:b463:9dcf with SMTP id o15-20020a056870968f00b00177b4639dcfmr51733oaq.46.1680804279669; Thu, 06 Apr 2023 11:04:39 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 13/20] target/riscv: remove cpu->cfg.ext_u Date: Thu, 6 Apr 2023 15:03:44 -0300 Message-Id: <20230406180351.570807-14-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::35; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804480713100011 Content-Type: text/plain; charset="utf-8" Create a new "u" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVU. Instances of cpu->cfg.ext_u and similar are replaced with riscv_has_ext(env, RVU). Remove the old "u" property and 'ext_u' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 9 ++++----- target/riscv/cpu.h | 1 - 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cded82ac7a..9565495839 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -407,7 +407,6 @@ static void rv64_thead_c906_cpu_init(Object *obj) set_priv_version(env, PRIV_VERSION_1_11_0); =20 cpu->cfg.ext_g =3D true; - cpu->cfg.ext_u =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_zfh =3D true; cpu->cfg.mmu =3D true; @@ -842,7 +841,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (riscv_has_ext(env, RVS) && !cpu->cfg.ext_u) { + if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { error_setg(errp, "Setting S extension without U extension is illegal"); return; @@ -1170,7 +1169,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVS)) { ext |=3D RVS; } - if (riscv_cpu_cfg(env)->ext_u) { + if (riscv_has_ext(env, RVU)) { ext |=3D RVU; } if (riscv_cpu_cfg(env)->ext_h) { @@ -1508,6 +1507,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVM, .enabled =3D true}, {.name =3D "s", .description =3D "Supervisor-level instructions", .misa_bit =3D RVS, .enabled =3D true}, + {.name =3D "u", .description =3D "User-level instructions", + .misa_bit =3D RVU, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1531,7 +1532,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), - DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), @@ -1647,7 +1647,6 @@ static void register_cpu_props(Object *obj) */ if (cpu->env.misa_ext !=3D 0) { cpu->cfg.ext_v =3D misa_ext & RVV; - cpu->cfg.ext_u =3D misa_ext & RVU; cpu->cfg.ext_h =3D misa_ext & RVH; cpu->cfg.ext_j =3D misa_ext & RVJ; =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8b8e541e5f..486061589e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -423,7 +423,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_u; bool ext_h; bool ext_j; bool ext_v; --=20 2.39.2 From nobody Wed May 15 04:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680804444; cv=none; d=zohomail.com; s=zohoarc; b=a5NPTboeT7OT/IKetDCdZWuegd5KFLDjc0MwA63xDlZZrVymUlJKV1tSrcRmAdADEGet63cbsAXyuJxwAbXdS8jFhB1kHMRpkfe22i1t17CNbSZ0cCINhtIKV0bHFKsrYQt+586D/yUrEPmk3FT9NRa7rHTApEnJrgxqaY9D1x8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680804444; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+m6bMfy/cyrt4lCC2IbuWnYLtXN0nBbEUV0AP0ycayo=; b=VXa7XTowF2+vO0j6njgSGmY+gkknfdgxn42JqRXUNcVDdoUjLoOsHHMW42bl1o+si9AdmzkFcPi5FgabZ2JWRWgOeE+wtInM2EIVrHN0bJR8XwiL0mLGKpX322SsA+cePap2AI8aKm3u+8rOw5ci0k1mcjmn5Bk9/MEILIj073c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680804444855597.1281912433064; Thu, 6 Apr 2023 11:07:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkTyY-0001Ct-O7; Thu, 06 Apr 2023 14:04:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkTyX-0001CI-6P for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:45 -0400 Received: from mail-oa1-x35.google.com ([2001:4860:4864:20::35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkTyV-0000cy-Ib for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:44 -0400 Received: by mail-oa1-x35.google.com with SMTP id 586e51a60fabf-17e140619fdso43208857fac.11 for ; Thu, 06 Apr 2023 11:04:43 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804282; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+m6bMfy/cyrt4lCC2IbuWnYLtXN0nBbEUV0AP0ycayo=; b=KmLnLi1305sEQuA4o1DojqZdFQLd5DegtjaNbLaTZnj7u2LndNKAcVts2vhqR9Hdzj wxeT2AB9lNDHb1g5QPm7/4VI5JPOhpdcCF8F11cTF0BZJTyJhH61ySyl1Vu12uxW4t4L gxOtMPtOlrtj+RHyFtTUqO7ughfljkbNIQfaWidgCVBybktqyq9+q0HSnWrhi1bH/N0b MwNbpTjRT0kdcBSCvoCArtttZI+iEKSGqk3gLVx6j70hlrqgHm0LW54wL3Xae71jVoDf udt89cGfuxTpRT7iZAZkx1LenDJt5PwNV6DLlO6PanfQVv/ak25MCorgg95aKghXU2Y3 +ycA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804282; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+m6bMfy/cyrt4lCC2IbuWnYLtXN0nBbEUV0AP0ycayo=; b=dsqSBApEKHvTkiWs6CnwI1B6Ll7xCAJog6B2wZZyUUja3xoYQ+qO6lP12tvwt0XBFn TfQpJ2ICfHOaajq/yXizxMqHFIx99ox1HQs2+2t/bwWqdTnapJwxs6D/ByqjoJQvQpIu gEQluZBJfe3NjuNTBP4JkHefn/li7HQjiYLfaXFzfWV34zXRr87oFNKVJtF1sL6e8+ch zOKKsPJPbD/Zw3ihvp04Zlbe2EOPKYe/aHXO9ADH1WlN1Hedvs8agNBelYDh4sKlVFoT 6O1S6VmtV/Y7xIwdqkhqWwRqMP1SEYv0wqbsN8s4Jb9SV0yKIFE5zLs5WvXn2otRfU79 UhdA== X-Gm-Message-State: AAQBX9cK5n/XVJ+iwJmZZGtmHFRcfxR6cEmoHEl4evdIcAjokU6Idipp 6V+KT7FlJUYx6szbNs41l6/CTKfYdscNbz0WHmU= X-Google-Smtp-Source: AKy350ZFcHDR3xtFi9ZiOrSX9nj9S9JpgvBiqz9V5hrZVv+/U0bDvfypERtVG6RLdCoWR88Bmki/jQ== X-Received: by 2002:a05:6870:5588:b0:17e:752f:2263 with SMTP id n8-20020a056870558800b0017e752f2263mr3647502oao.23.1680804282612; Thu, 06 Apr 2023 11:04:42 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 14/20] target/riscv: remove cpu->cfg.ext_h Date: Thu, 6 Apr 2023 15:03:45 -0300 Message-Id: <20230406180351.570807-15-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::35; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804446366100003 Content-Type: text/plain; charset="utf-8" Create a new "h" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVH. Instances of cpu->cfg.ext_h and similar are replaced with riscv_has_ext(env, RVH). Remove the old "h" property and 'ext_h' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 10 +++++----- target/riscv/cpu.h | 1 - 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9565495839..6291224905 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -847,13 +847,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) { + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { error_setg(errp, "H depends on an I base integer ISA with 32 x registers= "); return; } =20 - if (cpu->cfg.ext_h && !riscv_has_ext(env, RVS)) { + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { error_setg(errp, "H extension implicitly requires S-mode"); return; } @@ -1172,7 +1172,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVU)) { ext |=3D RVU; } - if (riscv_cpu_cfg(env)->ext_h) { + if (riscv_has_ext(env, RVH)) { ext |=3D RVH; } if (riscv_cpu_cfg(env)->ext_v) { @@ -1509,6 +1509,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVS, .enabled =3D true}, {.name =3D "u", .description =3D "User-level instructions", .misa_bit =3D RVU, .enabled =3D true}, + {.name =3D "h", .description =3D "Hypervisor", + .misa_bit =3D RVH, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1533,7 +1535,6 @@ static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), - DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), @@ -1647,7 +1648,6 @@ static void register_cpu_props(Object *obj) */ if (cpu->env.misa_ext !=3D 0) { cpu->cfg.ext_v =3D misa_ext & RVV; - cpu->cfg.ext_h =3D misa_ext & RVH; cpu->cfg.ext_j =3D misa_ext & RVJ; =20 /* diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 486061589e..823be82239 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -423,7 +423,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_h; bool ext_j; bool ext_v; bool ext_zba; --=20 2.39.2 From nobody Wed May 15 04:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680804462; cv=none; d=zohomail.com; s=zohoarc; b=cryPxiz0fx8D43HmuyJ0f7Kk0d9W5l56Wy3AxeGc/M4xobDPuvLW1H5ZdB/Wu/q3ucqrM9IjtSqoH5rfUjDNZU7l4BA1ZDJZdff8UhPL2lferxqs8mSN4wlxJtZUFJlOAKHpjo6L4PdeEMhGeJWwO547DBmArJ/MCSGSwK4hocU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680804462; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=poHf77vQ3VNnHuESrhfohTdDZ+AufSDEZlCfhUB/J+s=; b=ACQoPkE7HNpPnw6TzIxAseecCMcHLGgf8BAX57C/hEb+G1plr1vEUDKUUQIv3pm0E90Ray81oO5jehIuC5uT+G6Nbt0YHUVvcT+0ukrMDEcN3VUrX7zzz/n3iaTly4iz9Ke5rswkypi39bByAetYArsBS6+R0LonBGLTYpK0tyA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680804462683751.7504078901296; Thu, 6 Apr 2023 11:07:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkTyc-0001JU-GS; Thu, 06 Apr 2023 14:04:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkTya-0001E0-FI for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:48 -0400 Received: from mail-oa1-x2d.google.com ([2001:4860:4864:20::2d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkTyY-0000dG-RW for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:48 -0400 Received: by mail-oa1-x2d.google.com with SMTP id 586e51a60fabf-17aa62d0a4aso43232206fac.4 for ; Thu, 06 Apr 2023 11:04:46 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804286; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=poHf77vQ3VNnHuESrhfohTdDZ+AufSDEZlCfhUB/J+s=; b=CgtrCqHq2jBLxOwfJUIeFmPTGNFOiEYWBglD2fLnKOzs1G8H0rzO6phTEi9/1TlIAL dQOYzUG3m39dIc7aHT+SqzbuMg3uJdTHG/gBqSAuqo9UcZvwi0oL6OQHXZeVtB0yD/JV KiMzmPgieLou52PMXeFExEC1b6kpBSdcPTbpQoYBXb8IFD7vh8wjtmYJQQudFA7T/Lvk JT6QXyFiY8hhABiZ4BecL/GSFtODOB+fs34wZlCQhCf8D3EZ0xPM3Ph/284eGfMKf620 W2qShEn9Gjs+Kqv/CgjhMEWvV4GCEZcOv0KXbGZNYa9/8z0QtwKpSLaL/zcOjHHkke3C ARbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804286; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=poHf77vQ3VNnHuESrhfohTdDZ+AufSDEZlCfhUB/J+s=; b=lsnV8WlvfqaDvXqyw74mKO/ydVEKz4wCC4Tnw+wae/kFhsp1QicHbkoTt8UWywYOt6 1c4/04bRdZBeUeT6LH8MoUZZCO2jSqHgH32lz3yfeeH3AWKLpzj5etvICRMt737LxqVN xv94GmdqB3oeDi5nYf74RayG3vG8YGh848/pNhJ0bnBxvH4iU6fSnbpFox1VzSThIN8f qZ9R4X4O+bFRnptsuxw+QvVT/LTufzjPxZ0aUofd+bPI3vAQNFW/7zd6QzaPHWa6bl6h mI+ZuQQa1mDm+GSiqax71Iu0SfFrZ2C3zzu+E64rasTBKufjjexcJHj6zOM0620RbK8N Ah8g== X-Gm-Message-State: AAQBX9dA0T7TDBwNXligFLwfMXBrB+woThXbe7zLToaRXbo5VwxFHbck cXN5tWjXtCnxk3WQ3ipv6ARket4+wA20aoB60Uw= X-Google-Smtp-Source: AKy350ZpbCeXu1Bm664BV6kMsdxmFsRbj4dXcVTWB2mu70x3HcCIveJA3BAfEMV75LnaKYfLdX6VxA== X-Received: by 2002:a05:6870:3909:b0:177:a97c:ecde with SMTP id b9-20020a056870390900b00177a97cecdemr137065oap.22.1680804285816; Thu, 06 Apr 2023 11:04:45 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 15/20] target/riscv: remove cpu->cfg.ext_j Date: Thu, 6 Apr 2023 15:03:46 -0300 Message-Id: <20230406180351.570807-16-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804463781100001 Content-Type: text/plain; charset="utf-8" Create a new "j" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are replaced with riscv_has_ext(env, RVJ). Remove the old "j" property and 'ext_j' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 6 +++--- target/riscv/cpu.h | 1 - 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6291224905..3bdd6875a8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1178,7 +1178,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_cpu_cfg(env)->ext_v) { ext |=3D RVV; } - if (riscv_cpu_cfg(env)->ext_j) { + if (riscv_has_ext(env, RVJ)) { ext |=3D RVJ; } =20 @@ -1511,6 +1511,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVU, .enabled =3D true}, {.name =3D "h", .description =3D "Hypervisor", .misa_bit =3D RVH, .enabled =3D true}, + {.name =3D "x-j", .description =3D "Dynamic translated languages", + .misa_bit =3D RVJ, .enabled =3D false}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1607,7 +1609,6 @@ static Property riscv_cpu_extensions[] =3D { =20 /* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), - DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), =20 DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), @@ -1648,7 +1649,6 @@ static void register_cpu_props(Object *obj) */ if (cpu->env.misa_ext !=3D 0) { cpu->cfg.ext_v =3D misa_ext & RVV; - cpu->cfg.ext_j =3D misa_ext & RVJ; =20 /* * We don't want to set the default riscv_cpu_extensions diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 823be82239..1aff93ba91 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -423,7 +423,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_j; bool ext_v; bool ext_zba; bool ext_zbb; --=20 2.39.2 From nobody Wed May 15 04:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680804327; cv=none; d=zohomail.com; s=zohoarc; b=dwKxK6F5ijvv3YI30LkIYL1jM12AsYtGAZ3rgRAWhaFOOZJGgx7qgPYeU3QGUElo2nrSbdVMDAD4kVNEsaaIub+iyMvuIWQFeuypLSzLOthCXQjNMPotDGsGLMrQmSVsEdSNpYhvrwnP2J3x09fh3FYJ4jNIbWUXvRIhG09i6Ic= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680804327; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3Mgql+kTJwKO8IFxJFExkT4T9FA8hB8atR2o11uBQrY=; b=YFryDl8hzWka3f/jgYNdcO6K0QUb8QJGWX2MkaPvAY3oFAQTK3gTlpYAQnW6knvkzwDgLlHYDyyHdBCmA589eBbaXGG86MfDSHcaS6OoMcQN9Rl383NJnBcCFglMlI8duF11keezFpiR4zPNgu3qjXCuqctctboXzIV7yXd4zJs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680804327689642.6429917990076; Thu, 6 Apr 2023 11:05:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkTyo-0001MP-1L; Thu, 06 Apr 2023 14:05:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkTye-0001L3-Iv for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:52 -0400 Received: from mail-oa1-x2a.google.com ([2001:4860:4864:20::2a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkTyc-0000bX-5v for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:51 -0400 Received: by mail-oa1-x2a.google.com with SMTP id 586e51a60fabf-17aeb49429eso43239034fac.6 for ; Thu, 06 Apr 2023 11:04:49 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804289; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3Mgql+kTJwKO8IFxJFExkT4T9FA8hB8atR2o11uBQrY=; b=N9J763Qcep8NgBLYxWt3nQSmxW7O2+0d+QpyybZD8Uic2Kg4q9+oUwXnVR11hp79IH rrR+MR4bzIJizFpz5igdGrq2Gqq+080lGv5oS0Zq3HAtFfpqrNnutDo2xlBJIrtLkGLD WRm2eoDmcZ+tEkHbcGU3stSaRto8Bpf9CPos69RSCWiGw2zEt0sFYAyuNzXZD9ir8wvU tSS1AaRCd2/IzgkQc+Bn8esdLGAx2hTtikmgfhKKFAndfYO7cDbJXCAxMGqpEw21LAAN W4eMmSSgBi621hVJY5iqqN6OF+rFeoQx7OCAd+RKwjfBj1UlFS68xdAOUvZXr7ednXOy n+Tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804289; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3Mgql+kTJwKO8IFxJFExkT4T9FA8hB8atR2o11uBQrY=; b=tLTGXjNMcRo1Df5kA+JwMSwInJpXywPQTzLuWeT1TGfWPZc+uTFh6hlNwpFNOj0Kb2 EbHunj+7k6VJvz3sy0ZjONB/iV1gtyVCkUeoHk9fpGMh9FdA+lV7YWgyjHTZToN+/lvS jyU60QZh+cYr8bpIFhG4S7L7ZLCxg+3fpkzqHb+Tzs3ks8DDhh15BB5C+rIUs++kH3Js YqZkLSfQYKXPf+VBTHBuXQ34ye+cV8gDQjC8Tu1je/kA8nskcj0I+DML/L4U28uojNy4 iG92lOUY9FmreXZx5/lmKI7r4uJl3TKAcOdmzX0Nn42DWVtTkCm4pGfBPnWWzZIhZsz6 o0BA== X-Gm-Message-State: AAQBX9eFw1PxYleALMW+iSLWvFBO5H29x0IE7jD4jhsKojkKTiWTxAdD adH+/Vh0PB95r4MLOdjyN74KtNrelTaY2dByK2U= X-Google-Smtp-Source: AKy350ZX2xleF9w+p9tujIlNq59MIhenTXYcUhcAACzhs+XuUETeHiCXfgbP1Xx4wJ5g3pYmbSIe0w== X-Received: by 2002:a05:6870:3416:b0:172:289b:93c5 with SMTP id g22-20020a056870341600b00172289b93c5mr3691091oah.0.1680804289154; Thu, 06 Apr 2023 11:04:49 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 16/20] target/riscv: remove cpu->cfg.ext_v Date: Thu, 6 Apr 2023 15:03:47 -0300 Message-Id: <20230406180351.570807-17-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2a; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804329679100011 Content-Type: text/plain; charset="utf-8" Create a new "v" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVV. Instances of cpu->cfg.ext_v and similar are replaced with riscv_has_ext(env, RVV). Remove the old "v" property and 'ext_v' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 12 +++++------- target/riscv/cpu.h | 1 - 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3bdd6875a8..13ff37250e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -883,7 +883,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) } =20 /* The V vector extension depends on the Zve64d extension */ - if (cpu->cfg.ext_v) { + if (riscv_has_ext(env, RVV)) { cpu->cfg.ext_zve64d =3D true; } =20 @@ -1018,7 +1018,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) cpu->cfg.ext_zksh =3D true; } =20 - if (cpu->cfg.ext_v) { + if (riscv_has_ext(env, RVV)) { int vext_version =3D VEXT_VERSION_1_00_0; if (!is_power_of_2(cpu->cfg.vlen)) { error_setg(errp, @@ -1175,7 +1175,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVH)) { ext |=3D RVH; } - if (riscv_cpu_cfg(env)->ext_v) { + if (riscv_has_ext(env, RVV)) { ext |=3D RVV; } if (riscv_has_ext(env, RVJ)) { @@ -1513,6 +1513,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVH, .enabled =3D true}, {.name =3D "x-j", .description =3D "Dynamic translated languages", .misa_bit =3D RVJ, .enabled =3D false}, + {.name =3D "v", .description =3D "Vector operations", + .misa_bit =3D RVV, .enabled =3D false}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1536,7 +1538,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), - DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), @@ -1638,7 +1639,6 @@ static Property riscv_cpu_extensions[] =3D { static void register_cpu_props(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); - uint32_t misa_ext =3D cpu->env.misa_ext; Property *prop; DeviceState *dev =3D DEVICE(obj); =20 @@ -1648,8 +1648,6 @@ static void register_cpu_props(Object *obj) * later on. */ if (cpu->env.misa_ext !=3D 0) { - cpu->cfg.ext_v =3D misa_ext & RVV; - /* * We don't want to set the default riscv_cpu_extensions * in this case. diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1aff93ba91..e011cf6ca4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -423,7 +423,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_v; bool ext_zba; bool ext_zbb; bool ext_zbc; --=20 2.39.2 From nobody Wed May 15 04:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680804326; cv=none; d=zohomail.com; s=zohoarc; b=DpBMsHkwe9dwj7A0cFcMLgS3FJVnMIDSmOegLwW8RjfEJguyFMSV0hf/wHdJzAPLxxCHq3klOgn194Mfgc+7g2RgHyy29xnQQIjaOivHqoPzyurwpKD1M48bnucbgdBbjKuwycEU/uD8LuTv7DoAOx2i5wqTtA7+EtMBHDA7mxo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680804326; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wHPNf4kdLUhpUsUNMstnp9axE6T2pMxIcnuffMw58a4=; b=QnJner9PbZp1AMYx7uG6IMAn8TdDbcZ9cMABb0namqRdIoqEWVei6X98+9CBb9cOKaVArCV65aPn8e/mm/dY0ASHpmuhHrlS8KhOE5vTuiYX3B8upB3d4iKNo3lLiQ7jjkehI96YNkCsMNAKo2NXIyYoNxhTJQnl4lB1+XNy37g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680804326355136.18856272299251; Thu, 6 Apr 2023 11:05:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkTyu-0001Vf-9T; Thu, 06 Apr 2023 14:05:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkTyn-0001Mt-Qg for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:05:02 -0400 Received: from mail-oa1-x34.google.com ([2001:4860:4864:20::34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkTyg-0000eM-MP for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:58 -0400 Received: by mail-oa1-x34.google.com with SMTP id 586e51a60fabf-183f4efa98aso2161147fac.2 for ; Thu, 06 Apr 2023 11:04:52 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804292; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wHPNf4kdLUhpUsUNMstnp9axE6T2pMxIcnuffMw58a4=; b=EdtlV3aRc5K+rHsVsm1W84z9aiAxgA70QeZFXVBf/vOa4ABM2he4S/pdqmoCnpAdKK TDxpabc1qAABFacHg97TjBOIxpremerN8o0uXP58dc2kbzx51mTuX/LDUaAx/gdtMAIO fgTnCHCPErg+DrfxbbuAmV+JQQ//KVAx7+LBn7VTQrr5lH1IlfbTzUxrXa8tOgmtYY3C tHUKx72eALECWZTrHOmhWC3lj5aJ5opPytMoLXVFeq8BZIJKu9dnzf28SSe/XGZKSv0A ejj9yQlFFJXoP1S6gSWyN78AjWQn1hXu8TRuONfEo33Ljj3j33/bRAbqNkvvml3YyTZE 345w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804292; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wHPNf4kdLUhpUsUNMstnp9axE6T2pMxIcnuffMw58a4=; b=a9O2fdnJjPTULH/BZn+14oZeSKmmEg05gxS/LV59IQ1EOqDqH1OFEZkQ8VmNXdLbtY jJaB8+OR9hBryUq/iePI8t0Vg1jvrtIzzWNrRtb9g3Lcse61QgPK3VIR35Gj+mauggGz 97nsVVgXNqdnUtMyvVMxBfhTV+rlp2ajKa4XlqWNlY7/MWO7Tp+BD/w4fBSstPwtx3s0 8QsHKdj/tPuxghGjDG9vE68UpYKCM+mY4kxgFWmm+FMUBhmxB2lBrqspSPywrS40Cm0V yW8CkU7/fhafMnrglnLyUdcIVZe4xLHgfY0mw3dKAej8rRM6jWJwEFXjIeXhrg1TaOk3 9JqA== X-Gm-Message-State: AAQBX9f09Fow3GyFzn/doFLSyGYmOh3z010vAuKFFI3QCoJ15ptJopeN PHBb6XkGEfoBqqxvkWxteIWlR9Dij73amHhE6Sw= X-Google-Smtp-Source: AKy350ahXSaM7/GUi/ATigD7oYJpzur469Rv9JgQVNIzW+cScj5ColLyTvx9DijFWgg4Fq6xisimuQ== X-Received: by 2002:a05:6870:c1d5:b0:180:1faa:7c1c with SMTP id i21-20020a056870c1d500b001801faa7c1cmr63077oad.46.1680804292295; Thu, 06 Apr 2023 11:04:52 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 17/20] target/riscv: remove riscv_cpu_sync_misa_cfg() Date: Thu, 6 Apr 2023 15:03:48 -0300 Message-Id: <20230406180351.570807-18-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::34; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804327310100001 Content-Type: text/plain; charset="utf-8" This function was created to move the sync between cpu->cfg.ext_N bit changes to env->misa_ext* from the validation step to an ealier step, giving us a guarantee that we could use either cpu->cfg.ext_N or riscv_has_ext(env,N) in the validation. We don't have any cpu->cfg.ext_N left that has an existing MISA bit (cfg.ext_g will be handled shortly). The function is now a no-op, simply copying the existing values of misa_ext* back to misa_ext*. Remove it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 52 ---------------------------------------------- 1 file changed, 52 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 13ff37250e..1ecb82bb5d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1141,50 +1141,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cp= u, Error **errp) #endif } =20 -static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) -{ - uint32_t ext =3D 0; - - if (riscv_has_ext(env, RVI)) { - ext |=3D RVI; - } - if (riscv_has_ext(env, RVE)) { - ext |=3D RVE; - } - if (riscv_has_ext(env, RVM)) { - ext |=3D RVM; - } - if (riscv_has_ext(env, RVA)) { - ext |=3D RVA; - } - if (riscv_has_ext(env, RVF)) { - ext |=3D RVF; - } - if (riscv_has_ext(env, RVD)) { - ext |=3D RVD; - } - if (riscv_has_ext(env, RVC)) { - ext |=3D RVC; - } - if (riscv_has_ext(env, RVS)) { - ext |=3D RVS; - } - if (riscv_has_ext(env, RVU)) { - ext |=3D RVU; - } - if (riscv_has_ext(env, RVH)) { - ext |=3D RVH; - } - if (riscv_has_ext(env, RVV)) { - ext |=3D RVV; - } - if (riscv_has_ext(env, RVJ)) { - ext |=3D RVJ; - } - - env->misa_ext =3D env->misa_ext_mask =3D ext; -} - static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) { if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { @@ -1228,14 +1184,6 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) set_priv_version(env, priv_version); } =20 - /* - * We can't be sure of whether we set defaults during cpu_init() - * or whether the user enabled/disabled some bits via cpu->cfg - * flags. Sync env->misa_ext with cpu->cfg now to allow us to - * use just env->misa_ext later. - */ - riscv_cpu_sync_misa_cfg(env); - riscv_cpu_validate_misa_priv(env, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.39.2 From nobody Wed May 15 04:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680804407; cv=none; d=zohomail.com; s=zohoarc; b=mn69dGpI+SxRcB9UB3tWXCb2gD+RO9Tdj8w27t1eFIHrfQbJJPOubBhmw0bzeqCXHQ0+kwy6jptodsOkBogdXUWD8buX3YolYgls1RfoJsnefzYsEl1343ezZxzOfKZ60vNmz3IMA5QMWKJyN4sVlEkDRkcDx2StUW8IiZJHdZY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680804407; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6Wyx1FHmxLdFtf+sn5xFAZ+OPtPshuj5d2U+hRYbEPU=; b=KWxb7vYED15zp4eeoInw5rRXb2+ar+dv0ZsD7qxi92gJ8VXbB9r/nhaj1ZItSp9cCRpqi7T2tSVvErU/+hC762tSmylERRg8GDeZIfLcargOWSoiUNMlC/wodn4cg67w7ps2cAFxNtXnqFSsHiRAjV9iv3cnqat33TM2ghGlAV8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680804407663827.5775437919827; Thu, 6 Apr 2023 11:06:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkTys-0001Rw-1S; Thu, 06 Apr 2023 14:05:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkTyn-0001Ms-MK for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:05:01 -0400 Received: from mail-oa1-x32.google.com ([2001:4860:4864:20::32]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkTyj-0000bw-CY for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:04:59 -0400 Received: by mail-oa1-x32.google.com with SMTP id 586e51a60fabf-17aeb49429eso43239353fac.6 for ; Thu, 06 Apr 2023 11:04:56 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6Wyx1FHmxLdFtf+sn5xFAZ+OPtPshuj5d2U+hRYbEPU=; b=ndQ2X+kmw7UYP2zhjJqqooTLbEUUbWfBrKw9NbAXLWK9Iiace0HRsEoFeh5Mi0iAWS 8FqJdzSrYpbmlMCTmq8hHQuhwHfxTylLigDSyUcb9PQu5eC9kGxxrK+JJhBU8HmI2s1n 9UyEBToSFbpaQe3OhGoj5YBzYrFOOczE1Vw9hUGj47XnAZe6b5poDPpYPO5zV5ICCd5z 1nQEv7hyltpeYQYjXg6v13l9QDiHv2gcy8x+pGNe1dUG+SgklkgwDmgN6XTnuDoXcGkQ zxziRtWCaVagpKtw2PqNkvXbpamaV6ts7NwNIT4SEhSxK32A6Xy6Hc/JK/EBeYUGhkld aFOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6Wyx1FHmxLdFtf+sn5xFAZ+OPtPshuj5d2U+hRYbEPU=; b=GPXyt0h31L3Hua6RjgGFS0C4sSUHHv/6wzu7DYlFZQq69PrnNF1Z6FY8vp3d8XRbz2 KABM07FfNm7UCA6rwuGLtW6ZZmES+YILYeZSYzEgyMlw4KrLdrW6For+HtdmXcZw4pMM JtkkZ+CZCgg5aimTDRCxqRGSSa2HKlnuDtLbDkyjD+1irZ9gVFYi0KKkrYT5KYiBXAHU Vx/KgJt0jxmxmC6sDI4TxZha65jbCBhN1DyPOaOWErnEodiPvsXB26+KsvRjpIqlDAZh wzem+v5YvQxF0w51mfzfDsDc9sDSxN8dhgo5VtBNJIHAwsVMK+HhKQRORa4Mlfx/kHNb Xi0w== X-Gm-Message-State: AAQBX9eSjnkh3h386JeT+2MGpfrHZFXpc5YBuPq0Dv9cgvMljoplM5Bv k62gxM+iI1kIe7qWGk4OkodPxnOLkRfY3z5hfes= X-Google-Smtp-Source: AKy350YBor918awCNStMZ1zlzHp0MzyDIeSR9kuuQW3BNyaD1juNywcjPXBxBdnSK/VeetETpOYLfA== X-Received: by 2002:a05:6870:d595:b0:177:a4d0:e389 with SMTP id u21-20020a056870d59500b00177a4d0e389mr110831oao.28.1680804295404; Thu, 06 Apr 2023 11:04:55 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 18/20] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init() Date: Thu, 6 Apr 2023 15:03:49 -0300 Message-Id: <20230406180351.570807-19-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804409764100003 Content-Type: text/plain; charset="utf-8" This CPU is enabling G via cfg.ext_g and, at the same time, setting IMAFD in set_misa() and cfg.ext_icsr. riscv_cpu_validate_set_extensions() is already doing that, so there's no need for cpu_init() setups to worry about setting G and its extensions. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1ecb82bb5d..b005bcb786 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -403,11 +403,10 @@ static void rv64_thead_c906_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_misa(env, MXL_RV64, RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_11_0); =20 cpu->cfg.ext_g =3D true; - cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_zfh =3D true; cpu->cfg.mmu =3D true; cpu->cfg.ext_xtheadba =3D true; --=20 2.39.2 From nobody Wed May 15 04:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680804418; cv=none; d=zohomail.com; s=zohoarc; b=SeJB0KtKGWyM9P1nsvZ12svXSMuVL+PRuqqg45gG3t9SKgKXs0fpHeQLtmohXAPBG75jzAsP0vQQG+85aWH116vMQyXZLw1YyTb/WdyhMT4dpjDuNBc7bIEBGwfkiqf0x56gWJPEbkS8lIBZiswWQQLj9ay5t+0Z4095eiAh2fg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680804418; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2dnARg6F+1M5N4kesIx/7lK61VGskg0uBXfjuGkWyQw=; b=HsJpDOkF7EL6gUU2JvBzIzPbujRlsi0shsgxR9fL9KPr+05t8LJqm0v+GfOzWN8ErbWEpDuuwV8GLkOPFwEt7EAG0UEGyyZMVfqhMOSVP5LdsEMPTOjaDpDGcBfe8uJ74q9rmuPjUetdKG06Cz7qrsJ9XTisPhFLOgq3p252cUc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680804418161924.6093356507673; Thu, 6 Apr 2023 11:06:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkTys-0001Sh-Kv; Thu, 06 Apr 2023 14:05:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkTyp-0001QC-Gi for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:05:04 -0400 Received: from mail-oa1-x31.google.com ([2001:4860:4864:20::31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkTyn-0000eO-Gd for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:05:03 -0400 Received: by mail-oa1-x31.google.com with SMTP id 586e51a60fabf-17fcc07d6c4so29157199fac.8 for ; Thu, 06 Apr 2023 11:04:59 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804298; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2dnARg6F+1M5N4kesIx/7lK61VGskg0uBXfjuGkWyQw=; b=GehDbJeZOE6m0tXy1ITV35kss17z130eIf5ZYSMHv/BRM+XHL40z2Y73w6uuztd0B6 Upol5z4ldx+8q/LYWtmS6/lfux7w1S2rcIFarUBJG+KpNyfTFGx2b6wdHIkCCEGsvC3y QO6exmvGkZDuBlc9NIS84ut1iOLtnPCi5y8fn+9A3x7GImR6T0kDrfuWfoe75i61pMHF Rw0nfekDDUsoONKWM4O8/X+lfmLvqUHBGI1KNNhoRDJnJvZMOoQBNIYx85BJZAnODoQB I9FAXcvWeAnxd+i3kkwkweade8UwM85rBVkfFLYfEW3mBT3b7ZFISkJLyo9lbaXovA6w igBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804298; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2dnARg6F+1M5N4kesIx/7lK61VGskg0uBXfjuGkWyQw=; b=PyhNuSzL+74mXdAn8blhIkY3tqLPxbNiAcAyaIUReXlj8E0/HaiXJ/0z0M6xEMjbx4 UdjwK9XYaeKWfcoxRV5DnsoTJZFvgtFxgClNDQYs2aPzra97MkNlrto3iCDKG0mFqH/K TxBQg6W4xYHbehaNdLsz77TxpANQiDnKomn5SWmBMe9hdEUfRfrZbdjZBt5DY5zxsSSi V67XG20Te7WGvtIWfuthE9YxmoM/ohps9WupZD9iFIHWCTpob6DhCYmZ1jPRiq+GLUWb b3HrPyWkCkr4o+VdEFTOdjK9CZvg0ZTF+IEL0znZ129YNlOSju8cl8T8AY7yNJaGCT0O czFg== X-Gm-Message-State: AAQBX9crWbIlbuXKGn9CQ+aH4Ir3VpZ9Gh+0p3vlXZaHuyjrm171C//0 2VUbRaUpKDJ9Znwk2ShgxOCYZfxuzxAsoW2mWQM= X-Google-Smtp-Source: AKy350ZUaAFKEWbsjii8HaMQgAU8ApgCWVV8pA68iw43SgQqk2gSjSY7F9VgRs6IE9A5yjFy1XblIA== X-Received: by 2002:a05:6870:b28f:b0:183:cc50:f771 with SMTP id c15-20020a056870b28f00b00183cc50f771mr116038oao.25.1680804298491; Thu, 06 Apr 2023 11:04:58 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 19/20] target/riscv: add RVG and remove cpu->cfg.ext_g Date: Thu, 6 Apr 2023 15:03:50 -0300 Message-Id: <20230406180351.570807-20-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804419198100001 Content-Type: text/plain; charset="utf-8" We're still have one RISCVCPUConfig MISA flag, 'ext_g'. We'll remove it the same way we did with the others: create a "g" RISCVCPUMisaExtConfig property, remove the old "g" property, remove all instances of 'cfg.ext_g' and use riscv_has_ext(env, RVG). The caveat is that we don't have RVG, so add it. RVG will be used right off the bat in set_misa() of rv64_thead_c906_cpu_init() because the CPU is enabling G via the now removed 'ext_g' flag. After this patch, there are no more MISA extensions represented by flags in RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 17 ++++++++--------- target/riscv/cpu.h | 2 +- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b005bcb786..143079a8df 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -403,10 +403,9 @@ static void rv64_thead_c906_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV64, RVC | RVS | RVU); + set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_11_0); =20 - cpu->cfg.ext_g =3D true; cpu->cfg.ext_zfh =3D true; cpu->cfg.mmu =3D true; cpu->cfg.ext_xtheadba =3D true; @@ -814,12 +813,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) CPURISCVState *env =3D &cpu->env; =20 /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && - riscv_has_ext(env, RVM) && - riscv_has_ext(env, RVA) && - riscv_has_ext(env, RVF) && - riscv_has_ext(env, RVD) && - cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { + if (riscv_has_ext(env, RVG) && + !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && + riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && + riscv_has_ext(env, RVD) && + cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; @@ -1462,6 +1460,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVJ, .enabled =3D false}, {.name =3D "v", .description =3D "Vector operations", .misa_bit =3D RVV, .enabled =3D false}, + {.name =3D "g", .description =3D "General purpose (IMAFD_Zicsr_Zifence= i)", + .misa_bit =3D RVG, .enabled =3D false}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1484,7 +1484,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) =20 static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ - DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e011cf6ca4..070547234b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -81,6 +81,7 @@ #define RVU RV('U') #define RVH RV('H') #define RVJ RV('J') +#define RVG RV('G') =20 =20 /* Privileged specification version */ @@ -422,7 +423,6 @@ typedef struct { } RISCVSATPMap; =20 struct RISCVCPUConfig { - bool ext_g; bool ext_zba; bool ext_zbb; bool ext_zbc; --=20 2.39.2 From nobody Wed May 15 04:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1680804402; cv=none; d=zohomail.com; s=zohoarc; b=DPYh4Vy2nXT3I9wvcVJJeqJuRnfSN4gcVX6u9Z84hlXRfhFslu7kghmbJmTN63Vm9IQiHc+6FdDlS0Xm7aqZrRQlBXH+FzpkNzuWfwuweX2AGAKUCCvkvdEHDLow2qLXrh/W5bCJXOx5CdQd5I7+4DJoQpLAdXXBmhRUgBXiZ6Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1680804402; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oY1JOzwqJ/OA56uJv92L1IGN2k9NTuKv7EeDFnvQ2eo=; b=arDSbjqUEha6HMuOI3GwR2dpRd0yWQWum1VCdcFuW2HzX9QJh+tAwY6SCJRVKW8S/38bHAK5VW9AuHZAb9+F3htuUddyb6310gWwOLMdFSoZ+kjtucmzXCDfby1ObLzIvXoHFGhDqWAUCdberb/CoMytjIHM/oOc2mHwi6CbJ0c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680804402263564.6711252233059; Thu, 6 Apr 2023 11:06:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pkTyw-0001cN-0w; Thu, 06 Apr 2023 14:05:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pkTys-0001T6-E7 for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:05:06 -0400 Received: from mail-oa1-x2d.google.com ([2001:4860:4864:20::2d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pkTyp-0000dG-99 for qemu-devel@nongnu.org; Thu, 06 Apr 2023 14:05:06 -0400 Received: by mail-oa1-x2d.google.com with SMTP id 586e51a60fabf-17aa62d0a4aso43233226fac.4 for ; Thu, 06 Apr 2023 11:05:02 -0700 (PDT) Received: from grind.. ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:05:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804302; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oY1JOzwqJ/OA56uJv92L1IGN2k9NTuKv7EeDFnvQ2eo=; b=QHnLXPAF5Sgaa+jiZJRXWDnOs7+EhsDjy6kvZhK9oFz8CLOhC28+EiETQ8dxiuaoNM cg9uXqom/UiU7ejCjRT13Vk2kv9Spgq18Fuq4FeVV54GEDhcwDXAQTa1Ck7LRPc57AXI FUudNKpXYQikjGtPpmH2tH45YD2SYB4bHKrbPK7eWiItMYh2AOTK8A9sZV3HyFoO9unb seFmrLPf0T9E1aN4utUP5hDCk2mYzRKEyCvs/Wpw4hOgLU4fTXgyYSr/rngq5AgXukuu EYsx/wjSvjBBPEy3rakdBsXURWIyw0kx6OTnciHnBpIkHnkntI0OdJF73bXJCKek92DK uvBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804302; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oY1JOzwqJ/OA56uJv92L1IGN2k9NTuKv7EeDFnvQ2eo=; b=ly0jZQNXv/3cm0D2sf2M3z+hpr246tt8i7PdTQDRtRThYsGKvCQ4rhSv43lu+fTbIH Rw1SFxliyvDgcmdaLFfA+mF765xaL3ypLV9Hu5yBzu+NDJOFRGOPJT6typxhKCLCnXl+ HowYJkeR1ODyoQi9cvJjaZTTA4+gG5jS/kLm2yv5EAc32mDwXTpHWrq5JgrVQqqbiGt8 vLZK/FojfZ3g8y6xg0QcCTU9s9G518zSt+NMkramkM9vUsAqqtnGQaaqC2Ii4tZ1dKXP L3eb9JfWIvuKJTQhJ61SoLerb1+Vu2nivkwMy8uR4/8QBtv+2K+WY0Z1a1/y6Y2V2pXK R+Dg== X-Gm-Message-State: AAQBX9dhaW8tRQfcDWMiBlr+gsu9X/q2B+G3NA9ThRwF2y+6kWNKBuoW nVNkxFIQe0wbF7u1mySvejEdCDRtIXqgWmE/2x8= X-Google-Smtp-Source: AKy350aG++z4PIot/VYBR0y7NZ8A9pq+zNwpFRzMcA5xYXJvt9WKJz9bV3UGB/Y4mP/v6h+2qcrwMw== X-Received: by 2002:a05:6870:14c5:b0:17a:cb34:758a with SMTP id l5-20020a05687014c500b0017acb34758amr105053oab.34.1680804301887; Thu, 06 Apr 2023 11:05:01 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 20/20] target/riscv/cpu.c: redesign register_cpu_props() Date: Thu, 6 Apr 2023 15:03:51 -0300 Message-Id: <20230406180351.570807-21-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804403583100001 Content-Type: text/plain; charset="utf-8" The function is now a no-op for all cpu_init() callers that are setting a non-zero misa value in set_misa(), since it's no longer used to sync cpu->cfg props with env->misa_ext bits. Remove it in those cases. While we're at it, rename the function to match what it's actually doing: create user properties to set/remove CPU extensions. Make a note that it will overwrite env->misa_ext with the defaults set by each user property. Update the MISA bits comment in cpu.h as well. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 41 ++++++++++------------------------------- target/riscv/cpu.h | 5 +---- 2 files changed, 11 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 143079a8df..d1769fd218 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -228,7 +228,7 @@ static const char * const riscv_intr_names[] =3D { "reserved" }; =20 -static void register_cpu_props(Object *obj); +static void riscv_cpu_add_user_properties(Object *obj); =20 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { @@ -356,7 +356,6 @@ static void riscv_any_cpu_init(Object *obj) #endif =20 set_priv_version(env, PRIV_VERSION_1_12_0); - register_cpu_props(obj); } =20 #if defined(TARGET_RISCV64) @@ -365,7 +364,7 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); - register_cpu_props(obj); + riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); #ifndef CONFIG_USER_ONLY @@ -377,7 +376,6 @@ static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); @@ -390,7 +388,6 @@ static void rv64_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY @@ -436,7 +433,7 @@ static void rv128_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); - register_cpu_props(obj); + riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); #ifndef CONFIG_USER_ONLY @@ -449,7 +446,7 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); - register_cpu_props(obj); + riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); #ifndef CONFIG_USER_ONLY @@ -461,7 +458,6 @@ static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); @@ -474,7 +470,6 @@ static void rv32_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY @@ -488,7 +483,6 @@ static void rv32_ibex_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY @@ -503,7 +497,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); - register_cpu_props(obj); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY @@ -521,7 +514,7 @@ static void riscv_host_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, 0); #endif - register_cpu_props(obj); + riscv_cpu_add_user_properties(obj); } #endif =20 @@ -1577,30 +1570,16 @@ static Property riscv_cpu_extensions[] =3D { }; =20 /* - * Register CPU props based on env.misa_ext. If a non-zero - * value was set, register only the required cpu->cfg.ext_* - * properties and leave. env.misa_ext =3D 0 means that we want - * all the default properties to be registered. + * Add CPU properties with user-facing flags. + * + * This will overwrite existing env->misa_ext values with the + * defaults set via riscv_cpu_add_misa_properties(). */ -static void register_cpu_props(Object *obj) +static void riscv_cpu_add_user_properties(Object *obj) { - RISCVCPU *cpu =3D RISCV_CPU(obj); Property *prop; DeviceState *dev =3D DEVICE(obj); =20 - /* - * If misa_ext is not zero, set cfg properties now to - * allow them to be read during riscv_cpu_realize() - * later on. - */ - if (cpu->env.misa_ext !=3D 0) { - /* - * We don't want to set the default riscv_cpu_extensions - * in this case. - */ - return; - } - riscv_cpu_add_misa_properties(obj); =20 for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 070547234b..f47c3fc139 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -65,10 +65,7 @@ =20 #define RV(x) ((target_ulong)1 << (x - 'A')) =20 -/* - * Consider updating register_cpu_props() when adding - * new MISA bits here. - */ +/* Consider updating misa_ext_cfgs[] when adding new MISA bits here */ #define RVI RV('I') #define RVE RV('E') /* E and I are mutually exclusive */ #define RVM RV('M') --=20 2.39.2