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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id l26-20020a170906a41a00b009260634e25asm2526620ejz.121.2023.03.15.06.35.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 06:35:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1678887314; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=JMeY7OlPeMoHhkvzT7NtJPfGeoJnuULWDoHqSTPrTII=; b=XqVI09ASYSN7EPXySnMBxcKhFvmC12X2sqH3tQIA8GWBmEKCyVqF+WrNOJmrwBhMqO MBWfTjg/QczpnfVZL2J/OqxH96LFj20Q156+1NLv6f+D4L6htK2qkS8i5t2CES/+m2FO ZRp19qUTCXZQiinhYVeZ/S2kE+qU2og3DhbdT0CRJmKYxlH0h+YKsUYrUpxH1Z6Zn8TC PHtxtVjtEqRqvb898qLEspw1CymF6hqDqptQizxGjGNpOWlgTsghu51ziPaEpN8WDVy8 51h+AGLk+V+xjAqKw5BQpR09PDkBa0sjGIpJWM4j/ss8dYdtNViA5fI6Hcv2wW5uHrXF g6Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678887314; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=JMeY7OlPeMoHhkvzT7NtJPfGeoJnuULWDoHqSTPrTII=; b=HqXJ1UCHl8RM/mCQp/mQwQbS2HVt+071EWxXtvXcWP0DQcQWaO8xQuTstkoVzWULep kh78QdZcf2E3WlElrXfbQpHEGFbYonZzZZt7iDgp4gv+H7t5W68qy+t2FscDbVczGy9U VDJ2iLfoWSAHKVlJEJpiY/0JIdsd0KWzYVtLU/tmCSyO+hEHf6QoMYncBwRDswPi9/8a swW5+l0J8iKJsB6cUpmddUMOgnJjLlcXwvZJxc1PZBWTaTn+5Hs+VPyQ18spKdUXMBQF zQi8Af6/Yl60k+G0B5pYa3/XOYPAr17vugpfhMWqdo0hDL0jCr15wgCzsw8dtrhZ1WN6 dgqg== X-Gm-Message-State: AO0yUKVmRt88YIDkvvMlZxXhjdntTWY3rtumEun1Wd+9UGCzLyWhuU6c ZE/hO04O3KKPYf5aFqpdH6ibag== X-Google-Smtp-Source: AK7set/hcVkE/9IxiyT3xUMf7AfDZ0YqXN6dvNKcKfYG9kfyCl6RO81fgxCvoXISyiSaMbVY+rX1qg== X-Received: by 2002:a17:907:72c1:b0:920:388c:5c60 with SMTP id du1-20020a17090772c100b00920388c5c60mr8022263ejc.41.1678887314207; Wed, 15 Mar 2023 06:35:14 -0700 (PDT) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , Palmer Dabbelt , Richard Henderson , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= , Alistair Francis Subject: [PATCH] disas/riscv: Add support for XThead* instructions Date: Wed, 15 Mar 2023 14:35:10 +0100 Message-Id: <20230315133510.3511784-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=christoph.muellner@vrull.eu; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @vrull.eu) X-ZM-MESSAGEID: 1678887366013100003 From: Christoph M=C3=BCllner Support for emulating XThead* instruction has been added recently. This patch adds support for these instructions to the RISC-V disassembler. Co-developed-by: LIU Zhiwei Signed-off-by: Christoph M=C3=BCllner --- disas/riscv.c | 366 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 365 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/riscv.c index d6b0fbe5e8..14f3faaef4 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "disas/dis-asm.h" +#include "qemu/bitops.h" =20 =20 /* types */ @@ -163,6 +164,12 @@ typedef enum { rv_codec_v_i, rv_codec_vsetvli, rv_codec_vsetivli, + rv_codec_r2_imm5, + rv_codec_r2, + rv_codec_r2_imm6, + rv_codec_r_imm2, + rv_codec_r2_immhl, + rv_codec_r2_imm2_imm5, } rv_codec; =20 typedef enum { @@ -935,6 +942,90 @@ typedef enum { rv_op_vsetvli =3D 766, rv_op_vsetivli =3D 767, rv_op_vsetvl =3D 768, + /* XTheadBa */ + rv_op_th_addsl =3D 769, + /* XTheadBb */ + rv_op_th_srri =3D 770, + rv_op_th_srriw =3D 771, + rv_op_th_ext =3D 772, + rv_op_th_extu =3D 773, + rv_op_th_ff0 =3D 774, + rv_op_th_ff1 =3D 775, + rv_op_th_rev =3D 776, + rv_op_th_revw =3D 777, + rv_op_th_tstnbz =3D 778, + /* XTheadBs */ + rv_op_th_tst =3D 779, + /* XTheadCondMov */ + rv_op_th_mveqz =3D 780, + rv_op_th_mvnez =3D 781, + /* XTheadFMemIdx */ + rv_op_th_flrd =3D 782, + rv_op_th_flrw =3D 783, + rv_op_th_flurd =3D 784, + rv_op_th_flurw =3D 785, + rv_op_th_fsrd =3D 786, + rv_op_th_fsrw =3D 787, + rv_op_th_fsurd =3D 788, + rv_op_th_fsurw =3D 789, + /* XTheadMac */ + rv_op_th_mula =3D 790, + rv_op_th_mulah =3D 791, + rv_op_th_mulaw =3D 792, + rv_op_th_muls =3D 793, + rv_op_th_mulsw =3D 794, + rv_op_th_mulsh =3D 795, + /* XTheadMemIdx */ + rv_op_th_lbia =3D 796, + rv_op_th_lbib =3D 797, + rv_op_th_lbuia =3D 798, + rv_op_th_lbuib =3D 799, + rv_op_th_lhia =3D 800, + rv_op_th_lhib =3D 801, + rv_op_th_lhuia =3D 802, + rv_op_th_lhuib =3D 803, + rv_op_th_lwia =3D 804, + rv_op_th_lwib =3D 805, + rv_op_th_lwuia =3D 806, + rv_op_th_lwuib =3D 807, + rv_op_th_ldia =3D 808, + rv_op_th_ldib =3D 809, + rv_op_th_sbia =3D 810, + rv_op_th_sbib =3D 811, + rv_op_th_shia =3D 812, + rv_op_th_shib =3D 813, + rv_op_th_swia =3D 814, + rv_op_th_swib =3D 815, + rv_op_th_sdia =3D 816, + rv_op_th_sdib =3D 817, + rv_op_th_lrb =3D 818, + rv_op_th_lrbu =3D 819, + rv_op_th_lrh =3D 820, + rv_op_th_lrhu =3D 821, + rv_op_th_lrw =3D 822, + rv_op_th_lrwu =3D 823, + rv_op_th_lrd =3D 824, + rv_op_th_srb =3D 825, + rv_op_th_srh =3D 826, + rv_op_th_srw =3D 827, + rv_op_th_srd =3D 828, + rv_op_th_lurb =3D 829, + rv_op_th_lurbu =3D 830, + rv_op_th_lurh =3D 831, + rv_op_th_lurhu =3D 832, + rv_op_th_lurw =3D 833, + rv_op_th_lurwu =3D 834, + rv_op_th_lurd =3D 835, + rv_op_th_surb =3D 836, + rv_op_th_surh =3D 837, + rv_op_th_surw =3D 838, + rv_op_th_surd =3D 839, + /* XTheadMemPair */ + rv_op_th_ldd =3D 840, + rv_op_th_lwd =3D 841, + rv_op_th_lwud =3D 842, + rv_op_th_sdd =3D 843, + rv_op_th_swd =3D 844, } rv_op; =20 /* structures */ @@ -943,6 +1034,7 @@ typedef struct { uint64_t pc; uint64_t inst; int32_t imm; + int32_t imm1; uint16_t op; uint8_t codec; uint8_t rd; @@ -1071,6 +1163,11 @@ static const char rv_vreg_name_sym[32][4] =3D { #define rv_fmt_vd_vm "O\tDm" #define rv_fmt_vsetvli "O\t0,1,v" #define rv_fmt_vsetivli "O\t0,u,v" +#define rv_fmt_rd_rs1_rs2_imm "O\t0,1,2,i" +#define rv_fmt_frd_rs1_rs2_imm "O\t3,1,2,i" +#define rv_fmt_rd_rs1_immh_imml "O\t0,1,i,j" +#define rv_fmt_rd_rs1_immh_imml_addr "O\t0,(1),i,j" +#define rv_fmt_rd2_imm "O\t0,2,(1),i" =20 /* pseudo-instruction constraints */ =20 @@ -2066,7 +2163,91 @@ const rv_opcode_data opcode_data[] =3D { { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf8, = rv_op_vsext_vf8, 0 }, { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, rv_op_vsetvli, rv= _op_vsetvli, 0 }, { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, rv_op_vsetivli= , rv_op_vsetivli, 0 }, - { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_v= setvl, 0 } + { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_v= setvl, 0 }, + /* XTheadBa */ + { "th.addsl", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + /* XTheadBb */ + { "th.srri", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0}, + { "th.srriw", rv_codec_r2_imm5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0}, + { "th.ext", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml, NULL, 0, 0, 0}, + { "th.extu", rv_codec_r2_immhl, rv_fmt_rd_rs1_immh_imml, NULL, 0, 0, 0= }, + { "th.ff0", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "th.ff1", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "th.rev", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "th.revw", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "th.tstnbz", rv_codec_r2, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + /* XTheadBs */ + { "th.tst", rv_codec_r2_imm6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0}, + /* XTheadCondMov */ + { "th.mveqz", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "th.mvnez", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + /* XTheadFMemIdx */ + { "th.flrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.flrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.flurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.flurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.fsrd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.fsrw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.fsurd", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.fsurw", rv_codec_r_imm2, rv_fmt_frd_rs1_rs2_imm, NULL, 0, 0, 0 }, + /* XTheadMac */ + { "th.mula", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "th.mulaw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "th.mulah", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "th.muls", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "th.mulsw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + { "th.mulsh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, + /* XTheadMemIdx */ + { "th.lbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL= , 0, 0, 0 }, + { "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml, NULL, 0, = 0, 0 }, + { "th.lbuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NUL= L, 0, 0, 0 }, + { "th.lbuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NUL= L, 0, 0, 0 }, + { "th.lhia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL= , 0, 0, 0 }, + { "th.lhib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL= , 0, 0, 0 }, + { "th.lhuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NUL= L, 0, 0, 0 }, + { "th.lhuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NUL= L, 0, 0, 0 }, + { "th.lwia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL= , 0, 0, 0 }, + { "th.lwib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL= , 0, 0, 0 }, + { "th.lwuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NUL= L, 0, 0, 0 }, + { "th.lwuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NUL= L, 0, 0, 0 }, + { "th.ldia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL= , 0, 0, 0 }, + { "th.ldib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL= , 0, 0, 0 }, + { "th.sbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL= , 0, 0, 0 }, + { "th.sbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL= , 0, 0, 0 }, + { "th.shia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL= , 0, 0, 0 }, + { "th.shib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL= , 0, 0, 0 }, + { "th.swia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL= , 0, 0, 0 }, + { "th.swib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL= , 0, 0, 0 }, + { "th.sdia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL= , 0, 0, 0 }, + { "th.sdib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL= , 0, 0, 0 }, + { "th.lrb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.lrbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.lrh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.lrhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.lrw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.lrwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.lrd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.srb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.srh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.srw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.srd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.lurb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.lurbu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.lurh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.lurhu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.lurw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.lurwu", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.lurd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.surb", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.surh", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.surw", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + { "th.surd", rv_codec_r_imm2, rv_fmt_rd_rs1_rs2_imm, NULL, 0, 0, 0 }, + /* XTheadMemPair */ + { "th.ldd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 }, + { "th.lwd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 }, + { "th.lwud", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 }, + { "th.sdd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 }, + { "th.swd", rv_codec_r_imm2, rv_fmt_rd2_imm, NULL, 0, 0, 0 }, }; =20 /* CSR names */ @@ -2528,6 +2709,133 @@ static void decode_inst_opcode(rv_decode *dec, rv_i= sa isa) break; } break; + case 2: + /* custom-0 */ + switch ((inst >> 12) & 0b111) { + case 0: /* ingore priviledged inst */ break; + case 1: + switch ((inst >> 25) & 0b1111111) { + case 0b0001010: op =3D rv_op_th_srriw; break; + case 0b0010000: op =3D rv_op_th_mula; break; + case 0b0010001: op =3D rv_op_th_muls; break; + case 0b0010010: op =3D rv_op_th_mulaw; break; + case 0b0010011: op =3D rv_op_th_mulsw; break; + case 0b0010100: op =3D rv_op_th_mulah; break; + case 0b0010101: op =3D rv_op_th_mulsh; break; + case 0b0100000: op =3D rv_op_th_mveqz; break; + case 0b0100001: op =3D rv_op_th_mvnez; break; + case 0b1000000: + if (((inst >> 20) & 0b11111) =3D=3D 0) { + op =3D rv_op_th_tstnbz; + } + break; + case 0b1000001: + if (((inst >> 20) & 0b11111) =3D=3D 0) { + op =3D rv_op_th_rev; + } + break; + case 0b1000010: + if (((inst >> 20) & 0b11111) =3D=3D 0) { + op =3D rv_op_th_ff0; + } + break; + case 0b1000011: + if (((inst >> 20) & 0b11111) =3D=3D 0) { + op =3D rv_op_th_ff1; + } + break; + case 0b1000100: + case 0b1000101: op =3D rv_op_th_tst; break; + case 0b1001000: + if (((inst >> 20) & 0b11111) =3D=3D 0) { + op =3D rv_op_th_revw; + } + break; + case 0b0000000: + case 0b0000001: + case 0b0000010: + case 0b0000011: op =3D rv_op_th_addsl; break; + case 0b0000100: + case 0b0000101: op =3D rv_op_th_srri; break; + } + break; + case 2: op =3D rv_op_th_ext; break; + case 3: op =3D rv_op_th_extu; break; + case 4: + switch ((inst >> 27) & 0b11111) { + case 0: op =3D rv_op_th_lrb; break; + case 1: op =3D rv_op_th_lbib; break; + case 2: op =3D rv_op_th_lurb; break; + case 3: op =3D rv_op_th_lbia; break; + case 4: op =3D rv_op_th_lrh; break; + case 5: op =3D rv_op_th_lhib; break; + case 6: op =3D rv_op_th_lurh; break; + case 7: op =3D rv_op_th_lhia; break; + case 8: op =3D rv_op_th_lrw; break; + case 9: op =3D rv_op_th_lwib; break; + case 10: op =3D rv_op_th_lurw; break; + case 11: op =3D rv_op_th_lwia; break; + case 12: op =3D rv_op_th_lrd; break; + case 13: op =3D rv_op_th_ldib; break; + case 14: op =3D rv_op_th_lurd; break; + case 15: op =3D rv_op_th_ldia; break; + case 16: op =3D rv_op_th_lrbu; break; + case 17: op =3D rv_op_th_lbuib; break; + case 18: op =3D rv_op_th_lurbu; break; + case 19: op =3D rv_op_th_lbuia; break; + case 20: op =3D rv_op_th_lrhu; break; + case 21: op =3D rv_op_th_lhuib; break; + case 22: op =3D rv_op_th_lurhu; break; + case 23: op =3D rv_op_th_lhuia; break; + case 24: op =3D rv_op_th_lrwu; break; + case 25: op =3D rv_op_th_lwuib; break; + case 26: op =3D rv_op_th_lurwu; break; + case 27: op =3D rv_op_th_lwuia; break; + case 28: op =3D rv_op_th_lwd; break; + case 30: op =3D rv_op_th_lwud; break; + case 31: op =3D rv_op_th_ldd; break; + } + break; + case 5: + switch ((inst >> 27) & 0b11111) { + case 0: op =3D rv_op_th_srb; break; + case 1: op =3D rv_op_th_sbib; break; + case 2: op =3D rv_op_th_surb; break; + case 3: op =3D rv_op_th_sbia; break; + case 4: op =3D rv_op_th_srh; break; + case 5: op =3D rv_op_th_shib; break; + case 6: op =3D rv_op_th_surh; break; + case 7: op =3D rv_op_th_shia; break; + case 8: op =3D rv_op_th_srw; break; + case 9: op =3D rv_op_th_swib; break; + case 10: op =3D rv_op_th_surw; break; + case 11: op =3D rv_op_th_swia; break; + case 12: op =3D rv_op_th_srd; break; + case 13: op =3D rv_op_th_sdib; break; + case 14: op =3D rv_op_th_surd; break; + case 15: op =3D rv_op_th_sdia; break; + case 28: op =3D rv_op_th_swd; break; + case 31: op =3D rv_op_th_sdd; break; + } + break; + case 6: + switch ((inst >> 27) & 0b11111) { + case 8: op =3D rv_op_th_flrw; break; + case 10: op =3D rv_op_th_flurw; break; + case 12: op =3D rv_op_th_flrd; break; + case 14: op =3D rv_op_th_flurd; break; + } + break; + case 7: + switch ((inst >> 27) & 0b11111) { + case 8: op =3D rv_op_th_fsrw; break; + case 10: op =3D rv_op_th_fsurw; break; + case 12: op =3D rv_op_th_fsrd; break; + case 14: op =3D rv_op_th_fsurd; break; + } + break; + } + break; case 3: switch (((inst >> 12) & 0b111)) { case 0: op =3D rv_op_fence; break; @@ -3884,6 +4192,26 @@ static uint32_t operand_vm(rv_inst inst) return (inst << 38) >> 63; } =20 +static uint32_t operand_imm6(rv_inst inst) +{ + return (inst << 38) >> 60; +} + +static uint32_t operand_imm2(rv_inst inst) +{ + return (inst << 37) >> 62; +} + +static uint32_t operand_immh(rv_inst inst) +{ + return (inst << 32) >> 58; +} + +static uint32_t operand_imml(rv_inst inst) +{ + return (inst << 38) >> 58; +} + /* decode operands */ =20 static void decode_inst_operands(rv_decode *dec, rv_isa isa) @@ -4200,6 +4528,38 @@ static void decode_inst_operands(rv_decode *dec, rv_= isa isa) dec->imm =3D operand_vimm(inst); dec->vzimm =3D operand_vzimm10(inst); break; + case rv_codec_r2_imm5: + dec->rd =3D operand_rd(inst); + dec->rs1 =3D operand_rs1(inst); + dec->imm =3D operand_rs2(inst); + break; + case rv_codec_r2: + dec->rd =3D operand_rd(inst); + dec->rs1 =3D operand_rs1(inst); + break; + case rv_codec_r2_imm6: + dec->rd =3D operand_rd(inst); + dec->rs1 =3D operand_rs1(inst); + dec->imm =3D operand_imm6(inst); + break; + case rv_codec_r_imm2: + dec->rd =3D operand_rd(inst); + dec->rs1 =3D operand_rs1(inst); + dec->rs2 =3D operand_rs2(inst); + dec->imm =3D operand_imm2(inst); + break; + case rv_codec_r2_immhl: + dec->rd =3D operand_rd(inst); + dec->rs1 =3D operand_rs1(inst); + dec->imm =3D operand_immh(inst); + dec->imm1 =3D operand_imml(inst); + break; + case rv_codec_r2_imm2_imm5: + dec->rd =3D operand_rd(inst); + dec->rs1 =3D operand_rs1(inst); + dec->imm =3D sextract32(operand_rs2(inst), 0, 5); + dec->imm1 =3D operand_imm2(inst); + break; }; } =20 @@ -4396,6 +4756,10 @@ static void format_inst(char *buf, size_t buflen, si= ze_t tab, rv_decode *dec) snprintf(tmp, sizeof(tmp), "%d", dec->imm); append(buf, tmp, buflen); break; + case 'j': + snprintf(tmp, sizeof(tmp), "%d", dec->imm1); + append(buf, tmp, buflen); + break; case 'u': snprintf(tmp, sizeof(tmp), "%u", ((uint32_t)dec->imm & 0b11111= )); append(buf, tmp, buflen); --=20 2.39.2