[v1] riscv-to-apply queue

[PULL 0/2] riscv-to-apply queue

Alistair Francis posted 2 patches 1 year, 1 month ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20230314063812.30450-1-alistair.francis@opensource.wdc.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>

There is a newer version of this series

disas/riscv.c | 27 ++++++++++++++-------------
1 file changed, 14 insertions(+), 13 deletions(-)

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[PULL 0/2] riscv-to-apply queue

Posted by Alistair Francis 1 year, 1 month ago

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 284c52eec2d0a1b9c47f06c3eee46762c5fc0915:

  Merge tag 'win-socket-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging (2023-03-13 13:44:17 +0000)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230314

for you to fetch changes up to 0d581506de803204c5a321100afa270573382932:

  Fix incorrect register name in disassembler for fmv,fabs,fneg instructions (2023-03-14 16:36:43 +1000)

----------------------------------------------------------------
Seventh RISC-V PR for 8.0

* Fix slli_uw decoding
* Fix incorrect register name in disassembler for fmv,fabs,fneg instructions

----------------------------------------------------------------
Ivan Klokov (1):
      disas/riscv: Fix slli_uw decoding

Mikhail Tyutin (1):
      Fix incorrect register name in disassembler for fmv,fabs,fneg instructions

 disas/riscv.c | 27 ++++++++++++++-------------
 1 file changed, 14 insertions(+), 13 deletions(-)

Re: [PULL 0/2] riscv-to-apply queue

Posted by Peter Maydell 1 year, 1 month ago

On Tue, 14 Mar 2023 at 06:39, Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The following changes since commit 284c52eec2d0a1b9c47f06c3eee46762c5fc0915:
>
>   Merge tag 'win-socket-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging (2023-03-13 13:44:17 +0000)
>
> are available in the Git repository at:
>
>   https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230314
>
> for you to fetch changes up to 0d581506de803204c5a321100afa270573382932:
>
>   Fix incorrect register name in disassembler for fmv,fabs,fneg instructions (2023-03-14 16:36:43 +1000)
>
> ----------------------------------------------------------------
> Seventh RISC-V PR for 8.0
>
> * Fix slli_uw decoding
> * Fix incorrect register name in disassembler for fmv,fabs,fneg instructions
>
> ----------------------------------------------------------------


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0
for any user-visible changes.

-- PMM