From nobody Fri May 17 07:56:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678678853626213.15085467291965; Sun, 12 Mar 2023 20:40:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pbZ2n-0004k2-Nk; Sun, 12 Mar 2023 23:40:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pbZ2j-0004jV-JY; Sun, 12 Mar 2023 23:40:13 -0400 Received: from azure-sdnproxy.icoremail.net ([20.228.234.168]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pbZ2f-0002Qa-Be; Sun, 12 Mar 2023 23:40:13 -0400 Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-7 (Coremail) with SMTP id AQAAfwCHTZLRmg5kIDsTCg--.11017S2; Mon, 13 Mar 2023 11:38:57 +0800 (CST) Received: from localhost (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwDHCLf+mg5kEK4CAA--.938S2; Mon, 13 Mar 2023 11:39:42 +0800 (CST) From: Chen Baozi To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v4] target/arm: Add Neoverse-N1 registers Date: Mon, 13 Mar 2023 11:39:36 +0800 Message-Id: <20230313033936.585669-1-chenbaozi@phytium.com.cn> X-Mailer: git-send-email 2.37.3 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAfwDHCLf+mg5kEK4CAA--.938S2 X-CM-SenderInfo: hfkh0updr2xqxsk13x1xpou0fpof0/1tbiAQAREWQOJWUC5gACsN Authentication-Results: hzbj-icmmx-7; spf=neutral smtp.mail=chenbaozi@ phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvJXoWxWF17uF4UKw43JrykCw4Durg_yoWrur4kpF nrAr15WFyjqFsxJF4xC343Ca95A3WFgr4jkrZFgryI9F13XrW5KFyqq34YgF98GaykJ34F ka1jqryfuw17ZrUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj DUYxn0WfASr-VFAU7a7-sFnT9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUU UUUUU Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=20.228.234.168; envelope-from=chenbaozi@phytium.com.cn; helo=azure-sdnproxy.icoremail.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1678678855884100001 Content-Type: text/plain; charset="utf-8" Add implementation defined registers for neoverse-n1 which would be accessed by TF-A. Since there is no DSU in Qemu, CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition. Signed-off-by: Chen Baozi Reviewed-by: Peter Maydell Tested-by: Marcin Juszkiewicz --- target/arm/cpu64.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4066950da1..0fb07cc7b6 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "cpu.h" +#include "cpregs.h" #include "qemu/module.h" #include "sysemu/kvm.h" #include "sysemu/hvf.h" @@ -1027,6 +1028,72 @@ static void aarch64_a64fx_initfn(Object *obj) /* TODO: Add A64FX specific HPC extension registers */ } =20 +static const ARMCPRegInfo neoverse_n1_cp_reginfo[] =3D { + { .name =3D "ATCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 7, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "ATCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 15, .crm =3D 7, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "ATCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 7, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "ATCR_EL12", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 5, .crn =3D 15, .crm =3D 7, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "AVTCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 15, .crm =3D 7, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR2_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR3_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + /* + * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU + * (and in particular its system registers). + */ + { .name =3D "CPUCFR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 4 }, + { .name =3D "CPUECTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 4, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0x961563= 010 }, + { .name =3D "CPUPCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 8, .opc2 =3D 1, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPMR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 8, .opc2 =3D 3, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPOR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 8, .opc2 =3D 2, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPSELR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 8, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPWRCTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 2, .opc2 =3D 7, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "ERXPFGCDN_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 2, .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "ERXPFGCTL_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "ERXPFGF_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, +}; + +static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) +{ + define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); +} + static void aarch64_neoverse_n1_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -1094,6 +1161,8 @@ static void aarch64_neoverse_n1_initfn(Object *obj) =20 /* From D5.1 AArch64 PMU register summary */ cpu->isar.reset_pmcr_el0 =3D 0x410c3000; + + define_neoverse_n1_cp_reginfo(cpu); } =20 static void aarch64_host_initfn(Object *obj) --=20 2.37.3