This introduces new properties to allow the user to set the satp mode,
see patch 3 for full syntax. In addition, it prevents cpus to boot in a
satp mode they do not support (see patch 4).

base-commit: commit c61d1a066cb6 ("Merge tag 'for-upstream' of
https://gitlab.com/bonzini/qemu into staging")

v11:
- rebase on top of master
- Added RB/AB from Frank and Alistair
- Use VM_1_10_XX directly instead of satp_mode_from_str, from Frank
- Set satp mode max for thead c906 to sv39

v10:
- Fix user mode build by surrounding satp handling with #ifndef
  CONFIG_USER_ONLY, Frank
- Fix AB/RB from Frank and Alistair

v9:
- Move valid_vm[i] up, Andrew
- Fixed expansion of the bitmap map, Bin
- Rename set_satp_mode_default into set_satp_mode_default_map, Bin
- Remove outer parenthesis and alignment, Bin
- Fix qemu32 build failure, Bin
- Fixed a few typos, Bin
- Add RB from Andrew and Bin

v8:
- Remove useless !map check, Andrew
- Add RB from Andrew

v7:
- Expand map to contain all valid modes, Andrew
- Fix commit log for patch 3, Andrew
- Remove is_32_bit argument from set_satp_mode_default, Andrew
- Move and fixed comment, Andrew
- Fix satp_mode_map_max in riscv_cpu_satp_mode_finalize which was set
  too early, Alex
- Remove is_32_bit argument from set_satp_mode_max_supported, Andrew
- Use satp_mode directly instead of a string in
  set_satp_mode_max_supported, Andrew
- Swap the patch introducing supported bitmap and the patch that sets
  sv57 in the dt, Andrew
- Add various RB from Andrew and Alistair, thanks

v6:
- Remove the valid_vm check in validate_vm and add it to the finalize function
  so that map already contains the constraint, Alex
- Add forgotten mbare to satp_mode_from_str, Alex
- Move satp mode properties handling to riscv_cpu_satp_mode_finalize, Andrew
- Only add satp mode properties corresponding to the cpu, and then remove the
  check against valid_vm_1_10_32/64 in riscv_cpu_satp_mode_finalize,
  Andrew/Alistair/Alex
- Move mmu-type setting to its own patch, Andrew
- patch 5 is new and is a fix, Alex

v5:
- Simplify v4 implementation by leveraging valid_vm_1_10_32/64, as
  suggested by Andrew
- Split the v4 patch into 2 patches as suggested by Andrew
- Lot of other minor corrections, from Andrew
- Set the satp mode N by disabling the satp mode N + 1
- Add a helper to set satp mode from a string, as suggested by Frank

v4:
- Use custom boolean properties instead of OnOffAuto properties, based
  on ARMVQMap, as suggested by Andrew

v3:
- Free sv_name as pointed by Bin
- Replace satp-mode with boolean properties as suggested by Andrew
- Removed RB from Atish as the patch considerably changed

v2:
- Use error_setg + return as suggested by Alistair
- Add RB from Atish
- Fixed checkpatch issues missed in v1
- Replaced Ludovic email address with the rivos one

Alexandre Ghiti (5):
  riscv: Pass Object to register_cpu_props instead of DeviceState
  riscv: Change type of valid_vm_1_10_[32|64] to bool
  riscv: Allow user to set the satp mode
  riscv: Introduce satp mode hw capabilities
  riscv: Correctly set the device-tree entry 'mmu-type'

 hw/riscv/virt.c    |  19 +--
 target/riscv/cpu.c | 288 ++++++++++++++++++++++++++++++++++++++++++---
 target/riscv/cpu.h |  25 ++++
 target/riscv/csr.c |  29 +++--
 4 files changed, 323 insertions(+), 38 deletions(-)

-- 
2.37.2

On Fri, 03 Mar 2023 05:12:47 PST (-0800), alexghiti@rivosinc.com wrote:
> This introduces new properties to allow the user to set the satp mode,
> see patch 3 for full syntax. In addition, it prevents cpus to boot in a
> satp mode they do not support (see patch 4).
>
> base-commit: commit c61d1a066cb6 ("Merge tag 'for-upstream' of
> https://gitlab.com/bonzini/qemu into staging")

I have that, but I still got some merge conflicts.  I've put that here 
<https://github.com/palmer-dabbelt/qemu/tree/set-satp> for now, pending 
Daniel's response below.

>
> v11:
> - rebase on top of master
> - Added RB/AB from Frank and Alistair
> - Use VM_1_10_XX directly instead of satp_mode_from_str, from Frank
> - Set satp mode max for thead c906 to sv39

Daniel: It looks like the feedback on v10 included dropping the first 
patch
<https://lore.kernel.org/qemu-devel/66d80b94-5941-31f3-995f-e9666a91fbb7@ventanamicro.com/T/#macdb6c5232bd8c082966107d7b44aaaec9b29ad6>.
Sorry if I'm just misunderstanding, but it looks to me like that patch 
is still useful and the v11 doesn't even build without it.

>
> v10:
> - Fix user mode build by surrounding satp handling with #ifndef
>   CONFIG_USER_ONLY, Frank
> - Fix AB/RB from Frank and Alistair
>
> v9:
> - Move valid_vm[i] up, Andrew
> - Fixed expansion of the bitmap map, Bin
> - Rename set_satp_mode_default into set_satp_mode_default_map, Bin
> - Remove outer parenthesis and alignment, Bin
> - Fix qemu32 build failure, Bin
> - Fixed a few typos, Bin
> - Add RB from Andrew and Bin
>
> v8:
> - Remove useless !map check, Andrew
> - Add RB from Andrew
>
> v7:
> - Expand map to contain all valid modes, Andrew
> - Fix commit log for patch 3, Andrew
> - Remove is_32_bit argument from set_satp_mode_default, Andrew
> - Move and fixed comment, Andrew
> - Fix satp_mode_map_max in riscv_cpu_satp_mode_finalize which was set
>   too early, Alex
> - Remove is_32_bit argument from set_satp_mode_max_supported, Andrew
> - Use satp_mode directly instead of a string in
>   set_satp_mode_max_supported, Andrew
> - Swap the patch introducing supported bitmap and the patch that sets
>   sv57 in the dt, Andrew
> - Add various RB from Andrew and Alistair, thanks
>
> v6:
> - Remove the valid_vm check in validate_vm and add it to the finalize function
>   so that map already contains the constraint, Alex
> - Add forgotten mbare to satp_mode_from_str, Alex
> - Move satp mode properties handling to riscv_cpu_satp_mode_finalize, Andrew
> - Only add satp mode properties corresponding to the cpu, and then remove the
>   check against valid_vm_1_10_32/64 in riscv_cpu_satp_mode_finalize,
>   Andrew/Alistair/Alex
> - Move mmu-type setting to its own patch, Andrew
> - patch 5 is new and is a fix, Alex
>
> v5:
> - Simplify v4 implementation by leveraging valid_vm_1_10_32/64, as
>   suggested by Andrew
> - Split the v4 patch into 2 patches as suggested by Andrew
> - Lot of other minor corrections, from Andrew
> - Set the satp mode N by disabling the satp mode N + 1
> - Add a helper to set satp mode from a string, as suggested by Frank
>
> v4:
> - Use custom boolean properties instead of OnOffAuto properties, based
>   on ARMVQMap, as suggested by Andrew
>
> v3:
> - Free sv_name as pointed by Bin
> - Replace satp-mode with boolean properties as suggested by Andrew
> - Removed RB from Atish as the patch considerably changed
>
> v2:
> - Use error_setg + return as suggested by Alistair
> - Add RB from Atish
> - Fixed checkpatch issues missed in v1
> - Replaced Ludovic email address with the rivos one
>
> Alexandre Ghiti (5):
>   riscv: Pass Object to register_cpu_props instead of DeviceState
>   riscv: Change type of valid_vm_1_10_[32|64] to bool
>   riscv: Allow user to set the satp mode
>   riscv: Introduce satp mode hw capabilities
>   riscv: Correctly set the device-tree entry 'mmu-type'
>
>  hw/riscv/virt.c    |  19 +--
>  target/riscv/cpu.c | 288 ++++++++++++++++++++++++++++++++++++++++++---
>  target/riscv/cpu.h |  25 ++++
>  target/riscv/csr.c |  29 +++--
>  4 files changed, 323 insertions(+), 38 deletions(-)

On 3/5/23 20:34, Palmer Dabbelt wrote:
> On Fri, 03 Mar 2023 05:12:47 PST (-0800), alexghiti@rivosinc.com wrote:
>> This introduces new properties to allow the user to set the satp mode,
>> see patch 3 for full syntax. In addition, it prevents cpus to boot in a
>> satp mode they do not support (see patch 4).
>>
>> base-commit: commit c61d1a066cb6 ("Merge tag 'for-upstream' of
>> https://gitlab.com/bonzini/qemu into staging")
> 
> I have that, but I still got some merge conflicts.  I've put that here <https://github.com/palmer-dabbelt/qemu/tree/set-satp> for now, pending Daniel's response below.
> 
>>
>> v11:
>> - rebase on top of master
>> - Added RB/AB from Frank and Alistair
>> - Use VM_1_10_XX directly instead of satp_mode_from_str, from Frank
>> - Set satp mode max for thead c906 to sv39
> 
> Daniel: It looks like the feedback on v10 included dropping the first patch
> <https://lore.kernel.org/qemu-devel/66d80b94-5941-31f3-995f-e9666a91fbb7@ventanamicro.com/T/#macdb6c5232bd8c082966107d7b44aaaec9b29ad6>.
> Sorry if I'm just misunderstanding, but it looks to me like that patch is still useful and the v11 doesn't even build without it.


I believe I mentioned that patch 1 was obsolete in the context of version 10, where
I think I also mentioned that a rebase would be good.

Alexandre rebased it and, from what I can see, patch 1 looks good to go.


Thanks,

Daniel

> 
>>
>> v10:
>> - Fix user mode build by surrounding satp handling with #ifndef
>>   CONFIG_USER_ONLY, Frank
>> - Fix AB/RB from Frank and Alistair
>>
>> v9:
>> - Move valid_vm[i] up, Andrew
>> - Fixed expansion of the bitmap map, Bin
>> - Rename set_satp_mode_default into set_satp_mode_default_map, Bin
>> - Remove outer parenthesis and alignment, Bin
>> - Fix qemu32 build failure, Bin
>> - Fixed a few typos, Bin
>> - Add RB from Andrew and Bin
>>
>> v8:
>> - Remove useless !map check, Andrew
>> - Add RB from Andrew
>>
>> v7:
>> - Expand map to contain all valid modes, Andrew
>> - Fix commit log for patch 3, Andrew
>> - Remove is_32_bit argument from set_satp_mode_default, Andrew
>> - Move and fixed comment, Andrew
>> - Fix satp_mode_map_max in riscv_cpu_satp_mode_finalize which was set
>>   too early, Alex
>> - Remove is_32_bit argument from set_satp_mode_max_supported, Andrew
>> - Use satp_mode directly instead of a string in
>>   set_satp_mode_max_supported, Andrew
>> - Swap the patch introducing supported bitmap and the patch that sets
>>   sv57 in the dt, Andrew
>> - Add various RB from Andrew and Alistair, thanks
>>
>> v6:
>> - Remove the valid_vm check in validate_vm and add it to the finalize function
>>   so that map already contains the constraint, Alex
>> - Add forgotten mbare to satp_mode_from_str, Alex
>> - Move satp mode properties handling to riscv_cpu_satp_mode_finalize, Andrew
>> - Only add satp mode properties corresponding to the cpu, and then remove the
>>   check against valid_vm_1_10_32/64 in riscv_cpu_satp_mode_finalize,
>>   Andrew/Alistair/Alex
>> - Move mmu-type setting to its own patch, Andrew
>> - patch 5 is new and is a fix, Alex
>>
>> v5:
>> - Simplify v4 implementation by leveraging valid_vm_1_10_32/64, as
>>   suggested by Andrew
>> - Split the v4 patch into 2 patches as suggested by Andrew
>> - Lot of other minor corrections, from Andrew
>> - Set the satp mode N by disabling the satp mode N + 1
>> - Add a helper to set satp mode from a string, as suggested by Frank
>>
>> v4:
>> - Use custom boolean properties instead of OnOffAuto properties, based
>>   on ARMVQMap, as suggested by Andrew
>>
>> v3:
>> - Free sv_name as pointed by Bin
>> - Replace satp-mode with boolean properties as suggested by Andrew
>> - Removed RB from Atish as the patch considerably changed
>>
>> v2:
>> - Use error_setg + return as suggested by Alistair
>> - Add RB from Atish
>> - Fixed checkpatch issues missed in v1
>> - Replaced Ludovic email address with the rivos one
>>
>> Alexandre Ghiti (5):
>>   riscv: Pass Object to register_cpu_props instead of DeviceState
>>   riscv: Change type of valid_vm_1_10_[32|64] to bool
>>   riscv: Allow user to set the satp mode
>>   riscv: Introduce satp mode hw capabilities
>>   riscv: Correctly set the device-tree entry 'mmu-type'
>>
>>  hw/riscv/virt.c    |  19 +--
>>  target/riscv/cpu.c | 288 ++++++++++++++++++++++++++++++++++++++++++---
>>  target/riscv/cpu.h |  25 ++++
>>  target/riscv/csr.c |  29 +++--
>>  4 files changed, 323 insertions(+), 38 deletions(-)

On Mon, 06 Mar 2023 09:50:49 PST (-0800), dbarboza@ventanamicro.com wrote:
>
>
> On 3/5/23 20:34, Palmer Dabbelt wrote:
>> On Fri, 03 Mar 2023 05:12:47 PST (-0800), alexghiti@rivosinc.com wrote:
>>> This introduces new properties to allow the user to set the satp mode,
>>> see patch 3 for full syntax. In addition, it prevents cpus to boot in a
>>> satp mode they do not support (see patch 4).
>>>
>>> base-commit: commit c61d1a066cb6 ("Merge tag 'for-upstream' of
>>> https://gitlab.com/bonzini/qemu into staging")
>>
>> I have that, but I still got some merge conflicts.  I've put that here <https://github.com/palmer-dabbelt/qemu/tree/set-satp> for now, pending Daniel's response below.
>>
>>>
>>> v11:
>>> - rebase on top of master
>>> - Added RB/AB from Frank and Alistair
>>> - Use VM_1_10_XX directly instead of satp_mode_from_str, from Frank
>>> - Set satp mode max for thead c906 to sv39
>>
>> Daniel: It looks like the feedback on v10 included dropping the first patch
>> <https://lore.kernel.org/qemu-devel/66d80b94-5941-31f3-995f-e9666a91fbb7@ventanamicro.com/T/#macdb6c5232bd8c082966107d7b44aaaec9b29ad6>.
>> Sorry if I'm just misunderstanding, but it looks to me like that patch is still useful and the v11 doesn't even build without it.
>
>
> I believe I mentioned that patch 1 was obsolete in the context of version 10, where
> I think I also mentioned that a rebase would be good.
>
> Alexandre rebased it and, from what I can see, patch 1 looks good to go.

Sounds good, thanks.

>
>
> Thanks,
>
> Daniel
>
>>
>>>
>>> v10:
>>> - Fix user mode build by surrounding satp handling with #ifndef
>>>   CONFIG_USER_ONLY, Frank
>>> - Fix AB/RB from Frank and Alistair
>>>
>>> v9:
>>> - Move valid_vm[i] up, Andrew
>>> - Fixed expansion of the bitmap map, Bin
>>> - Rename set_satp_mode_default into set_satp_mode_default_map, Bin
>>> - Remove outer parenthesis and alignment, Bin
>>> - Fix qemu32 build failure, Bin
>>> - Fixed a few typos, Bin
>>> - Add RB from Andrew and Bin
>>>
>>> v8:
>>> - Remove useless !map check, Andrew
>>> - Add RB from Andrew
>>>
>>> v7:
>>> - Expand map to contain all valid modes, Andrew
>>> - Fix commit log for patch 3, Andrew
>>> - Remove is_32_bit argument from set_satp_mode_default, Andrew
>>> - Move and fixed comment, Andrew
>>> - Fix satp_mode_map_max in riscv_cpu_satp_mode_finalize which was set
>>>   too early, Alex
>>> - Remove is_32_bit argument from set_satp_mode_max_supported, Andrew
>>> - Use satp_mode directly instead of a string in
>>>   set_satp_mode_max_supported, Andrew
>>> - Swap the patch introducing supported bitmap and the patch that sets
>>>   sv57 in the dt, Andrew
>>> - Add various RB from Andrew and Alistair, thanks
>>>
>>> v6:
>>> - Remove the valid_vm check in validate_vm and add it to the finalize function
>>>   so that map already contains the constraint, Alex
>>> - Add forgotten mbare to satp_mode_from_str, Alex
>>> - Move satp mode properties handling to riscv_cpu_satp_mode_finalize, Andrew
>>> - Only add satp mode properties corresponding to the cpu, and then remove the
>>>   check against valid_vm_1_10_32/64 in riscv_cpu_satp_mode_finalize,
>>>   Andrew/Alistair/Alex
>>> - Move mmu-type setting to its own patch, Andrew
>>> - patch 5 is new and is a fix, Alex
>>>
>>> v5:
>>> - Simplify v4 implementation by leveraging valid_vm_1_10_32/64, as
>>>   suggested by Andrew
>>> - Split the v4 patch into 2 patches as suggested by Andrew
>>> - Lot of other minor corrections, from Andrew
>>> - Set the satp mode N by disabling the satp mode N + 1
>>> - Add a helper to set satp mode from a string, as suggested by Frank
>>>
>>> v4:
>>> - Use custom boolean properties instead of OnOffAuto properties, based
>>>   on ARMVQMap, as suggested by Andrew
>>>
>>> v3:
>>> - Free sv_name as pointed by Bin
>>> - Replace satp-mode with boolean properties as suggested by Andrew
>>> - Removed RB from Atish as the patch considerably changed
>>>
>>> v2:
>>> - Use error_setg + return as suggested by Alistair
>>> - Add RB from Atish
>>> - Fixed checkpatch issues missed in v1
>>> - Replaced Ludovic email address with the rivos one
>>>
>>> Alexandre Ghiti (5):
>>>   riscv: Pass Object to register_cpu_props instead of DeviceState
>>>   riscv: Change type of valid_vm_1_10_[32|64] to bool
>>>   riscv: Allow user to set the satp mode
>>>   riscv: Introduce satp mode hw capabilities
>>>   riscv: Correctly set the device-tree entry 'mmu-type'
>>>
>>>  hw/riscv/virt.c    |  19 +--
>>>  target/riscv/cpu.c | 288 ++++++++++++++++++++++++++++++++++++++++++---
>>>  target/riscv/cpu.h |  25 ++++
>>>  target/riscv/csr.c |  29 +++--
>>>  4 files changed, 323 insertions(+), 38 deletions(-)

Hi Palmer,

On Mon, Mar 6, 2023 at 12:34 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Fri, 03 Mar 2023 05:12:47 PST (-0800), alexghiti@rivosinc.com wrote:
> > This introduces new properties to allow the user to set the satp mode,
> > see patch 3 for full syntax. In addition, it prevents cpus to boot in a
> > satp mode they do not support (see patch 4).
> >
> > base-commit: commit c61d1a066cb6 ("Merge tag 'for-upstream' of
> > https://gitlab.com/bonzini/qemu into staging")
>
> I have that, but I still got some merge conflicts.  I've put that here
> <https://github.com/palmer-dabbelt/qemu/tree/set-satp> for now, pending
> Daniel's response below.

Weird, I have just tried again and it applied cleanly on the
base-commit I mentioned, I tried to cherry-pick a few patches, even
commit d4ea71170432 ("target/riscv: introduce riscv_cpu_cfg()") does
not break the merge.

Anyway, FWIW I checked the patches on the set-satp branch again, and
your merge seems ok.

>
> >
> > v11:
> > - rebase on top of master
> > - Added RB/AB from Frank and Alistair
> > - Use VM_1_10_XX directly instead of satp_mode_from_str, from Frank
> > - Set satp mode max for thead c906 to sv39
>
> Daniel: It looks like the feedback on v10 included dropping the first
> patch
> <https://lore.kernel.org/qemu-devel/66d80b94-5941-31f3-995f-e9666a91fbb7@ventanamicro.com/T/#macdb6c5232bd8c082966107d7b44aaaec9b29ad6>.
> Sorry if I'm just misunderstanding, but it looks to me like that patch
> is still useful and the v11 doesn't even build without it.

No, the first commit is a preparatory commit for the series, it is required.


>
> >
> > v10:
> > - Fix user mode build by surrounding satp handling with #ifndef
> >   CONFIG_USER_ONLY, Frank
> > - Fix AB/RB from Frank and Alistair
> >
> > v9:
> > - Move valid_vm[i] up, Andrew
> > - Fixed expansion of the bitmap map, Bin
> > - Rename set_satp_mode_default into set_satp_mode_default_map, Bin
> > - Remove outer parenthesis and alignment, Bin
> > - Fix qemu32 build failure, Bin
> > - Fixed a few typos, Bin
> > - Add RB from Andrew and Bin
> >
> > v8:
> > - Remove useless !map check, Andrew
> > - Add RB from Andrew
> >
> > v7:
> > - Expand map to contain all valid modes, Andrew
> > - Fix commit log for patch 3, Andrew
> > - Remove is_32_bit argument from set_satp_mode_default, Andrew
> > - Move and fixed comment, Andrew
> > - Fix satp_mode_map_max in riscv_cpu_satp_mode_finalize which was set
> >   too early, Alex
> > - Remove is_32_bit argument from set_satp_mode_max_supported, Andrew
> > - Use satp_mode directly instead of a string in
> >   set_satp_mode_max_supported, Andrew
> > - Swap the patch introducing supported bitmap and the patch that sets
> >   sv57 in the dt, Andrew
> > - Add various RB from Andrew and Alistair, thanks
> >
> > v6:
> > - Remove the valid_vm check in validate_vm and add it to the finalize function
> >   so that map already contains the constraint, Alex
> > - Add forgotten mbare to satp_mode_from_str, Alex
> > - Move satp mode properties handling to riscv_cpu_satp_mode_finalize, Andrew
> > - Only add satp mode properties corresponding to the cpu, and then remove the
> >   check against valid_vm_1_10_32/64 in riscv_cpu_satp_mode_finalize,
> >   Andrew/Alistair/Alex
> > - Move mmu-type setting to its own patch, Andrew
> > - patch 5 is new and is a fix, Alex
> >
> > v5:
> > - Simplify v4 implementation by leveraging valid_vm_1_10_32/64, as
> >   suggested by Andrew
> > - Split the v4 patch into 2 patches as suggested by Andrew
> > - Lot of other minor corrections, from Andrew
> > - Set the satp mode N by disabling the satp mode N + 1
> > - Add a helper to set satp mode from a string, as suggested by Frank
> >
> > v4:
> > - Use custom boolean properties instead of OnOffAuto properties, based
> >   on ARMVQMap, as suggested by Andrew
> >
> > v3:
> > - Free sv_name as pointed by Bin
> > - Replace satp-mode with boolean properties as suggested by Andrew
> > - Removed RB from Atish as the patch considerably changed
> >
> > v2:
> > - Use error_setg + return as suggested by Alistair
> > - Add RB from Atish
> > - Fixed checkpatch issues missed in v1
> > - Replaced Ludovic email address with the rivos one
> >
> > Alexandre Ghiti (5):
> >   riscv: Pass Object to register_cpu_props instead of DeviceState
> >   riscv: Change type of valid_vm_1_10_[32|64] to bool
> >   riscv: Allow user to set the satp mode
> >   riscv: Introduce satp mode hw capabilities
> >   riscv: Correctly set the device-tree entry 'mmu-type'
> >
> >  hw/riscv/virt.c    |  19 +--
> >  target/riscv/cpu.c | 288 ++++++++++++++++++++++++++++++++++++++++++---
> >  target/riscv/cpu.h |  25 ++++
> >  target/riscv/csr.c |  29 +++--
> >  4 files changed, 323 insertions(+), 38 deletions(-)

On Mon, 06 Mar 2023 00:33:20 PST (-0800), alexghiti@rivosinc.com wrote:
> Hi Palmer,
>
> On Mon, Mar 6, 2023 at 12:34 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>>
>> On Fri, 03 Mar 2023 05:12:47 PST (-0800), alexghiti@rivosinc.com wrote:
>> > This introduces new properties to allow the user to set the satp mode,
>> > see patch 3 for full syntax. In addition, it prevents cpus to boot in a
>> > satp mode they do not support (see patch 4).
>> >
>> > base-commit: commit c61d1a066cb6 ("Merge tag 'for-upstream' of
>> > https://gitlab.com/bonzini/qemu into staging")
>>
>> I have that, but I still got some merge conflicts.  I've put that here
>> <https://github.com/palmer-dabbelt/qemu/tree/set-satp> for now, pending
>> Daniel's response below.
>
> Weird, I have just tried again and it applied cleanly on the
> base-commit I mentioned, I tried to cherry-pick a few patches, even
> commit d4ea71170432 ("target/riscv: introduce riscv_cpu_cfg()") does
> not break the merge.

Weird, I'm just using b4 to pick up the patches from lore so not sure 
what's up.

> Anyway, FWIW I checked the patches on the set-satp branch again, and
> your merge seems ok.

OK, I picked those onto riscv-to-apply.next and everything looks fine on 
my end.

>
>>
>> >
>> > v11:
>> > - rebase on top of master
>> > - Added RB/AB from Frank and Alistair
>> > - Use VM_1_10_XX directly instead of satp_mode_from_str, from Frank
>> > - Set satp mode max for thead c906 to sv39
>>
>> Daniel: It looks like the feedback on v10 included dropping the first
>> patch
>> <https://lore.kernel.org/qemu-devel/66d80b94-5941-31f3-995f-e9666a91fbb7@ventanamicro.com/T/#macdb6c5232bd8c082966107d7b44aaaec9b29ad6>.
>> Sorry if I'm just misunderstanding, but it looks to me like that patch
>> is still useful and the v11 doesn't even build without it.
>
> No, the first commit is a preparatory commit for the series, it is required.

Ya, that's what I'm seeing too.  It's in the queue before the rest.

Thanks!

>
>
>>
>> >
>> > v10:
>> > - Fix user mode build by surrounding satp handling with #ifndef
>> >   CONFIG_USER_ONLY, Frank
>> > - Fix AB/RB from Frank and Alistair
>> >
>> > v9:
>> > - Move valid_vm[i] up, Andrew
>> > - Fixed expansion of the bitmap map, Bin
>> > - Rename set_satp_mode_default into set_satp_mode_default_map, Bin
>> > - Remove outer parenthesis and alignment, Bin
>> > - Fix qemu32 build failure, Bin
>> > - Fixed a few typos, Bin
>> > - Add RB from Andrew and Bin
>> >
>> > v8:
>> > - Remove useless !map check, Andrew
>> > - Add RB from Andrew
>> >
>> > v7:
>> > - Expand map to contain all valid modes, Andrew
>> > - Fix commit log for patch 3, Andrew
>> > - Remove is_32_bit argument from set_satp_mode_default, Andrew
>> > - Move and fixed comment, Andrew
>> > - Fix satp_mode_map_max in riscv_cpu_satp_mode_finalize which was set
>> >   too early, Alex
>> > - Remove is_32_bit argument from set_satp_mode_max_supported, Andrew
>> > - Use satp_mode directly instead of a string in
>> >   set_satp_mode_max_supported, Andrew
>> > - Swap the patch introducing supported bitmap and the patch that sets
>> >   sv57 in the dt, Andrew
>> > - Add various RB from Andrew and Alistair, thanks
>> >
>> > v6:
>> > - Remove the valid_vm check in validate_vm and add it to the finalize function
>> >   so that map already contains the constraint, Alex
>> > - Add forgotten mbare to satp_mode_from_str, Alex
>> > - Move satp mode properties handling to riscv_cpu_satp_mode_finalize, Andrew
>> > - Only add satp mode properties corresponding to the cpu, and then remove the
>> >   check against valid_vm_1_10_32/64 in riscv_cpu_satp_mode_finalize,
>> >   Andrew/Alistair/Alex
>> > - Move mmu-type setting to its own patch, Andrew
>> > - patch 5 is new and is a fix, Alex
>> >
>> > v5:
>> > - Simplify v4 implementation by leveraging valid_vm_1_10_32/64, as
>> >   suggested by Andrew
>> > - Split the v4 patch into 2 patches as suggested by Andrew
>> > - Lot of other minor corrections, from Andrew
>> > - Set the satp mode N by disabling the satp mode N + 1
>> > - Add a helper to set satp mode from a string, as suggested by Frank
>> >
>> > v4:
>> > - Use custom boolean properties instead of OnOffAuto properties, based
>> >   on ARMVQMap, as suggested by Andrew
>> >
>> > v3:
>> > - Free sv_name as pointed by Bin
>> > - Replace satp-mode with boolean properties as suggested by Andrew
>> > - Removed RB from Atish as the patch considerably changed
>> >
>> > v2:
>> > - Use error_setg + return as suggested by Alistair
>> > - Add RB from Atish
>> > - Fixed checkpatch issues missed in v1
>> > - Replaced Ludovic email address with the rivos one
>> >
>> > Alexandre Ghiti (5):
>> >   riscv: Pass Object to register_cpu_props instead of DeviceState
>> >   riscv: Change type of valid_vm_1_10_[32|64] to bool
>> >   riscv: Allow user to set the satp mode
>> >   riscv: Introduce satp mode hw capabilities
>> >   riscv: Correctly set the device-tree entry 'mmu-type'
>> >
>> >  hw/riscv/virt.c    |  19 +--
>> >  target/riscv/cpu.c | 288 ++++++++++++++++++++++++++++++++++++++++++---
>> >  target/riscv/cpu.h |  25 ++++
>> >  target/riscv/csr.c |  29 +++--
>> >  4 files changed, 323 insertions(+), 38 deletions(-)