From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677475756; cv=none; d=zohomail.com; s=zohoarc; b=P1eb2rDOJTVbvwX+xN5rHfGVSQm5zTOY7WqRXHJs8xjqveC0PqwG95oNLsCHgMkwX+dC/+jAdFiOa8jKSYulxOA4gsv/FqROvPSwZrFNZKLeDH3rxQTVbKtEtwpy4NyX+qnJLjFpvik0YpWK/z/6AfWc9zk4qL+0V4Vfllt75DU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677475756; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=D7Dr5dVd5BMP8VbVASryumiENZXah1Y2zUeyDZafQVk=; b=TQnGcr63bEzvrSdaUuUCkd/Z5HXism+9LKlcej0OjiApLBHeAJcZbCA950JUlgroteUNmpVNGUM3v6G5OiRgE3wJTmrLZY56c9hfYAOwHp2vaabwli7sdIg/PQ2kwRntH6qQEEdI+GCMAcJ23X+LgkWbjE13WeVseONW0tyBM44= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677475756351205.86580321885697; Sun, 26 Feb 2023 21:29:16 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW1A-0006ob-GA; Mon, 27 Feb 2023 00:25:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW0l-0006dH-Q0 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:25:20 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW0h-00079a-6q for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:25:18 -0500 Received: by mail-pj1-x1031.google.com with SMTP id gi3-20020a17090b110300b0023762f642dcso5005610pjb.4 for ; Sun, 26 Feb 2023 21:25:14 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.25.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:25:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D7Dr5dVd5BMP8VbVASryumiENZXah1Y2zUeyDZafQVk=; b=AIwUmVtqm3EQWqE0nuArRl98xM3APLghad3m8L3hE5rrtJYNzonJWtFFfNEnAuTvII SiyuAV6LWAhVizYX3oMLoYAbskNCs89x5af4UVaHqUwak0O82e4trCLH3DjPiEN5PvRX AK0uk9b6l8dqnTruUVm+ZXYCDxNxq+xpSMzghVDCndGXp/lTV6KQe+aVkNHrMBl1eOS9 3T578Xi0b1XjaM2gRLrCUkv7B3cvQ1ooC7XhazzyLKzVh1u+0PGq5XafZ/uiiFOaDOe2 kGy7jDAhVloSh6Wi9pwjbpU6D/XDAb/dHzlU1A7kz+b178ZeMAxSq22Aox9oaYbKa41w GFPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D7Dr5dVd5BMP8VbVASryumiENZXah1Y2zUeyDZafQVk=; b=D+7Ns/XwTWlWh+QEePAIA+MOkO8gKBLle9Dy1277Rwo9QmN1ihjDP8Yb4kWQriZmVa ujdvAnUCmSfYZEbHP2NfWklsmbozuXLXMmtDgH5IeCOlK/wRdGeFSiBxyKtnEuY0QGhE h7XZentyuXaKyGhj0PqIVE/am5Ahgis2y8icbbLgYS3UXZhawAuqXTPbxZ9oZzVheZPf tjKVeqgvVOsb2wZ8F9YeGaKxN1CBotxHYckqSvQ4fg7wmXmgQGYCCwdYXwrjJ4JHVThw ND849hXwftL32Fhd+2i51svmYuDCN3FQ6Feg1CbRKYJbGYv28jfL8h1Xn1D0Cxypn4sr gH4w== X-Gm-Message-State: AO0yUKVavaNn2tzpy2lkcDulCQ8YCoUbXe0koR0VcU+dWwfCZ+qj8GqU 1x7lOXJN0RY/MF2vA7dzcNwIaS5KpVkXOjZ0clo= X-Google-Smtp-Source: AK7set/fMeI0SqXaIxDJlJv6jADDS28zH5sRrUoa33mqbv05qgxGhKi3UDGWt4jd1g+vRaHyRPswAQ== X-Received: by 2002:a17:902:f693:b0:19d:1e33:a60d with SMTP id l19-20020a170902f69300b0019d1e33a60dmr1212656plg.25.1677475512964; Sun, 26 Feb 2023 21:25:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 01/76] tcg: Remove tcg_check_temp_count, tcg_clear_temp_count Date: Sun, 26 Feb 2023 19:23:50 -1000 Message-Id: <20230227052505.352889-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475756706100001 Content-Type: text/plain; charset="utf-8" Since all temps allocated by guest front-ends are now TEMP_TB, and we don't recycle TEMP_TB, there's no point in requiring that the front-ends free the temps at all. Begin by dropping the inner-most checks that all temps have been freed. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- include/tcg/tcg.h | 14 ----------- accel/tcg/translator.c | 12 ---------- tcg/tcg.c | 54 +++++++----------------------------------- 3 files changed, 8 insertions(+), 72 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 7e2b954dbc..e8f73115ec 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -567,7 +567,6 @@ struct TCGContext { #endif =20 #ifdef CONFIG_DEBUG_TCG - int temps_in_use; int goto_tb_issue_mask; const TCGOpcode *vecop_list; #endif @@ -958,19 +957,6 @@ static inline TCGv_ptr tcg_temp_new_ptr(void) return temp_tcgv_ptr(t); } =20 -#if defined(CONFIG_DEBUG_TCG) -/* If you call tcg_clear_temp_count() at the start of a section of - * code which is not supposed to leak any TCG temporaries, then - * calling tcg_check_temp_count() at the end of the section will - * return 1 if the section did in fact leak a temporary. - */ -void tcg_clear_temp_count(void); -int tcg_check_temp_count(void); -#else -#define tcg_clear_temp_count() do { } while (0) -#define tcg_check_temp_count() 0 -#endif - int64_t tcg_cpu_exec_time(void); void tcg_dump_info(GString *buf); void tcg_dump_op_count(GString *buf); diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 62e8f28025..88567a88d1 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -18,17 +18,8 @@ #include "exec/plugin-gen.h" #include "sysemu/replay.h" =20 -/* Pairs with tcg_clear_temp_count. - To be called by #TranslatorOps.{translate_insn,tb_stop} if - (1) the target is sufficiently clean to support reporting, - (2) as and when all temporaries are known to be consumed. - For most targets, (2) is at the end of translate_insn. */ void translator_loop_temp_check(DisasContextBase *db) { - if (tcg_check_temp_count()) { - qemu_log("warning: TCG temporary leaks before " - TARGET_FMT_lx "\n", db->pc_next); - } } =20 bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest) @@ -67,9 +58,6 @@ void translator_loop(CPUState *cpu, TranslationBlock *tb,= int *max_insns, ops->init_disas_context(db, cpu); tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ =20 - /* Reset the temp count so that we can identify leaks */ - tcg_clear_temp_count(); - /* Start translating. */ gen_tb_start(db->tb); ops->tb_start(db, cpu); diff --git a/tcg/tcg.c b/tcg/tcg.c index b65f2ffdbe..e3c0fa1012 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1272,7 +1272,7 @@ TCGTemp *tcg_temp_new_internal(TCGType type, TCGTempK= ind kind) ts->temp_allocated =3D 1; tcg_debug_assert(ts->base_type =3D=3D type); tcg_debug_assert(ts->kind =3D=3D kind); - goto done; + return ts; } } else { tcg_debug_assert(kind =3D=3D TEMP_TB); @@ -1316,11 +1316,6 @@ TCGTemp *tcg_temp_new_internal(TCGType type, TCGTemp= Kind kind) ts2->kind =3D kind; } } - - done: -#if defined(CONFIG_DEBUG_TCG) - s->temps_in_use++; -#endif return ts; } =20 @@ -1365,30 +1360,18 @@ void tcg_temp_free_internal(TCGTemp *ts) =20 switch (ts->kind) { case TEMP_CONST: - /* - * In order to simplify users of tcg_constant_*, - * silently ignore free. - */ - return; - case TEMP_EBB: case TEMP_TB: + /* Silently ignore free. */ + break; + case TEMP_EBB: + tcg_debug_assert(ts->temp_allocated !=3D 0); + ts->temp_allocated =3D 0; + set_bit(temp_idx(ts), s->free_temps[ts->base_type].l); break; default: + /* It never made sense to free TEMP_FIXED or TEMP_GLOBAL. */ g_assert_not_reached(); } - - tcg_debug_assert(ts->temp_allocated !=3D 0); - ts->temp_allocated =3D 0; - -#if defined(CONFIG_DEBUG_TCG) - assert(s->temps_in_use > 0); - s->temps_in_use--; -#endif - - if (ts->kind =3D=3D TEMP_EBB) { - int idx =3D temp_idx(ts); - set_bit(idx, s->free_temps[ts->base_type].l); - } } =20 TCGTemp *tcg_constant_internal(TCGType type, int64_t val) @@ -1476,27 +1459,6 @@ TCGv_i64 tcg_const_i64(int64_t val) return t0; } =20 -#if defined(CONFIG_DEBUG_TCG) -void tcg_clear_temp_count(void) -{ - TCGContext *s =3D tcg_ctx; - s->temps_in_use =3D 0; -} - -int tcg_check_temp_count(void) -{ - TCGContext *s =3D tcg_ctx; - if (s->temps_in_use) { - /* Clear the count so that we don't give another - * warning immediately next time around. - */ - s->temps_in_use =3D 0; - return 1; - } - return 0; -} -#endif - /* Return true if OP may appear in the opcode stream. Test the runtime variable that controls each opcode. */ bool tcg_op_supported(TCGOpcode op) --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677475617; cv=none; d=zohomail.com; s=zohoarc; b=AXBYNZsd3TaXOlwVFHGyHngbRcRzqnSsmBi4PrIm18Jp5ZcVW/1Nt+gbbQApSMWbjb1/9wpnT+AHXGqnNNuj5UA6eeFdRuJHwc9xiRx6gcor4N6w6OZe5cnkLrg9FtbALjMPnmbvjJHOXiVEvCN4SbqtPGNXyEIZosPVv3I3pUo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677475617; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9BPaQYLLp4+nmOO9gXaqu9l3zT8hpHGLtGA7cjOsUko=; b=R7FJE0W+vM9ylcGtAlLjSgWL6NlcYJej+pXVD4BIKbQY9XoAcfNF+27gkBwhKCXJC8TXDVjKH6myjK/31BZq38Blm5yr4D1goPbDCQrfFixOi+a/cLh3a1KPryLVUNr1TfJ/ozQaKKouszPomUDAm7I5U+BUwYhxG+okrFdB6lE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16774756174791013.0635790671338; Sun, 26 Feb 2023 21:26:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW1D-0006ui-Da; Mon, 27 Feb 2023 00:25:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW0o-0006e9-NW for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:25:24 -0500 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW0j-000791-Gh for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:25:20 -0500 Received: by mail-pl1-x643.google.com with SMTP id bh1so5498445plb.11 for ; Sun, 26 Feb 2023 21:25:15 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.25.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:25:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9BPaQYLLp4+nmOO9gXaqu9l3zT8hpHGLtGA7cjOsUko=; b=cC6KasIgcfgFhHc0ZB5CO3YGMa5Zi8yzHQ9e+3yw8UjpJiBdchIp3TWvi8hvzT5jFo T5i0y/iyyO30fCAPC/PH6C5iMzTc40o7lU2W9slISetRnJr1xjWad23uNrrHePz5+rI8 XZjWEDuTxGWcJzEGeZGi+mIUdbMJJv1027DidFfEHd2gtF/PuyGMM8nUGTAtaosCWeJZ fE3Wt9wsurYGTBrMCQ6ooKIlOzBOxE+cSKZXZbi7mXt7BjhEVY8tqfnwO9trv/4zJ27f RXlFRgWzMytxuWipTAWXg07VFSPT27wQRQ7EKpaxkDv5J7N9iR/tZm21dAQPTJNc5WG3 msyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9BPaQYLLp4+nmOO9gXaqu9l3zT8hpHGLtGA7cjOsUko=; b=QHNgi4loCXP7dYb2fJ67vvezMgfOuGfERU/id3s9c5qdh30k6WJoxEgCDiQ5ZdN6SF /2uSsz895KBbxIQQ/XOb0VuIiU6YDF8wLuf+rZuAGWwH13hnUhSMA0gg4ZKkNLrWb53/ BNATyHhq5e8iDk1/IaBtKoUTWIRyu2LicmR+wmyYNEMoezw5sihPbxDlLdqGvd1i4tdq nhFZeNckAeWOFz47Qmn/I6FLMSs2/rddI3qaO8PejYj6Ed4NfAwuChIaA4Of7W2/rRY9 ojc0nzte1OsRVnG5jpz+mhvj9dzwhDBsbvqdN5aJChBZv5u0X7PMZZBjAjdl4bqsXh1W l5Pw== X-Gm-Message-State: AO0yUKXeOH1bE7bpgZWALUJRtffWgEcGdiaFJ0jakJGmIkI9COcIq1Ku +LXmn/WwAgywsFp+AGjBpWES7A16fe/ecLbx4dMYCw== X-Google-Smtp-Source: AK7set/D+clYVKbDxAFqrP5s99INO/hQHt+v9opJ9ki0tZ9jzZ4NpHle/Ziu/ae8NmeFAXXYIDS/2w== X-Received: by 2002:a17:902:c407:b0:19b:dbf7:f9d1 with SMTP id k7-20020a170902c40700b0019bdbf7f9d1mr26066194plk.37.1677475515545; Sun, 26 Feb 2023 21:25:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 02/76] accel/tcg: Remove translator_loop_temp_check Date: Sun, 26 Feb 2023 19:23:51 -1000 Message-Id: <20230227052505.352889-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x643.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475617760100007 Content-Type: text/plain; charset="utf-8" Finish removing tcg temp free accounting interfaces. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- include/exec/translator.h | 2 -- accel/tcg/translator.c | 4 ---- target/alpha/translate.c | 1 - target/arm/translate-a64.c | 2 -- target/arm/translate.c | 1 - target/ppc/translate.c | 2 -- 6 files changed, 12 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index 8b36690e80..797fef7515 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -150,8 +150,6 @@ void translator_loop(CPUState *cpu, TranslationBlock *t= b, int *max_insns, target_ulong pc, void *host_pc, const TranslatorOps *ops, DisasContextBase *db); =20 -void translator_loop_temp_check(DisasContextBase *db); - /** * translator_use_goto_tb * @db: Disassembly context diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 88567a88d1..b4183d0278 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -18,10 +18,6 @@ #include "exec/plugin-gen.h" #include "sysemu/replay.h" =20 -void translator_loop_temp_check(DisasContextBase *db) -{ -} - bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest) { /* Suppress goto_tb if requested. */ diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 716b083f39..a0afdbb465 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2996,7 +2996,6 @@ static void alpha_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) ctx->base.is_jmp =3D translate_one(ctx, insn); =20 free_context_temps(ctx); - translator_loop_temp_check(&ctx->base); } =20 static void alpha_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9da5010fe1..98537bc2ef 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14957,8 +14957,6 @@ static void aarch64_tr_translate_insn(DisasContextB= ase *dcbase, CPUState *cpu) if (s->btype > 0 && s->base.is_jmp !=3D DISAS_NORETURN) { reset_btype(s); } - - translator_loop_temp_check(&s->base); } =20 static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) diff --git a/target/arm/translate.c b/target/arm/translate.c index 9c8e1ac04c..614c438786 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9600,7 +9600,6 @@ static void arm_post_translate_insn(DisasContext *dc) gen_set_label(dc->condlabel.label); dc->condjmp =3D 0; } - translator_loop_temp_check(&dc->base); } =20 static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 2956021e89..c179f26f64 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7618,8 +7618,6 @@ static void ppc_tr_translate_insn(DisasContextBase *d= cbase, CPUState *cs) if (ctx->base.is_jmp =3D=3D DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { ctx->base.is_jmp =3D DISAS_TOO_MANY; } - - translator_loop_temp_check(&ctx->base); } =20 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677475623; cv=none; d=zohomail.com; s=zohoarc; b=lFccyGrVH8Xy3dbL2UJB6B/WGN0ugcA4NgcXE0kEDOfIwwxv8WUhhyFk0Z2RkltNhw6h0rxX2PaTgi/S4iXDRsk5s7ZpINMguGhIG5ZXmTx9VbWRFO9kWPGT0voX9PGd7WOgui4SrBtNWfmqvje7VCPgneqcUlnMCtMxeQ5/iLM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677475623; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kzN44zkvPiekz5pNcUok1y3dyGa4SpE7A5HrTAlnyn4=; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.25.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:25:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kzN44zkvPiekz5pNcUok1y3dyGa4SpE7A5HrTAlnyn4=; b=iIyWqt/6bsgvl8/B1/1pKLzTmwA+5QDNeYhWL10YlwkTybn8kNyaZB91KEMUcUh9SQ beVyQs1Pes1d0ijj2JP5KVGlgY/V8Nk8ydYz/WFEoUijYeKlwOpjfS0JmgL+boVa3Myg fB3lO3us612LwDZ2LnqTVXhK+2f7r55kOeodFEPDbx4eFy7fvHZ4FW0QawanfPXSeV7Y PvdIkl7dRw3YQBtl1WoU/w7ML+pcY+r9HA+QMpb1sOBOGj+NuVIyLaEkBPCLYmiFzB4r krjWSSRaR3dxCA2vW0SyRnIRcvQxI4PmdvNqxo4CxCPXs1S7wurgVLXLrZQinWLq4+wI iF8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kzN44zkvPiekz5pNcUok1y3dyGa4SpE7A5HrTAlnyn4=; b=Sc5V5H2aZRJFzyK+hqcup/scoIlcs8YCv8XuYMYFgZjDtuMfRyiswmCNlbpveEyN1t 8D0EpVYHNp71+BSIFW8NqwdXn8mfl+qKVbdKjLGM+bD62faPPxN/7KB3i1klp2RqAY6v Ue0BmluVnKVuxIBhb6OY+lZI+v1UE5Jqj+cjCtsJLTyXbhZbToX04GvOCQdvXay9tv/e 0fRpwYG0swqlO1xczQYFDadGGzlo6s568zO7ngGgkU5sFDqEeHH5fe1wKGtPi7TJoBCw 2QDLsx1K9nn6McWGZpsxuMOguEBSxCnHrxri6meiqjXMhbhaPhlXPF6DqDdpWgIZYOS6 Zx9Q== X-Gm-Message-State: AO0yUKUFML6s0tlg2pf1X3wmKRhKfKuhrwLhoRLgmaQ9uE47Zaol1Vq6 nSJfkWDwVxAxFenGOgHPE0qXhTgpgfoseiHMp5k= X-Google-Smtp-Source: AK7set/Lyfr/+0kiY9+7z5SPcrSjLk3muZDpU1d6MDsUwqtCMxl9ubx/WmrRohGXAoErLJuBGZEzAw== X-Received: by 2002:a17:903:32cf:b0:19b:441c:3913 with SMTP id i15-20020a17090332cf00b0019b441c3913mr28466148plr.44.1677475518144; Sun, 26 Feb 2023 21:25:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 03/76] target/alpha: Drop tcg_temp_free Date: Sun, 26 Feb 2023 19:23:52 -1000 Message-Id: <20230227052505.352889-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475623986100015 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/alpha/translate.c | 70 ---------------------------------------- 1 file changed, 70 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index a0afdbb465..9d25e21164 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -179,7 +179,6 @@ static void free_context_temps(DisasContext *ctx) { if (ctx->sink) { tcg_gen_discard_i64(ctx->sink); - tcg_temp_free(ctx->sink); ctx->sink =3D NULL; } } @@ -279,7 +278,6 @@ static void gen_ldf(DisasContext *ctx, TCGv dest, TCGv = addr) TCGv_i32 tmp32 =3D tcg_temp_new_i32(); tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); gen_helper_memory_to_f(dest, tmp32); - tcg_temp_free_i32(tmp32); } =20 static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv addr) @@ -287,7 +285,6 @@ static void gen_ldg(DisasContext *ctx, TCGv dest, TCGv = addr) TCGv tmp =3D tcg_temp_new(); tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_LEUQ | UNALIGN(ctx)); gen_helper_memory_to_g(dest, tmp); - tcg_temp_free(tmp); } =20 static void gen_lds(DisasContext *ctx, TCGv dest, TCGv addr) @@ -295,7 +292,6 @@ static void gen_lds(DisasContext *ctx, TCGv dest, TCGv = addr) TCGv_i32 tmp32 =3D tcg_temp_new_i32(); tcg_gen_qemu_ld_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); gen_helper_memory_to_s(dest, tmp32); - tcg_temp_free_i32(tmp32); } =20 static void gen_ldt(DisasContext *ctx, TCGv dest, TCGv addr) @@ -311,7 +307,6 @@ static void gen_load_fp(DisasContext *ctx, int ra, int = rb, int32_t disp16, TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); func(ctx, cpu_fir[ra], addr); - tcg_temp_free(addr); } } =20 @@ -342,7 +337,6 @@ static void gen_load_int(DisasContext *ctx, int ra, int= rb, int32_t disp16, tcg_gen_mov_i64(cpu_lock_addr, addr); tcg_gen_mov_i64(cpu_lock_value, dest); } - tcg_temp_free(addr); } =20 static void gen_stf(DisasContext *ctx, TCGv src, TCGv addr) @@ -350,7 +344,6 @@ static void gen_stf(DisasContext *ctx, TCGv src, TCGv a= ddr) TCGv_i32 tmp32 =3D tcg_temp_new_i32(); gen_helper_f_to_memory(tmp32, addr); tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); - tcg_temp_free_i32(tmp32); } =20 static void gen_stg(DisasContext *ctx, TCGv src, TCGv addr) @@ -358,7 +351,6 @@ static void gen_stg(DisasContext *ctx, TCGv src, TCGv a= ddr) TCGv tmp =3D tcg_temp_new(); gen_helper_g_to_memory(tmp, src); tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_LEUQ | UNALIGN(ctx)); - tcg_temp_free(tmp); } =20 static void gen_sts(DisasContext *ctx, TCGv src, TCGv addr) @@ -366,7 +358,6 @@ static void gen_sts(DisasContext *ctx, TCGv src, TCGv a= ddr) TCGv_i32 tmp32 =3D tcg_temp_new_i32(); gen_helper_s_to_memory(tmp32, src); tcg_gen_qemu_st_i32(tmp32, addr, ctx->mem_idx, MO_LEUL | UNALIGN(ctx)); - tcg_temp_free_i32(tmp32); } =20 static void gen_stt(DisasContext *ctx, TCGv src, TCGv addr) @@ -380,7 +371,6 @@ static void gen_store_fp(DisasContext *ctx, int ra, int= rb, int32_t disp16, TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i64(addr, load_gpr(ctx, rb), disp16); func(ctx, load_fpr(ctx, ra), addr); - tcg_temp_free(addr); } =20 static void gen_store_int(DisasContext *ctx, int ra, int rb, int32_t disp1= 6, @@ -398,8 +388,6 @@ static void gen_store_int(DisasContext *ctx, int ra, in= t rb, int32_t disp16, =20 src =3D load_gpr(ctx, ra); tcg_gen_qemu_st_i64(src, addr, ctx->mem_idx, op); - - tcg_temp_free(addr); } =20 static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int = rb, @@ -416,7 +404,6 @@ static DisasJumpType gen_store_conditional(DisasContext= *ctx, int ra, int rb, lab_fail =3D gen_new_label(); lab_done =3D gen_new_label(); tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_lock_addr, lab_fail); - tcg_temp_free_i64(addr); =20 val =3D tcg_temp_new_i64(); tcg_gen_atomic_cmpxchg_i64(val, cpu_lock_addr, cpu_lock_value, @@ -426,7 +413,6 @@ static DisasJumpType gen_store_conditional(DisasContext= *ctx, int ra, int rb, if (ra !=3D 31) { tcg_gen_setcond_i64(TCG_COND_EQ, ctx->ir[ra], val, cpu_lock_value); } - tcg_temp_free_i64(val); tcg_gen_br(lab_done); =20 gen_set_label(lab_fail); @@ -504,7 +490,6 @@ static DisasJumpType gen_bcond(DisasContext *ctx, TCGCo= nd cond, int ra, =20 tcg_gen_andi_i64(tmp, load_gpr(ctx, ra), 1); ret =3D gen_bcond_internal(ctx, cond, tmp, disp); - tcg_temp_free(tmp); return ret; } return gen_bcond_internal(ctx, cond, load_gpr(ctx, ra), disp); @@ -550,7 +535,6 @@ static DisasJumpType gen_fbcond(DisasContext *ctx, TCGC= ond cond, int ra, =20 gen_fold_mzero(cond, cmp_tmp, load_fpr(ctx, ra)); ret =3D gen_bcond_internal(ctx, cond, cmp_tmp, disp); - tcg_temp_free(cmp_tmp); return ret; } =20 @@ -564,8 +548,6 @@ static void gen_fcmov(DisasContext *ctx, TCGCond cond, = int ra, int rb, int rc) gen_fold_mzero(cond, va, load_fpr(ctx, ra)); =20 tcg_gen_movcond_i64(cond, dest_fpr(ctx, rc), va, z, vb, load_fpr(ctx, = rc)); - - tcg_temp_free(va); } =20 #define QUAL_RM_N 0x080 /* Round mode nearest even */ @@ -615,8 +597,6 @@ static void gen_qual_roundmode(DisasContext *ctx, int f= n11) #else gen_helper_setroundmode(tmp); #endif - - tcg_temp_free_i32(tmp); } =20 static void gen_qual_flushzero(DisasContext *ctx, int fn11) @@ -645,8 +625,6 @@ static void gen_qual_flushzero(DisasContext *ctx, int f= n11) #else gen_helper_setflushzero(tmp); #endif - - tcg_temp_free_i32(tmp); } =20 static TCGv gen_ieee_input(DisasContext *ctx, int reg, int fn11, int is_cm= p) @@ -716,8 +694,6 @@ static void gen_cvtlq(TCGv vc, TCGv vb) tcg_gen_shri_i64(tmp, vb, 29); tcg_gen_sari_i64(vc, vb, 32); tcg_gen_deposit_i64(vc, vc, tmp, 0, 30); - - tcg_temp_free(tmp); } =20 static void gen_ieee_arith2(DisasContext *ctx, @@ -808,8 +784,6 @@ static void gen_cpy_mask(TCGv vc, TCGv va, TCGv vb, boo= l inv_a, uint64_t mask) =20 tcg_gen_andc_i64(vc, vb, vmask); tcg_gen_or_i64(vc, vc, tmp); - - tcg_temp_free(tmp); } =20 static void gen_ieee_arith3(DisasContext *ctx, @@ -927,7 +901,6 @@ static void gen_ext_h(DisasContext *ctx, TCGv vc, TCGv = va, int rb, bool islit, tcg_gen_neg_i64(tmp, tmp); tcg_gen_andi_i64(tmp, tmp, 0x3f); tcg_gen_shl_i64(vc, va, tmp); - tcg_temp_free(tmp); } gen_zapnoti(vc, vc, byte_mask); } @@ -948,7 +921,6 @@ static void gen_ext_l(DisasContext *ctx, TCGv vc, TCGv = va, int rb, bool islit, tcg_gen_andi_i64(tmp, load_gpr(ctx, rb), 7); tcg_gen_shli_i64(tmp, tmp, 3); tcg_gen_shr_i64(vc, va, tmp); - tcg_temp_free(tmp); gen_zapnoti(vc, vc, byte_mask); } } @@ -986,8 +958,6 @@ static void gen_ins_h(DisasContext *ctx, TCGv vc, TCGv = va, int rb, bool islit, =20 tcg_gen_shr_i64(vc, tmp, shift); tcg_gen_shri_i64(vc, vc, 1); - tcg_temp_free(shift); - tcg_temp_free(tmp); } } =20 @@ -1015,8 +985,6 @@ static void gen_ins_l(DisasContext *ctx, TCGv vc, TCGv= va, int rb, bool islit, tcg_gen_andi_i64(shift, load_gpr(ctx, rb), 7); tcg_gen_shli_i64(shift, shift, 3); tcg_gen_shl_i64(vc, tmp, shift); - tcg_temp_free(shift); - tcg_temp_free(tmp); } } =20 @@ -1047,9 +1015,6 @@ static void gen_msk_h(DisasContext *ctx, TCGv vc, TCG= v va, int rb, bool islit, tcg_gen_shri_i64(mask, mask, 1); =20 tcg_gen_andc_i64(vc, va, mask); - - tcg_temp_free(mask); - tcg_temp_free(shift); } } =20 @@ -1069,9 +1034,6 @@ static void gen_msk_l(DisasContext *ctx, TCGv vc, TCG= v va, int rb, bool islit, tcg_gen_shl_i64(mask, mask, shift); =20 tcg_gen_andc_i64(vc, va, mask); - - tcg_temp_free(mask); - tcg_temp_free(shift); } } =20 @@ -1152,7 +1114,6 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, = int palcode) TCGv tmp =3D tcg_temp_new(); tcg_gen_andi_i64(tmp, ctx->ir[IR_A0], PS_INT_MASK); st_flag_byte(tmp, ENV_FLAG_PS_SHIFT); - tcg_temp_free(tmp); } =20 /* Allow interrupts to be recognized right away. */ @@ -1215,7 +1176,6 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, = int palcode) =20 tcg_gen_movi_i64(tmp, exc_addr); tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUAlphaState, exc_addr)); - tcg_temp_free(tmp); =20 entry +=3D (palcode & 0x80 ? 0x2000 + (palcode - 0x80) * 64 @@ -1550,7 +1510,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tcg_gen_shli_i64(tmp, va, 2); tcg_gen_add_i64(tmp, tmp, vb); tcg_gen_ext32s_i64(vc, tmp); - tcg_temp_free(tmp); break; case 0x09: /* SUBL */ @@ -1563,7 +1522,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tcg_gen_shli_i64(tmp, va, 2); tcg_gen_sub_i64(tmp, tmp, vb); tcg_gen_ext32s_i64(vc, tmp); - tcg_temp_free(tmp); break; case 0x0F: /* CMPBGE */ @@ -1580,7 +1538,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tcg_gen_shli_i64(tmp, va, 3); tcg_gen_add_i64(tmp, tmp, vb); tcg_gen_ext32s_i64(vc, tmp); - tcg_temp_free(tmp); break; case 0x1B: /* S8SUBL */ @@ -1588,7 +1545,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tcg_gen_shli_i64(tmp, va, 3); tcg_gen_sub_i64(tmp, tmp, vb); tcg_gen_ext32s_i64(vc, tmp); - tcg_temp_free(tmp); break; case 0x1D: /* CMPULT */ @@ -1603,7 +1559,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tmp =3D tcg_temp_new(); tcg_gen_shli_i64(tmp, va, 2); tcg_gen_add_i64(vc, tmp, vb); - tcg_temp_free(tmp); break; case 0x29: /* SUBQ */ @@ -1614,7 +1569,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tmp =3D tcg_temp_new(); tcg_gen_shli_i64(tmp, va, 2); tcg_gen_sub_i64(vc, tmp, vb); - tcg_temp_free(tmp); break; case 0x2D: /* CMPEQ */ @@ -1625,14 +1579,12 @@ static DisasJumpType translate_one(DisasContext *ct= x, uint32_t insn) tmp =3D tcg_temp_new(); tcg_gen_shli_i64(tmp, va, 3); tcg_gen_add_i64(vc, tmp, vb); - tcg_temp_free(tmp); break; case 0x3B: /* S8SUBQ */ tmp =3D tcg_temp_new(); tcg_gen_shli_i64(tmp, va, 3); tcg_gen_sub_i64(vc, tmp, vb); - tcg_temp_free(tmp); break; case 0x3D: /* CMPULE */ @@ -1646,7 +1598,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tcg_gen_add_i64(tmp, tmp, vc); tcg_gen_ext32s_i64(vc, tmp); gen_helper_check_overflow(cpu_env, vc, tmp); - tcg_temp_free(tmp); break; case 0x49: /* SUBL/V */ @@ -1656,7 +1607,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tcg_gen_sub_i64(tmp, tmp, vc); tcg_gen_ext32s_i64(vc, tmp); gen_helper_check_overflow(cpu_env, vc, tmp); - tcg_temp_free(tmp); break; case 0x4D: /* CMPLT */ @@ -1674,8 +1624,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tcg_gen_shri_i64(tmp, tmp, 63); tcg_gen_movi_i64(tmp2, 0); gen_helper_check_overflow(cpu_env, tmp, tmp2); - tcg_temp_free(tmp); - tcg_temp_free(tmp2); break; case 0x69: /* SUBQ/V */ @@ -1689,8 +1637,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tcg_gen_shri_i64(tmp, tmp, 63); tcg_gen_movi_i64(tmp2, 0); gen_helper_check_overflow(cpu_env, tmp, tmp2); - tcg_temp_free(tmp); - tcg_temp_free(tmp2); break; case 0x6D: /* CMPLE */ @@ -1744,7 +1690,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tcg_gen_andi_i64(tmp, va, 1); tcg_gen_movcond_i64(TCG_COND_NE, vc, tmp, load_zero(ctx), vb, load_gpr(ctx, rc)); - tcg_temp_free(tmp); break; case 0x16: /* CMOVLBC */ @@ -1752,7 +1697,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tcg_gen_andi_i64(tmp, va, 1); tcg_gen_movcond_i64(TCG_COND_EQ, vc, tmp, load_zero(ctx), vb, load_gpr(ctx, rc)); - tcg_temp_free(tmp); break; case 0x20: /* BIS */ @@ -1884,7 +1828,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) vb =3D load_gpr(ctx, rb); tcg_gen_andi_i64(tmp, vb, 0x3f); tcg_gen_shr_i64(vc, va, tmp); - tcg_temp_free(tmp); } break; case 0x36: @@ -1900,7 +1843,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) vb =3D load_gpr(ctx, rb); tcg_gen_andi_i64(tmp, vb, 0x3f); tcg_gen_shl_i64(vc, va, tmp); - tcg_temp_free(tmp); } break; case 0x3B: @@ -1916,7 +1858,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) vb =3D load_gpr(ctx, rb); tcg_gen_andi_i64(tmp, vb, 0x3f); tcg_gen_sar_i64(vc, va, tmp); - tcg_temp_free(tmp); } break; case 0x52: @@ -1978,7 +1919,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) /* UMULH */ tmp =3D tcg_temp_new(); tcg_gen_mulu2_i64(tmp, vc, va, vb); - tcg_temp_free(tmp); break; case 0x40: /* MULL/V */ @@ -1988,7 +1928,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tcg_gen_mul_i64(tmp, tmp, vc); tcg_gen_ext32s_i64(vc, tmp); gen_helper_check_overflow(cpu_env, vc, tmp); - tcg_temp_free(tmp); break; case 0x60: /* MULQ/V */ @@ -1997,8 +1936,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tcg_gen_muls2_i64(vc, tmp, va, vb); tcg_gen_sari_i64(tmp2, vc, 63); gen_helper_check_overflow(cpu_env, tmp, tmp2); - tcg_temp_free(tmp); - tcg_temp_free(tmp2); break; default: goto invalid_opc; @@ -2017,7 +1954,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) va =3D load_gpr(ctx, ra); tcg_gen_extrl_i64_i32(t32, va); gen_helper_memory_to_s(vc, t32); - tcg_temp_free_i32(t32); break; case 0x0A: /* SQRTF */ @@ -2040,7 +1976,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) va =3D load_gpr(ctx, ra); tcg_gen_extrl_i64_i32(t32, va); gen_helper_memory_to_f(vc, t32); - tcg_temp_free_i32(t32); break; case 0x24: /* ITOFT */ @@ -2526,7 +2461,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX, MO_LEUQ); break; } - tcg_temp_free(addr); break; } #else @@ -2550,7 +2484,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) va =3D load_fpr(ctx, ra); gen_helper_s_to_memory(t32, va); tcg_gen_ext_i32_i64(vc, t32); - tcg_temp_free_i32(t32); break; } =20 @@ -2706,7 +2639,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tmp =3D tcg_temp_new(); tcg_gen_andi_i64(tmp, vb, 1); st_flag_byte(tmp, ENV_FLAG_PAL_SHIFT); - tcg_temp_free(tmp); tcg_gen_andi_i64(cpu_pc, vb, ~3); /* Allow interrupts to be recognized right away. */ ret =3D DISAS_PC_UPDATED_NOCHAIN; @@ -2728,7 +2660,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tmp =3D tcg_temp_new(); tcg_gen_addi_i64(tmp, vb, disp12); tcg_gen_qemu_st_i64(va, tmp, MMU_PHYS_IDX, MO_LESL); - tcg_temp_free(tmp); break; case 0x1: /* Quadword physical access */ @@ -2737,7 +2668,6 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tmp =3D tcg_temp_new(); tcg_gen_addi_i64(tmp, vb, disp12); tcg_gen_qemu_st_i64(va, tmp, MMU_PHYS_IDX, MO_LEUQ); - tcg_temp_free(tmp); break; case 0x2: /* Longword physical access with lock */ --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.25.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:25:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1VaFmmXL1EVKNQ+ZqOqeimp8aObM/yTnVcjTeVASrNc=; b=blhxItn+e4d0L1sgDWHLlaL1/CFBOZ2hyoopvIoz912HhHGJ3ExhH3GP66E3MgEzBH BIXSSJj97eB6ib78ED7mXECzLEfVPte/TAoZb4mmX41nZRK9L1y3nW7WBH21gFtrQKDm FqEmvlIjPrBRm63s51k3u5VFmch2Atgupdp2KK23j1Mt5+atz/oKdi0P4bzpaYCj/KZY 6KV3sMGuz16CbTUo2eJJLtKS/FTZGdNt6rq4aMx413JMnyZmBN/XRvUSNBEMefGfA5ge RKBwXFzRZl+MBHu5bIqtINJEQZYCEt2Z1ntMqxjI/nbqMEKVGP2ab0lor3owfHnAeTDh 93gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1VaFmmXL1EVKNQ+ZqOqeimp8aObM/yTnVcjTeVASrNc=; b=h8R9AhrbwRORp2DZ655AZIW3gwZiYYFsqmIkJpmja4cJA3rB+l5Ujzyf9/prp19G1U GhMyxGObZU4BVX88wwA+VrQnJSqfIaaAMBfkZt6lH1MOfsmKQ9aAhGlfrDI1kzQZ9na+ mqP3j2l27ZpkQhzG26ZI/0SW7kFyP53gZUrX0KVivLiOAGG2qPrSmNBZjuBCTRp7BNft p1RKpxZnKDoZOnkNqxOj9AOtEzi105bR88ASLFrrc4Oi5F9AKHtikNMwvo3S/gToXPDS lCQ+TfQSaEJPDVbrG9BQ1lm9Mu4ocQ4+L2Zt+OjIL0+K8bgELxp48H/px8KY99oG3cWA 8F4w== X-Gm-Message-State: AO0yUKW8HJXE0Xh2cE6eEXG4jgwEC7nmJCvVF9V5xmcugkBOf3mPZHS9 J1ocSdqP4j5tmy5qt4AKJxWCUsPOfONdEw8D5IA= X-Google-Smtp-Source: AK7set+gPNLIZbkWk0lb9ap7DcAp28h8i6WoWhABzkl5SiUPP4W22l0siBovgnWBcndGtUtqA0jLBQ== X-Received: by 2002:a17:902:e547:b0:19a:7a02:7954 with SMTP id n7-20020a170902e54700b0019a7a027954mr29986916plf.24.1677475521037; Sun, 26 Feb 2023 21:25:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 04/76] target/arm: Remove arm_free_cc, a64_free_cc Date: Sun, 26 Feb 2023 19:23:53 -1000 Message-Id: <20230227052505.352889-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475774742100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/arm/translate.h | 1 - target/arm/translate-a64.c | 17 ++++------------- target/arm/translate.c | 9 --------- 3 files changed, 4 insertions(+), 23 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 3717824b75..7f52f08c5e 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -304,7 +304,6 @@ static inline void gen_a64_update_pc(DisasContext *s, t= arget_long diff) #endif =20 void arm_test_cc(DisasCompare *cmp, int cc); -void arm_free_cc(DisasCompare *cmp); void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); void arm_gen_test_cc(int cc, TCGLabel *label); MemOp pow2_align(unsigned i); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 98537bc2ef..2a0bba3815 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -319,18 +319,13 @@ static void a64_test_cc(DisasCompare64 *c64, int cc) =20 arm_test_cc(&c32, cc); =20 - /* Sign-extend the 32-bit value so that the GE/LT comparisons work - * properly. The NE/EQ comparisons are also fine with this choice. = */ + /* + * Sign-extend the 32-bit value so that the GE/LT comparisons work + * properly. The NE/EQ comparisons are also fine with this choice. + */ c64->cond =3D c32.cond; c64->value =3D tcg_temp_new_i64(); tcg_gen_ext_i32_i64(c64->value, c32.value); - - arm_free_cc(&c32); -} - -static void a64_free_cc(DisasCompare64 *c64) -{ - tcg_temp_free_i64(c64->value); } =20 static void gen_rebuild_hflags(DisasContext *s) @@ -5315,7 +5310,6 @@ static void disas_cc(DisasContext *s, uint32_t insn) tcg_t0 =3D tcg_temp_new_i32(); arm_test_cc(&c, cond); tcg_gen_setcondi_i32(tcg_invert_cond(c.cond), tcg_t0, c.value, 0); - arm_free_cc(&c); =20 /* Load the arguments for the new comparison. */ if (is_imm) { @@ -5435,8 +5429,6 @@ static void disas_cond_select(DisasContext *s, uint32= _t insn) tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false= ); } =20 - a64_free_cc(&c); - if (!sf) { tcg_gen_ext32u_i64(tcg_rd, tcg_rd); } @@ -6256,7 +6248,6 @@ static void disas_fp_csel(DisasContext *s, uint32_t i= nsn) tcg_gen_movcond_i64(c.cond, t_true, c.value, tcg_constant_i64(0), t_true, t_false); tcg_temp_free_i64(t_false); - a64_free_cc(&c); =20 /* Note that sregs & hregs write back zeros to the high bits, and we've already done the zero-extension. */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 614c438786..a0a298f8f7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -754,13 +754,6 @@ void arm_test_cc(DisasCompare *cmp, int cc) cmp->value_global =3D global; } =20 -void arm_free_cc(DisasCompare *cmp) -{ - if (!cmp->value_global) { - tcg_temp_free_i32(cmp->value); - } -} - void arm_jump_cc(DisasCompare *cmp, TCGLabel *label) { tcg_gen_brcondi_i32(cmp->cond, cmp->value, 0, label); @@ -771,7 +764,6 @@ void arm_gen_test_cc(int cc, TCGLabel *label) DisasCompare cmp; arm_test_cc(&cmp, cc); arm_jump_cc(&cmp, label); - arm_free_cc(&cmp); } =20 void gen_set_condexec(DisasContext *s) @@ -9125,7 +9117,6 @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a) =20 arm_test_cc(&c, a->fcond); tcg_gen_movcond_i32(c.cond, rn, c.value, zero, rn, rm); - arm_free_cc(&c); =20 store_reg(s, a->rd, rn); tcg_temp_free_i32(rm); --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677475614; cv=none; d=zohomail.com; s=zohoarc; b=iTv2Kl/yb2jEjdFPAhQBg1fkzK3OxDsA1vPs5kQPS4SEUk4GE7W+xfCJKT5palj+Fvybbugnz6mlurBwkzb2eTqlPSvsbReQ/HsJzs1e1UiFmEJHy/iEVI6Brg+QLl8KR+gl4orerQUgVv6yV465pzHcROfE2SwfrsaJrb/37OM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677475614; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uAH8ikgVoM0tmsv4PlPVbF0wuX8FOHP0nhWlFFURJoY=; b=O5k4yDPc+tCEzbCYBqF7JJtGRn+ILSIxAF8QaqZYIS1ijX42Pr5fGoWBFRwCBT/sP6/TTGrCvyr8/huwnDhtTHglvEK4AiQjKysTPIAIiftiW21EWUpkU36koNhwSWC/Ac2jvg+kzIuPc3czOAtMO2LfqSKU01PMI8muq8C0rL4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167747561456499.17847626175; Sun, 26 Feb 2023 21:26:54 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW19-0006mo-W2; Mon, 27 Feb 2023 00:25:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW0z-0006hw-0k for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:25:35 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW0s-0007F9-5u for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:25:28 -0500 Received: by mail-pj1-x1030.google.com with SMTP id y15-20020a17090aa40f00b00237ad8ee3a0so5040823pjp.2 for ; Sun, 26 Feb 2023 21:25:24 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.25.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:25:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uAH8ikgVoM0tmsv4PlPVbF0wuX8FOHP0nhWlFFURJoY=; b=uY91TEymIvOROqCyc3f8T5/iDb+AgW5yzmpq+9/HL2VXkgh3cD2xHCIis+l9+xfnaw Y64FURVLiTm5hHKD3cvRUqdCcaK/Zku2JnD/VsmedcyosKTxeT6exqFyjp04Fu8itJdB IEiTFo/fS6NXoHrFxnx/lTlZW0XXQFPievCIi0i8Om9LXWjT1nexRIJldLei7SLHa/2v LXhKzPKjpK7iIhdjTPRMXBhzKVIMmxZJBFGkZWBHoAPFikomtDkVpHL6qgKkqwVF/GdQ dvR7sR3xDAoIEBtyhKg4QU8J8FmjcgR5PBQMBdd4GDtUN17jNKg4HGJnLphUsLynx9pY 1wEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uAH8ikgVoM0tmsv4PlPVbF0wuX8FOHP0nhWlFFURJoY=; b=r6S1SAJVqzHKJqHsI1q3GflUrWjQ8oZslw3p8cBCpcfh6k9KlHmP4OP7pamRaNv9n0 igXDN3W/YxoEHniVbO7LD63glKqIJEfVGmQ8teB6tchUbte7letLAqdfSyhFoIil/SnX EvW6hDnJCd1IQ+HpNMOny7S1o4W35FoUnG4u2j+cx3PbAapI4rF0tbSUhBEGG7XkBwQf lYHdewbaPvDjicStrEZ5pDYBPgD+mTN2VV34x2ym/ayiXMkUk77g+c3oElQLrkMaJSHn DY9Qa/THVkSEjXR5pUnhbtrVjbqnkrrXBliQes8crWXoZN8wZ1b3s7zKrAzyuXGvzNRy T7Ig== X-Gm-Message-State: AO0yUKUeqKAut9DO4956qBT7jMNcqH6a4OADXuEu4vf/TuA5Vq/ptIHN 9/UJUJsnYmHTPR4Q2s3SVTuoytqxIWEpy43BShg= X-Google-Smtp-Source: AK7set/y1BBtrakPcby2yR6CU/5kaabXAxGWQzu8nNV1L7mzQrq5BArhAzW0mpkDIPhM44kdERmMyQ== X-Received: by 2002:a17:902:db08:b0:19c:da7f:a234 with SMTP id m8-20020a170902db0800b0019cda7fa234mr11843415plx.67.1677475523774; Sun, 26 Feb 2023 21:25:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 05/76] target/arm: Remove value_global from DisasCompare Date: Sun, 26 Feb 2023 19:23:54 -1000 Message-Id: <20230227052505.352889-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475616035100001 Content-Type: text/plain; charset="utf-8" This field was only used to avoid freeing globals. Since we no longer free any temps, this is dead. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/arm/translate.h | 1 - target/arm/translate.c | 5 ----- 2 files changed, 6 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 7f52f08c5e..db29e8d799 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -157,7 +157,6 @@ typedef struct DisasContext { typedef struct DisasCompare { TCGCond cond; TCGv_i32 value; - bool value_global; } DisasCompare; =20 /* Share the TCG temporaries common between 32 and 64 bit modes. */ diff --git a/target/arm/translate.c b/target/arm/translate.c index a0a298f8f7..f76a83b473 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -672,7 +672,6 @@ void arm_test_cc(DisasCompare *cmp, int cc) { TCGv_i32 value; TCGCond cond; - bool global =3D true; =20 switch (cc) { case 0: /* eq: Z */ @@ -703,7 +702,6 @@ void arm_test_cc(DisasCompare *cmp, int cc) case 9: /* ls: !C || Z -> !(C && !Z) */ cond =3D TCG_COND_NE; value =3D tcg_temp_new_i32(); - global =3D false; /* CF is 1 for C, so -CF is an all-bits-set mask for C; ZF is non-zero for !Z; so AND the two subexpressions. */ tcg_gen_neg_i32(value, cpu_CF); @@ -715,7 +713,6 @@ void arm_test_cc(DisasCompare *cmp, int cc) /* Since we're only interested in the sign bit, =3D=3D 0 is >=3D 0= . */ cond =3D TCG_COND_GE; value =3D tcg_temp_new_i32(); - global =3D false; tcg_gen_xor_i32(value, cpu_VF, cpu_NF); break; =20 @@ -723,7 +720,6 @@ void arm_test_cc(DisasCompare *cmp, int cc) case 13: /* le: Z || N !=3D V */ cond =3D TCG_COND_NE; value =3D tcg_temp_new_i32(); - global =3D false; /* (N =3D=3D V) is equal to the sign bit of ~(NF ^ VF). Propagate * the sign bit then AND with ZF to yield the result. */ tcg_gen_xor_i32(value, cpu_VF, cpu_NF); @@ -751,7 +747,6 @@ void arm_test_cc(DisasCompare *cmp, int cc) no_invert: cmp->cond =3D cond; cmp->value =3D value; - cmp->value_global =3D global; } =20 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label) --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677475661; cv=none; d=zohomail.com; s=zohoarc; b=V4h8AvVGOqmFs4a9Zxc+MEsrHd3vLZTv3lu+YxG818cGymrxXyTmO63EJ1TvCd4MNbp2mONk1I//CCB5VIMNdYXL14T9WKaCT0if2pJt9FCxkPAFpnIxjx7R+CYNOtp9pJNeapTVlGhhGrj/HWHWakopXTrx80zGVRheflLFqHw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677475661; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qOBtvFMoY0KEyRlCMgows0z9/m76rQnQOiGjaEjvbyI=; b=DBIOSQnZAX7ZJeKWi8swBd6aII61WXwq+TxBwvu2pwTY7ZvNHTYThx3/w56peIOfy+jCSoVNMuMECWu1yXQhhBhQ8yQhDYK2pjCPlcIiwmFW+CsPYl38gRKp81otmmD83+qKCSpkH0vgRPhN9+K29C/Zg8dskuS8XaiCUaofUU4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677475661072442.9114199540236; Sun, 26 Feb 2023 21:27:41 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW1K-00075J-6V; Mon, 27 Feb 2023 00:25:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW16-0006lS-4r for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:25:41 -0500 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW0y-0007HQ-Nn for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:25:39 -0500 Received: by mail-pl1-x644.google.com with SMTP id i10so5510212plr.9 for ; Sun, 26 Feb 2023 21:25:28 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.25.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:25:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qOBtvFMoY0KEyRlCMgows0z9/m76rQnQOiGjaEjvbyI=; b=Q0TrT0eoGRjZ7sX3KFMTHZcgOM11M66x6LRJn31qNZ5Bc3Y64ApGzC+svTor56XInP ineY1iDFz9s/w7UxlVQxgp1b1JWYBP3KhjPXyUdQ5QJAGoyRuFd+tdvUci/83DGW4PlP tg09aZVQC9aWnTis2flXKDAN4fvN2UpJN0s5tQ+Zf/9OUZ+xlZsPz+1CEAFEqKLBsrLO 1Rp4Ipeh2ToGx6mK3fxBMEbcbH9ij1PFTyly9406Z/7rHt96azta5gnHxTsO6EJYOA0s NFsrk46SzUhbLxIy35e3GpC8UPAnSVGy7zqGEou4DaPbpUkZlwQf2+ryOxoS4Y78Xc1k HZuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qOBtvFMoY0KEyRlCMgows0z9/m76rQnQOiGjaEjvbyI=; b=L0PSA00yCdzLjA8FEQGDeGQktk8Jg4CMzaSqxTSbyiiFzCYhe7MgyJI6llCh4m6tG+ NOYEyEPtZWHPdSNVA3lF43AZc5PqbB5PL1J/Dx/kFLSp3hNbjAnZP7u1jfHDcYpVPTSO QtlAENxGGPUzKawoAyn5rSYAGfqi6llqSLQqQKQqAeHxw1G6agsbw8gIYO7J2VePjIBb j1tioFVIzXwoF+iq3OoPjKk9RQL/wXxJvWZJIRZSsyhB1Ggxt5gYojoZJKxaRost+EJ/ 12MMjAxLzo8pK+m2HPNbWO1ISunDHT+lkB+E10JfZSe/syaQghsMBFe4ACLUokdRBhK2 /toA== X-Gm-Message-State: AO0yUKV9P9RQYpMzSeip166bzKHll1ByjRNhn89+lfyGFfIZaMfp7aqg D1/uKJVwOTD6vcNKpa2HEw6uA2xTTYDcxi8577Ezxw== X-Google-Smtp-Source: AK7set82NMsY66DoKDNpY6x7ZYXS8lCiJgu+tLZsVGMJa66vH9sNx+nTb9ul/oilesrbGYYcxYjTSw== X-Received: by 2002:a17:903:32cf:b0:19a:8e52:ce0 with SMTP id i15-20020a17090332cf00b0019a8e520ce0mr31211237plr.58.1677475526829; Sun, 26 Feb 2023 21:25:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 06/76] target/arm: Drop tcg_temp_free from translator.c Date: Sun, 26 Feb 2023 19:23:55 -1000 Message-Id: <20230227052505.352889-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x644.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475662065100003 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/arm/translate.c | 266 +---------------------------------------- 1 file changed, 5 insertions(+), 261 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index f76a83b473..645bcf8d0a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -195,7 +195,6 @@ void store_cpu_offset(TCGv_i32 var, int offset, int siz= e) default: g_assert_not_reached(); } - tcg_temp_free_i32(var); } =20 /* Save the syndrome information for a Data Abort */ @@ -325,7 +324,6 @@ void store_reg(DisasContext *s, int reg, TCGv_i32 var) tcg_gen_andi_i32(var, var, ~3); } tcg_gen_mov_i32(cpu_R[reg], var); - tcg_temp_free_i32(var); } =20 /* @@ -420,12 +418,10 @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) tcg_gen_ext16s_i32(tmp1, a); tcg_gen_ext16s_i32(tmp2, b); tcg_gen_mul_i32(tmp1, tmp1, tmp2); - tcg_temp_free_i32(tmp2); tcg_gen_sari_i32(a, a, 16); tcg_gen_sari_i32(b, b, 16); tcg_gen_mul_i32(b, b, a); tcg_gen_mov_i32(a, tmp1); - tcg_temp_free_i32(tmp1); } =20 /* Byteswap each halfword. */ @@ -438,7 +434,6 @@ void gen_rev16(TCGv_i32 dest, TCGv_i32 var) tcg_gen_and_i32(var, var, mask); tcg_gen_shli_i32(var, var, 8); tcg_gen_or_i32(dest, var, tmp); - tcg_temp_free_i32(tmp); } =20 /* Byteswap low halfword and sign extend. */ @@ -463,7 +458,6 @@ static void gen_add16(TCGv_i32 dest, TCGv_i32 t0, TCGv_= i32 t1) tcg_gen_andi_i32(t1, t1, ~0x8000); tcg_gen_add_i32(t0, t0, t1); tcg_gen_xor_i32(dest, t0, tmp); - tcg_temp_free_i32(tmp); } =20 /* Set N and Z flags from var. */ @@ -498,7 +492,6 @@ static void gen_add_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv= _i32 t1) tcg_gen_xor_i32(cpu_VF, cpu_NF, t0); tcg_gen_xor_i32(tmp, t0, t1); tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); - tcg_temp_free_i32(tmp); tcg_gen_mov_i32(dest, cpu_NF); } =20 @@ -519,14 +512,11 @@ static void gen_adc_CC(TCGv_i32 dest, TCGv_i32 t0, TC= Gv_i32 t1) tcg_gen_extu_i32_i64(q1, cpu_CF); tcg_gen_add_i64(q0, q0, q1); tcg_gen_extr_i64_i32(cpu_NF, cpu_CF, q0); - tcg_temp_free_i64(q0); - tcg_temp_free_i64(q1); } tcg_gen_mov_i32(cpu_ZF, cpu_NF); tcg_gen_xor_i32(cpu_VF, cpu_NF, t0); tcg_gen_xor_i32(tmp, t0, t1); tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); - tcg_temp_free_i32(tmp); tcg_gen_mov_i32(dest, cpu_NF); } =20 @@ -541,7 +531,6 @@ static void gen_sub_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv= _i32 t1) tmp =3D tcg_temp_new_i32(); tcg_gen_xor_i32(tmp, t0, t1); tcg_gen_and_i32(cpu_VF, cpu_VF, tmp); - tcg_temp_free_i32(tmp); tcg_gen_mov_i32(dest, cpu_NF); } =20 @@ -551,7 +540,6 @@ static void gen_sbc_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv= _i32 t1) TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_not_i32(tmp, t1); gen_adc_CC(dest, t0, tmp); - tcg_temp_free_i32(tmp); } =20 #define GEN_SHIFT(name) \ @@ -564,8 +552,6 @@ static void gen_##name(TCGv_i32 dest, TCGv_i32 t0, TCGv= _i32 t1) \ tcg_gen_##name##_i32(tmpd, t0, tmp1); \ tcg_gen_andi_i32(tmp1, t1, 0xe0); \ tcg_gen_movcond_i32(TCG_COND_NE, dest, tmp1, zero, zero, tmpd); \ - tcg_temp_free_i32(tmpd); \ - tcg_temp_free_i32(tmp1); \ } GEN_SHIFT(shl) GEN_SHIFT(shr) @@ -578,7 +564,6 @@ static void gen_sar(TCGv_i32 dest, TCGv_i32 t0, TCGv_i3= 2 t1) tcg_gen_andi_i32(tmp1, t1, 0xff); tcg_gen_umin_i32(tmp1, tmp1, tcg_constant_i32(31)); tcg_gen_sar_i32(dest, t0, tmp1); - tcg_temp_free_i32(tmp1); } =20 static void shifter_out_im(TCGv_i32 var, int shift) @@ -631,7 +616,6 @@ static inline void gen_arm_shift_im(TCGv_i32 var, int s= hiftop, shifter_out_im(var, 0); tcg_gen_shri_i32(var, var, 1); tcg_gen_or_i32(var, var, tmp); - tcg_temp_free_i32(tmp); } } }; @@ -661,7 +645,6 @@ static inline void gen_arm_shift_reg(TCGv_i32 var, int = shiftop, tcg_gen_rotr_i32(var, var, shift); break; } } - tcg_temp_free_i32(shift); } =20 /* @@ -875,7 +858,6 @@ static inline void gen_bxns(DisasContext *s, int rm) * "zeroes the IT bits" as our UNPREDICTABLE behaviour otherwise. */ gen_helper_v7m_bxns(cpu_env, var); - tcg_temp_free_i32(var); s->base.is_jmp =3D DISAS_EXIT; } =20 @@ -889,7 +871,6 @@ static inline void gen_blxns(DisasContext *s, int rm) */ gen_update_pc(s, curr_insn_len(s)); gen_helper_v7m_blxns(cpu_env, var); - tcg_temp_free_i32(var); s->base.is_jmp =3D DISAS_EXIT; } =20 @@ -969,7 +950,6 @@ void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32= val, { TCGv addr =3D gen_aa32_addr(s, a32, opc); tcg_gen_qemu_ld_i32(val, addr, index, opc); - tcg_temp_free(addr); } =20 void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val, @@ -977,7 +957,6 @@ void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32= val, { TCGv addr =3D gen_aa32_addr(s, a32, opc); tcg_gen_qemu_st_i32(val, addr, index, opc); - tcg_temp_free(addr); } =20 void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val, @@ -991,7 +970,6 @@ void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64= val, if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) =3D=3D MO_64) { tcg_gen_rotri_i64(val, val, 32); } - tcg_temp_free(addr); } =20 void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val, @@ -1004,11 +982,9 @@ void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i= 64 val, TCGv_i64 tmp =3D tcg_temp_new_i64(); tcg_gen_rotri_i64(tmp, val, 32); tcg_gen_qemu_st_i64(tmp, addr, index, opc); - tcg_temp_free_i64(tmp); } else { tcg_gen_qemu_st_i64(val, addr, index, opc); } - tcg_temp_free(addr); } =20 void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, @@ -1320,7 +1296,6 @@ static inline TCGv_i32 iwmmxt_load_creg(int reg) static inline void iwmmxt_store_creg(int reg, TCGv_i32 var) { tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg])); - tcg_temp_free_i32(var); } =20 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn) @@ -1479,10 +1454,9 @@ static inline int gen_iwmmxt_address(DisasContext *s= , uint32_t insn, else tcg_gen_addi_i32(tmp, tmp, -offset); tcg_gen_mov_i32(dest, tmp); - if (insn & (1 << 21)) + if (insn & (1 << 21)) { store_reg(s, rd, tmp); - else - tcg_temp_free_i32(tmp); + } } else if (insn & (1 << 21)) { /* Post indexed */ tcg_gen_mov_i32(dest, tmp); @@ -1514,7 +1488,6 @@ static inline int gen_iwmmxt_shift(uint32_t insn, uin= t32_t mask, TCGv_i32 dest) } tcg_gen_andi_i32(tmp, tmp, mask); tcg_gen_mov_i32(dest, tmp); - tcg_temp_free_i32(tmp); return 0; } =20 @@ -1547,7 +1520,6 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) wrd =3D (insn >> 12) & 0xf; addr =3D tcg_temp_new_i32(); if (gen_iwmmxt_address(s, insn, addr)) { - tcg_temp_free_i32(addr); return 1; } if (insn & ARM_CP_RW_BIT) { @@ -1575,7 +1547,6 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) } if (i) { tcg_gen_extu_i32_i64(cpu_M0, tmp); - tcg_temp_free_i32(tmp); } gen_op_iwmmxt_movq_wRn_M0(wrd); } @@ -1603,9 +1574,7 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) } } } - tcg_temp_free_i32(tmp); } - tcg_temp_free_i32(addr); return 0; } =20 @@ -1640,7 +1609,6 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) tmp =3D iwmmxt_load_creg(wrd); tmp2 =3D load_reg(s, rd); tcg_gen_andc_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); iwmmxt_store_creg(wrd, tmp); break; case ARM_IWMMXT_wCGR0: @@ -1853,7 +1821,6 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) tcg_gen_andi_i32(tmp, tmp, 7); iwmmxt_load_reg(cpu_V1, rd1); gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp); - tcg_temp_free_i32(tmp); gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_set_mup(); break; @@ -1881,7 +1848,6 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) g_assert_not_reached(); } gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3); - tcg_temp_free_i32(tmp); gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_set_mup(); break; @@ -1935,7 +1901,6 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) } tcg_gen_shli_i32(tmp, tmp, 28); gen_set_nzcv(tmp); - tcg_temp_free_i32(tmp); break; case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */ if (((insn >> 6) & 3) =3D=3D 3) @@ -1954,7 +1919,6 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) gen_helper_iwmmxt_bcstl(cpu_M0, tmp); break; } - tcg_temp_free_i32(tmp); gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_set_mup(); break; @@ -1983,8 +1947,6 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) break; } gen_set_nzcv(tmp); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); break; case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */ wrd =3D (insn >> 12) & 0xf; @@ -2031,8 +1993,6 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) break; } gen_set_nzcv(tmp); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); break; case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */ rd =3D (insn >> 12) & 0xf; @@ -2157,7 +2117,6 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) gen_op_iwmmxt_movq_M0_wRn(rd0); tmp =3D tcg_temp_new_i32(); if (gen_iwmmxt_shift(insn, 0xff, tmp)) { - tcg_temp_free_i32(tmp); return 1; } switch ((insn >> 22) & 3) { @@ -2171,7 +2130,6 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp); break; } - tcg_temp_free_i32(tmp); gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_set_mup(); gen_op_iwmmxt_set_cup(); @@ -2185,7 +2143,6 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) gen_op_iwmmxt_movq_M0_wRn(rd0); tmp =3D tcg_temp_new_i32(); if (gen_iwmmxt_shift(insn, 0xff, tmp)) { - tcg_temp_free_i32(tmp); return 1; } switch ((insn >> 22) & 3) { @@ -2199,7 +2156,6 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp); break; } - tcg_temp_free_i32(tmp); gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_set_mup(); gen_op_iwmmxt_set_cup(); @@ -2213,7 +2169,6 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) gen_op_iwmmxt_movq_M0_wRn(rd0); tmp =3D tcg_temp_new_i32(); if (gen_iwmmxt_shift(insn, 0xff, tmp)) { - tcg_temp_free_i32(tmp); return 1; } switch ((insn >> 22) & 3) { @@ -2227,7 +2182,6 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp); break; } - tcg_temp_free_i32(tmp); gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_set_mup(); gen_op_iwmmxt_set_cup(); @@ -2243,27 +2197,23 @@ static int disas_iwmmxt_insn(DisasContext *s, uint3= 2_t insn) switch ((insn >> 22) & 3) { case 1: if (gen_iwmmxt_shift(insn, 0xf, tmp)) { - tcg_temp_free_i32(tmp); return 1; } gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp); break; case 2: if (gen_iwmmxt_shift(insn, 0x1f, tmp)) { - tcg_temp_free_i32(tmp); return 1; } gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp); break; case 3: if (gen_iwmmxt_shift(insn, 0x3f, tmp)) { - tcg_temp_free_i32(tmp); return 1; } gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp); break; } - tcg_temp_free_i32(tmp); gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_set_mup(); gen_op_iwmmxt_set_cup(); @@ -2502,12 +2452,8 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32= _t insn) gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2); break; default: - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); return 1; } - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_set_mup(); break; @@ -2556,8 +2502,6 @@ static int disas_dsp_insn(DisasContext *s, uint32_t i= nsn) default: return 1; } - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); =20 gen_op_iwmmxt_movq_wRn_M0(acc); return 0; @@ -2734,7 +2678,6 @@ static int gen_set_psr(DisasContext *s, uint32_t mask= , int spsr, TCGv_i32 t0) } else { gen_set_cpsr(t0, mask); } - tcg_temp_free_i32(t0); gen_lookup_tb(s); return 0; } @@ -2882,7 +2825,6 @@ static bool msr_banked_access_decode(DisasContext *s,= int r, int sysm, int rn, =20 gen_exception_insn_el_v(s, 0, EXCP_UDEF, syn_uncategorized(), tcg_el); - tcg_temp_free_i32(tcg_el); return false; } break; @@ -2926,7 +2868,6 @@ static void gen_msr_banked(DisasContext *s, int r, in= t sysm, int rn) gen_helper_msr_banked(cpu_env, tcg_reg, tcg_constant_i32(tgtmode), tcg_constant_i32(regno)); - tcg_temp_free_i32(tcg_reg); s->base.is_jmp =3D DISAS_UPDATE_EXIT; } =20 @@ -2957,7 +2898,6 @@ static void gen_mrs_banked(DisasContext *s, int r, in= t sysm, int rn) static void store_pc_exc_ret(DisasContext *s, TCGv_i32 pc) { tcg_gen_mov_i32(cpu_R[15], pc); - tcg_temp_free_i32(pc); } =20 /* Generate a v6 exception return. Marks both values as dead. */ @@ -2972,7 +2912,6 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCG= v_i32 cpsr) gen_io_start(); } gen_helper_cpsr_write_eret(cpu_env, cpsr); - tcg_temp_free_i32(cpsr); /* Must exit loop to check un-masked IRQs */ s->base.is_jmp =3D DISAS_EXIT; } @@ -2992,7 +2931,6 @@ static void gen_gvec_fn3_qc(uint32_t rd_ofs, uint32_t= rn_ofs, uint32_t rm_ofs, tcg_gen_addi_ptr(qc_ptr, cpu_env, offsetof(CPUARMState, vfp.qc)); tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, qc_ptr, opr_sz, max_sz, 0, fn); - tcg_temp_free_ptr(qc_ptr); } =20 void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, @@ -3238,7 +3176,6 @@ static void gen_srshr8_i64(TCGv_i64 d, TCGv_i64 a, in= t64_t sh) tcg_gen_andi_i64(t, t, dup_const(MO_8, 1)); tcg_gen_vec_sar8i_i64(d, a, sh); tcg_gen_vec_add8_i64(d, d, t); - tcg_temp_free_i64(t); } =20 static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh) @@ -3249,7 +3186,6 @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, i= nt64_t sh) tcg_gen_andi_i64(t, t, dup_const(MO_16, 1)); tcg_gen_vec_sar16i_i64(d, a, sh); tcg_gen_vec_add16_i64(d, d, t); - tcg_temp_free_i64(t); } =20 static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh) @@ -3265,7 +3201,6 @@ static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, i= nt32_t sh) tcg_gen_extract_i32(t, a, sh - 1, 1); tcg_gen_sari_i32(d, a, sh); tcg_gen_add_i32(d, d, t); - tcg_temp_free_i32(t); } =20 static void gen_srshr64_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh) @@ -3275,7 +3210,6 @@ static void gen_srshr64_i64(TCGv_i64 d, TCGv_i64 a, i= nt64_t sh) tcg_gen_extract_i64(t, a, sh - 1, 1); tcg_gen_sari_i64(d, a, sh); tcg_gen_add_i64(d, d, t); - tcg_temp_free_i64(t); } =20 static void gen_srshr_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t s= h) @@ -3288,9 +3222,6 @@ static void gen_srshr_vec(unsigned vece, TCGv_vec d, = TCGv_vec a, int64_t sh) tcg_gen_and_vec(vece, t, t, ones); tcg_gen_sari_vec(vece, d, a, sh); tcg_gen_add_vec(vece, d, d, t); - - tcg_temp_free_vec(t); - tcg_temp_free_vec(ones); } =20 void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, @@ -3346,7 +3277,6 @@ static void gen_srsra8_i64(TCGv_i64 d, TCGv_i64 a, in= t64_t sh) =20 gen_srshr8_i64(t, a, sh); tcg_gen_vec_add8_i64(d, d, t); - tcg_temp_free_i64(t); } =20 static void gen_srsra16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh) @@ -3355,7 +3285,6 @@ static void gen_srsra16_i64(TCGv_i64 d, TCGv_i64 a, i= nt64_t sh) =20 gen_srshr16_i64(t, a, sh); tcg_gen_vec_add16_i64(d, d, t); - tcg_temp_free_i64(t); } =20 static void gen_srsra32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh) @@ -3364,7 +3293,6 @@ static void gen_srsra32_i32(TCGv_i32 d, TCGv_i32 a, i= nt32_t sh) =20 gen_srshr32_i32(t, a, sh); tcg_gen_add_i32(d, d, t); - tcg_temp_free_i32(t); } =20 static void gen_srsra64_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh) @@ -3373,7 +3301,6 @@ static void gen_srsra64_i64(TCGv_i64 d, TCGv_i64 a, i= nt64_t sh) =20 gen_srshr64_i64(t, a, sh); tcg_gen_add_i64(d, d, t); - tcg_temp_free_i64(t); } =20 static void gen_srsra_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t s= h) @@ -3382,7 +3309,6 @@ static void gen_srsra_vec(unsigned vece, TCGv_vec d, = TCGv_vec a, int64_t sh) =20 gen_srshr_vec(vece, t, a, sh); tcg_gen_add_vec(vece, d, d, t); - tcg_temp_free_vec(t); } =20 void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, @@ -3445,7 +3371,6 @@ static void gen_urshr8_i64(TCGv_i64 d, TCGv_i64 a, in= t64_t sh) tcg_gen_andi_i64(t, t, dup_const(MO_8, 1)); tcg_gen_vec_shr8i_i64(d, a, sh); tcg_gen_vec_add8_i64(d, d, t); - tcg_temp_free_i64(t); } =20 static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh) @@ -3456,7 +3381,6 @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, i= nt64_t sh) tcg_gen_andi_i64(t, t, dup_const(MO_16, 1)); tcg_gen_vec_shr16i_i64(d, a, sh); tcg_gen_vec_add16_i64(d, d, t); - tcg_temp_free_i64(t); } =20 static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh) @@ -3472,7 +3396,6 @@ static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, i= nt32_t sh) tcg_gen_extract_i32(t, a, sh - 1, 1); tcg_gen_shri_i32(d, a, sh); tcg_gen_add_i32(d, d, t); - tcg_temp_free_i32(t); } =20 static void gen_urshr64_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh) @@ -3482,7 +3405,6 @@ static void gen_urshr64_i64(TCGv_i64 d, TCGv_i64 a, i= nt64_t sh) tcg_gen_extract_i64(t, a, sh - 1, 1); tcg_gen_shri_i64(d, a, sh); tcg_gen_add_i64(d, d, t); - tcg_temp_free_i64(t); } =20 static void gen_urshr_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t s= hift) @@ -3495,9 +3417,6 @@ static void gen_urshr_vec(unsigned vece, TCGv_vec d, = TCGv_vec a, int64_t shift) tcg_gen_and_vec(vece, t, t, ones); tcg_gen_shri_vec(vece, d, a, shift); tcg_gen_add_vec(vece, d, d, t); - - tcg_temp_free_vec(t); - tcg_temp_free_vec(ones); } =20 void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, @@ -3556,7 +3475,6 @@ static void gen_ursra8_i64(TCGv_i64 d, TCGv_i64 a, in= t64_t sh) gen_urshr8_i64(t, a, sh); } tcg_gen_vec_add8_i64(d, d, t); - tcg_temp_free_i64(t); } =20 static void gen_ursra16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh) @@ -3569,7 +3487,6 @@ static void gen_ursra16_i64(TCGv_i64 d, TCGv_i64 a, i= nt64_t sh) gen_urshr16_i64(t, a, sh); } tcg_gen_vec_add16_i64(d, d, t); - tcg_temp_free_i64(t); } =20 static void gen_ursra32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh) @@ -3582,7 +3499,6 @@ static void gen_ursra32_i32(TCGv_i32 d, TCGv_i32 a, i= nt32_t sh) gen_urshr32_i32(t, a, sh); } tcg_gen_add_i32(d, d, t); - tcg_temp_free_i32(t); } =20 static void gen_ursra64_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh) @@ -3595,7 +3511,6 @@ static void gen_ursra64_i64(TCGv_i64 d, TCGv_i64 a, i= nt64_t sh) gen_urshr64_i64(t, a, sh); } tcg_gen_add_i64(d, d, t); - tcg_temp_free_i64(t); } =20 static void gen_ursra_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t s= h) @@ -3608,7 +3523,6 @@ static void gen_ursra_vec(unsigned vece, TCGv_vec d, = TCGv_vec a, int64_t sh) gen_urshr_vec(vece, t, a, sh); } tcg_gen_add_vec(vece, d, d, t); - tcg_temp_free_vec(t); } =20 void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, @@ -3661,7 +3575,6 @@ static void gen_shr8_ins_i64(TCGv_i64 d, TCGv_i64 a, = int64_t shift) tcg_gen_andi_i64(t, t, mask); tcg_gen_andi_i64(d, d, ~mask); tcg_gen_or_i64(d, d, t); - tcg_temp_free_i64(t); } =20 static void gen_shr16_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) @@ -3673,7 +3586,6 @@ static void gen_shr16_ins_i64(TCGv_i64 d, TCGv_i64 a,= int64_t shift) tcg_gen_andi_i64(t, t, mask); tcg_gen_andi_i64(d, d, ~mask); tcg_gen_or_i64(d, d, t); - tcg_temp_free_i64(t); } =20 static void gen_shr32_ins_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift) @@ -3697,9 +3609,6 @@ static void gen_shr_ins_vec(unsigned vece, TCGv_vec d= , TCGv_vec a, int64_t sh) tcg_gen_shri_vec(vece, t, a, sh); tcg_gen_and_vec(vece, d, d, m); tcg_gen_or_vec(vece, d, d, t); - - tcg_temp_free_vec(t); - tcg_temp_free_vec(m); } =20 void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, @@ -3756,7 +3665,6 @@ static void gen_shl8_ins_i64(TCGv_i64 d, TCGv_i64 a, = int64_t shift) tcg_gen_andi_i64(t, t, mask); tcg_gen_andi_i64(d, d, ~mask); tcg_gen_or_i64(d, d, t); - tcg_temp_free_i64(t); } =20 static void gen_shl16_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) @@ -3768,7 +3676,6 @@ static void gen_shl16_ins_i64(TCGv_i64 d, TCGv_i64 a,= int64_t shift) tcg_gen_andi_i64(t, t, mask); tcg_gen_andi_i64(d, d, ~mask); tcg_gen_or_i64(d, d, t); - tcg_temp_free_i64(t); } =20 static void gen_shl32_ins_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift) @@ -3790,9 +3697,6 @@ static void gen_shl_ins_vec(unsigned vece, TCGv_vec d= , TCGv_vec a, int64_t sh) tcg_gen_dupi_vec(vece, m, MAKE_64BIT_MASK(0, sh)); tcg_gen_and_vec(vece, d, d, m); tcg_gen_or_vec(vece, d, d, t); - - tcg_temp_free_vec(t); - tcg_temp_free_vec(m); } =20 void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, @@ -4033,11 +3937,6 @@ void gen_ushl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i= 32 shift) tcg_gen_shr_i32(rval, src, rsh); tcg_gen_movcond_i32(TCG_COND_LTU, dst, lsh, max, lval, zero); tcg_gen_movcond_i32(TCG_COND_LTU, dst, rsh, max, rval, dst); - - tcg_temp_free_i32(lval); - tcg_temp_free_i32(rval); - tcg_temp_free_i32(lsh); - tcg_temp_free_i32(rsh); } =20 void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift) @@ -4060,11 +3959,6 @@ void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i= 64 shift) tcg_gen_shr_i64(rval, src, rsh); tcg_gen_movcond_i64(TCG_COND_LTU, dst, lsh, max, lval, zero); tcg_gen_movcond_i64(TCG_COND_LTU, dst, rsh, max, rval, dst); - - tcg_temp_free_i64(lval); - tcg_temp_free_i64(rval); - tcg_temp_free_i64(lsh); - tcg_temp_free_i64(rsh); } =20 static void gen_ushl_vec(unsigned vece, TCGv_vec dst, @@ -4084,7 +3978,6 @@ static void gen_ushl_vec(unsigned vece, TCGv_vec dst, tcg_gen_dupi_vec(vece, msk, 0xff); tcg_gen_and_vec(vece, lsh, shift, msk); tcg_gen_and_vec(vece, rsh, rsh, msk); - tcg_temp_free_vec(msk); } =20 /* @@ -4117,12 +4010,6 @@ static void gen_ushl_vec(unsigned vece, TCGv_vec dst, tcg_gen_and_vec(vece, rval, rval, rsh); } tcg_gen_or_vec(vece, dst, lval, rval); - - tcg_temp_free_vec(max); - tcg_temp_free_vec(lval); - tcg_temp_free_vec(rval); - tcg_temp_free_vec(lsh); - tcg_temp_free_vec(rsh); } =20 void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, @@ -4174,11 +4061,6 @@ void gen_sshl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i= 32 shift) tcg_gen_sar_i32(rval, src, rsh); tcg_gen_movcond_i32(TCG_COND_LEU, lval, lsh, max, lval, zero); tcg_gen_movcond_i32(TCG_COND_LT, dst, lsh, zero, rval, lval); - - tcg_temp_free_i32(lval); - tcg_temp_free_i32(rval); - tcg_temp_free_i32(lsh); - tcg_temp_free_i32(rsh); } =20 void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift) @@ -4202,11 +4084,6 @@ void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i= 64 shift) tcg_gen_sar_i64(rval, src, rsh); tcg_gen_movcond_i64(TCG_COND_LEU, lval, lsh, max, lval, zero); tcg_gen_movcond_i64(TCG_COND_LT, dst, lsh, zero, rval, lval); - - tcg_temp_free_i64(lval); - tcg_temp_free_i64(rval); - tcg_temp_free_i64(lsh); - tcg_temp_free_i64(rsh); } =20 static void gen_sshl_vec(unsigned vece, TCGv_vec dst, @@ -4251,12 +4128,6 @@ static void gen_sshl_vec(unsigned vece, TCGv_vec dst, tcg_gen_dupi_vec(vece, tmp, 0x80); tcg_gen_cmpsel_vec(TCG_COND_LT, vece, dst, lsh, tmp, lval, rval); } - - tcg_temp_free_vec(lval); - tcg_temp_free_vec(rval); - tcg_temp_free_vec(lsh); - tcg_temp_free_vec(rsh); - tcg_temp_free_vec(tmp); } =20 void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, @@ -4295,7 +4166,6 @@ static void gen_uqadd_vec(unsigned vece, TCGv_vec t, = TCGv_vec sat, tcg_gen_usadd_vec(vece, t, a, b); tcg_gen_cmp_vec(TCG_COND_NE, vece, x, x, t); tcg_gen_or_vec(vece, sat, sat, x); - tcg_temp_free_vec(x); } =20 void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, @@ -4338,7 +4208,6 @@ static void gen_sqadd_vec(unsigned vece, TCGv_vec t, = TCGv_vec sat, tcg_gen_ssadd_vec(vece, t, a, b); tcg_gen_cmp_vec(TCG_COND_NE, vece, x, x, t); tcg_gen_or_vec(vece, sat, sat, x); - tcg_temp_free_vec(x); } =20 void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, @@ -4381,7 +4250,6 @@ static void gen_uqsub_vec(unsigned vece, TCGv_vec t, = TCGv_vec sat, tcg_gen_ussub_vec(vece, t, a, b); tcg_gen_cmp_vec(TCG_COND_NE, vece, x, x, t); tcg_gen_or_vec(vece, sat, sat, x); - tcg_temp_free_vec(x); } =20 void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, @@ -4424,7 +4292,6 @@ static void gen_sqsub_vec(unsigned vece, TCGv_vec t, = TCGv_vec sat, tcg_gen_sssub_vec(vece, t, a, b); tcg_gen_cmp_vec(TCG_COND_NE, vece, x, x, t); tcg_gen_or_vec(vece, sat, sat, x); - tcg_temp_free_vec(x); } =20 void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, @@ -4466,7 +4333,6 @@ static void gen_sabd_i32(TCGv_i32 d, TCGv_i32 a, TCGv= _i32 b) tcg_gen_sub_i32(t, a, b); tcg_gen_sub_i32(d, b, a); tcg_gen_movcond_i32(TCG_COND_LT, d, a, b, d, t); - tcg_temp_free_i32(t); } =20 static void gen_sabd_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) @@ -4476,7 +4342,6 @@ static void gen_sabd_i64(TCGv_i64 d, TCGv_i64 a, TCGv= _i64 b) tcg_gen_sub_i64(t, a, b); tcg_gen_sub_i64(d, b, a); tcg_gen_movcond_i64(TCG_COND_LT, d, a, b, d, t); - tcg_temp_free_i64(t); } =20 static void gen_sabd_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) @@ -4486,7 +4351,6 @@ static void gen_sabd_vec(unsigned vece, TCGv_vec d, T= CGv_vec a, TCGv_vec b) tcg_gen_smin_vec(vece, t, a, b); tcg_gen_smax_vec(vece, d, a, b); tcg_gen_sub_vec(vece, d, d, t); - tcg_temp_free_vec(t); } =20 void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, @@ -4526,7 +4390,6 @@ static void gen_uabd_i32(TCGv_i32 d, TCGv_i32 a, TCGv= _i32 b) tcg_gen_sub_i32(t, a, b); tcg_gen_sub_i32(d, b, a); tcg_gen_movcond_i32(TCG_COND_LTU, d, a, b, d, t); - tcg_temp_free_i32(t); } =20 static void gen_uabd_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) @@ -4536,7 +4399,6 @@ static void gen_uabd_i64(TCGv_i64 d, TCGv_i64 a, TCGv= _i64 b) tcg_gen_sub_i64(t, a, b); tcg_gen_sub_i64(d, b, a); tcg_gen_movcond_i64(TCG_COND_LTU, d, a, b, d, t); - tcg_temp_free_i64(t); } =20 static void gen_uabd_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) @@ -4546,7 +4408,6 @@ static void gen_uabd_vec(unsigned vece, TCGv_vec d, T= CGv_vec a, TCGv_vec b) tcg_gen_umin_vec(vece, t, a, b); tcg_gen_umax_vec(vece, d, a, b); tcg_gen_sub_vec(vece, d, d, t); - tcg_temp_free_vec(t); } =20 void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, @@ -4584,7 +4445,6 @@ static void gen_saba_i32(TCGv_i32 d, TCGv_i32 a, TCGv= _i32 b) TCGv_i32 t =3D tcg_temp_new_i32(); gen_sabd_i32(t, a, b); tcg_gen_add_i32(d, d, t); - tcg_temp_free_i32(t); } =20 static void gen_saba_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) @@ -4592,7 +4452,6 @@ static void gen_saba_i64(TCGv_i64 d, TCGv_i64 a, TCGv= _i64 b) TCGv_i64 t =3D tcg_temp_new_i64(); gen_sabd_i64(t, a, b); tcg_gen_add_i64(d, d, t); - tcg_temp_free_i64(t); } =20 static void gen_saba_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) @@ -4600,7 +4459,6 @@ static void gen_saba_vec(unsigned vece, TCGv_vec d, T= CGv_vec a, TCGv_vec b) TCGv_vec t =3D tcg_temp_new_vec_matching(d); gen_sabd_vec(vece, t, a, b); tcg_gen_add_vec(vece, d, d, t); - tcg_temp_free_vec(t); } =20 void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, @@ -4643,7 +4501,6 @@ static void gen_uaba_i32(TCGv_i32 d, TCGv_i32 a, TCGv= _i32 b) TCGv_i32 t =3D tcg_temp_new_i32(); gen_uabd_i32(t, a, b); tcg_gen_add_i32(d, d, t); - tcg_temp_free_i32(t); } =20 static void gen_uaba_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) @@ -4651,7 +4508,6 @@ static void gen_uaba_i64(TCGv_i64 d, TCGv_i64 a, TCGv= _i64 b) TCGv_i64 t =3D tcg_temp_new_i64(); gen_uabd_i64(t, a, b); tcg_gen_add_i64(d, d, t); - tcg_temp_free_i64(t); } =20 static void gen_uaba_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) @@ -4659,7 +4515,6 @@ static void gen_uaba_vec(unsigned vece, TCGv_vec d, T= CGv_vec a, TCGv_vec b) TCGv_vec t =3D tcg_temp_new_vec_matching(d); gen_uabd_vec(vece, t, a, b); tcg_gen_add_vec(vece, d, d, t); - tcg_temp_free_vec(t); } =20 void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, @@ -4766,7 +4621,6 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, t =3D load_cpu_offset(offsetoflow32(CPUARMState, cp15.hstr_el2= )); tcg_gen_andi_i32(t, t, 1u << maskbit); tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label); - tcg_temp_free_i32(t); =20 gen_exception_insn(s, 0, EXCP_UDEF, syndrome); set_disas_label(s, over); @@ -4831,7 +4685,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, case 0: break; case ARM_CP_NOP: - goto exit; + return; case ARM_CP_WFI: if (isread) { unallocated_encoding(s); @@ -4839,7 +4693,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, gen_update_pc(s, curr_insn_len(s)); s->base.is_jmp =3D DISAS_WFI; } - goto exit; + return; default: g_assert_not_reached(); } @@ -4870,7 +4724,6 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, store_reg(s, rt, tmp); tmp =3D tcg_temp_new_i32(); tcg_gen_extrh_i64_i32(tmp, tmp64); - tcg_temp_free_i64(tmp64); store_reg(s, rt2, tmp); } else { TCGv_i32 tmp; @@ -4890,7 +4743,6 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, * the condition codes from the high 4 bits of the value */ gen_set_nzcv(tmp); - tcg_temp_free_i32(tmp); } else { store_reg(s, rt, tmp); } @@ -4899,7 +4751,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, /* Write */ if (ri->type & ARM_CP_CONST) { /* If not forbidden by access permissions, treat as WI */ - goto exit; + return; } =20 if (is64) { @@ -4908,8 +4760,6 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, tmplo =3D load_reg(s, rt); tmphi =3D load_reg(s, rt2); tcg_gen_concat_i32_i64(tmp64, tmplo, tmphi); - tcg_temp_free_i32(tmplo); - tcg_temp_free_i32(tmphi); if (ri->writefn) { if (!tcg_ri) { tcg_ri =3D gen_lookup_cp_reg(key); @@ -4918,7 +4768,6 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, } else { tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset); } - tcg_temp_free_i64(tmp64); } else { TCGv_i32 tmp =3D load_reg(s, rt); if (ri->writefn) { @@ -4926,7 +4775,6 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, tcg_ri =3D gen_lookup_cp_reg(key); } gen_helper_set_cp_reg(cpu_env, tcg_ri, tmp); - tcg_temp_free_i32(tmp); } else { store_cpu_offset(tmp, ri->fieldoffset, 4); } @@ -4953,11 +4801,6 @@ static void do_coproc_insn(DisasContext *s, int cpnu= m, int is64, if (need_exit_tb) { gen_lookup_tb(s); } - - exit: - if (tcg_ri) { - tcg_temp_free_ptr(tcg_ri); - } } =20 /* Decode XScale DSP or iWMMXt insn (in the copro space, cp=3D0 or 1) */ @@ -5002,10 +4845,7 @@ static void gen_addq(DisasContext *s, TCGv_i64 val, = int rlow, int rhigh) tmph =3D load_reg(s, rhigh); tmp =3D tcg_temp_new_i64(); tcg_gen_concat_i32_i64(tmp, tmpl, tmph); - tcg_temp_free_i32(tmpl); - tcg_temp_free_i32(tmph); tcg_gen_add_i64(val, val, tmp); - tcg_temp_free_i64(tmp); } =20 /* Set N and Z flags from hi|lo. */ @@ -5044,15 +4884,12 @@ static void gen_load_exclusive(DisasContext *s, int= rt, int rt2, TCGv taddr =3D gen_aa32_addr(s, addr, opc); =20 tcg_gen_qemu_ld_i64(t64, taddr, get_mem_index(s), opc); - tcg_temp_free(taddr); tcg_gen_mov_i64(cpu_exclusive_val, t64); if (s->be_data =3D=3D MO_BE) { tcg_gen_extr_i64_i32(tmp2, tmp, t64); } else { tcg_gen_extr_i64_i32(tmp, tmp2, t64); } - tcg_temp_free_i64(t64); - store_reg(s, rt2, tmp2); } else { gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), opc); @@ -5089,7 +4926,6 @@ static void gen_store_exclusive(DisasContext *s, int = rd, int rt, int rt2, extaddr =3D tcg_temp_new_i64(); tcg_gen_extu_i32_i64(extaddr, addr); tcg_gen_brcond_i64(TCG_COND_NE, extaddr, cpu_exclusive_addr, fail_labe= l); - tcg_temp_free_i64(extaddr); =20 taddr =3D gen_aa32_addr(s, addr, opc); t0 =3D tcg_temp_new_i32(); @@ -5114,27 +4950,19 @@ static void gen_store_exclusive(DisasContext *s, in= t rd, int rt, int rt2, } else { tcg_gen_concat_i32_i64(n64, t1, t2); } - tcg_temp_free_i32(t2); =20 tcg_gen_atomic_cmpxchg_i64(o64, taddr, cpu_exclusive_val, n64, get_mem_index(s), opc); - tcg_temp_free_i64(n64); =20 tcg_gen_setcond_i64(TCG_COND_NE, o64, o64, cpu_exclusive_val); tcg_gen_extrl_i64_i32(t0, o64); - - tcg_temp_free_i64(o64); } else { t2 =3D tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(t2, cpu_exclusive_val); tcg_gen_atomic_cmpxchg_i32(t0, taddr, t2, t1, get_mem_index(s), op= c); tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t2); - tcg_temp_free_i32(t2); } - tcg_temp_free_i32(t1); - tcg_temp_free(taddr); tcg_gen_mov_i32(cpu_R[rd], t0); - tcg_temp_free_i32(t0); tcg_gen_br(done_label); =20 gen_set_label(fail_label); @@ -5236,11 +5064,9 @@ static void gen_srs(DisasContext *s, tcg_gen_addi_i32(addr, addr, offset); tmp =3D load_reg(s, 14); gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); - tcg_temp_free_i32(tmp); tmp =3D load_cpu_field(spsr); tcg_gen_addi_i32(addr, addr, 4); gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); - tcg_temp_free_i32(tmp); if (writeback) { switch (amode) { case 0: @@ -5261,7 +5087,6 @@ static void gen_srs(DisasContext *s, tcg_gen_addi_i32(addr, addr, offset); gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr); } - tcg_temp_free_i32(addr); s->base.is_jmp =3D DISAS_UPDATE_EXIT; } =20 @@ -5453,7 +5278,6 @@ static bool store_reg_kind(DisasContext *s, int rd, { switch (kind) { case STREG_NONE: - tcg_temp_free_i32(val); return true; case STREG_NORMAL: /* See ALUWritePC: Interworking only from a32 mode. */ @@ -5490,7 +5314,6 @@ static bool op_s_rrr_shi(DisasContext *s, arg_s_rrr_s= hi *a, tmp1 =3D load_reg(s, a->rn); =20 gen(tmp1, tmp1, tmp2); - tcg_temp_free_i32(tmp2); =20 if (logic_cc) { gen_logic_CC(tmp1); @@ -5532,7 +5355,6 @@ static bool op_s_rrr_shr(DisasContext *s, arg_s_rrr_s= hr *a, tmp1 =3D load_reg(s, a->rn); =20 gen(tmp1, tmp1, tmp2); - tcg_temp_free_i32(tmp2); =20 if (logic_cc) { gen_logic_CC(tmp1); @@ -5791,7 +5613,6 @@ static bool do_mve_shl_ri(DisasContext *s, arg_mve_sh= l_ri *a, tcg_gen_extrh_i64_i32(rdahi, rda); store_reg(s, a->rdalo, rdalo); store_reg(s, a->rdahi, rdahi); - tcg_temp_free_i64(rda); =20 return true; } @@ -5875,7 +5696,6 @@ static bool do_mve_shl_rr(DisasContext *s, arg_mve_sh= l_rr *a, WideShiftFn *fn) tcg_gen_extrh_i64_i32(rdahi, rda); store_reg(s, a->rdalo, rdalo); store_reg(s, a->rdahi, rdahi); - tcg_temp_free_i64(rda); =20 return true; } @@ -6003,11 +5823,9 @@ static bool op_mla(DisasContext *s, arg_s_rrrr *a, b= ool add) t1 =3D load_reg(s, a->rn); t2 =3D load_reg(s, a->rm); tcg_gen_mul_i32(t1, t1, t2); - tcg_temp_free_i32(t2); if (add) { t2 =3D load_reg(s, a->ra); tcg_gen_add_i32(t1, t1, t2); - tcg_temp_free_i32(t2); } if (a->s) { gen_logic_CC(t1); @@ -6036,10 +5854,8 @@ static bool trans_MLS(DisasContext *s, arg_MLS *a) t1 =3D load_reg(s, a->rn); t2 =3D load_reg(s, a->rm); tcg_gen_mul_i32(t1, t1, t2); - tcg_temp_free_i32(t2); t2 =3D load_reg(s, a->ra); tcg_gen_sub_i32(t1, t2, t1); - tcg_temp_free_i32(t2); store_reg(s, a->rd, t1); return true; } @@ -6059,8 +5875,6 @@ static bool op_mlal(DisasContext *s, arg_s_rrrr *a, b= ool uns, bool add) t2 =3D load_reg(s, a->ra); t3 =3D load_reg(s, a->rd); tcg_gen_add2_i32(t0, t1, t0, t1, t2, t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } if (a->s) { gen_logicq_cc(t0, t1); @@ -6106,10 +5920,8 @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL *= a) zero =3D tcg_constant_i32(0); t2 =3D load_reg(s, a->ra); tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); - tcg_temp_free_i32(t2); t2 =3D load_reg(s, a->rd); tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); - tcg_temp_free_i32(t2); store_reg(s, a->ra, t0); store_reg(s, a->rd, t1); return true; @@ -6139,7 +5951,6 @@ static bool op_qaddsub(DisasContext *s, arg_rrr *a, b= ool add, bool doub) } else { gen_helper_sub_saturate(t0, cpu_env, t0, t1); } - tcg_temp_free_i32(t1); store_reg(s, a->rd, t0); return true; } @@ -6175,7 +5986,6 @@ static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, t0 =3D load_reg(s, a->rn); t1 =3D load_reg(s, a->rm); gen_mulxy(t0, t1, nt, mt); - tcg_temp_free_i32(t1); =20 switch (add_long) { case 0: @@ -6184,7 +5994,6 @@ static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, case 1: t1 =3D load_reg(s, a->ra); gen_helper_add_setq(t0, cpu_env, t0, t1); - tcg_temp_free_i32(t1); store_reg(s, a->rd, t0); break; case 2: @@ -6194,8 +6003,6 @@ static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, t1 =3D tcg_temp_new_i32(); tcg_gen_sari_i32(t1, t0, 31); tcg_gen_add2_i32(tl, th, tl, th, t0, t1); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); store_reg(s, a->ra, tl); store_reg(s, a->rd, th); break; @@ -6248,11 +6055,9 @@ static bool op_smlawx(DisasContext *s, arg_rrrr *a, = bool add, bool mt) tcg_gen_shli_i32(t1, t1, 16); } tcg_gen_muls2_i32(t0, t1, t0, t1); - tcg_temp_free_i32(t0); if (add) { t0 =3D load_reg(s, a->ra); gen_helper_add_setq(t1, cpu_env, t1, t0); - tcg_temp_free_i32(t0); } store_reg(s, a->rd, t1); return true; @@ -6385,7 +6190,6 @@ static bool op_crc32(DisasContext *s, arg_rrr *a, boo= l c, MemOp sz) } else { gen_helper_crc32(t1, t1, t2, t3); } - tcg_temp_free_i32(t2); store_reg(s, a->rd, t1); return true; } @@ -6484,7 +6288,6 @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7= m *a) addr =3D tcg_constant_i32((a->mask << 10) | a->sysm); reg =3D load_reg(s, a->rn); gen_helper_v7m_msr(cpu_env, addr, reg); - tcg_temp_free_i32(reg); /* If we wrote to CONTROL, the EL might have changed */ gen_rebuild_hflags(s, true); gen_lookup_tb(s); @@ -6694,7 +6497,6 @@ static bool trans_TT(DisasContext *s, arg_TT *a) addr =3D load_reg(s, a->rn); tmp =3D tcg_temp_new_i32(); gen_helper_v7m_tt(tmp, cpu_env, addr, tcg_constant_i32((a->A << 1) | a= ->T)); - tcg_temp_free_i32(addr); store_reg(s, a->rd, tmp); return true; } @@ -6735,7 +6537,6 @@ static TCGv_i32 op_addr_rr_pre(DisasContext *s, arg_l= dst_rr *a) } else { tcg_gen_sub_i32(addr, addr, ofs); } - tcg_temp_free_i32(ofs); } return addr; } @@ -6751,9 +6552,7 @@ static void op_addr_rr_post(DisasContext *s, arg_ldst= _rr *a, } else { tcg_gen_sub_i32(addr, addr, ofs); } - tcg_temp_free_i32(ofs); } else if (!a->w) { - tcg_temp_free_i32(addr); return; } tcg_gen_addi_i32(addr, addr, address_offset); @@ -6800,7 +6599,6 @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr = *a, tmp =3D load_reg(s, a->rt); gen_aa32_st_i32(s, tmp, addr, mem_idx, mop); disas_set_da_iss(s, mop, issinfo); - tcg_temp_free_i32(tmp); =20 op_addr_rr_post(s, a, addr, 0); return true; @@ -6851,13 +6649,11 @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst= _rr *a) =20 tmp =3D load_reg(s, a->rt); gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); - tcg_temp_free_i32(tmp); =20 tcg_gen_addi_i32(addr, addr, 4); =20 tmp =3D load_reg(s, a->rt + 1); gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); - tcg_temp_free_i32(tmp); =20 op_addr_rr_post(s, a, addr, -4); return true; @@ -6886,7 +6682,6 @@ static TCGv_i32 op_addr_ri_pre(DisasContext *s, arg_l= dst_ri *a) TCGv_i32 newsp =3D tcg_temp_new_i32(); tcg_gen_addi_i32(newsp, cpu_R[13], ofs); gen_helper_v8m_stackcheck(cpu_env, newsp); - tcg_temp_free_i32(newsp); } else { gen_helper_v8m_stackcheck(cpu_env, cpu_R[13]); } @@ -6905,7 +6700,6 @@ static void op_addr_ri_post(DisasContext *s, arg_ldst= _ri *a, address_offset -=3D a->imm; } } else if (!a->w) { - tcg_temp_free_i32(addr); return; } tcg_gen_addi_i32(addr, addr, address_offset); @@ -6952,7 +6746,6 @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri = *a, tmp =3D load_reg(s, a->rt); gen_aa32_st_i32(s, tmp, addr, mem_idx, mop); disas_set_da_iss(s, mop, issinfo); - tcg_temp_free_i32(tmp); =20 op_addr_ri_post(s, a, addr, 0); return true; @@ -7006,13 +6799,11 @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri= *a, int rt2) =20 tmp =3D load_reg(s, a->rt); gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); - tcg_temp_free_i32(tmp); =20 tcg_gen_addi_i32(addr, addr, 4); =20 tmp =3D load_reg(s, rt2); gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); - tcg_temp_free_i32(tmp); =20 op_addr_ri_post(s, a, addr, -4); return true; @@ -7077,11 +6868,9 @@ static bool op_swp(DisasContext *s, arg_SWP *a, MemO= p opc) opc |=3D s->be_data; addr =3D load_reg(s, a->rn); taddr =3D gen_aa32_addr(s, addr, opc); - tcg_temp_free_i32(addr); =20 tmp =3D load_reg(s, a->rt2); tcg_gen_atomic_xchg_i32(tmp, taddr, tmp, get_mem_index(s), opc); - tcg_temp_free(taddr); =20 store_reg(s, a->rt, tmp); return true; @@ -7128,7 +6917,6 @@ static bool op_strex(DisasContext *s, arg_STREX *a, M= emOp mop, bool rel) tcg_gen_addi_i32(addr, addr, a->imm); =20 gen_store_exclusive(s, a->rd, a->rt, a->rt2, addr, mop); - tcg_temp_free_i32(addr); return true; } =20 @@ -7240,8 +7028,6 @@ static bool op_stl(DisasContext *s, arg_STL *a, MemOp= mop) gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | MO_ALIGN); disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite); =20 - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(addr); return true; } =20 @@ -7281,7 +7067,6 @@ static bool op_ldrex(DisasContext *s, arg_LDREX *a, M= emOp mop, bool acq) tcg_gen_addi_i32(addr, addr, a->imm); =20 gen_load_exclusive(s, a->rt, a->rt2, addr, mop); - tcg_temp_free_i32(addr); =20 if (acq) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -7395,7 +7180,6 @@ static bool op_lda(DisasContext *s, arg_LDA *a, MemOp= mop) tmp =3D tcg_temp_new_i32(); gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | MO_ALIGN); disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel); - tcg_temp_free_i32(addr); =20 store_reg(s, a->rt, tmp); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); @@ -7432,11 +7216,9 @@ static bool trans_USADA8(DisasContext *s, arg_USADA8= *a) t1 =3D load_reg(s, a->rn); t2 =3D load_reg(s, a->rm); gen_helper_usad8(t1, t1, t2); - tcg_temp_free_i32(t2); if (a->ra !=3D 15) { t2 =3D load_reg(s, a->ra); tcg_gen_add_i32(t1, t1, t2); - tcg_temp_free_i32(t2); } store_reg(s, a->rd, t1); return true; @@ -7503,7 +7285,6 @@ static bool trans_BFCI(DisasContext *s, arg_BFCI *a) if (width !=3D 32) { TCGv_i32 tmp2 =3D load_reg(s, a->rd); tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width); - tcg_temp_free_i32(tmp2); } store_reg(s, a->rd, tmp); return true; @@ -7535,7 +7316,6 @@ static bool op_par_addsub(DisasContext *s, arg_rrr *a, =20 gen(t0, t0, t1); =20 - tcg_temp_free_i32(t1); store_reg(s, a->rd, t0); return true; } @@ -7560,8 +7340,6 @@ static bool op_par_addsub_ge(DisasContext *s, arg_rrr= *a, tcg_gen_addi_ptr(ge, cpu_env, offsetof(CPUARMState, GE)); gen(t0, t0, t1, ge); =20 - tcg_temp_free_ptr(ge); - tcg_temp_free_i32(t1); store_reg(s, a->rd, t0); return true; } @@ -7652,7 +7430,6 @@ static bool trans_PKH(DisasContext *s, arg_PKH *a) tcg_gen_shli_i32(tm, tm, shift); tcg_gen_deposit_i32(tn, tm, tn, 0, 16); } - tcg_temp_free_i32(tm); store_reg(s, a->rd, tn); return true; } @@ -7727,7 +7504,6 @@ static bool op_xta(DisasContext *s, arg_rrr_rot *a, if (a->rn !=3D 15) { TCGv_i32 tmp2 =3D load_reg(s, a->rn); gen_add(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); } store_reg(s, a->rd, tmp); return true; @@ -7784,8 +7560,6 @@ static bool trans_SEL(DisasContext *s, arg_rrr *a) t3 =3D tcg_temp_new_i32(); tcg_gen_ld_i32(t3, cpu_env, offsetof(CPUARMState, GE)); gen_helper_sel_flags(t1, t3, t1, t2); - tcg_temp_free_i32(t3); - tcg_temp_free_i32(t2); store_reg(s, a->rd, t1); return true; } @@ -7859,17 +7633,14 @@ static bool op_smlad(DisasContext *s, arg_rrrr *a, = bool m_swap, bool sub) * addition of Ra. */ tcg_gen_sub_i32(t1, t1, t2); - tcg_temp_free_i32(t2); =20 if (a->ra !=3D 15) { t2 =3D load_reg(s, a->ra); gen_helper_add_setq(t1, cpu_env, t1, t2); - tcg_temp_free_i32(t2); } } else if (a->ra =3D=3D 15) { /* Single saturation-checking addition */ gen_helper_add_setq(t1, cpu_env, t1, t2); - tcg_temp_free_i32(t2); } else { /* * We need to add the products and Ra together and then @@ -7889,10 +7660,8 @@ static bool op_smlad(DisasContext *s, arg_rrrr *a, b= ool m_swap, bool sub) load_reg_var(s, t2, a->ra); tcg_gen_ext_i32_i64(q64, t2); tcg_gen_add_i64(p64, p64, q64); - tcg_temp_free_i64(q64); =20 tcg_gen_extr_i64_i32(t1, t2, p64); - tcg_temp_free_i64(p64); /* * t1 is the low half of the result which goes into Rd. * We have overflow and must set Q if the high half (t2) @@ -7904,8 +7673,6 @@ static bool op_smlad(DisasContext *s, arg_rrrr *a, bo= ol m_swap, bool sub) one =3D tcg_constant_i32(1); tcg_gen_movcond_i32(TCG_COND_NE, qf, t2, t3, one, qf); store_cpu_field(qf, QF); - tcg_temp_free_i32(t3); - tcg_temp_free_i32(t2); } store_reg(s, a->rd, t1); return true; @@ -7951,19 +7718,15 @@ static bool op_smlald(DisasContext *s, arg_rrrr *a,= bool m_swap, bool sub) l2 =3D tcg_temp_new_i64(); tcg_gen_ext_i32_i64(l1, t1); tcg_gen_ext_i32_i64(l2, t2); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); =20 if (sub) { tcg_gen_sub_i64(l1, l1, l2); } else { tcg_gen_add_i64(l1, l1, l2); } - tcg_temp_free_i64(l2); =20 gen_addq(s, l1, a->ra, a->rd); gen_storeq_reg(s, a->ra, a->rd, l1); - tcg_temp_free_i64(l1); return true; } =20 @@ -8013,7 +7776,6 @@ static bool op_smmla(DisasContext *s, arg_rrrr *a, bo= ol round, bool sub) } else { tcg_gen_add_i32(t1, t1, t3); } - tcg_temp_free_i32(t3); } if (round) { /* @@ -8023,7 +7785,6 @@ static bool op_smmla(DisasContext *s, arg_rrrr *a, bo= ol round, bool sub) tcg_gen_shri_i32(t2, t2, 31); tcg_gen_add_i32(t1, t1, t2); } - tcg_temp_free_i32(t2); store_reg(s, a->rd, t1); return true; } @@ -8065,7 +7826,6 @@ static bool op_div(DisasContext *s, arg_rrr *a, bool = u) } else { gen_helper_sdiv(t1, cpu_env, t1, t2); } - tcg_temp_free_i32(t2); store_reg(s, a->rd, t1); return true; } @@ -8137,8 +7897,6 @@ static void op_addr_block_post(DisasContext *s, arg_l= dst_block *a, tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); } store_reg(s, a->rn, addr); - } else { - tcg_temp_free_i32(addr); } } =20 @@ -8181,7 +7939,6 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a= , int min_n) tmp =3D load_reg(s, i); } gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); - tcg_temp_free_i32(tmp); =20 /* No need to add after the last transfer. */ if (++j !=3D n) { @@ -8261,7 +8018,6 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a= , int min_n) gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); if (user) { gen_helper_set_user_reg(cpu_env, tcg_constant_i32(i), tmp); - tcg_temp_free_i32(tmp); } else if (i =3D=3D a->rn) { loaded_var =3D tmp; loaded_base =3D true; @@ -8291,7 +8047,6 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a= , int min_n) gen_io_start(); } gen_helper_cpsr_write_eret(cpu_env, tmp); - tcg_temp_free_i32(tmp); /* Must exit loop to check un-masked IRQs */ s->base.is_jmp =3D DISAS_EXIT; } @@ -8657,7 +8412,6 @@ static bool trans_LE(DisasContext *s, arg_LE *a) DisasLabel skipexc =3D gen_disas_label(s); tmp =3D load_cpu_field(v7m.ltpsize); tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc.label); - tcg_temp_free_i32(tmp); gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized()); set_disas_label(s, skipexc); } @@ -8687,12 +8441,10 @@ static bool trans_LE(DisasContext *s, arg_LE *a) TCGv_i32 ltpsize =3D load_cpu_field(v7m.ltpsize); tcg_gen_sub_i32(decr, tcg_constant_i32(4), ltpsize); tcg_gen_shl_i32(decr, tcg_constant_i32(1), decr); - tcg_temp_free_i32(ltpsize); =20 tcg_gen_brcond_i32(TCG_COND_LEU, cpu_R[14], decr, loopend.label); =20 tcg_gen_sub_i32(cpu_R[14], cpu_R[14], decr); - tcg_temp_free_i32(decr); } /* Jump back to the loop start */ gen_jmp(s, jmp_diff(s, -a->imm)); @@ -8756,8 +8508,6 @@ static bool trans_VCTP(DisasContext *s, arg_VCTP *a) masklen, tcg_constant_i32(1 << (4 - a->size)), rn_shifted, tcg_constant_i32(16)); gen_helper_mve_vctp(cpu_env, masklen); - tcg_temp_free_i32(masklen); - tcg_temp_free_i32(rn_shifted); /* This insn updates predication bits */ s->base.is_jmp =3D DISAS_UPDATE_NOCHAIN; mve_update_eci(s); @@ -8780,7 +8530,6 @@ static bool op_tbranch(DisasContext *s, arg_tbranch *= a, bool half) tcg_gen_add_i32(tmp, tmp, tmp); gen_pc_plus_diff(s, addr, jmp_diff(s, 0)); tcg_gen_add_i32(tmp, tmp, addr); - tcg_temp_free_i32(addr); store_reg(s, 15, tmp); return true; } @@ -8802,7 +8551,6 @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a) arm_gen_condlabel(s); tcg_gen_brcondi_i32(a->nz ? TCG_COND_EQ : TCG_COND_NE, tmp, 0, s->condlabel.label); - tcg_temp_free_i32(tmp); gen_jmp(s, jmp_diff(s, a->imm)); return true; } @@ -8869,8 +8617,6 @@ static bool trans_RFE(DisasContext *s, arg_RFE *a) /* Base writeback. */ tcg_gen_addi_i32(addr, addr, post_offset[a->pu]); store_reg(s, a->rn, addr); - } else { - tcg_temp_free_i32(addr); } gen_rfe(s, t1, t2); return true; @@ -9114,8 +8860,6 @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a) tcg_gen_movcond_i32(c.cond, rn, c.value, zero, rn, rm); =20 store_reg(s, a->rd, rn); - tcg_temp_free_i32(rm); - return true; } =20 --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677475638; cv=none; d=zohomail.com; s=zohoarc; b=LvGJv3UtQlcA+jkDTkXi9uhB6S3I8Hgm1Z0RLJeMU7uHpdhgzZ+/MGLp2x3PpeOml1SSFL6RQF65oHLxT9ghlb37iR541XmFscRim9GJ7y+vxS3ECkA3ag4jqP06qdAXykQimNfzHfMzDC5D3fbwlEJ1wLajbPbwhRjn34s7kHI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677475638; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hocy2mGz2CCTt4Bq9qJMXd0ON/jxXgLLJ1IYsbDvM70=; b=gGDpIAbMh/5vumNOLYBqGwM2tSxw1KjWuHstQKHNcPL3Z8jBt22mfROzPiTxBUU4Wih+kVQdQQJPNLdto5xt5+Zhtcu6gzHYMHFCIdpMBfzcMN+loSSrkSTp561IVhxgYDtAHTBaBLgklX8frLBZPsAOZAUWr+x1PAghHoEfPJk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167747563805666.6785831834352; Sun, 26 Feb 2023 21:27:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW1C-0006sC-4H; Mon, 27 Feb 2023 00:25:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW13-0006jo-HX for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:25:38 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW0y-00079b-OE for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:25:37 -0500 Received: by mail-pl1-x62c.google.com with SMTP id i10so5510285plr.9 for ; Sun, 26 Feb 2023 21:25:29 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.25.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:25:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hocy2mGz2CCTt4Bq9qJMXd0ON/jxXgLLJ1IYsbDvM70=; b=Z3qB62jRnsosfZFFSnFsygvQwHDESxfA6NXeL/SrCxOH4nlJPz/sQnIq5WdwrbKbcq YallIXZuELjIHIiN9/0lt+SJdGu8U1NCnplKGkWm/kfYSIAEaE169XiEEnjfsbN2w3Lu zUsEirC+QmGVRnWIIjRSLzoWck4KIpiVOlhgs6TihYhii19HqJ9JOUl2HTGU4mc/nBkL GghIFUJnHhk4Aj87GYp3Rm3v+MEQseSGwOVmsJ2tfFmZkGtgyOWDbUr2/fDhXuPoKiYw mnwG+j4WfyubHZG9qw22iKv79dI97857/t85UVRCaEUIw0z6RQJXiJeawuAKRPLleO8z rCSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hocy2mGz2CCTt4Bq9qJMXd0ON/jxXgLLJ1IYsbDvM70=; b=OMYEwZ8WV816zbd5DwkqlOYdiA3t906xQsBCWS/4oHTMLwYOCP2tm8VGGI7grtdtny xqJ4ZLlrF1LOT/HTEzCxL1l9Oe/MOmy9QgRbu+l8tWk34OpZl/jniutO1W0Ewoe9QNOP 6++E3PfxHT8im22hdWzi7kQh07L59uCOV6l/+ePysBOCwQilBgrTqZR+Z03byGFf/m4M MRVYZeVSkRh+/ubmDYSJtn+lGca+yuF02aUuIXKm1K63xaUceyaa+jLwZRTgwwxb+XuR WQ34mLyaW8tiLbCW28btpL5LEMvQUuL6hNgk3Ges2NGoRMwmmnjX1DZTAGZCd27OzZGN InVg== X-Gm-Message-State: AO0yUKXtPapRC6ER2pz/L0BmeQyYDurbEc8GZFMkVRL51vWEuPpyrxex PvLq9IQmM9KE1OPplgg08xKzFOZQ5BrKQlf4ogA= X-Google-Smtp-Source: AK7set8kol9HF9Xbb7B3wZ0EdzlGrvHSIx3cExvKYnzgr6V7Zxfhwi5c1uYhkK53No6Q8Eby3YXoCg== X-Received: by 2002:a17:903:41cd:b0:199:10d2:b9da with SMTP id u13-20020a17090341cd00b0019910d2b9damr24884092ple.58.1677475529538; Sun, 26 Feb 2023 21:25:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 07/76] target/arm: Drop DisasContext.tmp_a64 Date: Sun, 26 Feb 2023 19:23:56 -1000 Message-Id: <20230227052505.352889-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475639889100003 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries, therefore there's no need to record temps for later freeing. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/arm/translate.h | 3 --- target/arm/translate-a64.c | 25 +------------------------ 2 files changed, 1 insertion(+), 27 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index db29e8d799..d7fdbc1e3e 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -149,9 +149,6 @@ typedef struct DisasContext { int c15_cpar; /* TCG op of the current insn_start. */ TCGOp *insn_start; -#define TMP_A64_MAX 16 - int tmp_a64_count; - TCGv_i64 tmp_a64[TMP_A64_MAX]; } DisasContext; =20 typedef struct DisasCompare { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2a0bba3815..98d1bee5d5 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -408,27 +408,9 @@ static void gen_goto_tb(DisasContext *s, int n, int64_= t diff) } } =20 -static void init_tmp_a64_array(DisasContext *s) -{ -#ifdef CONFIG_DEBUG_TCG - memset(s->tmp_a64, 0, sizeof(s->tmp_a64)); -#endif - s->tmp_a64_count =3D 0; -} - -static void free_tmp_a64(DisasContext *s) -{ - int i; - for (i =3D 0; i < s->tmp_a64_count; i++) { - tcg_temp_free_i64(s->tmp_a64[i]); - } - init_tmp_a64_array(s); -} - TCGv_i64 new_tmp_a64(DisasContext *s) { - assert(s->tmp_a64_count < TMP_A64_MAX); - return s->tmp_a64[s->tmp_a64_count++] =3D tcg_temp_new_i64(); + return tcg_temp_new_i64(); } =20 TCGv_i64 new_tmp_a64_zero(DisasContext *s) @@ -14781,8 +14763,6 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, bound =3D 1; } dc->base.max_insns =3D MIN(dc->base.max_insns, bound); - - init_tmp_a64_array(dc); } =20 static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu) @@ -14938,9 +14918,6 @@ static void aarch64_tr_translate_insn(DisasContextB= ase *dcbase, CPUState *cpu) break; } =20 - /* if we allocated any temporaries, free them here */ - free_tmp_a64(s); - /* * After execution of most insns, btype is reset to 0. * Note that we set btype =3D=3D -1 when the insn sets btype. --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677475614; cv=none; d=zohomail.com; s=zohoarc; b=fgnIrtxWt0+6zZYASEAomByJa14Lzy8c31mzH63Pytmin2nWM4g0We/muZhWpMACvmPd0VL5syuk2xmil8sDknV2BLa43AIIvQvl+OrLI5wsfMCI9tn7yQlLaTRmdotnNr8ntAywgou8vvgBm3IrfHezois9bCrJh1E01XZCH4E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677475614; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=P8j3IPZTVyN+dZUsOhoCKYp0bksAGUAJsCP3IzISZ8Y=; b=ilz3CruIQWT7N62+pshnRvLWxYUNGNuOd7w3OhKcwIoWTNRR9BbYFjS+Tzpy7+YKxYqERyZGFt7/JLsPmsq7qcvrAWl6T1SY1BUFOZTK+13BVfP2oIW8MeRdCDQBpM9y5qbN/3xsWQUGEEMk7aVbKSQ6KuWYwy2obDlnqffZVOc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677475614599446.27845314283024; Sun, 26 Feb 2023 21:26:54 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW1F-0006yr-HT; Mon, 27 Feb 2023 00:25:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW18-0006mk-2l for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:25:42 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW13-0007BQ-AI for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:25:41 -0500 Received: by mail-pl1-x629.google.com with SMTP id i3so5529345plg.6 for ; Sun, 26 Feb 2023 21:25:32 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.25.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:25:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P8j3IPZTVyN+dZUsOhoCKYp0bksAGUAJsCP3IzISZ8Y=; b=RwHqMSXBs2NnX6KE/iDfjScxX75nxc703+JON3Zu5OtWd+FH3GYhShlwYzbkLgSqSA CLxRDQHFwfYWaPvxRQfOMTwIpIh6XVM/jG9EeNWtzYE5wOB7faIi57jL7wcnJX+FLTwp v4LAQsHC2ly5OvdRIJazA9p0NUSBlx+EbKEQbzjxD3APnKRc9Jac26+EUOYV+BwlN4PQ tU+CjnV0ipiv+5uHqR1An/BelORrejLY7S3CGBsfuDlDXvj0TzkEdMtmRzn8Nn5otmk7 5le50ltqTpXS0tg6MnvguseA3zS9fxpzB6KJPFEMFaJSMN9A5ZHne4iZgb5+vSFRePrU b/Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P8j3IPZTVyN+dZUsOhoCKYp0bksAGUAJsCP3IzISZ8Y=; b=SVc2u5Yx/WxOmhF19MAqW8J0tL50VlcQpScKzhWXLOb9Pe4yRXIXwLPMrTnRmMmalA 3Oe4XKwqFGVAvg6PXvancE0IhLT9+r9FNU2//Z/89CVCjeI7nPfxAbs/yumgwTn13CFb ztRW5+3l4XIY9pzRScrsQ0Oa9qInoLDyDiCiwkO4PHkflNW6+GPwHNhPCep5EUx8ohaG zvUrPL28M5oYSlTvCOkTk+uwlXSotFxy6t8RPDTcKh0jtaTXgF4hIvxcCRJk/kNXRol2 4ddcNkI1z7eIwQlX7Jtde/vJq0RqNqhWiaiie4CR7kuBgVhDJjBzE4yNbIivFuzKZTdH tcGQ== X-Gm-Message-State: AO0yUKU+87MRPx+p9NV/X9wE9B2Tw/jgYlVk5w5se5Fh+L6gdsXtZHdY NHEg1w8oobYcSr6BlvTM4TlXOoqueypAmnNSHx0= X-Google-Smtp-Source: AK7set+Ls4FwnENuYGBxgs8sWzVN9/RkiwPjgkUSvYG73mh2Fd1c6oh+ot02JvyTqN1HmTOuC0FxSg== X-Received: by 2002:a17:903:28c7:b0:19d:297:f300 with SMTP id kv7-20020a17090328c700b0019d0297f300mr3568950plb.45.1677475532203; Sun, 26 Feb 2023 21:25:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 08/76] target/arm: Drop new_tmp_a64 Date: Sun, 26 Feb 2023 19:23:57 -1000 Message-Id: <20230227052505.352889-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475616068100002 Content-Type: text/plain; charset="utf-8" This is now a simple wrapper for tcg_temp_new_i64. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/arm/translate-a64.h | 1 - target/arm/translate-a64.c | 45 +++++++++++++++++--------------------- target/arm/translate-sve.c | 20 ++++++++--------- 3 files changed, 30 insertions(+), 36 deletions(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index ca24c39dbe..8ac126991f 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -18,7 +18,6 @@ #ifndef TARGET_ARM_TRANSLATE_A64_H #define TARGET_ARM_TRANSLATE_A64_H =20 -TCGv_i64 new_tmp_a64(DisasContext *s); TCGv_i64 new_tmp_a64_zero(DisasContext *s); TCGv_i64 cpu_reg(DisasContext *s, int reg); TCGv_i64 cpu_reg_sp(DisasContext *s, int reg); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 98d1bee5d5..04872d9925 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -224,7 +224,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 sr= c) =20 TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) { - TCGv_i64 clean =3D new_tmp_a64(s); + TCGv_i64 clean =3D tcg_temp_new_i64(); #ifdef CONFIG_USER_ONLY gen_top_byte_ignore(s, clean, addr, s->tbid); #else @@ -269,7 +269,7 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, = TCGv_i64 addr, desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << log2_size) - 1); =20 - ret =3D new_tmp_a64(s); + ret =3D tcg_temp_new_i64(); gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr); =20 return ret; @@ -300,7 +300,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr,= bool is_write, desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, size - 1); =20 - ret =3D new_tmp_a64(s); + ret =3D tcg_temp_new_i64(); gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr); =20 return ret; @@ -408,14 +408,9 @@ static void gen_goto_tb(DisasContext *s, int n, int64_= t diff) } } =20 -TCGv_i64 new_tmp_a64(DisasContext *s) -{ - return tcg_temp_new_i64(); -} - TCGv_i64 new_tmp_a64_zero(DisasContext *s) { - TCGv_i64 t =3D new_tmp_a64(s); + TCGv_i64 t =3D tcg_temp_new_i64(); tcg_gen_movi_i64(t, 0); return t; } @@ -456,7 +451,7 @@ TCGv_i64 cpu_reg_sp(DisasContext *s, int reg) */ TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf) { - TCGv_i64 v =3D new_tmp_a64(s); + TCGv_i64 v =3D tcg_temp_new_i64(); if (reg !=3D 31) { if (sf) { tcg_gen_mov_i64(v, cpu_X[reg]); @@ -471,7 +466,7 @@ TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf) =20 TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf) { - TCGv_i64 v =3D new_tmp_a64(s); + TCGv_i64 v =3D tcg_temp_new_i64(); if (sf) { tcg_gen_mov_i64(v, cpu_X[reg]); } else { @@ -1984,7 +1979,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); =20 - tcg_rt =3D new_tmp_a64(s); + tcg_rt =3D tcg_temp_new_i64(); gen_helper_mte_check_zva(tcg_rt, cpu_env, tcg_constant_i32(desc), cpu_reg(s, rt= )); } else { @@ -2293,7 +2288,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3= 2_t insn) modifier =3D new_tmp_a64_zero(s); } if (s->pauth_active) { - dst =3D new_tmp_a64(s); + dst =3D tcg_temp_new_i64(); if (op3 =3D=3D 2) { gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifie= r); } else { @@ -2311,7 +2306,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3= 2_t insn) if (opc =3D=3D 1) { TCGv_i64 lr =3D cpu_reg(s, 30); if (dst =3D=3D lr) { - TCGv_i64 tmp =3D new_tmp_a64(s); + TCGv_i64 tmp =3D tcg_temp_new_i64(); tcg_gen_mov_i64(tmp, dst); dst =3D tmp; } @@ -2330,7 +2325,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3= 2_t insn) } btype_mod =3D opc & 1; if (s->pauth_active) { - dst =3D new_tmp_a64(s); + dst =3D tcg_temp_new_i64(); modifier =3D cpu_reg_sp(s, op4); if (op3 =3D=3D 2) { gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier); @@ -2344,7 +2339,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3= 2_t insn) if (opc =3D=3D 9) { TCGv_i64 lr =3D cpu_reg(s, 30); if (dst =3D=3D lr) { - TCGv_i64 tmp =3D new_tmp_a64(s); + TCGv_i64 tmp =3D tcg_temp_new_i64(); tcg_gen_mov_i64(tmp, dst); dst =3D tmp; } @@ -2912,7 +2907,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) =20 tcg_rt =3D cpu_reg(s, rt); =20 - clean_addr =3D new_tmp_a64(s); + clean_addr =3D tcg_temp_new_i64(); gen_pc_plus_diff(s, clean_addr, imm); if (is_vector) { do_fp_ld(s, rt, clean_addr, size); @@ -5167,7 +5162,7 @@ static void disas_adc_sbc(DisasContext *s, uint32_t i= nsn) tcg_rn =3D cpu_reg(s, rn); =20 if (op) { - tcg_y =3D new_tmp_a64(s); + tcg_y =3D tcg_temp_new_i64(); tcg_gen_not_i64(tcg_y, cpu_reg(s, rm)); } else { tcg_y =3D cpu_reg(s, rm); @@ -5295,7 +5290,7 @@ static void disas_cc(DisasContext *s, uint32_t insn) =20 /* Load the arguments for the new comparison. */ if (is_imm) { - tcg_y =3D new_tmp_a64(s); + tcg_y =3D tcg_temp_new_i64(); tcg_gen_movi_i64(tcg_y, y); } else { tcg_y =3D cpu_reg(s, y); @@ -5724,8 +5719,8 @@ static void handle_div(DisasContext *s, bool is_signe= d, unsigned int sf, tcg_rd =3D cpu_reg(s, rd); =20 if (!sf && is_signed) { - tcg_n =3D new_tmp_a64(s); - tcg_m =3D new_tmp_a64(s); + tcg_n =3D tcg_temp_new_i64(); + tcg_m =3D tcg_temp_new_i64(); tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn)); tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm)); } else { @@ -5790,7 +5785,7 @@ static void handle_crc32(DisasContext *s, default: g_assert_not_reached(); } - tcg_val =3D new_tmp_a64(s); + tcg_val =3D tcg_temp_new_i64(); tcg_gen_andi_i64(tcg_val, cpu_reg(s, rm), mask); } =20 @@ -7062,7 +7057,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, i= nt rn, int opcode, if (itof) { TCGv_i64 tcg_int =3D cpu_reg(s, rn); if (!sf) { - TCGv_i64 tcg_extend =3D new_tmp_a64(s); + TCGv_i64 tcg_extend =3D tcg_temp_new_i64(); =20 if (is_signed) { tcg_gen_ext32s_i64(tcg_extend, tcg_int); @@ -10707,8 +10702,8 @@ static void handle_vec_simd_wshli(DisasContext *s, = bool is_q, bool is_u, int dsize =3D 64; int esize =3D 8 << size; int elements =3D dsize/esize; - TCGv_i64 tcg_rn =3D new_tmp_a64(s); - TCGv_i64 tcg_rd =3D new_tmp_a64(s); + TCGv_i64 tcg_rn =3D tcg_temp_new_i64(); + TCGv_i64 tcg_rd =3D tcg_temp_new_i64(); int i; =20 if (size >=3D 3) { diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 718a5bce1b..2f607a355e 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4721,7 +4721,7 @@ static bool trans_LD_zprr(DisasContext *s, arg_rprr_l= oad *a) return false; } if (sve_access_check(s)) { - TCGv_i64 addr =3D new_tmp_a64(s); + TCGv_i64 addr =3D tcg_temp_new_i64(); tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); do_ld_zpa(s, a->rd, a->pg, addr, a->dtype, a->nreg); @@ -4737,7 +4737,7 @@ static bool trans_LD_zpri(DisasContext *s, arg_rpri_l= oad *a) if (sve_access_check(s)) { int vsz =3D vec_full_reg_size(s); int elements =3D vsz >> dtype_esz[a->dtype]; - TCGv_i64 addr =3D new_tmp_a64(s); + TCGv_i64 addr =3D tcg_temp_new_i64(); =20 tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), (a->imm * elements * (a->nreg + 1)) @@ -4840,7 +4840,7 @@ static bool trans_LDFF1_zprr(DisasContext *s, arg_rpr= r_load *a) } s->is_nonstreaming =3D true; if (sve_access_check(s)) { - TCGv_i64 addr =3D new_tmp_a64(s); + TCGv_i64 addr =3D tcg_temp_new_i64(); tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 1, false, @@ -4945,7 +4945,7 @@ static bool trans_LDNF1_zpri(DisasContext *s, arg_rpr= i_load *a) int vsz =3D vec_full_reg_size(s); int elements =3D vsz >> dtype_esz[a->dtype]; int off =3D (a->imm * elements) << dtype_msz(a->dtype); - TCGv_i64 addr =3D new_tmp_a64(s); + TCGv_i64 addr =3D tcg_temp_new_i64(); =20 tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), off); do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 1, false, @@ -5003,7 +5003,7 @@ static bool trans_LD1RQ_zprr(DisasContext *s, arg_rpr= r_load *a) } if (sve_access_check(s)) { int msz =3D dtype_msz(a->dtype); - TCGv_i64 addr =3D new_tmp_a64(s); + TCGv_i64 addr =3D tcg_temp_new_i64(); tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), msz); tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); do_ldrq(s, a->rd, a->pg, addr, a->dtype); @@ -5017,7 +5017,7 @@ static bool trans_LD1RQ_zpri(DisasContext *s, arg_rpr= i_load *a) return false; } if (sve_access_check(s)) { - TCGv_i64 addr =3D new_tmp_a64(s); + TCGv_i64 addr =3D tcg_temp_new_i64(); tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 16); do_ldrq(s, a->rd, a->pg, addr, a->dtype); } @@ -5097,7 +5097,7 @@ static bool trans_LD1RO_zprr(DisasContext *s, arg_rpr= r_load *a) } s->is_nonstreaming =3D true; if (sve_access_check(s)) { - TCGv_i64 addr =3D new_tmp_a64(s); + TCGv_i64 addr =3D tcg_temp_new_i64(); tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); do_ldro(s, a->rd, a->pg, addr, a->dtype); @@ -5112,7 +5112,7 @@ static bool trans_LD1RO_zpri(DisasContext *s, arg_rpr= i_load *a) } s->is_nonstreaming =3D true; if (sve_access_check(s)) { - TCGv_i64 addr =3D new_tmp_a64(s); + TCGv_i64 addr =3D tcg_temp_new_i64(); tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 32); do_ldro(s, a->rd, a->pg, addr, a->dtype); } @@ -5307,7 +5307,7 @@ static bool trans_ST_zprr(DisasContext *s, arg_rprr_s= tore *a) return false; } if (sve_access_check(s)) { - TCGv_i64 addr =3D new_tmp_a64(s); + TCGv_i64 addr =3D tcg_temp_new_i64(); tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->msz); tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); do_st_zpa(s, a->rd, a->pg, addr, a->msz, a->esz, a->nreg); @@ -5326,7 +5326,7 @@ static bool trans_ST_zpri(DisasContext *s, arg_rpri_s= tore *a) if (sve_access_check(s)) { int vsz =3D vec_full_reg_size(s); int elements =3D vsz >> a->esz; - TCGv_i64 addr =3D new_tmp_a64(s); + TCGv_i64 addr =3D tcg_temp_new_i64(); =20 tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), (a->imm * elements * (a->nreg + 1)) << a->msz); --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.25.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:25:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7rXk1sKSqinlJBrFL9P/VMnnxUDcgz/M8L7XKzjlIwM=; b=iBUO0I6K2axChAXmnL7RumH5ABIuO0oC17d4GVO+ll8rulb28mqJaTerL47dYFuMoA fggRX5zjBgu6ItGme89+8YqayZgGluTIL9aOG+zzXAigh1jq3wbxLC7QhT9gdTua5jCa 0ONU8ofUlZf0MFlXd/+GILBI6Mv8iwSTjk4jgsIkWCpBb8OQtHyoH7xD3OxTehTQzpMw 23bruLMPbV7mNIbTQBsURTRnzLSN+iS1366mHbkv0QgJZZoaPkrIznK47gtZMi5BBYs/ yzd1Z4IBv7NEck24yaTOxyPyIUbei7q/EaH1U7QGbbLh+o9xW9ZPHH52HF/lSR80pUSN 7yfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7rXk1sKSqinlJBrFL9P/VMnnxUDcgz/M8L7XKzjlIwM=; b=3KJCNBBFW/UuURbqUj3s2YwHWKpJdM6wrbcGayYTHzMaBLNYY6hIMpsMbIwV9mjSI8 c81opewUqrH+emG8e8Gkw3LjxVeC+2CTS/Y3AYAyYn6IsYIuUtyYYTefCbRw01j2II+e H4xPAqs5418KGGbvTs3IJJKE0uysW/S3XS8BK584R+CuWoVW37Bm+aCi5REsK1kncYoP i00SFcdXimnN/OFQBD7HGSLS6+lo0AAOR8wKPG95q1w/9hwYK7FPr4E0gz3Pb9GO9Isc Ie4arfD3CKtQhZe4SUjMTj+LxueE+PmVOJBrS1dOWcFQQnk2T4iQej/uv3VVfNCf3JpD OxKA== X-Gm-Message-State: AO0yUKXvUOWxz7peW1JbZpk6Ce0KyWgvB6d+Hnz8UWEkhla1pctvftlS kVpoPorClt/opvNPpv05IlCVZahsok/JodD7yeg= X-Google-Smtp-Source: AK7set8m3YAw+wt5BhSLJFeicnxxhLP4EC88PXa+RRdPMAOS5P8WEpruOYnHeYHKtOj0sqluNKeLyA== X-Received: by 2002:a17:903:1d1:b0:19d:1dfe:eab4 with SMTP id e17-20020a17090301d100b0019d1dfeeab4mr1243388plh.41.1677475534806; Sun, 26 Feb 2023 21:25:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 09/76] target/arm: Drop new_tmp_a64_zero Date: Sun, 26 Feb 2023 19:23:58 -1000 Message-Id: <20230227052505.352889-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475903436100001 Content-Type: text/plain; charset="utf-8" Only the use within cpu_reg requires a writable temp, so inline new_tmp_a64_zero there. All other uses are fine with a constant temp, so use tcg_constant_i64(0). Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/arm/translate-a64.h | 1 - target/arm/translate-a64.c | 41 +++++++++++++++++--------------------- 2 files changed, 18 insertions(+), 24 deletions(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 8ac126991f..0576c4ea12 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -18,7 +18,6 @@ #ifndef TARGET_ARM_TRANSLATE_A64_H #define TARGET_ARM_TRANSLATE_A64_H =20 -TCGv_i64 new_tmp_a64_zero(DisasContext *s); TCGv_i64 cpu_reg(DisasContext *s, int reg); TCGv_i64 cpu_reg_sp(DisasContext *s, int reg); TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 04872d9925..b5d6508cbc 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -408,13 +408,6 @@ static void gen_goto_tb(DisasContext *s, int n, int64_= t diff) } } =20 -TCGv_i64 new_tmp_a64_zero(DisasContext *s) -{ - TCGv_i64 t =3D tcg_temp_new_i64(); - tcg_gen_movi_i64(t, 0); - return t; -} - /* * Register access functions * @@ -433,7 +426,9 @@ TCGv_i64 new_tmp_a64_zero(DisasContext *s) TCGv_i64 cpu_reg(DisasContext *s, int reg) { if (reg =3D=3D 31) { - return new_tmp_a64_zero(s); + TCGv_i64 t =3D tcg_temp_new_i64(); + tcg_gen_movi_i64(t, 0); + return t; } else { return cpu_X[reg]; } @@ -1532,7 +1527,7 @@ static void handle_hint(DisasContext *s, uint32_t ins= n, case 0b11000: /* PACIAZ */ if (s->pauth_active) { gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], - new_tmp_a64_zero(s)); + tcg_constant_i64(0)); } break; case 0b11001: /* PACIASP */ @@ -1543,7 +1538,7 @@ static void handle_hint(DisasContext *s, uint32_t ins= n, case 0b11010: /* PACIBZ */ if (s->pauth_active) { gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], - new_tmp_a64_zero(s)); + tcg_constant_i64(0)); } break; case 0b11011: /* PACIBSP */ @@ -1554,7 +1549,7 @@ static void handle_hint(DisasContext *s, uint32_t ins= n, case 0b11100: /* AUTIAZ */ if (s->pauth_active) { gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], - new_tmp_a64_zero(s)); + tcg_constant_i64(0)); } break; case 0b11101: /* AUTIASP */ @@ -1565,7 +1560,7 @@ static void handle_hint(DisasContext *s, uint32_t ins= n, case 0b11110: /* AUTIBZ */ if (s->pauth_active) { gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], - new_tmp_a64_zero(s)); + tcg_constant_i64(0)); } break; case 0b11111: /* AUTIBSP */ @@ -2285,7 +2280,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3= 2_t insn) if (op4 !=3D 0x1f) { goto do_unallocated; } - modifier =3D new_tmp_a64_zero(s); + modifier =3D tcg_constant_i64(0); } if (s->pauth_active) { dst =3D tcg_temp_new_i64(); @@ -3550,10 +3545,10 @@ static void disas_ldst_pac(DisasContext *s, uint32_= t insn, if (s->pauth_active) { if (use_key_a) { gen_helper_autda(dirty_addr, cpu_env, dirty_addr, - new_tmp_a64_zero(s)); + tcg_constant_i64(0)); } else { gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, - new_tmp_a64_zero(s)); + tcg_constant_i64(0)); } } =20 @@ -5628,7 +5623,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) goto do_unallocated; } else if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0)); } break; case MAP(1, 0x01, 0x09): /* PACIZB */ @@ -5636,7 +5631,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) goto do_unallocated; } else if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0)); } break; case MAP(1, 0x01, 0x0a): /* PACDZA */ @@ -5644,7 +5639,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) goto do_unallocated; } else if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0)); } break; case MAP(1, 0x01, 0x0b): /* PACDZB */ @@ -5652,7 +5647,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) goto do_unallocated; } else if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0)); } break; case MAP(1, 0x01, 0x0c): /* AUTIZA */ @@ -5660,7 +5655,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) goto do_unallocated; } else if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_autia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + gen_helper_autia(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0)); } break; case MAP(1, 0x01, 0x0d): /* AUTIZB */ @@ -5668,7 +5663,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) goto do_unallocated; } else if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_autib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + gen_helper_autib(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0)); } break; case MAP(1, 0x01, 0x0e): /* AUTDZA */ @@ -5676,7 +5671,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) goto do_unallocated; } else if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_autda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + gen_helper_autda(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0)); } break; case MAP(1, 0x01, 0x0f): /* AUTDZB */ @@ -5684,7 +5679,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) goto do_unallocated; } else if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s)); + gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0)); } break; case MAP(1, 0x01, 0x10): /* XPACI */ --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677475740; cv=none; d=zohomail.com; s=zohoarc; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.25.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:25:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p1emp/tNLeWyW6jIioRs4cMEwuOfQt7qMeQLtGu1o9s=; b=ACVjf3q7j8vmBBssv73Elv8QsM47DrhnBh33bjbjEDP/+QLj3qWDwrJe+P/hdtp7Pi R+Z2bvFLc3tTw1N06z1LyLIxUHYgthJiMKYpC3I8fzy1nUgs87K4IxygWSGBnWpmUlQp /fvoE5RFYfiLs5iXFzvmz+alMJ8bm/89jzNN3tP8jRTXFXzRW9QzTd4BXrpTA3e8q/v7 z0+Uhw7MB3WffO/PBptE0Xm1GBExfdF6p0aQjJU9GDrG23Q2vRUXDiCjqalosxUfks1g xMxOiEtXArAxk3bYby/ZqWk1tJIeA8OJz/8S+8A5hDlYLGC+QcrcG5IrK9PjmrBXCbJJ jLqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p1emp/tNLeWyW6jIioRs4cMEwuOfQt7qMeQLtGu1o9s=; b=S1bbcjfxPPbrWARz2zx0nTB6gToYdAUzThjS12urS9F/DtObUdzNDmOepa2eqBhH3e zo4o75OXjLLLjzCJRiQSzduA2CX1K/VMxrLY5+J9CpoUuTwoWVwwT9BQpYCmm0CYBeEc g0kNoFj4dxvgew13Vx7sNKt4EtSwfg+Q0YpGeYNKYFPZiarC5LSMI6LUg0gOIe1bP/3P ViW8Yewod9U0pATFhH9V4eSqDE6gV6pm1akkfbDNONF7y/AwlYDnYoR0UVE8wDAKIZR4 xXutqDKTFgi4Vm3+U2VMk4HBcg5NPFEudmpbhQ/OZxzH3qD0HU00UAUaBVLFCPNDJpKW 4Wng== X-Gm-Message-State: AO0yUKXFC+jf/k/pUrc38Vpd2h+TzU7NY0nTKKAYaRHreG2sWeA7LGHZ Es7X0X091XJqrVHuIFQYro5Vkuf8EqN0MwYiq3jRhQ== X-Google-Smtp-Source: AK7set9JxoG5uoK7t1NqfS5i75+AGN2UZEU2A9/IovvWIJ9HVMsgijCmXpkBkG8ugsiF9evZ+073pA== X-Received: by 2002:a17:903:2283:b0:19a:ae30:3a42 with SMTP id b3-20020a170903228300b0019aae303a42mr8526570plh.21.1677475537749; Sun, 26 Feb 2023 21:25:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 10/76] target/arm: Drop tcg_temp_free from translator-a64.c Date: Sun, 26 Feb 2023 19:23:59 -1000 Message-Id: <20230227052505.352889-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475740699100003 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/arm/translate-a64.c | 468 +------------------------------------ 1 file changed, 11 insertions(+), 457 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b5d6508cbc..b1fa210d64 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -542,7 +542,6 @@ static void write_fp_sreg(DisasContext *s, int reg, TCG= v_i32 v) =20 tcg_gen_extu_i32_i64(tmp, v); write_fp_dreg(s, reg, tmp); - tcg_temp_free_i64(tmp); } =20 /* Expand a 2-operand AdvSIMD vector operation using an expander function.= */ @@ -611,7 +610,6 @@ static void gen_gvec_op3_fpst(DisasContext *s, bool is_= q, int rd, int rn, vec_full_reg_offset(s, rn), vec_full_reg_offset(s, rm), fpst, is_q ? 16 : 8, vec_full_reg_size(s), data, fn); - tcg_temp_free_ptr(fpst); } =20 /* Expand a 3-operand + qc + operation using an out-of-line helper. */ @@ -625,7 +623,6 @@ static void gen_gvec_op3_qc(DisasContext *s, bool is_q,= int rd, int rn, vec_full_reg_offset(s, rn), vec_full_reg_offset(s, rm), qc_ptr, is_q ? 16 : 8, vec_full_reg_size(s), 0, fn); - tcg_temp_free_ptr(qc_ptr); } =20 /* Expand a 4-operand operation using an out-of-line helper. */ @@ -653,7 +650,6 @@ static void gen_gvec_op4_fpst(DisasContext *s, bool is_= q, int rd, int rn, vec_full_reg_offset(s, rm), vec_full_reg_offset(s, ra), fpst, is_q ? 16 : 8, vec_full_reg_size(s), data, fn); - tcg_temp_free_ptr(fpst); } =20 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier @@ -697,12 +693,9 @@ static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64= t0, TCGv_i64 t1) tcg_gen_xor_i64(flag, result, t0); tcg_gen_xor_i64(tmp, t0, t1); tcg_gen_andc_i64(flag, flag, tmp); - tcg_temp_free_i64(tmp); tcg_gen_extrh_i64_i32(cpu_VF, flag); =20 tcg_gen_mov_i64(dest, result); - tcg_temp_free_i64(result); - tcg_temp_free_i64(flag); } else { /* 32 bit arithmetic */ TCGv_i32 t0_32 =3D tcg_temp_new_i32(); @@ -718,10 +711,6 @@ static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64= t0, TCGv_i64 t1) tcg_gen_xor_i32(tmp, t0_32, t1_32); tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); tcg_gen_extu_i32_i64(dest, cpu_NF); - - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(t0_32); - tcg_temp_free_i32(t1_32); } } =20 @@ -745,11 +734,8 @@ static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64= t0, TCGv_i64 t1) tmp =3D tcg_temp_new_i64(); tcg_gen_xor_i64(tmp, t0, t1); tcg_gen_and_i64(flag, flag, tmp); - tcg_temp_free_i64(tmp); tcg_gen_extrh_i64_i32(cpu_VF, flag); tcg_gen_mov_i64(dest, result); - tcg_temp_free_i64(flag); - tcg_temp_free_i64(result); } else { /* 32 bit arithmetic */ TCGv_i32 t0_32 =3D tcg_temp_new_i32(); @@ -764,10 +750,7 @@ static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64= t0, TCGv_i64 t1) tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); tmp =3D tcg_temp_new_i32(); tcg_gen_xor_i32(tmp, t0_32, t1_32); - tcg_temp_free_i32(t0_32); - tcg_temp_free_i32(t1_32); tcg_gen_and_i32(cpu_VF, cpu_VF, tmp); - tcg_temp_free_i32(tmp); tcg_gen_extu_i32_i64(dest, cpu_NF); } } @@ -779,7 +762,6 @@ static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0,= TCGv_i64 t1) tcg_gen_extu_i32_i64(flag, cpu_CF); tcg_gen_add_i64(dest, t0, t1); tcg_gen_add_i64(dest, dest, flag); - tcg_temp_free_i64(flag); =20 if (!sf) { tcg_gen_ext32u_i64(dest, dest); @@ -808,11 +790,6 @@ static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64= t0, TCGv_i64 t1) tcg_gen_extrh_i64_i32(cpu_VF, vf_64); =20 tcg_gen_mov_i64(dest, result); - - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(vf_64); - tcg_temp_free_i64(cf_64); - tcg_temp_free_i64(result); } else { TCGv_i32 t0_32 =3D tcg_temp_new_i32(); TCGv_i32 t1_32 =3D tcg_temp_new_i32(); @@ -829,10 +806,6 @@ static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64= t0, TCGv_i64 t1) tcg_gen_xor_i32(tmp, t0_32, t1_32); tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); tcg_gen_extu_i32_i64(dest, cpu_NF); - - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(t1_32); - tcg_temp_free_i32(t0_32); } } =20 @@ -942,12 +915,7 @@ static void do_fp_st(DisasContext *s, int srcidx, TCGv= _i64 tcg_addr, int size) tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); tcg_gen_qemu_st_i64(be ? tmplo : tmphi, tcg_hiaddr, get_mem_index(s), mop); - - tcg_temp_free_i64(tcg_hiaddr); - tcg_temp_free_i64(tmphi); } - - tcg_temp_free_i64(tmplo); } =20 /* @@ -976,15 +944,12 @@ static void do_fp_ld(DisasContext *s, int destidx, TC= Gv_i64 tcg_addr, int size) tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); tcg_gen_qemu_ld_i64(be ? tmplo : tmphi, tcg_hiaddr, get_mem_index(s), mop); - tcg_temp_free_i64(tcg_hiaddr); } =20 tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64)); - tcg_temp_free_i64(tmplo); =20 if (tmphi) { tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx)); - tcg_temp_free_i64(tmphi); } clear_vec_high(s, tmphi !=3D NULL, destidx); } @@ -1110,8 +1075,6 @@ static void do_vec_st(DisasContext *s, int srcidx, in= t element, =20 read_vec_element(s, tcg_tmp, srcidx, element, mop & MO_SIZE); tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), mop); - - tcg_temp_free_i64(tcg_tmp); } =20 /* Load from memory to vector register */ @@ -1122,8 +1085,6 @@ static void do_vec_ld(DisasContext *s, int destidx, i= nt element, =20 tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), mop); write_vec_element(s, tcg_tmp, destidx, element, mop & MO_SIZE); - - tcg_temp_free_i64(tcg_tmp); } =20 /* Check that FP/Neon access is enabled. If it is, return @@ -1407,7 +1368,6 @@ static void disas_test_b_imm(DisasContext *s, uint32_= t insn) match =3D gen_disas_label(s); tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, tcg_cmp, 0, match.label); - tcg_temp_free_i64(tcg_cmp); gen_goto_tb(s, 0, 4); set_disas_label(s, match); gen_goto_tb(s, 1, diff); @@ -1663,8 +1623,6 @@ static void gen_xaflag(void) =20 /* C | Z */ tcg_gen_or_i32(cpu_CF, cpu_CF, z); - - tcg_temp_free_i32(z); } =20 static void gen_axflag(void) @@ -1840,9 +1798,6 @@ static void gen_get_nzcv(TCGv_i64 tcg_rt) tcg_gen_deposit_i32(nzcv, nzcv, tmp, 28, 1); /* generate result */ tcg_gen_extu_i32_i64(tcg_rt, nzcv); - - tcg_temp_free_i32(nzcv); - tcg_temp_free_i32(tmp); } =20 static void gen_set_nzcv(TCGv_i64 tcg_rt) @@ -1863,7 +1818,6 @@ static void gen_set_nzcv(TCGv_i64 tcg_rt) /* bit 28, V */ tcg_gen_andi_i32(cpu_VF, nzcv, (1 << 28)); tcg_gen_shli_i32(cpu_VF, cpu_VF, 3); - tcg_temp_free_i32(nzcv); } =20 static void gen_sysreg_undef(DisasContext *s, bool isread, @@ -1949,7 +1903,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, case 0: break; case ARM_CP_NOP: - goto exit; + return; case ARM_CP_NZCV: tcg_rt =3D cpu_reg(s, rt); if (isread) { @@ -1957,14 +1911,14 @@ static void handle_sys(DisasContext *s, uint32_t in= sn, bool isread, } else { gen_set_nzcv(tcg_rt); } - goto exit; + return; case ARM_CP_CURRENTEL: /* Reads as current EL value from pstate, which is * guaranteed to be constant by the tb flags. */ tcg_rt =3D cpu_reg(s, rt); tcg_gen_movi_i64(tcg_rt, s->current_el << 2); - goto exit; + return; case ARM_CP_DC_ZVA: /* Writes clear the aligned block of memory which rt points into. = */ if (s->mte_active[0]) { @@ -1981,7 +1935,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, tcg_rt =3D clean_data_tbi(s, cpu_reg(s, rt)); } gen_helper_dc_zva(cpu_env, tcg_rt); - goto exit; + return; case ARM_CP_DC_GVA: { TCGv_i64 clean_addr, tag; @@ -1999,10 +1953,9 @@ static void handle_sys(DisasContext *s, uint32_t ins= n, bool isread, tag =3D tcg_temp_new_i64(); tcg_gen_shri_i64(tag, tcg_rt, 56); gen_helper_stzgm_tags(cpu_env, clean_addr, tag); - tcg_temp_free_i64(tag); } } - goto exit; + return; case ARM_CP_DC_GZVA: { TCGv_i64 clean_addr, tag; @@ -2017,19 +1970,18 @@ static void handle_sys(DisasContext *s, uint32_t in= sn, bool isread, tag =3D tcg_temp_new_i64(); tcg_gen_shri_i64(tag, tcg_rt, 56); gen_helper_stzgm_tags(cpu_env, clean_addr, tag); - tcg_temp_free_i64(tag); } } - goto exit; + return; default: g_assert_not_reached(); } if ((ri->type & ARM_CP_FPU) && !fp_access_check_only(s)) { - goto exit; + return; } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) { - goto exit; + return; } else if ((ri->type & ARM_CP_SME) && !sme_access_check(s)) { - goto exit; + return; } =20 if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO))= { @@ -2052,7 +2004,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, } else { if (ri->type & ARM_CP_CONST) { /* If not forbidden by access permissions, treat as WI */ - goto exit; + return; } else if (ri->writefn) { if (!tcg_ri) { tcg_ri =3D gen_lookup_cp_reg(key); @@ -2080,11 +2032,6 @@ static void handle_sys(DisasContext *s, uint32_t ins= n, bool isread, */ s->base.is_jmp =3D DISAS_UPDATE_EXIT; } - - exit: - if (tcg_ri) { - tcg_temp_free_ptr(tcg_ri); - } } =20 /* System @@ -2395,7 +2342,6 @@ static void disas_uncond_b_reg(DisasContext *s, uint3= 2_t insn) } =20 gen_helper_exception_return(cpu_env, dst); - tcg_temp_free_i64(dst); /* Must exit loop to check un-masked IRQs */ s->base.is_jmp =3D DISAS_EXIT; return; @@ -2515,7 +2461,6 @@ static void gen_load_exclusive(DisasContext *s, int r= t, int rt2, TCGv_i64 addr2 =3D tcg_temp_new_i64(); tcg_gen_addi_i64(addr2, addr, 8); tcg_gen_qemu_ld_i64(cpu_exclusive_high, addr2, idx, memop); - tcg_temp_free_i64(addr2); =20 tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val); tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high); @@ -2580,7 +2525,6 @@ static void gen_store_exclusive(DisasContext *s, int = rd, int rt, int rt2, tcg_gen_atomic_cmpxchg_i128(t16, cpu_exclusive_addr, c16, t16, get_mem_index(s), MO_128 | MO_ALIGN | s->be_data); - tcg_temp_free_i128(c16); =20 a =3D tcg_temp_new_i64(); b =3D tcg_temp_new_i64(); @@ -2593,9 +2537,6 @@ static void gen_store_exclusive(DisasContext *s, int = rd, int rt, int rt2, tcg_gen_xor_i64(a, a, cpu_exclusive_val); tcg_gen_xor_i64(b, b, cpu_exclusive_high); tcg_gen_or_i64(tmp, a, b); - tcg_temp_free_i64(a); - tcg_temp_free_i64(b); - tcg_temp_free_i128(t16); =20 tcg_gen_setcondi_i64(TCG_COND_NE, tmp, tmp, 0); } @@ -2606,7 +2547,6 @@ static void gen_store_exclusive(DisasContext *s, int = rd, int rt, int rt2, tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); } tcg_gen_mov_i64(cpu_reg(s, rd), tmp); - tcg_temp_free_i64(tmp); tcg_gen_br(done_label); =20 gen_set_label(fail_label); @@ -2662,14 +2602,12 @@ static void gen_compare_and_swap_pair(DisasContext = *s, int rs, int rt, =20 tcg_gen_atomic_cmpxchg_i64(cmp, clean_addr, cmp, val, memidx, MO_64 | MO_ALIGN | s->be_data); - tcg_temp_free_i64(val); =20 if (s->be_data =3D=3D MO_LE) { tcg_gen_extr32_i64(s1, s2, cmp); } else { tcg_gen_extr32_i64(s2, s1, cmp); } - tcg_temp_free_i64(cmp); } else { TCGv_i128 cmp =3D tcg_temp_new_i128(); TCGv_i128 val =3D tcg_temp_new_i128(); @@ -2684,14 +2622,12 @@ static void gen_compare_and_swap_pair(DisasContext = *s, int rs, int rt, =20 tcg_gen_atomic_cmpxchg_i128(cmp, clean_addr, cmp, val, memidx, MO_128 | MO_ALIGN | s->be_data); - tcg_temp_free_i128(val); =20 if (s->be_data =3D=3D MO_LE) { tcg_gen_extr_i128_i64(s1, s2, cmp); } else { tcg_gen_extr_i128_i64(s2, s1, cmp); } - tcg_temp_free_i128(cmp); } } =20 @@ -3075,7 +3011,6 @@ static void disas_ldst_pair(DisasContext *s, uint32_t= insn) false, false, 0, false, false); =20 tcg_gen_mov_i64(tcg_rt, tmp); - tcg_temp_free_i64(tmp); } else { do_gpr_st(s, tcg_rt, clean_addr, size, false, 0, false, false); @@ -3975,7 +3910,6 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt), (is_q + 1) * 8, vec_full_reg_size(s), tcg_tmp); - tcg_temp_free_i64(tcg_tmp); } else { /* Load/store one element per register */ if (is_load) { @@ -4317,8 +4251,6 @@ static void disas_add_sub_imm(DisasContext *s, uint32= _t insn) } else { tcg_gen_ext32u_i64(tcg_rd, tcg_result); } - - tcg_temp_free_i64(tcg_result); } =20 /* @@ -4706,10 +4638,8 @@ static void disas_extract(DisasContext *s, uint32_t = insn) TCGv_i32 t1 =3D tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(t1, tcg_rn); tcg_gen_extract2_i32(t0, t0, t1, imm); - tcg_temp_free_i32(t1); } tcg_gen_extu_i32_i64(tcg_rd, t0); - tcg_temp_free_i32(t0); } } } @@ -4778,8 +4708,6 @@ static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int= sf, tcg_gen_extrl_i64_i32(t1, shift_amount); tcg_gen_rotr_i32(t0, t0, t1); tcg_gen_extu_i32_i64(dst, t0); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); } break; default: @@ -4968,8 +4896,6 @@ static void disas_add_sub_ext_reg(DisasContext *s, ui= nt32_t insn) } else { tcg_gen_ext32u_i64(tcg_rd, tcg_result); } - - tcg_temp_free_i64(tcg_result); } =20 /* @@ -5032,8 +4958,6 @@ static void disas_add_sub_reg(DisasContext *s, uint32= _t insn) } else { tcg_gen_ext32u_i64(tcg_rd, tcg_result); } - - tcg_temp_free_i64(tcg_result); } =20 /* Data-processing (3 source) @@ -5091,8 +5015,6 @@ static void disas_data_proc_3src(DisasContext *s, uin= t32_t insn) } else { tcg_gen_mulu2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm); } - - tcg_temp_free_i64(low_bits); return; } =20 @@ -5128,10 +5050,6 @@ static void disas_data_proc_3src(DisasContext *s, ui= nt32_t insn) if (!sf) { tcg_gen_ext32u_i64(cpu_reg(s, rd), cpu_reg(s, rd)); } - - tcg_temp_free_i64(tcg_op1); - tcg_temp_free_i64(tcg_op2); - tcg_temp_free_i64(tcg_tmp); } =20 /* Add/subtract (with carry) @@ -5211,8 +5129,6 @@ static void disas_rotate_right_into_flags(DisasContex= t *s, uint32_t insn) if (mask & 1) { /* V */ tcg_gen_shli_i32(cpu_VF, nzcv, 31 - 0); } - - tcg_temp_free_i32(nzcv); } =20 /* @@ -5245,7 +5161,6 @@ static void disas_evaluate_into_flags(DisasContext *s= , uint32_t insn) tcg_gen_shli_i32(cpu_VF, tmp, shift - 1); tcg_gen_mov_i32(cpu_ZF, cpu_NF); tcg_gen_xor_i32(cpu_VF, cpu_VF, cpu_NF); - tcg_temp_free_i32(tmp); } =20 /* Conditional compare (immediate / register) @@ -5299,7 +5214,6 @@ static void disas_cc(DisasContext *s, uint32_t insn) } else { gen_add_CC(sf, tcg_tmp, tcg_rn, tcg_y); } - tcg_temp_free_i64(tcg_tmp); =20 /* If COND was false, force the flags to #nzcv. Compute two masks * to help with this: T1 =3D (COND ? 0 : -1), T2 =3D (COND ? -1 : 0). @@ -5347,9 +5261,6 @@ static void disas_cc(DisasContext *s, uint32_t insn) tcg_gen_and_i32(cpu_VF, cpu_VF, tcg_t2); } } - tcg_temp_free_i32(tcg_t0); - tcg_temp_free_i32(tcg_t1); - tcg_temp_free_i32(tcg_t2); } =20 /* Conditional select @@ -5420,7 +5331,6 @@ static void handle_clz(DisasContext *s, unsigned int = sf, tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); tcg_gen_clzi_i32(tcg_tmp32, tcg_tmp32, 32); tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); - tcg_temp_free_i32(tcg_tmp32); } } =20 @@ -5438,7 +5348,6 @@ static void handle_cls(DisasContext *s, unsigned int = sf, tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); tcg_gen_clrsb_i32(tcg_tmp32, tcg_tmp32); tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); - tcg_temp_free_i32(tcg_tmp32); } } =20 @@ -5456,7 +5365,6 @@ static void handle_rbit(DisasContext *s, unsigned int= sf, tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn); gen_helper_rbit(tcg_tmp32, tcg_tmp32); tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32); - tcg_temp_free_i32(tcg_tmp32); } } =20 @@ -5502,8 +5410,6 @@ static void handle_rev16(DisasContext *s, unsigned in= t sf, tcg_gen_and_i64(tcg_tmp, tcg_tmp, mask); tcg_gen_shli_i64(tcg_rd, tcg_rd, 8); tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp); - - tcg_temp_free_i64(tcg_tmp); } =20 /* Data-processing (1 source) @@ -5745,7 +5651,6 @@ static void handle_shift_reg(DisasContext *s, =20 tcg_gen_andi_i64(tcg_shift, cpu_reg(s, rm), sf ? 63 : 31); shift_reg(tcg_rd, tcg_rn, sf, shift_type, tcg_shift); - tcg_temp_free_i64(tcg_shift); } =20 /* CRC32[BHWX], CRC32C[BHWX] */ @@ -5862,8 +5767,6 @@ static void disas_data_proc_2src(DisasContext *s, uin= t32_t insn) tcg_gen_extract_i64(t, cpu_reg_sp(s, rn), 56, 4); tcg_gen_shl_i64(t, tcg_constant_i64(1), t); tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t); - - tcg_temp_free_i64(t); } break; case 8: /* LSLV */ @@ -6007,8 +5910,6 @@ static void handle_fp_compare(DisasContext *s, int si= ze, } else { gen_helper_vfp_cmpd_a64(tcg_flags, tcg_vn, tcg_vm, fpst); } - tcg_temp_free_i64(tcg_vn); - tcg_temp_free_i64(tcg_vm); } else { TCGv_i32 tcg_vn =3D tcg_temp_new_i32(); TCGv_i32 tcg_vm =3D tcg_temp_new_i32(); @@ -6038,16 +5939,9 @@ static void handle_fp_compare(DisasContext *s, int s= ize, default: g_assert_not_reached(); } - - tcg_temp_free_i32(tcg_vn); - tcg_temp_free_i32(tcg_vm); } =20 - tcg_temp_free_ptr(fpst); - gen_set_nzcv(tcg_flags); - - tcg_temp_free_i64(tcg_flags); } =20 /* Floating point compare @@ -6219,12 +6113,10 @@ static void disas_fp_csel(DisasContext *s, uint32_t= insn) a64_test_cc(&c, cond); tcg_gen_movcond_i64(c.cond, t_true, c.value, tcg_constant_i64(0), t_true, t_false); - tcg_temp_free_i64(t_false); =20 /* Note that sregs & hregs write back zeros to the high bits, and we've already done the zero-extension. */ write_fp_dreg(s, rd, t_true); - tcg_temp_free_i64(t_true); } =20 /* Floating-point data-processing (1 source) - half precision */ @@ -6261,7 +6153,6 @@ static void handle_fp_1src_half(DisasContext *s, int = opcode, int rd, int rn) gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); =20 gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - tcg_temp_free_i32(tcg_rmode); break; } case 0xe: /* FRINTX */ @@ -6277,12 +6168,6 @@ static void handle_fp_1src_half(DisasContext *s, int= opcode, int rd, int rn) } =20 write_fp_sreg(s, rd, tcg_res); - - if (fpst) { - tcg_temp_free_ptr(fpst); - } - tcg_temp_free_i32(tcg_op); - tcg_temp_free_i32(tcg_res); } =20 /* Floating-point data-processing (1 source) - single precision */ @@ -6350,16 +6235,12 @@ static void handle_fp_1src_single(DisasContext *s, = int opcode, int rd, int rn) gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); gen_fpst(tcg_res, tcg_op, fpst); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - tcg_temp_free_i32(tcg_rmode); } else { gen_fpst(tcg_res, tcg_op, fpst); } - tcg_temp_free_ptr(fpst); =20 done: write_fp_sreg(s, rd, tcg_res); - tcg_temp_free_i32(tcg_op); - tcg_temp_free_i32(tcg_res); } =20 /* Floating-point data-processing (1 source) - double precision */ @@ -6427,16 +6308,12 @@ static void handle_fp_1src_double(DisasContext *s, = int opcode, int rd, int rn) gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); gen_fpst(tcg_res, tcg_op, fpst); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - tcg_temp_free_i32(tcg_rmode); } else { gen_fpst(tcg_res, tcg_op, fpst); } - tcg_temp_free_ptr(fpst); =20 done: write_fp_dreg(s, rd, tcg_res); - tcg_temp_free_i64(tcg_op); - tcg_temp_free_i64(tcg_res); } =20 static void handle_fp_fcvt(DisasContext *s, int opcode, @@ -6451,7 +6328,6 @@ static void handle_fp_fcvt(DisasContext *s, int opcod= e, TCGv_i64 tcg_rd =3D tcg_temp_new_i64(); gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, cpu_env); write_fp_dreg(s, rd, tcg_rd); - tcg_temp_free_i64(tcg_rd); } else { /* Single to half */ TCGv_i32 tcg_rd =3D tcg_temp_new_i32(); @@ -6461,11 +6337,7 @@ static void handle_fp_fcvt(DisasContext *s, int opco= de, gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, fpst, ahp); /* write_fp_sreg is OK here because top half of tcg_rd is zero= */ write_fp_sreg(s, rd, tcg_rd); - tcg_temp_free_i32(tcg_rd); - tcg_temp_free_i32(ahp); - tcg_temp_free_ptr(fpst); } - tcg_temp_free_i32(tcg_rn); break; } case 0x1: @@ -6481,12 +6353,8 @@ static void handle_fp_fcvt(DisasContext *s, int opco= de, /* Double to half */ gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, fpst, ahp); /* write_fp_sreg is OK here because top half of tcg_rd is zero= */ - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(ahp); } write_fp_sreg(s, rd, tcg_rd); - tcg_temp_free_i32(tcg_rd); - tcg_temp_free_i64(tcg_rn); break; } case 0x3: @@ -6500,17 +6368,12 @@ static void handle_fp_fcvt(DisasContext *s, int opc= ode, TCGv_i32 tcg_rd =3D tcg_temp_new_i32(); gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, tcg_fpst, tcg_a= hp); write_fp_sreg(s, rd, tcg_rd); - tcg_temp_free_i32(tcg_rd); } else { /* Half to double */ TCGv_i64 tcg_rd =3D tcg_temp_new_i64(); gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, tcg_fpst, tcg_a= hp); write_fp_dreg(s, rd, tcg_rd); - tcg_temp_free_i64(tcg_rd); } - tcg_temp_free_i32(tcg_rn); - tcg_temp_free_ptr(tcg_fpst); - tcg_temp_free_i32(tcg_ahp); break; } default: @@ -6658,11 +6521,6 @@ static void handle_fp_2src_single(DisasContext *s, i= nt opcode, } =20 write_fp_sreg(s, rd, tcg_res); - - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tcg_op1); - tcg_temp_free_i32(tcg_op2); - tcg_temp_free_i32(tcg_res); } =20 /* Floating-point data-processing (2 source) - double precision */ @@ -6711,11 +6569,6 @@ static void handle_fp_2src_double(DisasContext *s, i= nt opcode, } =20 write_fp_dreg(s, rd, tcg_res); - - tcg_temp_free_ptr(fpst); - tcg_temp_free_i64(tcg_op1); - tcg_temp_free_i64(tcg_op2); - tcg_temp_free_i64(tcg_res); } =20 /* Floating-point data-processing (2 source) - half precision */ @@ -6766,11 +6619,6 @@ static void handle_fp_2src_half(DisasContext *s, int= opcode, } =20 write_fp_sreg(s, rd, tcg_res); - - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tcg_op1); - tcg_temp_free_i32(tcg_op2); - tcg_temp_free_i32(tcg_res); } =20 /* Floating point data-processing (2 source) @@ -6851,12 +6699,6 @@ static void handle_fp_3src_single(DisasContext *s, b= ool o0, bool o1, gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); =20 write_fp_sreg(s, rd, tcg_res); - - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tcg_op1); - tcg_temp_free_i32(tcg_op2); - tcg_temp_free_i32(tcg_op3); - tcg_temp_free_i32(tcg_res); } =20 /* Floating-point data-processing (3 source) - double precision */ @@ -6889,12 +6731,6 @@ static void handle_fp_3src_double(DisasContext *s, b= ool o0, bool o1, gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); =20 write_fp_dreg(s, rd, tcg_res); - - tcg_temp_free_ptr(fpst); - tcg_temp_free_i64(tcg_op1); - tcg_temp_free_i64(tcg_op2); - tcg_temp_free_i64(tcg_op3); - tcg_temp_free_i64(tcg_res); } =20 /* Floating-point data-processing (3 source) - half precision */ @@ -6927,12 +6763,6 @@ static void handle_fp_3src_half(DisasContext *s, boo= l o0, bool o1, gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); =20 write_fp_sreg(s, rd, tcg_res); - - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tcg_op1); - tcg_temp_free_i32(tcg_op2); - tcg_temp_free_i32(tcg_op3); - tcg_temp_free_i32(tcg_res); } =20 /* Floating point data-processing (3 source) @@ -7074,7 +6904,6 @@ static void handle_fpfpcvt(DisasContext *s, int rd, i= nt rn, int opcode, tcg_shift, tcg_fpstatus); } write_fp_dreg(s, rd, tcg_double); - tcg_temp_free_i64(tcg_double); break; =20 case 0: /* float32 */ @@ -7087,7 +6916,6 @@ static void handle_fpfpcvt(DisasContext *s, int rd, i= nt rn, int opcode, tcg_shift, tcg_fpstatus); } write_fp_sreg(s, rd, tcg_single); - tcg_temp_free_i32(tcg_single); break; =20 case 3: /* float16 */ @@ -7100,7 +6928,6 @@ static void handle_fpfpcvt(DisasContext *s, int rd, i= nt rn, int opcode, tcg_shift, tcg_fpstatus); } write_fp_sreg(s, rd, tcg_single); - tcg_temp_free_i32(tcg_single); break; =20 default: @@ -7144,7 +6971,6 @@ static void handle_fpfpcvt(DisasContext *s, int rd, i= nt rn, int opcode, if (!sf) { tcg_gen_ext32u_i64(tcg_int, tcg_int); } - tcg_temp_free_i64(tcg_double); break; =20 case 0: /* float32 */ @@ -7167,9 +6993,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, i= nt rn, int opcode, tcg_shift, tcg_fpstatus); } tcg_gen_extu_i32_i64(tcg_int, tcg_dest); - tcg_temp_free_i32(tcg_dest); } - tcg_temp_free_i32(tcg_single); break; =20 case 3: /* float16 */ @@ -7192,9 +7016,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, i= nt rn, int opcode, tcg_shift, tcg_fpstatus); } tcg_gen_extu_i32_i64(tcg_int, tcg_dest); - tcg_temp_free_i32(tcg_dest); } - tcg_temp_free_i32(tcg_single); break; =20 default: @@ -7202,10 +7024,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, = int rn, int opcode, } =20 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); - tcg_temp_free_i32(tcg_rmode); } - - tcg_temp_free_ptr(tcg_fpstatus); } =20 /* Floating point <-> fixed point conversions @@ -7282,7 +7101,6 @@ static void handle_fmov(DisasContext *s, int rd, int = rn, int type, bool itof) tmp =3D tcg_temp_new_i64(); tcg_gen_ext32u_i64(tmp, tcg_rn); write_fp_dreg(s, rd, tmp); - tcg_temp_free_i64(tmp); break; case 1: /* 64 bit */ @@ -7298,7 +7116,6 @@ static void handle_fmov(DisasContext *s, int rd, int = rn, int type, bool itof) tmp =3D tcg_temp_new_i64(); tcg_gen_ext16u_i64(tmp, tcg_rn); write_fp_dreg(s, rd, tmp); - tcg_temp_free_i64(tmp); break; default: g_assert_not_reached(); @@ -7336,15 +7153,11 @@ static void handle_fjcvtzs(DisasContext *s, int rd,= int rn) =20 gen_helper_fjcvtzs(t, t, fpstatus); =20 - tcg_temp_free_ptr(fpstatus); - tcg_gen_ext32u_i64(cpu_reg(s, rd), t); tcg_gen_extrh_i64_i32(cpu_ZF, t); tcg_gen_movi_i32(cpu_CF, 0); tcg_gen_movi_i32(cpu_NF, 0); tcg_gen_movi_i32(cpu_VF, 0); - - tcg_temp_free_i64(t); } =20 /* Floating point <-> integer conversions @@ -7509,8 +7322,6 @@ static void do_ext64(DisasContext *s, TCGv_i64 tcg_le= ft, TCGv_i64 tcg_right, tcg_gen_shri_i64(tcg_right, tcg_right, pos); tcg_gen_shli_i64(tcg_tmp, tcg_left, 64 - pos); tcg_gen_or_i64(tcg_right, tcg_right, tcg_tmp); - - tcg_temp_free_i64(tcg_tmp); } =20 /* EXT @@ -7575,16 +7386,13 @@ static void disas_simd_ext(DisasContext *s, uint32_= t insn) tcg_hh =3D tcg_temp_new_i64(); read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_64); do_ext64(s, tcg_hh, tcg_resh, pos); - tcg_temp_free_i64(tcg_hh); } } =20 write_vec_element(s, tcg_resl, rd, 0, MO_64); - tcg_temp_free_i64(tcg_resl); if (is_q) { write_vec_element(s, tcg_resh, rd, 1, MO_64); } - tcg_temp_free_i64(tcg_resh); clear_vec_high(s, is_q, rd); } =20 @@ -7701,14 +7509,9 @@ static void disas_simd_zip_trn(DisasContext *s, uint= 32_t insn) } } =20 - tcg_temp_free_i64(tcg_res); - write_vec_element(s, tcg_resl, rd, 0, MO_64); - tcg_temp_free_i64(tcg_resl); - if (is_q) { write_vec_element(s, tcg_resh, rd, 1, MO_64); - tcg_temp_free_i64(tcg_resh); } clear_vec_high(s, is_q, rd); } @@ -7778,9 +7581,6 @@ static TCGv_i32 do_reduction_op(DisasContext *s, int = fpopcode, int rn, default: g_assert_not_reached(); } - - tcg_temp_free_i32(tcg_hi); - tcg_temp_free_i32(tcg_lo); return tcg_res; } } @@ -7908,12 +7708,8 @@ static void disas_simd_across_lanes(DisasContext *s,= uint32_t insn) TCGv_i32 tcg_res32 =3D do_reduction_op(s, fpopcode, rn, esize, (is_q ? 128 : 64), vmap, fpst= ); tcg_gen_extu_i32_i64(tcg_res, tcg_res32); - tcg_temp_free_i32(tcg_res32); - tcg_temp_free_ptr(fpst); } =20 - tcg_temp_free_i64(tcg_elt); - /* Now truncate the result to the width required for the final output = */ if (opcode =3D=3D 0x03) { /* SADDLV, UADDLV: result is 2*esize */ @@ -7937,7 +7733,6 @@ static void disas_simd_across_lanes(DisasContext *s, = uint32_t insn) } =20 write_fp_dreg(s, rd, tcg_res); - tcg_temp_free_i64(tcg_res); } =20 /* DUP (Element, Vector) @@ -8000,7 +7795,6 @@ static void handle_simd_dupes(DisasContext *s, int rd= , int rn, tmp =3D tcg_temp_new_i64(); read_vec_element(s, tmp, rn, index, size); write_fp_dreg(s, rd, tmp); - tcg_temp_free_i64(tmp); } =20 /* DUP (General) @@ -8068,8 +7862,6 @@ static void handle_simd_inse(DisasContext *s, int rd,= int rn, read_vec_element(s, tmp, rn, src_index, size); write_vec_element(s, tmp, rd, dst_index, size); =20 - tcg_temp_free_i64(tmp); - /* INS is considered a 128-bit write for SVE. */ clear_vec_high(s, true, rd); } @@ -8380,10 +8172,6 @@ static void disas_simd_scalar_pairwise(DisasContext = *s, uint32_t insn) } =20 write_fp_dreg(s, rd, tcg_res); - - tcg_temp_free_i64(tcg_op1); - tcg_temp_free_i64(tcg_op2); - tcg_temp_free_i64(tcg_res); } else { TCGv_i32 tcg_op1 =3D tcg_temp_new_i32(); TCGv_i32 tcg_op2 =3D tcg_temp_new_i32(); @@ -8435,14 +8223,6 @@ static void disas_simd_scalar_pairwise(DisasContext = *s, uint32_t insn) } =20 write_fp_sreg(s, rd, tcg_res); - - tcg_temp_free_i32(tcg_op1); - tcg_temp_free_i32(tcg_op2); - tcg_temp_free_i32(tcg_res); - } - - if (fpst) { - tcg_temp_free_ptr(fpst); } } =20 @@ -8527,10 +8307,6 @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res= , TCGv_i64 tcg_src, } else { tcg_gen_mov_i64(tcg_res, tcg_src); } - - if (extended_result) { - tcg_temp_free_i64(tcg_src_hi); - } } =20 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */ @@ -8596,9 +8372,6 @@ static void handle_scalar_simd_shri(DisasContext *s, } =20 write_fp_dreg(s, rd, tcg_rd); - - tcg_temp_free_i64(tcg_rn); - tcg_temp_free_i64(tcg_rd); } =20 /* SHL/SLI - Scalar shift left */ @@ -8631,9 +8404,6 @@ static void handle_scalar_simd_shli(DisasContext *s, = bool insert, } =20 write_fp_dreg(s, rd, tcg_rd); - - tcg_temp_free_i64(tcg_rn); - tcg_temp_free_i64(tcg_rd); } =20 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with @@ -8715,12 +8485,6 @@ static void handle_vec_simd_sqshrn(DisasContext *s, = bool is_scalar, bool is_q, } else { write_vec_element(s, tcg_final, rd, 1, MO_64); } - - tcg_temp_free_i64(tcg_rn); - tcg_temp_free_i64(tcg_rd); - tcg_temp_free_i32(tcg_rd_narrowed); - tcg_temp_free_i64(tcg_final); - clear_vec_high(s, is_q, rd); } =20 @@ -8781,8 +8545,6 @@ static void handle_simd_qshl(DisasContext *s, bool sc= alar, bool is_q, read_vec_element(s, tcg_op, rn, pass, MO_64); genfn(tcg_op, cpu_env, tcg_op, tcg_shift); write_vec_element(s, tcg_op, rd, pass, MO_64); - - tcg_temp_free_i64(tcg_op); } clear_vec_high(s, is_q, rd); } else { @@ -8828,8 +8590,6 @@ static void handle_simd_qshl(DisasContext *s, bool sc= alar, bool is_q, } else { write_vec_element_i32(s, tcg_op, rd, pass, MO_32); } - - tcg_temp_free_i32(tcg_op); } =20 if (!scalar) { @@ -8873,10 +8633,6 @@ static void handle_simd_intfp_conv(DisasContext *s, = int rd, int rn, write_vec_element(s, tcg_double, rd, pass, MO_64); } } - - tcg_temp_free_i64(tcg_int64); - tcg_temp_free_i64(tcg_double); - } else { TCGv_i32 tcg_int32 =3D tcg_temp_new_i32(); TCGv_i32 tcg_float =3D tcg_temp_new_i32(); @@ -8929,13 +8685,8 @@ static void handle_simd_intfp_conv(DisasContext *s, = int rd, int rn, write_vec_element_i32(s, tcg_float, rd, pass, size); } } - - tcg_temp_free_i32(tcg_int32); - tcg_temp_free_i32(tcg_float); } =20 - tcg_temp_free_ptr(tcg_fpst); - clear_vec_high(s, elements << size =3D=3D 16, rd); } =20 @@ -9039,7 +8790,6 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, gen_helper_vfp_tosqd(tcg_op, tcg_op, tcg_shift, tcg_fpstat= us); } write_vec_element(s, tcg_op, rd, pass, MO_64); - tcg_temp_free_i64(tcg_op); } clear_vec_high(s, is_q, rd); } else { @@ -9075,7 +8825,6 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, } else { write_vec_element_i32(s, tcg_op, rd, pass, size); } - tcg_temp_free_i32(tcg_op); } if (!is_scalar) { clear_vec_high(s, is_q, rd); @@ -9083,8 +8832,6 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, } =20 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); - tcg_temp_free_ptr(tcg_fpstatus); - tcg_temp_free_i32(tcg_rmode); } =20 /* AdvSIMD scalar shift by immediate @@ -9227,10 +8974,6 @@ static void disas_simd_scalar_three_reg_diff(DisasCo= ntext *s, uint32_t insn) } =20 write_fp_dreg(s, rd, tcg_res); - - tcg_temp_free_i64(tcg_op1); - tcg_temp_free_i64(tcg_op2); - tcg_temp_free_i64(tcg_res); } else { TCGv_i32 tcg_op1 =3D read_fp_hreg(s, rn); TCGv_i32 tcg_op2 =3D read_fp_hreg(s, rm); @@ -9251,7 +8994,6 @@ static void disas_simd_scalar_three_reg_diff(DisasCon= text *s, uint32_t insn) read_vec_element(s, tcg_op3, rd, 0, MO_32); gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_op3); - tcg_temp_free_i64(tcg_op3); break; } default: @@ -9260,10 +9002,6 @@ static void disas_simd_scalar_three_reg_diff(DisasCo= ntext *s, uint32_t insn) =20 tcg_gen_ext32u_i64(tcg_res, tcg_res); write_fp_dreg(s, rd, tcg_res); - - tcg_temp_free_i32(tcg_op1); - tcg_temp_free_i32(tcg_op2); - tcg_temp_free_i64(tcg_res); } } =20 @@ -9438,10 +9176,6 @@ static void handle_3same_float(DisasContext *s, int = size, int elements, } =20 write_vec_element(s, tcg_res, rd, pass, MO_64); - - tcg_temp_free_i64(tcg_res); - tcg_temp_free_i64(tcg_op1); - tcg_temp_free_i64(tcg_op2); } else { /* Single */ TCGv_i32 tcg_op1 =3D tcg_temp_new_i32(); @@ -9523,19 +9257,12 @@ static void handle_3same_float(DisasContext *s, int= size, int elements, =20 tcg_gen_extu_i32_i64(tcg_tmp, tcg_res); write_vec_element(s, tcg_tmp, rd, pass, MO_64); - tcg_temp_free_i64(tcg_tmp); } else { write_vec_element_i32(s, tcg_res, rd, pass, MO_32); } - - tcg_temp_free_i32(tcg_res); - tcg_temp_free_i32(tcg_op1); - tcg_temp_free_i32(tcg_op2); } } =20 - tcg_temp_free_ptr(fpst); - clear_vec_high(s, elements * (size ? 8 : 4) > 8, rd); } =20 @@ -9621,8 +9348,6 @@ static void disas_simd_scalar_three_reg_same(DisasCon= text *s, uint32_t insn) TCGv_i64 tcg_rm =3D read_fp_dreg(s, rm); =20 handle_3same_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rm); - tcg_temp_free_i64(tcg_rn); - tcg_temp_free_i64(tcg_rm); } else { /* Do a single operation on the lowest element in the vector. * We use the standard Neon helpers and rely on 0 OP 0 =3D=3D 0 wi= th @@ -9695,14 +9420,9 @@ static void disas_simd_scalar_three_reg_same(DisasCo= ntext *s, uint32_t insn) =20 genenvfn(tcg_rd32, cpu_env, tcg_rn, tcg_rm); tcg_gen_extu_i32_i64(tcg_rd, tcg_rd32); - tcg_temp_free_i32(tcg_rd32); - tcg_temp_free_i32(tcg_rn); - tcg_temp_free_i32(tcg_rm); } =20 write_fp_dreg(s, rd, tcg_rd); - - tcg_temp_free_i64(tcg_rd); } =20 /* AdvSIMD scalar three same FP16 @@ -9792,12 +9512,6 @@ static void disas_simd_scalar_three_reg_same_fp16(Di= sasContext *s, } =20 write_fp_sreg(s, rd, tcg_res); - - - tcg_temp_free_i32(tcg_res); - tcg_temp_free_i32(tcg_op1); - tcg_temp_free_i32(tcg_op2); - tcg_temp_free_ptr(fpst); } =20 /* AdvSIMD scalar three same extra @@ -9872,15 +9586,10 @@ static void disas_simd_scalar_three_reg_same_extra(= DisasContext *s, default: g_assert_not_reached(); } - tcg_temp_free_i32(ele1); - tcg_temp_free_i32(ele2); =20 res =3D tcg_temp_new_i64(); tcg_gen_extu_i32_i64(res, ele3); - tcg_temp_free_i32(ele3); - write_fp_dreg(s, rd, res); - tcg_temp_free_i64(res); } =20 static void handle_2misc_64(DisasContext *s, int opcode, bool u, @@ -10036,8 +9745,6 @@ static void handle_2misc_fcmp_zero(DisasContext *s, = int opcode, } write_vec_element(s, tcg_res, rd, pass, MO_64); } - tcg_temp_free_i64(tcg_res); - tcg_temp_free_i64(tcg_op); =20 clear_vec_high(s, !is_scalar, rd); } else { @@ -10110,14 +9817,11 @@ static void handle_2misc_fcmp_zero(DisasContext *s= , int opcode, write_vec_element_i32(s, tcg_res, rd, pass, size); } } - tcg_temp_free_i32(tcg_res); - tcg_temp_free_i32(tcg_op); + if (!is_scalar) { clear_vec_high(s, is_q, rd); } } - - tcg_temp_free_ptr(fpst); } =20 static void handle_2misc_reciprocal(DisasContext *s, int opcode, @@ -10149,8 +9853,6 @@ static void handle_2misc_reciprocal(DisasContext *s,= int opcode, } write_vec_element(s, tcg_res, rd, pass, MO_64); } - tcg_temp_free_i64(tcg_res); - tcg_temp_free_i64(tcg_op); clear_vec_high(s, !is_scalar, rd); } else { TCGv_i32 tcg_op =3D tcg_temp_new_i32(); @@ -10189,13 +9891,10 @@ static void handle_2misc_reciprocal(DisasContext *= s, int opcode, write_vec_element_i32(s, tcg_res, rd, pass, MO_32); } } - tcg_temp_free_i32(tcg_res); - tcg_temp_free_i32(tcg_op); if (!is_scalar) { clear_vec_high(s, is_q, rd); } } - tcg_temp_free_ptr(fpst); } =20 static void handle_2misc_narrow(DisasContext *s, bool scalar, @@ -10273,17 +9972,12 @@ static void handle_2misc_narrow(DisasContext *s, b= ool scalar, gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, fpst, ahp); gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, fpst, ahp); tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16); - tcg_temp_free_i32(tcg_lo); - tcg_temp_free_i32(tcg_hi); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(ahp); } break; case 0x36: /* BFCVTN, BFCVTN2 */ { TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_bfcvt_pair(tcg_res[pass], tcg_op, fpst); - tcg_temp_free_ptr(fpst); } break; case 0x56: /* FCVTXN, FCVTXN2 */ @@ -10302,13 +9996,10 @@ static void handle_2misc_narrow(DisasContext *s, b= ool scalar, } else if (genenvfn) { genenvfn(tcg_res[pass], cpu_env, tcg_op); } - - tcg_temp_free_i64(tcg_op); } =20 for (pass =3D 0; pass < 2; pass++) { write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32); - tcg_temp_free_i32(tcg_res[pass]); } clear_vec_high(s, is_q, rd); } @@ -10335,8 +10026,6 @@ static void handle_2misc_satacc(DisasContext *s, bo= ol is_scalar, bool is_u, } write_vec_element(s, tcg_rd, rd, pass, MO_64); } - tcg_temp_free_i64(tcg_rd); - tcg_temp_free_i64(tcg_rn); clear_vec_high(s, !is_scalar, rd); } else { TCGv_i32 tcg_rn =3D tcg_temp_new_i32(); @@ -10393,8 +10082,6 @@ static void handle_2misc_satacc(DisasContext *s, bo= ol is_scalar, bool is_u, } write_vec_element_i32(s, tcg_rd, rd, pass, MO_32); } - tcg_temp_free_i32(tcg_rd); - tcg_temp_free_i32(tcg_rn); clear_vec_high(s, is_q, rd); } } @@ -10546,8 +10233,6 @@ static void disas_simd_scalar_two_reg_misc(DisasCon= text *s, uint32_t insn) =20 handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rmode, tcg_fpsta= tus); write_fp_dreg(s, rd, tcg_rd); - tcg_temp_free_i64(tcg_rd); - tcg_temp_free_i64(tcg_rn); } else { TCGv_i32 tcg_rn =3D tcg_temp_new_i32(); TCGv_i32 tcg_rd =3D tcg_temp_new_i32(); @@ -10588,14 +10273,10 @@ static void disas_simd_scalar_two_reg_misc(DisasC= ontext *s, uint32_t insn) } =20 write_fp_sreg(s, rd, tcg_rd); - tcg_temp_free_i32(tcg_rd); - tcg_temp_free_i32(tcg_rn); } =20 if (is_fcvt) { gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); - tcg_temp_free_i32(tcg_rmode); - tcg_temp_free_ptr(tcg_fpstatus); } } =20 @@ -10772,9 +10453,6 @@ static void handle_vec_simd_shrn(DisasContext *s, b= ool is_q, } else { write_vec_element(s, tcg_final, rd, 1, MO_64); } - tcg_temp_free_i64(tcg_rn); - tcg_temp_free_i64(tcg_rd); - tcg_temp_free_i64(tcg_final); =20 clear_vec_high(s, is_q, rd); } @@ -10945,8 +10623,6 @@ static void handle_3rd_widening(DisasContext *s, in= t is_q, int is_u, int size, tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE, tcg_passres, tcg_op1, tcg_op2, tcg_tmp1, tcg_tmp2); - tcg_temp_free_i64(tcg_tmp1); - tcg_temp_free_i64(tcg_tmp2); break; } case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */ @@ -10977,13 +10653,6 @@ static void handle_3rd_widening(DisasContext *s, i= nt is_q, int is_u, int size, } else if (accop < 0) { tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres); } - - if (accop !=3D 0) { - tcg_temp_free_i64(tcg_passres); - } - - tcg_temp_free_i64(tcg_op1); - tcg_temp_free_i64(tcg_op2); } } else { /* size 0 or 1, generally helper functions */ @@ -11017,7 +10686,6 @@ static void handle_3rd_widening(DisasContext *s, in= t is_q, int is_u, int size, widenfn(tcg_passres, tcg_op1); gen_neon_addl(size, (opcode =3D=3D 2), tcg_passres, tcg_passres, tcg_op2_64); - tcg_temp_free_i64(tcg_op2_64); break; } case 5: /* SABAL, SABAL2, UABAL, UABAL2 */ @@ -11064,8 +10732,6 @@ static void handle_3rd_widening(DisasContext *s, in= t is_q, int is_u, int size, default: g_assert_not_reached(); } - tcg_temp_free_i32(tcg_op1); - tcg_temp_free_i32(tcg_op2); =20 if (accop !=3D 0) { if (opcode =3D=3D 9 || opcode =3D=3D 11) { @@ -11080,15 +10746,12 @@ static void handle_3rd_widening(DisasContext *s, = int is_q, int is_u, int size, gen_neon_addl(size, (accop < 0), tcg_res[pass], tcg_res[pass], tcg_passres); } - tcg_temp_free_i64(tcg_passres); } } } =20 write_vec_element(s, tcg_res[0], rd, 0, MO_64); write_vec_element(s, tcg_res[1], rd, 1, MO_64); - tcg_temp_free_i64(tcg_res[0]); - tcg_temp_free_i64(tcg_res[1]); } =20 static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size, @@ -11112,17 +10775,13 @@ static void handle_3rd_wide(DisasContext *s, int = is_q, int is_u, int size, read_vec_element(s, tcg_op1, rn, pass, MO_64); read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_32); widenfn(tcg_op2_wide, tcg_op2); - tcg_temp_free_i32(tcg_op2); tcg_res[pass] =3D tcg_temp_new_i64(); gen_neon_addl(size, (opcode =3D=3D 3), tcg_res[pass], tcg_op1, tcg_op2_wide); - tcg_temp_free_i64(tcg_op1); - tcg_temp_free_i64(tcg_op2_wide); } =20 for (pass =3D 0; pass < 2; pass++) { write_vec_element(s, tcg_res[pass], rd, pass, MO_64); - tcg_temp_free_i64(tcg_res[pass]); } } =20 @@ -11157,17 +10816,12 @@ static void handle_3rd_narrowing(DisasContext *s,= int is_q, int is_u, int size, =20 gen_neon_addl(size, (opcode =3D=3D 6), tcg_wideres, tcg_op1, tcg_o= p2); =20 - tcg_temp_free_i64(tcg_op1); - tcg_temp_free_i64(tcg_op2); - tcg_res[pass] =3D tcg_temp_new_i32(); gennarrow(tcg_res[pass], tcg_wideres); - tcg_temp_free_i64(tcg_wideres); } =20 for (pass =3D 0; pass < 2; pass++) { write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32); - tcg_temp_free_i32(tcg_res[pass]); } clear_vec_high(s, is_q, rd); } @@ -11394,14 +11048,10 @@ static void handle_simd_3same_pair(DisasContext *= s, int is_q, int u, int opcode, default: g_assert_not_reached(); } - - tcg_temp_free_i64(tcg_op1); - tcg_temp_free_i64(tcg_op2); } =20 for (pass =3D 0; pass < 2; pass++) { write_vec_element(s, tcg_res[pass], rd, pass, MO_64); - tcg_temp_free_i64(tcg_res[pass]); } } else { int maxpass =3D is_q ? 4 : 2; @@ -11473,21 +11123,13 @@ static void handle_simd_3same_pair(DisasContext *= s, int is_q, int u, int opcode, if (genfn) { genfn(tcg_res[pass], tcg_op1, tcg_op2); } - - tcg_temp_free_i32(tcg_op1); - tcg_temp_free_i32(tcg_op2); } =20 for (pass =3D 0; pass < maxpass; pass++) { write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); - tcg_temp_free_i32(tcg_res[pass]); } clear_vec_high(s, is_q, rd); } - - if (fpst) { - tcg_temp_free_ptr(fpst); - } } =20 /* Floating point op subgroup of C3.6.16. */ @@ -11744,10 +11386,6 @@ static void disas_simd_3same_int(DisasContext *s, = uint32_t insn) handle_3same_64(s, opcode, u, tcg_res, tcg_op1, tcg_op2); =20 write_vec_element(s, tcg_res, rd, pass, MO_64); - - tcg_temp_free_i64(tcg_res); - tcg_temp_free_i64(tcg_op1); - tcg_temp_free_i64(tcg_op2); } } else { for (pass =3D 0; pass < (is_q ? 4 : 2); pass++) { @@ -11832,10 +11470,6 @@ static void disas_simd_3same_int(DisasContext *s, = uint32_t insn) } =20 write_vec_element_i32(s, tcg_res, rd, pass, MO_32); - - tcg_temp_free_i32(tcg_res); - tcg_temp_free_i32(tcg_op1); - tcg_temp_free_i32(tcg_op2); } } clear_vec_high(s, is_q, rd); @@ -12006,12 +11640,7 @@ static void disas_simd_three_reg_same_fp16(DisasCo= ntext *s, uint32_t insn) =20 for (pass =3D 0; pass < maxpass; pass++) { write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16); - tcg_temp_free_i32(tcg_res[pass]); } - - tcg_temp_free_i32(tcg_op1); - tcg_temp_free_i32(tcg_op2); - } else { for (pass =3D 0; pass < elements; pass++) { TCGv_i32 tcg_op1 =3D tcg_temp_new_i32(); @@ -12091,14 +11720,9 @@ static void disas_simd_three_reg_same_fp16(DisasCo= ntext *s, uint32_t insn) } =20 write_vec_element_i32(s, tcg_res, rd, pass, MO_16); - tcg_temp_free_i32(tcg_res); - tcg_temp_free_i32(tcg_op1); - tcg_temp_free_i32(tcg_op2); } } =20 - tcg_temp_free_ptr(fpst); - clear_vec_high(s, is_q, rd); } =20 @@ -12310,11 +11934,9 @@ static void handle_2misc_widening(DisasContext *s,= int opcode, bool is_q, =20 read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_32); gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, cpu_env); - tcg_temp_free_i32(tcg_op); } for (pass =3D 0; pass < 2; pass++) { write_vec_element(s, tcg_res[pass], rd, pass, MO_64); - tcg_temp_free_i64(tcg_res[pass]); } } else { /* 16 -> 32 bit fp conversion */ @@ -12332,11 +11954,7 @@ static void handle_2misc_widening(DisasContext *s,= int opcode, bool is_q, } for (pass =3D 0; pass < 4; pass++) { write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32); - tcg_temp_free_i32(tcg_res[pass]); } - - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(ahp); } } =20 @@ -12380,7 +11998,6 @@ static void handle_rev(DisasContext *s, int opcode,= bool u, g_assert_not_reached(); } write_vec_element(s, tcg_tmp, rd, i, grp_size); - tcg_temp_free_i64(tcg_tmp); } clear_vec_high(s, is_q, rd); } else { @@ -12404,10 +12021,6 @@ static void handle_rev(DisasContext *s, int opcode= , bool u, } write_vec_element(s, tcg_rd, rd, 0, MO_64); write_vec_element(s, tcg_rd_hi, rd, 1, MO_64); - - tcg_temp_free_i64(tcg_rd_hi); - tcg_temp_free_i64(tcg_rd); - tcg_temp_free_i64(tcg_rn); } } =20 @@ -12441,9 +12054,6 @@ static void handle_2misc_pairwise(DisasContext *s, = int opcode, bool u, read_vec_element(s, tcg_op1, rd, pass, MO_64); tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_op1); } - - tcg_temp_free_i64(tcg_op1); - tcg_temp_free_i64(tcg_op2); } } else { for (pass =3D 0; pass < maxpass; pass++) { @@ -12471,7 +12081,6 @@ static void handle_2misc_pairwise(DisasContext *s, = int opcode, bool u, tcg_res[pass], tcg_op); } } - tcg_temp_free_i64(tcg_op); } } if (!is_q) { @@ -12479,7 +12088,6 @@ static void handle_2misc_pairwise(DisasContext *s, = int opcode, bool u, } for (pass =3D 0; pass < 2; pass++) { write_vec_element(s, tcg_res[pass], rd, pass, MO_64); - tcg_temp_free_i64(tcg_res[pass]); } } =20 @@ -12503,13 +12111,10 @@ static void handle_shll(DisasContext *s, bool is_= q, int size, int rn, int rd) tcg_res[pass] =3D tcg_temp_new_i64(); widenfn(tcg_res[pass], tcg_op); tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << size); - - tcg_temp_free_i32(tcg_op); } =20 for (pass =3D 0; pass < 2; pass++) { write_vec_element(s, tcg_res[pass], rd, pass, MO_64); - tcg_temp_free_i64(tcg_res[pass]); } } =20 @@ -12864,9 +12469,6 @@ static void disas_simd_two_reg_misc(DisasContext *s= , uint32_t insn) tcg_rmode, tcg_fpstatus); =20 write_vec_element(s, tcg_res, rd, pass, MO_64); - - tcg_temp_free_i64(tcg_res); - tcg_temp_free_i64(tcg_op); } } else { int pass; @@ -12989,19 +12591,12 @@ static void disas_simd_two_reg_misc(DisasContext = *s, uint32_t insn) } =20 write_vec_element_i32(s, tcg_res, rd, pass, MO_32); - - tcg_temp_free_i32(tcg_res); - tcg_temp_free_i32(tcg_op); } } clear_vec_high(s, is_q, rd); =20 if (need_rmode) { gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); - tcg_temp_free_i32(tcg_rmode); - } - if (need_fpstatus) { - tcg_temp_free_ptr(tcg_fpstatus); } } =20 @@ -13227,9 +12822,6 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) /* limit any sign extension going on */ tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff); write_fp_sreg(s, rd, tcg_res); - - tcg_temp_free_i32(tcg_res); - tcg_temp_free_i32(tcg_op); } else { for (pass =3D 0; pass < (is_q ? 8 : 4); pass++) { TCGv_i32 tcg_op =3D tcg_temp_new_i32(); @@ -13283,9 +12875,6 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) } =20 write_vec_element_i32(s, tcg_res, rd, pass, MO_16); - - tcg_temp_free_i32(tcg_res); - tcg_temp_free_i32(tcg_op); } =20 clear_vec_high(s, is_q, rd); @@ -13293,11 +12882,6 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) =20 if (tcg_rmode) { gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); - tcg_temp_free_i32(tcg_rmode); - } - - if (tcg_fpstatus) { - tcg_temp_free_ptr(tcg_fpstatus); } } =20 @@ -13567,7 +13151,6 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) size =3D=3D MO_64 ? gen_helper_gvec_fcmlas_idx : gen_helper_gvec_fcmlah_idx); - tcg_temp_free_ptr(fpst); } return; =20 @@ -13672,11 +13255,8 @@ static void disas_simd_indexed(DisasContext *s, ui= nt32_t insn) } =20 write_vec_element(s, tcg_res, rd, pass, MO_64); - tcg_temp_free_i64(tcg_op); - tcg_temp_free_i64(tcg_res); } =20 - tcg_temp_free_i64(tcg_idx); clear_vec_high(s, !is_scalar, rd); } else if (!is_long) { /* 32 bit floating point, or 16 or 32 bit integer. @@ -13850,12 +13430,8 @@ static void disas_simd_indexed(DisasContext *s, ui= nt32_t insn) } else { write_vec_element_i32(s, tcg_res, rd, pass, MO_32); } - - tcg_temp_free_i32(tcg_op); - tcg_temp_free_i32(tcg_res); } =20 - tcg_temp_free_i32(tcg_idx); clear_vec_high(s, is_q, rd); } else { /* long ops: 16x16->32 or 32x32->64 */ @@ -13896,7 +13472,6 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) } =20 tcg_gen_mul_i64(tcg_passres, tcg_op, tcg_idx); - tcg_temp_free_i64(tcg_op); =20 if (satop) { /* saturating, doubling */ @@ -13929,9 +13504,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) default: g_assert_not_reached(); } - tcg_temp_free_i64(tcg_passres); } - tcg_temp_free_i64(tcg_idx); =20 clear_vec_high(s, !is_scalar, rd); } else { @@ -13977,7 +13550,6 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, tcg_passres, tcg_pas= sres); } - tcg_temp_free_i32(tcg_op); =20 if (opcode =3D=3D 0xa || opcode =3D=3D 0xb) { continue; @@ -14006,9 +13578,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) default: g_assert_not_reached(); } - tcg_temp_free_i64(tcg_passres); } - tcg_temp_free_i32(tcg_idx); =20 if (is_scalar) { tcg_gen_ext32u_i64(tcg_res[0], tcg_res[0]); @@ -14021,13 +13591,8 @@ static void disas_simd_indexed(DisasContext *s, ui= nt32_t insn) =20 for (pass =3D 0; pass < 2; pass++) { write_vec_element(s, tcg_res[pass], rd, pass, MO_64); - tcg_temp_free_i64(tcg_res[pass]); } } - - if (fpst) { - tcg_temp_free_ptr(fpst); - } } =20 /* Crypto AES @@ -14407,12 +13972,6 @@ static void disas_crypto_four_reg(DisasContext *s,= uint32_t insn) } write_vec_element(s, tcg_res[0], rd, 0, MO_64); write_vec_element(s, tcg_res[1], rd, 1, MO_64); - - tcg_temp_free_i64(tcg_op1); - tcg_temp_free_i64(tcg_op2); - tcg_temp_free_i64(tcg_op3); - tcg_temp_free_i64(tcg_res[0]); - tcg_temp_free_i64(tcg_res[1]); } else { TCGv_i32 tcg_op1, tcg_op2, tcg_op3, tcg_res, tcg_zero; =20 @@ -14435,11 +13994,6 @@ static void disas_crypto_four_reg(DisasContext *s,= uint32_t insn) write_vec_element_i32(s, tcg_zero, rd, 1, MO_32); write_vec_element_i32(s, tcg_zero, rd, 2, MO_32); write_vec_element_i32(s, tcg_res, rd, 3, MO_32); - - tcg_temp_free_i32(tcg_op1); - tcg_temp_free_i32(tcg_op2); - tcg_temp_free_i32(tcg_op3); - tcg_temp_free_i32(tcg_res); } } =20 --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677475912; cv=none; d=zohomail.com; s=zohoarc; b=D0os34UDjKr5DLoMiC88x/kdKemN0NjgsZG2BGXRfJN+a3GmJKGAbDW+Fq8z3G9h011myT5GnWhvNTWhXHMUMZ8hyR1ovNm6oM94Ce8I4pp1ihduanKIas9Dj2MzDwer6CzpGWbz21YEWObMLPkzud3tK2gdLOszLJBizZuRuYw= ARC-Message-Signature: i=1; a=rsa-sha256; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.25.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:25:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N6B+a0N7tu/9UM+UAFolg4I0Ga2IK7hy9mNAOGH/dPg=; b=gJdK7aZt1u6+wWiGl1LYeNpXxYb3+8ND4VW+6DB/lxPFH0LVS6lgzwz+RFBEiHXDUl Wx2ksEBy+GIjAR169yqfWsXAjZYVB61RHCH7cLovDFZB1rJDBdyJ0o5FfnzEBFS04Rmf lFGGSpMDTEG+EE4r0UNGtEPiKMKRgDPWInM6ydpKkxodp8A5JCxMtD63h1JsW/q+t64K jES4lFteJg0Bfg4wg8/8GyrGSQLbNpP0lMZGLod1oj7nsCVVUjf8Ite/a4ZoIMZX1w11 dYGqwUgs/3b5ztfOruJmJ/gXoIaYK8xTqnjSlkgA29mdz+gULKHNYb43CBlMLSO7oqPE HbBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N6B+a0N7tu/9UM+UAFolg4I0Ga2IK7hy9mNAOGH/dPg=; b=f3nd93L05by2NUqa76OdP3OxbEO/PyyDUpT+jvWckQaJ6DbNLIjcQbj7jCs0nSfCrP 2SGOjUNXhiSsR19wkt/eACLtmk8nWT89fPL6l8tGP4wvirH4PTcgXuHHiWOwR93jCWIQ 07v+6QhW5ZzZcoEp3i9O5ZWZuXnmUPqJz7cznqqPCFW1B2EYQJFDXAj3MRGXTqjwnlsX HhuCgrFfdfIoUR03dDUQ7jbAcfIa0IeK/S4wnxN26eR6oTr06Mn9Zpsk7ftbGUerqFLh 4FanaaMM+LA/TpO/2w8rorZXM3uhTs3+HHKUeBbs8tTbzfn6SCUqesshbP34VTrVoYgk T54Q== X-Gm-Message-State: AO0yUKXEprLnNezN0Zhbu9a3TPe48durm8efe4D4Wq3FFsnjECphi/BA ytuP5CbS24yHYNsy7pFJ8RRD4wVowcn0jytwH4VFZQ== X-Google-Smtp-Source: AK7set8Sw6LABw9Um0lgl6lAMOhowI/V18JbvsWtqZmUH5YmEIdK18hPklc2kIMXOHerBA5iAHTTZQ== X-Received: by 2002:a17:902:fb90:b0:19c:d97f:5d20 with SMTP id lg16-20020a170902fb9000b0019cd97f5d20mr8882982plb.38.1677475540543; Sun, 26 Feb 2023 21:25:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 11/76] target/arm: Drop tcg_temp_free from translator-m-nocp.c Date: Sun, 26 Feb 2023 19:24:00 -1000 Message-Id: <20230227052505.352889-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475913543100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/arm/translate-m-nocp.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c index 5df7d46120..9a89aab785 100644 --- a/target/arm/translate-m-nocp.c +++ b/target/arm/translate-m-nocp.c @@ -91,7 +91,6 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_= VLSTM *a) } else { gen_helper_v7m_vlstm(cpu_env, fptr); } - tcg_temp_free_i32(fptr); =20 clear_eci_state(s); =20 @@ -303,8 +302,6 @@ static void gen_branch_fpInactive(DisasContext *s, TCGC= ond cond, tcg_gen_andi_i32(fpca, fpca, R_V7M_CONTROL_FPCA_MASK); tcg_gen_or_i32(fpca, fpca, aspen); tcg_gen_brcondi_i32(tcg_invert_cond(cond), fpca, 0, label); - tcg_temp_free_i32(aspen); - tcg_temp_free_i32(fpca); } =20 static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, @@ -328,7 +325,6 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, case ARM_VFP_FPSCR: tmp =3D loadfn(s, opaque, true); gen_helper_vfp_set_fpscr(cpu_env, tmp); - tcg_temp_free_i32(tmp); gen_lookup_tb(s); break; case ARM_VFP_FPSCR_NZCVQC: @@ -351,7 +347,6 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK); tcg_gen_or_i32(fpscr, fpscr, tmp); store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]); - tcg_temp_free_i32(tmp); break; } case ARM_VFP_FPCXT_NS: @@ -400,8 +395,6 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); gen_helper_vfp_set_fpscr(cpu_env, tmp); s->base.is_jmp =3D DISAS_UPDATE_NOCHAIN; - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(sfpa); break; } case ARM_VFP_VPR: @@ -423,7 +416,6 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH); store_cpu_field(vpr, v7m.vpr); s->base.is_jmp =3D DISAS_UPDATE_NOCHAIN; - tcg_temp_free_i32(tmp); break; } default: @@ -491,7 +483,6 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT); tcg_gen_or_i32(tmp, tmp, sfpa); - tcg_temp_free_i32(sfpa); /* * Store result before updating FPSCR etc, in case * it is a memory write which causes an exception. @@ -505,7 +496,6 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, store_cpu_field(control, v7m.control[M_REG_S]); fpscr =3D load_cpu_field(v7m.fpdscr[M_REG_NS]); gen_helper_vfp_set_fpscr(cpu_env, fpscr); - tcg_temp_free_i32(fpscr); lookup_tb =3D true; break; } @@ -546,7 +536,6 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT); tcg_gen_or_i32(tmp, tmp, sfpa); - tcg_temp_free_i32(control); /* Store result before updating FPSCR, in case it faults */ storefn(s, opaque, tmp, true); /* If SFPA is zero then set FPSCR from FPDSCR_NS */ @@ -554,9 +543,6 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, tcg_constant_i32(0), fpdscr, fpscr); gen_helper_vfp_set_fpscr(cpu_env, fpscr); - tcg_temp_free_i32(sfpa); - tcg_temp_free_i32(fpdscr); - tcg_temp_free_i32(fpscr); break; } case ARM_VFP_VPR: @@ -598,7 +584,6 @@ static void fp_sysreg_to_gpr(DisasContext *s, void *opa= que, TCGv_i32 value, if (a->rt =3D=3D 15) { /* Set the 4 flag bits in the CPSR */ gen_set_nzcv(value); - tcg_temp_free_i32(value); } else { store_reg(s, a->rt, value); } @@ -666,7 +651,6 @@ static void fp_sysreg_to_memory(DisasContext *s, void *= opaque, TCGv_i32 value, if (do_access) { gen_aa32_st_i32(s, value, addr, get_mem_index(s), MO_UL | MO_ALIGN | s->be_data); - tcg_temp_free_i32(value); } =20 if (a->w) { @@ -675,8 +659,6 @@ static void fp_sysreg_to_memory(DisasContext *s, void *= opaque, TCGv_i32 value, tcg_gen_addi_i32(addr, addr, offset); } store_reg(s, a->rn, addr); - } else { - tcg_temp_free_i32(addr); } } =20 @@ -717,8 +699,6 @@ static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, vo= id *opaque, tcg_gen_addi_i32(addr, addr, offset); } store_reg(s, a->rn, addr); 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Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/arm/translate-mve.c | 52 -------------------------------------- 1 file changed, 52 deletions(-) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index db7ea3f603..798b4fddfe 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -178,7 +178,6 @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, = MVEGenLdStFn *fn, =20 qreg =3D mve_qreg_ptr(a->qd); fn(cpu_env, qreg, addr); - tcg_temp_free_ptr(qreg); =20 /* * Writeback always happens after the last beat of the insn, @@ -189,8 +188,6 @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, = MVEGenLdStFn *fn, tcg_gen_addi_i32(addr, addr, offset); } store_reg(s, a->rn, addr); - } else { - tcg_temp_free_i32(addr); } mve_update_eci(s); return true; @@ -242,9 +239,6 @@ static bool do_ldst_sg(DisasContext *s, arg_vldst_sg *a= , MVEGenLdStSGFn fn) qd =3D mve_qreg_ptr(a->qd); qm =3D mve_qreg_ptr(a->qm); fn(cpu_env, qd, qm, addr); - tcg_temp_free_ptr(qd); - tcg_temp_free_ptr(qm); - tcg_temp_free_i32(addr); mve_update_eci(s); return true; } @@ -341,8 +335,6 @@ static bool do_ldst_sg_imm(DisasContext *s, arg_vldst_s= g_imm *a, qd =3D mve_qreg_ptr(a->qd); qm =3D mve_qreg_ptr(a->qm); fn(cpu_env, qd, qm, tcg_constant_i32(offset)); - tcg_temp_free_ptr(qd); - tcg_temp_free_ptr(qm); mve_update_eci(s); return true; } @@ -414,8 +406,6 @@ static bool do_vldst_il(DisasContext *s, arg_vldst_il *= a, MVEGenLdStIlFn *fn, if (a->w) { tcg_gen_addi_i32(rn, rn, addrinc); store_reg(s, a->rn, rn); - } else { - tcg_temp_free_i32(rn); } mve_update_and_store_eci(s); return true; @@ -506,9 +496,7 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) qd =3D mve_qreg_ptr(a->qd); tcg_gen_dup_i32(a->size, rt, rt); gen_helper_mve_vdup(cpu_env, qd, rt); - tcg_temp_free_ptr(qd); } - tcg_temp_free_i32(rt); mve_update_eci(s); return true; } @@ -534,8 +522,6 @@ static bool do_1op_vec(DisasContext *s, arg_1op *a, MVE= GenOneOpFn fn, qd =3D mve_qreg_ptr(a->qd); qm =3D mve_qreg_ptr(a->qm); fn(cpu_env, qd, qm); - tcg_temp_free_ptr(qd); - tcg_temp_free_ptr(qm); } mve_update_eci(s); return true; @@ -631,8 +617,6 @@ static bool do_vcvt_rmode(DisasContext *s, arg_1op *a, qd =3D mve_qreg_ptr(a->qd); qm =3D mve_qreg_ptr(a->qm); fn(cpu_env, qd, qm, tcg_constant_i32(arm_rmode_to_sf(rmode))); - tcg_temp_free_ptr(qd); - tcg_temp_free_ptr(qm); mve_update_eci(s); return true; } @@ -821,9 +805,6 @@ static bool do_2op_vec(DisasContext *s, arg_2op *a, MVE= GenTwoOpFn fn, qn =3D mve_qreg_ptr(a->qn); qm =3D mve_qreg_ptr(a->qm); fn(cpu_env, qd, qn, qm); - tcg_temp_free_ptr(qd); - tcg_temp_free_ptr(qn); - tcg_temp_free_ptr(qm); } mve_update_eci(s); return true; @@ -1076,9 +1057,6 @@ static bool do_2op_scalar(DisasContext *s, arg_2scala= r *a, qn =3D mve_qreg_ptr(a->qn); rm =3D load_reg(s, a->rm); fn(cpu_env, qd, qn, rm); - tcg_temp_free_i32(rm); - tcg_temp_free_ptr(qd); - tcg_temp_free_ptr(qn); mve_update_eci(s); return true; } @@ -1204,15 +1182,11 @@ static bool do_long_dual_acc(DisasContext *s, arg_v= mlaldav *a, rdalo =3D load_reg(s, a->rdalo); rdahi =3D load_reg(s, a->rdahi); tcg_gen_concat_i32_i64(rda, rdalo, rdahi); - tcg_temp_free_i32(rdalo); - tcg_temp_free_i32(rdahi); } else { rda =3D tcg_const_i64(0); } =20 fn(rda, cpu_env, qn, qm, rda); - tcg_temp_free_ptr(qn); - tcg_temp_free_ptr(qm); =20 rdalo =3D tcg_temp_new_i32(); rdahi =3D tcg_temp_new_i32(); @@ -1220,7 +1194,6 @@ static bool do_long_dual_acc(DisasContext *s, arg_vml= aldav *a, tcg_gen_extrh_i64_i32(rdahi, rda); store_reg(s, a->rdalo, rdalo); store_reg(s, a->rdahi, rdahi); - tcg_temp_free_i64(rda); mve_update_eci(s); return true; } @@ -1312,8 +1285,6 @@ static bool do_dual_acc(DisasContext *s, arg_vmladav = *a, MVEGenDualAccOpFn *fn) =20 fn(rda, cpu_env, qn, qm, rda); store_reg(s, a->rda, rda); - tcg_temp_free_ptr(qn); - tcg_temp_free_ptr(qm); =20 mve_update_eci(s); return true; @@ -1451,7 +1422,6 @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a) qm =3D mve_qreg_ptr(a->qm); fns[a->size][a->u](rda, cpu_env, qm, rda); store_reg(s, a->rda, rda); - tcg_temp_free_ptr(qm); =20 mve_update_eci(s); return true; @@ -1494,8 +1464,6 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV = *a) rdalo =3D load_reg(s, a->rdalo); rdahi =3D load_reg(s, a->rdahi); tcg_gen_concat_i32_i64(rda, rdalo, rdahi); - tcg_temp_free_i32(rdalo); - tcg_temp_free_i32(rdahi); } else { /* Accumulate starting at zero */ rda =3D tcg_const_i64(0); @@ -1507,7 +1475,6 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV = *a) } else { gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda); } - tcg_temp_free_ptr(qm); =20 rdalo =3D tcg_temp_new_i32(); rdahi =3D tcg_temp_new_i32(); @@ -1515,7 +1482,6 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV = *a) tcg_gen_extrh_i64_i32(rdahi, rda); store_reg(s, a->rdalo, rdalo); store_reg(s, a->rdahi, rdahi); - tcg_temp_free_i64(rda); mve_update_eci(s); return true; } @@ -1543,7 +1509,6 @@ static bool do_1imm(DisasContext *s, arg_1imm *a, MVE= GenOneOpImmFn *fn, } else { qd =3D mve_qreg_ptr(a->qd); fn(cpu_env, qd, tcg_constant_i64(imm)); - tcg_temp_free_ptr(qd); } mve_update_eci(s); return true; @@ -1616,8 +1581,6 @@ static bool do_2shift_vec(DisasContext *s, arg_2shift= *a, MVEGenTwoOpShiftFn fn, qd =3D mve_qreg_ptr(a->qd); qm =3D mve_qreg_ptr(a->qm); fn(cpu_env, qd, qm, tcg_constant_i32(shift)); - tcg_temp_free_ptr(qd); - tcg_temp_free_ptr(qm); } mve_update_eci(s); return true; @@ -1723,8 +1686,6 @@ static bool do_2shift_scalar(DisasContext *s, arg_shl= _scalar *a, qda =3D mve_qreg_ptr(a->qda); rm =3D load_reg(s, a->rm); fn(cpu_env, qda, qda, rm); - tcg_temp_free_ptr(qda); - tcg_temp_free_i32(rm); mve_update_eci(s); return true; } @@ -1868,7 +1829,6 @@ static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a) rdm =3D load_reg(s, a->rdm); gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm)); store_reg(s, a->rdm, rdm); - tcg_temp_free_ptr(qd); mve_update_eci(s); return true; } @@ -1898,7 +1858,6 @@ static bool do_vidup(DisasContext *s, arg_vidup *a, M= VEGenVIDUPFn *fn) rn =3D load_reg(s, a->rn); fn(rn, cpu_env, qd, rn, tcg_constant_i32(a->imm)); store_reg(s, a->rn, rn); - tcg_temp_free_ptr(qd); mve_update_eci(s); return true; } @@ -1934,8 +1893,6 @@ static bool do_viwdup(DisasContext *s, arg_viwdup *a,= MVEGenVIWDUPFn *fn) rm =3D load_reg(s, a->rm); fn(rn, cpu_env, qd, rn, rm, tcg_constant_i32(a->imm)); store_reg(s, a->rn, rn); - tcg_temp_free_ptr(qd); - tcg_temp_free_i32(rm); mve_update_eci(s); return true; } @@ -2001,8 +1958,6 @@ static bool do_vcmp(DisasContext *s, arg_vcmp *a, MVE= GenCmpFn *fn) qn =3D mve_qreg_ptr(a->qn); qm =3D mve_qreg_ptr(a->qm); fn(cpu_env, qn, qm); - tcg_temp_free_ptr(qn); - tcg_temp_free_ptr(qm); if (a->mask) { /* VPT */ gen_vpst(s, a->mask); @@ -2034,8 +1989,6 @@ static bool do_vcmp_scalar(DisasContext *s, arg_vcmp_= scalar *a, rm =3D load_reg(s, a->rm); } fn(cpu_env, qn, rm); - tcg_temp_free_ptr(qn); - tcg_temp_free_i32(rm); if (a->mask) { /* VPT */ gen_vpst(s, a->mask); @@ -2138,7 +2091,6 @@ static bool do_vmaxv(DisasContext *s, arg_vmaxv *a, M= VEGenVADDVFn fn) rda =3D load_reg(s, a->rda); fn(rda, cpu_env, qm, rda); store_reg(s, a->rda, rda); - tcg_temp_free_ptr(qm); mve_update_eci(s); return true; } @@ -2203,8 +2155,6 @@ static bool do_vabav(DisasContext *s, arg_vabav *a, M= VEGenVABAVFn *fn) rda =3D load_reg(s, a->rda); fn(rda, cpu_env, qn, qm, rda); store_reg(s, a->rda, rda); - tcg_temp_free_ptr(qm); - tcg_temp_free_ptr(qn); mve_update_eci(s); return true; } @@ -2297,12 +2247,10 @@ static bool trans_VMOV_from_2gp(DisasContext *s, ar= g_VMOV_to_2gp *a) if (!mve_skip_vmov(s, vd, a->idx, MO_32)) { tmp =3D load_reg(s, a->rt); write_neon_element32(tmp, vd, a->idx, MO_32); - tcg_temp_free_i32(tmp); } if (!mve_skip_vmov(s, vd + 1, a->idx, MO_32)) { tmp =3D load_reg(s, a->rt2); write_neon_element32(tmp, vd + 1, a->idx, MO_32); - tcg_temp_free_i32(tmp); } =20 mve_update_and_store_eci(s); --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.25.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:25:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WiwFjCR7gVoljxenCQXrfcALDaPAGhUgclRRM6SrQmE=; b=juTiH2f9DAP1Z44gkyhm5jd5lnUZELkgTdCwLupp79S/eO8BMHBNphKGzBGukUmKpy ftC8o3b9BZJahtjX52V/57VZ1AXqt8m36juKx1vO0GCsuSpU0scAyTvkmAY5pTGHYw08 x/Hq0sbWs1W5oGVPrI2qQ4nSM3b0SZB80kPL39xV3vmHuB/RSbPV7/RcNS4xguYsPmzl wIiXdwFq44RIt0f+Pi4pPUoVy4g2YHFb73DTbh6ic3Yhs5iy+LtSWP23qz6+o3GG3U2O ogNVlpwS+7FC3CHnhqGTz46o6yv7bq+cHZRLXJAMunbmLrSq8xC4I5RNWQ2HXJao55/s QljA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WiwFjCR7gVoljxenCQXrfcALDaPAGhUgclRRM6SrQmE=; b=P4qAhBxjRa1Kq90iENBjULbup71UWBqVIYLqkDBrkDIKih1HgsiTQdmUW/ypU7aDzq fNQ3d7z8yUYVG3zqIUdUlL+T1aBSNW4FCBkOlFVHTXAAmrRt+BzwP82ljGghH54BBysk pih3ODxKlK23F/4H6naS8rrN/H/SiZ8Y4jvRd4bwnWTWnP0vSA3Jt0Nem4vtaS12XiBa /Ol8c/tjo76amqmNvPvrNZ+d4a15o1Bav7X83qmFDkAPBDxm/QDUvcNTY2THEeC7hrz+ KpoH9jqR7DVG1yngfn29Degh41GtXmvh70AKgPnJ6Cz5WcrKmN+ITZYdddJnJRP3f4+V gPSw== X-Gm-Message-State: AO0yUKWIepC68c1n3RLEzH4GM5XUiqrKHT7XhlcLjNl7Ms1Hpv/Ppb3q LpF61X3cqDOBqdzh2RtNz65XImSHOoydw82OWeI= X-Google-Smtp-Source: AK7set/FHJwjP+8akggij2G/v1pWRO5eWpxpfKrra40OOrvdI3IyCwqELZPfxDpmGij8gt7brzf+2A== X-Received: by 2002:a17:902:e745:b0:19a:839d:b682 with SMTP id p5-20020a170902e74500b0019a839db682mr27503075plf.17.1677475545870; Sun, 26 Feb 2023 21:25:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 13/76] target/arm: Drop tcg_temp_free from translator-neon.c Date: Sun, 26 Feb 2023 19:24:02 -1000 Message-Id: <20230227052505.352889-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475893379100003 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/arm/translate-neon.c | 131 +----------------------------------- 1 file changed, 1 insertion(+), 130 deletions(-) diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c index 4016339d46..af8685a4ac 100644 --- a/target/arm/translate-neon.c +++ b/target/arm/translate-neon.c @@ -182,7 +182,6 @@ static bool do_neon_ddda_fpst(DisasContext *s, int q, i= nt vd, int vn, int vm, vfp_reg_offset(1, vm), vfp_reg_offset(1, vd), fpst, opr_sz, opr_sz, data, fn_gvec_ptr); - tcg_temp_free_ptr(fpst); return true; } =20 @@ -236,7 +235,6 @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a) vfp_reg_offset(1, a->vm), fpst, opr_sz, opr_sz, a->rot, fn_gvec_ptr); - tcg_temp_free_ptr(fpst); return true; } =20 @@ -433,7 +431,6 @@ static void gen_neon_ldst_base_update(DisasContext *s, = int rm, int rn, TCGv_i32 index; index =3D load_reg(s, rm); tcg_gen_add_i32(base, base, index); - tcg_temp_free_i32(index); } store_reg(s, rn, base); } @@ -536,8 +533,6 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_V= LDST_multiple *a) } } } - tcg_temp_free_i32(addr); - tcg_temp_free_i64(tmp64); =20 gen_neon_ldst_base_update(s, a->rm, a->rn, nregs * interleave * 8); return true; @@ -630,8 +625,6 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VL= D_all_lanes *a) /* Subsequent memory operations inherit alignment */ mop &=3D ~MO_AMASK; } - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(addr); =20 gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << size) * nregs); =20 @@ -751,8 +744,6 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLD= ST_single *a) /* Subsequent memory operations inherit alignment */ mop &=3D ~MO_AMASK; } - tcg_temp_free_i32(addr); - tcg_temp_free_i32(tmp); =20 gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << a->size) * nregs); =20 @@ -1061,9 +1052,6 @@ static bool do_3same_pair(DisasContext *s, arg_3same = *a, NeonGenTwoOpFn *fn) write_neon_element32(tmp, a->vd, 0, MO_32); write_neon_element32(tmp3, a->vd, 1, MO_32); =20 - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); return true; } =20 @@ -1126,7 +1114,6 @@ DO_3SAME_VQDMULH(VQRDMULH, qrdmulh) TCGv_ptr fpst =3D fpstatus_ptr(FPST); \ tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpst, \ oprsz, maxsz, 0, FUNC); \ - tcg_temp_free_ptr(fpst); \ } =20 #define DO_3S_FP_GVEC(INSN,SFUNC,HFUNC) \ @@ -1225,7 +1212,6 @@ static bool do_3same_fp_pair(DisasContext *s, arg_3sa= me *a, vfp_reg_offset(1, a->vn), vfp_reg_offset(1, a->vm), fpstatus, 8, 8, 0, fn); - tcg_temp_free_ptr(fpstatus); =20 return true; } @@ -1358,7 +1344,6 @@ static bool do_2shift_env_64(DisasContext *s, arg_2re= g_shift *a, read_neon_element64(tmp, a->vm, pass, MO_64); fn(tmp, cpu_env, tmp, constimm); write_neon_element64(tmp, a->vd, pass, MO_64); - tcg_temp_free_i64(tmp); } return true; } @@ -1403,7 +1388,6 @@ static bool do_2shift_env_32(DisasContext *s, arg_2re= g_shift *a, fn(tmp, cpu_env, tmp, constimm); write_neon_element32(tmp, a->vd, pass, MO_32); } - tcg_temp_free_i32(tmp); return true; } =20 @@ -1474,10 +1458,6 @@ static bool do_2shift_narrow_64(DisasContext *s, arg= _2reg_shift *a, narrowfn(rd, cpu_env, rm2); write_neon_element32(rd, a->vd, 1, MO_32); =20 - tcg_temp_free_i32(rd); - tcg_temp_free_i64(rm1); - tcg_temp_free_i64(rm2); - return true; } =20 @@ -1537,22 +1517,17 @@ static bool do_2shift_narrow_32(DisasContext *s, ar= g_2reg_shift *a, shiftfn(rm2, rm2, constimm); =20 tcg_gen_concat_i32_i64(rtmp, rm1, rm2); - tcg_temp_free_i32(rm2); =20 narrowfn(rm1, cpu_env, rtmp); write_neon_element32(rm1, a->vd, 0, MO_32); - tcg_temp_free_i32(rm1); =20 shiftfn(rm3, rm3, constimm); shiftfn(rm4, rm4, constimm); =20 tcg_gen_concat_i32_i64(rtmp, rm3, rm4); - tcg_temp_free_i32(rm4); =20 narrowfn(rm3, cpu_env, rtmp); - tcg_temp_free_i64(rtmp); write_neon_element32(rm3, a->vd, 1, MO_32); - tcg_temp_free_i32(rm3); return true; } =20 @@ -1660,7 +1635,6 @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_sh= ift *a, tmp =3D tcg_temp_new_i64(); =20 widenfn(tmp, rm0); - tcg_temp_free_i32(rm0); if (a->shift !=3D 0) { tcg_gen_shli_i64(tmp, tmp, a->shift); tcg_gen_andi_i64(tmp, tmp, ~widen_mask); @@ -1668,13 +1642,11 @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_= shift *a, write_neon_element64(tmp, a->vd, 0, MO_64); =20 widenfn(tmp, rm1); - tcg_temp_free_i32(rm1); if (a->shift !=3D 0) { tcg_gen_shli_i64(tmp, tmp, a->shift); tcg_gen_andi_i64(tmp, tmp, ~widen_mask); } write_neon_element64(tmp, a->vd, 1, MO_64); - tcg_temp_free_i64(tmp); return true; } =20 @@ -1733,7 +1705,6 @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift= *a, =20 fpst =3D fpstatus_ptr(a->size =3D=3D MO_16 ? FPST_STD_F16 : FPST_STD); tcg_gen_gvec_2_ptr(rd_ofs, rm_ofs, fpst, vec_size, vec_size, a->shift,= fn); - tcg_temp_free_ptr(fpst); return true; } =20 @@ -1849,7 +1820,6 @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff= *a, TCGv_i32 tmp =3D tcg_temp_new_i32(); read_neon_element32(tmp, a->vn, 0, MO_32); widenfn(rn0_64, tmp); - tcg_temp_free_i32(tmp); } if (src2_mop >=3D 0) { read_neon_element64(rm_64, a->vm, 0, src2_mop); @@ -1857,7 +1827,6 @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff= *a, TCGv_i32 tmp =3D tcg_temp_new_i32(); read_neon_element32(tmp, a->vm, 0, MO_32); widenfn(rm_64, tmp); - tcg_temp_free_i32(tmp); } =20 opfn(rn0_64, rn0_64, rm_64); @@ -1872,7 +1841,6 @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff= *a, TCGv_i32 tmp =3D tcg_temp_new_i32(); read_neon_element32(tmp, a->vn, 1, MO_32); widenfn(rn1_64, tmp); - tcg_temp_free_i32(tmp); } if (src2_mop >=3D 0) { read_neon_element64(rm_64, a->vm, 1, src2_mop); @@ -1880,7 +1848,6 @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff= *a, TCGv_i32 tmp =3D tcg_temp_new_i32(); read_neon_element32(tmp, a->vm, 1, MO_32); widenfn(rm_64, tmp); - tcg_temp_free_i32(tmp); } =20 write_neon_element64(rn0_64, a->vd, 0, MO_64); @@ -1888,10 +1855,6 @@ static bool do_prewiden_3d(DisasContext *s, arg_3dif= f *a, opfn(rn1_64, rn1_64, rm_64); write_neon_element64(rn1_64, a->vd, 1, MO_64); =20 - tcg_temp_free_i64(rn0_64); - tcg_temp_free_i64(rn1_64); - tcg_temp_free_i64(rm_64); - return true; } =20 @@ -1976,11 +1939,6 @@ static bool do_narrow_3d(DisasContext *s, arg_3diff = *a, write_neon_element32(rd0, a->vd, 0, MO_32); write_neon_element32(rd1, a->vd, 1, MO_32); =20 - tcg_temp_free_i32(rd0); - tcg_temp_free_i32(rd1); - tcg_temp_free_i64(rn_64); - tcg_temp_free_i64(rm_64); - return true; } =20 @@ -2061,8 +2019,6 @@ static bool do_long_3d(DisasContext *s, arg_3diff *a, read_neon_element32(rn, a->vn, 1, MO_32); read_neon_element32(rm, a->vm, 1, MO_32); opfn(rd1, rn, rm); - tcg_temp_free_i32(rn); - tcg_temp_free_i32(rm); =20 /* Don't store results until after all loads: they might overlap */ if (accfn) { @@ -2071,13 +2027,10 @@ static bool do_long_3d(DisasContext *s, arg_3diff *= a, accfn(rd0, tmp, rd0); read_neon_element64(tmp, a->vd, 1, MO_64); accfn(rd1, tmp, rd1); - tcg_temp_free_i64(tmp); } =20 write_neon_element64(rd0, a->vd, 0, MO_64); write_neon_element64(rd1, a->vd, 1, MO_64); - tcg_temp_free_i64(rd0); - tcg_temp_free_i64(rd1); =20 return true; } @@ -2149,9 +2102,6 @@ static void gen_mull_s32(TCGv_i64 rd, TCGv_i32 rn, TC= Gv_i32 rm) =20 tcg_gen_muls2_i32(lo, hi, rn, rm); tcg_gen_concat_i32_i64(rd, lo, hi); - - tcg_temp_free_i32(lo); - tcg_temp_free_i32(hi); } =20 static void gen_mull_u32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) @@ -2161,9 +2111,6 @@ static void gen_mull_u32(TCGv_i64 rd, TCGv_i32 rn, TC= Gv_i32 rm) =20 tcg_gen_mulu2_i32(lo, hi, rn, rm); tcg_gen_concat_i32_i64(rd, lo, hi); - - tcg_temp_free_i32(lo); - tcg_temp_free_i32(hi); } =20 static bool trans_VMULL_S_3d(DisasContext *s, arg_3diff *a) @@ -2344,7 +2291,6 @@ static void gen_neon_dup_low16(TCGv_i32 var) tcg_gen_ext16u_i32(var, var); tcg_gen_shli_i32(tmp, var, 16); tcg_gen_or_i32(var, var, tmp); - tcg_temp_free_i32(tmp); } =20 static void gen_neon_dup_high16(TCGv_i32 var) @@ -2353,7 +2299,6 @@ static void gen_neon_dup_high16(TCGv_i32 var) tcg_gen_andi_i32(var, var, 0xffff0000); tcg_gen_shri_i32(tmp, var, 16); tcg_gen_or_i32(var, var, tmp); - tcg_temp_free_i32(tmp); } =20 static inline TCGv_i32 neon_get_scalar(int size, int reg) @@ -2417,12 +2362,9 @@ static bool do_2scalar(DisasContext *s, arg_2scalar = *a, TCGv_i32 rd =3D tcg_temp_new_i32(); read_neon_element32(rd, a->vd, pass, MO_32); accfn(tmp, rd, tmp); - tcg_temp_free_i32(rd); } write_neon_element32(tmp, a->vd, pass, MO_32); } - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(scalar); return true; } =20 @@ -2516,7 +2458,6 @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2s= calar *a, fpstatus =3D fpstatus_ptr(a->size =3D=3D 1 ? FPST_STD_F16 : FPST_STD); tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpstatus, vec_size, vec_size, idx, fn); - tcg_temp_free_ptr(fpstatus); return true; } =20 @@ -2616,10 +2557,6 @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2sc= alar *a, opfn(rd, cpu_env, rn, scalar, rd); write_neon_element32(rd, a->vd, pass, MO_32); } - tcg_temp_free_i32(rn); - tcg_temp_free_i32(rd); - tcg_temp_free_i32(scalar); - return true; } =20 @@ -2692,8 +2629,6 @@ static bool do_2scalar_long(DisasContext *s, arg_2sca= lar *a, read_neon_element32(rn, a->vn, 1, MO_32); rn1_64 =3D tcg_temp_new_i64(); opfn(rn1_64, rn, scalar); - tcg_temp_free_i32(rn); - tcg_temp_free_i32(scalar); =20 if (accfn) { TCGv_i64 t64 =3D tcg_temp_new_i64(); @@ -2701,13 +2636,10 @@ static bool do_2scalar_long(DisasContext *s, arg_2s= calar *a, accfn(rn0_64, t64, rn0_64); read_neon_element64(t64, a->vd, 1, MO_64); accfn(rn1_64, t64, rn1_64); - tcg_temp_free_i64(t64); } =20 write_neon_element64(rn0_64, a->vd, 0, MO_64); write_neon_element64(rn1_64, a->vd, 1, MO_64); - tcg_temp_free_i64(rn0_64); - tcg_temp_free_i64(rn1_64); return true; } =20 @@ -2842,10 +2774,6 @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a) read_neon_element64(left, a->vm, 0, MO_64); tcg_gen_extract2_i64(dest, right, left, a->imm * 8); write_neon_element64(dest, a->vd, 0, MO_64); - - tcg_temp_free_i64(left); - tcg_temp_free_i64(right); - tcg_temp_free_i64(dest); } else { /* Extract 128 bits from */ TCGv_i64 left, middle, right, destleft, destright; @@ -2872,12 +2800,6 @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a) =20 write_neon_element64(destright, a->vd, 0, MO_64); write_neon_element64(destleft, a->vd, 1, MO_64); - - tcg_temp_free_i64(destright); - tcg_temp_free_i64(destleft); - tcg_temp_free_i64(right); - tcg_temp_free_i64(middle); - tcg_temp_free_i64(left); } return true; } @@ -2921,9 +2843,6 @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) =20 gen_helper_neon_tbl(val, cpu_env, desc, val, def); write_neon_element64(val, a->vd, 0, MO_64); - - tcg_temp_free_i64(def); - tcg_temp_free_i64(val); return true; } =20 @@ -3002,9 +2921,6 @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 = *a) write_neon_element32(tmp[1], a->vd, pass * 2, MO_32); write_neon_element32(tmp[0], a->vd, pass * 2 + 1, MO_32); } - - tcg_temp_free_i32(tmp[0]); - tcg_temp_free_i32(tmp[1]); return true; } =20 @@ -3055,20 +2971,15 @@ static bool do_2misc_pairwise(DisasContext *s, arg_= 2misc *a, widenfn(rm0_64, tmp); read_neon_element32(tmp, a->vm, pass * 2 + 1, MO_32); widenfn(rm1_64, tmp); - tcg_temp_free_i32(tmp); =20 opfn(rd_64, rm0_64, rm1_64); - tcg_temp_free_i64(rm0_64); - tcg_temp_free_i64(rm1_64); =20 if (accfn) { TCGv_i64 tmp64 =3D tcg_temp_new_i64(); read_neon_element64(tmp64, a->vd, pass, MO_64); accfn(rd_64, tmp64, rd_64); - tcg_temp_free_i64(tmp64); } write_neon_element64(rd_64, a->vd, pass, MO_64); - tcg_temp_free_i64(rd_64); } return true; } @@ -3192,8 +3103,6 @@ static bool do_zip_uzp(DisasContext *s, arg_2misc *a, pd =3D vfp_reg_ptr(true, a->vd); pm =3D vfp_reg_ptr(true, a->vm); fn(pd, pm); - tcg_temp_free_ptr(pd); - tcg_temp_free_ptr(pm); return true; } =20 @@ -3271,9 +3180,6 @@ static bool do_vmovn(DisasContext *s, arg_2misc *a, narrowfn(rd1, cpu_env, rm); write_neon_element32(rd0, a->vd, 0, MO_32); write_neon_element32(rd1, a->vd, 1, MO_32); - tcg_temp_free_i32(rd0); - tcg_temp_free_i32(rd1); - tcg_temp_free_i64(rm); return true; } =20 @@ -3341,10 +3247,6 @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *= a) widenfn(rd, rm1); tcg_gen_shli_i64(rd, rd, 8 << a->size); write_neon_element64(rd, a->vd, 1, MO_64); - - tcg_temp_free_i64(rd); - tcg_temp_free_i32(rm0); - tcg_temp_free_i32(rm1); return true; } =20 @@ -3385,11 +3287,6 @@ static bool trans_VCVT_B16_F32(DisasContext *s, arg_= 2misc *a) =20 write_neon_element32(dst0, a->vd, 0, MO_32); write_neon_element32(dst1, a->vd, 1, MO_32); - - tcg_temp_free_i64(tmp); - tcg_temp_free_i32(dst0); - tcg_temp_free_i32(dst1); - tcg_temp_free_ptr(fpst); return true; } =20 @@ -3432,16 +3329,10 @@ static bool trans_VCVT_F16_F32(DisasContext *s, arg= _2misc *a) tmp3 =3D tcg_temp_new_i32(); read_neon_element32(tmp3, a->vm, 3, MO_32); write_neon_element32(tmp2, a->vd, 0, MO_32); - tcg_temp_free_i32(tmp2); gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp); tcg_gen_shli_i32(tmp3, tmp3, 16); tcg_gen_or_i32(tmp3, tmp3, tmp); write_neon_element32(tmp3, a->vd, 1, MO_32); - tcg_temp_free_i32(tmp3); - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(ahp); - tcg_temp_free_ptr(fpst); - return true; } =20 @@ -3482,18 +3373,12 @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg= _2misc *a) tcg_gen_shri_i32(tmp, tmp, 16); gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp); write_neon_element32(tmp, a->vd, 1, MO_32); - tcg_temp_free_i32(tmp); tcg_gen_ext16u_i32(tmp3, tmp2); gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); write_neon_element32(tmp3, a->vd, 2, MO_32); - tcg_temp_free_i32(tmp3); tcg_gen_shri_i32(tmp2, tmp2, 16); gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp); write_neon_element32(tmp2, a->vd, 3, MO_32); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(ahp); - tcg_temp_free_ptr(fpst); - return true; } =20 @@ -3628,8 +3513,6 @@ static bool do_2misc(DisasContext *s, arg_2misc *a, N= eonGenOneOpFn *fn) fn(tmp, tmp); write_neon_element32(tmp, a->vd, pass, MO_32); } - tcg_temp_free_i32(tmp); - return true; } =20 @@ -3790,7 +3673,6 @@ static bool trans_VQNEG(DisasContext *s, arg_2misc *a) fpst =3D fpstatus_ptr(vece =3D=3D MO_16 ? FPST_STD_F16 : FPST_STD)= ; \ tcg_gen_gvec_2_ptr(rd_ofs, rm_ofs, fpst, oprsz, maxsz, 0, \ fns[vece]); \ - tcg_temp_free_ptr(fpst); \ } \ static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ { \ @@ -3841,7 +3723,6 @@ static bool trans_VRINTX(DisasContext *s, arg_2misc *= a) fpst =3D fpstatus_ptr(vece =3D=3D 1 ? FPST_STD_F16 : FPST_STD); = \ tcg_gen_gvec_2_ptr(rd_ofs, rm_ofs, fpst, oprsz, maxsz, \ arm_rmode_to_sf(RMODE), fns[vece]); \ - tcg_temp_free_ptr(fpst); \ } \ static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ { \ @@ -3908,11 +3789,9 @@ static bool trans_VSWP(DisasContext *s, arg_2misc *a) write_neon_element64(rm, a->vd, pass, MO_64); write_neon_element64(rd, a->vm, pass, MO_64); } - tcg_temp_free_i64(rm); - tcg_temp_free_i64(rd); - return true; } + static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1) { TCGv_i32 rd, tmp; @@ -3930,9 +3809,6 @@ static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1) tcg_gen_andi_i32(tmp, t0, 0xff00ff00); tcg_gen_or_i32(t1, t1, tmp); tcg_gen_mov_i32(t0, rd); - - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(rd); } =20 static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1) @@ -3949,9 +3825,6 @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1) tcg_gen_andi_i32(tmp, t0, 0xffff0000); tcg_gen_or_i32(t1, t1, tmp); tcg_gen_mov_i32(t0, rd); - - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(rd); } =20 static bool trans_VTRN(DisasContext *s, arg_2misc *a) @@ -4003,8 +3876,6 @@ static bool trans_VTRN(DisasContext *s, arg_2misc *a) write_neon_element32(tmp, a->vd, pass, MO_32); } } - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); return true; } =20 --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677475893; cv=none; d=zohomail.com; s=zohoarc; b=ACBzWeZPgBaNLGe9ynly+sKORGQZyHaBLDdnV0XUAQZE7jxnNHSt5PcdsE0B26KXPS7pHwGECDF17zA4fb+MH5mwTNPNmDY4Rxdvh77QFMkCFQNANoP4OlXlXTi0kRn089dStWlqSOFzaj9b/HEE1rVTmCxo5v5yCx9gT0wsxGM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677475893; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TdAJOX1FcZjtnyq2ALvPntQgs+t2YDMFFecOsF1aMGk=; b=XA955/vknNT/ThSG9PUfnFsvIyB7w84X+ZJIgbYeMm+zS5hyv9yc1ojROpErMZWKzvXKSXvUpTFhXrx/cqo81eYAifI5Xu5AD9SGu33QXxdu2F2PTVL/tEblRG1j1RPcNYLFsES05xfuyFG4Qg8tNIkk9H6aF/mVunUKGkNqdSE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677475893776876.1547768905637; Sun, 26 Feb 2023 21:31:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW1M-00079Y-Qr; Mon, 27 Feb 2023 00:25:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW1J-00075E-UM for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:25:53 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW1F-0007Mz-BQ for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:25:53 -0500 Received: by mail-pj1-x102b.google.com with SMTP id h11-20020a17090a2ecb00b00237c740335cso3976233pjs.3 for ; Sun, 26 Feb 2023 21:25:48 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.25.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:25:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TdAJOX1FcZjtnyq2ALvPntQgs+t2YDMFFecOsF1aMGk=; b=vGdk98fpRaawt/TmCEPwqbh5DAKUjpvs2PZeMjhry4+3V9vh7GRWptaqgSyPHN0DRx AoqUgGfxXgLM1xdG9so6fCaqkk8NNWXBIRj9uGe47uT2HYJZMPXt4VsoHly03fK55iz0 W5jPSV6KSu7H7Su2W59WvV05eMCHymBJQCU/6zW48rV4RsFbo1WGifB2u9zWTPktVmcX kMnok78x6RaMVVV/osUxtoSl04P4s8qvQboyr4PMbq9E4S0GDyhLYlCC7W7+p8ZMOpNI fkSL3d/JBwHb/cxVdsHwag9KrEWROVkUpbakHGAKQSRQSk/fYzttBXrFFIN/lQSmdxCV oGxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TdAJOX1FcZjtnyq2ALvPntQgs+t2YDMFFecOsF1aMGk=; b=y/eFF7A6LV5njTa/xa1GbBr3si2CdTozOmwypO2O2t9H63RX4AQSUqiJ39PC5c4tyY zABEBOFRlHQ7Kbsdwi0zYNSSmKQTNU0Und1InVHh9+FMOsTdtqrUqu3msupIUvD+mwIx z+m/SckXF0cs26XbiTB4FIC5PsZSss7iyAPVmlTkBrX8JGk38xemHGhGIl8yBWaXAO8g TkC8IXuSKHJ09MHZDZ6kYoG42wlpS8xR5chpqFIbWgiseDNhM//2p8oy+5WxWjsyJfas K0vvAR6Z4tlIId2k3XGcrKFAoXlQkr+X56g3A+yQqdTcu77u1IZ3GludlPhtN1Jiu5Y5 77KQ== X-Gm-Message-State: AO0yUKXznxbfmc6gaNJ2CSvZHcQ+MBq9MkuFA87L1mQTrGTem3IH9ohI PIiRikDm4WaMKa7FEv43oi32B3Ju7gsdHcxE5yk= X-Google-Smtp-Source: AK7set/QmzLSTTKhAhKGeBkiNX1utJ0tq7Gr3ZDvNt8FJjbg6p1tRwPb40r/LM3AqtQkip6tX+rC2g== X-Received: by 2002:a17:902:8b85:b0:19a:b74a:7f7e with SMTP id ay5-20020a1709028b8500b0019ab74a7f7emr20204625plb.28.1677475548497; Sun, 26 Feb 2023 21:25:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 14/76] target/arm: Drop tcg_temp_free from translator-sme.c Date: Sun, 26 Feb 2023 19:24:03 -1000 Message-Id: <20230227052505.352889-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475895339100009 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/arm/translate-sme.c | 28 ---------------------------- 1 file changed, 28 deletions(-) diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index 7b87a9df63..e3adba314e 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -97,7 +97,6 @@ static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz,= int rs, /* Add the byte offset to env to produce the final pointer. */ addr =3D tcg_temp_new_ptr(); tcg_gen_ext_i32_ptr(addr, tmp); - tcg_temp_free_i32(tmp); tcg_gen_add_ptr(addr, addr, cpu_env); =20 return addr; @@ -166,11 +165,6 @@ static bool trans_MOVA(DisasContext *s, arg_MOVA *a) h_fns[a->esz](t_za, t_zr, t_za, t_pg, t_desc); } } - - tcg_temp_free_ptr(t_za); - tcg_temp_free_ptr(t_zr); - tcg_temp_free_ptr(t_pg); - return true; } =20 @@ -237,10 +231,6 @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) =20 fns[a->esz][be][a->v][mte][a->st](cpu_env, t_za, t_pg, addr, tcg_constant_i32(desc)); - - tcg_temp_free_ptr(t_za); - tcg_temp_free_ptr(t_pg); - tcg_temp_free_i64(addr); return true; } =20 @@ -260,8 +250,6 @@ static bool do_ldst_r(DisasContext *s, arg_ldstr *a, Ge= nLdStR *fn) base =3D get_tile_rowcol(s, MO_8, a->rv, imm, false); =20 fn(s, base, 0, svl, a->rn, imm * svl); - - tcg_temp_free_ptr(base); return true; } =20 @@ -286,11 +274,6 @@ static bool do_adda(DisasContext *s, arg_adda *a, MemO= p esz, pm =3D pred_full_reg_ptr(s, a->pm); =20 fn(za, zn, pn, pm, tcg_constant_i32(desc)); - - tcg_temp_free_ptr(za); - tcg_temp_free_ptr(zn); - tcg_temp_free_ptr(pn); - tcg_temp_free_ptr(pm); return true; } =20 @@ -318,11 +301,6 @@ static bool do_outprod(DisasContext *s, arg_op *a, Mem= Op esz, pm =3D pred_full_reg_ptr(s, a->pm); =20 fn(za, zn, zm, pn, pm, tcg_constant_i32(desc)); - - tcg_temp_free_ptr(za); - tcg_temp_free_ptr(zn); - tcg_temp_free_ptr(pn); - tcg_temp_free_ptr(pm); return true; } =20 @@ -346,12 +324,6 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a= , MemOp esz, fpst =3D fpstatus_ptr(FPST_FPCR); =20 fn(za, zn, zm, pn, pm, fpst, tcg_constant_i32(desc)); - - tcg_temp_free_ptr(za); - tcg_temp_free_ptr(zn); - tcg_temp_free_ptr(pn); - tcg_temp_free_ptr(pm); - tcg_temp_free_ptr(fpst); return true; } =20 --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677475949; cv=none; d=zohomail.com; s=zohoarc; b=ImHbXUhKOFczsUgA2iVI8OvRM0GM2Y4cyB554izIkayuVcE0+x2kGBJOh4VZNbT2yCqeNl6L3yv4pj70QUlHa+EVkGY0IrDdhff5O3dhy0En346x4FLAsXbbLj2gzv58f2cbeUu3Cnx1Sb3/+985HTj6OPL1/k205ZzKy8/w98w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677475949; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oyukTKpkx7E2+5MyXTDekUgKr37KnymCTJNQhCaEjRc=; b=BSyjtq0DsB+T9Xnu0tlWeJrh+JmwRYPJm07i9U2KVmAf745cNzHrjc7nBw0bjJyC0J11oxCIcdmguc1JGYuQzhI8XqryCyYW2udjHP1T9y0kchwfYibfzl/Fb9ZOsMHtoFS4U7I1eF7CRTTOOagwGpru2EupCeqOsj2qTOKpkQ8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677475949491334.96508286676897; Sun, 26 Feb 2023 21:32:29 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW1b-0007Qm-VX; Mon, 27 Feb 2023 00:26:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW1N-00079l-2q for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:25:58 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW1I-0007Cs-HW for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:25:56 -0500 Received: by mail-pj1-x102c.google.com with SMTP id qa18-20020a17090b4fd200b0023750b675f5so8836536pjb.3 for ; Sun, 26 Feb 2023 21:25:52 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.25.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:25:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oyukTKpkx7E2+5MyXTDekUgKr37KnymCTJNQhCaEjRc=; b=GZwZ9IPZdcGH0v+1UV05rCL4VhHAF89wdAU7Me8H3Ts84yWNzUgnePwl5wH7IfSiZt 5t+yRlBqh7WR4ztFYpBWEMn7wMfYqaDgLYTzqv2SNJviy6mZF3xc/4cG03W4PiyaeAsB ne4f63ds4y6bXY43VuuOsLYCJfCtlmkhyeZ9+vNMi/ZU4QRPgD+cCHMx1MWlsaWM1xfX DSoWu8rXvvV+miS0ErmgxQWJkyC5IisV5f2PZuhL1RYiajz7XlKoCC25wGBmJcQ5R1PG 2CkK49m37av60JxuU2sE2JFsFmN4MQH9+AtcyhTZIF7yODqluxQGHJUe1yM0E7M9ol7N AMkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oyukTKpkx7E2+5MyXTDekUgKr37KnymCTJNQhCaEjRc=; b=HEJJK3VPdo6/RUmYBPsPsu5nSFlEMq9zWD3kgTQMQhKAVXgdy1Do/54kxGoGUIbZ4B hLSoz8G9rf+gp7xFcxj6LkbNgiYeIhvE49RhTr0HkBI4cEoNhJQ52Jb1JH4QhA/lGdSt KioigA1qgu+83f85zZqqdM6ec4H7cpjn2TL/LgRjXqXH6hHaEUbhmBkLpVsNCCQe23I3 hsQA0ydJSbtsiJg50CdR7dZEN805CgQ8MhIktAsLhlbwpJCZhgMUjCCmTxkGeLupUAAV WHtzg09E/Oa4KKUoJOPTC9jyzahiUDxCF0UtawuJt3d6HE5HKVMKAY/Yrdp70i5Psvk8 AOlA== X-Gm-Message-State: AO0yUKVrwN3+TLaabVZXvr1raUg5qNU+U5dTn0liOpc6MrYeTVUIGPNT vE5dzpj0hU5Z2sZcbGW8dMku0DKvRSV5/IypoTg= X-Google-Smtp-Source: AK7set99v5aZJYMnK60Dn9cwAMmiz4Q2gR4CXVh8MdbXnKLfZMcoYMWcOPfs9gpN9LLDsY04x7vKfQ== X-Received: by 2002:a17:902:e745:b0:19b:dfd:a202 with SMTP id p5-20020a170902e74500b0019b0dfda202mr28728490plf.38.1677475551660; Sun, 26 Feb 2023 21:25:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 15/76] target/arm: Drop tcg_temp_free from translator-sve.c Date: Sun, 26 Feb 2023 19:24:04 -1000 Message-Id: <20230227052505.352889-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475951707100003 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/arm/translate-sve.c | 186 +------------------------------------ 1 file changed, 2 insertions(+), 184 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 2f607a355e..5bf80b22d7 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -130,7 +130,6 @@ static bool gen_gvec_fpst_zz(DisasContext *s, gen_helpe= r_gvec_2_ptr *fn, tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), status, vsz, vsz, data, fn); - tcg_temp_free_ptr(status); } return true; } @@ -181,8 +180,6 @@ static bool gen_gvec_fpst_zzz(DisasContext *s, gen_help= er_gvec_3_ptr *fn, vec_full_reg_offset(s, rn), vec_full_reg_offset(s, rm), status, vsz, vsz, data, fn); - - tcg_temp_free_ptr(status); } return true; } @@ -249,7 +246,6 @@ static bool gen_gvec_fpst_zzzz(DisasContext *s, gen_hel= per_gvec_4_ptr *fn, { TCGv_ptr status =3D fpstatus_ptr(flavour); bool ret =3D gen_gvec_ptr_zzzz(s, fn, rd, rn, rm, ra, data, status); - tcg_temp_free_ptr(status); return ret; } =20 @@ -271,8 +267,6 @@ static bool gen_gvec_fpst_zzzzp(DisasContext *s, gen_he= lper_gvec_5_ptr *fn, vec_full_reg_offset(s, ra), pred_full_reg_offset(s, pg), status, vsz, vsz, data, fn); - - tcg_temp_free_ptr(status); } return true; } @@ -321,7 +315,6 @@ static bool gen_gvec_fpst_zzp(DisasContext *s, gen_help= er_gvec_3_ptr *fn, vec_full_reg_offset(s, rn), pred_full_reg_offset(s, pg), status, vsz, vsz, data, fn); - tcg_temp_free_ptr(status); } return true; } @@ -374,7 +367,6 @@ static bool gen_gvec_fpst_zzzp(DisasContext *s, gen_hel= per_gvec_4_ptr *fn, vec_full_reg_offset(s, rm), pred_full_reg_offset(s, pg), status, vsz, vsz, data, fn); - tcg_temp_free_ptr(status); } return true; } @@ -508,7 +500,6 @@ static void do_predtest1(TCGv_i64 d, TCGv_i64 g) =20 gen_helper_sve_predtest1(t, d, g); do_pred_flags(t); - tcg_temp_free_i32(t); } =20 static void do_predtest(DisasContext *s, int dofs, int gofs, int words) @@ -521,11 +512,8 @@ static void do_predtest(DisasContext *s, int dofs, int= gofs, int words) tcg_gen_addi_ptr(gptr, cpu_env, gofs); =20 gen_helper_sve_predtest(t, dptr, gptr, tcg_constant_i32(words)); - tcg_temp_free_ptr(dptr); - tcg_temp_free_ptr(gptr); =20 do_pred_flags(t); - tcg_temp_free_i32(t); } =20 /* For each element size, the bits within a predicate word that are active= . */ @@ -561,7 +549,6 @@ static void gen_xar8_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i= 64 m, int64_t sh) tcg_gen_andi_i64(d, d, mask); tcg_gen_andi_i64(t, t, ~mask); tcg_gen_or_i64(d, d, t); - tcg_temp_free_i64(t); } =20 static void gen_xar16_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh) @@ -575,7 +562,6 @@ static void gen_xar16_i64(TCGv_i64 d, TCGv_i64 n, TCGv_= i64 m, int64_t sh) tcg_gen_andi_i64(d, d, mask); tcg_gen_andi_i64(t, t, ~mask); tcg_gen_or_i64(d, d, t); - tcg_temp_free_i64(t); } =20 static void gen_xar_i32(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m, int32_t sh) @@ -984,11 +970,8 @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a, tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); fn(temp, t_zn, t_pg, desc); - tcg_temp_free_ptr(t_zn); - tcg_temp_free_ptr(t_pg); =20 write_fp_dreg(s, a->rd, temp); - tcg_temp_free_i64(temp); return true; } =20 @@ -1253,11 +1236,7 @@ static bool do_index(DisasContext *s, int esz, int r= d, tcg_gen_extrl_i64_i32(s32, start); tcg_gen_extrl_i64_i32(i32, incr); fns[esz](t_zd, s32, i32, desc); - - tcg_temp_free_i32(s32); - tcg_temp_free_i32(i32); } - tcg_temp_free_ptr(t_zd); return true; } =20 @@ -1419,11 +1398,6 @@ static bool do_pppp_flags(DisasContext *s, arg_rprr_= s *a, tcg_gen_st_i64(pd, cpu_env, dofs); =20 do_predtest1(pd, pg); - - tcg_temp_free_i64(pd); - tcg_temp_free_i64(pn); - tcg_temp_free_i64(pm); - tcg_temp_free_i64(pg); } else { /* The operation and flags generation is large. The computation * of the flags depends on the original contents of the guarding @@ -1694,9 +1668,6 @@ static bool trans_PTEST(DisasContext *s, arg_PTEST *a) tcg_gen_ld_i64(pn, cpu_env, nofs); tcg_gen_ld_i64(pg, cpu_env, gofs); do_predtest1(pn, pg); - - tcg_temp_free_i64(pn); - tcg_temp_free_i64(pg); } else { do_predtest(s, nofs, gofs, words); } @@ -1810,8 +1781,6 @@ static bool do_predset(DisasContext *s, int esz, int = rd, int pat, bool setflag) } =20 done: - tcg_temp_free_i64(t); - /* PTRUES */ if (setflag) { tcg_gen_movi_i32(cpu_NF, -(word !=3D 0)); @@ -1869,11 +1838,8 @@ static bool do_pfirst_pnext(DisasContext *s, arg_rr_= esz *a, t =3D tcg_temp_new_i32(); =20 gen_fn(t, t_pd, t_pg, tcg_constant_i32(desc)); - tcg_temp_free_ptr(t_pd); - tcg_temp_free_ptr(t_pg); =20 do_pred_flags(t); - tcg_temp_free_i32(t); return true; } =20 @@ -1950,9 +1916,7 @@ static void do_sat_addsub_64(TCGv_i64 reg, TCGv_i64 v= al, bool u, bool d) t2 =3D tcg_constant_i64(0); tcg_gen_movcond_i64(TCG_COND_LT, reg, t0, t2, t1, reg); } - tcg_temp_free_i64(t1); } - tcg_temp_free_i64(t0); } =20 /* Similarly with a vector and a scalar operand. */ @@ -1982,7 +1946,6 @@ static void do_sat_addsub_vec(DisasContext *s, int es= z, int rd, int rn, } else { gen_helper_sve_sqaddi_b(dptr, nptr, t32, desc); } - tcg_temp_free_i32(t32); break; =20 case MO_16: @@ -1996,7 +1959,6 @@ static void do_sat_addsub_vec(DisasContext *s, int es= z, int rd, int rn, } else { gen_helper_sve_sqaddi_h(dptr, nptr, t32, desc); } - tcg_temp_free_i32(t32); break; =20 case MO_32: @@ -2011,7 +1973,6 @@ static void do_sat_addsub_vec(DisasContext *s, int es= z, int rd, int rn, } else { gen_helper_sve_sqaddi_s(dptr, nptr, t64, desc); } - tcg_temp_free_i64(t64); break; =20 case MO_64: @@ -2025,7 +1986,6 @@ static void do_sat_addsub_vec(DisasContext *s, int es= z, int rd, int rn, t64 =3D tcg_temp_new_i64(); tcg_gen_neg_i64(t64, val); gen_helper_sve_sqaddi_d(dptr, nptr, t64, desc); - tcg_temp_free_i64(t64); } else { gen_helper_sve_sqaddi_d(dptr, nptr, val, desc); } @@ -2034,9 +1994,6 @@ static void do_sat_addsub_vec(DisasContext *s, int es= z, int rd, int rn, default: g_assert_not_reached(); } - - tcg_temp_free_ptr(dptr); - tcg_temp_free_ptr(nptr); } =20 static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a) @@ -2222,10 +2179,6 @@ static void do_cpy_m(DisasContext *s, int esz, int r= d, int rn, int pg, tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); =20 fns[esz](t_zd, t_zn, t_pg, val, desc); - - tcg_temp_free_ptr(t_zd); - tcg_temp_free_ptr(t_zn); - tcg_temp_free_ptr(t_pg); } =20 static bool trans_FCPY(DisasContext *s, arg_FCPY *a) @@ -2372,9 +2325,6 @@ static void do_insr_i64(DisasContext *s, arg_rrr_esz = *a, TCGv_i64 val) tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); =20 fns[a->esz](t_zd, t_zn, val, desc); - - tcg_temp_free_ptr(t_zd); - tcg_temp_free_ptr(t_zn); } =20 static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a) @@ -2386,7 +2336,6 @@ static bool trans_INSR_f(DisasContext *s, arg_rrr_esz= *a) TCGv_i64 t =3D tcg_temp_new_i64(); tcg_gen_ld_i64(t, cpu_env, vec_reg_offset(s, a->rm, 0, MO_64)); do_insr_i64(s, a, t); - tcg_temp_free_i64(t); } return true; } @@ -2476,10 +2425,6 @@ static bool do_perm_pred3(DisasContext *s, arg_rrr_e= sz *a, bool high_odd, tcg_gen_addi_ptr(t_m, cpu_env, pred_full_reg_offset(s, a->rm)); =20 fn(t_d, t_n, t_m, tcg_constant_i32(desc)); - - tcg_temp_free_ptr(t_d); - tcg_temp_free_ptr(t_n); - tcg_temp_free_ptr(t_m); return true; } =20 @@ -2503,9 +2448,6 @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz= *a, bool high_odd, desc =3D FIELD_DP32(desc, PREDDESC, DATA, high_odd); =20 fn(t_d, t_n, tcg_constant_i32(desc)); - - tcg_temp_free_ptr(t_d); - tcg_temp_free_ptr(t_n); return true; } =20 @@ -2597,8 +2539,6 @@ static void find_last_active(DisasContext *s, TCGv_i3= 2 ret, int esz, int pg) tcg_gen_addi_ptr(t_p, cpu_env, pred_full_reg_offset(s, pg)); =20 gen_helper_sve_last_active_element(ret, t_p, tcg_constant_i32(desc)); - - tcg_temp_free_ptr(t_p); } =20 /* Increment LAST to the offset of the next element in the vector, @@ -2661,7 +2601,6 @@ static TCGv_i64 load_last_active(DisasContext *s, TCG= v_i32 last, int rm, int esz) { TCGv_ptr p =3D tcg_temp_new_ptr(); - TCGv_i64 r; =20 /* Convert offset into vector into offset into ENV. * The final adjustment for the vector register base @@ -2676,10 +2615,7 @@ static TCGv_i64 load_last_active(DisasContext *s, TC= Gv_i32 last, tcg_gen_ext_i32_ptr(p, last); tcg_gen_add_ptr(p, p, cpu_env); =20 - r =3D load_esz(p, vec_full_reg_offset(s, rm), esz); - tcg_temp_free_ptr(p); - - return r; + return load_esz(p, vec_full_reg_offset(s, rm), esz); } =20 /* Compute CLAST for a Zreg. */ @@ -2709,11 +2645,9 @@ static bool do_clast_vector(DisasContext *s, arg_rpr= r_esz *a, bool before) } =20 ele =3D load_last_active(s, last, a->rm, esz); - tcg_temp_free_i32(last); =20 vsz =3D vec_full_reg_size(s); tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd), vsz, vsz, ele= ); - tcg_temp_free_i64(ele); =20 /* If this insn used MOVPRFX, we may need a second move. */ if (a->rd !=3D a->rn) { @@ -2756,13 +2690,9 @@ static void do_clast_scalar(DisasContext *s, int esz= , int pg, int rm, * a conditional move. */ ele =3D load_last_active(s, last, rm, esz); - tcg_temp_free_i32(last); =20 tcg_gen_movcond_i64(TCG_COND_GE, reg_val, cmp, tcg_constant_i64(0), ele, reg_val); - - tcg_temp_free_i64(cmp); - tcg_temp_free_i64(ele); } =20 /* Compute CLAST for a Vreg. */ @@ -2775,7 +2705,6 @@ static bool do_clast_fp(DisasContext *s, arg_rpr_esz = *a, bool before) =20 do_clast_scalar(s, esz, a->pg, a->rn, before, reg); write_fp_dreg(s, a->rd, reg); - tcg_temp_free_i64(reg); } return true; } @@ -2821,7 +2750,6 @@ static TCGv_i64 do_last_scalar(DisasContext *s, int e= sz, int pg, int rm, bool before) { TCGv_i32 last =3D tcg_temp_new_i32(); - TCGv_i64 ret; =20 find_last_active(s, last, esz, pg); if (before) { @@ -2830,9 +2758,7 @@ static TCGv_i64 do_last_scalar(DisasContext *s, int e= sz, incr_last_active(s, last, esz); } =20 - ret =3D load_last_active(s, last, rm, esz); - tcg_temp_free_i32(last); - return ret; + return load_last_active(s, last, rm, esz); } =20 /* Compute LAST for a Vreg. */ @@ -2841,7 +2767,6 @@ static bool do_last_fp(DisasContext *s, arg_rpr_esz *= a, bool before) if (sve_access_check(s)) { TCGv_i64 val =3D do_last_scalar(s, a->esz, a->pg, a->rn, before); write_fp_dreg(s, a->rd, val); - tcg_temp_free_i64(val); } return true; } @@ -2855,7 +2780,6 @@ static bool do_last_general(DisasContext *s, arg_rpr_= esz *a, bool before) if (sve_access_check(s)) { TCGv_i64 val =3D do_last_scalar(s, a->esz, a->pg, a->rn, before); tcg_gen_mov_i64(cpu_reg(s, a->rd), val); - tcg_temp_free_i64(val); } return true; } @@ -2883,7 +2807,6 @@ static bool trans_CPY_m_v(DisasContext *s, arg_rpr_es= z *a) int ofs =3D vec_reg_offset(s, a->rn, 0, a->esz); TCGv_i64 t =3D load_esz(cpu_env, ofs, a->esz); do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, t); - tcg_temp_free_i64(t); } return true; } @@ -2942,14 +2865,7 @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_= esz *a, =20 gen_fn(t, pd, zn, zm, pg, tcg_constant_i32(simd_desc(vsz, vsz, 0))); =20 - tcg_temp_free_ptr(pd); - tcg_temp_free_ptr(zn); - tcg_temp_free_ptr(zm); - tcg_temp_free_ptr(pg); - do_pred_flags(t); - - tcg_temp_free_i32(t); return true; } =20 @@ -3021,13 +2937,7 @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_= esz *a, =20 gen_fn(t, pd, zn, pg, tcg_constant_i32(simd_desc(vsz, vsz, a->imm))); =20 - tcg_temp_free_ptr(pd); - tcg_temp_free_ptr(zn); - tcg_temp_free_ptr(pg); - do_pred_flags(t); - - tcg_temp_free_i32(t); return true; } =20 @@ -3081,14 +2991,9 @@ static bool do_brk3(DisasContext *s, arg_rprr_s *a, TCGv_i32 t =3D tcg_temp_new_i32(); fn_s(t, d, n, m, g, desc); do_pred_flags(t); - tcg_temp_free_i32(t); } else { fn(d, n, m, g, desc); } - tcg_temp_free_ptr(d); - tcg_temp_free_ptr(n); - tcg_temp_free_ptr(m); - tcg_temp_free_ptr(g); return true; } =20 @@ -3115,13 +3020,9 @@ static bool do_brk2(DisasContext *s, arg_rpr_s *a, TCGv_i32 t =3D tcg_temp_new_i32(); fn_s(t, d, n, g, desc); do_pred_flags(t); - tcg_temp_free_i32(t); } else { fn(d, n, g, desc); } - tcg_temp_free_ptr(d); - tcg_temp_free_ptr(n); - tcg_temp_free_ptr(g); return true; } =20 @@ -3159,7 +3060,6 @@ static void do_cntp(DisasContext *s, TCGv_i64 val, in= t esz, int pn, int pg) TCGv_i64 g =3D tcg_temp_new_i64(); tcg_gen_ld_i64(g, cpu_env, pred_full_reg_offset(s, pg)); tcg_gen_and_i64(val, val, g); - tcg_temp_free_i64(g); } =20 /* Reduce the pred_esz_masks value simply to reduce the @@ -3181,8 +3081,6 @@ static void do_cntp(DisasContext *s, TCGv_i64 val, in= t esz, int pn, int pg) tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); =20 gen_helper_sve_cntp(val, t_pn, t_pg, tcg_constant_i32(desc)); - tcg_temp_free_ptr(t_pn); - tcg_temp_free_ptr(t_pg); } } =20 @@ -3212,7 +3110,6 @@ static bool trans_INCDECP_r(DisasContext *s, arg_incd= ec_pred *a) } else { tcg_gen_add_i64(reg, reg, val); } - tcg_temp_free_i64(val); } return true; } @@ -3297,7 +3194,6 @@ static bool trans_CTERM(DisasContext *s, arg_CTERM *a) =20 tcg_gen_setcond_i64(cond, cmp, rn, rm); tcg_gen_extrl_i64_i32(cpu_NF, cmp); - tcg_temp_free_i64(cmp); =20 /* VF =3D !NF & !CF. */ tcg_gen_xori_i32(cpu_VF, cpu_NF, 1); @@ -3394,12 +3290,10 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE = *a) /* Set the count to zero if the condition is false. */ tcg_gen_movi_i64(t1, 0); tcg_gen_movcond_i64(cond, t0, op0, op1, t0, t1); - tcg_temp_free_i64(t1); =20 /* Since we're bounded, pass as a 32-bit type. */ t2 =3D tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(t2, t0); - tcg_temp_free_i64(t0); =20 /* Scale elements to bits. */ tcg_gen_shli_i32(t2, t2, a->esz); @@ -3416,9 +3310,6 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a) gen_helper_sve_whileg(t2, ptr, t2, tcg_constant_i32(desc)); } do_pred_flags(t2); - - tcg_temp_free_ptr(ptr); - tcg_temp_free_i32(t2); return true; } =20 @@ -3450,7 +3341,6 @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHIL= E_ptr *a) tcg_gen_sub_i64(diff, op0, op1); tcg_gen_sub_i64(t1, op1, op0); tcg_gen_movcond_i64(TCG_COND_GEU, diff, op0, op1, diff, t1); - tcg_temp_free_i64(t1); /* Round down to a multiple of ESIZE. */ tcg_gen_andi_i64(diff, diff, -1 << a->esz); /* If op1 =3D=3D op0, diff =3D=3D 0, and the condition is always t= rue. */ @@ -3470,7 +3360,6 @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHIL= E_ptr *a) /* Since we're bounded, pass as a 32-bit type. */ t2 =3D tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(t2, diff); - tcg_temp_free_i64(diff); =20 desc =3D FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8); desc =3D FIELD_DP32(desc, PREDDESC, ESZ, a->esz); @@ -3480,9 +3369,6 @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHIL= E_ptr *a) =20 gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc)); do_pred_flags(t2); - - tcg_temp_free_ptr(ptr); - tcg_temp_free_i32(t2); return true; } =20 @@ -3814,12 +3700,8 @@ static bool do_reduce(DisasContext *s, arg_rpr_esz *= a, status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_FPC= R); =20 fn(temp, t_zn, t_pg, status, t_desc); - tcg_temp_free_ptr(t_zn); - tcg_temp_free_ptr(t_pg); - tcg_temp_free_ptr(status); =20 write_fp_dreg(s, a->rd, temp); - tcg_temp_free_i64(temp); return true; } =20 @@ -3873,7 +3755,6 @@ static bool do_ppz_fp(DisasContext *s, arg_rpr_esz *a, vec_full_reg_offset(s, a->rn), pred_full_reg_offset(s, a->pg), status, vsz, vsz, 0, fn); - tcg_temp_free_ptr(status); } return true; } @@ -3942,12 +3823,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_es= z *a) =20 fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc); =20 - tcg_temp_free_ptr(t_fpst); - tcg_temp_free_ptr(t_pg); - tcg_temp_free_ptr(t_rm); - write_fp_dreg(s, a->rd, t_val); - tcg_temp_free_i64(t_val); return true; } =20 @@ -4020,11 +3896,6 @@ static void do_fp_scalar(DisasContext *s, int zd, in= t zn, int pg, bool is_fp16, status =3D fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR); desc =3D tcg_constant_i32(simd_desc(vsz, vsz, 0)); fn(t_zd, t_zn, t_pg, scalar, status, desc); - - tcg_temp_free_ptr(status); - tcg_temp_free_ptr(t_pg); - tcg_temp_free_ptr(t_zn); - tcg_temp_free_ptr(t_zd); } =20 static bool do_fp_imm(DisasContext *s, arg_rpri_esz *a, uint64_t imm, @@ -4080,7 +3951,6 @@ static bool do_fp_cmp(DisasContext *s, arg_rprr_esz *= a, vec_full_reg_offset(s, a->rm), pred_full_reg_offset(s, a->pg), status, vsz, vsz, 0, fn); - tcg_temp_free_ptr(status); } return true; } @@ -4237,8 +4107,6 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_es= z *a, status, vsz, vsz, 0, fn); =20 gen_helper_set_rmode(tmode, tmode, status); - tcg_temp_free_i32(tmode); - tcg_temp_free_ptr(status); return true; } =20 @@ -4321,7 +4189,6 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int = vofs, dirty_addr =3D tcg_temp_new_i64(); tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); clean_addr =3D gen_mte_checkN(s, dirty_addr, false, rn !=3D 31, len); - tcg_temp_free_i64(dirty_addr); =20 /* * Note that unpredicated load/store of vector/predicate registers @@ -4339,7 +4206,6 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int = vofs, tcg_gen_st_i64(t0, base, vofs + i); tcg_gen_addi_i64(clean_addr, clean_addr, 8); } - tcg_temp_free_i64(t0); } else { TCGLabel *loop =3D gen_new_label(); TCGv_ptr tp, i =3D tcg_const_ptr(0); @@ -4354,11 +4220,8 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int= vofs, tcg_gen_add_ptr(tp, base, i); tcg_gen_addi_ptr(i, i, 8); tcg_gen_st_i64(t0, tp, vofs); - tcg_temp_free_ptr(tp); - tcg_temp_free_i64(t0); =20 tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); - tcg_temp_free_ptr(i); } =20 /* @@ -4381,14 +4244,12 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, in= t vofs, tcg_gen_addi_i64(clean_addr, clean_addr, 4); tcg_gen_qemu_ld_i64(t1, clean_addr, midx, MO_LEUW); tcg_gen_deposit_i64(t0, t0, t1, 32, 32); - tcg_temp_free_i64(t1); break; =20 default: g_assert_not_reached(); } tcg_gen_st_i64(t0, base, vofs + len_align); - tcg_temp_free_i64(t0); } } =20 @@ -4405,7 +4266,6 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int = vofs, dirty_addr =3D tcg_temp_new_i64(); tcg_gen_addi_i64(dirty_addr, cpu_reg_sp(s, rn), imm); clean_addr =3D gen_mte_checkN(s, dirty_addr, false, rn !=3D 31, len); - tcg_temp_free_i64(dirty_addr); =20 /* Note that unpredicated load/store of vector/predicate registers * are defined as a stream of bytes, which equates to little-endian @@ -4424,7 +4284,6 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int = vofs, tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ); tcg_gen_addi_i64(clean_addr, clean_addr, 8); } - tcg_temp_free_i64(t0); } else { TCGLabel *loop =3D gen_new_label(); TCGv_ptr tp, i =3D tcg_const_ptr(0); @@ -4436,14 +4295,11 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, in= t vofs, tcg_gen_add_ptr(tp, base, i); tcg_gen_ld_i64(t0, tp, vofs); tcg_gen_addi_ptr(i, i, 8); - tcg_temp_free_ptr(tp); =20 tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ); tcg_gen_addi_i64(clean_addr, clean_addr, 8); - tcg_temp_free_i64(t0); =20 tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); - tcg_temp_free_ptr(i); } =20 /* Predicate register stores can be any multiple of 2. */ @@ -4469,7 +4325,6 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int = vofs, default: g_assert_not_reached(); } - tcg_temp_free_i64(t0); } } =20 @@ -4578,8 +4433,6 @@ static void do_mem_zpa(DisasContext *s, int zt, int p= g, TCGv_i64 addr, =20 tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); fn(cpu_env, t_pg, addr, tcg_constant_i32(desc)); - - tcg_temp_free_ptr(t_pg); } =20 /* Indexed by [mte][be][dtype][nreg] */ @@ -4977,7 +4830,6 @@ static void do_ldrq(DisasContext *s, int zt, int pg, = TCGv_i64 addr, int dtype) =20 poff =3D offsetof(CPUARMState, vfp.preg_tmp); tcg_gen_st_i64(tmp, cpu_env, poff); - tcg_temp_free_i64(tmp); } =20 t_pg =3D tcg_temp_new_ptr(); @@ -4987,8 +4839,6 @@ static void do_ldrq(DisasContext *s, int zt, int pg, = TCGv_i64 addr, int dtype) =3D ldr_fns[s->mte_active[0]][s->be_data =3D=3D MO_BE][dtype][0]; fn(cpu_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt))); =20 - tcg_temp_free_ptr(t_pg); - /* Replicate that first quadword. */ if (vsz > 16) { int doff =3D vec_full_reg_offset(s, zt); @@ -5059,7 +4909,6 @@ static void do_ldro(DisasContext *s, int zt, int pg, = TCGv_i64 addr, int dtype) =20 poff =3D offsetof(CPUARMState, vfp.preg_tmp); tcg_gen_st_i64(tmp, cpu_env, poff); - tcg_temp_free_i64(tmp); } =20 t_pg =3D tcg_temp_new_ptr(); @@ -5069,8 +4918,6 @@ static void do_ldro(DisasContext *s, int zt, int pg, = TCGv_i64 addr, int dtype) =3D ldr_fns[s->mte_active[0]][s->be_data =3D=3D MO_BE][dtype][0]; fn(cpu_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt))); =20 - tcg_temp_free_ptr(t_pg); - /* * Replicate that first octaword. * The replication happens in units of 32; if the full vector size @@ -5148,12 +4995,10 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rp= ri_load *a) tcg_gen_ld_i64(temp, cpu_env, pred_full_reg_offset(s, a->pg)); tcg_gen_andi_i64(temp, temp, pred_esz_masks[esz] & psz_mask); tcg_gen_brcondi_i64(TCG_COND_EQ, temp, 0, over); - tcg_temp_free_i64(temp); } else { TCGv_i32 t32 =3D tcg_temp_new_i32(); find_last_active(s, t32, esz, a->pg); tcg_gen_brcondi_i32(TCG_COND_LT, t32, 0, over); - tcg_temp_free_i32(t32); } =20 /* Load the data. */ @@ -5167,7 +5012,6 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri= _load *a) /* Broadcast to *all* elements. */ tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd), vsz, vsz, temp); - tcg_temp_free_i64(temp); =20 /* Zero the inactive elements. */ gen_set_label(over); @@ -5363,10 +5207,6 @@ static void do_mem_zpz(DisasContext *s, int zt, int = pg, int zm, tcg_gen_addi_ptr(t_zm, cpu_env, vec_full_reg_offset(s, zm)); tcg_gen_addi_ptr(t_zt, cpu_env, vec_full_reg_offset(s, zt)); fn(cpu_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc)); - - tcg_temp_free_ptr(t_zt); - tcg_temp_free_ptr(t_zm); - tcg_temp_free_ptr(t_pg); } =20 /* Indexed by [mte][be][ff][xs][u][msz]. */ @@ -6301,7 +6141,6 @@ static void gen_sshll_vec(unsigned vece, TCGv_vec d, = TCGv_vec n, int64_t imm) TCGv_vec t =3D tcg_temp_new_vec_matching(d); tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(halfbits, halfbits)); tcg_gen_and_vec(vece, d, n, t); - tcg_temp_free_vec(t); } else { tcg_gen_sari_vec(vece, d, n, halfbits); tcg_gen_shli_vec(vece, d, d, shl); @@ -6359,7 +6198,6 @@ static void gen_ushll_vec(unsigned vece, TCGv_vec d, = TCGv_vec n, int64_t imm) TCGv_vec t =3D tcg_temp_new_vec_matching(d); tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(halfbits, halfbits)); tcg_gen_and_vec(vece, d, n, t); - tcg_temp_free_vec(t); } else { tcg_gen_shri_vec(vece, d, n, halfbits); tcg_gen_shli_vec(vece, d, d, shl); @@ -6369,7 +6207,6 @@ static void gen_ushll_vec(unsigned vece, TCGv_vec d, = TCGv_vec n, int64_t imm) TCGv_vec t =3D tcg_temp_new_vec_matching(d); tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); tcg_gen_and_vec(vece, d, n, t); - tcg_temp_free_vec(t); } else { tcg_gen_shli_vec(vece, d, n, halfbits); tcg_gen_shri_vec(vece, d, d, halfbits - shl); @@ -6549,7 +6386,6 @@ static void gen_sqxtnb_vec(unsigned vece, TCGv_vec d,= TCGv_vec n) tcg_gen_smin_vec(vece, d, d, t); tcg_gen_dupi_vec(vece, t, mask); tcg_gen_and_vec(vece, d, d, t); - tcg_temp_free_vec(t); } =20 static const GVecGen2 sqxtnb_ops[3] =3D { @@ -6583,7 +6419,6 @@ static void gen_sqxtnt_vec(unsigned vece, TCGv_vec d,= TCGv_vec n) tcg_gen_shli_vec(vece, n, n, halfbits); tcg_gen_dupi_vec(vece, t, mask); tcg_gen_bitsel_vec(vece, d, t, d, n); - tcg_temp_free_vec(t); } =20 static const GVecGen2 sqxtnt_ops[3] =3D { @@ -6617,7 +6452,6 @@ static void gen_uqxtnb_vec(unsigned vece, TCGv_vec d,= TCGv_vec n) =20 tcg_gen_dupi_vec(vece, t, max); tcg_gen_umin_vec(vece, d, n, t); - tcg_temp_free_vec(t); } =20 static const GVecGen2 uqxtnb_ops[3] =3D { @@ -6646,7 +6480,6 @@ static void gen_uqxtnt_vec(unsigned vece, TCGv_vec d,= TCGv_vec n) tcg_gen_umin_vec(vece, n, n, t); tcg_gen_shli_vec(vece, n, n, halfbits); tcg_gen_bitsel_vec(vece, d, t, d, n); - tcg_temp_free_vec(t); } =20 static const GVecGen2 uqxtnt_ops[3] =3D { @@ -6682,7 +6515,6 @@ static void gen_sqxtunb_vec(unsigned vece, TCGv_vec d= , TCGv_vec n) tcg_gen_smax_vec(vece, d, n, t); tcg_gen_dupi_vec(vece, t, max); tcg_gen_umin_vec(vece, d, d, t); - tcg_temp_free_vec(t); } =20 static const GVecGen2 sqxtunb_ops[3] =3D { @@ -6713,7 +6545,6 @@ static void gen_sqxtunt_vec(unsigned vece, TCGv_vec d= , TCGv_vec n) tcg_gen_umin_vec(vece, n, n, t); tcg_gen_shli_vec(vece, n, n, halfbits); tcg_gen_bitsel_vec(vece, d, t, d, n); - tcg_temp_free_vec(t); } =20 static const GVecGen2 sqxtunt_ops[3] =3D { @@ -6784,7 +6615,6 @@ static void gen_shrnb_vec(unsigned vece, TCGv_vec d, = TCGv_vec n, int64_t shr) tcg_gen_shri_vec(vece, n, n, shr); tcg_gen_dupi_vec(vece, t, mask); tcg_gen_and_vec(vece, d, n, t); - tcg_temp_free_vec(t); } =20 static const TCGOpcode shrnb_vec_list[] =3D { INDEX_op_shri_vec, 0 }; @@ -6843,7 +6673,6 @@ static void gen_shrnt_vec(unsigned vece, TCGv_vec d, = TCGv_vec n, int64_t shr) tcg_gen_shli_vec(vece, n, n, halfbits - shr); tcg_gen_dupi_vec(vece, t, mask); tcg_gen_bitsel_vec(vece, d, t, d, n); - tcg_temp_free_vec(t); } =20 static const TCGOpcode shrnt_vec_list[] =3D { INDEX_op_shli_vec, 0 }; @@ -6894,7 +6723,6 @@ static void gen_sqshrunb_vec(unsigned vece, TCGv_vec = d, tcg_gen_smax_vec(vece, n, n, t); tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); tcg_gen_umin_vec(vece, d, n, t); - tcg_temp_free_vec(t); } =20 static const TCGOpcode sqshrunb_vec_list[] =3D { @@ -6929,7 +6757,6 @@ static void gen_sqshrunt_vec(unsigned vece, TCGv_vec = d, tcg_gen_umin_vec(vece, n, n, t); tcg_gen_shli_vec(vece, n, n, halfbits); tcg_gen_bitsel_vec(vece, d, t, d, n); - tcg_temp_free_vec(t); } =20 static const TCGOpcode sqshrunt_vec_list[] =3D { @@ -6984,7 +6811,6 @@ static void gen_sqshrnb_vec(unsigned vece, TCGv_vec d, tcg_gen_smin_vec(vece, n, n, t); tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); tcg_gen_and_vec(vece, d, n, t); - tcg_temp_free_vec(t); } =20 static const TCGOpcode sqshrnb_vec_list[] =3D { @@ -7022,7 +6848,6 @@ static void gen_sqshrnt_vec(unsigned vece, TCGv_vec d, tcg_gen_shli_vec(vece, n, n, halfbits); tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); tcg_gen_bitsel_vec(vece, d, t, d, n); - tcg_temp_free_vec(t); } =20 static const TCGOpcode sqshrnt_vec_list[] =3D { @@ -7071,7 +6896,6 @@ static void gen_uqshrnb_vec(unsigned vece, TCGv_vec d, tcg_gen_shri_vec(vece, n, n, shr); tcg_gen_dupi_vec(vece, t, MAKE_64BIT_MASK(0, halfbits)); tcg_gen_umin_vec(vece, d, n, t); - tcg_temp_free_vec(t); } =20 static const TCGOpcode uqshrnb_vec_list[] =3D { @@ -7104,7 +6928,6 @@ static void gen_uqshrnt_vec(unsigned vece, TCGv_vec d, tcg_gen_umin_vec(vece, n, n, t); tcg_gen_shli_vec(vece, n, n, halfbits); tcg_gen_bitsel_vec(vece, d, t, d, n); - tcg_temp_free_vec(t); } =20 static const TCGOpcode uqshrnt_vec_list[] =3D { @@ -7440,11 +7263,6 @@ static bool trans_PSEL(DisasContext *s, arg_psel *a) /* Apply to either copy the source, or write zeros. */ tcg_gen_gvec_ands(MO_64, pred_full_reg_offset(s, a->pd), pred_full_reg_offset(s, a->pn), tmp, pl, pl); - - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(dbit); - tcg_temp_free_i64(didx); - tcg_temp_free_ptr(ptr); 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Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/arm/translate-vfp.c | 193 ------------------------------------- 1 file changed, 193 deletions(-) diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 5c5d58d2c6..757a2bf7d9 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -178,7 +178,6 @@ static void gen_update_fp_context(DisasContext *s) =20 fpscr =3D load_cpu_field(v7m.fpdscr[s->v8m_secure]); gen_helper_vfp_set_fpscr(cpu_env, fpscr); - tcg_temp_free_i32(fpscr); if (dc_isar_feature(aa32_mve, s)) { store_cpu_field(tcg_constant_i32(0), v7m.vpr); } @@ -365,24 +364,15 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) tmp =3D tcg_temp_new_i64(); tcg_gen_xor_i64(tmp, vf, nf); tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, frn, frm); - tcg_temp_free_i64(tmp); break; case 3: /* gt: !Z && N =3D=3D V */ tcg_gen_movcond_i64(TCG_COND_NE, dest, zf, zero, frn, frm); tmp =3D tcg_temp_new_i64(); tcg_gen_xor_i64(tmp, vf, nf); tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, dest, frm); - tcg_temp_free_i64(tmp); break; } vfp_store_reg64(dest, rd); - tcg_temp_free_i64(frn); - tcg_temp_free_i64(frm); - tcg_temp_free_i64(dest); - - tcg_temp_free_i64(zf); - tcg_temp_free_i64(nf); - tcg_temp_free_i64(vf); } else { TCGv_i32 frn, frm, dest; TCGv_i32 tmp, zero; @@ -405,14 +395,12 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) tmp =3D tcg_temp_new_i32(); tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF); tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, frn, frm); - tcg_temp_free_i32(tmp); break; case 3: /* gt: !Z && N =3D=3D V */ tcg_gen_movcond_i32(TCG_COND_NE, dest, cpu_ZF, zero, frn, frm); tmp =3D tcg_temp_new_i32(); tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF); tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, dest, frm); - tcg_temp_free_i32(tmp); break; } /* For fp16 the top half is always zeroes */ @@ -420,9 +408,6 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) tcg_gen_andi_i32(dest, dest, 0xffff); } vfp_store_reg32(dest, rd); - tcg_temp_free_i32(frn); - tcg_temp_free_i32(frm); - tcg_temp_free_i32(dest); } =20 return true; @@ -490,8 +475,6 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) vfp_load_reg64(tcg_op, rm); gen_helper_rintd(tcg_res, tcg_op, fpst); vfp_store_reg64(tcg_res, rd); - tcg_temp_free_i64(tcg_op); - tcg_temp_free_i64(tcg_res); } else { TCGv_i32 tcg_op; TCGv_i32 tcg_res; @@ -504,14 +487,9 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) gen_helper_rints(tcg_res, tcg_op, fpst); } vfp_store_reg32(tcg_res, rd); - tcg_temp_free_i32(tcg_op); - tcg_temp_free_i32(tcg_res); } =20 gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - tcg_temp_free_i32(tcg_rmode); - - tcg_temp_free_ptr(fpst); return true; } =20 @@ -573,9 +551,6 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) } tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res); vfp_store_reg32(tcg_tmp, rd); - tcg_temp_free_i32(tcg_tmp); - tcg_temp_free_i64(tcg_res); - tcg_temp_free_i64(tcg_double); } else { TCGv_i32 tcg_single, tcg_res; tcg_single =3D tcg_temp_new_i32(); @@ -595,15 +570,9 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) } } vfp_store_reg32(tcg_res, rd); - tcg_temp_free_i32(tcg_res); - tcg_temp_free_i32(tcg_single); } =20 gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - tcg_temp_free_i32(tcg_rmode); - - tcg_temp_free_ptr(fpst); - return true; } =20 @@ -729,7 +698,6 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMO= V_from_gp *a) if (!mve_skip_vmov(s, a->vn, a->index, a->size)) { tmp =3D load_reg(s, a->rt); write_neon_element32(tmp, a->vn, a->index, a->size); - tcg_temp_free_i32(tmp); } =20 if (dc_isar_feature(aa32_mve, s)) { @@ -777,8 +745,6 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) tmp =3D load_reg(s, a->rt); tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(a->vn), vec_size, vec_size, tmp); - tcg_temp_free_i32(tmp); - return true; } =20 @@ -883,7 +849,6 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_V= MRS *a) if (a->rt =3D=3D 15) { /* Set the 4 flag bits in the CPSR. */ gen_set_nzcv(tmp); - tcg_temp_free_i32(tmp); } else { store_reg(s, a->rt, tmp); } @@ -899,7 +864,6 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_V= MRS *a) case ARM_VFP_FPSCR: tmp =3D load_reg(s, a->rt); gen_helper_vfp_set_fpscr(cpu_env, tmp); - tcg_temp_free_i32(tmp); gen_lookup_tb(s); break; case ARM_VFP_FPEXC: @@ -954,7 +918,6 @@ static bool trans_VMOV_half(DisasContext *s, arg_VMOV_s= ingle *a) tmp =3D load_reg(s, a->rt); tcg_gen_andi_i32(tmp, tmp, 0xffff); vfp_store_reg32(tmp, a->vn); - tcg_temp_free_i32(tmp); } =20 return true; @@ -979,7 +942,6 @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV= _single *a) if (a->rt =3D=3D 15) { /* Set the 4 flag bits in the CPSR. */ gen_set_nzcv(tmp); - tcg_temp_free_i32(tmp); } else { store_reg(s, a->rt, tmp); } @@ -987,7 +949,6 @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV= _single *a) /* general purpose register to VFP */ tmp =3D load_reg(s, a->rt); vfp_store_reg32(tmp, a->vn); - tcg_temp_free_i32(tmp); } =20 return true; @@ -1021,10 +982,8 @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMO= V_64_sp *a) /* gpreg to fpreg */ tmp =3D load_reg(s, a->rt); vfp_store_reg32(tmp, a->vm); - tcg_temp_free_i32(tmp); tmp =3D load_reg(s, a->rt2); vfp_store_reg32(tmp, a->vm + 1); - tcg_temp_free_i32(tmp); } =20 return true; @@ -1064,10 +1023,8 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VM= OV_64_dp *a) /* gpreg to fpreg */ tmp =3D load_reg(s, a->rt); vfp_store_reg32(tmp, a->vm * 2); - tcg_temp_free_i32(tmp); tmp =3D load_reg(s, a->rt2); vfp_store_reg32(tmp, a->vm * 2 + 1); - tcg_temp_free_i32(tmp); } =20 return true; @@ -1102,9 +1059,6 @@ static bool trans_VLDR_VSTR_hp(DisasContext *s, arg_V= LDR_VSTR_sp *a) vfp_load_reg32(tmp, a->vd); gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UW | MO_ALIGN); } - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(addr); - return true; } =20 @@ -1136,9 +1090,6 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_V= LDR_VSTR_sp *a) vfp_load_reg32(tmp, a->vd); gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); } - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(addr); - return true; } =20 @@ -1177,9 +1128,6 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_V= LDR_VSTR_dp *a) vfp_load_reg64(tmp, a->vd); gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), MO_UQ | MO_ALIGN_4= ); } - tcg_temp_free_i64(tmp); - tcg_temp_free_i32(addr); - return true; } =20 @@ -1246,7 +1194,6 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_V= LDM_VSTM_sp *a) } tcg_gen_addi_i32(addr, addr, offset); } - tcg_temp_free_i32(tmp); if (a->w) { /* writeback */ if (a->p) { @@ -1254,8 +1201,6 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_V= LDM_VSTM_sp *a) tcg_gen_addi_i32(addr, addr, offset); } store_reg(s, a->rn, addr); - } else { - tcg_temp_free_i32(addr); } =20 clear_eci_state(s); @@ -1332,7 +1277,6 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_V= LDM_VSTM_dp *a) } tcg_gen_addi_i32(addr, addr, offset); } - tcg_temp_free_i64(tmp); if (a->w) { /* writeback */ if (a->p) { @@ -1347,8 +1291,6 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_V= LDM_VSTM_dp *a) tcg_gen_addi_i32(addr, addr, offset); } store_reg(s, a->rn, addr); - } else { - tcg_temp_free_i32(addr); } =20 clear_eci_state(s); @@ -1485,12 +1427,6 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3Op= SPFn *fn, vfp_load_reg32(f1, vm); } } - - tcg_temp_free_i32(f0); - tcg_temp_free_i32(f1); - tcg_temp_free_i32(fd); - tcg_temp_free_ptr(fpst); - return true; } =20 @@ -1533,12 +1469,6 @@ static bool do_vfp_3op_hp(DisasContext *s, VFPGen3Op= SPFn *fn, } fn(fd, f0, f1, fpst); vfp_store_reg32(fd, vd); - - tcg_temp_free_i32(f0); - tcg_temp_free_i32(f1); - tcg_temp_free_i32(fd); - tcg_temp_free_ptr(fpst); - return true; } =20 @@ -1615,12 +1545,6 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3Op= DPFn *fn, vfp_load_reg64(f1, vm); } } - - tcg_temp_free_i64(f0); - tcg_temp_free_i64(f1); - tcg_temp_free_i64(fd); - tcg_temp_free_ptr(fpst); - return true; } =20 @@ -1688,10 +1612,6 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2Op= SPFn *fn, int vd, int vm) vm =3D vfp_advance_sreg(vm, delta_m); vfp_load_reg32(f0, vm); } - - tcg_temp_free_i32(f0); - tcg_temp_free_i32(fd); - return true; } =20 @@ -1724,7 +1644,6 @@ static bool do_vfp_2op_hp(DisasContext *s, VFPGen2OpS= PFn *fn, int vd, int vm) vfp_load_reg32(f0, vm); fn(f0, f0); vfp_store_reg32(f0, vd); - tcg_temp_free_i32(f0); =20 return true; } @@ -1798,10 +1717,6 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2Op= DPFn *fn, int vd, int vm) vd =3D vfp_advance_dreg(vm, delta_m); vfp_load_reg64(f0, vm); } - - tcg_temp_free_i64(f0); - tcg_temp_free_i64(fd); - return true; } =20 @@ -1812,7 +1727,6 @@ static void gen_VMLA_hp(TCGv_i32 vd, TCGv_i32 vn, TCG= v_i32 vm, TCGv_ptr fpst) =20 gen_helper_vfp_mulh(tmp, vn, vm, fpst); gen_helper_vfp_addh(vd, vd, tmp, fpst); - tcg_temp_free_i32(tmp); } =20 static bool trans_VMLA_hp(DisasContext *s, arg_VMLA_sp *a) @@ -1827,7 +1741,6 @@ static void gen_VMLA_sp(TCGv_i32 vd, TCGv_i32 vn, TCG= v_i32 vm, TCGv_ptr fpst) =20 gen_helper_vfp_muls(tmp, vn, vm, fpst); gen_helper_vfp_adds(vd, vd, tmp, fpst); - tcg_temp_free_i32(tmp); } =20 static bool trans_VMLA_sp(DisasContext *s, arg_VMLA_sp *a) @@ -1842,7 +1755,6 @@ static void gen_VMLA_dp(TCGv_i64 vd, TCGv_i64 vn, TCG= v_i64 vm, TCGv_ptr fpst) =20 gen_helper_vfp_muld(tmp, vn, vm, fpst); gen_helper_vfp_addd(vd, vd, tmp, fpst); - tcg_temp_free_i64(tmp); } =20 static bool trans_VMLA_dp(DisasContext *s, arg_VMLA_dp *a) @@ -1861,7 +1773,6 @@ static void gen_VMLS_hp(TCGv_i32 vd, TCGv_i32 vn, TCG= v_i32 vm, TCGv_ptr fpst) gen_helper_vfp_mulh(tmp, vn, vm, fpst); gen_helper_vfp_negh(tmp, tmp); gen_helper_vfp_addh(vd, vd, tmp, fpst); - tcg_temp_free_i32(tmp); } =20 static bool trans_VMLS_hp(DisasContext *s, arg_VMLS_sp *a) @@ -1880,7 +1791,6 @@ static void gen_VMLS_sp(TCGv_i32 vd, TCGv_i32 vn, TCG= v_i32 vm, TCGv_ptr fpst) gen_helper_vfp_muls(tmp, vn, vm, fpst); gen_helper_vfp_negs(tmp, tmp); gen_helper_vfp_adds(vd, vd, tmp, fpst); - tcg_temp_free_i32(tmp); } =20 static bool trans_VMLS_sp(DisasContext *s, arg_VMLS_sp *a) @@ -1899,7 +1809,6 @@ static void gen_VMLS_dp(TCGv_i64 vd, TCGv_i64 vn, TCG= v_i64 vm, TCGv_ptr fpst) gen_helper_vfp_muld(tmp, vn, vm, fpst); gen_helper_vfp_negd(tmp, tmp); gen_helper_vfp_addd(vd, vd, tmp, fpst); - tcg_temp_free_i64(tmp); } =20 static bool trans_VMLS_dp(DisasContext *s, arg_VMLS_dp *a) @@ -1920,7 +1829,6 @@ static void gen_VNMLS_hp(TCGv_i32 vd, TCGv_i32 vn, TC= Gv_i32 vm, TCGv_ptr fpst) gen_helper_vfp_mulh(tmp, vn, vm, fpst); gen_helper_vfp_negh(vd, vd); gen_helper_vfp_addh(vd, vd, tmp, fpst); - tcg_temp_free_i32(tmp); } =20 static bool trans_VNMLS_hp(DisasContext *s, arg_VNMLS_sp *a) @@ -1941,7 +1849,6 @@ static void gen_VNMLS_sp(TCGv_i32 vd, TCGv_i32 vn, TC= Gv_i32 vm, TCGv_ptr fpst) gen_helper_vfp_muls(tmp, vn, vm, fpst); gen_helper_vfp_negs(vd, vd); gen_helper_vfp_adds(vd, vd, tmp, fpst); - tcg_temp_free_i32(tmp); } =20 static bool trans_VNMLS_sp(DisasContext *s, arg_VNMLS_sp *a) @@ -1962,7 +1869,6 @@ static void gen_VNMLS_dp(TCGv_i64 vd, TCGv_i64 vn, TC= Gv_i64 vm, TCGv_ptr fpst) gen_helper_vfp_muld(tmp, vn, vm, fpst); gen_helper_vfp_negd(vd, vd); gen_helper_vfp_addd(vd, vd, tmp, fpst); - tcg_temp_free_i64(tmp); } =20 static bool trans_VNMLS_dp(DisasContext *s, arg_VNMLS_dp *a) @@ -1979,7 +1885,6 @@ static void gen_VNMLA_hp(TCGv_i32 vd, TCGv_i32 vn, TC= Gv_i32 vm, TCGv_ptr fpst) gen_helper_vfp_negh(tmp, tmp); gen_helper_vfp_negh(vd, vd); gen_helper_vfp_addh(vd, vd, tmp, fpst); - tcg_temp_free_i32(tmp); } =20 static bool trans_VNMLA_hp(DisasContext *s, arg_VNMLA_sp *a) @@ -1996,7 +1901,6 @@ static void gen_VNMLA_sp(TCGv_i32 vd, TCGv_i32 vn, TC= Gv_i32 vm, TCGv_ptr fpst) gen_helper_vfp_negs(tmp, tmp); gen_helper_vfp_negs(vd, vd); gen_helper_vfp_adds(vd, vd, tmp, fpst); - tcg_temp_free_i32(tmp); } =20 static bool trans_VNMLA_sp(DisasContext *s, arg_VNMLA_sp *a) @@ -2013,7 +1917,6 @@ static void gen_VNMLA_dp(TCGv_i64 vd, TCGv_i64 vn, TC= Gv_i64 vm, TCGv_ptr fpst) gen_helper_vfp_negd(tmp, tmp); gen_helper_vfp_negd(vd, vd); gen_helper_vfp_addd(vd, vd, tmp, fpst); - tcg_temp_free_i64(tmp); } =20 static bool trans_VNMLA_dp(DisasContext *s, arg_VNMLA_dp *a) @@ -2225,12 +2128,6 @@ static bool do_vfm_hp(DisasContext *s, arg_VFMA_sp *= a, bool neg_n, bool neg_d) fpst =3D fpstatus_ptr(FPST_FPCR_F16); gen_helper_vfp_muladdh(vd, vn, vm, vd, fpst); vfp_store_reg32(vd, a->vd); - - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(vn); - tcg_temp_free_i32(vm); - tcg_temp_free_i32(vd); - return true; } =20 @@ -2290,12 +2187,6 @@ static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *= a, bool neg_n, bool neg_d) fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_vfp_muladds(vd, vn, vm, vd, fpst); vfp_store_reg32(vd, a->vd); - - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(vn); - tcg_temp_free_i32(vm); - tcg_temp_free_i32(vd); - return true; } =20 @@ -2361,12 +2252,6 @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *= a, bool neg_n, bool neg_d) fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst); vfp_store_reg64(vd, a->vd); - - tcg_temp_free_ptr(fpst); - tcg_temp_free_i64(vn); - tcg_temp_free_i64(vm); - tcg_temp_free_i64(vd); - return true; } =20 @@ -2591,10 +2476,6 @@ static bool trans_VCMP_hp(DisasContext *s, arg_VCMP_= sp *a) } else { gen_helper_vfp_cmph(vd, vm, cpu_env); } - - tcg_temp_free_i32(vd); - tcg_temp_free_i32(vm); - return true; } =20 @@ -2630,10 +2511,6 @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_= sp *a) } else { gen_helper_vfp_cmps(vd, vm, cpu_env); } - - tcg_temp_free_i32(vd); - tcg_temp_free_i32(vm); - return true; } =20 @@ -2674,10 +2551,6 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_= dp *a) } else { gen_helper_vfp_cmpd(vd, vm, cpu_env); } - - tcg_temp_free_i64(vd); - tcg_temp_free_i64(vm); - return true; } =20 @@ -2702,9 +2575,6 @@ static bool trans_VCVT_f32_f16(DisasContext *s, arg_V= CVT_f32_f16 *a) tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode); vfp_store_reg32(tmp, a->vd); - tcg_temp_free_i32(ahp_mode); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tmp); return true; } =20 @@ -2740,10 +2610,6 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_= VCVT_f64_f16 *a) vd =3D tcg_temp_new_i64(); gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode); vfp_store_reg64(vd, a->vd); - tcg_temp_free_i32(ahp_mode); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tmp); - tcg_temp_free_i64(vd); return true; } =20 @@ -2766,8 +2632,6 @@ static bool trans_VCVT_b16_f32(DisasContext *s, arg_V= CVT_b16_f32 *a) vfp_load_reg32(tmp, a->vm); gen_helper_bfcvt(tmp, tmp, fpst); tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tmp); return true; } =20 @@ -2792,9 +2656,6 @@ static bool trans_VCVT_f16_f32(DisasContext *s, arg_V= CVT_f16_f32 *a) vfp_load_reg32(tmp, a->vm); gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode); tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); - tcg_temp_free_i32(ahp_mode); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tmp); return true; } =20 @@ -2829,11 +2690,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_= VCVT_f16_f64 *a) =20 vfp_load_reg64(vm, a->vm); gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode); - tcg_temp_free_i64(vm); tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); - tcg_temp_free_i32(ahp_mode); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tmp); return true; } =20 @@ -2855,8 +2712,6 @@ static bool trans_VRINTR_hp(DisasContext *s, arg_VRIN= TR_sp *a) fpst =3D fpstatus_ptr(FPST_FPCR_F16); gen_helper_rinth(tmp, tmp, fpst); vfp_store_reg32(tmp, a->vd); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tmp); return true; } =20 @@ -2878,8 +2733,6 @@ static bool trans_VRINTR_sp(DisasContext *s, arg_VRIN= TR_sp *a) fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_rints(tmp, tmp, fpst); vfp_store_reg32(tmp, a->vd); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tmp); return true; } =20 @@ -2910,8 +2763,6 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRIN= TR_dp *a) fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_rintd(tmp, tmp, fpst); vfp_store_reg64(tmp, a->vd); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i64(tmp); return true; } =20 @@ -2937,9 +2788,6 @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRIN= TZ_sp *a) gen_helper_rinth(tmp, tmp, fpst); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); vfp_store_reg32(tmp, a->vd); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tcg_rmode); - tcg_temp_free_i32(tmp); return true; } =20 @@ -2965,9 +2813,6 @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRIN= TZ_sp *a) gen_helper_rints(tmp, tmp, fpst); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); vfp_store_reg32(tmp, a->vd); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tcg_rmode); - tcg_temp_free_i32(tmp); return true; } =20 @@ -3002,9 +2847,6 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRIN= TZ_dp *a) gen_helper_rintd(tmp, tmp, fpst); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); vfp_store_reg64(tmp, a->vd); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i64(tmp); - tcg_temp_free_i32(tcg_rmode); return true; } =20 @@ -3026,8 +2868,6 @@ static bool trans_VRINTX_hp(DisasContext *s, arg_VRIN= TX_sp *a) fpst =3D fpstatus_ptr(FPST_FPCR_F16); gen_helper_rinth_exact(tmp, tmp, fpst); vfp_store_reg32(tmp, a->vd); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tmp); return true; } =20 @@ -3049,8 +2889,6 @@ static bool trans_VRINTX_sp(DisasContext *s, arg_VRIN= TX_sp *a) fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_rints_exact(tmp, tmp, fpst); vfp_store_reg32(tmp, a->vd); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i32(tmp); return true; } =20 @@ -3081,8 +2919,6 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRIN= TX_dp *a) fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_rintd_exact(tmp, tmp, fpst); vfp_store_reg64(tmp, a->vd); - tcg_temp_free_ptr(fpst); - tcg_temp_free_i64(tmp); return true; } =20 @@ -3109,8 +2945,6 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_s= p *a) vfp_load_reg32(vm, a->vm); gen_helper_vfp_fcvtds(vd, vm, cpu_env); vfp_store_reg64(vd, a->vd); - tcg_temp_free_i32(vm); - tcg_temp_free_i64(vd); return true; } =20 @@ -3137,8 +2971,6 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_d= p *a) vfp_load_reg64(vm, a->vm); gen_helper_vfp_fcvtsd(vd, vm, cpu_env); vfp_store_reg32(vd, a->vd); - tcg_temp_free_i32(vd); - tcg_temp_free_i64(vm); return true; } =20 @@ -3166,8 +2998,6 @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VC= VT_int_sp *a) gen_helper_vfp_uitoh(vm, vm, fpst); } vfp_store_reg32(vm, a->vd); - tcg_temp_free_i32(vm); - tcg_temp_free_ptr(fpst); return true; } =20 @@ -3195,8 +3025,6 @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VC= VT_int_sp *a) gen_helper_vfp_uitos(vm, vm, fpst); } vfp_store_reg32(vm, a->vd); - tcg_temp_free_i32(vm); - tcg_temp_free_ptr(fpst); return true; } =20 @@ -3231,9 +3059,6 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VC= VT_int_dp *a) gen_helper_vfp_uitod(vd, vm, fpst); } vfp_store_reg64(vd, a->vd); - tcg_temp_free_i32(vm); - tcg_temp_free_i64(vd); - tcg_temp_free_ptr(fpst); return true; } =20 @@ -3264,8 +3089,6 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) vfp_load_reg64(vm, a->vm); gen_helper_vjcvt(vd, vm, cpu_env); vfp_store_reg32(vd, a->vd); - tcg_temp_free_i64(vm); - tcg_temp_free_i32(vd); return true; } =20 @@ -3322,8 +3145,6 @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VC= VT_fix_sp *a) } =20 vfp_store_reg32(vd, a->vd); - tcg_temp_free_i32(vd); - tcg_temp_free_ptr(fpst); return true; } =20 @@ -3380,8 +3201,6 @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VC= VT_fix_sp *a) } =20 vfp_store_reg32(vd, a->vd); - tcg_temp_free_i32(vd); - tcg_temp_free_ptr(fpst); return true; } =20 @@ -3444,8 +3263,6 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VC= VT_fix_dp *a) } =20 vfp_store_reg64(vd, a->vd); - tcg_temp_free_i64(vd); - tcg_temp_free_ptr(fpst); return true; } =20 @@ -3480,8 +3297,6 @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VC= VT_sp_int *a) } } vfp_store_reg32(vm, a->vd); - tcg_temp_free_i32(vm); - tcg_temp_free_ptr(fpst); return true; } =20 @@ -3516,8 +3331,6 @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VC= VT_sp_int *a) } } vfp_store_reg32(vm, a->vd); - tcg_temp_free_i32(vm); - tcg_temp_free_ptr(fpst); return true; } =20 @@ -3559,9 +3372,6 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VC= VT_dp_int *a) } } vfp_store_reg32(vd, a->vd); - tcg_temp_free_i32(vd); - tcg_temp_free_i64(vm); - tcg_temp_free_ptr(fpst); return true; } =20 @@ -3588,8 +3398,6 @@ static bool trans_VINS(DisasContext *s, arg_VINS *a) vfp_load_reg32(rd, a->vd); tcg_gen_deposit_i32(rd, rd, rm, 16, 16); vfp_store_reg32(rd, a->vd); - tcg_temp_free_i32(rm); - tcg_temp_free_i32(rd); return true; } =20 @@ -3614,6 +3422,5 @@ static bool trans_VMOVX(DisasContext *s, arg_VINS *a) vfp_load_reg32(rm, a->vm); tcg_gen_shri_i32(rm, rm, 16); vfp_store_reg32(rm, a->vd); - tcg_temp_free_i32(rm); return true; } --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.25.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:25:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fUKDP/sNQLKaEx4yocSZm1dTXssXHt62OOCODiQNZGU=; b=pb2kbo47HbvRUUNVkcNeUOtIqlWwf+DS4XGfQ8tzQfe9OtQpRnodhBoB9GMTVapI80 Nm1umsGT9uAdU3Oy+UOieeyzrQXsRxqZJJjJC+r4I+4C7Mx/KC5ztwjn9Z1vSRLyC2ip uB/PXHbWywghcgZ1i/5/U/4LOpyLs95nuNmdPO2iQngNIaDA8pnR06JHzZOzJAEloxnH JuhiRMw/Wh7QCBAeHhYRMOOi/YvnQMOVzXUT0PqJK66OwmZcW+ieQ9X6TKdj2JM7S87y b/jD5bc88xWq+BJJdS2RYRwZ9t/y/LadW2yoRHHcQEscSlFvQQX+pwtpZzHHknPtryr0 LqQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fUKDP/sNQLKaEx4yocSZm1dTXssXHt62OOCODiQNZGU=; b=e8z1J6c4zfNjz4d6A+45TuL9oIDsl3KkuXD5kUOmuf9d0Px/7HdZRsxZi6waok5w4r VSWtKkCq8FAXnPkrWKMRczTECcnn5YgVc3fOWnVMCMbZ+KxxHBVCcP9QBaeyGNJaMTh2 pDEphnmBePXVtbTbRIEDMx4/FNzmRpEz3qPgcfRts2fikeBIdshbrtW812q5FI6BtWXW 46/WK2HkpYeB3hTtcpS0urU6dONIcLbU1IRF6DAROYVTeiluGEqiPSjAvWQriDZgMdyq EFQjNHivLP4WX11zUovZ8f04mIyZ5X0E8HjsmaSPXmuY+g7nHn7JZornsomENRZzZxUA cOIA== X-Gm-Message-State: AO0yUKVeIZ8zYNxhIOj/rYTlvzKpWSuXdyKZZXYU/oqbDIxPNCFWv0al R5L7U0L1AknYu4xuDjNBD4F8HjDza446UR9n0qI= X-Google-Smtp-Source: AK7set/otA9XSVpwNYlze3y0UqjlAjcFwQt9JjhDwhI2Fo969oVwwF8PwFLVo6iVxNYaOWTcIWv3CQ== X-Received: by 2002:a17:903:42cd:b0:19c:d452:b282 with SMTP id jy13-20020a17090342cd00b0019cd452b282mr9040245plb.12.1677475557365; Sun, 26 Feb 2023 21:25:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 17/76] target/arm: Drop tcg_temp_free from translator.h Date: Sun, 26 Feb 2023 19:24:06 -1000 Message-Id: <20230227052505.352889-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475768696100002 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/arm/translate.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index d7fdbc1e3e..3dbff87349 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -331,7 +331,6 @@ static inline void set_pstate_bits(uint32_t bits) tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); tcg_gen_ori_i32(p, p, bits); tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); - tcg_temp_free_i32(p); } =20 /* Clear bits within PSTATE. */ @@ -344,7 +343,6 @@ static inline void clear_pstate_bits(uint32_t bits) tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); tcg_gen_andi_i32(p, p, ~bits); tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); - tcg_temp_free_i32(p); } =20 /* If the singlestep state is Active-not-pending, advance to Active-pendin= g. */ --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677475865; cv=none; d=zohomail.com; s=zohoarc; b=YtlSpqcs7wL19rzZE1UNj63R2fPA6/p5uKyBJR9G/emWxXGmBH8Xl9/Fzfc2ejqjBTABMYO3lhcoaAc+aWVZQ2X784hqhxTcL0IoiRM2me6ulQul1elx9ckuEbFeaX8vJoHVYVn4i6s8nTHLF+W+yvrlq8lrtWSt/QSTyYDtyRQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677475865; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Gk4H/gx5fzfdthfB0AF4cgfQbvoN/h/04Yaxfs06mIY=; b=dgU0a47AlP4EqZGNM6GsDuOP9n25CkM9BUts4qsxb4BWcP21wdCI76qoiowN7C1IGeZN5B/G7yIhjKRDM1kxCVjxhzC1x1Sib9tvfpIYEAmdTmImV4pBoRGYDwgQWOkt1uGfjM87jHBWXu2ShsIlvl6zGNaPuHdEipHVGUb3kpQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677475865687343.72287958319566; Sun, 26 Feb 2023 21:31:05 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW1m-0007pQ-8D; Mon, 27 Feb 2023 00:26:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW1T-0007HY-So for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:26:04 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW1R-0007Xy-5c for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:26:03 -0500 Received: by mail-pj1-x102b.google.com with SMTP id l1so4875687pjt.2 for ; Sun, 26 Feb 2023 21:26:00 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.25.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:25:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Gk4H/gx5fzfdthfB0AF4cgfQbvoN/h/04Yaxfs06mIY=; b=dD0t6uI0pGApM5SWyG0MErMgEpv5CaKArSDb6d/nTo8GC0MZExohTA3tzFsf6PQQ/B nqeeY8lso8AUWVDB14Jk7/6b7dXZc0jhlI/T3JylJobHWkZE2lfqxYe8x7OnectdYM3T WmD6iI5J+S8s6uEvpZE+sPQO8Dq+jr6YbU8uw0Lg04mK8ZcxVKUka46M66YKxGGELM1u RAeIEB7GDjLiT/WWQ4RY2pcuxJn4yqBmUPGWYDDUq2oCRnuT4cQ5KOzxEdW7vgdSGzg3 mZoZF+i8CcUritjaOdrYoaiC7pCRvDfgqLGlnQdF9BkIaLbAQ/ACvW6tL4qfy1hMIh7F imzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Gk4H/gx5fzfdthfB0AF4cgfQbvoN/h/04Yaxfs06mIY=; b=TZfFtkjIrhtTUWV/XH68ItOMPSg8kByM/M4U9BdZ7AZEkT9uniKH4dVIiNCG/o0/hK spw3MpjyTtOCa343Lq4Ft9Fsg8k56aZDQ8sFavZtc3mC3f4vLNqGnoZ45oHAOVVnatFz IEPZdEfOjcVvdVRzAwackKWxtICpPuThI2ASy1ghkcGuBnINARBp6lwM0BSc9gVvArJo Ygi5E+vYU/7zV/hhb4tae+pNsSYLnVSPi9stQeJkHtHApcz0YD7cqAgvgnlPaD52UQhd wZ6K7sGccOV3TvOsBiYnhdV3rpC7ueqL9akl58dR8Iz2BPl+4KwqIZfHgBPEK+e+YERr sJFQ== X-Gm-Message-State: AO0yUKVdPPMs5pd9+oTnqKhqXQgHjsdZHuZyVxPz1lk4an1o6/87nTF9 hw9waVs/Vn+fVqUcUFxirv0AFZv2W/hFTh8GA9w= X-Google-Smtp-Source: AK7set9S2qWLaJTM3qzqHU47FR6GNIREaBLbElpYxQJTe0LnAMezy8tdPzj6J1wXxuN59HLKCd9R+g== X-Received: by 2002:a17:902:e54a:b0:19d:ab83:ec70 with SMTP id n10-20020a170902e54a00b0019dab83ec70mr159826plf.45.1677475559952; Sun, 26 Feb 2023 21:25:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 18/76] target/avr: Drop DisasContext.free_skip_var0 Date: Sun, 26 Feb 2023 19:24:07 -1000 Message-Id: <20230227052505.352889-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475867253100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries, therefore there's no need to record for later freeing. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/avr/translate.c | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index e40d8e9681..e7f0e2bbe3 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -107,11 +107,6 @@ struct DisasContext { * tcg_gen_brcond_tl(skip_cond, skip_var0, skip_var1, skip_label); * } * - * if (free_skip_var0) { - * tcg_temp_free(skip_var0); - * free_skip_var0 =3D false; - * } - * * translate(ctx); * * if (skip_label) { @@ -121,7 +116,6 @@ struct DisasContext { TCGv skip_var0; TCGv skip_var1; TCGCond skip_cond; - bool free_skip_var0; }; =20 void avr_cpu_tcg_init(void) @@ -1375,7 +1369,6 @@ static bool trans_SBRC(DisasContext *ctx, arg_SBRC *a) =20 ctx->skip_cond =3D TCG_COND_EQ; ctx->skip_var0 =3D tcg_temp_new(); - ctx->free_skip_var0 =3D true; =20 tcg_gen_andi_tl(ctx->skip_var0, Rr, 1 << a->bit); return true; @@ -1391,7 +1384,6 @@ static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a) =20 ctx->skip_cond =3D TCG_COND_NE; ctx->skip_var0 =3D tcg_temp_new(); - ctx->free_skip_var0 =3D true; =20 tcg_gen_andi_tl(ctx->skip_var0, Rr, 1 << a->bit); return true; @@ -1410,7 +1402,6 @@ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) tcg_gen_andi_tl(temp, temp, 1 << a->bit); ctx->skip_cond =3D TCG_COND_EQ; ctx->skip_var0 =3D temp; - ctx->free_skip_var0 =3D true; =20 return true; } @@ -1428,7 +1419,6 @@ static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a) tcg_gen_andi_tl(temp, temp, 1 << a->bit); ctx->skip_cond =3D TCG_COND_NE; ctx->skip_var0 =3D temp; - ctx->free_skip_var0 =3D true; =20 return true; } @@ -2886,10 +2876,6 @@ static bool canonicalize_skip(DisasContext *ctx) ctx->skip_cond =3D TCG_COND_NE; break; } - if (ctx->free_skip_var0) { - tcg_temp_free(ctx->skip_var0); - ctx->free_skip_var0 =3D false; - } ctx->skip_var0 =3D cpu_skip; return true; } @@ -2944,7 +2930,6 @@ static void avr_tr_translate_insn(DisasContextBase *d= cbase, CPUState *cs) * This ensures that cpu_skip is non-zero after the label * if and only if the skipped insn itself sets a skip. */ - ctx->free_skip_var0 =3D true; ctx->skip_var0 =3D tcg_temp_new(); tcg_gen_mov_tl(ctx->skip_var0, cpu_skip); tcg_gen_movi_tl(cpu_skip, 0); @@ -2956,10 +2941,6 @@ static void avr_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) ctx->skip_var1, skip_label); ctx->skip_var1 =3D NULL; } - if (ctx->free_skip_var0) { - tcg_temp_free(ctx->skip_var0); - ctx->free_skip_var0 =3D false; - } ctx->skip_cond =3D TCG_COND_NEVER; ctx->skip_var0 =3D NULL; } --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677476579; cv=none; d=zohomail.com; s=zohoarc; b=PpzSyKq6uH0sVvnQuuxEvcZjnVeB0AOqeAXtYxHAWBtgtgyq8Nh2k918xTqnciHlC8jeTDhDZUpHCQAdPLTstbIFYk2uDXyhp52W+yc44DY/0U1HGxQ310/wu5IgxKr006Yj+Kgm6s4nF+odxfsSq0sQRgjfeAeDneftR7lYtVg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677476579; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sDmUkw3rhG8oPNlT9S5tPo3W1aQ6y0j58Lj/IZXgOuc=; b=bYA9MqRrOmaezhmV6v0jhhV43rWfYe5UdkGAGR4wbw4SB1WMijvRbEWk4NlRISPnrY42Zp6ZC+twILWF7ubfmlHgXPPiNeM7INM304x0C2rvss42I8H/TJFQx9DM29oRZx27GJMSrYSqlXFlwOUxXMAtjhYsEwTOlh5YK2H+KkE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677476579743935.936151811443; Sun, 26 Feb 2023 21:42:59 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW1l-0007mr-OW; Mon, 27 Feb 2023 00:26:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW1V-0007KM-27 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:26:05 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW1T-0007Cv-A8 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:26:04 -0500 Received: by mail-pj1-x1035.google.com with SMTP id me6-20020a17090b17c600b0023816b0c7ceso912436pjb.2 for ; Sun, 26 Feb 2023 21:26:02 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.26.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:26:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sDmUkw3rhG8oPNlT9S5tPo3W1aQ6y0j58Lj/IZXgOuc=; b=haYDju3Oq0TFDt054lTRvhpdyhG8zQrYLQgWvStwosYWTF7DfYk1IxrgEN56G8Ay3w YUW2gID5JRO1+LtFd5OVvVUjd0UqENyltlH8lLIEfOplJccS5zqyLaP1LhVpF5dUNDoY j5SRjKrK3z0+yP0BmVioTx3RNjwNU8aC5WTkmYp6VXdOXcyndO0yDRm4NzbxP/tRqrkl 1r0Jo/KJ0IcahaTmeQtwD4x3ALtjXryAboDgthVJLy7eWtPFRUniWYaBgNaF0yQJ/ceT glgsE/HfF2HdhbHCCgV5TZOq0OfgDDMv81QpEvGg8HCEE/bImdlOeCn07NwiFjxE+3Ui /KZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sDmUkw3rhG8oPNlT9S5tPo3W1aQ6y0j58Lj/IZXgOuc=; b=s/DjvohZ0IBlgk/aWJHh4YHKuLgPv4Vv+eA9d/T0UKbp4ndvY3ROYfGFSzYZzgOfvb /ukNADe3rl+NyekvvhYfEaDzhtwxNPNMA69/E/bZ8n1t/fnZFrIlCDw0IODRwPaTyghW wbZdYibUw/NzO53OJfwcG5qLDmMTxEMscyYWoM6sB6CHM4GzeVSN/uyXj34+FlKkbsv+ MafNhpPM4YBhF7YiUaCWeGTN4vQqUSb3KFWD0xIS1H/kiDhdH7bNKkM8QN0pEUp4BUdo I4CINlqKH1UqHMqXJTeaK9wG7bPGOZva8VYHfvUIG+YhRWP6J5F4Ez+xcyzgvQJyOLIt JRLg== X-Gm-Message-State: AO0yUKXsnalpMiWemjarw02rRTZKhvI2sKXOposG2ub2lMiIjP1f8y0W PQzt/95stZogCKQpJbt96dvf9lYrEwFoyZBK4ik= X-Google-Smtp-Source: AK7set8W9RMQUbuGHkBa56ZwzlcEiqGNtkhXoZukDkPODsPLd3E2bHNArOowCSYWauG4+C5x1+noIw== X-Received: by 2002:a17:902:d4c4:b0:19d:6f7:70d2 with SMTP id o4-20020a170902d4c400b0019d06f770d2mr2969392plg.50.1677475562632; Sun, 26 Feb 2023 21:26:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 19/76] target/avr: Drop R from trans_COM Date: Sun, 26 Feb 2023 19:24:08 -1000 Message-Id: <20230227052505.352889-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476580507100001 Content-Type: text/plain; charset="utf-8" This variable is not used, only allocated and freed. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/avr/translate.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index e7f0e2bbe3..4f8112c3e6 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -670,7 +670,6 @@ static bool trans_EOR(DisasContext *ctx, arg_EOR *a) static bool trans_COM(DisasContext *ctx, arg_COM *a) { TCGv Rd =3D cpu_r[a->rd]; - TCGv R =3D tcg_temp_new_i32(); =20 tcg_gen_xori_tl(Rd, Rd, 0xff); =20 @@ -678,9 +677,6 @@ static bool trans_COM(DisasContext *ctx, arg_COM *a) tcg_gen_movi_tl(cpu_Cf, 1); /* Cf =3D 1 */ tcg_gen_movi_tl(cpu_Vf, 0); /* Vf =3D 0 */ gen_ZNSf(Rd); - - tcg_temp_free_i32(R); - return true; } =20 --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677476477; cv=none; d=zohomail.com; s=zohoarc; b=Z14nTiKhVK4OsgUZIMTXM0YfR/9EA80hH1aONSq69dBZFgll02G0HcLF7L81UUAy1OlDnW19WnGuh+PW6RtOckW7REUWgGIjgYA8OXZ8IPF4uxOFO5Oq/kk+EtBFzz/6t6maesClLkxFYMygmqQePD4F/Wh2+u6QmC6ApT/nyJ0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677476477; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VDigh3LB3s6a/Rl+FCKzmXQVkFODGqoxKbWHFAog88M=; b=SIKC5OgMuK6KYnJ/Hn7QDvFx52wIgayLig/KURIpJNrvmjJtuo6vua8+RssY4vruIJIQFWPlyka6AHQ6hIpGH9ESZ0fT5GFGSh2NqpPfvK86pfhGvvKY/XWXuPaHKExueDIA2Gzkunxpv2SyFhXp3P7/JvdygV7DIEqc/483VkU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677476477366358.6347093785047; Sun, 26 Feb 2023 21:41:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW1n-0007tx-9F; Mon, 27 Feb 2023 00:26:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW1b-0007RH-VK for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:26:13 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW1X-0007aV-4l for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:26:11 -0500 Received: by mail-pl1-x62d.google.com with SMTP id y11so1381970plg.1 for ; Sun, 26 Feb 2023 21:26:06 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.26.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:26:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VDigh3LB3s6a/Rl+FCKzmXQVkFODGqoxKbWHFAog88M=; b=UPaUNyhkbfn5ggIGRDsDj95zzTZRFvfQEMst2Yt0/u9IK34EeYPA5zNw9Awt4eql3e YOY6boDL62zwRWW/PJ7lmoVkRP2CVrsv7mbxmQTfGNbM7xldCnl9OrH/92hd7V3KXFUX jto1tzJpqoiTNYQHM8WSmUQj14jF5FF6Ubv+fE1FOa3Z9t7a3j/e/1jXMu5m62/HU9yu Nu3vYw1UrujpIejwJ9IfT9mLYaRpz9ciGYJ4q6HNNs3Zj/CxMPjet1FQFpT88GAcFGX4 yVHVXmQon5Dq9Gw9HQrqPVHOHBmTcQtlPEEbcUGjQi/K/OHY1CAXMb3wDOnxgdFEsLhh cfBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VDigh3LB3s6a/Rl+FCKzmXQVkFODGqoxKbWHFAog88M=; b=rBRo2le9N37XceliYEn19XUBWtsU7zjsTQ094713cslQYjqMPq7RegQosrJJjbPV8C w9klw9wKWP6xYh9pW/2j8sa9BP0u4zALJ1AvFdUUT9Xaxlh6NE9cHqRDTMYHi8UAFwc/ 6f9fdEZiUSFDOLO39FdMc87zeO+2mgUGLi9tn/g8/Fnnw8jCzGLQjK7v2BjhaPKNoRq6 Kf542Arrwtvgg1gFPNMVvj5mmJQtxAjeLgrhNlddMOqgiKKKSvGOJaTVtWh79NTZTF68 cjfpZMJ1l6+lqeRWPod356CUBN8VMTXnINVPzurzoj1Pe8opodXjjUQEXnBoSC/gyWSl lRrw== X-Gm-Message-State: AO0yUKXMyC2gq3o6zGw0Sta/j4bYTon2uqniluGFAOKd0doJByCPjN0L 8wREJpLY/2XUo3+1XzJ5BeufXslXKzGcF/ij4ac= X-Google-Smtp-Source: AK7set/8bvVMG7CwaT0P9noKJXvh56blwjvM4CgGuRcsxG+SOHpECb3Vx9oVlYiueeAcDHQnSMPnlQ== X-Received: by 2002:a17:902:d709:b0:19c:d78b:cdc with SMTP id w9-20020a170902d70900b0019cd78b0cdcmr8499032ply.5.1677475565584; Sun, 26 Feb 2023 21:26:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 20/76] target/avr: Drop tcg_temp_free Date: Sun, 26 Feb 2023 19:24:09 -1000 Message-Id: <20230227052505.352889-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476478131100009 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/avr/translate.c | 228 ----------------------------------------- 1 file changed, 228 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index 4f8112c3e6..b9506a8d86 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -221,10 +221,6 @@ static void gen_add_CHf(TCGv R, TCGv Rd, TCGv Rr) tcg_gen_shri_tl(cpu_Cf, t1, 7); /* Cf =3D t1(7) */ tcg_gen_shri_tl(cpu_Hf, t1, 3); /* Hf =3D t1(3) */ tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1); - - tcg_temp_free_i32(t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t1); } =20 static void gen_add_Vf(TCGv R, TCGv Rd, TCGv Rr) @@ -239,9 +235,6 @@ static void gen_add_Vf(TCGv R, TCGv Rd, TCGv Rr) tcg_gen_andc_tl(t1, t1, t2); =20 tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf =3D t1(7) */ - - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t1); } =20 static void gen_sub_CHf(TCGv R, TCGv Rd, TCGv Rr) @@ -259,10 +252,6 @@ static void gen_sub_CHf(TCGv R, TCGv Rd, TCGv Rr) tcg_gen_shri_tl(cpu_Cf, t2, 7); /* Cf =3D t2(7) */ tcg_gen_shri_tl(cpu_Hf, t2, 3); /* Hf =3D t2(3) */ tcg_gen_andi_tl(cpu_Hf, cpu_Hf, 1); - - tcg_temp_free_i32(t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t1); } =20 static void gen_sub_Vf(TCGv R, TCGv Rd, TCGv Rr) @@ -277,9 +266,6 @@ static void gen_sub_Vf(TCGv R, TCGv Rd, TCGv Rr) tcg_gen_and_tl(t1, t1, t2); =20 tcg_gen_shri_tl(cpu_Vf, t1, 7); /* Vf =3D t1(7) */ - - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t1); } =20 static void gen_NSf(TCGv R) @@ -317,9 +303,6 @@ static bool trans_ADD(DisasContext *ctx, arg_ADD *a) =20 /* update output registers */ tcg_gen_mov_tl(Rd, R); - - tcg_temp_free_i32(R); - return true; } =20 @@ -344,9 +327,6 @@ static bool trans_ADC(DisasContext *ctx, arg_ADC *a) =20 /* update output registers */ tcg_gen_mov_tl(Rd, R); - - tcg_temp_free_i32(R); - return true; } =20 @@ -385,10 +365,6 @@ static bool trans_ADIW(DisasContext *ctx, arg_ADIW *a) /* update output registers */ tcg_gen_andi_tl(RdL, R, 0xff); tcg_gen_shri_tl(RdH, R, 8); - - tcg_temp_free_i32(Rd); - tcg_temp_free_i32(R); - return true; } =20 @@ -413,9 +389,6 @@ static bool trans_SUB(DisasContext *ctx, arg_SUB *a) =20 /* update output registers */ tcg_gen_mov_tl(Rd, R); - - tcg_temp_free_i32(R); - return true; } =20 @@ -440,10 +413,6 @@ static bool trans_SUBI(DisasContext *ctx, arg_SUBI *a) =20 /* update output registers */ tcg_gen_mov_tl(Rd, R); - - tcg_temp_free_i32(R); - tcg_temp_free_i32(Rr); - return true; } =20 @@ -475,10 +444,6 @@ static bool trans_SBC(DisasContext *ctx, arg_SBC *a) =20 /* update output registers */ tcg_gen_mov_tl(Rd, R); - - tcg_temp_free_i32(zero); - tcg_temp_free_i32(R); - return true; } =20 @@ -509,11 +474,6 @@ static bool trans_SBCI(DisasContext *ctx, arg_SBCI *a) =20 /* update output registers */ tcg_gen_mov_tl(Rd, R); - - tcg_temp_free_i32(zero); - tcg_temp_free_i32(R); - tcg_temp_free_i32(Rr); - return true; } =20 @@ -552,10 +512,6 @@ static bool trans_SBIW(DisasContext *ctx, arg_SBIW *a) /* update output registers */ tcg_gen_andi_tl(RdL, R, 0xff); tcg_gen_shri_tl(RdH, R, 8); - - tcg_temp_free_i32(Rd); - tcg_temp_free_i32(R); - return true; } =20 @@ -578,9 +534,6 @@ static bool trans_AND(DisasContext *ctx, arg_AND *a) =20 /* update output registers */ tcg_gen_mov_tl(Rd, R); - - tcg_temp_free_i32(R); - return true; } =20 @@ -620,9 +573,6 @@ static bool trans_OR(DisasContext *ctx, arg_OR *a) =20 /* update output registers */ tcg_gen_mov_tl(Rd, R); - - tcg_temp_free_i32(R); - return true; } =20 @@ -700,10 +650,6 @@ static bool trans_NEG(DisasContext *ctx, arg_NEG *a) =20 /* update output registers */ tcg_gen_mov_tl(Rd, R); - - tcg_temp_free_i32(t0); - tcg_temp_free_i32(R); - return true; } =20 @@ -773,9 +719,6 @@ static bool trans_MUL(DisasContext *ctx, arg_MUL *a) /* update status register */ tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf =3D R(15) */ tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf =3D R =3D=3D 0 */ - - tcg_temp_free_i32(R); - return true; } =20 @@ -806,11 +749,6 @@ static bool trans_MULS(DisasContext *ctx, arg_MULS *a) /* update status register */ tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf =3D R(15) */ tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf =3D R =3D=3D 0 */ - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(R); - return true; } =20 @@ -840,10 +778,6 @@ static bool trans_MULSU(DisasContext *ctx, arg_MULSU *= a) /* update status register */ tcg_gen_shri_tl(cpu_Cf, R, 15); /* Cf =3D R(15) */ tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_Zf, R, 0); /* Zf =3D R =3D=3D 0 */ - - tcg_temp_free_i32(t0); - tcg_temp_free_i32(R); - return true; } =20 @@ -874,10 +808,6 @@ static bool trans_FMUL(DisasContext *ctx, arg_FMUL *a) tcg_gen_andi_tl(R0, R, 0xff); tcg_gen_shri_tl(R1, R, 8); tcg_gen_andi_tl(R1, R1, 0xff); - - - tcg_temp_free_i32(R); - return true; } =20 @@ -913,11 +843,6 @@ static bool trans_FMULS(DisasContext *ctx, arg_FMULS *= a) tcg_gen_andi_tl(R0, R, 0xff); tcg_gen_shri_tl(R1, R, 8); tcg_gen_andi_tl(R1, R1, 0xff); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(R); - return true; } =20 @@ -951,10 +876,6 @@ static bool trans_FMULSU(DisasContext *ctx, arg_FMULSU= *a) tcg_gen_andi_tl(R0, R, 0xff); tcg_gen_shri_tl(R1, R, 8); tcg_gen_andi_tl(R1, R1, 0xff); - - tcg_temp_free_i32(t0); - tcg_temp_free_i32(R); - return true; } =20 @@ -1009,25 +930,17 @@ static void gen_jmp_z(DisasContext *ctx) static void gen_push_ret(DisasContext *ctx, int ret) { if (avr_feature(ctx->env, AVR_FEATURE_1_BYTE_PC)) { - TCGv t0 =3D tcg_const_i32((ret & 0x0000ff)); =20 tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB); tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); - - tcg_temp_free_i32(t0); } else if (avr_feature(ctx->env, AVR_FEATURE_2_BYTE_PC)) { - TCGv t0 =3D tcg_const_i32((ret & 0x00ffff)); =20 tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW); tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); - - tcg_temp_free_i32(t0); - } else if (avr_feature(ctx->env, AVR_FEATURE_3_BYTE_PC)) { - TCGv lo =3D tcg_const_i32((ret & 0x0000ff)); TCGv hi =3D tcg_const_i32((ret & 0xffff00) >> 8); =20 @@ -1035,9 +948,6 @@ static void gen_push_ret(DisasContext *ctx, int ret) tcg_gen_subi_tl(cpu_sp, cpu_sp, 2); tcg_gen_qemu_st_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW); tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); - - tcg_temp_free_i32(lo); - tcg_temp_free_i32(hi); } } =20 @@ -1061,9 +971,6 @@ static void gen_pop_ret(DisasContext *ctx, TCGv ret) tcg_gen_qemu_ld_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB); =20 tcg_gen_deposit_tl(ret, lo, hi, 8, 16); - - tcg_temp_free_i32(lo); - tcg_temp_free_i32(hi); } } =20 @@ -1291,9 +1198,6 @@ static bool trans_CP(DisasContext *ctx, arg_CP *a) gen_sub_CHf(R, Rd, Rr); gen_sub_Vf(R, Rd, Rr); gen_ZNSf(R); - - tcg_temp_free_i32(R); - return true; } =20 @@ -1322,10 +1226,6 @@ static bool trans_CPC(DisasContext *ctx, arg_CPC *a) * cleared otherwise. */ tcg_gen_movcond_tl(TCG_COND_EQ, cpu_Zf, R, zero, cpu_Zf, zero); - - tcg_temp_free_i32(zero); - tcg_temp_free_i32(R); - return true; } =20 @@ -1348,10 +1248,6 @@ static bool trans_CPI(DisasContext *ctx, arg_CPI *a) gen_sub_CHf(R, Rd, Rr); gen_sub_Vf(R, Rd, Rr); gen_ZNSf(R); - - tcg_temp_free_i32(R); - tcg_temp_free_i32(Rr); - return true; } =20 @@ -1683,9 +1579,6 @@ static bool trans_LDS(DisasContext *ctx, arg_LDS *a) tcg_gen_ori_tl(addr, addr, a->imm); =20 gen_data_load(ctx, Rd, addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -1720,9 +1613,6 @@ static bool trans_LDX1(DisasContext *ctx, arg_LDX1 *a) TCGv addr =3D gen_get_xaddr(); =20 gen_data_load(ctx, Rd, addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -1735,9 +1625,6 @@ static bool trans_LDX2(DisasContext *ctx, arg_LDX2 *a) tcg_gen_addi_tl(addr, addr, 1); /* addr =3D addr + 1 */ =20 gen_set_xaddr(addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -1749,9 +1636,6 @@ static bool trans_LDX3(DisasContext *ctx, arg_LDX3 *a) tcg_gen_subi_tl(addr, addr, 1); /* addr =3D addr - 1 */ gen_data_load(ctx, Rd, addr); gen_set_xaddr(addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -1789,9 +1673,6 @@ static bool trans_LDY2(DisasContext *ctx, arg_LDY2 *a) tcg_gen_addi_tl(addr, addr, 1); /* addr =3D addr + 1 */ =20 gen_set_yaddr(addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -1803,9 +1684,6 @@ static bool trans_LDY3(DisasContext *ctx, arg_LDY3 *a) tcg_gen_subi_tl(addr, addr, 1); /* addr =3D addr - 1 */ gen_data_load(ctx, Rd, addr); gen_set_yaddr(addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -1816,9 +1694,6 @@ static bool trans_LDDY(DisasContext *ctx, arg_LDDY *a) =20 tcg_gen_addi_tl(addr, addr, a->imm); /* addr =3D addr + q */ gen_data_load(ctx, Rd, addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -1860,9 +1735,6 @@ static bool trans_LDZ2(DisasContext *ctx, arg_LDZ2 *a) tcg_gen_addi_tl(addr, addr, 1); /* addr =3D addr + 1 */ =20 gen_set_zaddr(addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -1875,9 +1747,6 @@ static bool trans_LDZ3(DisasContext *ctx, arg_LDZ3 *a) gen_data_load(ctx, Rd, addr); =20 gen_set_zaddr(addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -1888,9 +1757,6 @@ static bool trans_LDDZ(DisasContext *ctx, arg_LDDZ *a) =20 tcg_gen_addi_tl(addr, addr, a->imm); /* addr =3D addr + q */ gen_data_load(ctx, Rd, addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -1917,9 +1783,6 @@ static bool trans_STS(DisasContext *ctx, arg_STS *a) tcg_gen_shli_tl(addr, addr, 16); tcg_gen_ori_tl(addr, addr, a->imm); gen_data_store(ctx, Rd, addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -1950,9 +1813,6 @@ static bool trans_STX1(DisasContext *ctx, arg_STX1 *a) TCGv addr =3D gen_get_xaddr(); =20 gen_data_store(ctx, Rd, addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -1964,9 +1824,6 @@ static bool trans_STX2(DisasContext *ctx, arg_STX2 *a) gen_data_store(ctx, Rd, addr); tcg_gen_addi_tl(addr, addr, 1); /* addr =3D addr + 1 */ gen_set_xaddr(addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -1978,9 +1835,6 @@ static bool trans_STX3(DisasContext *ctx, arg_STX3 *a) tcg_gen_subi_tl(addr, addr, 1); /* addr =3D addr - 1 */ gen_data_store(ctx, Rd, addr); gen_set_xaddr(addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -2015,9 +1869,6 @@ static bool trans_STY2(DisasContext *ctx, arg_STY2 *a) gen_data_store(ctx, Rd, addr); tcg_gen_addi_tl(addr, addr, 1); /* addr =3D addr + 1 */ gen_set_yaddr(addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -2029,9 +1880,6 @@ static bool trans_STY3(DisasContext *ctx, arg_STY3 *a) tcg_gen_subi_tl(addr, addr, 1); /* addr =3D addr - 1 */ gen_data_store(ctx, Rd, addr); gen_set_yaddr(addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -2042,9 +1890,6 @@ static bool trans_STDY(DisasContext *ctx, arg_STDY *a) =20 tcg_gen_addi_tl(addr, addr, a->imm); /* addr =3D addr + q */ gen_data_store(ctx, Rd, addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -2080,9 +1925,6 @@ static bool trans_STZ2(DisasContext *ctx, arg_STZ2 *a) tcg_gen_addi_tl(addr, addr, 1); /* addr =3D addr + 1 */ =20 gen_set_zaddr(addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -2095,9 +1937,6 @@ static bool trans_STZ3(DisasContext *ctx, arg_STZ3 *a) gen_data_store(ctx, Rd, addr); =20 gen_set_zaddr(addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -2108,9 +1947,6 @@ static bool trans_STDZ(DisasContext *ctx, arg_STDZ *a) =20 tcg_gen_addi_tl(addr, addr, a->imm); /* addr =3D addr + q */ gen_data_store(ctx, Rd, addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -2142,9 +1978,6 @@ static bool trans_LPM1(DisasContext *ctx, arg_LPM1 *a) tcg_gen_shli_tl(addr, H, 8); /* addr =3D H:L */ tcg_gen_or_tl(addr, addr, L); tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd =3D mem[addr] */ - - tcg_temp_free_i32(addr); - return true; } =20 @@ -2162,9 +1995,6 @@ static bool trans_LPM2(DisasContext *ctx, arg_LPM2 *a) tcg_gen_shli_tl(addr, H, 8); /* addr =3D H:L */ tcg_gen_or_tl(addr, addr, L); tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd =3D mem[addr] */ - - tcg_temp_free_i32(addr); - return true; } =20 @@ -2186,9 +2016,6 @@ static bool trans_LPMX(DisasContext *ctx, arg_LPMX *a) tcg_gen_andi_tl(L, addr, 0xff); tcg_gen_shri_tl(addr, addr, 8); tcg_gen_andi_tl(H, addr, 0xff); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -2217,9 +2044,6 @@ static bool trans_ELPM1(DisasContext *ctx, arg_ELPM1 = *a) TCGv addr =3D gen_get_zaddr(); =20 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd =3D mem[addr] */ - - tcg_temp_free_i32(addr); - return true; } =20 @@ -2233,9 +2057,6 @@ static bool trans_ELPM2(DisasContext *ctx, arg_ELPM2 = *a) TCGv addr =3D gen_get_zaddr(); =20 tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd =3D mem[addr] */ - - tcg_temp_free_i32(addr); - return true; } =20 @@ -2251,9 +2072,6 @@ static bool trans_ELPMX(DisasContext *ctx, arg_ELPMX = *a) tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd =3D mem[addr] */ tcg_gen_addi_tl(addr, addr, 1); /* addr =3D addr + 1 */ gen_set_zaddr(addr); - - tcg_temp_free_i32(addr); - return true; } =20 @@ -2307,9 +2125,6 @@ static bool trans_IN(DisasContext *ctx, arg_IN *a) TCGv port =3D tcg_const_i32(a->imm); =20 gen_helper_inb(Rd, cpu_env, port); - - tcg_temp_free_i32(port); - return true; } =20 @@ -2323,9 +2138,6 @@ static bool trans_OUT(DisasContext *ctx, arg_OUT *a) TCGv port =3D tcg_const_i32(a->imm); =20 gen_helper_outb(cpu_env, port, Rd); - - tcg_temp_free_i32(port); - return true; } =20 @@ -2393,10 +2205,6 @@ static bool trans_XCH(DisasContext *ctx, arg_XCH *a) gen_data_load(ctx, t0, addr); gen_data_store(ctx, Rd, addr); tcg_gen_mov_tl(Rd, t0); - - tcg_temp_free_i32(t0); - tcg_temp_free_i32(addr); - return true; } =20 @@ -2426,11 +2234,6 @@ static bool trans_LAS(DisasContext *ctx, arg_LAS *a) tcg_gen_or_tl(t1, t0, Rr); tcg_gen_mov_tl(Rr, t0); /* Rr =3D t0 */ gen_data_store(ctx, t1, addr); /* mem[addr] =3D t1 */ - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(addr); - return true; } =20 @@ -2461,11 +2264,6 @@ static bool trans_LAC(DisasContext *ctx, arg_LAC *a) tcg_gen_andc_tl(t1, t0, Rr); /* t1 =3D t0 & (0xff - Rr) =3D t0 & ~Rr */ tcg_gen_mov_tl(Rr, t0); /* Rr =3D t0 */ gen_data_store(ctx, t1, addr); /* mem[addr] =3D t1 */ - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(addr); - return true; } =20 @@ -2496,11 +2294,6 @@ static bool trans_LAT(DisasContext *ctx, arg_LAT *a) tcg_gen_xor_tl(t1, t0, Rd); tcg_gen_mov_tl(Rd, t0); /* Rd =3D t0 */ gen_data_store(ctx, t1, addr); /* mem[addr] =3D t1 */ - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(addr); - return true; } =20 @@ -2559,9 +2352,6 @@ static bool trans_ROR(DisasContext *ctx, arg_ROR *a) =20 /* update status register */ gen_rshift_ZNVSf(Rd); - - tcg_temp_free_i32(t0); - return true; } =20 @@ -2586,9 +2376,6 @@ static bool trans_ASR(DisasContext *ctx, arg_ASR *a) =20 /* update status register */ gen_rshift_ZNVSf(Rd); - - tcg_temp_free_i32(t0); - return true; } =20 @@ -2606,10 +2393,6 @@ static bool trans_SWAP(DisasContext *ctx, arg_SWAP *= a) tcg_gen_andi_tl(t1, Rd, 0xf0); tcg_gen_shri_tl(t1, t1, 4); tcg_gen_or_tl(Rd, t0, t1); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t0); - return true; } =20 @@ -2625,10 +2408,6 @@ static bool trans_SBI(DisasContext *ctx, arg_SBI *a) gen_helper_inb(data, cpu_env, port); tcg_gen_ori_tl(data, data, 1 << a->bit); gen_helper_outb(cpu_env, port, data); - - tcg_temp_free_i32(port); - tcg_temp_free_i32(data); - return true; } =20 @@ -2644,10 +2423,6 @@ static bool trans_CBI(DisasContext *ctx, arg_CBI *a) gen_helper_inb(data, cpu_env, port); tcg_gen_andi_tl(data, data, ~(1 << a->bit)); gen_helper_outb(cpu_env, port, data); - - tcg_temp_free_i32(data); - tcg_temp_free_i32(port); - return true; } =20 @@ -2675,9 +2450,6 @@ static bool trans_BLD(DisasContext *ctx, arg_BLD *a) tcg_gen_andi_tl(Rd, Rd, ~(1u << a->bit)); /* clear bit */ tcg_gen_shli_tl(t1, cpu_Tf, a->bit); /* create mask */ tcg_gen_or_tl(Rd, Rd, t1); - - tcg_temp_free_i32(t1); - return true; } =20 --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677476877; cv=none; d=zohomail.com; s=zohoarc; b=aXdO4Ihpu/f2QJD/2AnbG7j2bHxSVnvHnbKvlMUMXWpf2K6y3PMgBtNEw0cN8a4cxAxEKWsjPi+C1x/k/w4ri6rD4n4xmMHXNN83D+rY5vvYkp3bQrrOpcGB0dNcW/4agWTIn4WIXicXc8RewLEtVfJpb48A3bM7wDg+UVHMNT0= ARC-Message-Signature: i=1; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.26.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:26:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TToqxygHAy4B0miglawoSDtyexliIjv3wj5R/FRq4Q4=; b=vLpTW+Z3xIg9Y8wuea4FJMzYg3oHr8RhFVobl3FUCuao6MdWt9CvXZL35xGbZXfRtG XyCRu2XoDYHp6rJveu9zlvRMfRwwZrBGOa6wLHChUDwgAxbsQTBN8nK1yKNnZDU/EUWS uYl6k3B62XQHYc5S/UHiAyc2cvKmOX9R+q6TI1EZmPcrMnE0oRY80QoYGvmSJa/dE7EG U7HaNBblbcPEBK1OxW/Toseu7IKQv7lMFAvbmj4QbxFOVzrMnz2rC3+cOCGL7eJOhHri 9IYRLWibibBZ92i1HOG1fPb6TwL03kjSi+HqLEtlypFBSf+j31PEjHJZ067zYmYPke8k O7eA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TToqxygHAy4B0miglawoSDtyexliIjv3wj5R/FRq4Q4=; b=dhM4O8Y+PpaBBXTaHydiA0UV0USMfA0uvN4sVJ9R1pqbd7Bjy2v60E577M+uTroqpD YF2PXNs+0njfMRDM3Xq9PLeuwgSnY85LVaMamsRuN7CVM6FYZ2YSrlEJ3cj7ghNTHzas 6VfAnYqb6weEsdOgFA7pgTDcQzPuqCkDe9jjqnBM5xux04van2kGgrRnOuvn6x4UKOA9 YWlx/hteNZlbTbKdxsO6trIkWdB5/fY0OXWFpFzbXLHZI4HhKLaHaxArh1MGC4QR1PmC szfn6Zf05FaoDg7Ckg30gZo1yHWjZfSQJzh6fwAh/noBLudbktcKMc3G33dlfLrXRjhy UXWQ== X-Gm-Message-State: AO0yUKVBP4oxOef9uKlvKdNTwoxt3jIgQMGKXMJWuJpGS10MESxisUc1 TPr4D3lWArMr6TqIJ0evqFjUtPzGh2eb5YMAGgM= X-Google-Smtp-Source: AK7set8HaAGUv7NPNvvq/6Vi7id6S4EqUGqOmBbYLkWuh35OChUyCrSJf153WmxiF8KL8oZb/bvfRw== X-Received: by 2002:a17:902:ec8f:b0:19c:171a:d346 with SMTP id x15-20020a170902ec8f00b0019c171ad346mr27849452plg.44.1677475568208; Sun, 26 Feb 2023 21:26:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 21/76] target/cris: Drop cris_alu_free_temps Date: Sun, 26 Feb 2023 19:24:10 -1000 Message-Id: <20230227052505.352889-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476878037100003 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/cris/translate.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/target/cris/translate.c b/target/cris/translate.c index a959b27373..76db745fe2 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -1467,14 +1467,6 @@ static inline void cris_alu_alloc_temps(DisasContext= *dc, int size, TCGv *t) } } =20 -static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t) -{ - if (size !=3D 4) { - tcg_temp_free(t[0]); - tcg_temp_free(t[1]); - } -} - static int dec_and_r(CPUCRISState *env, DisasContext *dc) { TCGv t[2]; @@ -1488,7 +1480,6 @@ static int dec_and_r(CPUCRISState *env, DisasContext = *dc) cris_alu_alloc_temps(dc, size, t); dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size); - cris_alu_free_temps(dc, size, t); return 2; } =20 @@ -1518,7 +1509,6 @@ static int dec_lsl_r(CPUCRISState *env, DisasContext = *dc) dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); tcg_gen_andi_tl(t[1], t[1], 63); cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size); - cris_alu_free_temps(dc, size, t); return 2; } =20 @@ -1535,7 +1525,6 @@ static int dec_lsr_r(CPUCRISState *env, DisasContext = *dc) dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); tcg_gen_andi_tl(t[1], t[1], 63); cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size); - cris_alu_free_temps(dc, size, t); return 2; } =20 @@ -1552,7 +1541,6 @@ static int dec_asr_r(CPUCRISState *env, DisasContext = *dc) dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]); tcg_gen_andi_tl(t[1], t[1], 63); cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size); - cris_alu_free_temps(dc, size, t); return 2; } =20 @@ -1568,7 +1556,6 @@ static int dec_muls_r(CPUCRISState *env, DisasContext= *dc) dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]); =20 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4); - cris_alu_free_temps(dc, size, t); return 2; } =20 @@ -1584,7 +1571,6 @@ static int dec_mulu_r(CPUCRISState *env, DisasContext= *dc) dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); =20 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4); - cris_alu_free_temps(dc, size, t); return 2; } =20 @@ -1610,7 +1596,6 @@ static int dec_xor_r(CPUCRISState *env, DisasContext = *dc) dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); =20 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4); - cris_alu_free_temps(dc, size, t); return 2; } =20 @@ -1639,7 +1624,6 @@ static int dec_cmp_r(CPUCRISState *env, DisasContext = *dc) dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); =20 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size); - cris_alu_free_temps(dc, size, t); return 2; } =20 @@ -1666,7 +1650,6 @@ static int dec_add_r(CPUCRISState *env, DisasContext = *dc) dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); =20 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size); - cris_alu_free_temps(dc, size, t); return 2; } =20 @@ -1755,7 +1738,6 @@ static int dec_or_r(CPUCRISState *env, DisasContext *= dc) cris_alu_alloc_temps(dc, size, t); dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size); - cris_alu_free_temps(dc, size, t); return 2; } =20 @@ -1796,7 +1778,6 @@ static int dec_neg_r(CPUCRISState *env, DisasContext = *dc) dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); =20 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size); - cris_alu_free_temps(dc, size, t); return 2; } =20 @@ -1825,7 +1806,6 @@ static int dec_sub_r(CPUCRISState *env, DisasContext = *dc) cris_alu_alloc_temps(dc, size, t); dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size); - cris_alu_free_temps(dc, size, t); return 2; } =20 --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.26.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:26:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LUdQc0vOWU2ksX0RP7JNSAL2uqNTzPqxOne2f4ZPS34=; b=DABoIIBjeLCSWX9fNpvYc9qNBud2YuoAWQDZDiWduAFTnM/ZVQHWEKyMAsdYHPgOZm WYH9VVE86nARsQz3jmcu18/G8RmwKHt1WNK5/GVFzYNK7i6Z+OpJw6EsYY751SinJwwZ odhhfmdWzM+dm7Om0LgErwBIEbfU1fa/NEyUx1M442sA8ybg59wO2TFqhX/UA9Y4U38a 3VZErgUKnNMjJl8G7Cm6dHvrSE2zu1I8zavR5MV3jiKW2/AI31JEVRc3UjzjOTjLbFIx Zxpmz/JZf5/FUGT49WTsRKK0gjGSYcc4VZUpAkhD1QFyc5WM6Bi58Q+JvSj8s8o6hZwT BODQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LUdQc0vOWU2ksX0RP7JNSAL2uqNTzPqxOne2f4ZPS34=; b=LqkzTv7t8c3fVJ59YVijG2KBtX7YsQ7grF+Hg9ICKpbh2iTZdkckAtaTy2xzr6v4yV 5YRtRfsaYxRJA86gQBh918U/7ambwZueSUQ1vqwADl7sk3u6c/YBThxQsu0Ma9noYG9f s4paLFqy6X4WVhXNIMtkkTSgsKj1QcO3LZDNotSMpH/RRVXgchN7N1upHHD902HCNLea aMC7BMifVQ+oMmzhCD6hYt9WqxORyz8KaVMPFWx5xkME/uuWvn3pyTPMXvE1ctIwnVKi drMpTlclRLNxjEZMAEhqEHPo1a8C+zKeg+kxyRXNNWaJOkZoWO/CEMO2lIhFUwf/AA4N pQdA== X-Gm-Message-State: AO0yUKUEvd+f8owXLZpsbGrdTUPGp0SF2iweQZafe9yU20WEOE7RKzoK 0TvMmZjQhGBhdkPeeAMJHZImNU6k1+hun94VDKs= X-Google-Smtp-Source: AK7set9dRRiuDvKK4eWySxtMxmoRw/RRzPlMLAB3jiLJiW+qG+T3MNFS5JqeAtCpVAX9ZVNRUKaOzQ== X-Received: by 2002:a17:903:74d:b0:19c:d550:8cd4 with SMTP id kl13-20020a170903074d00b0019cd5508cd4mr8911733plb.7.1677475570866; Sun, 26 Feb 2023 21:26:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 22/76] target/cris: Drop cris_alu_m_free_temps Date: Sun, 26 Feb 2023 19:24:11 -1000 Message-Id: <20230227052505.352889-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476204931100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/cris/translate.c | 23 ----------------------- target/cris/translate_v10.c.inc | 4 ---- 2 files changed, 27 deletions(-) diff --git a/target/cris/translate.c b/target/cris/translate.c index 76db745fe2..439af701e6 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -2101,12 +2101,6 @@ static inline void cris_alu_m_alloc_temps(TCGv *t) t[1] =3D tcg_temp_new(); } =20 -static inline void cris_alu_m_free_temps(TCGv *t) -{ - tcg_temp_free(t[0]); - tcg_temp_free(t[1]); -} - static int dec_movs_m(CPUCRISState *env, DisasContext *dc) { TCGv t[2]; @@ -2124,7 +2118,6 @@ static int dec_movs_m(CPUCRISState *env, DisasContext= *dc) cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); do_postinc(dc, memsize); - cris_alu_m_free_temps(t); return insn_len; } =20 @@ -2145,7 +2138,6 @@ static int dec_addu_m(CPUCRISState *env, DisasContext= *dc) cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); do_postinc(dc, memsize); - cris_alu_m_free_temps(t); return insn_len; } =20 @@ -2165,7 +2157,6 @@ static int dec_adds_m(CPUCRISState *env, DisasContext= *dc) cris_cc_mask(dc, CC_MASK_NZVC); cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); do_postinc(dc, memsize); - cris_alu_m_free_temps(t); return insn_len; } =20 @@ -2185,7 +2176,6 @@ static int dec_subu_m(CPUCRISState *env, DisasContext= *dc) cris_cc_mask(dc, CC_MASK_NZVC); cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); do_postinc(dc, memsize); - cris_alu_m_free_temps(t); return insn_len; } =20 @@ -2205,7 +2195,6 @@ static int dec_subs_m(CPUCRISState *env, DisasContext= *dc) cris_cc_mask(dc, CC_MASK_NZVC); cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); do_postinc(dc, memsize); - cris_alu_m_free_temps(t); return insn_len; } =20 @@ -2225,7 +2214,6 @@ static int dec_movu_m(CPUCRISState *env, DisasContext= *dc) cris_cc_mask(dc, CC_MASK_NZ); cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); do_postinc(dc, memsize); - cris_alu_m_free_temps(t); return insn_len; } =20 @@ -2244,7 +2232,6 @@ static int dec_cmpu_m(CPUCRISState *env, DisasContext= *dc) cris_cc_mask(dc, CC_MASK_NZVC); cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4); do_postinc(dc, memsize); - cris_alu_m_free_temps(t); return insn_len; } =20 @@ -2265,7 +2252,6 @@ static int dec_cmps_m(CPUCRISState *env, DisasContext= *dc) cpu_R[dc->op2], cpu_R[dc->op2], t[1], memsize_zz(dc)); do_postinc(dc, memsize); - cris_alu_m_free_temps(t); return insn_len; } =20 @@ -2286,7 +2272,6 @@ static int dec_cmp_m(CPUCRISState *env, DisasContext = *dc) cpu_R[dc->op2], cpu_R[dc->op2], t[1], memsize_zz(dc)); do_postinc(dc, memsize); - cris_alu_m_free_temps(t); return insn_len; } =20 @@ -2312,7 +2297,6 @@ static int dec_test_m(CPUCRISState *env, DisasContext= *dc) cpu_R[dc->op2], t[1], c, memsize_zz(dc)); tcg_temp_free(c); do_postinc(dc, memsize); - cris_alu_m_free_temps(t); return insn_len; } =20 @@ -2331,7 +2315,6 @@ static int dec_and_m(CPUCRISState *env, DisasContext = *dc) cris_cc_mask(dc, CC_MASK_NZ); cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc)); do_postinc(dc, memsize); - cris_alu_m_free_temps(t); return insn_len; } =20 @@ -2351,7 +2334,6 @@ static int dec_add_m(CPUCRISState *env, DisasContext = *dc) cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc)); do_postinc(dc, memsize); - cris_alu_m_free_temps(t); return insn_len; } =20 @@ -2370,7 +2352,6 @@ static int dec_addo_m(CPUCRISState *env, DisasContext= *dc) cris_cc_mask(dc, 0); cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4); do_postinc(dc, memsize); - cris_alu_m_free_temps(t); return insn_len; } =20 @@ -2413,7 +2394,6 @@ static int dec_addc_mr(CPUCRISState *env, DisasContex= t *dc) cris_cc_mask(dc, CC_MASK_NZVC); cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4); do_postinc(dc, 4); - cris_alu_m_free_temps(t); return insn_len; } =20 @@ -2432,7 +2412,6 @@ static int dec_sub_m(CPUCRISState *env, DisasContext = *dc) cris_cc_mask(dc, CC_MASK_NZVC); cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize); do_postinc(dc, memsize); - cris_alu_m_free_temps(t); return insn_len; } =20 @@ -2452,7 +2431,6 @@ static int dec_or_m(CPUCRISState *env, DisasContext *= dc) cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc)); do_postinc(dc, memsize); - cris_alu_m_free_temps(t); return insn_len; } =20 @@ -2484,7 +2462,6 @@ static int dec_move_mp(CPUCRISState *env, DisasContex= t *dc) t_gen_mov_preg_TN(dc, dc->op2, t[1]); =20 do_postinc(dc, memsize); - cris_alu_m_free_temps(t); return insn_len; } =20 diff --git a/target/cris/translate_v10.c.inc b/target/cris/translate_v10.c.= inc index 9660f28584..5e9d1c0fe8 100644 --- a/target/cris/translate_v10.c.inc +++ b/target/cris/translate_v10.c.inc @@ -922,9 +922,6 @@ static int dec10_ind_alu(CPUCRISState *env, DisasContex= t *dc, dc->delayed_branch =3D 1; return insn_len; } - - cris_alu_m_free_temps(t); - return insn_len; } =20 @@ -1058,7 +1055,6 @@ static unsigned int dec10_ind(CPUCRISState *env, Disa= sContext *dc) cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst], t[0], c, size); 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.26.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:26:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/xF3Zv42jI/oruaha4e4sWoXABmLVdJQBTLNajb+CF8=; b=X+pP2vR6DKKUY7zIJxV0IG+zHr4jj06M02ffECX3vuC0mTcHEe2cgIixGrKHVjrrc1 bGUaZYz0rdCz035oqhwlOD29cqcJQNFX6Lw0EA2dhduyWqFCL/7tDMytP4WO/cnrEbmR 9i3ATwg1xAyuwDceVVAKXpoOW3zDTnweKJYaXOniWXMA6wJUIQVvW0IepPzgNHOgkopK xDriqG6segjZDhA3FYXTIOHH2mkb8iDkM5oDhxR2RzjNjeOU++xLsQRjxYQyTZYZFOW5 eGdQw0vdpva2uwdg9uzdpO8jiQCUgkyyNpzEogfXlBO4+1ppwCRkfw0asTYcW9vPMzVT YL7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/xF3Zv42jI/oruaha4e4sWoXABmLVdJQBTLNajb+CF8=; b=go02ZTbx2cSBUt6iW8MyRnVtrwcZOjgDpJFSHvowmet8T1/vjtpKDhZAUgqwV/4txf ILzmkmpuAH4Tpfe96h5sTq1fQWCPhDXHdrckoHDr2zYJkUfkRbshbWtJwufvCRW1gRW8 nDnOf0mSLGJo9j7dtakn0SwMa1lAA/+ZIPKvXSdoNExirlUzFupbnrXcf/Jjmk5B1dwF WdkQoVsQTTtmuuFz5rXj3xnhCtcugmYjt30KMbf8fW9SiMIdandx3l2E1Waw2LM2XHc/ 90imD/91HKIUsfncp5nh3f+lXcWwzEa98w0MJYOYuq3KSnJY3BLZykahvBEOIpupxEL+ SVvQ== X-Gm-Message-State: AO0yUKW0N7DT+7YLcZ9k+Pi4uSf7BDPz9RhvXt46NY9rHPT8+nCTqgwJ WdH8vGhwQAx6QczPZ6rwe2KZjoe+SKsUHv0/v58= X-Google-Smtp-Source: AK7set+/92daBnjQjxBJuU5+gl4PwZziYINYQJxL1fmK7kC0r9mPtVgt2AyuzCLpbTEK1JNE/WixCg== X-Received: by 2002:a17:903:1205:b0:19a:b151:bf68 with SMTP id l5-20020a170903120500b0019ab151bf68mr27857055plh.38.1677475573454; Sun, 26 Feb 2023 21:26:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 23/76] target/cris: Drop addr from dec10_ind_move_m_pr Date: Sun, 26 Feb 2023 19:24:12 -1000 Message-Id: <20230227052505.352889-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476343664100001 Content-Type: text/plain; charset="utf-8" This variable is not used, only allocated and freed. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/cris/translate_v10.c.inc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/cris/translate_v10.c.inc b/target/cris/translate_v10.c.= inc index 5e9d1c0fe8..4f03548365 100644 --- a/target/cris/translate_v10.c.inc +++ b/target/cris/translate_v10.c.inc @@ -800,12 +800,11 @@ static unsigned int dec10_ind_move_r_m(DisasContext *= dc, unsigned int size) static unsigned int dec10_ind_move_m_pr(CPUCRISState *env, DisasContext *d= c) { unsigned int insn_len =3D 2, rd =3D dc->dst; - TCGv t, addr; + TCGv t; =20 LOG_DIS("move.%d $p%d, [$r%d]\n", dc->size, dc->dst, dc->src); cris_lock_irq(dc); =20 - addr =3D tcg_temp_new(); t =3D tcg_temp_new(); insn_len +=3D dec10_prep_move_m(env, dc, 0, 4, t); if (rd =3D=3D 15) { @@ -816,7 +815,6 @@ static unsigned int dec10_ind_move_m_pr(CPUCRISState *e= nv, DisasContext *dc) tcg_gen_mov_tl(cpu_PR[rd], t); dc->cpustate_changed =3D 1; } - tcg_temp_free(addr); tcg_temp_free(t); return insn_len; } --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677476223; cv=none; d=zohomail.com; s=zohoarc; b=ZEG2MagU9DUl0TlKrPrCu/KpsAbSeKVUVUO6pIWIoMAVzq3x70Y9jPz6tW6+JK2iBE7ZI08JF2P930/kBjU2vMl0lXboQwADj1n+lxaPC7wZJ9IfSnDAkzLDk7LHU7kKvMhS4h8m4g4kQ8Kz4102sVsM9WLOrQ7MC2y+q9r+ixk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677476223; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QKuhry1+rNBBF3JD8VJFYog29cwlZnnDsNByu0HUpIA=; b=n4CS9xDLDUf2PNxYPZvEb44e9l0LjhO8Y/X+UFW7/JoBcC3ANSORz3FXu2UwSd7bH5Vmtg8lJv1shcQkHZZ1fByjB411A3QEIaCAQa9dzNHlr/deh22zjFFzbxZ6NXpnAxcVSw59FucTqd27wp16sPaCS+MY8IHVBYGAp0g3lhk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167747622332215.675578443621816; Sun, 26 Feb 2023 21:37:03 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW1z-0008OS-8V; Mon, 27 Feb 2023 00:26:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW1n-0007tm-6I for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:26:23 -0500 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW1h-0007fd-Uf for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:26:22 -0500 Received: by mail-pj1-x1042.google.com with SMTP id m8-20020a17090a4d8800b002377bced051so8922468pjh.0 for ; Sun, 26 Feb 2023 21:26:17 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.26.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:26:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QKuhry1+rNBBF3JD8VJFYog29cwlZnnDsNByu0HUpIA=; b=Sayt5Vvx6zx7Ta7PBxd20mk8JxqZxyy4dUaISoD1qQuglrM0paqtx754pipvFQ9b89 C7GR0Pt9NMa66VhqSC6W/vHyFYSVLw5biMaOQPfWxYAA4Sa6FlOqnfOvylQbGA6nlUzv pgJ4NIXsmWbFIDQAy3PO4k/u9ozYUYSYupB89mwHBZmmgM70v0WyHSfrT2H1s4Gci0tB n2gnb+etezILSTkaZhfvVC2/6O5W7G/6cQ7L+TvHqXM5jMzpQwnG415hkL0SoVb0oDtE gFk85IMoA8k/u6/svnRHNnZkBIv5oYLYoT0/t9HuxXHS8OtP5hY3RZTYuWyBIeX5ej61 fr7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QKuhry1+rNBBF3JD8VJFYog29cwlZnnDsNByu0HUpIA=; b=ad2Uokpzk/+O8TmMpJptSuP9DJmcbpa4sgcrVzMmdimdYpoP7KN9YhyNHrXDPd9Y+a oieWeSBeSfyQAaLSWbi2GOS8Y6XdTyOEXhM/pZ7OSM5YhQJmtk3LF+4hf5Roe223K9SR PPkD06GTZfEiSAMyrCYipZKDVBqH7pZuZROHZqoK6jKbQEyNy8xPY3/+zgTmXJbGLAbX 6vqWwBO7V4k6w/LuHM7AIsVoAcYTfhet4JWBXU9T4Yn0p8pk+k9UXMtFN9E7oMMY3ez4 Nb3c+H1GlTE5kjmAS5ave/NHZxi2Ta95FUsk3Xv85BqzCn3cPVHTqZXdFw03dI/P6FBv 72TQ== X-Gm-Message-State: AO0yUKX+9TbN+RHZqo/m+A+fEec4sQbDYAQe942mRU8GE6HjY77eS4Ej MdXbIrLgeA9d29SI+wHDJInnUGM2soT0T2TQYt6Low== X-Google-Smtp-Source: AK7set+/Oq2yaGuidDyze7ObnBT8j/sw9WnTQRX0ikQ1W0GT+sGkCsr5sZIdEivJJJJ+Oh0r/oooiA== X-Received: by 2002:a17:902:dad1:b0:196:5839:b374 with SMTP id q17-20020a170902dad100b001965839b374mr27846291plx.9.1677475576198; Sun, 26 Feb 2023 21:26:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 24/76] target/cris: Drop tcg_temp_free Date: Sun, 26 Feb 2023 19:24:13 -1000 Message-Id: <20230227052505.352889-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476225070100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/cris/translate.c | 70 --------------------------------- target/cris/translate_v10.c.inc | 41 ------------------- 2 files changed, 111 deletions(-) diff --git a/target/cris/translate.c b/target/cris/translate.c index 439af701e6..5172c9b9b2 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -178,7 +178,6 @@ static const int preg_sizes[] =3D { do { \ TCGv tc =3D tcg_const_tl(c); \ t_gen_mov_env_TN(member, tc); \ - tcg_temp_free(tc); \ } while (0) =20 static inline void t_gen_mov_TN_preg(TCGv tn, int r) @@ -271,7 +270,6 @@ static inline void t_gen_raise_exception(uint32_t index) { TCGv_i32 tmp =3D tcg_const_i32(index); gen_helper_raise_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); } =20 static void t_gen_lsl(TCGv d, TCGv a, TCGv b) @@ -286,8 +284,6 @@ static void t_gen_lsl(TCGv d, TCGv a, TCGv b) tcg_gen_sar_tl(t0, t0, t_31); tcg_gen_and_tl(t0, t0, d); tcg_gen_xor_tl(d, d, t0); - tcg_temp_free(t0); - tcg_temp_free(t_31); } =20 static void t_gen_lsr(TCGv d, TCGv a, TCGv b) @@ -303,8 +299,6 @@ static void t_gen_lsr(TCGv d, TCGv a, TCGv b) tcg_gen_sar_tl(t0, t0, t_31); tcg_gen_and_tl(t0, t0, d); tcg_gen_xor_tl(d, d, t0); - tcg_temp_free(t0); - tcg_temp_free(t_31); } =20 static void t_gen_asr(TCGv d, TCGv a, TCGv b) @@ -319,8 +313,6 @@ static void t_gen_asr(TCGv d, TCGv a, TCGv b) tcg_gen_sub_tl(t0, t_31, b); tcg_gen_sar_tl(t0, t0, t_31); tcg_gen_or_tl(d, d, t0); - tcg_temp_free(t0); - tcg_temp_free(t_31); } =20 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b) @@ -335,7 +327,6 @@ static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b) tcg_gen_shli_tl(d, a, 1); tcg_gen_sub_tl(t, d, b); tcg_gen_movcond_tl(TCG_COND_GEU, d, d, b, t, d); - tcg_temp_free(t); } =20 static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs) @@ -353,7 +344,6 @@ static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TC= Gv ccs) tcg_gen_sari_tl(t, t, 31); tcg_gen_and_tl(t, t, b); tcg_gen_add_tl(d, d, t); - tcg_temp_free(t); } =20 /* Extended arithmetics on CRIS. */ @@ -369,7 +359,6 @@ static inline void t_gen_add_flag(TCGv d, int flag) tcg_gen_shri_tl(c, c, flag); } tcg_gen_add_tl(d, d, c); - tcg_temp_free(c); } =20 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d) @@ -381,7 +370,6 @@ static inline void t_gen_addx_carry(DisasContext *dc, T= CGv d) /* C flag is already at bit 0. */ tcg_gen_andi_tl(c, c, C_FLAG); tcg_gen_add_tl(d, d, c); - tcg_temp_free(c); } } =20 @@ -394,7 +382,6 @@ static inline void t_gen_subx_carry(DisasContext *dc, T= CGv d) /* C flag is already at bit 0. */ tcg_gen_andi_tl(c, c, C_FLAG); tcg_gen_sub_tl(d, d, c); - tcg_temp_free(c); } } =20 @@ -414,8 +401,6 @@ static inline void t_gen_swapb(TCGv d, TCGv s) tcg_gen_shri_tl(t, org_s, 8); tcg_gen_andi_tl(t, t, 0x00ff00ff); tcg_gen_or_tl(d, d, t); - tcg_temp_free(t); - tcg_temp_free(org_s); } =20 /* Swap the halfwords of the s operand. */ @@ -428,7 +413,6 @@ static inline void t_gen_swapw(TCGv d, TCGv s) tcg_gen_shli_tl(d, t, 16); tcg_gen_shri_tl(t, t, 16); tcg_gen_or_tl(d, d, t); - tcg_temp_free(t); } =20 /* Reverse the within each byte. @@ -475,8 +459,6 @@ static void t_gen_swapr(TCGv d, TCGv s) tcg_gen_andi_tl(t, t, bitrev[i].mask); tcg_gen_or_tl(d, d, t); } - tcg_temp_free(t); - tcg_temp_free(org_s); } =20 static bool use_goto_tb(DisasContext *dc, target_ulong dest) @@ -778,9 +760,6 @@ static void cris_alu(DisasContext *dc, int op, } tcg_gen_or_tl(d, d, tmp); } - if (tmp !=3D d) { - tcg_temp_free(tmp); - } } =20 static int arith_cc(DisasContext *dc) @@ -919,8 +898,6 @@ static void gen_tst_cc (DisasContext *dc, TCGv cc, int = cond) tcg_gen_shli_tl(cc, tmp, 2); tcg_gen_and_tl(cc, tmp, cc); tcg_gen_andi_tl(cc, cc, Z_FLAG); - - tcg_temp_free(tmp); } break; case CC_GE: @@ -959,9 +936,6 @@ static void gen_tst_cc (DisasContext *dc, TCGv cc, int = cond) tcg_gen_xori_tl(n, n, 2); tcg_gen_and_tl(cc, z, n); tcg_gen_andi_tl(cc, cc, 2); - - tcg_temp_free(n); - tcg_temp_free(z); } break; case CC_LE: @@ -980,9 +954,6 @@ static void gen_tst_cc (DisasContext *dc, TCGv cc, int = cond) tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]); tcg_gen_or_tl(cc, z, n); tcg_gen_andi_tl(cc, cc, 2); - - tcg_temp_free(n); - tcg_temp_free(z); } break; case CC_P: @@ -1282,7 +1253,6 @@ static int dec_addq(CPUCRISState *env, DisasContext *= dc) c =3D tcg_const_tl(dc->op1); cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], c, 4); - tcg_temp_free(c); return 2; } static int dec_moveq(CPUCRISState *env, DisasContext *dc) @@ -1307,7 +1277,6 @@ static int dec_subq(CPUCRISState *env, DisasContext *= dc) c =3D tcg_const_tl(dc->op1); cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], c, 4); - tcg_temp_free(c); return 2; } static int dec_cmpq(CPUCRISState *env, DisasContext *dc) @@ -1323,7 +1292,6 @@ static int dec_cmpq(CPUCRISState *env, DisasContext *= dc) c =3D tcg_const_tl(imm); cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], c, 4); - tcg_temp_free(c); return 2; } static int dec_andq(CPUCRISState *env, DisasContext *dc) @@ -1339,7 +1307,6 @@ static int dec_andq(CPUCRISState *env, DisasContext *= dc) c =3D tcg_const_tl(imm); cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], cpu_R[dc->op2], c, 4); - tcg_temp_free(c); return 2; } static int dec_orq(CPUCRISState *env, DisasContext *dc) @@ -1354,7 +1321,6 @@ static int dec_orq(CPUCRISState *env, DisasContext *d= c) c =3D tcg_const_tl(imm); cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], cpu_R[dc->op2], c, 4); - tcg_temp_free(c); return 2; } static int dec_btstq(CPUCRISState *env, DisasContext *dc) @@ -1368,7 +1334,6 @@ static int dec_btstq(CPUCRISState *env, DisasContext = *dc) cris_evaluate_flags(dc); gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2], c, cpu_PR[PR_CCS]); - tcg_temp_free(c); cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4); cris_update_cc_op(dc, CC_OP_FLAGS, 4); @@ -1437,7 +1402,6 @@ static int dec_move_r(CPUCRISState *env, DisasContext= *dc) cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, size); - tcg_temp_free(t0); } return 2; } @@ -1492,7 +1456,6 @@ static int dec_lz_r(CPUCRISState *env, DisasContext *= dc) t0 =3D tcg_temp_new(); dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0); cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); - tcg_temp_free(t0); return 2; } =20 @@ -1609,7 +1572,6 @@ static int dec_bound_r(CPUCRISState *env, DisasContex= t *dc) l0 =3D tcg_temp_new(); dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0); cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4); - tcg_temp_free(l0); return 2; } =20 @@ -1724,7 +1686,6 @@ static int dec_swap_r(CPUCRISState *env, DisasContext= *dc) t_gen_swapr(t0, t0); } cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op1], cpu_R[dc->op1], t0, 4); - tcg_temp_free(t0); return 2; } =20 @@ -1750,7 +1711,6 @@ static int dec_addi_r(CPUCRISState *env, DisasContext= *dc) t0 =3D tcg_temp_new(); tcg_gen_shli_tl(t0, cpu_R[dc->op2], dc->zzsize); tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0); - tcg_temp_free(t0); return 2; } =20 @@ -1763,7 +1723,6 @@ static int dec_addi_acr(CPUCRISState *env, DisasConte= xt *dc) t0 =3D tcg_temp_new(); tcg_gen_shli_tl(t0, cpu_R[dc->op2], dc->zzsize); tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0); - tcg_temp_free(t0); return 2; } =20 @@ -1822,7 +1781,6 @@ static int dec_movu_r(CPUCRISState *env, DisasContext= *dc) t0 =3D tcg_temp_new(); dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0); cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); - tcg_temp_free(t0); return 2; } =20 @@ -1841,7 +1799,6 @@ static int dec_movs_r(CPUCRISState *env, DisasContext= *dc) t_gen_sext(t0, cpu_R[dc->op1], size); cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op1], t0, 4); - tcg_temp_free(t0); return 2; } =20 @@ -1859,7 +1816,6 @@ static int dec_addu_r(CPUCRISState *env, DisasContext= *dc) /* Size can only be qi or hi. */ t_gen_zext(t0, cpu_R[dc->op1], size); cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); - tcg_temp_free(t0); return 2; } =20 @@ -1878,7 +1834,6 @@ static int dec_adds_r(CPUCRISState *env, DisasContext= *dc) t_gen_sext(t0, cpu_R[dc->op1], size); cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); - tcg_temp_free(t0); return 2; } =20 @@ -1897,7 +1852,6 @@ static int dec_subu_r(CPUCRISState *env, DisasContext= *dc) t_gen_zext(t0, cpu_R[dc->op1], size); cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); - tcg_temp_free(t0); return 2; } =20 @@ -1916,7 +1870,6 @@ static int dec_subs_r(CPUCRISState *env, DisasContext= *dc) t_gen_sext(t0, cpu_R[dc->op1], size); cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4); - tcg_temp_free(t0); return 2; } =20 @@ -1996,8 +1949,6 @@ static int dec_move_rs(CPUCRISState *env, DisasContex= t *dc) c2 =3D tcg_const_tl(dc->op2); cris_cc_mask(dc, 0); gen_helper_movl_sreg_reg(cpu_env, c2, c1); - tcg_temp_free(c1); - tcg_temp_free(c2); return 2; } static int dec_move_sr(CPUCRISState *env, DisasContext *dc) @@ -2008,8 +1959,6 @@ static int dec_move_sr(CPUCRISState *env, DisasContex= t *dc) c2 =3D tcg_const_tl(dc->op2); cris_cc_mask(dc, 0); gen_helper_movl_reg_sreg(cpu_env, c1, c2); - tcg_temp_free(c1); - tcg_temp_free(c2); return 2; } =20 @@ -2029,7 +1978,6 @@ static int dec_move_rp(CPUCRISState *env, DisasContex= t *dc) tcg_gen_andi_tl(t[0], t[0], 0x39f); tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f); tcg_gen_or_tl(t[0], t[1], t[0]); - tcg_temp_free(t[1]); } } else { tcg_gen_mov_tl(t[0], cpu_R[dc->op1]); @@ -2040,7 +1988,6 @@ static int dec_move_rp(CPUCRISState *env, DisasContex= t *dc) cris_update_cc_op(dc, CC_OP_FLAGS, 4); dc->flags_uptodate =3D 1; } - tcg_temp_free(t[0]); return 2; } static int dec_move_pr(CPUCRISState *env, DisasContext *dc) @@ -2061,7 +2008,6 @@ static int dec_move_pr(CPUCRISState *env, DisasContex= t *dc) cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op1], cpu_R[dc->op1], t0, preg_sizes[dc->op2]); - tcg_temp_free(t0); } return 2; } @@ -2089,7 +2035,6 @@ static int dec_move_mr(CPUCRISState *env, DisasContex= t *dc) cris_cc_mask(dc, CC_MASK_NZ); cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize); - tcg_temp_free(t0); } do_postinc(dc, memsize); return insn_len; @@ -2295,7 +2240,6 @@ static int dec_test_m(CPUCRISState *env, DisasContext= *dc) c =3D tcg_const_tl(0); cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[1], c, memsize_zz(dc)); - tcg_temp_free(c); do_postinc(dc, memsize); return insn_len; } @@ -2371,8 +2315,6 @@ static int dec_bound_m(CPUCRISState *env, DisasContex= t *dc) cris_cc_mask(dc, CC_MASK_NZ); cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4); do_postinc(dc, memsize); - tcg_temp_free(l[0]); - tcg_temp_free(l[1]); return insn_len; } =20 @@ -2484,7 +2426,6 @@ static int dec_move_pm(CPUCRISState *env, DisasContex= t *dc) t_gen_mov_TN_preg(t0, dc->op2); cris_flush_cc_state(dc); gen_store(dc, cpu_R[dc->op1], t0, memsize); - tcg_temp_free(t0); =20 cris_cc_mask(dc, 0); if (dc->postinc) { @@ -2519,17 +2460,14 @@ static int dec_movem_mr(CPUCRISState *env, DisasCon= text *dc) } else { tmp32 =3D NULL; } - tcg_temp_free(addr); =20 for (i =3D 0; i < (nr >> 1); i++) { tcg_gen_extrl_i64_i32(cpu_R[i * 2], tmp[i]); tcg_gen_shri_i64(tmp[i], tmp[i], 32); tcg_gen_extrl_i64_i32(cpu_R[i * 2 + 1], tmp[i]); - tcg_temp_free_i64(tmp[i]); } if (nr & 1) { tcg_gen_mov_tl(cpu_R[dc->op2], tmp32); - tcg_temp_free(tmp32); } =20 /* writeback the updated pointer value. */ @@ -2567,8 +2505,6 @@ static int dec_movem_rm(CPUCRISState *env, DisasConte= xt *dc) tcg_gen_mov_tl(cpu_R[dc->op1], addr); } cris_cc_mask(dc, 0); - tcg_temp_free(tmp); - tcg_temp_free(addr); return 2; } =20 @@ -2648,7 +2584,6 @@ static int dec_jas_r(CPUCRISState *env, DisasContext = *dc) } c =3D tcg_const_tl(dc->pc + 4); t_gen_mov_preg_TN(dc, dc->op2, c); - tcg_temp_free(c); =20 cris_prepare_jmp(dc, JMP_INDIRECT); return 2; @@ -2666,7 +2601,6 @@ static int dec_jas_im(CPUCRISState *env, DisasContext= *dc) c =3D tcg_const_tl(dc->pc + 8); /* Store the return address in Pd. */ t_gen_mov_preg_TN(dc, dc->op2, c); - tcg_temp_free(c); =20 dc->jmp_pc =3D imm; cris_prepare_jmp(dc, JMP_DIRECT); @@ -2685,7 +2619,6 @@ static int dec_jasc_im(CPUCRISState *env, DisasContex= t *dc) c =3D tcg_const_tl(dc->pc + 8 + 4); /* Store the return address in Pd. */ t_gen_mov_preg_TN(dc, dc->op2, c); - tcg_temp_free(c); =20 dc->jmp_pc =3D imm; cris_prepare_jmp(dc, JMP_DIRECT); @@ -2701,7 +2634,6 @@ static int dec_jasc_r(CPUCRISState *env, DisasContext= *dc) tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]); c =3D tcg_const_tl(dc->pc + 4 + 4); t_gen_mov_preg_TN(dc, dc->op2, c); - tcg_temp_free(c); cris_prepare_jmp(dc, JMP_INDIRECT); return 2; } @@ -2735,7 +2667,6 @@ static int dec_bas_im(CPUCRISState *env, DisasContext= *dc) c =3D tcg_const_tl(dc->pc + 8); /* Store the return address in Pd. */ t_gen_mov_preg_TN(dc, dc->op2, c); - tcg_temp_free(c); =20 dc->jmp_pc =3D dc->pc + simm; cris_prepare_jmp(dc, JMP_DIRECT); @@ -2753,7 +2684,6 @@ static int dec_basc_im(CPUCRISState *env, DisasContex= t *dc) c =3D tcg_const_tl(dc->pc + 12); /* Store the return address in Pd. */ t_gen_mov_preg_TN(dc, dc->op2, c); - tcg_temp_free(c); =20 dc->jmp_pc =3D dc->pc + simm; cris_prepare_jmp(dc, JMP_DIRECT); diff --git a/target/cris/translate_v10.c.inc b/target/cris/translate_v10.c.= inc index 4f03548365..b03b2ef746 100644 --- a/target/cris/translate_v10.c.inc +++ b/target/cris/translate_v10.c.inc @@ -90,9 +90,6 @@ static void gen_store_v10_conditional(DisasContext *dc, T= CGv addr, TCGv val, gen_set_label(l1); tcg_gen_shri_tl(t1, t1, 1); /* shift F to P position */ tcg_gen_or_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], t1); /*P=3DF*/ - tcg_temp_free(t1); - tcg_temp_free(tval); - tcg_temp_free(taddr); } =20 static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val, @@ -215,7 +212,6 @@ static int dec10_prep_move_m(CPUCRISState *env, DisasCo= ntext *dc, else t_gen_zext(dst, dst, memsize); insn_len +=3D crisv10_post_memaddr(dc, memsize); - tcg_temp_free(addr); } =20 if (dc->mode =3D=3D CRISV10_MODE_INDIRECT && (dc->tb_flags & PFIX_FLAG= )) { @@ -258,7 +254,6 @@ static unsigned int dec10_quick_imm(DisasContext *dc) c =3D tcg_const_tl(simm); cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], c, 4); - tcg_temp_free(c); break; case CRISV10_QIMM_CMPQ: LOG_DIS("cmpq %d, $r%d\n", simm, dc->dst); @@ -267,7 +262,6 @@ static unsigned int dec10_quick_imm(DisasContext *dc) c =3D tcg_const_tl(simm); cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst], cpu_R[dc->dst], c, 4); - tcg_temp_free(c); break; case CRISV10_QIMM_ADDQ: LOG_DIS("addq %d, $r%d\n", imm, dc->dst); @@ -276,7 +270,6 @@ static unsigned int dec10_quick_imm(DisasContext *dc) c =3D tcg_const_tl(imm); cris_alu(dc, CC_OP_ADD, cpu_R[dc->dst], cpu_R[dc->dst], c, 4); - tcg_temp_free(c); break; case CRISV10_QIMM_ANDQ: LOG_DIS("andq %d, $r%d\n", simm, dc->dst); @@ -285,7 +278,6 @@ static unsigned int dec10_quick_imm(DisasContext *dc) c =3D tcg_const_tl(simm); cris_alu(dc, CC_OP_AND, cpu_R[dc->dst], cpu_R[dc->dst], c, 4); - tcg_temp_free(c); break; case CRISV10_QIMM_ASHQ: LOG_DIS("ashq %d, $r%d\n", simm, dc->dst); @@ -303,7 +295,6 @@ static unsigned int dec10_quick_imm(DisasContext *dc) gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst], c, cpu_PR[PR_CCS]); } - tcg_temp_free(c); break; case CRISV10_QIMM_LSHQ: LOG_DIS("lshq %d, $r%d\n", simm, dc->dst); @@ -317,7 +308,6 @@ static unsigned int dec10_quick_imm(DisasContext *dc) c =3D tcg_const_tl(imm); cris_alu(dc, op, cpu_R[dc->dst], cpu_R[dc->dst], c, 4); - tcg_temp_free(c); break; case CRISV10_QIMM_SUBQ: LOG_DIS("subq %d, $r%d\n", imm, dc->dst); @@ -326,7 +316,6 @@ static unsigned int dec10_quick_imm(DisasContext *dc) c =3D tcg_const_tl(imm); cris_alu(dc, CC_OP_SUB, cpu_R[dc->dst], cpu_R[dc->dst], c, 4); - tcg_temp_free(c); break; case CRISV10_QIMM_ORQ: LOG_DIS("andq %d, $r%d\n", simm, dc->dst); @@ -335,7 +324,6 @@ static unsigned int dec10_quick_imm(DisasContext *dc) c =3D tcg_const_tl(simm); cris_alu(dc, CC_OP_OR, cpu_R[dc->dst], cpu_R[dc->dst], c, 4); - tcg_temp_free(c); break; =20 case CRISV10_QIMM_BCC_R0: @@ -426,8 +414,6 @@ static void dec10_reg_alu(DisasContext *dc, int op, int= size, int sext) =20 assert(dc->dst !=3D 15); cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], size); - tcg_temp_free(t[0]); - tcg_temp_free(t[1]); } =20 static void dec10_reg_bound(DisasContext *dc, int size) @@ -437,7 +423,6 @@ static void dec10_reg_bound(DisasContext *dc, int size) t =3D tcg_temp_new(); t_gen_zext(t, cpu_R[dc->src], size); cris_alu(dc, CC_OP_BOUND, cpu_R[dc->dst], cpu_R[dc->dst], t, 4); - tcg_temp_free(t); } =20 static void dec10_reg_mul(DisasContext *dc, int size, int sext) @@ -451,9 +436,6 @@ static void dec10_reg_mul(DisasContext *dc, int size, i= nt sext) t[0], t[1], cpu_R[dc->dst], cpu_R[dc->src]); =20 cris_alu(dc, op, cpu_R[dc->dst], t[0], t[1], 4); - - tcg_temp_free(t[0]); - tcg_temp_free(t[1]); } =20 =20 @@ -472,7 +454,6 @@ static void dec10_reg_movs(DisasContext *dc) t_gen_zext(t, cpu_R[dc->src], size); =20 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t, 4); - tcg_temp_free(t); } =20 static void dec10_reg_alux(DisasContext *dc, int op) @@ -490,7 +471,6 @@ static void dec10_reg_alux(DisasContext *dc, int op) t_gen_zext(t, cpu_R[dc->src], size); =20 cris_alu(dc, op, cpu_R[dc->dst], cpu_R[dc->dst], t, 4); - tcg_temp_free(t); } =20 static void dec10_reg_mov_pr(DisasContext *dc) @@ -522,7 +502,6 @@ static void dec10_reg_abs(DisasContext *dc) tcg_gen_sub_tl(t0, cpu_R[dc->dst], t0); =20 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], cpu_R[dc->dst], t0, 4); - tcg_temp_free(t0); } =20 static void dec10_reg_swap(DisasContext *dc) @@ -543,7 +522,6 @@ static void dec10_reg_swap(DisasContext *dc) if (dc->dst & 1) t_gen_swapr(t0, t0); cris_alu(dc, CC_OP_MOVE, cpu_R[dc->src], cpu_R[dc->src], t0, 4); - tcg_temp_free(t0); } =20 static void dec10_reg_scc(DisasContext *dc) @@ -623,7 +601,6 @@ static unsigned int dec10_reg(DisasContext *dc) LOG_DIS("addi r%d r%d size=3D%d\n", dc->src, dc->dst, dc->= size); tcg_gen_shli_tl(t, cpu_R[dc->dst], dc->size & 3); tcg_gen_add_tl(cpu_R[dc->src], cpu_R[dc->src], t); - tcg_temp_free(t); break; case CRISV10_REG_LSL: LOG_DIS("lsl $r%d, $r%d sz=3D%d\n", dc->src, dc->dst, size= ); @@ -669,7 +646,6 @@ static unsigned int dec10_reg(DisasContext *dc) } else { tcg_gen_add_tl(cpu_PR[PR_PREFIX], cpu_R[dc->src], t); } - tcg_temp_free(t); cris_set_prefix(dc); break; =20 @@ -778,7 +754,6 @@ static unsigned int dec10_ind_move_m_r(CPUCRISState *en= v, DisasContext *dc, dc->delayed_branch =3D 1; } =20 - tcg_temp_free(t); return insn_len; } =20 @@ -792,7 +767,6 @@ static unsigned int dec10_ind_move_r_m(DisasContext *dc= , unsigned int size) crisv10_prepare_memaddr(dc, addr, size); gen_store_v10(dc, addr, cpu_R[dc->dst], size); insn_len +=3D crisv10_post_memaddr(dc, size); - tcg_temp_free(addr); =20 return insn_len; } @@ -815,7 +789,6 @@ static unsigned int dec10_ind_move_m_pr(CPUCRISState *e= nv, DisasContext *dc) tcg_gen_mov_tl(cpu_PR[rd], t); dc->cpustate_changed =3D 1; } - tcg_temp_free(t); return insn_len; } =20 @@ -833,12 +806,10 @@ static unsigned int dec10_ind_move_pr_m(DisasContext = *dc) cris_evaluate_flags(dc); tcg_gen_andi_tl(t0, cpu_PR[PR_CCS], ~PFIX_FLAG); gen_store_v10(dc, addr, t0, size); - tcg_temp_free(t0); } else { gen_store_v10(dc, addr, cpu_PR[dc->dst], size); } insn_len +=3D crisv10_post_memaddr(dc, size); - tcg_temp_free(addr); cris_lock_irq(dc); =20 return insn_len; @@ -872,8 +843,6 @@ static void dec10_movem_r_m(DisasContext *dc) if (!pfix && dc->mode =3D=3D CRISV10_MODE_AUTOINC) { tcg_gen_mov_tl(cpu_R[dc->src], addr); } - tcg_temp_free(addr); - tcg_temp_free(t0); } =20 static void dec10_movem_m_r(DisasContext *dc) @@ -900,8 +869,6 @@ static void dec10_movem_m_r(DisasContext *dc) if (!pfix && dc->mode =3D=3D CRISV10_MODE_AUTOINC) { tcg_gen_mov_tl(cpu_R[dc->src], addr); } - tcg_temp_free(addr); - tcg_temp_free(t0); } =20 static int dec10_ind_alu(CPUCRISState *env, DisasContext *dc, @@ -939,7 +906,6 @@ static int dec10_ind_bound(CPUCRISState *env, DisasCont= ext *dc, dc->delayed_branch =3D 1; } =20 - tcg_temp_free(t); return insn_len; } =20 @@ -964,7 +930,6 @@ static int dec10_alux_m(CPUCRISState *env, DisasContext= *dc, int op) dc->delayed_branch =3D 1; } =20 - tcg_temp_free(t); return insn_len; } =20 @@ -1052,7 +1017,6 @@ static unsigned int dec10_ind(CPUCRISState *env, Disa= sContext *dc) c =3D tcg_const_tl(0); cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst], t[0], c, size); - tcg_temp_free(c); break; case CRISV10_IND_ADD: LOG_DIS("add size=3D%d op=3D%d %d\n", size, dc->src, dc->= dst); @@ -1149,7 +1113,6 @@ static unsigned int dec10_ind(CPUCRISState *env, Disa= sContext *dc) =20 c =3D tcg_const_tl(dc->pc + insn_len); t_gen_mov_preg_TN(dc, dc->dst, c); - tcg_temp_free(c); dc->jmp_pc =3D imm; cris_prepare_jmp(dc, JMP_DIRECT); dc->delayed_branch--; /* v10 has no dslot here. */ @@ -1160,7 +1123,6 @@ static unsigned int dec10_ind(CPUCRISState *env, Disa= sContext *dc) tcg_gen_movi_tl(env_pc, dc->pc + 2); c =3D tcg_const_tl(dc->src + 2); t_gen_mov_env_TN(trap_vector, c); - tcg_temp_free(c); t_gen_raise_exception(EXCP_BREAK); dc->base.is_jmp =3D DISAS_NORETURN; return insn_len; @@ -1170,13 +1132,11 @@ static unsigned int dec10_ind(CPUCRISState *env, Di= sasContext *dc) t[0] =3D tcg_temp_new(); c =3D tcg_const_tl(dc->pc + insn_len); t_gen_mov_preg_TN(dc, dc->dst, c); - tcg_temp_free(c); crisv10_prepare_memaddr(dc, t[0], size); gen_load(dc, env_btarget, t[0], 4, 0); insn_len +=3D crisv10_post_memaddr(dc, size); cris_prepare_jmp(dc, JMP_INDIRECT); dc->delayed_branch--; /* v10 has no dslot here. */ - tcg_temp_free(t[0]); } break; =20 @@ -1195,7 +1155,6 @@ static unsigned int dec10_ind(CPUCRISState *env, Disa= sContext *dc) tcg_gen_mov_tl(env_btarget, cpu_R[dc->src]); c =3D tcg_const_tl(dc->pc + insn_len); t_gen_mov_preg_TN(dc, dc->dst, c); - tcg_temp_free(c); cris_prepare_jmp(dc, JMP_INDIRECT); dc->delayed_branch--; /* v10 has no dslot here. */ break; --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.26.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:26:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xvy4wYhYTWxOuE8RedvZQpxyXfOu/63Y7YjVW3K3Dzg=; b=d/wPaGeTVekrJbo2HIW/ikWnJqwJ09hM9BpGXqJESSah415UkqwJEo7sFPp/Ce7A4z gKe2aYFx8lR7ZNz0fCbKrSdp+BL8ikphXPuRDsqb2lAGZZbyzAPaFvH4Ih3l9JhAoSm/ NjlJdV4UEgFScM18npsM4DPeEqAxdDNvPu2eOQfpA7oP432BZTWUEmDUwdsxE4YfxA2E o8LfbDh8qBW0HoK5leNkVgTez0xP+V0TkC34Y0bPTe4QqnO4esvYTTgxdOw6OLYwvhH1 zJIH/fUw+d4Z26OVE4KDK2xXKPmOLDy5DXjsHFEc/t2vZ/VsllDSpQ2l+QQeXp4Ksfkc se0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xvy4wYhYTWxOuE8RedvZQpxyXfOu/63Y7YjVW3K3Dzg=; b=CEi8Rw8gB2r+hKDLBmY+3Aw53U2atAcz5rr5NqC3Bze7CCysVf7Za6ScldJdeQEss7 g8Q0TkdbNYx3YzbY25Va8sZTqRhv26qsTHZqnev4nk/J2ldOk8xXWtHkk+3rCpQ8Xb2a BCXkyYunKc60KkUJ2a07Gg3wArrtclBeCYNejxzpM8Dg4Wy779qlQgQ2WK1y5ypf9SxB ClF8O8OMCy9Tknviti8Pzee+xA1xKUM+kTNSCC955dj37CPNYu8nlFU2BiwQ4ArM75Ey 4kz3ZAttN3imdfMOmiTyepG5im2y4BHuB9PyLDFhBJhelKf6dB89EQ7AUSCJMbQth3Eb +VRA== X-Gm-Message-State: AO0yUKUSbJGFKshWq+RTrYQied0Zt8colZqbFoHPtr/PO/21O5CmVa7C 3PZnD1KQ7VJSCX3C7MBaGjO6meQRjXqR6TBD2lU= X-Google-Smtp-Source: AK7set+Pn8/b5Ol3KVMm0L5xQgUowRzCV/QCaPkxk4sv1YZDNeCVBZF5C90mEc2GNEHNCqTlfQTr8g== X-Received: by 2002:a17:903:2843:b0:19c:d309:4612 with SMTP id kq3-20020a170903284300b0019cd3094612mr9625595plb.6.1677475579003; Sun, 26 Feb 2023 21:26:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 25/76] target/hexagon: Drop tcg_temp_free from C code Date: Sun, 26 Feb 2023 19:24:14 -1000 Message-Id: <20230227052505.352889-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475658041100003 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 29 ------------------ target/hexagon/gen_tcg_hvx.h | 15 ---------- target/hexagon/macros.h | 7 ----- target/hexagon/genptr.c | 58 ------------------------------------ target/hexagon/translate.c | 7 ----- target/hexagon/README | 5 ---- 6 files changed, 121 deletions(-) diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index a219a7f5dd..b2e7880b5c 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -77,7 +77,6 @@ tcg_gen_mov_tl(EA, RxV); \ gen_read_ireg(ireg, MuV, (SHIFT)); \ gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN= ]); \ - tcg_temp_free(ireg); \ } while (0) =20 /* Instructions with multiple definitions */ @@ -116,7 +115,6 @@ gen_read_ireg(ireg, MuV, SHIFT); \ gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN= ]); \ LOAD; \ - tcg_temp_free(ireg); \ } while (0) =20 #define fGEN_TCG_L2_loadrub_pcr(SHORTCODE) \ @@ -168,8 +166,6 @@ for (int i =3D 0; i < 2; i++) { \ gen_set_half(i, RdV, gen_get_byte(byte, i, tmp, (SIGN))); \ } \ - tcg_temp_free(tmp); \ - tcg_temp_free(byte); \ } while (0) =20 #define fGEN_TCG_L2_loadbzw2_io(SHORTCODE) \ @@ -222,8 +218,6 @@ for (int i =3D 0; i < 4; i++) { \ gen_set_half_i64(i, RddV, gen_get_byte(byte, i, tmp, (SIGN)));= \ } \ - tcg_temp_free(tmp); \ - tcg_temp_free(byte); \ } while (0) =20 #define fGEN_TCG_L2_loadbzw4_io(SHORTCODE) \ @@ -273,8 +267,6 @@ tcg_gen_extu_i32_i64(tmp_i64, tmp); \ tcg_gen_shri_i64(RyyV, RyyV, 16); \ tcg_gen_deposit_i64(RyyV, RyyV, tmp_i64, 48, 16); \ - tcg_temp_free(tmp); \ - tcg_temp_free_i64(tmp_i64); \ } while (0) =20 #define fGEN_TCG_L4_loadalignh_ur(SHORTCODE) \ @@ -304,8 +296,6 @@ tcg_gen_extu_i32_i64(tmp_i64, tmp); \ tcg_gen_shri_i64(RyyV, RyyV, 8); \ tcg_gen_deposit_i64(RyyV, RyyV, tmp_i64, 56, 8); \ - tcg_temp_free(tmp); \ - tcg_temp_free_i64(tmp_i64); \ } while (0) =20 #define fGEN_TCG_L2_loadalignb_io(SHORTCODE) \ @@ -347,7 +337,6 @@ tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \ fLOAD(1, SIZE, SIGN, EA, RdV); \ gen_set_label(label); \ - tcg_temp_free(LSB); \ } while (0) =20 #define fGEN_TCG_L2_ploadrubt_pi(SHORTCODE) \ @@ -407,7 +396,6 @@ tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \ fLOAD(1, 8, u, EA, RddV); \ gen_set_label(label); \ - tcg_temp_free(LSB); \ } while (0) =20 #define fGEN_TCG_L2_ploadrdt_pi(SHORTCODE) \ @@ -434,8 +422,6 @@ TCGv HALF =3D tcg_temp_new(); \ TCGv BYTE =3D tcg_temp_new(); \ SHORTCODE; \ - tcg_temp_free(HALF); \ - tcg_temp_free(BYTE); \ } while (0) =20 #define fGEN_TCG_STORE_pcr(SHIFT, STORE) \ @@ -447,9 +433,6 @@ gen_read_ireg(ireg, MuV, SHIFT); \ gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN= ]); \ STORE; \ - tcg_temp_free(ireg); \ - tcg_temp_free(HALF); \ - tcg_temp_free(BYTE); \ } while (0) =20 #define fGEN_TCG_S2_storerb_pbr(SHORTCODE) \ @@ -531,7 +514,6 @@ gen_helper_sfrecipa(tmp, cpu_env, RsV, RtV); \ tcg_gen_extrh_i64_i32(RdV, tmp); \ tcg_gen_extrl_i64_i32(PeV, tmp); \ - tcg_temp_free_i64(tmp); \ } while (0) =20 /* @@ -547,7 +529,6 @@ gen_helper_sfinvsqrta(tmp, cpu_env, RsV); \ tcg_gen_extrh_i64_i32(RdV, tmp); \ tcg_gen_extrl_i64_i32(PeV, tmp); \ - tcg_temp_free_i64(tmp); \ } while (0) =20 /* @@ -565,7 +546,6 @@ tcg_gen_add2_i64(RddV, carry, RddV, carry, RttV, zero); \ tcg_gen_extrl_i64_i32(PxV, carry); \ gen_8bitsof(PxV, PxV); \ - tcg_temp_free_i64(carry); \ } while (0) =20 /* r5:4 =3D sub(r1:0, r3:2, p1):carry */ @@ -581,8 +561,6 @@ tcg_gen_add2_i64(RddV, carry, RddV, carry, not_RttV, zero); \ tcg_gen_extrl_i64_i32(PxV, carry); \ gen_8bitsof(PxV, PxV); \ - tcg_temp_free_i64(carry); \ - tcg_temp_free_i64(not_RttV); \ } while (0) =20 /* @@ -607,9 +585,6 @@ tcg_gen_umin_tl(tmp, left, right); \ gen_set_byte_i64(i, RddV, tmp); \ } \ - tcg_temp_free(left); \ - tcg_temp_free(right); \ - tcg_temp_free(tmp); \ } while (0) =20 #define fGEN_TCG_J2_call(SHORTCODE) \ @@ -815,14 +790,12 @@ TCGv LSB =3D tcg_temp_new(); \ COND; \ gen_cond_jump(ctx, TCG_COND_EQ, LSB, riV); \ - tcg_temp_free(LSB); \ } while (0) #define fGEN_TCG_cond_jumpf(COND) \ do { \ TCGv LSB =3D tcg_temp_new(); \ COND; \ gen_cond_jump(ctx, TCG_COND_NE, LSB, riV); \ - tcg_temp_free(LSB); \ } while (0) =20 #define fGEN_TCG_J2_jumpt(SHORTCODE) \ @@ -863,14 +836,12 @@ TCGv LSB =3D tcg_temp_new(); \ COND; \ gen_cond_jumpr(ctx, RsV, TCG_COND_EQ, LSB); \ - tcg_temp_free(LSB); \ } while (0) #define fGEN_TCG_cond_jumprf(COND) \ do { \ TCGv LSB =3D tcg_temp_new(); \ COND; \ gen_cond_jumpr(ctx, RsV, TCG_COND_NE, LSB); \ - tcg_temp_free(LSB); \ } while (0) =20 #define fGEN_TCG_J2_jumprt(SHORTCODE) \ diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h index 083f4d92c6..94f272e286 100644 --- a/target/hexagon/gen_tcg_hvx.h +++ b/target/hexagon/gen_tcg_hvx.h @@ -136,7 +136,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx) TCGLabel *end_label =3D gen_new_label(); \ tcg_gen_andi_tl(lsb, PsV, 1); \ tcg_gen_brcondi_tl(TCG_COND_NE, lsb, PRED, false_label); \ - tcg_temp_free(lsb); \ tcg_gen_gvec_mov(MO_64, VdV_off, VuV_off, \ sizeof(MMVector), sizeof(MMVector)); \ tcg_gen_br(end_label); \ @@ -212,7 +211,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx) tcg_gen_andi_tl(shift, RtV, 15); \ tcg_gen_gvec_sars(MO_16, VdV_off, VuV_off, shift, \ sizeof(MMVector), sizeof(MMVector)); \ - tcg_temp_free(shift); \ } while (0) =20 #define fGEN_TCG_V6_vasrh_acc(SHORTCODE) \ @@ -224,7 +222,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx) sizeof(MMVector), sizeof(MMVector)); \ tcg_gen_gvec_add(MO_16, VxV_off, VxV_off, tmpoff, \ sizeof(MMVector), sizeof(MMVector)); \ - tcg_temp_free(shift); \ } while (0) =20 #define fGEN_TCG_V6_vasrw(SHORTCODE) \ @@ -233,7 +230,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx) tcg_gen_andi_tl(shift, RtV, 31); \ tcg_gen_gvec_sars(MO_32, VdV_off, VuV_off, shift, \ sizeof(MMVector), sizeof(MMVector)); \ - tcg_temp_free(shift); \ } while (0) =20 #define fGEN_TCG_V6_vasrw_acc(SHORTCODE) \ @@ -245,7 +241,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx) sizeof(MMVector), sizeof(MMVector)); \ tcg_gen_gvec_add(MO_32, VxV_off, VxV_off, tmpoff, \ sizeof(MMVector), sizeof(MMVector)); \ - tcg_temp_free(shift); \ } while (0) =20 #define fGEN_TCG_V6_vlsrb(SHORTCODE) \ @@ -254,7 +249,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx) tcg_gen_andi_tl(shift, RtV, 7); \ tcg_gen_gvec_shrs(MO_8, VdV_off, VuV_off, shift, \ sizeof(MMVector), sizeof(MMVector)); \ - tcg_temp_free(shift); \ } while (0) =20 #define fGEN_TCG_V6_vlsrh(SHORTCODE) \ @@ -263,7 +257,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx) tcg_gen_andi_tl(shift, RtV, 15); \ tcg_gen_gvec_shrs(MO_16, VdV_off, VuV_off, shift, \ sizeof(MMVector), sizeof(MMVector)); \ - tcg_temp_free(shift); \ } while (0) =20 #define fGEN_TCG_V6_vlsrw(SHORTCODE) \ @@ -272,7 +265,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx) tcg_gen_andi_tl(shift, RtV, 31); \ tcg_gen_gvec_shrs(MO_32, VdV_off, VuV_off, shift, \ sizeof(MMVector), sizeof(MMVector)); \ - tcg_temp_free(shift); \ } while (0) =20 /* Vector shift left - various forms */ @@ -282,7 +274,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx) tcg_gen_andi_tl(shift, RtV, 7); \ tcg_gen_gvec_shls(MO_8, VdV_off, VuV_off, shift, \ sizeof(MMVector), sizeof(MMVector)); \ - tcg_temp_free(shift); \ } while (0) =20 #define fGEN_TCG_V6_vaslh(SHORTCODE) \ @@ -291,7 +282,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx) tcg_gen_andi_tl(shift, RtV, 15); \ tcg_gen_gvec_shls(MO_16, VdV_off, VuV_off, shift, \ sizeof(MMVector), sizeof(MMVector)); \ - tcg_temp_free(shift); \ } while (0) =20 #define fGEN_TCG_V6_vaslh_acc(SHORTCODE) \ @@ -303,7 +293,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx) sizeof(MMVector), sizeof(MMVector)); \ tcg_gen_gvec_add(MO_16, VxV_off, VxV_off, tmpoff, \ sizeof(MMVector), sizeof(MMVector)); \ - tcg_temp_free(shift); \ } while (0) =20 #define fGEN_TCG_V6_vaslw(SHORTCODE) \ @@ -312,7 +301,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx) tcg_gen_andi_tl(shift, RtV, 31); \ tcg_gen_gvec_shls(MO_32, VdV_off, VuV_off, shift, \ sizeof(MMVector), sizeof(MMVector)); \ - tcg_temp_free(shift); \ } while (0) =20 #define fGEN_TCG_V6_vaslw_acc(SHORTCODE) \ @@ -324,7 +312,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx) sizeof(MMVector), sizeof(MMVector)); \ tcg_gen_gvec_add(MO_32, VxV_off, VxV_off, tmpoff, \ sizeof(MMVector), sizeof(MMVector)); \ - tcg_temp_free(shift); \ } while (0) =20 /* Vector max - various forms */ @@ -564,7 +551,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx) GET_EA; \ PRED; \ tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, false_label); \ - tcg_temp_free(LSB); \ gen_vreg_load(ctx, DSTOFF, EA, true); \ INC; \ tcg_gen_br(end_label); \ @@ -735,7 +721,6 @@ static inline void assert_vhist_tmp(DisasContext *ctx) GET_EA; \ PRED; \ tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, false_label); \ - tcg_temp_free(LSB); \ gen_vreg_store(ctx, EA, SRCOFF, insn->slot, ALIGN); \ INC; \ tcg_gen_br(end_label); \ diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index cd64bb8eec..17facadaad 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -220,8 +220,6 @@ static inline void gen_pred_cancel(TCGv pred, uint32_t = slot_num) tcg_gen_andi_tl(tmp, pred, 1); tcg_gen_movcond_tl(TCG_COND_EQ, hex_slot_cancelled, tmp, zero, slot_mask, hex_slot_cancelled); - tcg_temp_free(slot_mask); - tcg_temp_free(tmp); } #define PRED_LOAD_CANCEL(PRED, EA) \ gen_pred_cancel(PRED, insn->is_endloop ? 4 : insn->slot) @@ -376,10 +374,6 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val= , int shift) tcg_gen_deposit_tl(result, msb, lsb, 0, 7); =20 tcg_gen_shli_tl(result, result, shift); - - tcg_temp_free(msb); - tcg_temp_free(lsb); - return result; } #define fREAD_IREG(VAL, SHIFT) gen_read_ireg(ireg, (VAL), (SHIFT)) @@ -512,7 +506,6 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val,= int shift) TCGv tmp =3D tcg_temp_new(); \ tcg_gen_shli_tl(tmp, REG2, SCALE); \ tcg_gen_add_tl(EA, REG, tmp); \ - tcg_temp_free(tmp); \ } while (0) #define fEA_IRs(IMM, REG, SCALE) \ do { \ diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 591461b043..86bd093ce8 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -65,8 +65,6 @@ static inline void gen_masked_reg_write(TCGv new_val, TCG= v cur_val, tcg_gen_andi_tl(new_val, new_val, ~reg_mask); tcg_gen_andi_tl(tmp, cur_val, reg_mask); tcg_gen_or_tl(new_val, new_val, tmp); - - tcg_temp_free(tmp); } } =20 @@ -90,8 +88,6 @@ static inline void gen_log_predicated_reg_write(int rnum,= TCGv val, tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero); tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_m= ask); } - - tcg_temp_free(slot_mask); } =20 void gen_log_reg_write(int rnum, TCGv val) @@ -137,9 +133,6 @@ static void gen_log_predicated_reg_write_pair(int rnum,= TCGv_i64 val, tcg_gen_or_tl(hex_reg_written[rnum + 1], hex_reg_written[rnum + 1], slot_mask); } - - tcg_temp_free(val32); - tcg_temp_free(slot_mask); } =20 static void gen_log_reg_write_pair(int rnum, TCGv_i64 val) @@ -165,8 +158,6 @@ static void gen_log_reg_write_pair(int rnum, TCGv_i64 v= al) /* Do this so HELPER(debug_commit_end) will know */ tcg_gen_movi_tl(hex_reg_written[rnum + 1], 1); } - - tcg_temp_free(val32); } =20 void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val) @@ -189,8 +180,6 @@ void gen_log_pred_write(DisasContext *ctx, int pnum, TC= Gv val) hex_new_pred_value[pnum], base_val); } tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum); - - tcg_temp_free(base_val); } =20 static inline void gen_read_p3_0(TCGv control_reg) @@ -238,7 +227,6 @@ static inline void gen_read_ctrl_reg_pair(DisasContext = *ctx, const int reg_num, TCGv p3_0 =3D tcg_temp_new(); gen_read_p3_0(p3_0); tcg_gen_concat_i32_i64(dest, p3_0, hex_gpr[reg_num + 1]); - tcg_temp_free(p3_0); } else if (reg_num =3D=3D HEX_REG_PC - 1) { TCGv pc =3D tcg_constant_tl(ctx->base.pc_next); tcg_gen_concat_i32_i64(dest, hex_gpr[reg_num], pc); @@ -250,14 +238,11 @@ static inline void gen_read_ctrl_reg_pair(DisasContex= t *ctx, const int reg_num, tcg_gen_addi_tl(insn_cnt, hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns); tcg_gen_concat_i32_i64(dest, pkt_cnt, insn_cnt); - tcg_temp_free(pkt_cnt); - tcg_temp_free(insn_cnt); } else if (reg_num =3D=3D HEX_REG_QEMU_HVX_CNT) { TCGv hvx_cnt =3D tcg_temp_new(); tcg_gen_addi_tl(hvx_cnt, hex_gpr[HEX_REG_QEMU_HVX_CNT], ctx->num_hvx_insns); tcg_gen_concat_i32_i64(dest, hvx_cnt, hex_gpr[reg_num + 1]); - tcg_temp_free(hvx_cnt); } else { tcg_gen_concat_i32_i64(dest, hex_gpr[reg_num], @@ -273,7 +258,6 @@ static void gen_write_p3_0(DisasContext *ctx, TCGv cont= rol_reg) gen_log_pred_write(ctx, i, hex_p8); ctx_log_pred_write(ctx, i); } - tcg_temp_free(hex_p8); } =20 /* @@ -312,7 +296,6 @@ static inline void gen_write_ctrl_reg_pair(DisasContext= *ctx, int reg_num, gen_write_p3_0(ctx, val32); tcg_gen_extrh_i64_i32(val32, val); gen_log_reg_write(reg_num + 1, val32); - tcg_temp_free(val32); ctx_log_reg_write(ctx, reg_num + 1); } else { gen_log_reg_write_pair(reg_num, val); @@ -346,7 +329,6 @@ TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src,= bool sign) tcg_gen_extract_i64(res64, src, N * 8, 8); } tcg_gen_extrl_i64_i32(result, res64); - tcg_temp_free_i64(res64); =20 return result; } @@ -371,7 +353,6 @@ void gen_set_half_i64(int N, TCGv_i64 result, TCGv src) TCGv_i64 src64 =3D tcg_temp_new_i64(); tcg_gen_extu_i32_i64(src64, src); tcg_gen_deposit_i64(result, result, src64, N * 16, 16); - tcg_temp_free_i64(src64); } =20 void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src) @@ -379,7 +360,6 @@ void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src) TCGv_i64 src64 =3D tcg_temp_new_i64(); tcg_gen_extu_i32_i64(src64, src); tcg_gen_deposit_i64(result, result, src64, N * 8, 8); - tcg_temp_free_i64(src64); } =20 static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index) @@ -412,7 +392,6 @@ static inline void gen_store_conditional4(DisasContext = *ctx, ctx->mem_idx, MO_32); tcg_gen_movcond_tl(TCG_COND_EQ, pred, tmp, hex_llsc_val, one, zero); - tcg_temp_free(tmp); tcg_gen_br(done); =20 gen_set_label(fail); @@ -439,7 +418,6 @@ static inline void gen_store_conditional8(DisasContext = *ctx, tcg_gen_movcond_i64(TCG_COND_EQ, tmp, tmp, hex_llsc_val_i64, one, zero); tcg_gen_extrl_i64_i32(pred, tmp); - tcg_temp_free_i64(tmp); tcg_gen_br(done); =20 gen_set_label(fail); @@ -607,12 +585,10 @@ static void gen_cmpnd_cmp_jmp(DisasContext *ctx, TCGv pred =3D tcg_temp_new(); gen_compare(cond1, pred, arg1, arg2); gen_log_pred_write(ctx, pnum, pred); - tcg_temp_free(pred); } else { TCGv pred =3D tcg_temp_new(); tcg_gen_mov_tl(pred, hex_new_pred_value[pnum]); gen_cond_jump(ctx, cond2, pred, pc_off); - tcg_temp_free(pred); } } =20 @@ -666,12 +642,10 @@ static void gen_cmpnd_tstbit0_jmp(DisasContext *ctx, tcg_gen_andi_tl(pred, arg, 1); gen_8bitsof(pred, pred); gen_log_pred_write(ctx, pnum, pred); - tcg_temp_free(pred); } else { TCGv pred =3D tcg_temp_new(); tcg_gen_mov_tl(pred, hex_new_pred_value[pnum]); gen_cond_jump(ctx, cond, pred, pc_off); - tcg_temp_free(pred); } } =20 @@ -681,7 +655,6 @@ static void gen_testbit0_jumpnv(DisasContext *ctx, TCGv pred =3D tcg_temp_new(); tcg_gen_andi_tl(pred, arg, 1); gen_cond_jump(ctx, cond, pred, pc_off); - tcg_temp_free(pred); } =20 static void gen_jump(DisasContext *ctx, int pc_off) @@ -711,7 +684,6 @@ static void gen_cond_call(DisasContext *ctx, TCGv pred, tcg_gen_andi_tl(lsb, pred, 1); gen_write_new_pc_pcrel(ctx, pc_off, cond, lsb); tcg_gen_brcondi_tl(cond, lsb, 0, skip); - tcg_temp_free(lsb); next_PC =3D tcg_constant_tl(ctx->pkt->pc + ctx->pkt->encod_pkt_size_in_bytes); gen_log_reg_write(HEX_REG_LR, next_PC); @@ -771,8 +743,6 @@ static void gen_endloop0(DisasContext *ctx) } gen_set_label(label3); } - - tcg_temp_free(lpcfg); } =20 static void gen_cmp_jumpnv(DisasContext *ctx, @@ -781,7 +751,6 @@ static void gen_cmp_jumpnv(DisasContext *ctx, TCGv pred =3D tcg_temp_new(); tcg_gen_setcond_tl(cond, pred, val, src); gen_cond_jump(ctx, TCG_COND_EQ, pred, pc_off); - tcg_temp_free(pred); } =20 static void gen_cmpi_jumpnv(DisasContext *ctx, @@ -790,7 +759,6 @@ static void gen_cmpi_jumpnv(DisasContext *ctx, TCGv pred =3D tcg_temp_new(); tcg_gen_setcondi_tl(cond, pred, val, src); gen_cond_jump(ctx, TCG_COND_EQ, pred, pc_off); - tcg_temp_free(pred); } =20 /* Shift left with saturation */ @@ -830,11 +798,6 @@ static void gen_shl_sat(TCGv dst, TCGv src, TCGv shift= _amt) tcg_gen_or_tl(hex_new_value[HEX_REG_USR], hex_new_value[HEX_REG_USR], = ovf); =20 tcg_gen_movcond_tl(TCG_COND_EQ, dst, dst_sar, src, dst, satval); - - tcg_temp_free(sh32); - tcg_temp_free(dst_sar); - tcg_temp_free(ovf); - tcg_temp_free(satval); } =20 static void gen_sar(TCGv dst, TCGv src, TCGv shift_amt) @@ -846,7 +809,6 @@ static void gen_sar(TCGv dst, TCGv src, TCGv shift_amt) TCGv tmp =3D tcg_temp_new(); tcg_gen_umin_tl(tmp, shift_amt, tcg_constant_tl(31)); tcg_gen_sar_tl(dst, src, tmp); - tcg_temp_free(tmp); } =20 /* Bidirectional shift right with saturation */ @@ -869,8 +831,6 @@ static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv Rt= V) gen_sar(RdV, RsV, shift_amt); =20 gen_set_label(done); - - tcg_temp_free(shift_amt); } =20 /* Bidirectional shift left with saturation */ @@ -893,8 +853,6 @@ static void gen_asl_r_r_sat(TCGv RdV, TCGv RsV, TCGv Rt= V) gen_shl_sat(RdV, RsV, shift_amt); =20 gen_set_label(done); - - tcg_temp_free(shift_amt); } =20 static intptr_t vreg_src_off(DisasContext *ctx, int num) @@ -924,7 +882,6 @@ static void gen_log_vreg_write(DisasContext *ctx, intpt= r_t srcoff, int num, /* Don't do anything if the slot was cancelled */ tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1); tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end); - tcg_temp_free(cancelled); } =20 if (type !=3D EXT_TMP) { @@ -965,7 +922,6 @@ static void gen_log_qreg_write(intptr_t srcoff, int num= , int vnew, /* Don't do anything if the slot was cancelled */ tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1); tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end); - tcg_temp_free(cancelled); } =20 dstoff =3D offsetof(CPUHexagonState, future_QRegs[num]); @@ -989,7 +945,6 @@ static void gen_vreg_load(DisasContext *ctx, intptr_t d= stoff, TCGv src, tcg_gen_addi_tl(src, src, 8); tcg_gen_st_i64(tmp, cpu_env, dstoff + i * 8); } - tcg_temp_free_i64(tmp); } =20 static void gen_vreg_store(DisasContext *ctx, TCGv EA, intptr_t srcoff, @@ -1061,10 +1016,6 @@ static void vec_to_qvec(size_t size, intptr_t dstoff= , intptr_t srcoff) =20 tcg_gen_st8_i64(mask, cpu_env, dstoff + i); } - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(word); - tcg_temp_free_i64(bits); - tcg_temp_free_i64(mask); } =20 void probe_noshuf_load(TCGv va, int s, int mi) @@ -1088,7 +1039,6 @@ void gen_set_usr_field_if(int field, TCGv val) tcg_gen_or_tl(hex_new_value[HEX_REG_USR], hex_new_value[HEX_REG_USR], tmp); - tcg_temp_free(tmp); } else { TCGLabel *skip_label =3D gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, val, 0, skip_label); @@ -1140,7 +1090,6 @@ void gen_sat_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_= i64 source, int width) ovfl_64 =3D tcg_temp_new_i64(); tcg_gen_setcond_i64(TCG_COND_NE, ovfl_64, dest, source); tcg_gen_trunc_i64_tl(ovfl, ovfl_64); - tcg_temp_free_i64(ovfl_64); } =20 void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width) @@ -1158,7 +1107,6 @@ void gen_satu_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv= _i64 source, int width) ovfl_64 =3D tcg_temp_new_i64(); tcg_gen_setcond_i64(TCG_COND_NE, ovfl_64, dest, source); tcg_gen_trunc_i64_tl(ovfl, ovfl_64); - tcg_temp_free_i64(ovfl_64); } =20 /* Implements the fADDSAT64 macro in TCG */ @@ -1182,15 +1130,12 @@ void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv= _i64 b) =20 /* if (xor & mask) */ tcg_gen_and_i64(cond1, xor, mask); - tcg_temp_free_i64(xor); tcg_gen_brcondi_i64(TCG_COND_NE, cond1, 0, no_ovfl_label); - tcg_temp_free_i64(cond1); =20 /* else if ((a ^ sum) & mask) */ tcg_gen_xor_i64(cond2, a, sum); tcg_gen_and_i64(cond2, cond2, mask); tcg_gen_brcondi_i64(TCG_COND_NE, cond2, 0, ovfl_label); - tcg_temp_free_i64(cond2); /* fallthrough to no_ovfl_label branch */ =20 /* if branch */ @@ -1201,10 +1146,7 @@ void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_= i64 b) /* else if branch */ gen_set_label(ovfl_label); tcg_gen_and_i64(cond3, sum, mask); - tcg_temp_free_i64(mask); - tcg_temp_free_i64(sum); tcg_gen_movcond_i64(TCG_COND_NE, ret, cond3, zero, max_pos, max_neg); - tcg_temp_free_i64(cond3); SET_USR_FIELD(USR_OVF, 1); =20 gen_set_label(ret_label); diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 381fdaa3a8..93fd1b55e3 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -481,7 +481,6 @@ static void gen_pred_writes(DisasContext *ctx) hex_new_pred_value[pred_num], hex_pred[pred_num]); } - tcg_temp_free(pred_written); } else { for (i =3D 0; i < ctx->preg_log_idx; i++) { int pred_num =3D ctx->preg_log[i]; @@ -536,7 +535,6 @@ void process_store(DisasContext *ctx, int slot_num) /* Don't do anything if the slot was cancelled */ tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1); tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end); - tcg_temp_free(cancelled); } { TCGv address =3D tcg_temp_new(); @@ -586,7 +584,6 @@ void process_store(DisasContext *ctx, int slot_num) gen_helper_commit_store(cpu_env, slot); } } - tcg_temp_free(address); } if (is_predicated) { gen_set_label(label_end); @@ -627,8 +624,6 @@ static void process_dczeroa(DisasContext *ctx) tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); tcg_gen_addi_tl(addr, addr, 8); tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); - - tcg_temp_free(addr); } } =20 @@ -673,7 +668,6 @@ static void gen_commit_hvx(DisasContext *ctx) =20 tcg_gen_andi_tl(cmp, hex_VRegs_updated, 1 << rnum); tcg_gen_brcondi_tl(TCG_COND_EQ, cmp, 0, label_skip); - tcg_temp_free(cmp); tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); gen_set_label(label_skip); } else { @@ -706,7 +700,6 @@ static void gen_commit_hvx(DisasContext *ctx) =20 tcg_gen_andi_tl(cmp, hex_QRegs_updated, 1 << rnum); tcg_gen_brcondi_tl(TCG_COND_EQ, cmp, 0, label_skip); - tcg_temp_free(cmp); tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); gen_set_label(label_skip); } else { diff --git a/target/hexagon/README b/target/hexagon/README index 2e32639fb7..251960b862 100644 --- a/target/hexagon/README +++ b/target/hexagon/README @@ -88,7 +88,6 @@ tcg_funcs_generated.c.inc gen_helper_A2_add(RdV, cpu_env, RsV, RtV); gen_log_reg_write(RdN, RdV); ctx_log_reg_write(ctx, RdN); - tcg_temp_free(RdV); } =20 helper_funcs_generated.c.inc @@ -160,12 +159,8 @@ istruction. tcg_gen_addi_ptr(VvV, cpu_env, VvV_off); TCGv slot =3D tcg_constant_tl(insn->slot); gen_helper_V6_vaddw(cpu_env, VdV, VuV, VvV, slot); - tcg_temp_free(slot); gen_log_vreg_write(ctx, VdV_off, VdN, EXT_DFL, insn->slot, false); ctx_log_vreg_write(ctx, VdN, EXT_DFL, false); - tcg_temp_free_ptr(VdV); - tcg_temp_free_ptr(VuV); - tcg_temp_free_ptr(VvV); } =20 Notice that we also generate a variable named _off for each opera= nd of --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.26.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:26:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=71aFye+WP3h6iEWEabrVi+cTpkdhpONrYK9bA8dUw1w=; b=Q5n8RMLdumFshWYGiMjd5WBTB6KGLZ69qWxkM+c2EWG0yF7hUmXFZAlF2vIWg4iyMx 2ixCOtF45dyF0iQRjJoFvANR9XzpXyL1Vn59O/OFVttdxrop/o9+i4j+rE96pVb9M1wS 8cdKDcyyBrWLBZbnob5vmH62udbIen5b3SLnMddswwYWNpx51xSxczCFjCTGAKnDBxzC FAY4u2pIt1HXcYHFoEiuKqP5nXPUheQysia2eduLb6X+LWcLsjTk5OyizXrE3kKhSlzy zMtDuDIlglezchGyHyAViBFz3xCJePAaNeNTk32rI8fdhi+2kQ32by8OB7SqaAvtTnPL Vwjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=71aFye+WP3h6iEWEabrVi+cTpkdhpONrYK9bA8dUw1w=; b=7QddCfK5HT6Ag2Q11ve80+YWIN3WlYwQYIsmNRDDoVkqr5u0WVnO/VUyKtf4l6eE40 6hwrN8kYcjH4ZBe8KfdrlVwcqt1JvU3b1gdRH/NKmxy4bEfQr5O7iNIUiFpKc8V/TL+j oHDuskliuwCGqU6WJrzrOy2riBZCpovfy6kOpqkc19vG+hqgsLVPAd/0iQ4ZvYq7sAPV NPWFh6imNqO//5mptq1SlHZOQd736XKxCzhxgVJdjIgL+T6F0mxP6d3boASx7N0XtmMF hL/Yl2I1ebnFl8COQ+ViLXGOp9WTcs527tXn2ATx7fmzvcDcG02//PMPbk+MCPC/pDgr TK0w== X-Gm-Message-State: AO0yUKUB4HrU/9KfSGB1jCVWhcLCuPPG4HTRsY+YE357HWSKMDo/6Mfv VTyONYUJBKm70i31Uqlg7O4RboBjCPaWlKhaZ8iKuA== X-Google-Smtp-Source: AK7set8AT/VgbXVU2hREkJKYMdSkadtOgUSaGhvr+oE68s3Miqln+VCK3hTs5NbgPZgL4auC8URlgw== X-Received: by 2002:a17:903:2908:b0:19d:135:2013 with SMTP id lh8-20020a170903290800b0019d01352013mr3812096plb.26.1677475581659; Sun, 26 Feb 2023 21:26:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 26/76] target/hexagon: Drop tcg_temp_free from gen_tcg_funcs.py Date: Sun, 26 Feb 2023 19:24:15 -1000 Message-Id: <20230227052505.352889-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476349723100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Taylor Simpson --- target/hexagon/gen_tcg_funcs.py | 79 +-------------------------------- 1 file changed, 1 insertion(+), 78 deletions(-) diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py index dfc90712fb..02cb52c21e 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -26,10 +26,7 @@ ## Helpers for gen_tcg_func ## def gen_decl_ea_tcg(f, tag): - f.write(" TCGv EA =3D tcg_temp_new();\n") - -def gen_free_ea_tcg(f): - f.write(" tcg_temp_free(EA);\n") + f.write(" TCGv EA G_GNUC_UNUSED =3D tcg_temp_new();\n") =20 def genptr_decl_pair_writable(f, tag, regtype, regid, regno): regN=3D"%s%sN" % (regtype,regid) @@ -269,73 +266,6 @@ def genptr_decl_imm(f,immlett): f.write(" int %s =3D insn->immed[%d];\n" % \ (hex_common.imm_name(immlett), i)) =20 -def genptr_free(f, tag, regtype, regid, regno): - if (regtype =3D=3D "R"): - if (regid in {"dd", "ss", "tt", "xx", "yy"}): - f.write(" tcg_temp_free_i64(%s%sV);\n" % (regtype, regid)) - elif (regid in {"d", "e", "x", "y"}): - f.write(" tcg_temp_free(%s%sV);\n" % (regtype, regid)) - elif (regid not in {"s", "t", "u", "v"}): - print("Bad register parse: ",regtype,regid) - elif (regtype =3D=3D "P"): - if (regid in {"d", "e", "x"}): - f.write(" tcg_temp_free(%s%sV);\n" % (regtype, regid)) - elif (regid not in {"s", "t", "u", "v"}): - print("Bad register parse: ",regtype,regid) - elif (regtype =3D=3D "C"): - if (regid in {"dd", "ss"}): - f.write(" tcg_temp_free_i64(%s%sV);\n" % (regtype, regid)) - elif (regid in {"d", "s"}): - f.write(" tcg_temp_free(%s%sV);\n" % (regtype, regid)) - else: - print("Bad register parse: ",regtype,regid) - elif (regtype =3D=3D "M"): - if (regid !=3D "u"): - print("Bad register parse: ", regtype, regid) - elif (regtype =3D=3D "V"): - if (regid in {"dd", "uu", "vv", "xx", \ - "d", "s", "u", "v", "w", "x", "y"}): - if (not hex_common.skip_qemu_helper(tag)): - f.write(" tcg_temp_free_ptr(%s%sV);\n" % \ - (regtype, regid)) - else: - print("Bad register parse: ", regtype, regid) - elif (regtype =3D=3D "Q"): - if (regid in {"d", "e", "s", "t", "u", "v", "x"}): - if (not hex_common.skip_qemu_helper(tag)): - f.write(" tcg_temp_free_ptr(%s%sV);\n" % \ - (regtype, regid)) - else: - print("Bad register parse: ", regtype, regid) - else: - print("Bad register parse: ", regtype, regid) - -def genptr_free_new(f, tag, regtype, regid, regno): - if (regtype =3D=3D "N"): - if (regid not in {"s", "t"}): - print("Bad register parse: ", regtype, regid) - elif (regtype =3D=3D "P"): - if (regid not in {"t", "u", "v"}): - print("Bad register parse: ", regtype, regid) - elif (regtype =3D=3D "O"): - if (regid !=3D "s"): - print("Bad register parse: ", regtype, regid) - else: - print("Bad register parse: ", regtype, regid) - -def genptr_free_opn(f,regtype,regid,i,tag): - if (hex_common.is_pair(regid)): - genptr_free(f, tag, regtype, regid, i) - elif (hex_common.is_single(regid)): - if hex_common.is_old_val(regtype, regid, tag): - genptr_free(f, tag, regtype, regid, i) - elif hex_common.is_new_val(regtype, regid, tag): - genptr_free_new(f, tag, regtype, regid, i) - else: - print("Bad register parse: ",regtype,regid,toss,numregs) - else: - print("Bad register parse: ",regtype,regid,toss,numregs) - def genptr_src_read(f, tag, regtype, regid): if (regtype =3D=3D "R"): if (regid in {"ss", "tt", "xx", "yy"}): @@ -578,7 +508,6 @@ def genptr_dst_write_opn(f,regtype, regid, tag): ## ## gen_log_reg_write(RdN, RdV); ## ctx_log_reg_write(ctx, RdN); -## tcg_temp_free(RdV); ## } ## ## where depends on hex_common.skip_qemu_helper(tag) @@ -692,12 +621,6 @@ def gen_tcg_func(f, tag, regs, imms): if (hex_common.is_written(regid)): genptr_dst_write_opn(f,regtype, regid, tag) =20 - ## Free all the operands (regs and immediates) - if hex_common.need_ea(tag): gen_free_ea_tcg(f) - for regtype,regid,toss,numregs in regs: - genptr_free_opn(f,regtype,regid,i,tag) - i +=3D 1 - f.write("}\n\n") =20 def gen_def_tcg_func(f, tag, tagregs, tagimms): --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677476765; cv=none; d=zohomail.com; s=zohoarc; b=RYiO+PfQ92zg8hgofY2G2NZoEk9hvfKvA897glwLc+ILLKZ57h6ozs+9yErQHi+6pRGH8fqGYqQ8DBPPIS3EnQf149jdRj5lnIG0oHDcSGFNflXi9AniS+GqDXxSCOAGP2WpGvgFl4dwP2geuBnC89WXjmFpUE+6LYlwKXqBBdg= ARC-Message-Signature: i=1; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.26.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:26:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iXFDJ1LjOE1ad3aZYo7rVF9NYtO4EfezTlr8TwcRcS4=; b=fNMLT+mdRYstEzhR+d+GehzObMsKbXmLgb1guOIUCKGt84Scuq7GAqt79cvm4ONWlw 42Jx7TvyFCOB9z2GBjEeUlAymcaVumgK28c/gjgNOeWpxj0p89fXBSrpg8t54SHi/E+s UJn2HYBeyS82QghA2Ge91vhGQVAv7Pm5Y87XfQaxQ5OnbfhQBWkhGzlpoC8CGo4ORj2I qHhhuvh4FGG7x7jEXGLUBZZDgfPnYEdhvE+/IBcayLNn+YCCJuHeQFrRNQYyr6EEHsko vl8A2pK+oOLzE0onA3xRfgUjAeRB/bwtHdl1AcvRUoC57URn91D3tVfBF7cUFVhKWR4z Ov/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iXFDJ1LjOE1ad3aZYo7rVF9NYtO4EfezTlr8TwcRcS4=; b=VmEy9EWZtOPEbttJR4R8/l/vgkK5o16TqoVonjF/KXPr7GGpS9v5M6hckOyS33aEQo X0Rsi5L0eW2WtVAfHj2A8BqdXnAhhzpAmAty004agJKQm1UHsVInpx1nq3v63ziOF86U XFqhMw/B2xgxbQNglC4XFEsTJxS/Tc/j/tZZJ7IbsGJ4miJL3rwtc7ys/IAolc5a0XQV xZF6TkNq8/7mRnyC3Ds2XyzgXNA5eY7gVhEFvRNEIjqQxhZRaLjhelOQRfZ0HwTZEaoP 02ULB2Gln1mtoZV3xRFq2M7egqhhDgzbO4olqmpfhY1yxoWzCnLwUmNxqL2FHuV7k0E1 JLlQ== X-Gm-Message-State: AO0yUKWGbm6EnHiGi223s13wo7VsMiU8ji9ryNBSTuJvZiGUW5h6YJYo FqfZFPqkNffjwr66BVyx2MvdB+u1JH0PFPt8g31nFg== X-Google-Smtp-Source: AK7set9KakpXR1hgFlK/DSJyw1BIJHXEWt0sCzyd4xE0031G1GcYbEtn6BYN7vfX9YasukVqxHRtAw== X-Received: by 2002:a17:903:32ce:b0:194:7a99:d5ce with SMTP id i14-20020a17090332ce00b001947a99d5cemr28649358plr.12.1677475584550; Sun, 26 Feb 2023 21:26:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 27/76] target/hexagon/idef-parser: Drop tcg_temp_free Date: Sun, 26 Feb 2023 19:24:16 -1000 Message-Id: <20230227052505.352889-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476767458100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. This removes gen_rvalue_free, gen_rvalue_free_manual and free_variables, whose only purpose was to emit tcg_temp_free. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Taylor Simpson --- target/hexagon/idef-parser/README.rst | 8 -- target/hexagon/idef-parser/parser-helpers.h | 4 - target/hexagon/idef-parser/parser-helpers.c | 142 -------------------- target/hexagon/idef-parser/idef-parser.y | 10 -- 4 files changed, 164 deletions(-) diff --git a/target/hexagon/idef-parser/README.rst b/target/hexagon/idef-pa= rser/README.rst index c230fec124..debeddfde5 100644 --- a/target/hexagon/idef-parser/README.rst +++ b/target/hexagon/idef-parser/README.rst @@ -31,7 +31,6 @@ idef-parser will compile the above code into the followin= g code: TCGv_i32 tmp_0 =3D tcg_temp_new_i32(); tcg_gen_add_i32(tmp_0, RsV, RtV); tcg_gen_mov_i32(RdV, tmp_0); - tcg_temp_free_i32(tmp_0); } =20 The output of the compilation process will be a function, containing the @@ -102,12 +101,6 @@ The result of the addition is now stored in the tempor= ary, we move it into the correct destination register. This code may seem inefficient, but QEMU will perform some optimizations on the tinycode, reducing the unnecessary copy. =20 -:: - - tcg_temp_free_i32(tmp_0); - -Finally, we free the temporary we used to hold the addition result. - Parser Input ------------ =20 @@ -524,7 +517,6 @@ instruction, TCGv_i32 tmp_0 =3D tcg_temp_new_i32(); tcg_gen_add_i32(tmp_0, RsV, RsV); tcg_gen_mov_i32(RdV, tmp_0); - tcg_temp_free_i32(tmp_0); } =20 Here the bug, albeit hard to spot, is in ``tcg_gen_add_i32(tmp_0, RsV, RsV= );`` diff --git a/target/hexagon/idef-parser/parser-helpers.h b/target/hexagon/i= def-parser/parser-helpers.h index 2766296417..4c89498f5b 100644 --- a/target/hexagon/idef-parser/parser-helpers.h +++ b/target/hexagon/idef-parser/parser-helpers.h @@ -169,8 +169,6 @@ HexValue gen_imm_value(Context *c __attribute__((unused= )), HexValue gen_imm_qemu_tmp(Context *c, YYLTYPE *locp, unsigned bit_width, HexSignedness signedness); =20 -void gen_rvalue_free(Context *c, YYLTYPE *locp, HexValue *rvalue); - HexValue rvalue_materialize(Context *c, YYLTYPE *locp, HexValue *rvalue); =20 HexValue gen_rvalue_extend(Context *c, YYLTYPE *locp, HexValue *rvalue); @@ -365,8 +363,6 @@ void emit_footer(Context *c); =20 void track_string(Context *c, GString *s); =20 -void free_variables(Context *c, YYLTYPE *locp); - void free_instruction(Context *c); =20 void assert_signedness(Context *c, diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/i= def-parser/parser-helpers.c index 3025040640..bdbb8b6a5f 100644 --- a/target/hexagon/idef-parser/parser-helpers.c +++ b/target/hexagon/idef-parser/parser-helpers.c @@ -398,25 +398,10 @@ HexValue gen_imm_qemu_tmp(Context *c, YYLTYPE *locp, = unsigned bit_width, return rvalue; } =20 -void gen_rvalue_free(Context *c, YYLTYPE *locp, HexValue *rvalue) -{ - if (rvalue->type =3D=3D TEMP && !rvalue->is_manual) { - const char *bit_suffix =3D (rvalue->bit_width =3D=3D 64) ? "i64" := "i32"; - OUT(c, locp, "tcg_temp_free_", bit_suffix, "(", rvalue, ");\n"); - } -} - -static void gen_rvalue_free_manual(Context *c, YYLTYPE *locp, HexValue *rv= alue) -{ - rvalue->is_manual =3D false; - gen_rvalue_free(c, locp, rvalue); -} - HexValue rvalue_materialize(Context *c, YYLTYPE *locp, HexValue *rvalue) { if (rvalue->type =3D=3D IMMEDIATE) { HexValue res =3D gen_tmp_value_from_imm(c, locp, rvalue); - gen_rvalue_free(c, locp, rvalue); return res; } return *rvalue; @@ -445,7 +430,6 @@ HexValue gen_rvalue_extend(Context *c, YYLTYPE *locp, H= exValue *rvalue) const char *sign_suffix =3D is_unsigned ? "u" : ""; OUT(c, locp, "tcg_gen_ext", sign_suffix, "_i32_i64(", &res, ", ", rvalue, ");\n"); - gen_rvalue_free(c, locp, rvalue); return res; } } @@ -460,7 +444,6 @@ HexValue gen_rvalue_truncate(Context *c, YYLTYPE *locp,= HexValue *rvalue) if (rvalue->bit_width =3D=3D 64) { HexValue res =3D gen_tmp(c, locp, 32, rvalue->signedness); OUT(c, locp, "tcg_gen_trunc_i64_tl(", &res, ", ", rvalue, ");\= n"); - gen_rvalue_free(c, locp, rvalue); return res; } } @@ -587,11 +570,6 @@ HexValue gen_bin_cmp(Context *c, fprintf(stderr, "Error in evalutating immediateness!"); abort(); } - - /* Free operands */ - gen_rvalue_free(c, locp, &op1_m); - gen_rvalue_free(c, locp, &op2_m); - return res; } =20 @@ -627,8 +605,6 @@ static void gen_simple_op(Context *c, YYLTYPE *locp, un= signed bit_width, "(", res, ", ", op1, ", ", op2, ");\n"); break; } - gen_rvalue_free(c, locp, op1); - gen_rvalue_free(c, locp, op2); } =20 static void gen_sub_op(Context *c, YYLTYPE *locp, unsigned bit_width, @@ -658,8 +634,6 @@ static void gen_sub_op(Context *c, YYLTYPE *locp, unsig= ned bit_width, "(", res, ", ", op1, ", ", op2, ");\n"); } break; } - gen_rvalue_free(c, locp, op1); - gen_rvalue_free(c, locp, op2); } =20 static void gen_asl_op(Context *c, YYLTYPE *locp, unsigned bit_width, @@ -711,10 +685,7 @@ static void gen_asl_op(Context *c, YYLTYPE *locp, unsi= gned bit_width, OUT(c, locp, "tcg_gen_movcond_i", &bit_width); OUT(c, locp, "(TCG_COND_GEU, ", res, ", ", &op2_m, ", ", &edge); OUT(c, locp, ", ", &zero, ", ", res, ");\n"); - gen_rvalue_free(c, locp, &edge); } - gen_rvalue_free(c, locp, &op1_m); - gen_rvalue_free(c, locp, &op2_m); } =20 static void gen_asr_op(Context *c, YYLTYPE *locp, unsigned bit_width, @@ -769,11 +740,7 @@ static void gen_asr_op(Context *c, YYLTYPE *locp, unsi= gned bit_width, OUT(c, locp, "tcg_gen_movcond_i", &bit_width); OUT(c, locp, "(TCG_COND_GEU, ", res, ", ", &op2_m, ", ", &edge); OUT(c, locp, ", ", &tmp, ", ", res, ");\n"); - gen_rvalue_free(c, locp, &edge); - gen_rvalue_free(c, locp, &tmp); } - gen_rvalue_free(c, locp, &op1_m); - gen_rvalue_free(c, locp, &op2_m); } =20 static void gen_lsr_op(Context *c, YYLTYPE *locp, unsigned bit_width, @@ -815,10 +782,7 @@ static void gen_lsr_op(Context *c, YYLTYPE *locp, unsi= gned bit_width, OUT(c, locp, "tcg_gen_movcond_i", &bit_width); OUT(c, locp, "(TCG_COND_GEU, ", res, ", ", &op2_m, ", ", &edge); OUT(c, locp, ", ", &zero, ", ", res, ");\n"); - gen_rvalue_free(c, locp, &edge); } - gen_rvalue_free(c, locp, &op1_m); - gen_rvalue_free(c, locp, &op2_m); } =20 /* @@ -847,9 +811,6 @@ static void gen_andl_op(Context *c, YYLTYPE *locp, unsi= gned bit_width, tmp2 =3D gen_bin_cmp(c, locp, TCG_COND_NE, op2, &zero); OUT(c, locp, "tcg_gen_and_", bit_suffix, "(", res, ", ", &tmp1, ", ", &tmp2, ");\n"); - gen_rvalue_free_manual(c, locp, &zero); - gen_rvalue_free(c, locp, &tmp1); - gen_rvalue_free(c, locp, &tmp2); break; } } @@ -892,8 +853,6 @@ static void gen_minmax_op(Context *c, YYLTYPE *locp, un= signed bit_width, OUT(c, locp, res, ", ", op1, ", ", &op2_m, ");\n"); break; } - gen_rvalue_free(c, locp, &op1_m); - gen_rvalue_free(c, locp, &op2_m); } =20 /* Code generation functions */ @@ -1055,7 +1014,6 @@ HexValue gen_cast_op(Context *c, &res, ", ", src, ");\n"); } } - gen_rvalue_free(c, locp, src); return res; } } @@ -1115,8 +1073,6 @@ static HexValue gen_extend_imm_width_op(Context *c, if (need_guarding) { OUT(c, locp, "}\n"); } - - gen_rvalue_free(c, locp, value); return res; } else { /* @@ -1141,8 +1097,6 @@ static HexValue gen_extend_imm_width_op(Context *c, ", 0);\n"); OUT(c, locp, "}\n"); } - - gen_rvalue_free(c, locp, value); return res; } } @@ -1182,7 +1136,6 @@ static HexValue gen_extend_tcg_width_op(Context *c, &mask, ", ", &mask, ", ", &shift, ");\n"); OUT(c, locp, "tcg_gen_and_i", &dst_width, "(", &res, ", ", value, ", ", &mask, ");\n"); - gen_rvalue_free(c, locp, &mask); } else { OUT(c, locp, "tcg_gen_shl_i", &dst_width, "(", &res, ", ", value, ", ", &shift, ");\n"); @@ -1194,10 +1147,6 @@ static HexValue gen_extend_tcg_width_op(Context *c, OUT(c, locp, &src_width_m, ", ", &zero, ", ", &zero, ", ", &res, ");\n"); =20 - gen_rvalue_free(c, locp, &src_width_m); - gen_rvalue_free(c, locp, value); - gen_rvalue_free(c, locp, &shift); - return res; } =20 @@ -1316,9 +1265,6 @@ void gen_rdeposit_op(Context *c, dst); OUT(c, locp, ", ", &width_m, ", ", &zero, ", ", &res, ", ", dst, ");\n"); - - gen_rvalue_free(c, locp, width); - gen_rvalue_free(c, locp, &res); } =20 void gen_deposit_op(Context *c, @@ -1352,8 +1298,6 @@ void gen_deposit_op(Context *c, value_m =3D rvalue_materialize(c, locp, &value_m); OUT(c, locp, "tcg_gen_deposit_i", &bit_width, "(", dst, ", ", dst, ", = "); OUT(c, locp, &value_m, ", ", index, " * ", &width, ", ", &width, ");\n= "); - gen_rvalue_free(c, locp, index); - gen_rvalue_free(c, locp, &value_m); } =20 HexValue gen_rextract_op(Context *c, @@ -1366,7 +1310,6 @@ HexValue gen_rextract_op(Context *c, HexValue res =3D gen_tmp(c, locp, bit_width, UNSIGNED); OUT(c, locp, "tcg_gen_extract_i", &bit_width, "(", &res); OUT(c, locp, ", ", src, ", ", &begin, ", ", &width, ");\n"); - gen_rvalue_free(c, locp, src); return res; } =20 @@ -1399,12 +1342,8 @@ HexValue gen_extract_op(Context *c, const char *sign_suffix =3D (extract->signedness =3D=3D UNSIGNED) = ? "u" : ""; OUT(c, locp, "tcg_gen_ext", sign_suffix, "_i32_i64(", &tmp, ", ", &res, ");\n"); - gen_rvalue_free(c, locp, &res); res =3D tmp; } - - gen_rvalue_free(c, locp, src); - gen_rvalue_free(c, locp, index); return res; } =20 @@ -1422,8 +1361,6 @@ void gen_write_reg(Context *c, YYLTYPE *locp, HexValu= e *reg, HexValue *value) locp, "ctx_log_reg_write(ctx, ", ®->reg.id, ");\n"); - gen_rvalue_free(c, locp, reg); - gen_rvalue_free(c, locp, &value_m); } =20 void gen_assign(Context *c, @@ -1458,8 +1395,6 @@ void gen_assign(Context *c, const char *imm_suffix =3D (value_m.type =3D=3D IMMEDIATE) ? "i" : ""; OUT(c, locp, "tcg_gen_mov", imm_suffix, "_i", &bit_width, "(", dst, ", ", &value_m, ");\n"); - - gen_rvalue_free(c, locp, &value_m); } =20 HexValue gen_convround(Context *c, @@ -1484,12 +1419,6 @@ HexValue gen_convround(Context *c, OUT(c, locp, ", ", &and, ", ", &mask, ", "); OUT(c, locp, &src_p1, ", ", &src_m, ");\n"); =20 - /* Free src but use the original `is_manual` value */ - gen_rvalue_free(c, locp, src); - - /* Free the rest of the values */ - gen_rvalue_free(c, locp, &src_p1); - return res; } =20 @@ -1515,9 +1444,6 @@ static HexValue gen_convround_n_b(Context *c, OUT(c, locp, "tcg_gen_add_i64(", &res); OUT(c, locp, ", ", &res, ", ", &tmp_64, ");\n"); =20 - gen_rvalue_free(c, locp, &tmp); - gen_rvalue_free(c, locp, &tmp_64); - return res; } =20 @@ -1540,10 +1466,6 @@ static HexValue gen_convround_n_c(Context *c, OUT(c, locp, "tcg_gen_add_i64(", &res); OUT(c, locp, ", ", &res, ", ", &tmp_64, ");\n"); =20 - gen_rvalue_free(c, locp, &one); - gen_rvalue_free(c, locp, &tmp); - gen_rvalue_free(c, locp, &tmp_64); - return res; } =20 @@ -1614,18 +1536,6 @@ HexValue gen_convround_n(Context *c, OUT(c, locp, "tcg_gen_shr_i64(", &res); OUT(c, locp, ", ", &res, ", ", &n_64, ");\n"); =20 - gen_rvalue_free(c, locp, &src_casted); - gen_rvalue_free(c, locp, &pos_casted); - - gen_rvalue_free(c, locp, &r1); - gen_rvalue_free(c, locp, &r2); - gen_rvalue_free(c, locp, &r3); - - gen_rvalue_free(c, locp, &cond); - gen_rvalue_free(c, locp, &cond_64); - gen_rvalue_free(c, locp, &mask); - gen_rvalue_free(c, locp, &n_64); - res =3D gen_rvalue_truncate(c, locp, &res); return res; } @@ -1671,10 +1581,6 @@ HexValue gen_round(Context *c, OUT(c, locp, "(TCG_COND_EQ, ", &res, ", ", &b, ", ", &zero); OUT(c, locp, ", ", &a, ", ", &sum, ");\n"); =20 - gen_rvalue_free_manual(c, locp, &a); - gen_rvalue_free_manual(c, locp, &b); - gen_rvalue_free(c, locp, &sum); - return res; } =20 @@ -1700,9 +1606,6 @@ void gen_circ_op(Context *c, ", ", modifier); OUT(c, locp, ", ", &cs, ");\n"); - gen_rvalue_free(c, locp, &increment_m); - gen_rvalue_free(c, locp, modifier); - gen_rvalue_free(c, locp, &cs); } =20 HexValue gen_locnt_op(Context *c, YYLTYPE *locp, HexValue *src) @@ -1718,7 +1621,6 @@ HexValue gen_locnt_op(Context *c, YYLTYPE *locp, HexV= alue *src) &res, ", ", &src_m, ");\n"); OUT(c, locp, "tcg_gen_clzi_i", bit_suffix, "(", &res, ", ", &res, ", "= ); OUT(c, locp, bit_suffix, ");\n"); - gen_rvalue_free(c, locp, &src_m); return res; } =20 @@ -1732,7 +1634,6 @@ HexValue gen_ctpop_op(Context *c, YYLTYPE *locp, HexV= alue *src) src_m =3D rvalue_materialize(c, locp, &src_m); OUT(c, locp, "tcg_gen_ctpop_i", bit_suffix, "(", &res, ", ", &src_m, ");\n"); - gen_rvalue_free(c, locp, &src_m); return res; } =20 @@ -1751,8 +1652,6 @@ HexValue gen_rotl(Context *c, YYLTYPE *locp, HexValue= *src, HexValue *width) amount =3D rvalue_materialize(c, locp, &amount); OUT(c, locp, "tcg_gen_rotl_", suffix, "(", &res, ", ", src, ", ", &amount, ");\n"); - gen_rvalue_free(c, locp, src); - gen_rvalue_free(c, locp, &amount); =20 return res; } @@ -1777,10 +1676,6 @@ HexValue gen_carry_from_add(Context *c, OUT(c, locp, "tcg_gen_add2_i64(", &res, ", ", &cf, ", ", &res, ", ", &= cf); OUT(c, locp, ", ", &op2_m, ", ", &zero, ");\n"); =20 - gen_rvalue_free(c, locp, &op1_m); - gen_rvalue_free(c, locp, &op2_m); - gen_rvalue_free(c, locp, &op3_m); - gen_rvalue_free(c, locp, &res); return cf; } =20 @@ -1845,7 +1740,6 @@ void gen_inst_code(Context *c, YYLTYPE *locp) c->inst.name->str, c->inst.error_count); } else { - free_variables(c, locp); c->implemented_insn++; fprintf(c->enabled_file, "%s\n", c->inst.name->str); emit_footer(c); @@ -1875,10 +1769,7 @@ void gen_pred_assign(Context *c, YYLTYPE *locp, HexV= alue *left_pred, OUT(c, locp, "gen_log_pred_write(ctx, ", pred_id, ", ", left_pred, ");\n"); OUT(c, locp, "ctx_log_pred_write(ctx, ", pred_id, ");\n"); - gen_rvalue_free(c, locp, left_pred); } - /* Free temporary value */ - gen_rvalue_free(c, locp, &r); } =20 void gen_cancel(Context *c, YYLTYPE *locp) @@ -1928,8 +1819,6 @@ void gen_load(Context *c, YYLTYPE *locp, HexValue *wi= dth, OUT(c, locp, "(TCGv) "); } OUT(c, locp, dst, ", ", ea, ", ctx->mem_idx);\n"); - /* If the var in EA was truncated it is now a tmp HexValue, so free it= . */ - gen_rvalue_free(c, locp, ea); } =20 void gen_store(Context *c, YYLTYPE *locp, HexValue *width, HexValue *ea, @@ -1943,9 +1832,6 @@ void gen_store(Context *c, YYLTYPE *locp, HexValue *w= idth, HexValue *ea, src_m =3D rvalue_materialize(c, locp, &src_m); OUT(c, locp, "gen_store", &mem_width, "(cpu_env, ", ea, ", ", &src_m); OUT(c, locp, ", insn->slot);\n"); - gen_rvalue_free(c, locp, &src_m); - /* If the var in ea was truncated it is now a tmp HexValue, so free it= . */ - gen_rvalue_free(c, locp, ea); } =20 void gen_sethalf(Context *c, YYLTYPE *locp, HexCast *sh, HexValue *n, @@ -1982,11 +1868,6 @@ void gen_setbits(Context *c, YYLTYPE *locp, HexValue= *hi, HexValue *lo, OUT(c, locp, "tcg_gen_deposit_i32(", dst, ", ", dst, ", ", &tmp, ", "); OUT(c, locp, lo, ", ", &len, ");\n"); - - gen_rvalue_free(c, locp, &tmp); - gen_rvalue_free(c, locp, hi); - gen_rvalue_free(c, locp, lo); - gen_rvalue_free(c, locp, value); } =20 unsigned gen_if_cond(Context *c, YYLTYPE *locp, HexValue *cond) @@ -1999,7 +1880,6 @@ unsigned gen_if_cond(Context *c, YYLTYPE *locp, HexVa= lue *cond) bit_suffix =3D (cond->bit_width =3D=3D 64) ? "i64" : "i32"; OUT(c, locp, "tcg_gen_brcondi_", bit_suffix, "(TCG_COND_EQ, ", cond, ", 0, if_label_", &c->inst.if_count, ");\n"); - gen_rvalue_free(c, locp, cond); return c->inst.if_count++; } =20 @@ -2090,7 +1970,6 @@ static inline HexValue gen_rvalue_simple_unary(Contex= t *c, YYLTYPE *locp, res =3D gen_tmp(c, locp, bit_width, value->signedness); OUT(c, locp, tcg_code, "_i", &bit_width, "(", &res, ", ", value, ");\n"); - gen_rvalue_free(c, locp, value); } return res; } @@ -2116,7 +1995,6 @@ HexValue gen_rvalue_notl(Context *c, YYLTYPE *locp, H= exValue *value) OUT(c, locp, "tcg_gen_movcond_i", &bit_width); OUT(c, locp, "(TCG_COND_EQ, ", &res, ", ", value, ", ", &zero); OUT(c, locp, ", ", &one, ", ", &zero, ");\n"); - gen_rvalue_free(c, locp, value); } return res; } @@ -2147,7 +2025,6 @@ HexValue gen_rvalue_sat(Context *c, YYLTYPE *locp, He= xSat *sat, OUT(c, locp, &ovfl, ", ", &res, ", ", value, ", ", &width->imm.value, ");\n"); OUT(c, locp, "gen_set_usr_field_if(USR_OVF,", &ovfl, ");\n"); - gen_rvalue_free(c, locp, value); =20 return res; } @@ -2162,9 +2039,6 @@ HexValue gen_rvalue_fscr(Context *c, YYLTYPE *locp, H= exValue *value) OUT(c, locp, "tcg_gen_concat_i32_i64(", &key, ", ", &frame_key, ", ", &frame_key, ");\n"); OUT(c, locp, "tcg_gen_xor_i64(", &res, ", ", value, ", ", &key, ");\n"= ); - gen_rvalue_free(c, locp, &key); - gen_rvalue_free(c, locp, &frame_key); - gen_rvalue_free(c, locp, value); return res; } =20 @@ -2186,7 +2060,6 @@ HexValue gen_rvalue_brev(Context *c, YYLTYPE *locp, H= exValue *value) res =3D gen_tmp(c, locp, value->bit_width, value->signedness); *value =3D rvalue_materialize(c, locp, value); OUT(c, locp, "gen_helper_fbrev(", &res, ", ", value, ");\n"); - gen_rvalue_free(c, locp, value); return res; } =20 @@ -2198,7 +2071,6 @@ HexValue gen_rvalue_ternary(Context *c, YYLTYPE *locp= , HexValue *cond, unsigned bit_width =3D (is_64bit) ? 64 : 32; HexValue zero =3D gen_constant(c, locp, "0", bit_width, UNSIGNED); HexValue res =3D gen_tmp(c, locp, bit_width, UNSIGNED); - Ternary *ternary =3D NULL; =20 if (is_64bit) { *cond =3D gen_rvalue_extend(c, locp, cond); @@ -2216,13 +2088,8 @@ HexValue gen_rvalue_ternary(Context *c, YYLTYPE *loc= p, HexValue *cond, OUT(c, locp, ", ", true_branch, ", ", false_branch, ");\n"); =20 assert(c->ternary->len > 0); - ternary =3D &g_array_index(c->ternary, Ternary, c->ternary->len - 1); - gen_rvalue_free_manual(c, locp, &ternary->cond); g_array_remove_index(c->ternary, c->ternary->len - 1); =20 - gen_rvalue_free(c, locp, cond); - gen_rvalue_free(c, locp, true_branch); - gen_rvalue_free(c, locp, false_branch); return res; } =20 @@ -2301,15 +2168,6 @@ void track_string(Context *c, GString *s) g_array_append_val(c->inst.strings, s); } =20 -void free_variables(Context *c, YYLTYPE *locp) -{ - for (unsigned i =3D 0; i < c->inst.allocated->len; ++i) { - Var *var =3D &g_array_index(c->inst.allocated, Var, i); - const char *suffix =3D var->bit_width =3D=3D 64 ? "i64" : "i32"; - OUT(c, locp, "tcg_temp_free_", suffix, "(", var->name->str, ");\n"= ); - } -} - void free_instruction(Context *c) { assert(!is_inside_ternary(c)); diff --git a/target/hexagon/idef-parser/idef-parser.y b/target/hexagon/idef= -parser/idef-parser.y index c14cb39500..59c93f85b4 100644 --- a/target/hexagon/idef-parser/idef-parser.y +++ b/target/hexagon/idef-parser/idef-parser.y @@ -269,9 +269,6 @@ statements : statements statement statement : control_statement | var_decl ';' | rvalue ';' - { - gen_rvalue_free(c, &@1, &$1); - } | code_block | ';' ; @@ -347,7 +344,6 @@ assign_statement : lvalue '=3D' rvalue $3 =3D gen_rvalue_truncate(c, &@1, &$3); $3 =3D rvalue_materialize(c, &@1, &$3); OUT(c, &@1, "gen_write_new_pc(", &$3, ");\n"); - gen_rvalue_free(c, &@1, &$3); /* Free temporary val= ue */ } | LOAD '(' IMM ',' IMM ',' SIGN ',' var ',' lvalue ')' { @@ -376,7 +372,6 @@ assign_statement : lvalue '=3D' rvalue $3 =3D gen_rvalue_truncate(c, &@1, &$3); $3 =3D rvalue_materialize(c, &@1, &$3); OUT(c, &@1, "SET_USR_FIELD(USR_LPCFG, ", &$3, ");\n= "); - gen_rvalue_free(c, &@1, &$3); } | DEPOSIT '(' rvalue ',' rvalue ',' rvalue ')' { @@ -421,10 +416,6 @@ control_statement : frame_check ; =20 frame_check : FCHK '(' rvalue ',' rvalue ')' ';' - { - gen_rvalue_free(c, &@1, &$3); - gen_rvalue_free(c, &@1, &$5); - } ; =20 cancel_statement : LOAD_CANCEL @@ -774,7 +765,6 @@ rvalue : FAIL @1.last_column =3D @6.last_column; $$ =3D gen_tmp(c, &@1, 32, UNSIGNED); OUT(c, &@1, "gen_read_ireg(", &$$, ", ", &$3, ", ", &$6, ");\= n"); - gen_rvalue_free(c, &@1, &$3); } | CIRCADD '(' rvalue ',' rvalue ',' rvalue ')' { --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677476231; cv=none; d=zohomail.com; s=zohoarc; b=CcwO23GPwyAUUeCCQUH0F7f4Is4sZH3+LI3i/Gxj/1LXLXUXvbww6kSDUwdNL82fZvp3H4uwaOv2yFzp+HkOuwW0+QjAsUEv75mhRZd+zOoVEMiw7c4umwhS39QbRKTn/nx8Th0hGnGtlMMOumiyOuKCbR0Il578XFIwsE/FwrE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677476231; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+x4VXTBSHjkJ17E29ZUX+j7Q1yyitgbjfDCvsbqBOhY=; b=i0Nk8LOd4x0o8TdHcD91OpnEC6fnYUnm2EXL8EIuVJsI0vdMoxVcLGwWy9zJfHSapMYl2FOKixqKQ3zXI4osss/Ca486mBnf5+Jq3bPKLnMRKw6JRXPwTDFroT4cwZR2FCev8cCQAx9cYTiNsQ1WSMMFk85ZUouy8o2ymewFlsk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677476231052237.82988409717575; Sun, 26 Feb 2023 21:37:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW24-0008Vd-N0; Mon, 27 Feb 2023 00:26:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW1v-0008In-KD for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:26:31 -0500 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW1s-0007kn-Kv for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:26:31 -0500 Received: by mail-pj1-x1042.google.com with SMTP id h11-20020a17090a2ecb00b00237c740335cso3977337pjs.3 for ; Sun, 26 Feb 2023 21:26:28 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.26.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:26:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+x4VXTBSHjkJ17E29ZUX+j7Q1yyitgbjfDCvsbqBOhY=; b=G6Ie9lLEX+QUHBlmm7ymdhP0Y+aMant2l8Bg4XYNADDIntSeGH7UYmqlanHsfovo+a LbDaf7xYXnRawbaMmH3nEsPkX7p0H+b+GMg9A8ERcTHpzDpRfdc+zkn6ldSnBGrjePp8 t5b1Z1tzm6Owq3jsbOqZVLXY6P4U3kroUTURd1KNJQPiSfFI4sAJTH5AkNCS3adcEA/Y rsUh8BxTjC2+f8/gzKHtd0OXppHcyoDPBk98nOQCFTBKk1nnb7jlsVXGTyprFbiH/lp0 agBWM6dMMpjFoJRPyhnASB3LGzWOdhMqyxLhGUGc/Jb5Li48epx/PH7z182N0k1iRNaj MQmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+x4VXTBSHjkJ17E29ZUX+j7Q1yyitgbjfDCvsbqBOhY=; b=F8kke9SW7+nRnLNaplt4vEbGHVraeJSGwJlpXBGmQz04VsBLWWvCBz/0w9cJsPtJib gtrQ6aGHkZXz8/7m/BLzLBhlqTxJwN6PftTqIGTNM7nMbnDa9Tv1ft6DGlHmPzsgX2sE XIsUPjcU/7vWQSlfZFTMlpVjB2WQcEsZkvBHFqxz0vOhmNPXiACqv3bb1xTpjFJqaon6 JrZv4yoamlBEF+zIdVPettxQBi02LLIaLR2HjuEQNCP2BE6dbwtMOBjs8IIsjbIpRh+A FEWSh2rS/yNbb3Xjzu5wfxBjSMNcKqR0j8QUjxeMxHEC2CMqWCAWcTw5e/wsF/xaQtuQ vEjQ== X-Gm-Message-State: AO0yUKX14+AI8MKvWE6vOTg5KodR+XSxB7LtM6HxC2d5bsn5wHwOepb2 KA3mCgRhREL9Tkt26ucBNVJcKr5LW6G5y5+zTyUYbg== X-Google-Smtp-Source: AK7set99q7kWMYvmSQDIxS59NkYxQYRLN3967kRdH6EUMjnZbC+FvoEMUVMT3TIG0sKi5Zf4wX9How== X-Received: by 2002:a17:903:32cf:b0:19a:8e52:ce0 with SMTP id i15-20020a17090332cf00b0019a8e520ce0mr31213701plr.58.1677475587257; Sun, 26 Feb 2023 21:26:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 28/76] target/hexagon/idef-parser: Drop HexValue.is_manual Date: Sun, 26 Feb 2023 19:24:17 -1000 Message-Id: <20230227052505.352889-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476233205100001 Content-Type: text/plain; charset="utf-8" This field is no longer used. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Taylor Simpson --- target/hexagon/idef-parser/idef-parser.h | 1 - target/hexagon/idef-parser/parser-helpers.c | 15 --------------- target/hexagon/idef-parser/idef-parser.y | 2 -- 3 files changed, 18 deletions(-) diff --git a/target/hexagon/idef-parser/idef-parser.h b/target/hexagon/idef= -parser/idef-parser.h index 5c49d4da3e..17d2ebfaf6 100644 --- a/target/hexagon/idef-parser/idef-parser.h +++ b/target/hexagon/idef-parser/idef-parser.h @@ -185,7 +185,6 @@ typedef struct HexValue { unsigned bit_width; /**< Bit width of the rvalue = */ HexSignedness signedness; /**< Unsigned flag for the rvalue = */ bool is_dotnew; /**< rvalue of predicate type is dotnew? = */ - bool is_manual; /**< Opt out of automatic freeing of param= s */ } HexValue; =20 /** diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/i= def-parser/parser-helpers.c index bdbb8b6a5f..0b401f7dbe 100644 --- a/target/hexagon/idef-parser/parser-helpers.c +++ b/target/hexagon/idef-parser/parser-helpers.c @@ -278,7 +278,6 @@ static HexValue gen_constant(Context *c, rvalue.bit_width =3D bit_width; rvalue.signedness =3D signedness; rvalue.is_dotnew =3D false; - rvalue.is_manual =3D true; rvalue.tmp.index =3D c->inst.tmp_count; OUT(c, locp, "TCGv_i", &bit_width, " tmp_", &c->inst.tmp_count, " =3D tcg_constant_i", &bit_width, "(", value, ");\n"); @@ -299,7 +298,6 @@ HexValue gen_tmp(Context *c, rvalue.bit_width =3D bit_width; rvalue.signedness =3D signedness; rvalue.is_dotnew =3D false; - rvalue.is_manual =3D false; rvalue.tmp.index =3D c->inst.tmp_count; OUT(c, locp, "TCGv_i", &bit_width, " tmp_", &c->inst.tmp_count, " =3D tcg_temp_new_i", &bit_width, "();\n"); @@ -320,7 +318,6 @@ HexValue gen_tmp_value(Context *c, rvalue.bit_width =3D bit_width; rvalue.signedness =3D signedness; rvalue.is_dotnew =3D false; - rvalue.is_manual =3D false; rvalue.tmp.index =3D c->inst.tmp_count; OUT(c, locp, "TCGv_i", &bit_width, " tmp_", &c->inst.tmp_count, " =3D tcg_const_i", &bit_width, "(", value, ");\n"); @@ -339,7 +336,6 @@ static HexValue gen_tmp_value_from_imm(Context *c, rvalue.bit_width =3D value->bit_width; rvalue.signedness =3D value->signedness; rvalue.is_dotnew =3D false; - rvalue.is_manual =3D false; rvalue.tmp.index =3D c->inst.tmp_count; /* * Here we output the call to `tcg_const_i` in @@ -375,7 +371,6 @@ HexValue gen_imm_value(Context *c __attribute__((unused= )), rvalue.bit_width =3D bit_width; rvalue.signedness =3D signedness; rvalue.is_dotnew =3D false; - rvalue.is_manual =3D false; rvalue.imm.type =3D VALUE; rvalue.imm.value =3D value; return rvalue; @@ -390,7 +385,6 @@ HexValue gen_imm_qemu_tmp(Context *c, YYLTYPE *locp, un= signed bit_width, memset(&rvalue, 0, sizeof(HexValue)); rvalue.type =3D IMMEDIATE; rvalue.is_dotnew =3D false; - rvalue.is_manual =3D false; rvalue.bit_width =3D bit_width; rvalue.signedness =3D signedness; rvalue.imm.type =3D QEMU_TMP; @@ -1242,15 +1236,12 @@ void gen_rdeposit_op(Context *c, */ k64 =3D gen_bin_op(c, locp, SUB_OP, &k64, &width_m); mask =3D gen_bin_op(c, locp, LSR_OP, &mask, &k64); - begin_m.is_manual =3D true; mask =3D gen_bin_op(c, locp, ASL_OP, &mask, &begin_m); - mask.is_manual =3D true; value_m =3D gen_bin_op(c, locp, ASL_OP, &value_m, &begin_m); value_m =3D gen_bin_op(c, locp, ANDB_OP, &value_m, &mask); =20 OUT(c, locp, "tcg_gen_not_i", &dst->bit_width, "(", &mask, ", ", &mask, ");\n"); - mask.is_manual =3D false; res =3D gen_bin_op(c, locp, ANDB_OP, dst, &mask); res =3D gen_bin_op(c, locp, ORB_OP, &res, &value_m); =20 @@ -1410,8 +1401,6 @@ HexValue gen_convround(Context *c, HexValue and; HexValue src_p1; =20 - src_m.is_manual =3D true; - and =3D gen_bin_op(c, locp, ANDB_OP, &src_m, &mask); src_p1 =3D gen_bin_op(c, locp, ADD_OP, &src_m, &one); =20 @@ -1569,10 +1558,6 @@ HexValue gen_round(Context *c, b =3D gen_extend_op(c, locp, &src_width, 64, pos, UNSIGNED); b =3D rvalue_materialize(c, locp, &b); =20 - /* Disable auto-free of values used more than once */ - a.is_manual =3D true; - b.is_manual =3D true; - n_m1 =3D gen_bin_op(c, locp, SUB_OP, &b, &one); shifted =3D gen_bin_op(c, locp, ASL_OP, &one, &n_m1); sum =3D gen_bin_op(c, locp, ADD_OP, &shifted, &a); diff --git a/target/hexagon/idef-parser/idef-parser.y b/target/hexagon/idef= -parser/idef-parser.y index 59c93f85b4..fae291e5f8 100644 --- a/target/hexagon/idef-parser/idef-parser.y +++ b/target/hexagon/idef-parser/idef-parser.y @@ -534,7 +534,6 @@ rvalue : FAIL rvalue.imm.type =3D IMM_CONSTEXT; rvalue.signedness =3D UNSIGNED; rvalue.is_dotnew =3D false; - rvalue.is_manual =3D false; $$ =3D rvalue; } | var @@ -693,7 +692,6 @@ rvalue : FAIL } | rvalue '?' { - $1.is_manual =3D true; Ternary t =3D { 0 }; t.state =3D IN_LEFT; t.cond =3D $1; --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677476883; cv=none; d=zohomail.com; s=zohoarc; b=lyTNjR79xngVq6w7ugEgmOUnjdq3CMITJPoVz2+qb81L/CDpxEKFeVboMatfn/+vDfemzV5NHjn9YgX8wfTIgDvMmkBFf6NSxE4V/I4YWR0FAMe4QHPShZAGY0e76HS05ksqSpzSLUOnIh5F9pU1WNITdrovQR8Qny8qrbYyGHU= ARC-Message-Signature: i=1; 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Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/hppa/translate.c | 93 +---------------------------------------- 1 file changed, 1 insertion(+), 92 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index cee960949f..cb4fd1fd62 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -35,12 +35,10 @@ #undef TCGv #undef tcg_temp_new #undef tcg_global_mem_new -#undef tcg_temp_free =20 #if TARGET_LONG_BITS =3D=3D 64 #define TCGv_tl TCGv_i64 #define tcg_temp_new_tl tcg_temp_new_i64 -#define tcg_temp_free_tl tcg_temp_free_i64 #if TARGET_REGISTER_BITS =3D=3D 64 #define tcg_gen_extu_reg_tl tcg_gen_mov_i64 #else @@ -49,7 +47,6 @@ #else #define TCGv_tl TCGv_i32 #define tcg_temp_new_tl tcg_temp_new_i32 -#define tcg_temp_free_tl tcg_temp_free_i32 #define tcg_gen_extu_reg_tl tcg_gen_mov_i32 #endif =20 @@ -58,7 +55,6 @@ =20 #define tcg_temp_new tcg_temp_new_i64 #define tcg_global_mem_new tcg_global_mem_new_i64 -#define tcg_temp_free tcg_temp_free_i64 =20 #define tcg_gen_movi_reg tcg_gen_movi_i64 #define tcg_gen_mov_reg tcg_gen_mov_i64 @@ -153,7 +149,6 @@ #define TCGv_reg TCGv_i32 #define tcg_temp_new tcg_temp_new_i32 #define tcg_global_mem_new tcg_global_mem_new_i32 -#define tcg_temp_free tcg_temp_free_i32 =20 #define tcg_gen_movi_reg tcg_gen_movi_i32 #define tcg_gen_mov_reg tcg_gen_mov_i32 @@ -488,10 +483,6 @@ static void cond_free(DisasCond *cond) { switch (cond->c) { default: - if (cond->a0 !=3D cpu_psw_n) { - tcg_temp_free(cond->a0); - } - tcg_temp_free(cond->a1); cond->a0 =3D NULL; cond->a1 =3D NULL; /* fallthru */ @@ -1021,7 +1012,6 @@ static DisasCond do_unit_cond(unsigned cf, TCGv_reg r= es, tcg_gen_and_reg(tmp, in1, in2); tcg_gen_andc_reg(cb, cb, res); tcg_gen_or_reg(cb, cb, tmp); - tcg_temp_free(tmp); } =20 switch (cf >> 1) { @@ -1040,7 +1030,6 @@ static DisasCond do_unit_cond(unsigned cf, TCGv_reg r= es, tcg_gen_andc_reg(tmp, tmp, res); tcg_gen_andi_reg(tmp, tmp, 0x80808080u); cond =3D cond_make_0(TCG_COND_NE, tmp); - tcg_temp_free(tmp); break; =20 case 3: /* SHZ / NHZ */ @@ -1049,7 +1038,6 @@ static DisasCond do_unit_cond(unsigned cf, TCGv_reg r= es, tcg_gen_andc_reg(tmp, tmp, res); tcg_gen_andi_reg(tmp, tmp, 0x80008000u); cond =3D cond_make_0(TCG_COND_NE, tmp); - tcg_temp_free(tmp); break; =20 case 4: /* SDC / NDC */ @@ -1070,9 +1058,6 @@ static DisasCond do_unit_cond(unsigned cf, TCGv_reg r= es, default: g_assert_not_reached(); } - if (cf & 8) { - tcg_temp_free(cb); - } if (cf & 1) { cond.c =3D tcg_invert_cond(cond.c); } @@ -1090,7 +1075,6 @@ static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg= res, tcg_gen_xor_reg(sv, res, in1); tcg_gen_xor_reg(tmp, in1, in2); tcg_gen_andc_reg(sv, sv, tmp); - tcg_temp_free(tmp); =20 return sv; } @@ -1105,7 +1089,6 @@ static TCGv_reg do_sub_sv(DisasContext *ctx, TCGv_reg= res, tcg_gen_xor_reg(sv, res, in1); tcg_gen_xor_reg(tmp, in1, in2); tcg_gen_and_reg(sv, sv, tmp); - tcg_temp_free(tmp); =20 return sv; } @@ -1163,7 +1146,6 @@ static void do_add(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, tmp =3D tcg_temp_new(); tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(cpu_env, tmp); - tcg_temp_free(tmp); } =20 /* Write back the result. */ @@ -1172,7 +1154,6 @@ static void do_add(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, save_or_nullify(ctx, cpu_psw_cb_msb, cb_msb); } save_gpr(ctx, rt, dest); - tcg_temp_free(dest); =20 /* Install the new nullification. */ cond_free(&ctx->null_cond); @@ -1257,16 +1238,12 @@ static void do_sub(DisasContext *ctx, unsigned rt, = TCGv_reg in1, tmp =3D tcg_temp_new(); tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(cpu_env, tmp); - tcg_temp_free(tmp); } =20 /* Write back the result. */ save_or_nullify(ctx, cpu_psw_cb, cb); save_or_nullify(ctx, cpu_psw_cb_msb, cb_msb); save_gpr(ctx, rt, dest); - tcg_temp_free(dest); - tcg_temp_free(cb); - tcg_temp_free(cb_msb); =20 /* Install the new nullification. */ cond_free(&ctx->null_cond); @@ -1321,7 +1298,6 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt,= TCGv_reg in1, /* Clear. */ tcg_gen_movi_reg(dest, 0); save_gpr(ctx, rt, dest); - tcg_temp_free(dest); =20 /* Install the new nullification. */ cond_free(&ctx->null_cond); @@ -1381,7 +1357,6 @@ static void do_unit(DisasContext *ctx, unsigned rt, T= CGv_reg in1, TCGv_reg tmp =3D tcg_temp_new(); tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(cpu_env, tmp); - tcg_temp_free(tmp); } save_gpr(ctx, rt, dest); =20 @@ -1420,11 +1395,9 @@ static TCGv_i64 space_select(DisasContext *ctx, int = sp, TCGv_reg base) tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5); tcg_gen_andi_reg(tmp, tmp, 030); tcg_gen_trunc_reg_ptr(ptr, tmp); - tcg_temp_free(tmp); =20 tcg_gen_add_ptr(ptr, ptr, cpu_env); tcg_gen_ld_i64(spc, ptr, offsetof(CPUHPPAState, sr[4])); - tcg_temp_free_ptr(ptr); =20 return spc; } @@ -1582,7 +1555,6 @@ static bool do_floadw(DisasContext *ctx, unsigned rt,= unsigned rb, tmp =3D tcg_temp_new_i32(); do_load_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL); save_frw_i32(rt, tmp); - tcg_temp_free_i32(tmp); =20 if (rt =3D=3D 0) { gen_helper_loaded_fr0(cpu_env); @@ -1608,7 +1580,6 @@ static bool do_floadd(DisasContext *ctx, unsigned rt,= unsigned rb, tmp =3D tcg_temp_new_i64(); do_load_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUQ); save_frd(rt, tmp); - tcg_temp_free_i64(tmp); =20 if (rt =3D=3D 0) { gen_helper_loaded_fr0(cpu_env); @@ -1642,7 +1613,6 @@ static bool do_fstorew(DisasContext *ctx, unsigned rt= , unsigned rb, =20 tmp =3D load_frw_i32(rt); do_store_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL); - tcg_temp_free_i32(tmp); =20 return nullify_end(ctx); } @@ -1663,7 +1633,6 @@ static bool do_fstored(DisasContext *ctx, unsigned rt= , unsigned rb, =20 tmp =3D load_frd(rt); do_store_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUQ); - tcg_temp_free_i64(tmp); =20 return nullify_end(ctx); } @@ -1685,7 +1654,6 @@ static bool do_fop_wew(DisasContext *ctx, unsigned rt= , unsigned ra, func(tmp, cpu_env, tmp); =20 save_frw_i32(rt, tmp); - tcg_temp_free_i32(tmp); return nullify_end(ctx); } =20 @@ -1701,9 +1669,7 @@ static bool do_fop_wed(DisasContext *ctx, unsigned rt= , unsigned ra, =20 func(dst, cpu_env, src); =20 - tcg_temp_free_i64(src); save_frw_i32(rt, dst); - tcg_temp_free_i32(dst); return nullify_end(ctx); } =20 @@ -1718,7 +1684,6 @@ static bool do_fop_ded(DisasContext *ctx, unsigned rt= , unsigned ra, func(tmp, cpu_env, tmp); =20 save_frd(rt, tmp); - tcg_temp_free_i64(tmp); return nullify_end(ctx); } =20 @@ -1734,9 +1699,7 @@ static bool do_fop_dew(DisasContext *ctx, unsigned rt= , unsigned ra, =20 func(dst, cpu_env, src); =20 - tcg_temp_free_i32(src); save_frd(rt, dst); - tcg_temp_free_i64(dst); return nullify_end(ctx); } =20 @@ -1752,9 +1715,7 @@ static bool do_fop_weww(DisasContext *ctx, unsigned r= t, =20 func(a, cpu_env, a, b); =20 - tcg_temp_free_i32(b); save_frw_i32(rt, a); - tcg_temp_free_i32(a); return nullify_end(ctx); } =20 @@ -1770,9 +1731,7 @@ static bool do_fop_dedd(DisasContext *ctx, unsigned r= t, =20 func(a, cpu_env, a, b); =20 - tcg_temp_free_i64(b); save_frd(rt, a); - tcg_temp_free_i64(a); return nullify_end(ctx); } =20 @@ -2098,8 +2057,6 @@ static bool trans_mfsp(DisasContext *ctx, arg_mfsp *a) tcg_gen_trunc_i64_reg(t1, t0); =20 save_gpr(ctx, rt, t1); - tcg_temp_free(t1); - tcg_temp_free_i64(t0); =20 cond_free(&ctx->null_cond); return true; @@ -2176,7 +2133,6 @@ static bool trans_mtsp(DisasContext *ctx, arg_mtsp *a) } else { tcg_gen_mov_i64(cpu_sr[rs], t64); } - tcg_temp_free_i64(t64); =20 return nullify_end(ctx); } @@ -2192,7 +2148,6 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl = *a) tmp =3D tcg_temp_new(); tcg_gen_andi_reg(tmp, reg, TARGET_REGISTER_BITS - 1); save_or_nullify(ctx, cpu_sar, tmp); - tcg_temp_free(tmp); =20 cond_free(&ctx->null_cond); return true; @@ -2254,7 +2209,6 @@ static bool trans_mtsarcm(DisasContext *ctx, arg_mtsa= rcm *a) tcg_gen_not_reg(tmp, load_gpr(ctx, a->r)); tcg_gen_andi_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); save_or_nullify(ctx, cpu_sar, tmp); - tcg_temp_free(tmp); =20 cond_free(&ctx->null_cond); return true; @@ -2273,8 +2227,6 @@ static bool trans_ldsid(DisasContext *ctx, arg_ldsid = *a) tcg_gen_mov_i64(t0, space_select(ctx, a->sp, load_gpr(ctx, a->b))); tcg_gen_shri_i64(t0, t0, 32); tcg_gen_trunc_i64_reg(dest, t0); - - tcg_temp_free_i64(t0); #endif save_gpr(ctx, a->t, dest); =20 @@ -2437,8 +2389,6 @@ static bool trans_probe(DisasContext *ctx, arg_probe = *a) =20 gen_helper_probe(dest, cpu_env, addr, level, want); =20 - tcg_temp_free_i32(level); - save_gpr(ctx, a->t, dest); return nullify_end(ctx); } @@ -2530,8 +2480,6 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtl= bxf *a) : offsetof(CPUHPPAState, cr[CR_IIAOQ])); tcg_gen_shli_i64(stl, stl, 32); tcg_gen_or_tl(addr, atl, stl); - tcg_temp_free_tl(atl); - tcg_temp_free_tl(stl); =20 reg =3D load_gpr(ctx, a->r); if (a->addr) { @@ -2539,7 +2487,6 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtl= bxf *a) } else { gen_helper_itlbp(cpu_env, addr, reg); } - tcg_temp_free_tl(addr); =20 /* Exit TB for TLB change if mmu is enabled. */ if (ctx->tb_flags & PSW_C) { @@ -2568,7 +2515,6 @@ static bool trans_lpa(DisasContext *ctx, arg_ldst *a) save_gpr(ctx, a->b, ofs); } save_gpr(ctx, a->t, paddr); - tcg_temp_free(paddr); =20 return nullify_end(ctx); #endif @@ -2819,8 +2765,6 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) tcg_gen_add2_i32(dest, cpu_psw_cb_msb, add1, zero, add2, zero); tcg_gen_add2_i32(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zer= o); =20 - tcg_temp_free(addc); - /* Write back the result register. */ save_gpr(ctx, a->t, dest); =20 @@ -2842,10 +2786,6 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *= a) ctx->null_cond =3D do_cond(a->cf, dest, cpu_psw_cb_msb, sv); } =20 - tcg_temp_free(add1); - tcg_temp_free(add2); - tcg_temp_free(dest); - return nullify_end(ctx); } =20 @@ -3100,7 +3040,6 @@ static bool do_addb(DisasContext *ctx, unsigned r, TC= Gv_reg in1, =20 cond =3D do_cond(c * 2 + f, dest, cb_msb, sv); save_gpr(ctx, r, dest); - tcg_temp_free(dest); return do_cbranch(ctx, disp, n, &cond); } =20 @@ -3128,7 +3067,6 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sa= r *a) tcg_gen_shl_reg(tmp, tcg_r, cpu_sar); =20 cond =3D cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); - tcg_temp_free(tmp); return do_cbranch(ctx, a->disp, a->n, &cond); } =20 @@ -3144,7 +3082,6 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_im= m *a) tcg_gen_shli_reg(tmp, tcg_r, a->p); =20 cond =3D cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); - tcg_temp_free(tmp); return do_cbranch(ctx, a->disp, a->n, &cond); } =20 @@ -3197,7 +3134,6 @@ static bool trans_shrpw_sar(DisasContext *ctx, arg_sh= rpw_sar *a) tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2)); tcg_gen_rotr_i32(t32, t32, cpu_sar); tcg_gen_extu_i32_reg(dest, t32); - tcg_temp_free_i32(t32); } else { TCGv_i64 t =3D tcg_temp_new_i64(); TCGv_i64 s =3D tcg_temp_new_i64(); @@ -3206,9 +3142,6 @@ static bool trans_shrpw_sar(DisasContext *ctx, arg_sh= rpw_sar *a) tcg_gen_extu_reg_i64(s, cpu_sar); tcg_gen_shr_i64(t, t, s); tcg_gen_trunc_i64_reg(dest, t); - - tcg_temp_free_i64(t); - tcg_temp_free_i64(s); } save_gpr(ctx, a->t, dest); =20 @@ -3240,13 +3173,11 @@ static bool trans_shrpw_imm(DisasContext *ctx, arg_= shrpw_imm *a) tcg_gen_trunc_reg_i32(t32, t2); tcg_gen_rotri_i32(t32, t32, sa); tcg_gen_extu_i32_reg(dest, t32); - tcg_temp_free_i32(t32); } else { TCGv_i64 t64 =3D tcg_temp_new_i64(); tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]); tcg_gen_shri_i64(t64, t64, sa); tcg_gen_trunc_i64_reg(dest, t64); - tcg_temp_free_i64(t64); } save_gpr(ctx, a->t, dest); =20 @@ -3280,7 +3211,6 @@ static bool trans_extrw_sar(DisasContext *ctx, arg_ex= trw_sar *a) tcg_gen_shr_reg(dest, src, tmp); tcg_gen_extract_reg(dest, dest, 0, len); } - tcg_temp_free(tmp); save_gpr(ctx, a->t, dest); =20 /* Install the new nullification. */ @@ -3410,9 +3340,6 @@ static bool do_depw_sar(DisasContext *ctx, unsigned r= t, unsigned c, } else { tcg_gen_shl_reg(dest, tmp, shift); } - tcg_temp_free(shift); - tcg_temp_free(mask); - tcg_temp_free(tmp); save_gpr(ctx, rt, dest); =20 /* Install the new nullification. */ @@ -3487,7 +3414,6 @@ static bool trans_be(DisasContext *ctx, arg_be *a) tcg_gen_mov_i64(cpu_iasq_b, new_spc); nullify_set(ctx, a->n); } - tcg_temp_free_i64(new_spc); tcg_gen_lookup_and_goto_ptr(); ctx->base.is_jmp =3D DISAS_NORETURN; return nullify_end(ctx); @@ -3876,9 +3802,6 @@ static bool trans_fcmp_f(DisasContext *ctx, arg_fclas= s2 *a) =20 gen_helper_fcmp_s(cpu_env, ta, tb, ty, tc); =20 - tcg_temp_free_i32(ta); - tcg_temp_free_i32(tb); - return nullify_end(ctx); } =20 @@ -3896,9 +3819,6 @@ static bool trans_fcmp_d(DisasContext *ctx, arg_fclas= s2 *a) =20 gen_helper_fcmp_d(cpu_env, ta, tb, ty, tc); =20 - tcg_temp_free_i64(ta); - tcg_temp_free_i64(tb); - return nullify_end(ctx); } =20 @@ -3958,7 +3878,6 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest = *a) =20 tcg_gen_extract_reg(t, t, 21 - cbit, 1); ctx->null_cond =3D cond_make_0(TCG_COND_NE, t); - tcg_temp_free(t); } =20 done: @@ -4019,8 +3938,6 @@ static bool trans_xmpyu(DisasContext *ctx, arg_xmpyu = *a) y =3D load_frw0_i64(a->r2); tcg_gen_mul_i64(x, x, y); save_frd(a->t, x); - tcg_temp_free_i64(x); - tcg_temp_free_i64(y); =20 return nullify_end(ctx); } @@ -4094,10 +4011,7 @@ static bool trans_fmpyfadd_f(DisasContext *ctx, arg_= fmpyfadd_f *a) gen_helper_fmpyfadd_s(x, cpu_env, x, y, z); } =20 - tcg_temp_free_i32(y); - tcg_temp_free_i32(z); save_frw_i32(a->t, x); - tcg_temp_free_i32(x); return nullify_end(ctx); } =20 @@ -4116,10 +4030,7 @@ static bool trans_fmpyfadd_d(DisasContext *ctx, arg_= fmpyfadd_d *a) gen_helper_fmpyfadd_d(x, cpu_env, x, y, z); } =20 - tcg_temp_free_i64(y); - tcg_temp_free_i64(z); save_frd(a->t, x); - tcg_temp_free_i64(x); return nullify_end(ctx); } =20 @@ -4234,13 +4145,11 @@ static void hppa_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cs) } } =20 - /* Free any temporaries allocated. */ + /* Forget any temporaries allocated. */ for (i =3D 0, n =3D ctx->ntempr; i < n; ++i) { - tcg_temp_free(ctx->tempr[i]); ctx->tempr[i] =3D NULL; } for (i =3D 0, n =3D ctx->ntempl; i < n; ++i) { - tcg_temp_free_tl(ctx->templ[i]); ctx->templ[i] =3D NULL; } ctx->ntempr =3D 0; --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.26.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:26:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oRXjTp+TXfW0C5esl+Zugvmwem8SqRIai2YjZ7FQqDw=; b=IaDMnUfSpDyZf2gVFTRpcpj1HmN9PuUZYpRvelzakPf1zd2p9vl/+pgZQJ6usCkjsv RilHP9KdnJBIwBEYCZwYZ9MKCSrzN6uzgy3JG9OKjIbcNcAGTGWJhudrOav0HFx3eKIY 1+lvNGQi0ODjmog9tjYLPdVPN/fi9HXAMN6Y33ggnJYuAUuUW+dmAChvzCMeVpBBbwuP q6m0RngJOP8WDsXO4Nbl6ERQ1l0WuSMNEqqpdJPwG4a4rQ3cjrgrFGrKjHWPHpSdXlcZ mG2BdV+Qhsx809PIoNQH0xEdMvUQKsAh19CtWUO1KVvg1/eJhslcOgMBvElB2LiutfSC lXIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oRXjTp+TXfW0C5esl+Zugvmwem8SqRIai2YjZ7FQqDw=; b=Ri/Pkz3lESWvfJvK+aGtimZtsiApxax6BTf9XAw70qRpohrl1eJq5vXzpBHFcStYov /iN7wdP/Ne1cKuE81QrWRreR6HUVlpgn17ZUcB1fsIHJfvgqbVv/xokPa+lBUaA000rn JqOrg6k0/gCtWZEGXSSSD1KqQQTEpP0w8y71K5pbzmoTXticpx6HsOf8KFsoTezOlAgG Ld2EhWi+4j+Ijqg6bcMcsEo5yclPMi2p2MIz1x0AWCNo5iWHngxUfjeO4JQDDmpth4t8 7Djth1NxJ4VY4uhU5AUci+ZRWeSd9Eg3CoQRly2mTSGln9vqbuokT8q3IWahqdnQGdE4 lO9g== X-Gm-Message-State: AO0yUKU0/EKdmGvx3P5bcuFPxo1b1dRQYk9tWp4qzYzGHUVAwBQHMeea QEkU0BC9YMA1HH0LiJNYS+HGuca6aYd126Hk7HEnsg== X-Google-Smtp-Source: AK7set8ly18mIeAVUA5DhLkvciKB8cTkUjcyvY//+4dCDtnR/IZ9XCTboZNTCXaF9XAGZP6Ab8fxrQ== X-Received: by 2002:a17:902:e5d2:b0:19c:ff5d:1fd2 with SMTP id u18-20020a170902e5d200b0019cff5d1fd2mr5214788plf.8.1677475592648; Sun, 26 Feb 2023 21:26:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 30/76] target/i386: Drop tcg_temp_free Date: Sun, 26 Feb 2023 19:24:19 -1000 Message-Id: <20230227052505.352889-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x641.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476249200100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/i386/tcg/translate.c | 41 -------------------------------- target/i386/tcg/decode-new.c.inc | 15 ------------ target/i386/tcg/emit.c.inc | 6 ----- 3 files changed, 62 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index baf1cfc2bc..692f0c63a8 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -899,10 +899,6 @@ static void gen_compute_eflags(DisasContext *s) gen_update_cc_op(s); gen_helper_cc_compute_all(cpu_cc_src, dst, src1, src2, cpu_cc_op); set_cc_op(s, CC_OP_EFLAGS); - - if (dead) { - tcg_temp_free(zero); - } } =20 typedef struct CCPrepare { @@ -1650,7 +1646,6 @@ static void gen_shift_flags(DisasContext *s, MemOp ot= , TCGv result, } else { tcg_gen_mov_tl(cpu_cc_src, shm1); } - tcg_temp_free(z_tl); =20 /* Get the two potential CC_OP values into temporaries. */ tcg_gen_movi_i32(s->tmp2_i32, (is_right ? CC_OP_SARB : CC_OP_SHLB) + o= t); @@ -1666,8 +1661,6 @@ static void gen_shift_flags(DisasContext *s, MemOp ot= , TCGv result, s32 =3D tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(s32, count); tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, s32, z32, s->tmp2_i32, old= op); - tcg_temp_free_i32(z32); - tcg_temp_free_i32(s32); =20 /* The CC_OP value is no longer predictable. */ set_cc_op(s, CC_OP_DYNAMIC); @@ -1827,8 +1820,6 @@ static void gen_rot_rm_T1(DisasContext *s, MemOp ot, = int op1, int is_right) tcg_gen_movi_i32(s->tmp3_i32, CC_OP_EFLAGS); tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, t1, t0, s->tmp2_i32, s->tmp3_i32); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); =20 /* The CC_OP value is no longer predictable. */=20 set_cc_op(s, CC_OP_DYNAMIC); @@ -2049,7 +2040,6 @@ static void gen_shiftd_rm_T1(DisasContext *s, MemOp o= t, int op1, gen_op_st_rm_T0_A0(s, ot, op1); =20 gen_shift_flags(s, ot, s->T0, s->tmp0, count, is_right); - tcg_temp_free(count); } =20 static void gen_shift(DisasContext *s1, int op, MemOp ot, int d, int s) @@ -2513,13 +2503,6 @@ static void gen_cmovcc1(CPUX86State *env, DisasConte= xt *s, MemOp ot, int b, tcg_gen_movcond_tl(cc.cond, s->T0, cc.reg, cc.reg2, s->T0, cpu_regs[reg]); gen_op_mov_reg_v(s, ot, reg, s->T0); - - if (cc.mask !=3D -1) { - tcg_temp_free(cc.reg); - } - if (!cc.use_reg2) { - tcg_temp_free(cc.reg2); - } } =20 static inline void gen_op_movl_T0_seg(DisasContext *s, X86Seg seg_reg) @@ -2748,7 +2731,6 @@ static void gen_set_hflag(DisasContext *s, uint32_t m= ask) tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags)); tcg_gen_ori_i32(t, t, mask); tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags)); - tcg_temp_free_i32(t); s->flags |=3D mask; } } @@ -2760,7 +2742,6 @@ static void gen_reset_hflag(DisasContext *s, uint32_t= mask) tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags)); tcg_gen_andi_i32(t, t, ~mask); tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags)); - tcg_temp_free_i32(t); s->flags &=3D ~mask; } } @@ -2772,7 +2753,6 @@ static void gen_set_eflags(DisasContext *s, target_ul= ong mask) tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, eflags)); tcg_gen_ori_tl(t, t, mask); tcg_gen_st_tl(t, cpu_env, offsetof(CPUX86State, eflags)); - tcg_temp_free(t); } =20 static void gen_reset_eflags(DisasContext *s, target_ulong mask) @@ -2782,7 +2762,6 @@ static void gen_reset_eflags(DisasContext *s, target_= ulong mask) tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, eflags)); tcg_gen_andi_tl(t, t, ~mask); tcg_gen_st_tl(t, cpu_env, offsetof(CPUX86State, eflags)); - tcg_temp_free(t); } =20 /* Clear BND registers during legacy branches. */ @@ -3015,13 +2994,11 @@ static void gen_cmpxchg8b(DisasContext *s, CPUX86St= ate *env, int modrm) tcg_gen_nonatomic_cmpxchg_i64(old, s->A0, cmp, val, s->mem_index, MO_TEUQ); } - tcg_temp_free_i64(val); =20 /* Set tmp0 to match the required value of Z. */ tcg_gen_setcond_i64(TCG_COND_EQ, cmp, old, cmp); Z =3D tcg_temp_new(); tcg_gen_trunc_i64_tl(Z, cmp); - tcg_temp_free_i64(cmp); =20 /* * Extract the result values for the register pair. @@ -3042,12 +3019,10 @@ static void gen_cmpxchg8b(DisasContext *s, CPUX86St= ate *env, int modrm) tcg_gen_movcond_tl(TCG_COND_EQ, cpu_regs[R_EDX], Z, zero, s->T1, cpu_regs[R_EDX]); } - tcg_temp_free_i64(old); =20 /* Update Z. */ gen_compute_eflags(s); tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, Z, ctz32(CC_Z), 1); - tcg_temp_free(Z); } =20 #ifdef TARGET_X86_64 @@ -3072,8 +3047,6 @@ static void gen_cmpxchg16b(DisasContext *s, CPUX86Sta= te *env, int modrm) } =20 tcg_gen_extr_i128_i64(s->T0, s->T1, val); - tcg_temp_free_i128(cmp); - tcg_temp_free_i128(val); =20 /* Determine success after the fact. */ t0 =3D tcg_temp_new_i64(); @@ -3081,13 +3054,11 @@ static void gen_cmpxchg16b(DisasContext *s, CPUX86S= tate *env, int modrm) tcg_gen_xor_i64(t0, s->T0, cpu_regs[R_EAX]); tcg_gen_xor_i64(t1, s->T1, cpu_regs[R_EDX]); tcg_gen_or_i64(t0, t0, t1); - tcg_temp_free_i64(t1); =20 /* Update Z. */ gen_compute_eflags(s); tcg_gen_setcondi_i64(TCG_COND_EQ, t0, t0, 0); tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, t0, ctz32(CC_Z), 1); - tcg_temp_free_i64(t0); =20 /* * Extract the result values for the register pair. We may do this @@ -3437,10 +3408,8 @@ static bool disas_insn(DisasContext *s, CPUState *cp= u) tcg_gen_neg_tl(t1, t0); tcg_gen_atomic_cmpxchg_tl(t0, a0, t0, t1, s->mem_index, ot | MO_LE); - tcg_temp_free(t1); tcg_gen_brcond_tl(TCG_COND_NE, t0, t2, label1); =20 - tcg_temp_free(t2); tcg_gen_neg_tl(s->T0, t0); } else { tcg_gen_neg_tl(s->T0, s->T0); @@ -3927,9 +3896,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) tcg_gen_mov_tl(s->cc_srcT, cmpv); tcg_gen_sub_tl(cpu_cc_dst, cmpv, oldv); set_cc_op(s, CC_OP_SUBB + ot); - tcg_temp_free(oldv); - tcg_temp_free(newv); - tcg_temp_free(cmpv); } break; case 0x1c7: /* cmpxchg8b */ @@ -4380,7 +4346,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (shift) { TCGv imm =3D tcg_const_tl(x86_ldub_code(env, s)); gen_shiftd_rm_T1(s, ot, opreg, op, imm); - tcg_temp_free(imm); } else { gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]); } @@ -4614,7 +4579,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) tcg_gen_st_tl(last_addr, cpu_env, offsetof(CPUX86State, fpdp)); } - tcg_temp_free(last_addr); } else { /* register float ops */ opreg =3D rm; @@ -6279,9 +6243,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_compute_eflags(s); tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z); tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2); - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } break; case 0x102: /* lar */ @@ -6308,7 +6269,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_op_mov_reg_v(s, ot, reg, t0); gen_set_label(label1); set_cc_op(s, CC_OP_EFLAGS); - tcg_temp_free(t0); } break; case 0x118: @@ -6353,7 +6313,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) TCGv_i64 notu =3D tcg_temp_new_i64(); tcg_gen_not_i64(notu, cpu_bndu[reg]); gen_bndck(env, s, modrm, TCG_COND_GTU, notu); - tcg_temp_free_i64(notu); } else if (prefixes & PREFIX_DATA) { /* bndmov -- from reg/mem */ if (reg >=3D 4 || s->aflag =3D=3D MO_16) { diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index d5fd8d965c..4fdd87750b 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -1567,20 +1567,6 @@ illegal: return false; } =20 -static void decode_temp_free(X86DecodedOp *op) -{ - if (op->v_ptr) { - tcg_temp_free_ptr(op->v_ptr); - } -} - -static void decode_temps_free(X86DecodedInsn *decode) -{ - decode_temp_free(&decode->op[0]); - decode_temp_free(&decode->op[1]); - decode_temp_free(&decode->op[2]); -} - /* * Convert one instruction. s->base.is_jmp is set if the translation must * be stopped. @@ -1835,7 +1821,6 @@ static void disas_insn_new(DisasContext *s, CPUState = *cpu, int b) decode.e.gen(s, env, &decode); gen_writeback(s, &decode, 0, s->T0); } - decode_temps_free(&decode); return; illegal_op: gen_illegal_opcode(s); diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index e61ae9a2e9..88359480dd 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -629,7 +629,6 @@ static inline void gen_ternary_sse(DisasContext *s, CPU= X86State *env, X86Decoded /* The format of the fourth input is Lx */ tcg_gen_addi_ptr(ptr3, cpu_env, ZMM_OFFSET(op3)); fn(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, ptr3); - tcg_temp_free_ptr(ptr3); } #define TERNARY_SSE(uname, uvname, lname) = \ static void gen_##uvname(DisasContext *s, CPUX86State *env, X86DecodedInsn= *decode) \ @@ -1001,7 +1000,6 @@ static inline void gen_vsib_avx(DisasContext *s, CPUX= 86State *env, X86DecodedIns int ymmh_ofs =3D vector_elem_offset(&decode->op[1], MO_128, 1); tcg_gen_gvec_dup_imm(MO_64, ymmh_ofs, 16, 16, 0); } - tcg_temp_free_ptr(index); } #define VSIB_AVX(uname, lname) = \ static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn = *decode) \ @@ -1627,7 +1625,6 @@ static void gen_PMOVMSKB(DisasContext *s, CPUX86State= *env, X86DecodedInsn *deco tcg_gen_deposit_tl(s->T0, t, s->T0, 8, TARGET_LONG_BITS - 8); } } - tcg_temp_free(t); } =20 static void gen_PSHUFW(DisasContext *s, CPUX86State *env, X86DecodedInsn *= decode) @@ -1762,7 +1759,6 @@ static void gen_PSRLDQ_i(DisasContext *s, CPUX86State= *env, X86DecodedInsn *deco } else { gen_helper_psrldq_xmm(cpu_env, OP_PTR0, OP_PTR1, imm_vec); } - tcg_temp_free_ptr(imm_vec); } =20 static void gen_PSLLDQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn= *decode) @@ -1775,7 +1771,6 @@ static void gen_PSLLDQ_i(DisasContext *s, CPUX86State= *env, X86DecodedInsn *deco } else { gen_helper_pslldq_xmm(cpu_env, OP_PTR0, OP_PTR1, imm_vec); } - tcg_temp_free_ptr(imm_vec); } =20 static void gen_RORX(DisasContext *s, CPUX86State *env, X86DecodedInsn *de= code) @@ -2293,7 +2288,6 @@ static void gen_VZEROALL(DisasContext *s, CPUX86State= *env, X86DecodedInsn *deco tcg_gen_addi_ptr(ptr, cpu_env, offsetof(CPUX86State, xmm_t0)); gen_helper_memset(ptr, ptr, tcg_constant_i32(0), tcg_constant_ptr(CPU_NB_REGS * sizeof(ZMMReg))); - tcg_temp_free_ptr(ptr); } =20 static void gen_VZEROUPPER(DisasContext *s, CPUX86State *env, X86DecodedIn= sn *decode) --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.26.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:26:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gqHQnIXQuU7WvdYNKGsRU9JQ3hqtUaL0pq9Pxj9E05Q=; b=xuKMdqLyePGrT8T8X4T1rSMKzLfAJ8hjh2mMUUhGyFD/asKHRywZaxly+A0z+0UPht q7HhrqwACefN/KSfANTn87bNecKxkTUvFsy6nF+xQfOZnpbcIEuimU5DkgBgfqzFPdA9 eEBpm/8KGThZuHJrnFfZbyKe7hJMh/4IwwEhKOkl1dSsIadRUAT9PonjQcAgiGePrREP k4blLPIybMqAdUhwiwQ3EBg44VFOXtOb/gaRGTqxowL6VRKR8aWSFW0tICuowSWq2Gj4 +Qj/PLtONYs5i+sC4gKhfZSZbEykckOQ/b4LCrjRRGbwxivCiV98qMBxxBDepgRQpVlL iwZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gqHQnIXQuU7WvdYNKGsRU9JQ3hqtUaL0pq9Pxj9E05Q=; b=mEGhG1cwfh/AloAANeQ8ZFioG6sBjfF/n508hTEzEpQ6Me/9SAitz4UAnSaZ9ALkvQ iPj6XJ9INMyyUJ1mB/mGfkS0eelVY8W4wYf8QoQ3y4c3eH5njIyI5a54gKzJv0QgPuaI euyqSA/SpZqm9EfOBFJI2B98n1SUsydG3U9/e9+5Ac+dBH1reqfSsZM6gUKv2jiY/SVc CK50UyWks2DqiP7q6im4ug+jXAGvbj4RW7ssFpKZAZxXqUcogeKUcHiUTHr59zwx6xxk QLvMfNMrupJKmO2ImcAFId8s/x/FXLG0YjPyY17SYAniXIcAPYG1TLrZf9OBGev2Jk3v 2zCg== X-Gm-Message-State: AO0yUKXRVmNy3dIrMzofLzL3+C17EXilnSfJIz9Jva4ktH+g0wB2iVTh WMhnhpI2/Nmsqq2VT4sQpJq0fja0CTFqzgtgafg= X-Google-Smtp-Source: AK7set9flOMYHu+5yY08p20lwRc05Y8JTvoYJPp3tSqOGeJWCCwF99EGghAD7X5C4P+YLs/uxtT2VQ== X-Received: by 2002:a17:903:80c:b0:19c:dbce:dceb with SMTP id kr12-20020a170903080c00b0019cdbcedcebmr8450701plb.44.1677475595233; Sun, 26 Feb 2023 21:26:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 31/76] target/loongarch: Drop temp_new Date: Sun, 26 Feb 2023 19:24:20 -1000 Message-Id: <20230227052505.352889-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475776711100005 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries, therefore there's no need to record temps for later freeing. Replace the few uses with tcg_temp_new. Reviewed-by: Song Gao Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/loongarch/translate.h | 3 --- target/loongarch/translate.c | 21 +++---------------- .../insn_trans/trans_privileged.c.inc | 2 +- 3 files changed, 4 insertions(+), 22 deletions(-) diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h index 6d2e382e8b..67bc74c05b 100644 --- a/target/loongarch/translate.h +++ b/target/loongarch/translate.h @@ -32,9 +32,6 @@ typedef struct DisasContext { uint16_t mem_idx; uint16_t plv; TCGv zero; - /* Space for 3 operands plus 1 extra for address computation. */ - TCGv temp[4]; - uint8_t ntemp; } DisasContext; =20 void generate_exception(DisasContext *ctx, int excp); diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 2a43ab0201..f443b5822f 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -85,9 +85,6 @@ static void loongarch_tr_init_disas_context(DisasContextB= ase *dcbase, bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; ctx->base.max_insns =3D MIN(ctx->base.max_insns, bound); =20 - ctx->ntemp =3D 0; - memset(ctx->temp, 0, sizeof(ctx->temp)); - ctx->zero =3D tcg_constant_tl(0); } =20 @@ -110,12 +107,6 @@ static void loongarch_tr_insn_start(DisasContextBase *= dcbase, CPUState *cs) * * Further, we may provide an extension for word operations. */ -static TCGv temp_new(DisasContext *ctx) -{ - assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); - return ctx->temp[ctx->ntemp++] =3D tcg_temp_new(); -} - static TCGv gpr_src(DisasContext *ctx, int reg_num, DisasExtend src_ext) { TCGv t; @@ -128,11 +119,11 @@ static TCGv gpr_src(DisasContext *ctx, int reg_num, D= isasExtend src_ext) case EXT_NONE: return cpu_gpr[reg_num]; case EXT_SIGN: - t =3D temp_new(ctx); + t =3D tcg_temp_new(); tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); return t; case EXT_ZERO: - t =3D temp_new(ctx); + t =3D tcg_temp_new(); tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); return t; } @@ -142,7 +133,7 @@ static TCGv gpr_src(DisasContext *ctx, int reg_num, Dis= asExtend src_ext) static TCGv gpr_dst(DisasContext *ctx, int reg_num, DisasExtend dst_ext) { if (reg_num =3D=3D 0 || dst_ext) { - return temp_new(ctx); + return tcg_temp_new(); } return cpu_gpr[reg_num]; } @@ -195,12 +186,6 @@ static void loongarch_tr_translate_insn(DisasContextBa= se *dcbase, CPUState *cs) generate_exception(ctx, EXCCODE_INE); } =20 - for (int i =3D ctx->ntemp - 1; i >=3D 0; --i) { - tcg_temp_free(ctx->temp[i]); - ctx->temp[i] =3D NULL; - } - ctx->ntemp =3D 0; - ctx->base.pc_next +=3D 4; } =20 diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/lo= ongarch/insn_trans/trans_privileged.c.inc index 40f82becb0..56f4c45e09 100644 --- a/target/loongarch/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/insn_trans/trans_privileged.c.inc @@ -243,7 +243,7 @@ static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a) dest =3D gpr_dst(ctx, a->rd, EXT_NONE); csr->writefn(dest, cpu_env, src1); } else { - dest =3D temp_new(ctx); + dest =3D tcg_temp_new(); tcg_gen_ld_tl(dest, cpu_env, csr->offset); tcg_gen_st_tl(src1, cpu_env, csr->offset); } --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Song Gao Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/loongarch/insn_trans/trans_arith.c.inc | 12 ------- .../loongarch/insn_trans/trans_atomic.c.inc | 3 -- target/loongarch/insn_trans/trans_bit.c.inc | 12 ------- target/loongarch/insn_trans/trans_fcmp.c.inc | 3 -- .../loongarch/insn_trans/trans_fmemory.c.inc | 20 ++--------- target/loongarch/insn_trans/trans_fmov.c.inc | 6 ---- .../loongarch/insn_trans/trans_memory.c.inc | 34 +++---------------- .../insn_trans/trans_privileged.c.inc | 4 --- target/loongarch/insn_trans/trans_shift.c.inc | 11 ------ 9 files changed, 6 insertions(+), 99 deletions(-) diff --git a/target/loongarch/insn_trans/trans_arith.c.inc b/target/loongar= ch/insn_trans/trans_arith.c.inc index 8e45eadbc8..43d6cf261d 100644 --- a/target/loongarch/insn_trans/trans_arith.c.inc +++ b/target/loongarch/insn_trans/trans_arith.c.inc @@ -100,14 +100,12 @@ static void gen_mulh_d(TCGv dest, TCGv src1, TCGv src= 2) { TCGv discard =3D tcg_temp_new(); tcg_gen_muls2_tl(discard, dest, src1, src2); - tcg_temp_free(discard); } =20 static void gen_mulh_du(TCGv dest, TCGv src1, TCGv src2) { TCGv discard =3D tcg_temp_new(); tcg_gen_mulu2_tl(discard, dest, src1, src2); - tcg_temp_free(discard); } =20 static void prep_divisor_d(TCGv ret, TCGv src1, TCGv src2) @@ -129,9 +127,6 @@ static void prep_divisor_d(TCGv ret, TCGv src1, TCGv sr= c2) tcg_gen_and_tl(ret, ret, t0); tcg_gen_or_tl(ret, ret, t1); tcg_gen_movcond_tl(TCG_COND_NE, ret, ret, zero, ret, src2); - - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void prep_divisor_du(TCGv ret, TCGv src2) @@ -152,7 +147,6 @@ static void gen_div_d(TCGv dest, TCGv src1, TCGv src2) TCGv t0 =3D tcg_temp_new(); prep_divisor_d(t0, src1, src2); tcg_gen_div_tl(dest, src1, t0); - tcg_temp_free(t0); } =20 static void gen_rem_d(TCGv dest, TCGv src1, TCGv src2) @@ -160,7 +154,6 @@ static void gen_rem_d(TCGv dest, TCGv src1, TCGv src2) TCGv t0 =3D tcg_temp_new(); prep_divisor_d(t0, src1, src2); tcg_gen_rem_tl(dest, src1, t0); - tcg_temp_free(t0); } =20 static void gen_div_du(TCGv dest, TCGv src1, TCGv src2) @@ -168,7 +161,6 @@ static void gen_div_du(TCGv dest, TCGv src1, TCGv src2) TCGv t0 =3D tcg_temp_new(); prep_divisor_du(t0, src2); tcg_gen_divu_tl(dest, src1, t0); - tcg_temp_free(t0); } =20 static void gen_rem_du(TCGv dest, TCGv src1, TCGv src2) @@ -176,7 +168,6 @@ static void gen_rem_du(TCGv dest, TCGv src1, TCGv src2) TCGv t0 =3D tcg_temp_new(); prep_divisor_du(t0, src2); tcg_gen_remu_tl(dest, src1, t0); - tcg_temp_free(t0); } =20 static void gen_div_w(TCGv dest, TCGv src1, TCGv src2) @@ -185,7 +176,6 @@ static void gen_div_w(TCGv dest, TCGv src1, TCGv src2) /* We need not check for integer overflow for div_w. */ prep_divisor_du(t0, src2); tcg_gen_div_tl(dest, src1, t0); - tcg_temp_free(t0); } =20 static void gen_rem_w(TCGv dest, TCGv src1, TCGv src2) @@ -194,7 +184,6 @@ static void gen_rem_w(TCGv dest, TCGv src1, TCGv src2) /* We need not check for integer overflow for rem_w. */ prep_divisor_du(t0, src2); tcg_gen_rem_tl(dest, src1, t0); - tcg_temp_free(t0); } =20 static void gen_alsl(TCGv dest, TCGv src1, TCGv src2, target_long sa) @@ -202,7 +191,6 @@ static void gen_alsl(TCGv dest, TCGv src1, TCGv src2, t= arget_long sa) TCGv t0 =3D tcg_temp_new(); tcg_gen_shli_tl(t0, src1, sa); tcg_gen_add_tl(dest, t0, src2); - tcg_temp_free(t0); } =20 static bool trans_lu32i_d(DisasContext *ctx, arg_lu32i_d *a) diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loonga= rch/insn_trans/trans_atomic.c.inc index 6763c1c301..612709f2a7 100644 --- a/target/loongarch/insn_trans/trans_atomic.c.inc +++ b/target/loongarch/insn_trans/trans_atomic.c.inc @@ -14,7 +14,6 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp = mop) tcg_gen_st_tl(t0, cpu_env, offsetof(CPULoongArchState, lladdr)); tcg_gen_st_tl(dest, cpu_env, offsetof(CPULoongArchState, llval)); gen_set_gpr(a->rd, dest, EXT_NONE); - tcg_temp_free(t0); =20 return true; } @@ -43,8 +42,6 @@ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp = mop) tcg_gen_setcond_tl(TCG_COND_EQ, dest, t0, cpu_llval); gen_set_label(done); gen_set_gpr(a->rd, dest, EXT_NONE); - tcg_temp_free(t0); - tcg_temp_free(val); =20 return true; } diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch= /insn_trans/trans_bit.c.inc index b01e4aeb23..25b4d7858b 100644 --- a/target/loongarch/insn_trans/trans_bit.c.inc +++ b/target/loongarch/insn_trans/trans_bit.c.inc @@ -122,9 +122,6 @@ static void gen_revb_2h(TCGv dest, TCGv src1) tcg_gen_and_tl(t1, src1, mask); tcg_gen_shli_tl(t1, t1, 8); tcg_gen_or_tl(dest, t0, t1); - - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_revb_4h(TCGv dest, TCGv src1) @@ -138,9 +135,6 @@ static void gen_revb_4h(TCGv dest, TCGv src1) tcg_gen_and_tl(t1, src1, mask); tcg_gen_shli_tl(t1, t1, 8); tcg_gen_or_tl(dest, t0, t1); - - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_revh_2w(TCGv dest, TCGv src1) @@ -154,9 +148,6 @@ static void gen_revh_2w(TCGv dest, TCGv src1) tcg_gen_and_i64(t0, t0, mask); tcg_gen_shli_i64(t1, t1, 16); tcg_gen_or_i64(dest, t1, t0); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 static void gen_revh_d(TCGv dest, TCGv src1) @@ -171,9 +162,6 @@ static void gen_revh_d(TCGv dest, TCGv src1) tcg_gen_shli_tl(t0, t0, 16); tcg_gen_or_tl(t0, t0, t1); tcg_gen_rotri_tl(dest, t0, 32); - - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_maskeqz(TCGv dest, TCGv src1, TCGv src2) diff --git a/target/loongarch/insn_trans/trans_fcmp.c.inc b/target/loongarc= h/insn_trans/trans_fcmp.c.inc index 2ccf646ccb..3b0da2b9f4 100644 --- a/target/loongarch/insn_trans/trans_fcmp.c.inc +++ b/target/loongarch/insn_trans/trans_fcmp.c.inc @@ -38,7 +38,6 @@ static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp= _cond_s *a) fn(var, cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], tcg_constant_i32(flag= s)); =20 tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd])); - tcg_temp_free(var); return true; } =20 @@ -57,7 +56,5 @@ static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp= _cond_d *a) fn(var, cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], tcg_constant_i32(flag= s)); =20 tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd])); - - tcg_temp_free(var); return true; } diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loong= arch/insn_trans/trans_fmemory.c.inc index 3025a1d3e9..0d11843873 100644 --- a/target/loongarch/insn_trans/trans_fmemory.c.inc +++ b/target/loongarch/insn_trans/trans_fmemory.c.inc @@ -13,12 +13,11 @@ static void maybe_nanbox_load(TCGv freg, MemOp mop) static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp mop) { TCGv addr =3D gpr_src(ctx, a->rj, EXT_NONE); - TCGv temp =3D NULL; =20 CHECK_FPE; =20 if (a->imm) { - temp =3D tcg_temp_new(); + TCGv temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, addr, a->imm); addr =3D temp; } @@ -26,31 +25,22 @@ static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a,= MemOp mop) tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); maybe_nanbox_load(cpu_fpr[a->fd], mop); =20 - if (temp) { - tcg_temp_free(temp); - } - return true; } =20 static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, MemOp mop) { TCGv addr =3D gpr_src(ctx, a->rj, EXT_NONE); - TCGv temp =3D NULL; =20 CHECK_FPE; =20 if (a->imm) { - temp =3D tcg_temp_new(); + TCGv temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, addr, a->imm); addr =3D temp; } =20 tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); - - if (temp) { - tcg_temp_free(temp); - } return true; } =20 @@ -66,7 +56,6 @@ static bool gen_floadx(DisasContext *ctx, arg_frr *a, Mem= Op mop) tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); maybe_nanbox_load(cpu_fpr[a->fd], mop); - tcg_temp_free(addr); =20 return true; } @@ -82,7 +71,6 @@ static bool gen_fstorex(DisasContext *ctx, arg_frr *a, Me= mOp mop) addr =3D tcg_temp_new(); tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); - tcg_temp_free(addr); =20 return true; } @@ -100,7 +88,6 @@ static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, = MemOp mop) tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); maybe_nanbox_load(cpu_fpr[a->fd], mop); - tcg_temp_free(addr); =20 return true; } @@ -117,7 +104,6 @@ static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a= , MemOp mop) gen_helper_asrtgt_d(cpu_env, src1, src2); tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); - tcg_temp_free(addr); =20 return true; } @@ -135,7 +121,6 @@ static bool gen_fload_le(DisasContext *ctx, arg_frr *a,= MemOp mop) tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); maybe_nanbox_load(cpu_fpr[a->fd], mop); - tcg_temp_free(addr); =20 return true; } @@ -152,7 +137,6 @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a= , MemOp mop) gen_helper_asrtle_d(cpu_env, src1, src2); tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); - tcg_temp_free(addr); =20 return true; } diff --git a/target/loongarch/insn_trans/trans_fmov.c.inc b/target/loongarc= h/insn_trans/trans_fmov.c.inc index 8e5106db4e..069c941665 100644 --- a/target/loongarch/insn_trans/trans_fmov.c.inc +++ b/target/loongarch/insn_trans/trans_fmov.c.inc @@ -18,7 +18,6 @@ static bool trans_fsel(DisasContext *ctx, arg_fsel *a) tcg_gen_ld8u_tl(cond, cpu_env, offsetof(CPULoongArchState, cf[a->ca])); tcg_gen_movcond_tl(TCG_COND_EQ, cpu_fpr[a->fd], cond, zero, cpu_fpr[a->fj], cpu_fpr[a->fk]); - tcg_temp_free(cond); =20 return true; } @@ -82,9 +81,6 @@ static bool trans_movgr2fcsr(DisasContext *ctx, arg_movgr= 2fcsr *a) tcg_gen_andi_i32(fcsr0, fcsr0, ~mask); tcg_gen_or_i32(fcsr0, fcsr0, temp); tcg_gen_st_i32(fcsr0, cpu_env, offsetof(CPULoongArchState, fcsr0)); - - tcg_temp_free_i32(temp); - tcg_temp_free_i32(fcsr0); } =20 /* @@ -134,7 +130,6 @@ static bool trans_movfr2cf(DisasContext *ctx, arg_movfr= 2cf *a) t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, cpu_fpr[a->fj], 0x1); tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7= ])); - tcg_temp_free(t0); =20 return true; } @@ -157,7 +152,6 @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr= 2cf *a) t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, gpr_src(ctx, a->rj, EXT_NONE), 0x1); tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7= ])); - tcg_temp_free(t0); =20 return true; } diff --git a/target/loongarch/insn_trans/trans_memory.c.inc b/target/loonga= rch/insn_trans/trans_memory.c.inc index d5eb31147c..75cfdf59ad 100644 --- a/target/loongarch/insn_trans/trans_memory.c.inc +++ b/target/loongarch/insn_trans/trans_memory.c.inc @@ -7,21 +7,15 @@ static bool gen_load(DisasContext *ctx, arg_rr_i *a, MemO= p mop) { TCGv dest =3D gpr_dst(ctx, a->rd, EXT_NONE); TCGv addr =3D gpr_src(ctx, a->rj, EXT_NONE); - TCGv temp =3D NULL; =20 if (a->imm) { - temp =3D tcg_temp_new(); + TCGv temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, addr, a->imm); addr =3D temp; } =20 tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); gen_set_gpr(a->rd, dest, EXT_NONE); - - if (temp) { - tcg_temp_free(temp); - } - return true; } =20 @@ -29,20 +23,14 @@ static bool gen_store(DisasContext *ctx, arg_rr_i *a, M= emOp mop) { TCGv data =3D gpr_src(ctx, a->rd, EXT_NONE); TCGv addr =3D gpr_src(ctx, a->rj, EXT_NONE); - TCGv temp =3D NULL; =20 if (a->imm) { - temp =3D tcg_temp_new(); + TCGv temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, addr, a->imm); addr =3D temp; } =20 tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop); - - if (temp) { - tcg_temp_free(temp); - } - return true; } =20 @@ -56,7 +44,6 @@ static bool gen_loadx(DisasContext *ctx, arg_rrr *a, MemO= p mop) tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); gen_set_gpr(a->rd, dest, EXT_NONE); - tcg_temp_free(addr); =20 return true; } @@ -70,7 +57,6 @@ static bool gen_storex(DisasContext *ctx, arg_rrr *a, Mem= Op mop) =20 tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop); - tcg_temp_free(addr); =20 return true; } @@ -146,21 +132,15 @@ static bool gen_ldptr(DisasContext *ctx, arg_rr_i *a,= MemOp mop) { TCGv dest =3D gpr_dst(ctx, a->rd, EXT_NONE); TCGv addr =3D gpr_src(ctx, a->rj, EXT_NONE); - TCGv temp =3D NULL; =20 if (a->imm) { - temp =3D tcg_temp_new(); + TCGv temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, addr, a->imm); addr =3D temp; } =20 tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); gen_set_gpr(a->rd, dest, EXT_NONE); - - if (temp) { - tcg_temp_free(temp); - } - return true; } =20 @@ -168,20 +148,14 @@ static bool gen_stptr(DisasContext *ctx, arg_rr_i *a,= MemOp mop) { TCGv data =3D gpr_src(ctx, a->rd, EXT_NONE); TCGv addr =3D gpr_src(ctx, a->rj, EXT_NONE); - TCGv temp =3D NULL; =20 if (a->imm) { - temp =3D tcg_temp_new(); + TCGv temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, addr, a->imm); addr =3D temp; } =20 tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop); - - if (temp) { - tcg_temp_free(temp); - } - return true; } =20 diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/lo= ongarch/insn_trans/trans_privileged.c.inc index 56f4c45e09..5a04352b01 100644 --- a/target/loongarch/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/insn_trans/trans_privileged.c.inc @@ -291,10 +291,6 @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxc= hg *a) tcg_gen_st_tl(newv, cpu_env, csr->offset); } gen_set_gpr(a->rd, oldv, EXT_NONE); - - tcg_temp_free(temp); - tcg_temp_free(newv); - tcg_temp_free(oldv); return true; } =20 diff --git a/target/loongarch/insn_trans/trans_shift.c.inc b/target/loongar= ch/insn_trans/trans_shift.c.inc index 5260af2337..bf5428a2ba 100644 --- a/target/loongarch/insn_trans/trans_shift.c.inc +++ b/target/loongarch/insn_trans/trans_shift.c.inc @@ -8,7 +8,6 @@ static void gen_sll_w(TCGv dest, TCGv src1, TCGv src2) TCGv t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, src2, 0x1f); tcg_gen_shl_tl(dest, src1, t0); - tcg_temp_free(t0); } =20 static void gen_srl_w(TCGv dest, TCGv src1, TCGv src2) @@ -16,7 +15,6 @@ static void gen_srl_w(TCGv dest, TCGv src1, TCGv src2) TCGv t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, src2, 0x1f); tcg_gen_shr_tl(dest, src1, t0); - tcg_temp_free(t0); } =20 static void gen_sra_w(TCGv dest, TCGv src1, TCGv src2) @@ -24,7 +22,6 @@ static void gen_sra_w(TCGv dest, TCGv src1, TCGv src2) TCGv t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, src2, 0x1f); tcg_gen_sar_tl(dest, src1, t0); - tcg_temp_free(t0); } =20 static void gen_sll_d(TCGv dest, TCGv src1, TCGv src2) @@ -32,7 +29,6 @@ static void gen_sll_d(TCGv dest, TCGv src1, TCGv src2) TCGv t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, src2, 0x3f); tcg_gen_shl_tl(dest, src1, t0); - tcg_temp_free(t0); } =20 static void gen_srl_d(TCGv dest, TCGv src1, TCGv src2) @@ -40,7 +36,6 @@ static void gen_srl_d(TCGv dest, TCGv src1, TCGv src2) TCGv t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, src2, 0x3f); tcg_gen_shr_tl(dest, src1, t0); - tcg_temp_free(t0); } =20 static void gen_sra_d(TCGv dest, TCGv src1, TCGv src2) @@ -48,7 +43,6 @@ static void gen_sra_d(TCGv dest, TCGv src1, TCGv src2) TCGv t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, src2, 0x3f); tcg_gen_sar_tl(dest, src1, t0); - tcg_temp_free(t0); } =20 static void gen_rotr_w(TCGv dest, TCGv src1, TCGv src2) @@ -64,10 +58,6 @@ static void gen_rotr_w(TCGv dest, TCGv src1, TCGv src2) =20 tcg_gen_rotr_i32(t1, t1, t2); tcg_gen_ext_i32_tl(dest, t1); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); - tcg_temp_free(t0); } =20 static void gen_rotr_d(TCGv dest, TCGv src1, TCGv src2) @@ -75,7 +65,6 @@ static void gen_rotr_d(TCGv dest, TCGv src1, TCGv src2) TCGv t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, src2, 0x3f); tcg_gen_rotr_tl(dest, src1, t0); - tcg_temp_free(t0); } =20 static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a) --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.26.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:26:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PZT9JzGqWNeNM4srg9HjjFaakIhKs3s8GuAgd6TYYaQ=; b=Qbim//oujTqfuRONSlXfVji0kPeSbYsrURvV2V1SdFx6VOZI072Gn1sITztlpn3mUU h/smZopUdtRDzE7vhzzjBy76s583oiaolQGN2r9Q9cdsiCAQDSEZsE1nB4nTTZVgkBGr /FfCBKOPUuCq7GjJDeNvcY2gzeZN1NbVuVGZgP1yjOIKmWzNHAijpYjS8exHoion3e4K 6js0cghUQSAsk6ffHPfhGJZsJnG7LRcIn8Mj5hSGudRl+U1S+RNzZweAfwSofVxpgCSN B7muJGwMCmaMG5mxa5b2XYJ5QwfR8OlXKYzC5IptNuymvl2YEze0YoCg33yoR9qsnKi0 g70g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PZT9JzGqWNeNM4srg9HjjFaakIhKs3s8GuAgd6TYYaQ=; b=GFDDsjD01gjB/Cp83/ONpTfnxzoi++G0QCBpJ4knCuK8omZuGkQWmqIkf9C0ObbE3q qmCRl7CDpHEmGHkBQAFJUYBWbZ1OdVQRdzo0TDODLeuzmYeYq/CzW/09kCj4pGPTyB8z KnXrj7VRLffuhwUX5VINBC4dMeyd0OHfP3PrqAa2VNoJuxwpQgl9Q57WZslB1Mo1UnqB Se99W8O1PxCNx/71MljYMOEenfoXtuyp9DAsOmJ+73jBL+Wpm8Cks+MD58Lwgc7dmetk FOnVZd8TS5QdvCarINbZIW2uIVWnE6gwgy9+vhTkQJmwvkPXGF5ZPZOV5BaN9kEv8dnp 9PdA== X-Gm-Message-State: AO0yUKUe7mHfrJYtWrk0c27DpXFcEOXWmWXB81yujyoImEsiqURyqeCe Dvpp/wp8t85BCHyNJMfo6t5v1I+1/brWQXUs1qQ= X-Google-Smtp-Source: AK7set/FYj1UfDWXTr765oY7hPscjHh4L++am7Jq+O8fIODc90tGoeQMvO8qVTs7q6BXlOf9H6CN5w== X-Received: by 2002:a17:902:dace:b0:19d:c9f:44f3 with SMTP id q14-20020a170902dace00b0019d0c9f44f3mr3452349plx.21.1677475600708; Sun, 26 Feb 2023 21:26:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 33/76] target/m68k: Drop mark_to_release Date: Sun, 26 Feb 2023 19:24:22 -1000 Message-Id: <20230227052505.352889-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475883269100007 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries, therefore there's no need to record temps for later freeing. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/m68k/translate.c | 55 ++++++++++------------------------------- 1 file changed, 13 insertions(+), 42 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 157c2cbb8f..b3cd3e87e1 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -121,35 +121,9 @@ typedef struct DisasContext { int done_mac; int writeback_mask; TCGv writeback[8]; -#define MAX_TO_RELEASE 8 - int release_count; - TCGv release[MAX_TO_RELEASE]; bool ss_active; } DisasContext; =20 -static void init_release_array(DisasContext *s) -{ -#ifdef CONFIG_DEBUG_TCG - memset(s->release, 0, sizeof(s->release)); -#endif - s->release_count =3D 0; -} - -static void do_release(DisasContext *s) -{ - int i; - for (i =3D 0; i < s->release_count; i++) { - tcg_temp_free(s->release[i]); - } - init_release_array(s); -} - -static TCGv mark_to_release(DisasContext *s, TCGv tmp) -{ - g_assert(s->release_count < MAX_TO_RELEASE); - return s->release[s->release_count++] =3D tmp; -} - static TCGv get_areg(DisasContext *s, unsigned regno) { if (s->writeback_mask & (1 << regno)) { @@ -396,8 +370,7 @@ static TCGv gen_ldst(DisasContext *s, int opsize, TCGv = addr, TCGv val, gen_store(s, opsize, addr, val, index); return store_dummy; } else { - return mark_to_release(s, gen_load(s, opsize, addr, - what =3D=3D EA_LOADS, index)); + return gen_load(s, opsize, addr, what =3D=3D EA_LOADS, index); } } =20 @@ -491,7 +464,7 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasCon= text *s, TCGv base) } else { bd =3D 0; } - tmp =3D mark_to_release(s, tcg_temp_new()); + tmp =3D tcg_temp_new(); if ((ext & 0x44) =3D=3D 0) { /* pre-index */ add =3D gen_addr_index(s, ext, tmp); @@ -501,7 +474,7 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasCon= text *s, TCGv base) if ((ext & 0x80) =3D=3D 0) { /* base not suppressed */ if (IS_NULL_QREG(base)) { - base =3D mark_to_release(s, tcg_const_i32(offset + bd)); + base =3D tcg_const_i32(offset + bd); bd =3D 0; } if (!IS_NULL_QREG(add)) { @@ -517,11 +490,11 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasC= ontext *s, TCGv base) add =3D tmp; } } else { - add =3D mark_to_release(s, tcg_const_i32(bd)); + add =3D tcg_const_i32(bd); } if ((ext & 3) !=3D 0) { /* memory indirect */ - base =3D mark_to_release(s, gen_load(s, OS_LONG, add, 0, IS_US= ER(s))); + base =3D gen_load(s, OS_LONG, add, 0, IS_USER(s)); if ((ext & 0x44) =3D=3D 4) { add =3D gen_addr_index(s, ext, tmp); tcg_gen_add_i32(tmp, add, base); @@ -546,7 +519,7 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasCon= text *s, TCGv base) } } else { /* brief extension word format */ - tmp =3D mark_to_release(s, tcg_temp_new()); + tmp =3D tcg_temp_new(); add =3D gen_addr_index(s, ext, tmp); if (!IS_NULL_QREG(base)) { tcg_gen_add_i32(tmp, add, base); @@ -676,7 +649,7 @@ static inline TCGv gen_extend(DisasContext *s, TCGv val= , int opsize, int sign) if (opsize =3D=3D OS_LONG) { tmp =3D val; } else { - tmp =3D mark_to_release(s, tcg_temp_new()); + tmp =3D tcg_temp_new(); gen_ext(tmp, val, opsize, sign); } =20 @@ -802,7 +775,7 @@ static TCGv gen_lea_mode(CPUM68KState *env, DisasContex= t *s, return NULL_QREG; } reg =3D get_areg(s, reg0); - tmp =3D mark_to_release(s, tcg_temp_new()); + tmp =3D tcg_temp_new(); if (reg0 =3D=3D 7 && opsize =3D=3D OS_BYTE && m68k_feature(s->env, M68K_FEATURE_M68K)) { tcg_gen_subi_i32(tmp, reg, 2); @@ -812,7 +785,7 @@ static TCGv gen_lea_mode(CPUM68KState *env, DisasContex= t *s, return tmp; case 5: /* Indirect displacement. */ reg =3D get_areg(s, reg0); - tmp =3D mark_to_release(s, tcg_temp_new()); + tmp =3D tcg_temp_new(); ext =3D read_im16(env, s); tcg_gen_addi_i32(tmp, reg, (int16_t)ext); return tmp; @@ -823,14 +796,14 @@ static TCGv gen_lea_mode(CPUM68KState *env, DisasCont= ext *s, switch (reg0) { case 0: /* Absolute short. */ offset =3D (int16_t)read_im16(env, s); - return mark_to_release(s, tcg_const_i32(offset)); + return tcg_const_i32(offset); case 1: /* Absolute long. */ offset =3D read_im32(env, s); - return mark_to_release(s, tcg_const_i32(offset)); + return tcg_const_i32(offset); case 2: /* pc displacement */ offset =3D s->pc; offset +=3D (int16_t)read_im16(env, s); - return mark_to_release(s, tcg_const_i32(offset)); + return tcg_const_i32(offset); case 3: /* pc index+displacement. */ return gen_lea_indexed(env, s, NULL_QREG); case 4: /* Immediate. */ @@ -958,7 +931,7 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext= *s, int mode, int reg0, default: g_assert_not_reached(); } - return mark_to_release(s, tcg_const_i32(offset)); + return tcg_const_i32(offset); default: return NULL_QREG; } @@ -6287,7 +6260,6 @@ static void m68k_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cpu) dc->cc_op_synced =3D 1; dc->done_mac =3D 0; dc->writeback_mask =3D 0; - init_release_array(dc); =20 dc->ss_active =3D (M68K_SR_TRACE(env->sr) =3D=3D M68K_SR_TRACE_ANY_INS= ); /* If architectural single step active, limit to 1 */ @@ -6314,7 +6286,6 @@ static void m68k_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cpu) =20 opcode_table[insn](env, dc, insn); do_writebacks(dc); - do_release(dc); =20 dc->pc_prev =3D dc->base.pc_next; dc->base.pc_next =3D dc->pc; --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677476393; cv=none; d=zohomail.com; s=zohoarc; b=KzUMd58MX59YaP+YzccKRGxV+eEDJSYIEF9bdhcu39P8wCeS38GITG9pwJMgdNfPXWeWUrF0c8fAsZ4N2LLFcDDLoGs/mBWXjycCAxdvxCteu8VzTXTXg3XdGp0rxGhlTmnlpYov5X1vw6nIJx6x9F4/x6Gvx5KIUTz8kk9qawo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677476393; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZO7UItfQReoklgOJZJKKMMXCbbFRvVQBOxOhYteWFwg=; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.26.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:26:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZO7UItfQReoklgOJZJKKMMXCbbFRvVQBOxOhYteWFwg=; b=x3YWh6Y8Wl9/jAeHHhmj/GKXBMc51EvKKX4aGi4uIn72yLNZtdWJOVJCCJAptV0Uxo r0lQnej5CCFxIhIG6qG3fjPL0npmnXoRPI0kAFti/DkWRHDf+GJCO6ZJaIPQQdCJ8fGg sFmZ2CunPaqtp7P5iIEPbQ7Jfm3rxcrV1NOyiuid+xti+A1P5ewJvXM3m4Ly1SjTObcp VYaBD1qyS8eg8VYvC9Vnq1O5zr37YA4B8D1bK2zwsVKfkSCJd4qHivfds3RST5WQ3HYR rL3qaWmLAoN6cww96aybEDg1T+QBpg8EmWY6AQ53CLotbXzv2lN6+XlrNxjmiqq4RZjP HWMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZO7UItfQReoklgOJZJKKMMXCbbFRvVQBOxOhYteWFwg=; b=IQxckE0uH6usIm80T77npMVIsLZGQUGPV9tPuqC6QGjpgfn+GuiMWgSNcdgFPa2oSM epmkgMk0z+arf9hHFfohun6UrokHbbxI0pAwc/OidCgqZEyhVW+JGoatOOC3/b74dJjo YJ2r9wWCedg1/fsFpPRPITx/duzGY0x2yBQnw82qtWXNiI0jhlb+CBbskOv3H196C0L1 aKXM1cccQcHLA862U6sE8OY+eJf2WOfC3b/WZHAJsdGPG2Z75F42IQrbNeOV0zVqCaZY mOsPe+vX7lo4dxsFju0dDpjPHp8QGo9DjCBILfFTJ2lYGyRYKbIcnY8bOsy1n7EjehXt 45vg== X-Gm-Message-State: AO0yUKW3djFm3/aUC5NQN2vNEtdZEnfclshIuf+HeLF/0cl/Ugj38sHr vhFFfssUbEFSxEBun2JCJIJKvFqTjQ+P6uz1SkXb/w== X-Google-Smtp-Source: AK7set+LdMZViO7yFhYVGG002xPX4u26b6zxx8vsWM5QbembImHEOUoX2p7r/02oYGVotuZu6DnvGg== X-Received: by 2002:a17:902:f544:b0:19d:138b:7c4a with SMTP id h4-20020a170902f54400b0019d138b7c4amr3042423plf.3.1677475603333; Sun, 26 Feb 2023 21:26:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 34/76] target/m68k: Drop free_cond Date: Sun, 26 Feb 2023 19:24:23 -1000 Message-Id: <20230227052505.352889-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476395839100003 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Remove the g1 and g2 members of DisasCompare, as they were used to track which temps needed to be freed. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/m68k/translate.c | 40 ---------------------------------------- 1 file changed, 40 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index b3cd3e87e1..d7237b6a99 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -1249,8 +1249,6 @@ static int gen_ea_fp(CPUM68KState *env, DisasContext = *s, uint16_t insn, =20 typedef struct { TCGCond tcond; - bool g1; - bool g2; TCGv v1; TCGv v2; } DisasCompare; @@ -1263,7 +1261,6 @@ static void gen_cc_cond(DisasCompare *c, DisasContext= *s, int cond) =20 /* The CC_OP_CMP form can handle most normal comparisons directly. */ if (op =3D=3D CC_OP_CMPB || op =3D=3D CC_OP_CMPW || op =3D=3D CC_OP_CM= PL) { - c->g1 =3D c->g2 =3D 1; c->v1 =3D QREG_CC_N; c->v2 =3D QREG_CC_V; switch (cond) { @@ -1281,7 +1278,6 @@ static void gen_cc_cond(DisasCompare *c, DisasContext= *s, int cond) goto done; case 10: /* PL */ case 11: /* MI */ - c->g1 =3D c->g2 =3D 0; c->v2 =3D tcg_const_i32(0); c->v1 =3D tmp =3D tcg_temp_new(); tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V); @@ -1298,8 +1294,6 @@ static void gen_cc_cond(DisasCompare *c, DisasContext= *s, int cond) } } =20 - c->g1 =3D 1; - c->g2 =3D 0; c->v2 =3D tcg_const_i32(0); =20 switch (cond) { @@ -1383,7 +1377,6 @@ static void gen_cc_cond(DisasCompare *c, DisasContext= *s, int cond) case 2: /* HI (!C && !Z) -> !(C || Z)*/ case 3: /* LS (C || Z) */ c->v1 =3D tmp =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2); tcg_gen_or_i32(tmp, tmp, QREG_CC_C); tcond =3D TCG_COND_NE; @@ -1411,14 +1404,12 @@ static void gen_cc_cond(DisasCompare *c, DisasConte= xt *s, int cond) case 12: /* GE (!(N ^ V)) */ case 13: /* LT (N ^ V) */ c->v1 =3D tmp =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V); tcond =3D TCG_COND_LT; break; case 14: /* GT (!(Z || (N ^ V))) */ case 15: /* LE (Z || (N ^ V)) */ c->v1 =3D tmp =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2); tcg_gen_neg_i32(tmp, tmp); tmp2 =3D tcg_temp_new(); @@ -1436,16 +1427,6 @@ static void gen_cc_cond(DisasCompare *c, DisasContex= t *s, int cond) c->tcond =3D tcond; } =20 -static void free_cond(DisasCompare *c) -{ - if (!c->g1) { - tcg_temp_free(c->v1); - } - if (!c->g2) { - tcg_temp_free(c->v2); - } -} - static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) { DisasCompare c; @@ -1453,7 +1434,6 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGL= abel *l1) gen_cc_cond(&c, s, cond); update_cc_op(s); tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1); - free_cond(&c); } =20 /* Force a TB lookup after an instruction that changes the CPU state. */ @@ -1512,7 +1492,6 @@ DISAS_INSN(scc) =20 tmp =3D tcg_temp_new(); tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2); - free_cond(&c); =20 tcg_gen_neg_i32(tmp, tmp); DEST_EA(env, insn, OS_BYTE, tmp, NULL); @@ -4887,7 +4866,6 @@ static void do_trapcc(DisasContext *s, DisasCompare *= c) s->base.is_jmp =3D DISAS_NEXT; } } - free_cond(c); } =20 DISAS_INSN(trapcc) @@ -5383,9 +5361,7 @@ static void gen_fcc_cond(DisasCompare *c, DisasContex= t *s, int cond) { TCGv fpsr; =20 - c->g1 =3D 1; c->v2 =3D tcg_const_i32(0); - c->g2 =3D 0; /* TODO: Raise BSUN exception. */ fpsr =3D tcg_temp_new(); gen_load_fcr(s, fpsr, M68K_FPSR); @@ -5398,14 +5374,12 @@ static void gen_fcc_cond(DisasCompare *c, DisasCont= ext *s, int cond) case 1: /* EQual Z */ case 17: /* Signaling EQual Z */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z); c->tcond =3D TCG_COND_NE; break; case 2: /* Ordered Greater Than !(A || Z || N) */ case 18: /* Greater Than !(A || Z || N) */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N); c->tcond =3D TCG_COND_EQ; @@ -5413,7 +5387,6 @@ static void gen_fcc_cond(DisasCompare *c, DisasContex= t *s, int cond) case 3: /* Ordered Greater than or Equal Z || !(A || N) */ case 19: /* Greater than or Equal Z || !(A || N) */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A); tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A)= ); tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_Z | FPSR_CC_N); @@ -5424,7 +5397,6 @@ static void gen_fcc_cond(DisasCompare *c, DisasContex= t *s, int cond) case 4: /* Ordered Less Than !(!N || A || Z); */ case 20: /* Less Than !(!N || A || Z); */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_xori_i32(c->v1, fpsr, FPSR_CC_N); tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_N | FPSR_CC_A | FPSR_CC_Z); c->tcond =3D TCG_COND_EQ; @@ -5432,7 +5404,6 @@ static void gen_fcc_cond(DisasCompare *c, DisasContex= t *s, int cond) case 5: /* Ordered Less than or Equal Z || (N && !A) */ case 21: /* Less than or Equal Z || (N && !A) */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A); tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A)= ); tcg_gen_andc_i32(c->v1, fpsr, c->v1); @@ -5442,35 +5413,30 @@ static void gen_fcc_cond(DisasCompare *c, DisasCont= ext *s, int cond) case 6: /* Ordered Greater or Less than !(A || Z) */ case 22: /* Greater or Less than !(A || Z) */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z); c->tcond =3D TCG_COND_EQ; break; case 7: /* Ordered !A */ case 23: /* Greater, Less or Equal !A */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A); c->tcond =3D TCG_COND_EQ; break; case 8: /* Unordered A */ case 24: /* Not Greater, Less or Equal A */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A); c->tcond =3D TCG_COND_NE; break; case 9: /* Unordered or Equal A || Z */ case 25: /* Not Greater or Less then A || Z */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z); c->tcond =3D TCG_COND_NE; break; case 10: /* Unordered or Greater Than A || !(N || Z)) */ case 26: /* Not Less or Equal A || !(N || Z)) */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z); tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z)= ); tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_A | FPSR_CC_N); @@ -5481,7 +5447,6 @@ static void gen_fcc_cond(DisasCompare *c, DisasContex= t *s, int cond) case 11: /* Unordered or Greater or Equal A || Z || !N */ case 27: /* Not Less Than A || Z || !N */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N); tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N); c->tcond =3D TCG_COND_NE; @@ -5489,7 +5454,6 @@ static void gen_fcc_cond(DisasCompare *c, DisasContex= t *s, int cond) case 12: /* Unordered or Less Than A || (N && !Z) */ case 28: /* Not Greater than or Equal A || (N && !Z) */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z); tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z)= ); tcg_gen_andc_i32(c->v1, fpsr, c->v1); @@ -5499,14 +5463,12 @@ static void gen_fcc_cond(DisasCompare *c, DisasCont= ext *s, int cond) case 13: /* Unordered or Less or Equal A || Z || N */ case 29: /* Not Greater Than A || Z || N */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N); c->tcond =3D TCG_COND_NE; break; case 14: /* Not Equal !Z */ case 30: /* Signaling Not Equal !Z */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z); c->tcond =3D TCG_COND_EQ; break; @@ -5526,7 +5488,6 @@ static void gen_fjmpcc(DisasContext *s, int cond, TCG= Label *l1) gen_fcc_cond(&c, s, cond); update_cc_op(s); tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1); - free_cond(&c); } =20 DISAS_INSN(fbcc) @@ -5562,7 +5523,6 @@ DISAS_INSN(fscc) =20 tmp =3D tcg_temp_new(); tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2); - free_cond(&c); =20 tcg_gen_neg_i32(tmp, tmp); DEST_EA(env, insn, OS_BYTE, tmp, NULL); --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677475928; cv=none; d=zohomail.com; s=zohoarc; b=K7xbtjanzOrhhx3QbUkiIGyEFjWB/4Iqf5UUrWc99RANRqeyZEyuzGx98y/SJ+MD5DqDQ6l03Y8VlkTH1jL+L8cjTDQx7BzxcKsFkB1PgxMtxgnIDNVlLBpXgTUEGCCRWjmtOF4tndHP0/8ScsKpRWUxjaach6rKcKOVDzHq7yw= ARC-Message-Signature: i=1; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.26.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:26:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v8FvDq5cUYW7XqWD0shpF1rWNn8tp72Vhml1RK/Q060=; b=WoxcjpkBkK/L7vgkcvx4i8QJWDURzQ7qi75wvcFtEd418atYuO/PMBIz579KYBeTMn 2hAXOzbfI/nYkL9y+s9ln7Sv2to+5rwrXCCiAG++ZOjZ2Wzh8mKPONRQUlCvJLU0KBza Wal2seguVVBFt/anfaCslytLP7hqD3ORAZUEs6uioCV+cjlyJbyEuh0s9SPdJIkMkmdQ oiPX0BBEZySWxHhjhz6U7jwkYT+j9aULYFLvfFKAjIrUxztYJsbFAk6lhKNXvtEkGCY5 ZF23Oj6gkwiP3xcw7FKVEeK9dHm2Upm+djf9d9a6ytOx/kXyKCENRoA0D2ZMXK/YjpeD y05w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v8FvDq5cUYW7XqWD0shpF1rWNn8tp72Vhml1RK/Q060=; b=28O+uqtL89gY1NQRZBf5d+J5hpSUB93dWcUo5ZDRtknNP88J88Z5AVhPsdCENPf31F lk0wKbjhCmZ9kKO7MfojTjhnf4r7SiXYzg5yWLxcKcyiEzh5C2anaOuLqCrJjLU8n9St 1NUIZJUDPlyDq2cQ9v0FupEziLizhkWvZBmt9yw2qk0DQWSR2p09/plpOpXwZ+mOswSn XOtEdSX06LmsY6OO44qG1Jq2dTYW41kGfUkom6liX+ItTCwHBPDdtn9H6cFu76H+wYNv qD2KIroT2XfROLBje8JLGmjmFlkQrrSnUH9bdW+DWZhqJV6sjU6elZRIlg3jjtOd7/C6 35yg== X-Gm-Message-State: AO0yUKVhApc6aJ/xFNiBbwfEct/sy8IZkczVsNYjxVkNIXl8bgoN2h7Z QzqpxPZ2xGKd9ycUYTyCpDsfywMhRO+a89jRu4g= X-Google-Smtp-Source: AK7set8vnoeFr+VIxEtmE4Oj4UBXERF3T2mNwQEOvOAD9t9Sab2og0VtmK54vIDernNVer0ZDEETZA== X-Received: by 2002:a17:902:e851:b0:19b:c2d:1222 with SMTP id t17-20020a170902e85100b0019b0c2d1222mr28956836plg.52.1677475606022; Sun, 26 Feb 2023 21:26:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 35/76] target/m68k: Drop tcg_temp_free Date: Sun, 26 Feb 2023 19:24:24 -1000 Message-Id: <20230227052505.352889-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475929627100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/m68k/translate.c | 181 ---------------------------------------- 1 file changed, 181 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index d7237b6a99..3055d2d246 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -138,7 +138,6 @@ static void delay_set_areg(DisasContext *s, unsigned re= gno, { if (s->writeback_mask & (1 << regno)) { if (give_temp) { - tcg_temp_free(s->writeback[regno]); s->writeback[regno] =3D val; } else { tcg_gen_mov_i32(s->writeback[regno], val); @@ -163,7 +162,6 @@ static void do_writebacks(DisasContext *s) do { unsigned regno =3D ctz32(mask); tcg_gen_mov_i32(cpu_aregs[regno], s->writeback[regno]); - tcg_temp_free(s->writeback[regno]); mask &=3D mask - 1; } while (mask); } @@ -270,7 +268,6 @@ static void gen_raise_exception(int nr) =20 tmp =3D tcg_const_i32(nr); gen_helper_raise_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); } =20 static void gen_raise_exception_format2(DisasContext *s, int nr, @@ -582,9 +579,7 @@ static void gen_flush_flags(DisasContext *s) gen_ext(t0, t0, s->cc_op - CC_OP_ADDB, 1); tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V); tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0); - tcg_temp_free(t0); tcg_gen_andc_i32(QREG_CC_V, t1, QREG_CC_V); - tcg_temp_free(t1); break; =20 case CC_OP_SUBB: @@ -599,9 +594,7 @@ static void gen_flush_flags(DisasContext *s) gen_ext(t0, t0, s->cc_op - CC_OP_SUBB, 1); tcg_gen_xor_i32(t1, QREG_CC_N, t0); tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0); - tcg_temp_free(t0); tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t1); - tcg_temp_free(t1); break; =20 case CC_OP_CMPB: @@ -615,7 +608,6 @@ static void gen_flush_flags(DisasContext *s) tcg_gen_xor_i32(t0, QREG_CC_Z, QREG_CC_N); tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, QREG_CC_N); tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t0); - tcg_temp_free(t0); tcg_gen_mov_i32(QREG_CC_N, QREG_CC_Z); break; =20 @@ -633,7 +625,6 @@ static void gen_flush_flags(DisasContext *s) default: t0 =3D tcg_const_i32(s->cc_op); gen_helper_flush_flags(cpu_env, t0); - tcg_temp_free(t0); s->cc_op_synced =3D 1; break; } @@ -729,14 +720,12 @@ static void gen_partset_reg(int opsize, TCGv reg, TCG= v val) tmp =3D tcg_temp_new(); tcg_gen_ext8u_i32(tmp, val); tcg_gen_or_i32(reg, reg, tmp); - tcg_temp_free(tmp); break; case OS_WORD: tcg_gen_andi_i32(reg, reg, 0xffff0000); tmp =3D tcg_temp_new(); tcg_gen_ext16u_i32(tmp, val); tcg_gen_or_i32(reg, reg, tmp); - tcg_temp_free(tmp); break; case OS_LONG: case OS_SINGLE: @@ -970,12 +959,10 @@ static void gen_fp_move(TCGv_ptr dest, TCGv_ptr src) t32 =3D tcg_temp_new(); tcg_gen_ld16u_i32(t32, src, offsetof(FPReg, l.upper)); tcg_gen_st16_i32(t32, dest, offsetof(FPReg, l.upper)); - tcg_temp_free(t32); =20 t64 =3D tcg_temp_new_i64(); tcg_gen_ld_i64(t64, src, offsetof(FPReg, l.lower)); tcg_gen_st_i64(t64, dest, offsetof(FPReg, l.lower)); - tcg_temp_free_i64(t64); } =20 static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr f= p, @@ -1029,8 +1016,6 @@ static void gen_load_fp(DisasContext *s, int opsize, = TCGv addr, TCGv_ptr fp, default: g_assert_not_reached(); } - tcg_temp_free(tmp); - tcg_temp_free_i64(t64); } =20 static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr = fp, @@ -1084,8 +1069,6 @@ static void gen_store_fp(DisasContext *s, int opsize,= TCGv addr, TCGv_ptr fp, default: g_assert_not_reached(); } - tcg_temp_free(tmp); - tcg_temp_free_i64(t64); } =20 static void gen_ldst_fp(DisasContext *s, int opsize, TCGv addr, @@ -1141,7 +1124,6 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasCon= text *s, int mode, default: g_assert_not_reached(); } - tcg_temp_free(tmp); } return 0; case 1: /* Address register direct. */ @@ -1187,27 +1169,22 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasC= ontext *s, int mode, case OS_BYTE: tmp =3D tcg_const_i32((int8_t)read_im8(env, s)); gen_helper_exts32(cpu_env, fp, tmp); - tcg_temp_free(tmp); break; case OS_WORD: tmp =3D tcg_const_i32((int16_t)read_im16(env, s)); gen_helper_exts32(cpu_env, fp, tmp); - tcg_temp_free(tmp); break; case OS_LONG: tmp =3D tcg_const_i32(read_im32(env, s)); gen_helper_exts32(cpu_env, fp, tmp); - tcg_temp_free(tmp); break; case OS_SINGLE: tmp =3D tcg_const_i32(read_im32(env, s)); gen_helper_extf32(cpu_env, fp, tmp); - tcg_temp_free(tmp); break; case OS_DOUBLE: t64 =3D tcg_const_i64(read_im64(env, s)); gen_helper_extf64(cpu_env, fp, t64); - tcg_temp_free_i64(t64); break; case OS_EXTENDED: if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) { @@ -1216,10 +1193,8 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasCo= ntext *s, int mode, } tmp =3D tcg_const_i32(read_im32(env, s) >> 16); tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper)); - tcg_temp_free(tmp); t64 =3D tcg_const_i64(read_im64(env, s)); tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower)); - tcg_temp_free_i64(t64); break; case OS_PACKED: /* @@ -1415,7 +1390,6 @@ static void gen_cc_cond(DisasCompare *c, DisasContext= *s, int cond) tmp2 =3D tcg_temp_new(); tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V); tcg_gen_or_i32(tmp, tmp, tmp2); - tcg_temp_free(tmp2); tcond =3D TCG_COND_LT; break; } @@ -1495,7 +1469,6 @@ DISAS_INSN(scc) =20 tcg_gen_neg_i32(tmp, tmp); DEST_EA(env, insn, OS_BYTE, tmp, NULL); - tcg_temp_free(tmp); } =20 DISAS_INSN(dbcc) @@ -1562,7 +1535,6 @@ DISAS_INSN(mulw) tcg_gen_mul_i32(tmp, tmp, src); tcg_gen_mov_i32(reg, tmp); gen_logic_cc(s, tmp, OS_LONG); - tcg_temp_free(tmp); } =20 DISAS_INSN(divw) @@ -1693,7 +1665,6 @@ static void bcd_add(TCGv dest, TCGv src) tcg_gen_andi_i32(t0, t0, 0x22); tcg_gen_add_i32(dest, t0, t0); tcg_gen_add_i32(dest, dest, t0); - tcg_temp_free(t0); =20 /* * remove the exceeding 0x6 @@ -1701,7 +1672,6 @@ static void bcd_add(TCGv dest, TCGv src) */ =20 tcg_gen_sub_i32(dest, t1, dest); - tcg_temp_free(t1); } =20 static void bcd_sub(TCGv dest, TCGv src) @@ -1750,13 +1720,10 @@ static void bcd_sub(TCGv dest, TCGv src) tcg_gen_andi_i32(t2, t2, 0x22); tcg_gen_add_i32(t0, t2, t2); tcg_gen_add_i32(t0, t0, t2); - tcg_temp_free(t2); =20 /* return t1 - t0 */ =20 tcg_gen_sub_i32(dest, t1, t0); - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void bcd_flags(TCGv val) @@ -1857,8 +1824,6 @@ DISAS_INSN(nbcd) DEST_EA(env, insn, OS_BYTE, dest, &addr); =20 bcd_flags(dest); - - tcg_temp_free(dest); } =20 DISAS_INSN(addsub) @@ -1897,7 +1862,6 @@ DISAS_INSN(addsub) } else { gen_partset_reg(opsize, DREG(insn, 9), dest); } - tcg_temp_free(dest); } =20 /* Reverse the order of the bits in REG. */ @@ -1934,7 +1898,6 @@ DISAS_INSN(bitop_reg) =20 tmp =3D tcg_const_i32(1); tcg_gen_shl_i32(tmp, tmp, src2); - tcg_temp_free(src2); =20 tcg_gen_and_i32(QREG_CC_Z, src1, tmp); =20 @@ -1952,11 +1915,9 @@ DISAS_INSN(bitop_reg) default: /* btst */ break; } - tcg_temp_free(tmp); if (op) { DEST_EA(env, insn, opsize, dest, &addr); } - tcg_temp_free(dest); } =20 DISAS_INSN(sats) @@ -1976,7 +1937,6 @@ static void gen_push(DisasContext *s, TCGv val) tcg_gen_subi_i32(tmp, QREG_SP, 4); gen_store(s, OS_LONG, tmp, val, IS_USER(s)); tcg_gen_mov_i32(QREG_SP, tmp); - tcg_temp_free(tmp); } =20 static TCGv mreg(int reg) @@ -2052,7 +2012,6 @@ DISAS_INSN(movem) for (i =3D 0; i < 16; i++) { if (mask & (1 << i)) { tcg_gen_mov_i32(mreg(i), r[i]); - tcg_temp_free(r[i]); } } if (mode =3D=3D 3) { @@ -2079,7 +2038,6 @@ DISAS_INSN(movem) tmp =3D tcg_temp_new(); tcg_gen_sub_i32(tmp, cpu_aregs[reg0], incr); gen_store(s, opsize, addr, tmp, IS_USER(s)); - tcg_temp_free(tmp); } else { gen_store(s, opsize, addr, mreg(i), IS_USER(s)); } @@ -2095,9 +2053,6 @@ DISAS_INSN(movem) } } } - - tcg_temp_free(incr); - tcg_temp_free(addr); } =20 DISAS_INSN(movep) @@ -2141,8 +2096,6 @@ DISAS_INSN(movep) } } } - tcg_temp_free(abuf); - tcg_temp_free(dbuf); } =20 DISAS_INSN(bitop_im) @@ -2201,7 +2154,6 @@ DISAS_INSN(bitop_im) break; } DEST_EA(env, insn, opsize, tmp, &addr); - tcg_temp_free(tmp); } } =20 @@ -2224,7 +2176,6 @@ static TCGv gen_get_sr(DisasContext *s) sr =3D tcg_temp_new(); tcg_gen_andi_i32(sr, QREG_SR, 0xffe0); tcg_gen_or_i32(sr, sr, ccr); - tcg_temp_free(ccr); return sr; } =20 @@ -2373,8 +2324,6 @@ DISAS_INSN(arith_im) default: abort(); } - tcg_temp_free(im); - tcg_temp_free(dest); } =20 DISAS_INSN(cas) @@ -2430,8 +2379,6 @@ DISAS_INSN(cas) gen_update_cc_cmp(s, load, cmp, opsize); gen_partset_reg(opsize, DREG(ext, 0), load); =20 - tcg_temp_free(load); - switch (extract32(insn, 3, 3)) { case 3: /* Indirect postincrement. */ tcg_gen_addi_i32(AREG(insn, 0), addr, opsize_bytes(opsize)); @@ -2487,7 +2434,6 @@ DISAS_INSN(cas2w) } else { gen_helper_cas2w(cpu_env, regs, addr1, addr2); } - tcg_temp_free(regs); =20 /* Note that cas2w also assigned to env->cc_op. */ s->cc_op =3D CC_OP_CMPW; @@ -2538,7 +2484,6 @@ DISAS_INSN(cas2l) } else { gen_helper_cas2l(cpu_env, regs, addr1, addr2); } - tcg_temp_free(regs); =20 /* Note that cas2l also assigned to env->cc_op. */ s->cc_op =3D CC_OP_CMPL; @@ -2610,7 +2555,6 @@ DISAS_INSN(negx) z =3D tcg_const_i32(0); tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z); tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, z, z, QREG_CC_N, QREG_CC_X); - tcg_temp_free(z); gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); =20 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1); @@ -2658,7 +2602,6 @@ DISAS_INSN(clr) opsize =3D insn_opsize(insn); DEST_EA(env, insn, opsize, zero, NULL); gen_logic_cc(s, zero, opsize); - tcg_temp_free(zero); } =20 DISAS_INSN(move_from_ccr) @@ -2684,7 +2627,6 @@ DISAS_INSN(neg) gen_update_cc_add(dest, src1, opsize); tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, dest, 0); DEST_EA(env, insn, opsize, dest, &addr); - tcg_temp_free(dest); } =20 DISAS_INSN(move_to_ccr) @@ -2719,8 +2661,6 @@ DISAS_INSN(swap) tcg_gen_shli_i32(src1, reg, 16); tcg_gen_shri_i32(src2, reg, 16); tcg_gen_or_i32(reg, src1, src2); - tcg_temp_free(src2); - tcg_temp_free(src1); gen_logic_cc(s, reg, OS_LONG); } =20 @@ -2763,7 +2703,6 @@ DISAS_INSN(ext) else tcg_gen_mov_i32(reg, tmp); gen_logic_cc(s, tmp, OS_LONG); - tcg_temp_free(tmp); } =20 DISAS_INSN(tst) @@ -2808,7 +2747,6 @@ DISAS_INSN(tas) tcg_gen_atomic_fetch_or_tl(src1, addr, tcg_constant_tl(0x80), IS_USER(s), MO_SB); gen_logic_cc(s, src1, OS_BYTE); - tcg_temp_free(src1); =20 switch (mode) { case 3: /* Indirect postincrement. */ @@ -2897,7 +2835,6 @@ static void gen_link(DisasContext *s, uint16_t insn, = int32_t offset) tcg_gen_mov_i32(reg, tmp); } tcg_gen_addi_i32(QREG_SP, tmp, offset); - tcg_temp_free(tmp); } =20 DISAS_INSN(link) @@ -2928,8 +2865,6 @@ DISAS_INSN(unlk) tmp =3D gen_load(s, OS_LONG, src, 0, IS_USER(s)); tcg_gen_mov_i32(reg, tmp); tcg_gen_addi_i32(QREG_SP, src, 4); - tcg_temp_free(src); - tcg_temp_free(tmp); } =20 #if defined(CONFIG_SOFTMMU) @@ -2969,10 +2904,8 @@ DISAS_INSN(rtr) tcg_gen_addi_i32(sp, QREG_SP, 2); tmp =3D gen_load(s, OS_LONG, sp, 0, IS_USER(s)); tcg_gen_addi_i32(QREG_SP, sp, 4); - tcg_temp_free(sp); =20 gen_set_sr(s, ccr, true); - tcg_temp_free(ccr); =20 gen_jmp(s, tmp); } @@ -3051,9 +2984,7 @@ DISAS_INSN(addsubq) } gen_update_cc_add(dest, val, opsize); } - tcg_temp_free(val); DEST_EA(env, insn, opsize, dest, &addr); - tcg_temp_free(dest); } =20 DISAS_INSN(branch) @@ -3131,7 +3062,6 @@ DISAS_INSN(or) gen_partset_reg(opsize, DREG(insn, 9), dest); } gen_logic_cc(s, dest, opsize); - tcg_temp_free(dest); } =20 DISAS_INSN(suba) @@ -3166,7 +3096,6 @@ static inline void gen_subx(DisasContext *s, TCGv src= , TCGv dest, int opsize) tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest); tcg_gen_xor_i32(tmp, dest, src); tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, tmp); - tcg_temp_free(tmp); =20 /* Copy the rest of the results into place. */ tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */ @@ -3214,9 +3143,6 @@ DISAS_INSN(subx_mem) gen_subx(s, src, dest, opsize); =20 gen_store(s, opsize, addr_dest, QREG_CC_N, IS_USER(s)); - - tcg_temp_free(dest); - tcg_temp_free(src); } =20 DISAS_INSN(mov3q) @@ -3230,7 +3156,6 @@ DISAS_INSN(mov3q) src =3D tcg_const_i32(val); gen_logic_cc(s, src, OS_LONG); DEST_EA(env, insn, OS_LONG, src, NULL); - tcg_temp_free(src); } =20 DISAS_INSN(cmp) @@ -3290,7 +3215,6 @@ DISAS_INSN(eor) tcg_gen_xor_i32(dest, src, DREG(insn, 9)); gen_logic_cc(s, dest, opsize); DEST_EA(env, insn, opsize, dest, &addr); - tcg_temp_free(dest); } =20 static void do_exg(TCGv reg1, TCGv reg2) @@ -3299,7 +3223,6 @@ static void do_exg(TCGv reg1, TCGv reg2) tcg_gen_mov_i32(temp, reg1); tcg_gen_mov_i32(reg1, reg2); tcg_gen_mov_i32(reg2, temp); - tcg_temp_free(temp); } =20 DISAS_INSN(exg_dd) @@ -3342,7 +3265,6 @@ DISAS_INSN(and) gen_partset_reg(opsize, reg, dest); } gen_logic_cc(s, dest, opsize); - tcg_temp_free(dest); } =20 DISAS_INSN(adda) @@ -3376,7 +3298,6 @@ static inline void gen_addx(DisasContext *s, TCGv src= , TCGv dest, int opsize) tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src); tcg_gen_xor_i32(tmp, dest, src); tcg_gen_andc_i32(QREG_CC_V, QREG_CC_V, tmp); - tcg_temp_free(tmp); =20 /* Copy the rest of the results into place. */ tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */ @@ -3424,9 +3345,6 @@ DISAS_INSN(addx_mem) gen_addx(s, src, dest, opsize); =20 gen_store(s, opsize, addr_dest, QREG_CC_N, IS_USER(s)); - - tcg_temp_free(dest); - tcg_temp_free(src); } =20 static inline void shift_im(DisasContext *s, uint16_t insn, int opsize) @@ -3460,7 +3378,6 @@ static inline void shift_im(DisasContext *s, uint16_t= insn, int opsize) tcg_gen_sari_i32(QREG_CC_V, reg, bits - 1); tcg_gen_sari_i32(t0, reg, bits - count - 1); tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, t0); - tcg_temp_free(t0); } tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V); } @@ -3518,7 +3435,6 @@ static inline void shift_reg(DisasContext *s, uint16_= t insn, int opsize) tcg_gen_shri_i32(QREG_CC_C, QREG_CC_N, bits); tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C, s32, zero, zero, QREG_CC_C); - tcg_temp_free(zero); } tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); =20 @@ -3539,7 +3455,6 @@ static inline void shift_reg(DisasContext *s, uint16_= t insn, int opsize) TCGv_i64 tt =3D tcg_const_i64(32); /* if shift is greater than 32, use 32 */ tcg_gen_movcond_i64(TCG_COND_GT, s64, s64, tt, tt, s64); - tcg_temp_free_i64(tt); /* Sign extend the input to 64 bits; re-do the shift. */ tcg_gen_ext_i32_i64(t64, reg); tcg_gen_shl_i64(s64, t64, s64); @@ -3571,10 +3486,6 @@ static inline void shift_reg(DisasContext *s, uint16= _t insn, int opsize) gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); =20 - tcg_temp_free(s32); - tcg_temp_free_i64(s64); - tcg_temp_free_i64(t64); - /* Write back the result. */ gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N); set_cc_op(s, CC_OP_FLAGS); @@ -3735,25 +3646,20 @@ static TCGv rotate_x(TCGv reg, TCGv shift, int left= , int size) /* shx =3D shx < 0 ? size : shx; */ zero =3D tcg_const_i32(0); tcg_gen_movcond_i32(TCG_COND_LT, shx, shx, zero, sz, shx); - tcg_temp_free(zero); } else { tcg_gen_mov_i32(shr, shift); /* shr =3D shift */ tcg_gen_movi_i32(shl, size + 1); tcg_gen_sub_i32(shl, shl, shift); /* shl =3D size + 1 - shift */ tcg_gen_sub_i32(shx, sz, shift); /* shx =3D size - shift */ } - tcg_temp_free_i32(sz); =20 /* reg =3D (reg << shl) | (reg >> shr) | (x << shx); */ =20 tcg_gen_shl_i32(shl, reg, shl); tcg_gen_shr_i32(shr, reg, shr); tcg_gen_or_i32(reg, shl, shr); - tcg_temp_free(shl); - tcg_temp_free(shr); tcg_gen_shl_i32(shx, QREG_CC_X, shx); tcg_gen_or_i32(reg, reg, shx); - tcg_temp_free(shx); =20 /* X =3D (reg >> size) & 1 */ =20 @@ -3787,7 +3693,6 @@ static TCGv rotate32_x(TCGv reg, TCGv shift, int left) /* rotate */ =20 tcg_gen_rotl_i64(t0, t0, shift64); - tcg_temp_free_i64(shift64); =20 /* result is [reg:..:reg:X] */ =20 @@ -3801,7 +3706,6 @@ static TCGv rotate32_x(TCGv reg, TCGv shift, int left) tcg_gen_concat_i32_i64(t0, reg, QREG_CC_X); =20 tcg_gen_rotr_i64(t0, t0, shift64); - tcg_temp_free_i64(shift64); =20 /* result is value: [X:reg:..:reg] */ =20 @@ -3815,17 +3719,13 @@ static TCGv rotate32_x(TCGv reg, TCGv shift, int le= ft) =20 tcg_gen_shli_i32(hi, hi, 1); } - tcg_temp_free_i64(t0); tcg_gen_or_i32(lo, lo, hi); - tcg_temp_free(hi); =20 /* if shift =3D=3D 0, register and X are not affected */ =20 zero =3D tcg_const_i32(0); tcg_gen_movcond_i32(TCG_COND_EQ, X, shift, zero, QREG_CC_X, X); tcg_gen_movcond_i32(TCG_COND_EQ, reg, shift, zero, reg, lo); - tcg_temp_free(zero); - tcg_temp_free(lo); =20 return X; } @@ -3847,9 +3747,7 @@ DISAS_INSN(rotate_im) } else { TCGv X =3D rotate32_x(DREG(insn, 0), shift, left); rotate_x_flags(DREG(insn, 0), X, 32); - tcg_temp_free(X); } - tcg_temp_free(shift); =20 set_cc_op(s, CC_OP_FLAGS); } @@ -3874,9 +3772,7 @@ DISAS_INSN(rotate8_im) } else { TCGv X =3D rotate_x(reg, shift, left, 8); rotate_x_flags(reg, X, 8); - tcg_temp_free(X); } - tcg_temp_free(shift); gen_partset_reg(OS_BYTE, DREG(insn, 0), reg); set_cc_op(s, CC_OP_FLAGS); } @@ -3900,9 +3796,7 @@ DISAS_INSN(rotate16_im) } else { TCGv X =3D rotate_x(reg, shift, left, 16); rotate_x_flags(reg, X, 16); - tcg_temp_free(X); } - tcg_temp_free(shift); gen_partset_reg(OS_WORD, DREG(insn, 0), reg); set_cc_op(s, CC_OP_FLAGS); } @@ -3934,10 +3828,7 @@ DISAS_INSN(rotate_reg) tcg_gen_remu_i32(t1, t0, t1); X =3D rotate32_x(DREG(insn, 0), t1, left); rotate_x_flags(DREG(insn, 0), X, 32); - tcg_temp_free(X); } - tcg_temp_free(t1); - tcg_temp_free(t0); set_cc_op(s, CC_OP_FLAGS); } =20 @@ -3968,10 +3859,7 @@ DISAS_INSN(rotate8_reg) tcg_gen_remu_i32(t1, t0, t1); X =3D rotate_x(reg, t1, left, 8); rotate_x_flags(reg, X, 8); - tcg_temp_free(X); } - tcg_temp_free(t1); - tcg_temp_free(t0); gen_partset_reg(OS_BYTE, DREG(insn, 0), reg); set_cc_op(s, CC_OP_FLAGS); } @@ -4003,10 +3891,7 @@ DISAS_INSN(rotate16_reg) tcg_gen_remu_i32(t1, t0, t1); X =3D rotate_x(reg, t1, left, 16); rotate_x_flags(reg, X, 16); - tcg_temp_free(X); } - tcg_temp_free(t1); - tcg_temp_free(t0); gen_partset_reg(OS_WORD, DREG(insn, 0), reg); set_cc_op(s, CC_OP_FLAGS); } @@ -4026,9 +3911,7 @@ DISAS_INSN(rotate_mem) } else { TCGv X =3D rotate_x(src, shift, left, 16); rotate_x_flags(src, X, 16); - tcg_temp_free(X); } - tcg_temp_free(shift); DEST_EA(env, insn, OS_WORD, src, &addr); set_cc_op(s, CC_OP_FLAGS); } @@ -4069,7 +3952,6 @@ DISAS_INSN(bfext_reg) } else { tcg_gen_shr_i32(dst, tmp, shift); } - tcg_temp_free(shift); } else { /* Immediate width. */ if (ext & 0x800) { @@ -4098,7 +3980,6 @@ DISAS_INSN(bfext_reg) } } =20 - tcg_temp_free(tmp); set_cc_op(s, CC_OP_LOGIC); } =20 @@ -4133,16 +4014,8 @@ DISAS_INSN(bfext_mem) TCGv_i64 tmp =3D tcg_temp_new_i64(); gen_helper_bfextu_mem(tmp, cpu_env, addr, ofs, len); tcg_gen_extr_i64_i32(dest, QREG_CC_N, tmp); - tcg_temp_free_i64(tmp); } set_cc_op(s, CC_OP_LOGIC); - - if (!(ext & 0x20)) { - tcg_temp_free(len); - } - if (!(ext & 0x800)) { - tcg_temp_free(ofs); - } } =20 DISAS_INSN(bfop_reg) @@ -4210,7 +4083,6 @@ DISAS_INSN(bfop_reg) tcg_gen_movi_i32(tofs, ofs); } } - tcg_temp_free(tmp); } set_cc_op(s, CC_OP_LOGIC); =20 @@ -4223,8 +4095,6 @@ DISAS_INSN(bfop_reg) break; case 0x0d00: /* bfffo */ gen_helper_bfffo_reg(DREG(ext, 12), QREG_CC_N, tofs, tlen); - tcg_temp_free(tlen); - tcg_temp_free(tofs); break; case 0x0e00: /* bfset */ tcg_gen_orc_i32(src, src, mask); @@ -4235,7 +4105,6 @@ DISAS_INSN(bfop_reg) default: g_assert_not_reached(); } - tcg_temp_free(mask); } =20 DISAS_INSN(bfop_mem) @@ -4272,7 +4141,6 @@ DISAS_INSN(bfop_mem) t64 =3D tcg_temp_new_i64(); gen_helper_bfffo_mem(t64, cpu_env, addr, ofs, len); tcg_gen_extr_i64_i32(DREG(ext, 12), QREG_CC_N, t64); - tcg_temp_free_i64(t64); break; case 0x0e00: /* bfset */ gen_helper_bfset_mem(QREG_CC_N, cpu_env, addr, ofs, len); @@ -4284,13 +4152,6 @@ DISAS_INSN(bfop_mem) g_assert_not_reached(); } set_cc_op(s, CC_OP_LOGIC); - - if (!(ext & 0x20)) { - tcg_temp_free(len); - } - if (!(ext & 0x800)) { - tcg_temp_free(ofs); - } } =20 DISAS_INSN(bfins_reg) @@ -4360,11 +4221,7 @@ DISAS_INSN(bfins_reg) tcg_gen_rotr_i32(tmp, tmp, rot); tcg_gen_and_i32(dst, dst, mask); tcg_gen_or_i32(dst, dst, tmp); - - tcg_temp_free(rot); - tcg_temp_free(mask); } - tcg_temp_free(tmp); } =20 DISAS_INSN(bfins_mem) @@ -4392,13 +4249,6 @@ DISAS_INSN(bfins_mem) =20 gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len); set_cc_op(s, CC_OP_LOGIC); - - if (!(ext & 0x20)) { - tcg_temp_free(len); - } - if (!(ext & 0x800)) { - tcg_temp_free(ofs); - } } =20 DISAS_INSN(ff1) @@ -4467,9 +4317,7 @@ DISAS_INSN(chk2) tcg_gen_addi_i32(addr2, addr1, opsize_bytes(opsize)); =20 bound1 =3D gen_load(s, opsize, addr1, 1, IS_USER(s)); - tcg_temp_free(addr1); bound2 =3D gen_load(s, opsize, addr2, 1, IS_USER(s)); - tcg_temp_free(addr2); =20 reg =3D tcg_temp_new(); if (ext & 0x8000) { @@ -4480,9 +4328,6 @@ DISAS_INSN(chk2) =20 gen_flush_flags(s); gen_helper_chk2(cpu_env, reg, bound1, bound2); - tcg_temp_free(reg); - tcg_temp_free(bound1); - tcg_temp_free(bound2); } =20 static void m68k_copy_line(TCGv dst, TCGv src, int index) @@ -4504,10 +4349,6 @@ static void m68k_copy_line(TCGv dst, TCGv src, int i= ndex) tcg_gen_qemu_st64(t0, addr, index); tcg_gen_addi_i32(addr, addr, 8); tcg_gen_qemu_st64(t1, addr, index); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free(addr); } =20 DISAS_INSN(move16_reg) @@ -4528,7 +4369,6 @@ DISAS_INSN(move16_reg) tcg_gen_mov_i32(tmp, AREG(ext, 12)); tcg_gen_addi_i32(AREG(insn, 0), AREG(insn, 0), 16); tcg_gen_addi_i32(AREG(ext, 12), tmp, 16); - tcg_temp_free(tmp); } =20 DISAS_INSN(move16_mem) @@ -4547,8 +4387,6 @@ DISAS_INSN(move16_mem) m68k_copy_line(addr, reg, index); } =20 - tcg_temp_free(addr); - if (((insn >> 3) & 2) =3D=3D 0) { /* (Ay)+ */ tcg_gen_addi_i32(reg, reg, 16); @@ -4633,7 +4471,6 @@ DISAS_INSN(moves) } else { gen_partset_reg(opsize, reg, tmp); } - tcg_temp_free(tmp); } switch (extract32(insn, 3, 3)) { case 3: /* Indirect postincrement. */ @@ -4807,7 +4644,6 @@ DISAS_INSN(pflush) =20 opmode =3D tcg_const_i32((insn >> 3) & 3); gen_helper_pflush(cpu_env, AREG(insn, 0), opmode); - tcg_temp_free(opmode); } =20 DISAS_INSN(ptest) @@ -4820,7 +4656,6 @@ DISAS_INSN(ptest) } is_read =3D tcg_const_i32((insn >> 5) & 1); gen_helper_ptest(cpu_env, AREG(insn, 0), is_read); - tcg_temp_free(is_read); } #endif =20 @@ -4936,7 +4771,6 @@ static void gen_qemu_store_fcr(DisasContext *s, TCGv = addr, int reg) tmp =3D tcg_temp_new(); gen_load_fcr(s, tmp, reg); tcg_gen_qemu_st32(tmp, addr, index); - tcg_temp_free(tmp); } =20 static void gen_qemu_load_fcr(DisasContext *s, TCGv addr, int reg) @@ -4947,7 +4781,6 @@ static void gen_qemu_load_fcr(DisasContext *s, TCGv a= ddr, int reg) tmp =3D tcg_temp_new(); tcg_gen_qemu_ld32u(tmp, addr, index); gen_store_fcr(s, tmp, reg); - tcg_temp_free(tmp); } =20 =20 @@ -4993,7 +4826,6 @@ static void gen_op_fmove_fcr(CPUM68KState *env, Disas= Context *s, } tmp =3D tcg_const_i32(read_im32(env, s)); gen_store_fcr(s, tmp, mask); - tcg_temp_free(tmp); return; } break; @@ -5046,7 +4878,6 @@ static void gen_op_fmove_fcr(CPUM68KState *env, Disas= Context *s, tcg_gen_mov_i32(AREG(insn, 0), addr); } } - tcg_temp_free_i32(addr); } =20 static void gen_op_fmovem(CPUM68KState *env, DisasContext *s, @@ -5107,7 +4938,6 @@ static void gen_op_fmovem(CPUM68KState *env, DisasCon= text *s, if ((insn & 070) =3D=3D 030 || (insn & 070) =3D=3D 040) { tcg_gen_mov_i32(AREG(insn, 0), tmp); } - tcg_temp_free(tmp); } =20 /* @@ -5134,8 +4964,6 @@ DISAS_INSN(fpu) TCGv rom_offset =3D tcg_const_i32(opmode); cpu_dest =3D gen_fp_ptr(REG(ext, 7)); gen_helper_fconst(cpu_env, cpu_dest, rom_offset); - tcg_temp_free_ptr(cpu_dest); - tcg_temp_free(rom_offset); return; } break; @@ -5147,7 +4975,6 @@ DISAS_INSN(fpu) gen_addr_fault(s); } gen_helper_ftst(cpu_env, cpu_src); - tcg_temp_free_ptr(cpu_src); return; case 4: /* fmove to control register. */ case 5: /* fmove from control register. */ @@ -5335,7 +5162,6 @@ DISAS_INSN(fpu) case 0x36: case 0x37: { TCGv_ptr cpu_dest2 =3D gen_fp_ptr(REG(ext, 0)); gen_helper_fsincos(cpu_env, cpu_dest, cpu_dest2, cpu_src); - tcg_temp_free_ptr(cpu_dest2); } break; case 0x38: /* fcmp */ @@ -5347,9 +5173,7 @@ DISAS_INSN(fpu) default: goto undef; } - tcg_temp_free_ptr(cpu_src); gen_helper_ftst(cpu_env, cpu_dest); - tcg_temp_free_ptr(cpu_dest); return; undef: /* FIXME: Is this right for offset addressing modes? */ @@ -5478,7 +5302,6 @@ static void gen_fcc_cond(DisasCompare *c, DisasContex= t *s, int cond) c->tcond =3D TCG_COND_ALWAYS; break; } - tcg_temp_free(fpsr); } =20 static void gen_fjmpcc(DisasContext *s, int cond, TCGLabel *l1) @@ -5526,7 +5349,6 @@ DISAS_INSN(fscc) =20 tcg_gen_neg_i32(tmp, tmp); DEST_EA(env, insn, OS_BYTE, tmp, NULL); - tcg_temp_free(tmp); } =20 DISAS_INSN(ftrapcc) @@ -5585,7 +5407,6 @@ DISAS_INSN(fsave) /* always write IDLE */ TCGv idle =3D tcg_const_i32(0x41000000); DEST_EA(env, insn, OS_LONG, idle, NULL); - tcg_temp_free(idle); } else { disas_undef(env, s, insn); } @@ -5785,7 +5606,6 @@ DISAS_INSN(mac) case 4: /* Pre-decrement. */ tcg_gen_mov_i32(AREG(insn, 0), addr); } - tcg_temp_free(loadval); } } =20 @@ -5859,7 +5679,6 @@ DISAS_INSN(macsr_to_ccr) /* Note that X and C are always cleared. */ tcg_gen_andi_i32(tmp, QREG_MACSR, CCF_N | CCF_Z | CCF_V); gen_helper_set_ccr(cpu_env, tmp); - tcg_temp_free(tmp); set_cc_op(s, CC_OP_FLAGS); } =20 --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.26.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:26:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qqcBoIyNzQ5OuFvj0cjKdjpzjVGCMoFCf537HXgXhq4=; b=mb8lH7VgSwaFh29cS+Sa5koR76p8nr1k4b8g0YtsAvtM6hZCC2IhMegw9f8yQhgQiK mRud/LloH0qdK0ovXX58WhdWEzPwGoNz097gOD8I0x0QlckYrZKHgXo5ejxDE7tcyTDe puLHIpUP6P2Hv0o3HyR88axcR87twyli0NETiXa8cTDj0Ot3cYCwUdfvrHaoNrcftLK0 1D7zagMXj3INaeRQJe0cTZvXOVe1DSp8VmYRtFiN7/il8JR/tgHJwLdmt8pzv4n2yHBb unQg6tpr9yaeiUFTUVixssK/MvKpiQmXNhnOKejs+hr1mYvRm+9zZmyXQsSUhpNQrr8Q QOZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qqcBoIyNzQ5OuFvj0cjKdjpzjVGCMoFCf537HXgXhq4=; b=HNo2tnDN4IrvO57aAMaTJE3GYCOO0ziEDUf3PuFBT8l23BzMOCQgh1503vyP1r0sLc uOL7z1xXaO0VzP9DPJfrQ56c5SklQjJc4BdCQ0Uj/IPgyUEIwkbm6FCDgPhy2gCrWiw4 GO4HY2Q3dFcucqw3YLX/3hV1+wbJnsuFcyamteLmYr0U8S9e6xDcV644K+kIqNeGTdDt zfYVSqp2kVh4DWNtrcV9Ap2fUV9SX/lcD9Vi3MiXhLpboQvlqiTsST58NqWkXPTMLaCw Ggvim4mEBQOdmB6wbFei4FfLjVX7NrKyToZNRiN5W6EK0XFX6kWtQn+IL7izwI+UoIre RajQ== X-Gm-Message-State: AO0yUKVuVccOq8Qmtq9oq/RJ5Ui3kgPZkKCyngOQcJlrs57QdYAMubtb pcy+cdueC47s6v+WE6qYP84OGrXKP+Aeigyfbuyh3A== X-Google-Smtp-Source: AK7set/wZmZI95QKaYlStgV81ZtfQW/KwqLwtyrjn9JNSeZS4Sol7STCDgAvN+oOBmLfk5G9LPfqdg== X-Received: by 2002:a17:903:68f:b0:19c:f1ab:4220 with SMTP id ki15-20020a170903068f00b0019cf1ab4220mr5627289plb.46.1677475608695; Sun, 26 Feb 2023 21:26:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 36/76] target/microblaze: Drop tcg_temp_free Date: Sun, 26 Feb 2023 19:24:25 -1000 Message-Id: <20230227052505.352889-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475893308100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/microblaze/translate.c | 54 ----------------------------------- 1 file changed, 54 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 037a652cb9..eb6bdb49e1 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -104,7 +104,6 @@ static void gen_raise_exception(DisasContext *dc, uint3= 2_t index) TCGv_i32 tmp =3D tcg_const_i32(index); =20 gen_helper_raise_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); dc->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -119,7 +118,6 @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_= t esr_ec) { TCGv_i32 tmp =3D tcg_const_i32(esr_ec); tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, esr)); - tcg_temp_free_i32(tmp); =20 gen_raise_exception_sync(dc, EXCP_HW_EXCP); } @@ -265,8 +263,6 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *a= rg, bool side_effects, imm =3D tcg_const_i32(arg->imm); =20 fn(rd, ra, imm); - - tcg_temp_free_i32(imm); return true; } =20 @@ -312,8 +308,6 @@ static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i3= 2 inb) TCGv_i32 zero =3D tcg_const_i32(0); =20 tcg_gen_add2_i32(out, cpu_msr_c, ina, zero, inb, zero); - - tcg_temp_free_i32(zero); } =20 /* Input and output carry. */ @@ -324,9 +318,6 @@ static void gen_addc(TCGv_i32 out, TCGv_i32 ina, TCGv_i= 32 inb) =20 tcg_gen_add2_i32(tmp, cpu_msr_c, ina, zero, cpu_msr_c, zero); tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero); - - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(zero); } =20 /* Input carry, but no output carry. */ @@ -361,7 +352,6 @@ static void gen_bsra(TCGv_i32 out, TCGv_i32 ina, TCGv_i= 32 inb) TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_andi_i32(tmp, inb, 31); tcg_gen_sar_i32(out, ina, tmp); - tcg_temp_free_i32(tmp); } =20 static void gen_bsrl(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) @@ -369,7 +359,6 @@ static void gen_bsrl(TCGv_i32 out, TCGv_i32 ina, TCGv_i= 32 inb) TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_andi_i32(tmp, inb, 31); tcg_gen_shr_i32(out, ina, tmp); - tcg_temp_free_i32(tmp); } =20 static void gen_bsll(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) @@ -377,7 +366,6 @@ static void gen_bsll(TCGv_i32 out, TCGv_i32 ina, TCGv_i= 32 inb) TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_andi_i32(tmp, inb, 31); tcg_gen_shl_i32(out, ina, tmp); - tcg_temp_free_i32(tmp); } =20 static void gen_bsefi(TCGv_i32 out, TCGv_i32 ina, int32_t imm) @@ -436,7 +424,6 @@ static void gen_cmp(TCGv_i32 out, TCGv_i32 ina, TCGv_i3= 2 inb) tcg_gen_setcond_i32(TCG_COND_LT, lt, inb, ina); tcg_gen_sub_i32(out, inb, ina); tcg_gen_deposit_i32(out, out, lt, 31, 1); - tcg_temp_free_i32(lt); } =20 static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) @@ -446,7 +433,6 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i= 32 inb) tcg_gen_setcond_i32(TCG_COND_LTU, lt, inb, ina); tcg_gen_sub_i32(out, inb, ina); tcg_gen_deposit_i32(out, out, lt, 31, 1); - tcg_temp_free_i32(lt); } =20 DO_TYPEA(cmp, false, gen_cmp) @@ -513,21 +499,18 @@ static void gen_mulh(TCGv_i32 out, TCGv_i32 ina, TCGv= _i32 inb) { TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_muls2_i32(tmp, out, ina, inb); - tcg_temp_free_i32(tmp); } =20 static void gen_mulhu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_mulu2_i32(tmp, out, ina, inb); - tcg_temp_free_i32(tmp); } =20 static void gen_mulhsu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_mulsu2_i32(tmp, out, ina, inb); - tcg_temp_free_i32(tmp); } =20 DO_TYPEA_CFG(mul, use_hw_mul, false, tcg_gen_mul_i32) @@ -569,9 +552,6 @@ static void gen_rsubc(TCGv_i32 out, TCGv_i32 ina, TCGv_= i32 inb) tcg_gen_not_i32(tmp, ina); tcg_gen_add2_i32(tmp, cpu_msr_c, tmp, zero, cpu_msr_c, zero); tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero); - - tcg_temp_free_i32(zero); - tcg_temp_free_i32(tmp); } =20 /* No input or output carry. */ @@ -588,8 +568,6 @@ static void gen_rsubkc(TCGv_i32 out, TCGv_i32 ina, TCGv= _i32 inb) tcg_gen_not_i32(nota, ina); tcg_gen_add_i32(out, inb, nota); tcg_gen_add_i32(out, out, cpu_msr_c); - - tcg_temp_free_i32(nota); } =20 DO_TYPEA(rsub, true, gen_rsub) @@ -618,8 +596,6 @@ static void gen_src(TCGv_i32 out, TCGv_i32 ina) tcg_gen_mov_i32(tmp, cpu_msr_c); tcg_gen_andi_i32(cpu_msr_c, ina, 1); tcg_gen_extract2_i32(out, ina, tmp, 1); - - tcg_temp_free_i32(tmp); } =20 static void gen_srl(TCGv_i32 out, TCGv_i32 ina) @@ -659,7 +635,6 @@ static TCGv compute_ldst_addr_typea(DisasContext *dc, i= nt ra, int rb) TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_add_i32(tmp, cpu_R[ra], cpu_R[rb]); tcg_gen_extu_i32_tl(ret, tmp); - tcg_temp_free_i32(tmp); } else if (ra) { tcg_gen_extu_i32_tl(ret, cpu_R[ra]); } else if (rb) { @@ -683,7 +658,6 @@ static TCGv compute_ldst_addr_typeb(DisasContext *dc, i= nt ra, int imm) TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_addi_i32(tmp, cpu_R[ra], imm); tcg_gen_extu_i32_tl(ret, tmp); - tcg_temp_free_i32(tmp); } else { tcg_gen_movi_tl(ret, (uint32_t)imm); } @@ -772,8 +746,6 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr= , MemOp mop, #endif =20 tcg_gen_qemu_ld_i32(reg_for_write(dc, rd), addr, mem_index, mop); - - tcg_temp_free(addr); return true; } =20 @@ -879,7 +851,6 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg) =20 tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL); tcg_gen_mov_tl(cpu_res_addr, addr); - tcg_temp_free(addr); =20 if (arg->rd) { tcg_gen_mov_i32(cpu_R[arg->rd], cpu_res_val); @@ -925,8 +896,6 @@ static bool do_store(DisasContext *dc, int rd, TCGv add= r, MemOp mop, #endif =20 tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop); - - tcg_temp_free(addr); return true; } =20 @@ -1040,7 +1009,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *ar= g) * In either case, addr is no longer needed. */ tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_fail); - tcg_temp_free(addr); =20 /* * Compare the value loaded during lwx with current contents of @@ -1053,7 +1021,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *ar= g) dc->mem_index, MO_TEUL); =20 tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail); - tcg_temp_free_i32(tval); =20 /* Success */ tcg_gen_movi_i32(cpu_msr_c, 0); @@ -1155,8 +1122,6 @@ static bool do_bcc(DisasContext *dc, int dest_rb, int= dest_imm, tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget, reg_for_read(dc, ra), zero, cpu_btarget, next); - tcg_temp_free_i32(zero); - tcg_temp_free_i32(next); =20 return true; } @@ -1274,7 +1239,6 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *ar= g) tcg_gen_st_i32(tmp_1, cpu_env, -offsetof(MicroBlazeCPU, env) +offsetof(CPUState, halted)); - tcg_temp_free_i32(tmp_1); =20 tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); =20 @@ -1345,7 +1309,6 @@ static void msr_read(DisasContext *dc, TCGv_i32 d) t =3D tcg_temp_new_i32(); tcg_gen_muli_i32(t, cpu_msr_c, MSR_C | MSR_CC); tcg_gen_or_i32(d, cpu_msr, t); - tcg_temp_free_i32(t); } =20 static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set) @@ -1442,8 +1405,6 @@ static bool trans_mts(DisasContext *dc, arg_mts *arg) TCGv_i32 tmp_reg =3D tcg_const_i32(arg->rs & 7); =20 gen_helper_mmu_write(cpu_env, tmp_ext, tmp_reg, src); - tcg_temp_free_i32(tmp_reg); - tcg_temp_free_i32(tmp_ext); } break; =20 @@ -1467,7 +1428,6 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg) TCGv_i64 t64 =3D tcg_temp_new_i64(); tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); tcg_gen_extrh_i64_i32(dest, t64); - tcg_temp_free_i64(t64); } return true; #ifndef CONFIG_USER_ONLY @@ -1498,7 +1458,6 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg) TCGv_i64 t64 =3D tcg_temp_new_i64(); tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); tcg_gen_extrl_i64_i32(dest, t64); - tcg_temp_free_i64(t64); } break; case SR_ESR: @@ -1532,8 +1491,6 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg) TCGv_i32 tmp_reg =3D tcg_const_i32(arg->rs & 7); =20 gen_helper_mmu_read(dest, cpu_env, tmp_ext, tmp_reg); - tcg_temp_free_i32(tmp_reg); - tcg_temp_free_i32(tmp_ext); } break; #endif @@ -1559,8 +1516,6 @@ static void do_rti(DisasContext *dc) tcg_gen_andi_i32(tmp, tmp, MSR_VM | MSR_UM); tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM)); tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); - - tcg_temp_free_i32(tmp); } =20 static void do_rtb(DisasContext *dc) @@ -1571,8 +1526,6 @@ static void do_rtb(DisasContext *dc) tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM | MSR_BIP)); tcg_gen_andi_i32(tmp, tmp, (MSR_VM | MSR_UM)); tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); - - tcg_temp_free_i32(tmp); } =20 static void do_rte(DisasContext *dc) @@ -1584,8 +1537,6 @@ static void do_rte(DisasContext *dc) tcg_gen_andi_i32(tmp, tmp, (MSR_VM | MSR_UM)); tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM | MSR_EIP)); tcg_gen_or_i32(cpu_msr, cpu_msr, tmp); - - tcg_temp_free_i32(tmp); } =20 /* Insns connected to FSL or AXI stream attached devices. */ @@ -1606,8 +1557,6 @@ static bool do_get(DisasContext *dc, int rd, int rb, = int imm, int ctrl) =20 t_ctrl =3D tcg_const_i32(ctrl); gen_helper_get(reg_for_write(dc, rd), t_id, t_ctrl); - tcg_temp_free_i32(t_id); - tcg_temp_free_i32(t_ctrl); return true; } =20 @@ -1638,8 +1587,6 @@ static bool do_put(DisasContext *dc, int ra, int rb, = int imm, int ctrl) =20 t_ctrl =3D tcg_const_i32(ctrl); gen_helper_put(t_id, t_ctrl, reg_for_read(dc, ra)); - tcg_temp_free_i32(t_id); - tcg_temp_free_i32(t_ctrl); return true; } =20 @@ -1704,7 +1651,6 @@ static void mb_tr_translate_insn(DisasContextBase *dc= b, CPUState *cs) } =20 if (dc->r0) { - tcg_temp_free_i32(dc->r0); dc->r0 =3D NULL; dc->r0_set =3D false; } --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677475776; cv=none; d=zohomail.com; s=zohoarc; b=OtNGfcFMvXzMx73ZDsWcvms+LmGe544orR9p99zafqN6cxOrprbuczm6eAFUK2cLXufJgmGYp+jk16TmFGRl0kg7mcW+KfQB2Za9GrHNvqwwCUBX5fzEgPhOQXoqr+EMRhHqbm6tivYYl3DDXfT69vyhYd5TAy5Fb0szbBbqIjE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677475776; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.26.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:26:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TUvgLx5xhTwjb7hREopkObqZZiBh0MpycGbgHAh1Sr8=; b=ufm0rY5t9OPCPFAHVMiiEBR7CFHrxv13TfsrWHaYNIuzAcSfRUPX6OkiCl7v0S/TRi 4G6nczxCXULKrmBgauoMIuEOBNvYqmyobV2OA+57CPW/d24+1MtqISgCxnj3Sc0Gxm6g C7VFrN2BdYKxnMUhO2nIV0xcQSHTezC4/O5MtWIxubX7J4vDeKpEEP8gaSiIL2CMQr2L XmyDl8Hupa3CxL6aCzTcl4XmDeBRf/UoXHQmozE59hQxNcY7KYzJA+7WRzeXjIkisb1O vuscqx0Z2Zhm1TgTOTBhCIQOzE3FGNIRjuZUroU20K8Jnt03mKU4ekGjIXc7g4toxdjZ aNCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TUvgLx5xhTwjb7hREopkObqZZiBh0MpycGbgHAh1Sr8=; b=e3DapuVoqoyF6KwtDRZGNAg8rNLnFbyOdLpA5w8zbzUcB/KFZCssAwx+3aHnhqtKL5 7ZKahD50r7Jvc3hupEf3X+B5p9LBpjLijdFf9GUIKVGjdo+CpbGGiSeKUAaoE3xJzlKM 9wjQ/48V742AZC574bv16/9KrxRFlBqCwI8J6v+uFnFhRIC2f+4guiDAnwPbZeh/ihG+ sWLFK3dTYVltj+RLmEcLcZ/wKp31A8UggjDzPmwMEF29TK+AvYwApofbkl87pFt9gnNO fTuQbrX1iLHUArcmF9Q4aj6PSVlqh/VJbNFLQeakRZ4SuAHhMlAXaM53WZt55uPlc3CO mA6Q== X-Gm-Message-State: AO0yUKVD9axmdplud48g7mQu6rut7Fb9w5m8w9EzECp550anEASiK80o G+2GekvkJ6x/GOktzijKtmamYUTHut7gdZk9z1Youg== X-Google-Smtp-Source: AK7set/1rGKakzDJ/P1PwHrd6qOvoD2tuf790EKO4f+4b0OqSPR0jRU5iA+37bKv9d0P6haA8+B+Jg== X-Received: by 2002:a17:903:42cd:b0:19c:d452:b282 with SMTP id jy13-20020a17090342cd00b0019cd452b282mr9042209plb.12.1677475611555; Sun, 26 Feb 2023 21:26:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 37/76] target/mips: Drop tcg_temp_free from micromips_translate.c.inc Date: Sun, 26 Feb 2023 19:24:26 -1000 Message-Id: <20230227052505.352889-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x641.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475776737100006 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/mips/tcg/micromips_translate.c.inc | 8 -------- 1 file changed, 8 deletions(-) diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/mi= cromips_translate.c.inc index 632895cc9e..23f80d4315 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -724,9 +724,6 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32= _t opc, int reglist, break; #endif } - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free_i32(t2); } =20 =20 @@ -1018,8 +1015,6 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t= opc, int rd, break; #endif } - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, in= t rs) @@ -1067,7 +1062,6 @@ static void gen_pool32axf(CPUMIPSState *env, DisasCon= text *ctx, int rt, int rs) =20 gen_load_gpr(t0, rt); gen_mtc0(ctx, t0, rs, (ctx->opcode >> 11) & 0x7); - tcg_temp_free(t0); } break; #endif @@ -1276,7 +1270,6 @@ static void gen_pool32axf(CPUMIPSState *env, DisasCon= text *ctx, int rt, int rs) * mode. */ ctx->base.is_jmp =3D DISAS_STOP; - tcg_temp_free(t0); } break; case EI: @@ -1293,7 +1286,6 @@ static void gen_pool32axf(CPUMIPSState *env, DisasCon= text *ctx, int rt, int rs) */ gen_save_pc(ctx->base.pc_next + 4); ctx->base.is_jmp =3D DISAS_EXIT; - tcg_temp_free(t0); } break; default: --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677475879; cv=none; d=zohomail.com; s=zohoarc; b=c+sztfNvXdHKh1zDMjCPZ+r0KtJXCMApdiriZAGGJ8ZAG6rpc3M6CXvhK8IxomtgXY7nt+8+gM5zdYtIPFHK3KJWb9NQa6eMRTLPGjnUatavfH2NxRAboam0sv177ymnGtHCfWP4udiKaIA01MlzZhU3+56IOEJFXC2rSEIxke4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677475879; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=b6y4zpHlwmASZL3Wsq/COyCHbhwEv63XD2IWNIuyt6k=; b=ZLz0pjMyyyd91y8HH5spui3AE64uJcF5sW5TMoWgDI4jS62GpLT6mBgDBehzQNU124Lw1DnAo1xfMGEzqx4pyZpBCYgRzO4T3wHeAd8yzz0W2RfkSxwqanaF+Xoa+F4ijkcjlRDPg88ttfWynISDyjEk5nIlCvomHlBm2qTYXyM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677475879683217.02669799150453; Sun, 26 Feb 2023 21:31:19 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW2i-0002jv-5Q; Mon, 27 Feb 2023 00:27:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW2Q-0000ZT-Bf for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:27:02 -0500 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW2J-0007zy-Ia for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:26:58 -0500 Received: by mail-pj1-x102f.google.com with SMTP id gi3-20020a17090b110300b0023762f642dcso5008490pjb.4 for ; Sun, 26 Feb 2023 21:26:54 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.26.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:26:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b6y4zpHlwmASZL3Wsq/COyCHbhwEv63XD2IWNIuyt6k=; b=YDnEChFGZP6yT99BLe5B2vrbT8rKkEDDJPm8gI44g6SZllPaJM38yCofbRlDlqNfcH mixQ2IGdye33oYHp5P3JMms82cCJewRSMm/nt+KPhMKPBHbk6WIHTxUKT9Fn6y5XbfpW qsmBQtq0WVhdohU4OZyUEJHHV9ZKmjjtxVn+v7FmMoScQSMrCCptgdiE22v2qmfjDwN2 Bo0CMCkF4vTWFOfH5ZOFwlarujWzykrDKuCh+ObjTTm8VFrdNqscp/qdpy7zUoObXis/ yGj+PUTdOaO/X+pGyCYIqNseU+MuzRCAVT7q4EorFjceSIdAy7/LZNNaT7clv1kGS0vz GGYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b6y4zpHlwmASZL3Wsq/COyCHbhwEv63XD2IWNIuyt6k=; b=dSOYUIOeX4nR0dOdBI+Vih6A0/U722VYnyZbL491QMl35e0vgjQRWvsO9sM7AWyjnP bsPzqpx35MHpe6Kij5zZk8f+jby0eYlEiqaDQgH1JA07b1Jvg4aFrsGxZc9Gqp5P2vGa 7ENdHOvUEqCS400P2tMzEpoD25yBfb84nNQXxGhG0r3EG5IEGA6LBgBn2tsjj8c7KVN2 zDIIbmMv3Ig4hGvsGlKfTcL4FGcXykZF3YHEEfYN4BZrpBWseJxccKuEdjUPIKkOL/HS lkN6SGFaHiFSSFAOB5gAxK/RTRxxj3RnU+48BvMhaOdTAmFfUNwO8nM5P63ycwTTg94W iwPg== X-Gm-Message-State: AO0yUKUSTM6gxl1gZ/71zUCUWKatM6RSDJS9d6X1k46jfIU9U6P/cCDw L0sMZhpuDlsA1nkMTv8PEkC6p8v2iNEYeDnOmPs= X-Google-Smtp-Source: AK7set9sf89/GmYsKQ0+GRLBZqTeq5m4AsjpeaWHUeGlTtarBYrCQpSwqG3kh37yxeOj+e9Ym0BYIg== X-Received: by 2002:a17:903:5d0:b0:19c:f096:bbef with SMTP id kf16-20020a17090305d000b0019cf096bbefmr5658932plb.49.1677475614022; Sun, 26 Feb 2023 21:26:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 38/76] target/mips: Drop tcg_temp_free from mips16e_translate.c.inc Date: Sun, 26 Feb 2023 19:24:27 -1000 Message-Id: <20230227052505.352889-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475881244100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/mips/tcg/mips16e_translate.c.inc | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips= 16e_translate.c.inc index 918b15d55c..602f5f0c02 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -280,9 +280,6 @@ static void gen_mips16_save(DisasContext *ctx, =20 tcg_gen_movi_tl(t2, -framesize); gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2); - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } =20 static void gen_mips16_restore(DisasContext *ctx, @@ -386,9 +383,6 @@ static void gen_mips16_restore(DisasContext *ctx, =20 tcg_gen_movi_tl(t2, framesize); gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2); - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } =20 #if defined(TARGET_MIPS64) --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677477108; cv=none; d=zohomail.com; s=zohoarc; b=A9hYu+DSWTRS0Hi6fS9WmoTUkHvoVtryufGgd+kWR9MOHPy2QQ9Z6KDFx0j/1+g2crCVE+45A1Q27HNxQQ8fFr683FbLktVM8SnBobeQMG67tKCmHDnO2mYWEhD6bD8KLKkMC4l/nYxRdQsCJhybyhCB6NyfBhrRSDrlqg2GiW8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677477108; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+mYb7riWV9KcKnyuvmf5HGj/XCuu4SlQJaHS4dBhBKA=; b=TN2l8LvustE3R1ln8OjH1GcKAL0G42ZexqIkc80kNY7/1H+m1cWDW+iai+wb6eTiK4YoqgIljtEs9fvMr3oW4qdgs7wn0nPGQAHYeyFocWT+mhEmu3j7VDDPbtsACILXrn3v7vVpK1eGDgpvdkLVXKakyQhb1MNNKA87UX9U4Uo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167747710870160.17957254236012; Sun, 26 Feb 2023 21:51:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW2d-00028b-5c; Mon, 27 Feb 2023 00:27:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW2Q-0000Ze-C3 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:27:02 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW2L-0007he-QI for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:27:00 -0500 Received: by mail-pj1-x102d.google.com with SMTP id me6-20020a17090b17c600b0023816b0c7ceso913952pjb.2 for ; Sun, 26 Feb 2023 21:26:57 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.26.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:26:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+mYb7riWV9KcKnyuvmf5HGj/XCuu4SlQJaHS4dBhBKA=; b=iBEb0dehBGg22Tu70J3uchC3rNbPpQ01VA4aWW/aGL2c2389JIjYPVdqsb33DC/18N 1r1hnZQeS1OmW1yfjdwsUJxVdB7/HFfdjk0R80RcgF64ADk2XhiqJKom/fQFDxKvR19S U6soW4H98jgS9PiDmcGa9Wb0SrUl9aKljcsYOrtlLi9USthCC7lodbmsSNdyDPJUJp6m me1k24K3eqiRc6Hp6av/lGZ5TZDNOWfqAgBp6DnhbRQSSvTvLIqp0lwf8ctvKjZiW4Tu 0JnFnaOO7ZiW9zA1rNd5MMf+X+j4tVKm3sBxEbgqQZkqwO83EUIjbpZHQ4bW1IlIK0j/ DGOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+mYb7riWV9KcKnyuvmf5HGj/XCuu4SlQJaHS4dBhBKA=; b=LIx5IKIY/XMVqmUzDhh8k58lGZy4+K8uMDOhzktfX5glSI0FcrDIyMaAK0/PDClccg SkGX5354RPyJCiVaZGMc0etg1uKCGEmnlhFnuzmmjhtUx1N882ujR7mjng03HAZ0/dYP 1njHk8os5vFvt5aQBroJFaq19bcPtSWoIkXmc88pHFKisaM/KWOL5nc0ZmH5bQvNJuiU HNJhN9uTZEwu7Nl97EjyqXLpHL5h/I1TDZSQjAQn4ssOLygTffrDtsHwQfus89ky3QHP z+Pr8mfcbQ8e0ic0v2uWwnlZaFrlz5NgrUoFnpxqCFhmOTzaHcWRjvdQkuUvze7ze6rP 1uRA== X-Gm-Message-State: AO0yUKW3hPb/HPLByA1yi3q2YSHaGC/t5CT2920YqsfomuVP4BzvWgC+ gStulcm1gPSi7bw2JHT2TddTfgl77cHsC1I6RBM= X-Google-Smtp-Source: AK7set/P2pI/4HCsxe0TDA7l6prEI85C6wO6VNbLin6c2/nTj0YDisYE3w4jebFWVT/gWgHHEUDsRg== X-Received: by 2002:a17:903:2948:b0:19c:dbce:dce4 with SMTP id li8-20020a170903294800b0019cdbcedce4mr8280933plb.15.1677475616702; Sun, 26 Feb 2023 21:26:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 39/76] target/mips: Drop tcg_temp_free from msa_translate.c Date: Sun, 26 Feb 2023 19:24:28 -1000 Message-Id: <20230227052505.352889-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677477109062100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/mips/tcg/msa_translate.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 1bcdbb1121..220cd3b048 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -217,8 +217,6 @@ static void gen_check_zero_element(TCGv tresult, uint8_= t df, uint8_t wt, /* if some bit is non-zero then some element is zero */ tcg_gen_setcondi_i64(cond, t0, t0, 0); tcg_gen_trunc_i64_tl(tresult, t0); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond) @@ -237,7 +235,6 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, in= t sa, TCGCond cond) tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); tcg_gen_setcondi_i64(cond, t0, t0, 0); tcg_gen_trunc_i64_tl(bcond, t0); - tcg_temp_free_i64(t0); =20 ctx->btarget =3D ctx->base.pc_next + (sa << 2) + 4; =20 @@ -545,8 +542,6 @@ static bool trans_CTCMSA(DisasContext *ctx, arg_msa_elm= *a) gen_load_gpr(telm, a->ws); gen_helper_msa_ctcmsa(cpu_env, telm, tcg_constant_i32(a->wd)); =20 - tcg_temp_free(telm); - return true; } =20 @@ -563,8 +558,6 @@ static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm= *a) gen_helper_msa_cfcmsa(telm, cpu_env, tcg_constant_i32(a->ws)); gen_store_gpr(telm, a->wd); =20 - tcg_temp_free(telm); - return true; } =20 @@ -782,8 +775,6 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i= *a, gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df); gen_msa_ldst(cpu_env, tcg_constant_i32(a->wd), taddr); =20 - tcg_temp_free(taddr); - return true; } =20 --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677485631; cv=none; d=zohomail.com; s=zohoarc; b=E66FnTQrVqL96wfi4G2teXLfNkWmpeggRWy2gQqKSze2daIT0mt52j+trUuVdHhyz0Qd5gcieA+P69CNS72xbW0oCZrVDcdLqlPTJJdUH5DVkDbZ/IlXIerC+vPRMUZPNXtYBAvpjBDlB0eqBIqTLBMJhz/1cWEmH7XEZBx4J3Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677485631; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4kqBfUrEC0hgJZyLTR3qpiXaj+lmTNXQFttN4oATONw=; b=Uk3lnURc45EMWXWl/qZL7tif9oZ+WGh5CpmqshzVGhvBxnUISZEKaGah6l0qhtsMzIOJI+e0cJ39JVEOO1aB7DYR+17OWp1Qljg+pVrpHDNPAPIvzjdQB4HRlfaGATKFQF+y2i1NPn0+xzhj6HoMLJd92K4cTvEqDE/0b9ncx4g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677485631677509.9255098776159; Mon, 27 Feb 2023 00:13:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW5f-000378-HP; Mon, 27 Feb 2023 00:30:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW5O-0002o9-AQ for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:30:07 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW5L-000057-QB for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:30:05 -0500 Received: by mail-pj1-x1036.google.com with SMTP id cp7-20020a17090afb8700b0023756229427so8896094pjb.1 for ; Sun, 26 Feb 2023 21:30:02 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.29.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:30:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4kqBfUrEC0hgJZyLTR3qpiXaj+lmTNXQFttN4oATONw=; b=DMorFQz3rzOt3Ngjk3WkKsBMLyXwoZsGW9pGzH1c//uB6CSUhoyheWlsHyskDdGJIT YjVfrTWJKNBJX78bIx7vcez7m906cGI+tkUM3QKEfMKSWeJzH68KUqKKzpilLIXPlUXW UjbcCEqk+U1SY/lmwX1+Bp84SdQ1LpiOFU+/KSstIH6os2TdcvtjPUdKK5ZGRmm0IDJw S8frZ2XX+9C/MyVRiqy+qQefBY4HDJSAspQoR52WL0B2HRtAqWiA+29MDxvALkRD1dKk uEb3YVsL6kxH86qhiB37lJXA5SBTBU6QztJuovHkTXAbB7i24TGgI3DQj8oFfjKZFXYd 41Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4kqBfUrEC0hgJZyLTR3qpiXaj+lmTNXQFttN4oATONw=; b=oU/MEAcgNZiNlA0V70OlS9zPlINigH/BeVIAvWE3ForRhIoyUGCxy01FpBQDaatvjv 1hcr4R0yNfMpuK4E/8F/Hauh0uku8sSrVBAfder6CJKpU8FH9GE/JiFTgA/oW4MY/rQQ Ff0kwtag3B1RuCAMRCNyA3eM1x2CTQZ4mttPjXbKPMjCACPaC3jbAVhXpcPF3VHqpxGv g5J67btD0Qr5aFYVgDTa5E3iZmM1FRlcup9kK7E6buJUphiMPWxjBeqEhxSbORwgjU7P 8taCF5Mq1S9v4ZOAxu5Q9/Ma3NdJ9RlGcIOCKy30sob/ApBoK9nXULK8oXx2waWTmeCH j/lQ== X-Gm-Message-State: AO0yUKX4UY6PXcRFObwaElZlqFqDqlU1JcDV6DbWlllGKpIKXNbC6YCo oIbgYgnJq/Rz9+kcEepQu4rcgLrkf9e4MiRRSMc= X-Google-Smtp-Source: AK7set+EoI4EvIPcjLSB/+qsxXcYFmP3xcNCAcHk4VskzrKJJGd/ran/A+KGPyQtYbn6fV9Y0Mu7HA== X-Received: by 2002:a17:90b:2248:b0:235:31e9:e793 with SMTP id hk8-20020a17090b224800b0023531e9e793mr8367182pjb.13.1677475801245; Sun, 26 Feb 2023 21:30:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 40/76] target/mips: Drop tcg_temp_free from mxu_translate.c Date: Sun, 26 Feb 2023 19:24:29 -1000 Message-Id: <20230227052505.352889-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677485633269100003 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/mips/tcg/mxu_translate.c | 51 --------------------------------- 1 file changed, 51 deletions(-) diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translat= e.c index f52244e1b2..8703b0cef4 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -513,8 +513,6 @@ static void gen_mxu_s32i2m(DisasContext *ctx) } else if (XRa =3D=3D 16) { gen_store_mxu_cr(t0); } - - tcg_temp_free(t0); } =20 /* @@ -537,8 +535,6 @@ static void gen_mxu_s32m2i(DisasContext *ctx) } =20 gen_store_gpr(t0, Rb); - - tcg_temp_free(t0); } =20 /* @@ -613,9 +609,6 @@ static void gen_mxu_s8ldd(DisasContext *ctx) } =20 gen_store_mxu_gpr(t0, XRa); - - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 /* @@ -664,11 +657,6 @@ static void gen_mxu_d16mul(DisasContext *ctx) } gen_store_mxu_gpr(t3, XRa); gen_store_mxu_gpr(t2, XRd); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(t3); } =20 /* @@ -741,11 +729,6 @@ static void gen_mxu_d16mac(DisasContext *ctx) } gen_store_mxu_gpr(t3, XRa); gen_store_mxu_gpr(t2, XRd); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(t3); } =20 /* @@ -821,15 +804,6 @@ static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx) =20 gen_store_mxu_gpr(t0, XRd); gen_store_mxu_gpr(t1, XRa); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(t3); - tcg_temp_free(t4); - tcg_temp_free(t5); - tcg_temp_free(t6); - tcg_temp_free(t7); } =20 /* @@ -860,9 +834,6 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx) tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_TESL ^ (sel * MO_BSWAP)); =20 gen_store_mxu_gpr(t1, XRa); - - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 =20 @@ -1125,9 +1096,6 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx) tcg_gen_shri_i32(t0, t0, 16); /* finally update the destination */ tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); - - tcg_temp_free(t1); - tcg_temp_free(t0); } else if (unlikely(XRb =3D=3D XRc)) { /* both operands same -> just set destination to one of them */ tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); @@ -1161,9 +1129,6 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx) tcg_gen_shri_i32(t0, t0, 16); /* finally update the destination */ tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); - - tcg_temp_free(t1); - tcg_temp_free(t0); } } =20 @@ -1226,9 +1191,6 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) /* finally update the destination */ tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); } - - tcg_temp_free(t1); - tcg_temp_free(t0); } else if (unlikely(XRb =3D=3D XRc)) { /* both operands same -> just set destination to one of them */ tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); @@ -1266,9 +1228,6 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) /* finally update the destination */ tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); } - - tcg_temp_free(t1); - tcg_temp_free(t0); } } =20 @@ -1384,9 +1343,6 @@ static void gen_mxu_S32ALNI(DisasContext *ctx) tcg_gen_shri_i32(t1, t1, 24); =20 tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); - - tcg_temp_free(t1); - tcg_temp_free(t0); } break; case MXU_OPTN3_PTN2: @@ -1410,9 +1366,6 @@ static void gen_mxu_S32ALNI(DisasContext *ctx) tcg_gen_shri_i32(t1, t1, 16); =20 tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); - - tcg_temp_free(t1); - tcg_temp_free(t0); } break; case MXU_OPTN3_PTN3: @@ -1436,9 +1389,6 @@ static void gen_mxu_S32ALNI(DisasContext *ctx) tcg_gen_shri_i32(t1, t1, 8); =20 tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); - - tcg_temp_free(t1); - tcg_temp_free(t0); } break; case MXU_OPTN3_PTN4: @@ -1598,7 +1548,6 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn) } =20 gen_set_label(l_exit); - tcg_temp_free(t_mxu_cr); } =20 return true; --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.30.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:30:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OzenRWt+IW0b4GMVE6YHj3uhLXPgLUDQLxr6mseKj2c=; b=ZMbeJ8pTEPYETqX2rnqR+7vVOFOc2M4bX6mv0HzhHDKdEFw0LVpWrEzqRNxVZKBxPF 04TCdW8EmDnSS3ICXK6Ouy6zg/ImKhCLxkskrZ/4bR1XFMPPNsEv4XHaHOqbSv+Q6SPG Jp4+jE1GtpUheK8xe+Wx33gNRxRKDaJyWctg2awfu9RBVimy/wNv5p8HfVGSAuO1q7Zr 9k13h8SfNqeSvnsP44FeitwRXHodiFsILPbuS6Y7eO41Ud9NSoI7LNQNm0DJuBDuiRPR sYVdFUeZRINL9VgqQrx6/ZO3lJ1r5wRuAES3m6PBShdCwCQ/6EAav0Px8sQbL+wd95zG t6hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OzenRWt+IW0b4GMVE6YHj3uhLXPgLUDQLxr6mseKj2c=; b=eKcdbcsxWxGke4stRa7voiOaPs8NctlRWyXPubRU7WqRCILmVMpUmehacwSo/tt3KU lCDlWaiyM3zfWS7F+UQCNLR7cXu83VdLkTAwN4dpb7fn1+AHIPyr24zwFzJRGRIVAJ7K FgG17pHClkKAfOsi1oLamcs8lNJGsTbFios5pZ+9wlhj3TPCo9Cjki9qJ1/safOasMx4 xS3ZEXqmy6nBr+rXTMoUkakn6tHVuOcSHtexGqq9yrwxDMd6t7NhwNmWUJUcnNCxClZK /j17wXdlIZBaBvD5iGmqF5DDkfRMIx1ZhQWFr0ntSaIru6SWElYfXCLb1saAbC5FaB8L QPWA== X-Gm-Message-State: AO0yUKWTWt9+H1286ZgP0NR9drdC9RMsI+23P1xA1ukeTe2f1GMOBBKl qIEL/4xtROychk2tozYtAcZUeA89ilo3bon4MoDcGg== X-Google-Smtp-Source: AK7set8p+yOS6PYav/d6IuxV/JfZHk9agtL6P2SDmq+hpfxSpqWxLoRVUpOBGq28BSJuiut+uLenaA== X-Received: by 2002:a17:90a:974b:b0:237:aed6:fff3 with SMTP id i11-20020a17090a974b00b00237aed6fff3mr9088341pjw.44.1677475804202; Sun, 26 Feb 2023 21:30:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 41/76] target/mips: Drop tcg_temp_free from nanomips_translate.c.inc Date: Sun, 26 Feb 2023 19:24:30 -1000 Message-Id: <20230227052505.352889-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476206919100003 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/mips/tcg/nanomips_translate.c.inc | 127 ++--------------------- 1 file changed, 10 insertions(+), 117 deletions(-) diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nan= omips_translate.c.inc index faf6d679bd..b3df7fec40 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -1005,13 +1005,9 @@ static void gen_llwp(DisasContext *ctx, uint32_t bas= e, int16_t offset, tcg_gen_extr_i64_tl(tmp1, tmp2, tval); } gen_store_gpr(tmp1, reg1); - tcg_temp_free(tmp1); gen_store_gpr(tmp2, reg2); - tcg_temp_free(tmp2); tcg_gen_st_i64(tval, cpu_env, offsetof(CPUMIPSState, llval_wp)); - tcg_temp_free_i64(tval); tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, lladdr)); - tcg_temp_free(taddr); } =20 static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, @@ -1084,9 +1080,6 @@ static void gen_save(DisasContext *ctx, uint8_t rt, u= int8_t count, =20 /* adjust stack pointer */ gen_adjust_sp(ctx, -u); - - tcg_temp_free(t0); - tcg_temp_free(va); } =20 static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count, @@ -1110,9 +1103,6 @@ static void gen_restore(DisasContext *ctx, uint8_t rt= , uint8_t count, =20 /* adjust stack pointer */ gen_adjust_sp(ctx, u); - - tcg_temp_free(t0); - tcg_temp_free(va); } =20 static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc, @@ -1232,8 +1222,6 @@ static void gen_compute_branch_nm(DisasContext *ctx, = uint32_t opc, if (insn_bytes =3D=3D 2) { ctx->hflags |=3D MIPS_HFLAG_B16; } - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_pool16c_nanomips_insn(DisasContext *ctx) @@ -1358,7 +1346,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *= env, DisasContext *ctx) } break; } - tcg_temp_free(t0); #endif } else { gen_slt(ctx, OPC_SLTU, rd, rs, rt); @@ -1381,10 +1368,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState = *env, DisasContext *ctx) /* operands of same sign, result different sign */ tcg_gen_setcondi_tl(TCG_COND_LT, t0, t1, 0); gen_store_gpr(t0, rd); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } break; case NM_MUL: @@ -1427,7 +1410,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *= env, DisasContext *ctx) =20 gen_load_gpr(t0, rt); gen_mtc0(ctx, t0, rs, extract32(ctx->opcode, 11, 3)); - tcg_temp_free(t0); } break; case NM_D_E_MT_VPE: @@ -1467,8 +1449,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *= env, DisasContext *ctx) } break; } - - tcg_temp_free(t0); } break; case NM_FORK: @@ -1480,8 +1460,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *= env, DisasContext *ctx) gen_load_gpr(t0, rt); gen_load_gpr(t1, rs); gen_helper_fork(t0, t1); - tcg_temp_free(t0); - tcg_temp_free(t1); } break; case NM_MFTR: @@ -1508,7 +1486,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *= env, DisasContext *ctx) gen_load_gpr(t0, rs); gen_helper_yield(t0, cpu_env, t0); gen_store_gpr(t0, rt); - tcg_temp_free(t0); } break; #endif @@ -1557,11 +1534,6 @@ static void gen_pool32axf_1_5_nanomips_insn(DisasCon= text *ctx, uint32_t opc, gen_reserved_instruction(ctx); break; } - - tcg_temp_free_i32(t0); - - tcg_temp_free(v0_t); - tcg_temp_free(v1_t); } =20 =20 @@ -1682,10 +1654,6 @@ static void gen_pool32axf_1_nanomips_insn(DisasConte= xt *ctx, uint32_t opc, gen_reserved_instruction(ctx); break; } - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(v0_t); } =20 static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc, @@ -1802,8 +1770,6 @@ static void gen_pool32axf_2_multiply(DisasContext *ct= x, uint32_t opc, gen_reserved_instruction(ctx); break; } - - tcg_temp_free_i32(t0); } =20 static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, @@ -1855,10 +1821,8 @@ static void gen_pool32axf_2_nanomips_insn(DisasConte= xt *ctx, uint32_t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case NM_MULT: @@ -1878,8 +1842,6 @@ static void gen_pool32axf_2_nanomips_insn(DisasContex= t *ctx, uint32_t opc, tcg_gen_muls2_i32(t2, t3, t2, t3); tcg_gen_ext_i32_tl(cpu_LO[acc], t2); tcg_gen_ext_i32_tl(cpu_HI[acc], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case NM_EXTRV_W: @@ -1915,10 +1877,8 @@ static void gen_pool32axf_2_nanomips_insn(DisasConte= xt *ctx, uint32_t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case NM_MULTU: @@ -1938,8 +1898,6 @@ static void gen_pool32axf_2_nanomips_insn(DisasContex= t *ctx, uint32_t opc, tcg_gen_mulu2_i32(t2, t3, t2, t3); tcg_gen_ext_i32_tl(cpu_LO[acc], t2); tcg_gen_ext_i32_tl(cpu_HI[acc], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case NM_EXTRV_R_W: @@ -1982,10 +1940,8 @@ static void gen_pool32axf_2_nanomips_insn(DisasConte= xt *ctx, uint32_t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case NM_EXTRV_RS_W: @@ -2027,10 +1983,8 @@ static void gen_pool32axf_2_nanomips_insn(DisasConte= xt *ctx, uint32_t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case NM_EXTRV_S_H: @@ -2045,12 +1999,6 @@ static void gen_pool32axf_2_nanomips_insn(DisasConte= xt *ctx, uint32_t opc, gen_reserved_instruction(ctx); break; } - - tcg_temp_free(t0); - tcg_temp_free(t1); - - tcg_temp_free(v0_t); - tcg_temp_free(v1_t); } =20 static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc, @@ -2162,7 +2110,6 @@ static void gen_pool32axf_4_nanomips_insn(DisasContex= t *ctx, uint32_t opc, gen_load_gpr(tv0, rt); gen_helper_insv(v0_t, cpu_env, v0_t, tv0); gen_store_gpr(v0_t, ret); - tcg_temp_free(tv0); } break; case NM_RADDU_W_QB: @@ -2188,9 +2135,6 @@ static void gen_pool32axf_4_nanomips_insn(DisasContex= t *ctx, uint32_t opc, gen_reserved_instruction(ctx); break; } - - tcg_temp_free(v0_t); - tcg_temp_free(t0); } =20 static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc, @@ -2243,8 +2187,6 @@ static void gen_pool32axf_7_nanomips_insn(DisasContex= t *ctx, uint32_t opc, gen_reserved_instruction(ctx); break; } - tcg_temp_free(t0); - tcg_temp_free(rs_t); } =20 =20 @@ -2304,7 +2246,6 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState = *env, DisasContext *ctx) gen_store_gpr(t0, rt); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; - tcg_temp_free(t0); } break; case NM_EI: @@ -2317,7 +2258,6 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState = *env, DisasContext *ctx) gen_store_gpr(t0, rt); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; - tcg_temp_free(t0); } break; case NM_RDPGPR: @@ -2374,7 +2314,7 @@ static void gen_compute_imm_branch(DisasContext *ctx,= uint32_t opc, /* Unconditional branch */ } else if (rt =3D=3D 0 && imm !=3D 0) { /* Treat as NOP */ - goto out; + return; } else { cond =3D TCG_COND_EQ; } @@ -2384,12 +2324,12 @@ static void gen_compute_imm_branch(DisasContext *ct= x, uint32_t opc, check_nms(ctx); if (imm >=3D 32 && !(ctx->hflags & MIPS_HFLAG_64)) { gen_reserved_instruction(ctx); - goto out; + return; } else if (rt =3D=3D 0 && opc =3D=3D NM_BBEQZC) { /* Unconditional branch */ } else if (rt =3D=3D 0 && opc =3D=3D NM_BBNEZC) { /* Treat as NOP */ - goto out; + return; } else { tcg_gen_shri_tl(t0, t0, imm); tcg_gen_andi_tl(t0, t0, 1); @@ -2404,7 +2344,7 @@ static void gen_compute_imm_branch(DisasContext *ctx,= uint32_t opc, case NM_BNEIC: if (rt =3D=3D 0 && imm =3D=3D 0) { /* Treat as NOP */ - goto out; + return; } else if (rt =3D=3D 0 && imm !=3D 0) { /* Unconditional branch */ } else { @@ -2434,7 +2374,7 @@ static void gen_compute_imm_branch(DisasContext *ctx,= uint32_t opc, default: MIPS_INVAL("Immediate Value Compact branch"); gen_reserved_instruction(ctx); - goto out; + return; } =20 /* branch completion */ @@ -2455,10 +2395,6 @@ static void gen_compute_imm_branch(DisasContext *ctx= , uint32_t opc, =20 gen_goto_tb(ctx, 0, ctx->base.pc_next + 4); } - -out: - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 /* P.BALRSC type nanoMIPS R6 branches: BALRSC and BRSC */ @@ -2488,9 +2424,6 @@ static void gen_compute_nanomips_pbalrsc_branch(Disas= Context *ctx, int rs, /* unconditional branch to register */ tcg_gen_mov_tl(cpu_PC, btarget); tcg_gen_lookup_and_goto_ptr(); - - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 /* nanoMIPS Branches */ @@ -2540,14 +2473,12 @@ static void gen_compute_compact_branch_nm(DisasCont= ext *ctx, uint32_t opc, gen_load_gpr(tbase, rt); tcg_gen_movi_tl(toffset, offset); gen_op_addr_add(ctx, btarget, tbase, toffset); - tcg_temp_free(tbase); - tcg_temp_free(toffset); } break; default: MIPS_INVAL("Compact branch/jump"); gen_reserved_instruction(ctx); - goto out; + return; } =20 if (bcond_compute =3D=3D 0) { @@ -2559,7 +2490,7 @@ static void gen_compute_compact_branch_nm(DisasContex= t *ctx, uint32_t opc, default: MIPS_INVAL("Compact branch/jump"); gen_reserved_instruction(ctx); - goto out; + return; } } else { /* Conditional compact branch */ @@ -2620,7 +2551,7 @@ static void gen_compute_compact_branch_nm(DisasContex= t *ctx, uint32_t opc, default: MIPS_INVAL("Compact conditional branch/jump"); gen_reserved_instruction(ctx); - goto out; + return; } =20 /* branch completion */ @@ -2633,10 +2564,6 @@ static void gen_compute_compact_branch_nm(DisasConte= xt *ctx, uint32_t opc, =20 gen_goto_tb(ctx, 0, ctx->base.pc_next + 4); } - -out: - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 =20 @@ -2664,15 +2591,12 @@ static void gen_compute_branch_cp1_nm(DisasContext = *ctx, uint32_t op, default: MIPS_INVAL("cp1 cond branch"); gen_reserved_instruction(ctx); - goto out; + return; } =20 tcg_gen_trunc_i64_tl(bcond, t0); =20 ctx->btarget =3D btarget; - -out: - tcg_temp_free_i64(t0); } =20 =20 @@ -2709,7 +2633,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int = rs, int rt) break; default: gen_reserved_instruction(ctx); - goto out; + return; } } gen_op_addr_add(ctx, t0, t0, t1); @@ -2799,10 +2723,6 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int= rs, int rt) gen_reserved_instruction(ctx); break; } - -out: - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_pool32f_nanomips_insn(DisasContext *ctx) @@ -3443,7 +3363,6 @@ static void gen_pool32a5_nanomips_insn(DisasContext *= ctx, int opc, gen_helper_precr_sra_ph_w(v1_t, sa_t, v1_t, cpu_gpr[rt]); gen_store_gpr(v1_t, rt); - tcg_temp_free_i32(sa_t); } break; case 1: @@ -3453,7 +3372,6 @@ static void gen_pool32a5_nanomips_insn(DisasContext *= ctx, int opc, gen_helper_precr_sra_r_ph_w(v1_t, sa_t, v1_t, cpu_gpr[rt]); gen_store_gpr(v1_t, rt); - tcg_temp_free_i32(sa_t); } break; } @@ -3536,8 +3454,6 @@ static void gen_pool32a5_nanomips_insn(DisasContext *= ctx, int opc, tcg_gen_movi_tl(tv0, rd >> 3); tcg_gen_movi_tl(tv1, imm); gen_helper_shilo(tv0, tv1, cpu_env); - tcg_temp_free(tv1); - tcg_temp_free(tv0); } break; case NM_MULEQ_S_W_PHL: @@ -3652,10 +3568,6 @@ static void gen_pool32a5_nanomips_insn(DisasContext = *ctx, int opc, gen_reserved_instruction(ctx); break; } - - tcg_temp_free(v2_t); - tcg_temp_free(v1_t); - tcg_temp_free(t0); } =20 static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) @@ -3827,7 +3739,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) =20 tcg_gen_movi_tl(t0, addr); tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, MO_T= ESL); - tcg_temp_free(t0); } break; case NM_SWPC48: @@ -3844,9 +3755,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_load_gpr(t1, rt); =20 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); - - tcg_temp_free(t0); - tcg_temp_free(t1); } break; default: @@ -3908,8 +3816,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_load_gpr(t0, rs); tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, imm); gen_store_gpr(t0, rt); - - tcg_temp_free(t0); } break; case NM_ADDIUNEG: @@ -3965,11 +3871,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *e= nv, DisasContext *ctx) =20 gen_load_gpr(t0, rs); gen_helper_rotx(cpu_gpr[rt], t0, shift, shiftx, stripe); - tcg_temp_free(t0); - - tcg_temp_free_i32(shift); - tcg_temp_free_i32(shiftx); - tcg_temp_free_i32(stripe); } break; case NM_P_INS: @@ -4239,8 +4140,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) MO_UNALN); break; } - tcg_temp_free(t0); - tcg_temp_free(t1); } break; case NM_P_LL: @@ -4432,8 +4331,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) } counter++; } - tcg_temp_free(va); - tcg_temp_free(t1); } break; default: @@ -4454,7 +4351,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_load_gpr(t0, rt); tcg_gen_mov_tl(cpu_gpr[rd], t0); gen_compute_branch_nm(ctx, OPC_BGEZAL, 4, 0, 0, s); - tcg_temp_free(t0); } break; case NM_P_BAL: @@ -4606,7 +4502,6 @@ static int decode_isa_nanomips(CPUMIPSState *env, Dis= asContext *ctx) if (ctx->base.pc_next & 0x1) { TCGv tmp =3D tcg_const_tl(ctx->base.pc_next); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); - tcg_temp_free(tmp); generate_exception_end(ctx, EXCP_AdEL); return 2; } @@ -4941,8 +4836,6 @@ static int decode_isa_nanomips(CPUMIPSState *env, Dis= asContext *ctx) gen_load_gpr(t1, rt); tcg_gen_mov_tl(cpu_gpr[rd], t0); tcg_gen_mov_tl(cpu_gpr[re], t1); - tcg_temp_free(t0); - tcg_temp_free(t1); } break; default: --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677477224; cv=none; d=zohomail.com; s=zohoarc; b=LBwPz62xOh6iyPkUsC4K78ZOG5ke4hcVd5XgRFK1hOPvsChjV1IumB2+p4D3l5GZe3TcKvV5QjOqW5+PvI3ZATIXuUVRsIOwoG+rv6H+m+1CMs5OXn8LHNHFUzDhBD3A8PXDrzLwleVRBrMLCqDJSj/vzYMkyep5Vnevzaq5Nxo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677477224; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.30.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:30:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sG9cqgyja8wZFxXAESY3FM7IJYCLVD/+8GYVn1Dmh4s=; b=yCJe8I2rbmzaLFi6KoVGoDRbmJajAYfrmzGP2oByx1QR+RW3IxRKDNIK+2JbN0PVDc Cak9P5Eo1RKe9V9/NfZh3mQi0o4zskeHB/VMRub3DF/EKf8DCI9L5Is+5QGex0LDjNS1 qOsMa3jDMWjSl2Ob0+a0DfroxADZw1PKRF9DA/wxG+cJ6DcJXTA1vwcrNG1RbF2XiBmz rvx/ddn+G7cMx2z5lzqLl4TYIdWed+mxJFieiVJYbnGQDDgSAs1XG2vDPJ2EeUVLOIC8 fmmkJ8vZC+TpnB1yo9SVw8Do51HPFI9z6l3p9Ft2fdwWuF7MGzkDqtS2N+DDtxMBNGC3 AraQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sG9cqgyja8wZFxXAESY3FM7IJYCLVD/+8GYVn1Dmh4s=; b=1CaJaJ25Fq+jHg3+3qvSd0k4bHH9V975J2/lh0FLGEp+Bpqqc2MeLFsVYeCUiLDGD5 vzgl+X0oGwVg1rYuF5AB3yeU+KEW8Opay1ZQiYJRLLROTfZQy/Y0drbX8ulUzYk95nZo u4Pgg6B2f//k0Sg17AOaYKiGvwmutO+/LZOpkiytiXeb0gybc7+eQtwJsgm9neXtr+Yx J4XFQwcHoUsrOqa0V4JQjeNxmFdOFE0hzF0Mw9NAmUQfAfMi2fhtler86OXCw9/VpFSr y5MEFhEPP7BIlebS0LRWKkbsmnBsW0qvwTrplUzXzpCReUjJOCB9FCgeTNsfOX+vLPdA zHZA== X-Gm-Message-State: AO0yUKXU9Ht7VQlbAJ+dqswIsJwxpDuH9xa2rMWIx80n9cPZaQPJD+Id usd8Vgc5JHcqvTmURNJeJ/qkWDMnBcxY4oBxkC0= X-Google-Smtp-Source: AK7set/7Y86hC0OSR9e1OeIpptIqQgInmxP1c+wdT5ltBAnebfgw1c3P6edprCm7ib0G6xEAFVp0/Q== X-Received: by 2002:a17:90b:3b8d:b0:234:a299:b50a with SMTP id pc13-20020a17090b3b8d00b00234a299b50amr8447764pjb.2.1677475806933; Sun, 26 Feb 2023 21:30:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 42/76] target/mips: Drop tcg_temp_free from octeon_translate.c Date: Sun, 26 Feb 2023 19:24:31 -1000 Message-Id: <20230227052505.352889-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677477225500100003 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/mips/tcg/octeon_translate.c | 23 ----------------------- 1 file changed, 23 deletions(-) diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_tr= anslate.c index 6a207d2e7e..103c304d10 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -40,8 +40,6 @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a) ctx->hflags |=3D MIPS_HFLAG_BC; ctx->btarget =3D ctx->base.pc_next + 4 + a->offset * 4; ctx->hflags |=3D MIPS_HFLAG_BDS32; - - tcg_temp_free(t0); return true; } =20 @@ -61,10 +59,6 @@ static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a) =20 tcg_gen_add_tl(t0, t0, t1); tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff); - - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; } =20 @@ -83,10 +77,6 @@ static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a) gen_load_gpr(t1, a->rt); =20 tcg_gen_mul_i64(cpu_gpr[a->rd], t0, t1); - - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; } =20 @@ -103,8 +93,6 @@ static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a) gen_load_gpr(t0, a->rs); tcg_gen_sextract_tl(t0, t0, a->p, a->lenm1 + 1); gen_store_gpr(t0, a->rt); - tcg_temp_free(t0); - return true; } =20 @@ -121,8 +109,6 @@ static bool trans_CINS(DisasContext *ctx, arg_CINS *a) gen_load_gpr(t0, a->rs); tcg_gen_deposit_z_tl(t0, t0, a->p, a->lenm1 + 1); gen_store_gpr(t0, a->rt); - tcg_temp_free(t0); - return true; } =20 @@ -142,8 +128,6 @@ static bool trans_POP(DisasContext *ctx, arg_POP *a) } tcg_gen_ctpop_tl(t0, t0); gen_store_gpr(t0, a->rd); - tcg_temp_free(t0); - return true; } =20 @@ -167,10 +151,6 @@ static bool trans_SEQNE(DisasContext *ctx, arg_SEQNE *= a) } else { tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0); } - - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; } =20 @@ -194,8 +174,5 @@ static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI = *a) } else { tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm); } - - tcg_temp_free(t0); - return true; } --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677486480; cv=none; d=zohomail.com; s=zohoarc; b=isuxN5uVtc6Ic3KRT3NZNoo4Hv2Z4Tr8iRyZVMgvVN87uMCQaJC3CRi3bnP2XhGu5/BEXWmUZkfO78aNL/Iq5VNxU+LCSvZJT9jkDDAxe5Vo0eJczkCg6yeoei3Bzao8e3FoVNhMwe5mYpdsIK93aGnr+55qRs29bDsMx19gANQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677486480; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YHoTHrUgBZpaOPEfBJAi/HMPT06pVs2AARTKGv//H+s=; b=FWrSZjs74jY7rJuL2aDRueknhQmq/0wS3SfHRh2UqGd4f3qjb0/hHzG9MdoZn7KjlveQMWjNP4XomtxiSj/zsWqNYEFC9zJ2y6uMCPFgWpCJdbhUloeyUJhUINem7u7G1GhM9d3Txq2oPqzCRKiNv9rHytEYcHR3R4jXyfpSVs4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677486480476819.3345687138227; Mon, 27 Feb 2023 00:28:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW6K-0004sg-GR; Mon, 27 Feb 2023 00:31:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW5W-000341-4U for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:30:16 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW5U-0000Lq-7k for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:30:13 -0500 Received: by mail-pj1-x102b.google.com with SMTP id x34so4920869pjj.0 for ; Sun, 26 Feb 2023 21:30:10 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.30.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:30:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YHoTHrUgBZpaOPEfBJAi/HMPT06pVs2AARTKGv//H+s=; b=XE96EhJN+TaW6zfldy9kaaWagwgVOeCV+R0fCrCyVAa5mKlAS7ZXPHS8LadZFvkeOc OJVhlwBUtUO3L1Gq/bu/shyJT/o10aYGxr3CqgF2gQgA58PzqWjKBOOF1lmfd6nbmdwW KPJjrVn557j+Z/95YslK+uzaRIvtXVucDIKbx7SD/pyE+f3Fw9CqkKSs+hmWxna2+gb0 U1dR6ct2Y3kuuAb9THnZqswc+qEb+XDpXRXKB/6KnJsXwjlwrbafcMO8b8u88Ij2yPaW TsV5R5nInFMEezpTj0+s4ALPTpkPWXDmQZm8ZYrCPADVDFvbTGBqXkqk0hHTC7I+YRK+ Kpew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YHoTHrUgBZpaOPEfBJAi/HMPT06pVs2AARTKGv//H+s=; b=43w+LBAQWay6QrVXRv7l8vvM/LxEZ1nECUbGIW4Tx/H1Nk6h7zqR0Z+RFS9CBZATzj QCX1ujqB/i+PPVOhfcYg+WOHS6j5T86cxC5j52XSxiCUw5qnfwhJV/ybCHqPr5ckVxUm dc2Zc2Qu1nDzO7O5JFNX/mBaAPdvj96OmqWWlB6jHCBFnTmnDw24B6/gGPGGn/OCIVNv pNqc7/Rkz7AGT/CKrxmh5uMFQIdeMU3ecvGGgdqjIL73c8LxSI/Oaegb88hmEhw4Y/wx IapPu/7HqiagHAmdH2VqxIrlWTvfPqoCEW29A7A84MT1vEqsHnhKFm0AAgCaMDZSE3W9 /Cag== X-Gm-Message-State: AO0yUKVtiP7tYSuUAY7fnpNYhe3itwZNspASo+ba+OCg7IUQcbbYXrp0 r4TaVX+fQ9H6ymxv0LgGTjxX1Kgg8tSwPIMYEj4= X-Google-Smtp-Source: AK7set8Drj87yBFr3iVgLUt+IWpWUXGoQwrbFbIJ56AzWyNnZiiEnuQ7IsN1CgwCVaR4JJHWo3snEw== X-Received: by 2002:a17:90b:3802:b0:234:6c1a:8d9b with SMTP id mq2-20020a17090b380200b002346c1a8d9bmr24451990pjb.0.1677475809908; Sun, 26 Feb 2023 21:30:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 43/76] target/mips: Drop tcg_temp_free from translate_addr_const.c Date: Sun, 26 Feb 2023 19:24:32 -1000 Message-Id: <20230227052505.352889-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677486482130100005 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/mips/tcg/translate_addr_const.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/target/mips/tcg/translate_addr_const.c b/target/mips/tcg/trans= late_addr_const.c index 96f483418e..a510da406c 100644 --- a/target/mips/tcg/translate_addr_const.c +++ b/target/mips/tcg/translate_addr_const.c @@ -30,10 +30,6 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, = int sa) tcg_gen_shli_tl(t0, t0, sa + 1); tcg_gen_add_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - - tcg_temp_free(t1); - tcg_temp_free(t0); - return true; } =20 @@ -54,8 +50,5 @@ bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, = int sa) gen_load_gpr(t1, rt); tcg_gen_shli_tl(t0, t0, sa + 1); tcg_gen_add_tl(cpu_gpr[rd], t0, t1); - tcg_temp_free(t1); - tcg_temp_free(t0); - return true; } --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677476339; cv=none; d=zohomail.com; s=zohoarc; b=e8vBs7jzf+k9tbnT5YISA987rPr3XzVae6X3d6FcM5wMUTWvHiiSeAOtubD4O29/8z3f3kemsII6RcHRv68mNZpx7NVujNOulJX//v7jExAocXjuCsjMrjRf/4t+c1KViv/P5Bys0PcQSMGHAUpQ1tcht3FmnhRQWHvqxy5bl6A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677476339; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RUHY2yKH2nPTR6QE7c2gu4MGXp/9B0MeleLyAh2d26U=; b=IV6MX6WRQIS2OJfly4/+W6d6nTlA0WB7HwoG0k5Ti/NnfeaMa+l/imiJmnQhjSIWn0H3XxXj8QdGPNl4J/CUvYWjqv7Nhj3lbZ12nDH7cXbkOBDQ2eVwVFHCvJHVsmIZEryvmPBikPPsyMwfiIEkQv2tFXRo82KKD0TYZB4LcmE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677476339117304.593416523697; Sun, 26 Feb 2023 21:38:59 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW6F-0004Iw-FK; Mon, 27 Feb 2023 00:30:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW5X-00037A-Qq for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:30:17 -0500 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW5W-0000N0-4p for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:30:15 -0500 Received: by mail-pl1-x630.google.com with SMTP id i10so5518416plr.9 for ; Sun, 26 Feb 2023 21:30:13 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.30.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:30:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RUHY2yKH2nPTR6QE7c2gu4MGXp/9B0MeleLyAh2d26U=; b=oHVcueKiZMddjDB6fdk2r6swLMT9dSXuFthEBzBtUYbDqoqmBWeAAYmffyV0rENqhB C2vUtGHjR45c7rODKjVENrYWReQq3/MuOrxlE262a8md7FnG4Nzl8R+mEHl02AuJN85P y9wCj8/Th/4sE3GN7gjNaO6h3kubz0FVWzwHdjQhl8FfOvDVja0ZJge7v/1G5uRYEs63 dJa3eHesukTsBr3GtNcwMQv0UY/vQ+xr21byICAdhsjDTYZZbUlBIBzwMzeJceDoZG7y OxAEiJWTK2zkUMMYor/zstFBDFnT2/lKB6okteSOIthZzqBOyUYTwTC4cKzl+zf4IFuS zhwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RUHY2yKH2nPTR6QE7c2gu4MGXp/9B0MeleLyAh2d26U=; b=gQRRsVA9ZZo9402S+VMcOgtLbnDfh0EXbAznOIanmB9+BqbJejS8eE5IyW/ACE18fQ rSvS5DRoXqHXxs8UBrfHVuF+XCdapqQdeGJBazyUZ6MALa8sQLTX/zB77kVIFXlDh0gg LO8Lp8opMPkshKuGpsLZNkUacLQbEcLFCovTQYZHEWcT9zm5B6GT7T76n4ahEMoIW2kM s7A5qdyzgEW7Gqe/wvK/DCeEH4GsleEpJOeQgiOf5VSrhyOkJSyrfsM2pnbKciyrduzD IA9VsNIyW1lraBwpMFm3TsjujK1wjOrW8snaGKuiQO4vfjJfiZILHVIgNWvbmfUh9b+k 7DIA== X-Gm-Message-State: AO0yUKXWk50ay9ASsZwZWpnOglwGN6hyVqXoizX06K6qdXeLVxCuqJOw trEeP+unTOVshrLeE2BuZNMILZh6gIhghnuVPCA= X-Google-Smtp-Source: AK7set95dVZcASTB5ux/w+uI2tS77eQvhHenxle241fX6nDiXof1g8v2j+8KNp+mQNTlqB2bTAXr0w== X-Received: by 2002:a17:90b:390f:b0:231:24c1:8028 with SMTP id ob15-20020a17090b390f00b0023124c18028mr27646334pjb.29.1677475812671; Sun, 26 Feb 2023 21:30:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 44/76] target/mips: Drop tcg_temp_free from tx79_translate.c Date: Sun, 26 Feb 2023 19:24:33 -1000 Message-Id: <20230227052505.352889-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476339662100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/mips/tcg/tx79_translate.c | 41 -------------------------------- 1 file changed, 41 deletions(-) diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_transl= ate.c index 4e479c2d10..d46bc73972 100644 --- a/target/mips/tcg/tx79_translate.c +++ b/target/mips/tcg/tx79_translate.c @@ -138,10 +138,6 @@ static bool trans_parallel_arith(DisasContext *ctx, ar= g_r *a, gen_load_gpr_hi(ax, a->rs); gen_load_gpr_hi(bx, a->rt); gen_logic_i64(cpu_gpr_hi[a->rd], ax, bx); - - tcg_temp_free(bx); - tcg_temp_free(ax); - return true; } =20 @@ -273,15 +269,6 @@ static bool trans_parallel_compare(DisasContext *ctx, = arg_r *a, tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0); tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], t2, wlen= * i, wlen); } - - tcg_temp_free(t2); - tcg_temp_free(t1); - tcg_temp_free(t0); - tcg_temp_free(bx); - tcg_temp_free(ax); - tcg_temp_free(c1); - tcg_temp_free(c0); - return true; } =20 @@ -362,10 +349,6 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a) tcg_gen_addi_i64(addr, addr, 8); tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEUQ); gen_store_gpr_hi(t0, a->rt); - - tcg_temp_free(t0); - tcg_temp_free(addr); - return true; } =20 @@ -389,10 +372,6 @@ static bool trans_SQ(DisasContext *ctx, arg_i *a) tcg_gen_addi_i64(addr, addr, 8); gen_load_gpr_hi(t0, a->rt); tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEUQ); - - tcg_temp_free(addr); - tcg_temp_free(t0); - return true; } =20 @@ -458,11 +437,6 @@ static bool trans_PPACW(DisasContext *ctx, arg_r *a) =20 gen_load_gpr_hi(t0, a->rs); /* a1 */ tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], a0, t0, 32, 32); - - tcg_temp_free(t0); - tcg_temp_free(b0); - tcg_temp_free(a0); - return true; } =20 @@ -506,10 +480,6 @@ static bool trans_PEXTLx(DisasContext *ctx, arg_r *a, = unsigned wlen) tcg_gen_shri_i64(bx, bx, wlen); tcg_gen_shri_i64(ax, ax, wlen); } - - tcg_temp_free(bx); - tcg_temp_free(ax); - return true; } =20 @@ -541,10 +511,6 @@ static bool trans_PEXTLW(DisasContext *ctx, arg_r *a) gen_load_gpr(ax, a->rs); gen_load_gpr(bx, a->rt); gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx); - - tcg_temp_free(bx); - tcg_temp_free(ax); - return true; } =20 @@ -564,10 +530,6 @@ static bool trans_PEXTUW(DisasContext *ctx, arg_r *a) gen_load_gpr_hi(ax, a->rs); gen_load_gpr_hi(bx, a->rt); gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx); - - tcg_temp_free(bx); - tcg_temp_free(ax); - return true; } =20 @@ -678,8 +640,5 @@ static bool trans_PROT3W(DisasContext *ctx, arg_r *a) =20 tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], ax, 0, 32); tcg_gen_rotri_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], 32); - - tcg_temp_free(ax); - return true; } --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677477034; cv=none; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.30.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:30:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=niO44Co69efms0IVc6R/k9jlve0XAcHkzZjYqfu6blc=; b=sb+cdnbYsOXgn8MD7Pzyjou0dbcOJ6CQcx+rfjPxAQP/dUd5Mv5R+jTjMsYx2nee7t ruA8Ohas6ptT3YroJF0m97t5clvLSotWXkWElrGlMM8iQVfSdoEdp2U3+++1K0YYFBGP 0tkR6oAMS+KjaMuoyxRC18LNqfaZrNvs+oYOYiJyxqL6ZNo4brXKAnERH+MiMhypEEAi rDOS7P9PgVefPFAPPIBObDLZIU2hqziB53qQX8rNrBeIo89U2KFwewRssXL5fC1CXl2V BPwA4DVyRg0Zwti0K1Y7RN4vYuSzvJYzQg5zbS3ltY7f9JBQd7VnuL1ZFWwHHP/Edtxy R/VA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=niO44Co69efms0IVc6R/k9jlve0XAcHkzZjYqfu6blc=; b=1hIqXCBJMuGTczmadU/Uy3d32wPg+y2oZ4QadjAc3M4mTN8FY62Rmt9KRMUT/ueKi0 dDF5hE67VbrFWXDSvK4ozqpQfbtgdEieIhHYz9Y0k+dkFqC1XgN3c6vDpVL0Mv5ANQMg G75TLRb3/nqQfHF9q+LRt/LvYqnL+EYsqAN0oAix+4q0oR+7N5XE6B4B0z7Nv4WS+FEA jbfrc4JxP/Y/g+VGZDd2mbdB7e1fSGCEmmi2rmGp1k/FF3m5DDxhKivEbK8llzQrWd15 U/QNyNwoBk0hT1P37LRgWWKRgQi5S1UuXVfsEwyfbhMKeV4qG8O8lXXUntfFE58rGZcT k5wQ== X-Gm-Message-State: AO0yUKXKZmM5wOM5Kk8T1lxne1tjrYsAeR+VNt3gJ6LgfDj183V/iXt+ BoRvgUKrE9/YMNitFHMw33HhphTjDnLAXzw8KXM= X-Google-Smtp-Source: AK7set/Rdc5VZgmgmU9jB8t7rEYssvLCmI/KxHBaUxyOshBJl5njJaR6fUk0BgIigoi2zKcq8UPNBw== X-Received: by 2002:a17:90a:e7cc:b0:230:86de:f390 with SMTP id kb12-20020a17090ae7cc00b0023086def390mr24155960pjb.42.1677475815415; Sun, 26 Feb 2023 21:30:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 45/76] target/mips: Fix trans_mult_acc return Date: Sun, 26 Feb 2023 19:24:34 -1000 Message-Id: <20230227052505.352889-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677477034739100005 Success from trans_* subroutines should be true. Fixes: 5fa38eedbd ("target/mips: Convert Vr54xx MACC* opcodes to decodetree= ") Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/mips/tcg/vr54xx_translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_tr= anslate.c index 3e2c98f2c6..a7d241e4e7 100644 --- a/target/mips/tcg/vr54xx_translate.c +++ b/target/mips/tcg/vr54xx_translate.c @@ -53,7 +53,7 @@ static bool trans_mult_acc(DisasContext *ctx, arg_r *a, tcg_temp_free(t0); tcg_temp_free(t1); =20 - return false; + return true; } =20 TRANS(MACC, trans_mult_acc, gen_helper_macc); --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677476890; cv=none; d=zohomail.com; s=zohoarc; b=c7UvHYivdaBQCViEP3Bzz+UVUGQNb375aOZNYUv0voifPy92fAFsSOYgToq2zeVTYmGzKV+2zIAKNMHGHz7OHcXJJMlGE3eJoh0KQaliQt6Iuz1S3hU76118haO8q1JMuvEKzgwGI6JgSXA/bozwOB+hjiLXFtp4R+g8KmmFDpI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677476890; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OamVkTHfnUQ17ezU+zmeUz0tz/Qpam4ZKwlKCcTeapQ=; b=RAWnZ+1Iz0XgPiqOFggBjIVQwlHCDXhH/895nlUXQeQDBg7cqoE0XHScBYA2IwwT1O+ZUqOQSlgtCDekLLA+/9DKW1Nt+KWKRYOZdaCTG7dDoEuI3sotmc8qcPxH4utS4I0dJladEDpqajuhqrX3+HqnNLa/Ec2jcFIxX2muAIc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677476890846340.95606882641357; Sun, 26 Feb 2023 21:48:10 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW6T-000653-Fi; Mon, 27 Feb 2023 00:31:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW5d-0003I6-Jp for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:30:23 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW5b-0000PJ-AZ for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:30:21 -0500 Received: by mail-pl1-x62d.google.com with SMTP id p20so4317572plw.13 for ; Sun, 26 Feb 2023 21:30:18 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.30.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:30:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OamVkTHfnUQ17ezU+zmeUz0tz/Qpam4ZKwlKCcTeapQ=; b=SWlI378sWwI/K1RgeozMlwyvCYHMg6xJrUh53vXgBqgN1fvT+a6cNl0coTpmhFFjAY sYeoqh9thGGdU7ofM0GSYxSMuT+3zGuvEM5tN0c9B5c1sx1fsxf3paXzzOM8Z/2DAJBi HSbL2BbZmsyjAkMUvhXwC+2WOm7h8lI/59LnEkmGNhP+fulK+2C82mLRy2Uxy9492+f9 Hgu9z3VZDjlCLpK79qliJpRtt6/tbf6UedKZPu8YclDot8fn84zkq+R1IWIAtMScwlxN ifPLzQ7AZeot3MM9rstQkCIWr8WlQr/dgC4uP7K49acpYSOtsw94pMfPrc226IF1DnIz tNow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OamVkTHfnUQ17ezU+zmeUz0tz/Qpam4ZKwlKCcTeapQ=; b=qxlr7UgRZjtNCAhpiQiEzxRKNtghCnGd/hStPI9KwL+Rpg5pM9oUYChrx4xyrKgG5I Q+6wV35S8CUv65dJR+FAP6xFmII6ozs7mHqfyzB5c3TDDVforW+RL7NqP7yM8Menws/r KjiwH377rRN+sazMY6AVZYyuMjgqE1y2L86vA1gwhwZkZ+1U/VvxiBEdAWAgdknjchDl VAaz3Hqcs2C7tudkseF7sa2rzBC5oETHgEQaho6lzfiCT79CUmm4sFggcm3YJqtX3zwd zkU8h6PZbYJfXl9+TAmrgeugv1dRYPjVVCdzPNZJOaxACSk7+BH4KAMdxpVWvfJNksHF P9dA== X-Gm-Message-State: AO0yUKUQqo1bvbUyRMPuNpZZzQPbCHOu1vlHJ+/CWRQmYvL1/Tp5rSeb P0o1i2e5N5ZKrnKP8ELlm0ckDbmiMoKuTX5/Aek= X-Google-Smtp-Source: AK7set8oGElELa57SFMOVPHsjEarbsqRKrfiApe19dFZmlguEIBKHSV7GDl/DhRi35zUM2j6Fcy9tw== X-Received: by 2002:a17:90a:7a8f:b0:237:c7ed:8f4d with SMTP id q15-20020a17090a7a8f00b00237c7ed8f4dmr6495971pjf.15.1677475818072; Sun, 26 Feb 2023 21:30:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 46/76] target/mips: Drop tcg_temp_free from vr54xx_translate.c Date: Sun, 26 Feb 2023 19:24:35 -1000 Message-Id: <20230227052505.352889-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476891969100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/mips/tcg/vr54xx_translate.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_tr= anslate.c index a7d241e4e7..804672f84c 100644 --- a/target/mips/tcg/vr54xx_translate.c +++ b/target/mips/tcg/vr54xx_translate.c @@ -49,10 +49,6 @@ static bool trans_mult_acc(DisasContext *ctx, arg_r *a, gen_helper_mult_acc(t0, cpu_env, t0, t1); =20 gen_store_gpr(t0, a->rd); - - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; } =20 --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677475903; cv=none; d=zohomail.com; s=zohoarc; b=A6aj/hn0DsYzk+IXvk72pMM6AcFG6P5Ugs1eqHV4c6xIMBbNJaeHmtLj0yH6ZgXO82WYkEdV1xU1b1wajr0xAELxnhuzsqvSoXnIHHERjIl9XI3+Tp55lndLPWL0qLx5Cz1BIBQidVPWbmJYtX1tsYN+FjY4lEoYapk4PBCI9/E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677475903; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6fggkdWaXIry33qUz7sBhGNkv6UnQjXf9/nNJ0GPcic=; b=J7TgeQBVJ49xJroJVMA9BkEU887lWBJRqTSDc8xx6KvR1cJxeUi083d1TRUm/Y7Wnx5c/OO49T22EPw/zEeNvAnBDbnvGxkQbllEPrhROPqMJg17xXMCqoSX0SsRURX6KJZ5SKMewuj1P0SciB8EISo1AcGep7pgoTQd876cBV8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677475903915496.9862379081369; Sun, 26 Feb 2023 21:31:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW6a-0006wE-RT; Mon, 27 Feb 2023 00:31:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW5l-0003Ou-Kh for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:30:30 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW5f-0000R3-QI for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:30:28 -0500 Received: by mail-pj1-x1030.google.com with SMTP id oj5so896593pjb.5 for ; Sun, 26 Feb 2023 21:30:22 -0800 (PST) Received: from stoup.. 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Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/mips/tcg/translate.c | 537 +----------------------------------- 1 file changed, 14 insertions(+), 523 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 8cad3d15a0..0f27ca6149 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1274,11 +1274,8 @@ static inline void gen_load_srsgpr(int from, int to) tcg_gen_add_ptr(addr, cpu_env, addr); =20 tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from); - tcg_temp_free_ptr(addr); - tcg_temp_free_i32(t2); } gen_store_gpr(t0, to); - tcg_temp_free(t0); } =20 static inline void gen_store_srsgpr(int from, int to) @@ -1297,9 +1294,6 @@ static inline void gen_store_srsgpr(int from, int to) tcg_gen_add_ptr(addr, cpu_env, addr); =20 tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to); - tcg_temp_free_ptr(addr); - tcg_temp_free_i32(t2); - tcg_temp_free(t0); } } =20 @@ -1396,7 +1390,6 @@ void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, i= nt reg) t64 =3D tcg_temp_new_i64(); tcg_gen_extu_i32_i64(t64, t); tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 0, 32); - tcg_temp_free_i64(t64); } =20 static void gen_load_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg) @@ -1414,7 +1407,6 @@ static void gen_store_fpr32h(DisasContext *ctx, TCGv_= i32 t, int reg) TCGv_i64 t64 =3D tcg_temp_new_i64(); tcg_gen_extu_i32_i64(t64, t); tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 32, 32); - tcg_temp_free_i64(t64); } else { gen_store_fpr32(ctx, t, reg | 1); } @@ -1439,7 +1431,6 @@ void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, i= nt reg) t0 =3D tcg_temp_new_i64(); tcg_gen_shri_i64(t0, t, 32); tcg_gen_deposit_i64(fpu_f64[reg | 1], fpu_f64[reg | 1], t0, 0, 32); - tcg_temp_free_i64(t0); } } =20 @@ -1852,8 +1843,6 @@ static inline void gen_cmp ## type ## _ ## fmt(DisasC= ontext *ctx, int n, \ default: = \ abort(); = \ } = \ - tcg_temp_free_i##bits(fp0); = \ - tcg_temp_free_i##bits(fp1); = \ } =20 FOP_CONDS(, 0, d, FMT_D, 64) @@ -1946,8 +1935,6 @@ static inline void gen_r6_cmp_ ## fmt(DisasContext *c= tx, int n, \ abort(); \ } \ STORE; \ - tcg_temp_free_i ## bits(fp0); \ - tcg_temp_free_i ## bits(fp1); \ } =20 FOP_CONDNS(d, FMT_D, 64, gen_store_fpr64(ctx, fp0, fd)) @@ -1967,7 +1954,6 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, = int mem_idx, \ tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); = \ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); = \ tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); = \ - tcg_temp_free(t0); = \ } #else #define OP_LD_ATOMIC(insn, fname) = \ @@ -2065,9 +2051,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_gen_shl_tl(t2, t2, t1); gen_load_gpr(t1, rt); tcg_gen_andc_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); gen_store_gpr(t0, rt); break; case OPC_LDR: @@ -2090,15 +2074,12 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_gen_shl_tl(t2, t2, t1); gen_load_gpr(t1, rt); tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); gen_store_gpr(t0, rt); break; case OPC_LDPC: t1 =3D tcg_const_tl(pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); - tcg_temp_free(t1); tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ); gen_store_gpr(t0, rt); break; @@ -2106,7 +2087,6 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, case OPC_LWPC: t1 =3D tcg_const_tl(pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); - tcg_temp_free(t1); tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL); gen_store_gpr(t0, rt); break; @@ -2170,9 +2150,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_gen_shl_tl(t2, t2, t1); gen_load_gpr(t1, rt); tcg_gen_andc_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); tcg_gen_ext32s_tl(t0, t0); gen_store_gpr(t0, rt); break; @@ -2199,9 +2177,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_gen_shl_tl(t2, t2, t1); gen_load_gpr(t1, rt); tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); tcg_gen_ext32s_tl(t0, t0); gen_store_gpr(t0, rt); break; @@ -2214,7 +2190,6 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, gen_store_gpr(t0, rt); break; } - tcg_temp_free(t0); } =20 /* Store */ @@ -2273,8 +2248,6 @@ static void gen_st(DisasContext *ctx, uint32_t opc, i= nt rt, gen_helper_0e2i(swr, t1, t0, mem_idx); break; } - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 =20 @@ -2291,7 +2264,6 @@ static void gen_st_cond(DisasContext *ctx, int rt, in= t base, int offset, /* compare the address against that of the preceding LL */ gen_base_offset_addr(ctx, addr, base, offset); tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1); - tcg_temp_free(addr); tcg_gen_movi_tl(t0, 0); gen_store_gpr(t0, rt); tcg_gen_br(done); @@ -2304,10 +2276,8 @@ static void gen_st_cond(DisasContext *ctx, int rt, i= nt base, int offset, eva ? MIPS_HFLAG_UM : ctx->mem_idx, tcg_mo); tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_llval); gen_store_gpr(t0, rt); - tcg_temp_free(val); =20 gen_set_label(done); - tcg_temp_free(t0); } =20 /* Load and store */ @@ -2325,7 +2295,6 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t = opc, int ft, tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL | ctx->default_tcg_memop_mask); gen_store_fpr32(ctx, fp0, ft); - tcg_temp_free_i32(fp0); } break; case OPC_SWC1: @@ -2334,7 +2303,6 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t = opc, int ft, gen_load_fpr32(ctx, fp0, ft); tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL | ctx->default_tcg_memop_mask); - tcg_temp_free_i32(fp0); } break; case OPC_LDC1: @@ -2343,7 +2311,6 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t = opc, int ft, tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ | ctx->default_tcg_memop_mask); gen_store_fpr64(ctx, fp0, ft); - tcg_temp_free_i64(fp0); } break; case OPC_SDC1: @@ -2352,7 +2319,6 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t = opc, int ft, gen_load_fpr64(ctx, fp0, ft); tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ | ctx->default_tcg_memop_mask); - tcg_temp_free_i64(fp0); } break; default: @@ -2381,7 +2347,6 @@ static void gen_cop1_ldst(DisasContext *ctx, uint32_t= op, int rt, } else { generate_exception_err(ctx, EXCP_CpU, 1); } - tcg_temp_free(t0); } =20 /* Arithmetic with immediate operand */ @@ -2412,15 +2377,12 @@ static void gen_arith_imm(DisasContext *ctx, uint32= _t opc, tcg_gen_xori_tl(t1, t1, ~uimm); tcg_gen_xori_tl(t2, t0, uimm); tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); - tcg_temp_free(t1); /* operands of same sign, result different sign */ generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(l1); tcg_gen_ext32s_tl(t0, t0); gen_store_gpr(t0, rt); - tcg_temp_free(t0); } break; case OPC_ADDIU: @@ -2445,14 +2407,11 @@ static void gen_arith_imm(DisasContext *ctx, uint32= _t opc, tcg_gen_xori_tl(t1, t1, ~uimm); tcg_gen_xori_tl(t2, t0, uimm); tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); - tcg_temp_free(t1); /* operands of same sign, result different sign */ generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(l1); gen_store_gpr(t0, rt); - tcg_temp_free(t0); } break; case OPC_DADDIU: @@ -2535,7 +2494,6 @@ static void gen_slt_imm(DisasContext *ctx, uint32_t o= pc, tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rt], t0, uimm); break; } - tcg_temp_free(t0); } =20 /* Shifts with immediate operand */ @@ -2575,7 +2533,6 @@ static void gen_shift_imm(DisasContext *ctx, uint32_t= opc, tcg_gen_trunc_tl_i32(t1, t0); tcg_gen_rotri_i32(t1, t1, uimm); tcg_gen_ext_i32_tl(cpu_gpr[rt], t1); - tcg_temp_free_i32(t1); } else { tcg_gen_ext32s_tl(cpu_gpr[rt], t0); } @@ -2611,7 +2568,6 @@ static void gen_shift_imm(DisasContext *ctx, uint32_t= opc, break; #endif } - tcg_temp_free(t0); } =20 /* Arithmetic */ @@ -2642,14 +2598,11 @@ static void gen_arith(DisasContext *ctx, uint32_t o= pc, tcg_gen_xor_tl(t1, t1, t2); tcg_gen_xor_tl(t2, t0, t2); tcg_gen_andc_tl(t1, t2, t1); - tcg_temp_free(t2); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); - tcg_temp_free(t1); /* operands of same sign, result different sign */ generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(l1); gen_store_gpr(t0, rd); - tcg_temp_free(t0); } break; case OPC_ADDU: @@ -2678,9 +2631,7 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, tcg_gen_xor_tl(t2, t1, t2); tcg_gen_xor_tl(t1, t0, t1); tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); - tcg_temp_free(t1); /* * operands of different sign, first operand and the result * of different sign @@ -2688,7 +2639,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(l1); gen_store_gpr(t0, rd); - tcg_temp_free(t0); } break; case OPC_SUBU: @@ -2718,14 +2668,11 @@ static void gen_arith(DisasContext *ctx, uint32_t o= pc, tcg_gen_xor_tl(t1, t1, t2); tcg_gen_xor_tl(t2, t0, t2); tcg_gen_andc_tl(t1, t2, t1); - tcg_temp_free(t2); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); - tcg_temp_free(t1); /* operands of same sign, result different sign */ generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(l1); gen_store_gpr(t0, rd); - tcg_temp_free(t0); } break; case OPC_DADDU: @@ -2752,9 +2699,7 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, tcg_gen_xor_tl(t2, t1, t2); tcg_gen_xor_tl(t1, t0, t1); tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); - tcg_temp_free(t1); /* * Operands of different sign, first operand and result differ= ent * sign. @@ -2762,7 +2707,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(l1); gen_store_gpr(t0, rd); - tcg_temp_free(t0); } break; case OPC_DSUBU: @@ -2818,9 +2762,6 @@ static void gen_cond_move(DisasContext *ctx, uint32_t= opc, tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, t1); break; } - tcg_temp_free(t2); - tcg_temp_free(t1); - tcg_temp_free(t0); } =20 /* Logic */ @@ -2899,8 +2840,6 @@ static void gen_slt(DisasContext *ctx, uint32_t opc, tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr[rd], t0, t1); break; } - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 /* Shifts */ @@ -2947,8 +2886,6 @@ static void gen_shift(DisasContext *ctx, uint32_t opc, tcg_gen_andi_i32(t2, t2, 0x1f); tcg_gen_rotr_i32(t2, t3, t2); tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; #if defined(TARGET_MIPS64) @@ -2970,8 +2907,6 @@ static void gen_shift(DisasContext *ctx, uint32_t opc, break; #endif } - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 /* Arithmetic on HI/LO registers */ @@ -3044,7 +2979,6 @@ static inline void gen_r6_ld(target_long addr, int re= g, int memidx, TCGv t0 =3D tcg_const_tl(addr); tcg_gen_qemu_ld_tl(t0, t0, memidx, memop); gen_store_gpr(t0, reg); - tcg_temp_free(t0); } =20 static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc, @@ -3141,8 +3075,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); tcg_gen_div_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_MOD: @@ -3160,8 +3092,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_DIVU: @@ -3173,8 +3103,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_MODU: @@ -3186,8 +3114,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_MUL: @@ -3198,8 +3124,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_gen_trunc_tl_i32(t3, t1); tcg_gen_mul_i32(t2, t2, t3); tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case R6_OPC_MUH: @@ -3210,8 +3134,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_gen_trunc_tl_i32(t3, t1); tcg_gen_muls2_i32(t2, t3, t2, t3); tcg_gen_ext_i32_tl(cpu_gpr[rd], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case R6_OPC_MULU: @@ -3222,8 +3144,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_gen_trunc_tl_i32(t3, t1); tcg_gen_mul_i32(t2, t2, t3); tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case R6_OPC_MUHU: @@ -3234,8 +3154,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_gen_trunc_tl_i32(t3, t1); tcg_gen_mulu2_i32(t2, t3, t2, t3); tcg_gen_ext_i32_tl(cpu_gpr[rd], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; #if defined(TARGET_MIPS64) @@ -3251,8 +3169,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_gen_movi_tl(t3, 0); tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); tcg_gen_div_tl(cpu_gpr[rd], t0, t1); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_DMOD: @@ -3267,8 +3183,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_gen_movi_tl(t3, 0); tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_DDIVU: @@ -3277,8 +3191,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) TCGv t3 =3D tcg_const_tl(1); tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); tcg_gen_divu_i64(cpu_gpr[rd], t0, t1); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_DMODU: @@ -3287,8 +3199,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) TCGv t3 =3D tcg_const_tl(1); tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); tcg_gen_remu_i64(cpu_gpr[rd], t0, t1); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_DMUL: @@ -3298,7 +3208,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) { TCGv t2 =3D tcg_temp_new(); tcg_gen_muls2_i64(t2, cpu_gpr[rd], t0, t1); - tcg_temp_free(t2); } break; case R6_OPC_DMULU: @@ -3308,18 +3217,14 @@ static void gen_r6_muldiv(DisasContext *ctx, int op= c, int rd, int rs, int rt) { TCGv t2 =3D tcg_temp_new(); tcg_gen_mulu2_i64(t2, cpu_gpr[rd], t0, t1); - tcg_temp_free(t2); } break; #endif default: MIPS_INVAL("r6 mul/div"); gen_reserved_instruction(ctx); - goto out; + break; } - out: - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 #if defined(TARGET_MIPS64) @@ -3351,8 +3256,6 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t= opc, int rs, int rt) tcg_gen_rem_tl(cpu_HI[1], t0, t1); tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]); tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case MMI_OPC_DIVU1: @@ -3366,18 +3269,13 @@ static void gen_div1_tx79(DisasContext *ctx, uint32= _t opc, int rs, int rt) tcg_gen_remu_tl(cpu_HI[1], t0, t1); tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]); tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; default: MIPS_INVAL("div1 TX79"); gen_reserved_instruction(ctx); - goto out; + break; } - out: - tcg_temp_free(t0); - tcg_temp_free(t1); } #endif =20 @@ -3414,8 +3312,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t op= c, tcg_gen_rem_tl(cpu_HI[acc], t0, t1); tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]); tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case OPC_DIVU: @@ -3429,8 +3325,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t op= c, tcg_gen_remu_tl(cpu_HI[acc], t0, t1); tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]); tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case OPC_MULT: @@ -3442,8 +3336,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t op= c, tcg_gen_muls2_i32(t2, t3, t2, t3); tcg_gen_ext_i32_tl(cpu_LO[acc], t2); tcg_gen_ext_i32_tl(cpu_HI[acc], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case OPC_MULTU: @@ -3455,8 +3347,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t op= c, tcg_gen_mulu2_i32(t2, t3, t2, t3); tcg_gen_ext_i32_tl(cpu_LO[acc], t2); tcg_gen_ext_i32_tl(cpu_HI[acc], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; #if defined(TARGET_MIPS64) @@ -3473,8 +3363,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t op= c, tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); tcg_gen_div_tl(cpu_LO[acc], t0, t1); tcg_gen_rem_tl(cpu_HI[acc], t0, t1); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case OPC_DDIVU: @@ -3484,8 +3372,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t op= c, tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); tcg_gen_divu_i64(cpu_LO[acc], t0, t1); tcg_gen_remu_i64(cpu_HI[acc], t0, t1); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case OPC_DMULT: @@ -3505,10 +3391,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t o= pc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case OPC_MADDU: @@ -3523,10 +3407,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t o= pc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case OPC_MSUB: @@ -3539,10 +3421,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t o= pc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case OPC_MSUBU: @@ -3557,20 +3437,15 @@ static void gen_muldiv(DisasContext *ctx, uint32_t = opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; default: MIPS_INVAL("mul/div"); gen_reserved_instruction(ctx); - goto out; + break; } - out: - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 /* @@ -3625,8 +3500,6 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t = opc, } tcg_gen_ext_i32_tl(cpu_LO[acc], t2); tcg_gen_ext_i32_tl(cpu_HI[acc], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case MMI_OPC_MULTU1: @@ -3644,8 +3517,6 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t = opc, } tcg_gen_ext_i32_tl(cpu_LO[acc], t2); tcg_gen_ext_i32_tl(cpu_HI[acc], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case MMI_OPC_MADD1: @@ -3661,13 +3532,11 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_= t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); if (rd) { gen_move_low32(cpu_gpr[rd], t2); } - tcg_temp_free_i64(t2); } break; case MMI_OPC_MADDU1: @@ -3685,24 +3554,18 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_= t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); if (rd) { gen_move_low32(cpu_gpr[rd], t2); } - tcg_temp_free_i64(t2); } break; default: MIPS_INVAL("mul/madd TXx9"); gen_reserved_instruction(ctx); - goto out; + break; } - - out: - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_cl(DisasContext *ctx, uint32_t opc, @@ -3924,9 +3787,6 @@ static void gen_loongson_integer(DisasContext *ctx, u= int32_t opc, break; #endif } - - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 /* Loongson multimedia instructions */ @@ -4221,7 +4081,6 @@ static void gen_loongson_multimedia(DisasContext *ctx= , int rd, int rs, int rt) tcg_gen_xor_i64(t1, t1, t2); tcg_gen_xor_i64(t2, t2, t0); tcg_gen_andc_i64(t1, t2, t1); - tcg_temp_free_i64(t2); tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab); generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(lab); @@ -4242,7 +4101,6 @@ static void gen_loongson_multimedia(DisasContext *ctx= , int rd, int rs, int rt) tcg_gen_xor_i64(t1, t1, t2); tcg_gen_xor_i64(t2, t2, t0); tcg_gen_and_i64(t1, t1, t2); - tcg_temp_free_i64(t2); tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab); generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(lab); @@ -4284,12 +4142,8 @@ static void gen_loongson_multimedia(DisasContext *ct= x, int rd, int rs, int rt) tcg_gen_extrl_i64_i32(t32, t64); tcg_gen_deposit_i32(fpu_fcr31, fpu_fcr31, t32, get_fp_bit(cc), 1); - - tcg_temp_free_i32(t32); - tcg_temp_free_i64(t64); } - goto no_rd; - break; + return; default: MIPS_INVAL("loongson_cp2"); gen_reserved_instruction(ctx); @@ -4297,10 +4151,6 @@ static void gen_loongson_multimedia(DisasContext *ct= x, int rd, int rs, int rt) } =20 gen_store_fpr64(ctx, t0, rd); - -no_rd: - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 static void gen_loongson_lswc2(DisasContext *ctx, int rt, @@ -4328,7 +4178,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, ctx->default_tcg_memop_mask); gen_store_gpr(t1, rt); gen_store_gpr(t0, lsq_rt1); - tcg_temp_free(t1); break; case OPC_GSLQC1: check_cp1_enabled(ctx); @@ -4341,7 +4190,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, ctx->default_tcg_memop_mask); gen_store_fpr64(ctx, t1, rt); gen_store_fpr64(ctx, t0, lsq_rt1); - tcg_temp_free(t1); break; case OPC_GSSQ: t1 =3D tcg_temp_new(); @@ -4353,7 +4201,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_load_gpr(t1, lsq_rt1); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | ctx->default_tcg_memop_mask); - tcg_temp_free(t1); break; case OPC_GSSQC1: check_cp1_enabled(ctx); @@ -4366,7 +4213,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_load_fpr64(ctx, t1, lsq_rt1); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | ctx->default_tcg_memop_mask); - tcg_temp_free(t1); break; #endif case OPC_GSSHFL: @@ -4390,16 +4236,13 @@ static void gen_loongson_lswc2(DisasContext *ctx, i= nt rt, gen_load_fpr32(ctx, fp0, rt); tcg_gen_ext_i32_tl(t1, fp0); tcg_gen_andc_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); #if defined(TARGET_MIPS64) tcg_gen_extrl_i64_i32(fp0, t0); #else tcg_gen_ext32s_tl(fp0, t0); #endif gen_store_fpr32(ctx, fp0, rt); - tcg_temp_free_i32(fp0); break; case OPC_GSLWRC1: check_cp1_enabled(ctx); @@ -4421,16 +4264,13 @@ static void gen_loongson_lswc2(DisasContext *ctx, i= nt rt, gen_load_fpr32(ctx, fp0, rt); tcg_gen_ext_i32_tl(t1, fp0); tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); #if defined(TARGET_MIPS64) tcg_gen_extrl_i64_i32(fp0, t0); #else tcg_gen_ext32s_tl(fp0, t0); #endif gen_store_fpr32(ctx, fp0, rt); - tcg_temp_free_i32(fp0); break; #if defined(TARGET_MIPS64) case OPC_GSLDLC1: @@ -4450,9 +4290,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, tcg_gen_shl_tl(t2, t2, t1); gen_load_fpr64(ctx, t1, rt); tcg_gen_andc_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); gen_store_fpr64(ctx, t0, rt); break; case OPC_GSLDRC1: @@ -4473,9 +4311,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, tcg_gen_shl_tl(t2, t2, t1); gen_load_fpr64(ctx, t1, rt); tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); gen_store_fpr64(ctx, t0, rt); break; #endif @@ -4495,8 +4331,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_load_fpr32(ctx, fp0, rt); tcg_gen_ext_i32_tl(t1, fp0); gen_helper_0e2i(swl, t1, t0, ctx->mem_idx); - tcg_temp_free_i32(fp0); - tcg_temp_free(t1); break; case OPC_GSSWRC1: check_cp1_enabled(ctx); @@ -4506,8 +4340,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_load_fpr32(ctx, fp0, rt); tcg_gen_ext_i32_tl(t1, fp0); gen_helper_0e2i(swr, t1, t0, ctx->mem_idx); - tcg_temp_free_i32(fp0); - tcg_temp_free(t1); break; #if defined(TARGET_MIPS64) case OPC_GSSDLC1: @@ -4516,7 +4348,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_base_offset_addr(ctx, t0, rs, shf_offset); gen_load_fpr64(ctx, t1, rt); gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx); - tcg_temp_free(t1); break; case OPC_GSSDRC1: check_cp1_enabled(ctx); @@ -4524,7 +4355,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_base_offset_addr(ctx, t0, rs, shf_offset); gen_load_fpr64(ctx, t1, rt); gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx); - tcg_temp_free(t1); break; #endif default: @@ -4538,7 +4368,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_reserved_instruction(ctx); break; } - tcg_temp_free(t0); } =20 /* Loongson EXT LDC2/SDC2 */ @@ -4633,7 +4462,6 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int= rt, tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL | ctx->default_tcg_memop_mask); gen_store_fpr32(ctx, fp0, rt); - tcg_temp_free_i32(fp0); break; #if defined(TARGET_MIPS64) case OPC_GSLDXC1: @@ -4650,21 +4478,18 @@ static void gen_loongson_lsdc2(DisasContext *ctx, i= nt rt, t1 =3D tcg_temp_new(); gen_load_gpr(t1, rt); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_SB); - tcg_temp_free(t1); break; case OPC_GSSHX: t1 =3D tcg_temp_new(); gen_load_gpr(t1, rt); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW | ctx->default_tcg_memop_mask); - tcg_temp_free(t1); break; case OPC_GSSWX: t1 =3D tcg_temp_new(); gen_load_gpr(t1, rt); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | ctx->default_tcg_memop_mask); - tcg_temp_free(t1); break; #if defined(TARGET_MIPS64) case OPC_GSSDX: @@ -4672,7 +4497,6 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int= rt, gen_load_gpr(t1, rt); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | ctx->default_tcg_memop_mask); - tcg_temp_free(t1); break; #endif case OPC_GSSWXC1: @@ -4680,7 +4504,6 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int= rt, gen_load_fpr32(ctx, fp0, rt); tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL | ctx->default_tcg_memop_mask); - tcg_temp_free_i32(fp0); break; #if defined(TARGET_MIPS64) case OPC_GSSDXC1: @@ -4688,14 +4511,11 @@ static void gen_loongson_lsdc2(DisasContext *ctx, i= nt rt, gen_load_fpr64(ctx, t1, rt); tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TEUQ | ctx->default_tcg_memop_mask); - tcg_temp_free(t1); break; #endif default: break; } - - tcg_temp_free(t0); } =20 /* Traps */ @@ -4805,8 +4625,6 @@ static void gen_trap(DisasContext *ctx, uint32_t opc, generate_exception(ctx, EXCP_TRAP); gen_set_label(l1); } - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) @@ -5072,8 +4890,6 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, if (insn_bytes =3D=3D 2) { ctx->hflags |=3D MIPS_HFLAG_B16; } - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 =20 @@ -5142,13 +4958,9 @@ static void gen_bitops(DisasContext *ctx, uint32_t o= pc, int rt, fail: MIPS_INVAL("bitops"); gen_reserved_instruction(ctx); - tcg_temp_free(t0); - tcg_temp_free(t1); return; } gen_store_gpr(t0, rt); - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd) @@ -5173,8 +4985,6 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2= , int rt, int rd) tcg_gen_and_tl(t0, t0, t2); tcg_gen_shli_tl(t0, t0, 8); tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t2); - tcg_temp_free(t1); tcg_gen_ext32s_tl(cpu_gpr[rd], t0); } break; @@ -5195,8 +5005,6 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2= , int rt, int rd) tcg_gen_and_tl(t0, t0, t2); tcg_gen_shli_tl(t0, t0, 8); tcg_gen_or_tl(cpu_gpr[rd], t0, t1); - tcg_temp_free(t2); - tcg_temp_free(t1); } break; case OPC_DSHD: @@ -5212,18 +5020,14 @@ static void gen_bshfl(DisasContext *ctx, uint32_t o= p2, int rt, int rd) tcg_gen_shri_tl(t1, t0, 32); tcg_gen_shli_tl(t0, t0, 32); tcg_gen_or_tl(cpu_gpr[rd], t0, t1); - tcg_temp_free(t2); - tcg_temp_free(t1); } break; #endif default: MIPS_INVAL("bsfhl"); gen_reserved_instruction(ctx); - tcg_temp_free(t0); return; } - tcg_temp_free(t0); } =20 static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs, @@ -5262,7 +5066,6 @@ static void gen_align_bits(DisasContext *ctx, int wor= dsz, int rd, int rs, tcg_gen_concat_tl_i64(t2, t1, t0); tcg_gen_shri_i64(t2, t2, 32 - bits); gen_move_low32(cpu_gpr[rd], t2); - tcg_temp_free_i64(t2); } break; #if defined(TARGET_MIPS64) @@ -5273,10 +5076,7 @@ static void gen_align_bits(DisasContext *ctx, int wo= rdsz, int rd, int rs, break; #endif } - tcg_temp_free(t1); } - - tcg_temp_free(t0); } =20 void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int = bp) @@ -5303,7 +5103,6 @@ static void gen_bitswap(DisasContext *ctx, int opc, i= nt rd, int rt) break; #endif } - tcg_temp_free(t0); } =20 #ifndef CONFIG_USER_ONLY @@ -5321,8 +5120,6 @@ static inline void gen_mthc0_entrylo(TCGv arg, target= _ulong off) tcg_gen_concat32_i64(t1, t1, t0); #endif tcg_gen_st_i64(t1, cpu_env, off); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t0); } =20 static inline void gen_mthc0_store64(TCGv arg, target_ulong off) @@ -5334,8 +5131,6 @@ static inline void gen_mthc0_store64(TCGv arg, target= _ulong off) tcg_gen_ld_i64(t1, cpu_env, off); tcg_gen_concat32_i64(t1, t1, t0); tcg_gen_st_i64(t1, cpu_env, off); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t0); } =20 static inline void gen_mfhc0_entrylo(TCGv arg, target_ulong off) @@ -5349,7 +5144,6 @@ static inline void gen_mfhc0_entrylo(TCGv arg, target= _ulong off) tcg_gen_shri_i64(t0, t0, 32); #endif gen_move_low32(arg, t0); - tcg_temp_free_i64(t0); } =20 static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift) @@ -5359,7 +5153,6 @@ static inline void gen_mfhc0_load64(TCGv arg, target_= ulong off, int shift) tcg_gen_ld_i64(t0, cpu_env, off); tcg_gen_shri_i64(t0, t0, 32 + shift); gen_move_low32(arg, t0); - tcg_temp_free_i64(t0); } =20 static inline void gen_mfc0_load32(TCGv arg, target_ulong off) @@ -5368,7 +5161,6 @@ static inline void gen_mfc0_load32(TCGv arg, target_u= long off) =20 tcg_gen_ld_i32(t0, cpu_env, off); tcg_gen_ext_i32_tl(arg, t0); - tcg_temp_free_i32(t0); } =20 static inline void gen_mfc0_load64(TCGv arg, target_ulong off) @@ -5383,7 +5175,6 @@ static inline void gen_mtc0_store32(TCGv arg, target_= ulong off) =20 tcg_gen_trunc_tl_i32(t0, arg); tcg_gen_st_i32(t0, cpu_env, off); - tcg_temp_free_i32(t0); } =20 #define CP0_CHECK(c) \ @@ -5705,7 +5496,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) } #endif gen_move_low32(arg, tmp); - tcg_temp_free_i64(tmp); } register_name =3D "EntryLo0"; break; @@ -5763,7 +5553,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) } #endif gen_move_low32(arg, tmp); - tcg_temp_free_i64(tmp); } register_name =3D "EntryLo1"; break; @@ -6292,7 +6081,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) TCGv_i64 tmp =3D tcg_temp_new_i64(); tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState, CP0_Ta= gLo)); gen_move_low32(arg, tmp); - tcg_temp_free_i64(tmp); } register_name =3D "TagLo"; break; @@ -8813,13 +8601,11 @@ static void gen_mftr(CPUMIPSState *env, DisasContex= t *ctx, int rt, int rd, =20 gen_load_fpr32(ctx, fp0, rt); tcg_gen_ext_i32_tl(t0, fp0); - tcg_temp_free_i32(fp0); } else { TCGv_i32 fp0 =3D tcg_temp_new_i32(); =20 gen_load_fpr32h(ctx, fp0, rt); tcg_gen_ext_i32_tl(t0, fp0); - tcg_temp_free_i32(fp0); } break; case 3: @@ -8836,11 +8622,9 @@ static void gen_mftr(CPUMIPSState *env, DisasContext= *ctx, int rt, int rd, } trace_mips_translate_tr("mftr", rt, u, sel, h); gen_store_gpr(t0, rd); - tcg_temp_free(t0); return; =20 die: - tcg_temp_free(t0); LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h); gen_reserved_instruction(ctx); } @@ -9017,13 +8801,11 @@ static void gen_mttr(CPUMIPSState *env, DisasContex= t *ctx, int rd, int rt, =20 tcg_gen_trunc_tl_i32(fp0, t0); gen_store_fpr32(ctx, fp0, rd); - tcg_temp_free_i32(fp0); } else { TCGv_i32 fp0 =3D tcg_temp_new_i32(); =20 tcg_gen_trunc_tl_i32(fp0, t0); gen_store_fpr32h(ctx, fp0, rd); - tcg_temp_free_i32(fp0); } break; case 3: @@ -9041,11 +8823,9 @@ static void gen_mttr(CPUMIPSState *env, DisasContext= *ctx, int rd, int rt, } } trace_mips_translate_tr("mttr", rd, u, sel, h); - tcg_temp_free(t0); return; =20 die: - tcg_temp_free(t0); LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h); gen_reserved_instruction(ctx); } @@ -9071,7 +8851,6 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *= ctx, uint32_t opc, =20 gen_load_gpr(t0, rt); gen_mtc0(ctx, t0, rd, ctx->opcode & 0x7); - tcg_temp_free(t0); } opn =3D "mtc0"; break; @@ -9092,7 +8871,6 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *= ctx, uint32_t opc, =20 gen_load_gpr(t0, rt); gen_dmtc0(ctx, t0, rd, ctx->opcode & 0x7); - tcg_temp_free(t0); } opn =3D "dmtc0"; break; @@ -9112,7 +8890,6 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *= ctx, uint32_t opc, TCGv t0 =3D tcg_temp_new(); gen_load_gpr(t0, rt); gen_mthc0(ctx, t0, rd, ctx->opcode & 0x7); - tcg_temp_free(t0); } opn =3D "mthc0"; break; @@ -9246,7 +9023,7 @@ static void gen_compute_branch1(DisasContext *ctx, ui= nt32_t op, =20 if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK= )) { gen_reserved_instruction(ctx); - goto out; + return; } =20 if (cc !=3D 0) { @@ -9286,7 +9063,6 @@ static void gen_compute_branch1(DisasContext *ctx, ui= nt32_t op, tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); tcg_gen_nand_i32(t0, t0, t1); - tcg_temp_free_i32(t1); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); } @@ -9297,7 +9073,6 @@ static void gen_compute_branch1(DisasContext *ctx, ui= nt32_t op, tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); tcg_gen_or_i32(t0, t0, t1); - tcg_temp_free_i32(t1); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); } @@ -9312,7 +9087,6 @@ static void gen_compute_branch1(DisasContext *ctx, ui= nt32_t op, tcg_gen_and_i32(t0, t0, t1); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3)); tcg_gen_nand_i32(t0, t0, t1); - tcg_temp_free_i32(t1); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); } @@ -9327,7 +9101,6 @@ static void gen_compute_branch1(DisasContext *ctx, ui= nt32_t op, tcg_gen_or_i32(t0, t0, t1); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3)); tcg_gen_or_i32(t0, t0, t1); - tcg_temp_free_i32(t1); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); } @@ -9337,12 +9110,10 @@ static void gen_compute_branch1(DisasContext *ctx, = uint32_t op, default: MIPS_INVAL("cp1 cond branch"); gen_reserved_instruction(ctx); - goto out; + return; } ctx->btarget =3D btarget; ctx->hflags |=3D MIPS_HFLAG_BDS32; - out: - tcg_temp_free_i32(t0); } =20 /* R6 CP1 Branches */ @@ -9359,7 +9130,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx,= uint32_t op, "\n", ctx->base.pc_next); #endif gen_reserved_instruction(ctx); - goto out; + return; } =20 gen_load_fpr64(ctx, t0, ft); @@ -9379,7 +9150,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx,= uint32_t op, default: MIPS_INVAL("cp1 cond branch"); gen_reserved_instruction(ctx); - goto out; + return; } =20 tcg_gen_trunc_i64_tl(bcond, t0); @@ -9394,9 +9165,6 @@ static void gen_compute_branch1_r6(DisasContext *ctx,= uint32_t op, ctx->hflags |=3D MIPS_HFLAG_BDS32; break; } - -out: - tcg_temp_free_i64(t0); } =20 /* Coprocessor 1 (FPU) */ @@ -9624,7 +9392,6 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, = int rt, int fs) =20 gen_load_fpr32(ctx, fp0, fs); tcg_gen_ext_i32_tl(t0, fp0); - tcg_temp_free_i32(fp0); } gen_store_gpr(t0, rt); break; @@ -9635,7 +9402,6 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, = int rt, int fs) =20 tcg_gen_trunc_tl_i32(fp0, t0); gen_store_fpr32(ctx, fp0, fs); - tcg_temp_free_i32(fp0); } break; case OPC_CFC1: @@ -9665,7 +9431,6 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, = int rt, int fs) =20 gen_load_fpr32h(ctx, fp0, fs); tcg_gen_ext_i32_tl(t0, fp0); - tcg_temp_free_i32(fp0); } gen_store_gpr(t0, rt); break; @@ -9676,17 +9441,13 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc= , int rt, int fs) =20 tcg_gen_trunc_tl_i32(fp0, t0); gen_store_fpr32h(ctx, fp0, fs); - tcg_temp_free_i32(fp0); } break; default: MIPS_INVAL("cp1 move"); gen_reserved_instruction(ctx); - goto out; + return; } - - out: - tcg_temp_free(t0); } =20 static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf) @@ -9710,7 +9471,6 @@ static void gen_movci(DisasContext *ctx, int rd, int = rs, int cc, int tf) t0 =3D tcg_temp_new_i32(); tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); - tcg_temp_free_i32(t0); gen_load_gpr(cpu_gpr[rd], rs); gen_set_label(l1); } @@ -9733,7 +9493,6 @@ static inline void gen_movcf_s(DisasContext *ctx, int= fs, int fd, int cc, gen_load_fpr32(ctx, t0, fs); gen_store_fpr32(ctx, t0, fd); gen_set_label(l1); - tcg_temp_free_i32(t0); } =20 static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc, @@ -9752,11 +9511,9 @@ static inline void gen_movcf_d(DisasContext *ctx, in= t fs, int fd, int cc, =20 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); - tcg_temp_free_i32(t0); fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); gen_set_label(l1); } =20 @@ -9784,7 +9541,6 @@ static inline void gen_movcf_ps(DisasContext *ctx, in= t fs, int fd, tcg_gen_brcondi_i32(cond, t0, 0, l2); gen_load_fpr32h(ctx, t0, fs); gen_store_fpr32h(ctx, t0, fd); - tcg_temp_free_i32(t0); gen_set_label(l2); } =20 @@ -9819,10 +9575,6 @@ static void gen_sel_s(DisasContext *ctx, enum fopcod= e op1, int fd, int ft, } =20 gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp2); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(t1); } =20 static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft, @@ -9856,10 +9608,6 @@ static void gen_sel_d(DisasContext *ctx, enum fopcod= e op1, int fd, int ft, } =20 gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp2); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(t1); } =20 static void gen_farith(DisasContext *ctx, enum fopcode op1, @@ -9875,9 +9623,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_helper_float_add_s(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_SUB_S: @@ -9888,9 +9634,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_helper_float_sub_s(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_MUL_S: @@ -9901,9 +9645,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_helper_float_mul_s(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_DIV_S: @@ -9914,9 +9656,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_helper_float_div_s(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_SQRT_S: @@ -9926,7 +9666,6 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_sqrt_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_ABS_S: @@ -9940,7 +9679,6 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, gen_helper_float_abs_s(fp0, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_MOV_S: @@ -9949,7 +9687,6 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, =20 gen_load_fpr32(ctx, fp0, fs); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_NEG_S: @@ -9963,7 +9700,6 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, gen_helper_float_chs_s(fp0, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_ROUND_L_S: @@ -9978,9 +9714,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, } else { gen_helper_float_round_l_s(fp64, cpu_env, fp32); } - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_TRUNC_L_S: @@ -9995,9 +9729,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, } else { gen_helper_float_trunc_l_s(fp64, cpu_env, fp32); } - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_CEIL_L_S: @@ -10012,9 +9744,7 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, } else { gen_helper_float_ceil_l_s(fp64, cpu_env, fp32); } - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_FLOOR_L_S: @@ -10029,9 +9759,7 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, } else { gen_helper_float_floor_l_s(fp64, cpu_env, fp32); } - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_ROUND_W_S: @@ -10045,7 +9773,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_helper_float_round_w_s(fp0, cpu_env, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_TRUNC_W_S: @@ -10059,7 +9786,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_helper_float_trunc_w_s(fp0, cpu_env, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_CEIL_W_S: @@ -10073,7 +9799,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_helper_float_ceil_w_s(fp0, cpu_env, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_FLOOR_W_S: @@ -10087,7 +9812,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_helper_float_floor_w_s(fp0, cpu_env, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_SEL_S: @@ -10118,7 +9842,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, fp0 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); gen_set_label(l1); } break; @@ -10133,7 +9856,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, fp0 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); gen_set_label(l1); } } @@ -10145,7 +9867,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_recip_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_RSQRT_S: @@ -10155,7 +9876,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_rsqrt_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_MADDF_S: @@ -10169,9 +9889,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp2, fd); gen_helper_float_maddf_s(fp2, cpu_env, fp0, fp1, fp2); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); } break; case OPC_MSUBF_S: @@ -10185,9 +9902,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp2, fd); gen_helper_float_msubf_s(fp2, cpu_env, fp0, fp1, fp2); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); } break; case OPC_RINT_S: @@ -10197,7 +9911,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_rint_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_CLASS_S: @@ -10207,7 +9920,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_class_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_MIN_S: /* OPC_RECIP2_S */ @@ -10220,9 +9932,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp1, ft); gen_helper_float_min_s(fp2, cpu_env, fp0, fp1); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); } else { /* OPC_RECIP2_S */ check_cp1_64bitmode(ctx); @@ -10233,9 +9942,7 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_helper_float_recip2_s(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } } break; @@ -10249,9 +9956,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp1, ft); gen_helper_float_mina_s(fp2, cpu_env, fp0, fp1); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); } else { /* OPC_RECIP1_S */ check_cp1_64bitmode(ctx); @@ -10261,7 +9965,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_recip1_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } } break; @@ -10274,8 +9977,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp1, ft); gen_helper_float_max_s(fp1, cpu_env, fp0, fp1); gen_store_fpr32(ctx, fp1, fd); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); } else { /* OPC_RSQRT1_S */ check_cp1_64bitmode(ctx); @@ -10285,7 +9986,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_rsqrt1_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } } break; @@ -10298,8 +9998,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp1, ft); gen_helper_float_maxa_s(fp1, cpu_env, fp0, fp1); gen_store_fpr32(ctx, fp1, fd); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); } else { /* OPC_RSQRT2_S */ check_cp1_64bitmode(ctx); @@ -10310,9 +10008,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_helper_float_rsqrt2_s(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } } break; @@ -10324,9 +10020,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr32(ctx, fp32, fs); gen_helper_float_cvtd_s(fp64, cpu_env, fp32); - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_CVT_W_S: @@ -10340,7 +10034,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_helper_float_cvt_w_s(fp0, cpu_env, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_CVT_L_S: @@ -10355,9 +10048,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } else { gen_helper_float_cvt_l_s(fp64, cpu_env, fp32); } - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_CVT_PS_S: @@ -10370,10 +10061,7 @@ static void gen_farith(DisasContext *ctx, enum fop= code op1, gen_load_fpr32(ctx, fp32_0, fs); gen_load_fpr32(ctx, fp32_1, ft); tcg_gen_concat_i32_i64(fp64, fp32_1, fp32_0); - tcg_temp_free_i32(fp32_1); - tcg_temp_free_i32(fp32_0); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_CMP_F_S: @@ -10408,9 +10096,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_add_d(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_SUB_D: @@ -10422,9 +10108,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_sub_d(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MUL_D: @@ -10436,9 +10120,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_mul_d(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_DIV_D: @@ -10450,9 +10132,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_div_d(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_SQRT_D: @@ -10463,7 +10143,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_sqrt_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_ABS_D: @@ -10478,7 +10157,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_helper_float_abs_d(fp0, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MOV_D: @@ -10488,7 +10166,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_NEG_D: @@ -10503,7 +10180,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_helper_float_chs_d(fp0, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_ROUND_L_D: @@ -10518,7 +10194,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_helper_float_round_l_d(fp0, cpu_env, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_TRUNC_L_D: @@ -10533,7 +10208,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_helper_float_trunc_l_d(fp0, cpu_env, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_CEIL_L_D: @@ -10548,7 +10222,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_helper_float_ceil_l_d(fp0, cpu_env, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_FLOOR_L_D: @@ -10563,7 +10236,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_helper_float_floor_l_d(fp0, cpu_env, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_ROUND_W_D: @@ -10578,9 +10250,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } else { gen_helper_float_round_w_d(fp32, cpu_env, fp64); } - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_TRUNC_W_D: @@ -10595,9 +10265,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } else { gen_helper_float_trunc_w_d(fp32, cpu_env, fp64); } - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_CEIL_W_D: @@ -10612,9 +10280,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } else { gen_helper_float_ceil_w_d(fp32, cpu_env, fp64); } - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_FLOOR_W_D: @@ -10629,9 +10295,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } else { gen_helper_float_floor_w_d(fp32, cpu_env, fp64); } - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_SEL_D: @@ -10662,7 +10326,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); gen_set_label(l1); } break; @@ -10677,7 +10340,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); gen_set_label(l1); } } @@ -10690,7 +10352,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_recip_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_RSQRT_D: @@ -10701,7 +10362,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_rsqrt_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MADDF_D: @@ -10715,9 +10375,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp2, fd); gen_helper_float_maddf_d(fp2, cpu_env, fp0, fp1, fp2); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); } break; case OPC_MSUBF_D: @@ -10731,9 +10388,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp2, fd); gen_helper_float_msubf_d(fp2, cpu_env, fp0, fp1, fp2); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); } break; case OPC_RINT_D: @@ -10743,7 +10397,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_rint_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_CLASS_D: @@ -10753,7 +10406,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_class_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MIN_D: /* OPC_RECIP2_D */ @@ -10765,8 +10417,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp1, ft); gen_helper_float_min_d(fp1, cpu_env, fp0, fp1); gen_store_fpr64(ctx, fp1, fd); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); } else { /* OPC_RECIP2_D */ check_cp1_64bitmode(ctx); @@ -10777,9 +10427,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_recip2_d(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } } break; @@ -10792,8 +10440,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp1, ft); gen_helper_float_mina_d(fp1, cpu_env, fp0, fp1); gen_store_fpr64(ctx, fp1, fd); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); } else { /* OPC_RECIP1_D */ check_cp1_64bitmode(ctx); @@ -10803,7 +10449,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_recip1_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } } break; @@ -10816,8 +10461,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp1, ft); gen_helper_float_max_d(fp1, cpu_env, fp0, fp1); gen_store_fpr64(ctx, fp1, fd); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); } else { /* OPC_RSQRT1_D */ check_cp1_64bitmode(ctx); @@ -10827,7 +10470,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_rsqrt1_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } } break; @@ -10840,8 +10482,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp1, ft); gen_helper_float_maxa_d(fp1, cpu_env, fp0, fp1); gen_store_fpr64(ctx, fp1, fd); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); } else { /* OPC_RSQRT2_D */ check_cp1_64bitmode(ctx); @@ -10852,9 +10492,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_rsqrt2_d(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } } break; @@ -10889,9 +10527,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp64, fs); gen_helper_float_cvts_d(fp32, cpu_env, fp64); - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_CVT_W_D: @@ -10906,9 +10542,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } else { gen_helper_float_cvt_w_d(fp32, cpu_env, fp64); } - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_CVT_L_D: @@ -10923,7 +10557,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_helper_float_cvt_l_d(fp0, cpu_env, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_CVT_S_W: @@ -10933,7 +10566,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_cvts_w(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_CVT_D_W: @@ -10944,9 +10576,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr32(ctx, fp32, fs); gen_helper_float_cvtd_w(fp64, cpu_env, fp32); - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_CVT_S_L: @@ -10957,9 +10587,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp64, fs); gen_helper_float_cvts_l(fp32, cpu_env, fp64); - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_CVT_D_L: @@ -10970,7 +10598,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_cvtd_l(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_CVT_PS_PW: @@ -10981,7 +10608,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_cvtps_pw(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_ADD_PS: @@ -10993,9 +10619,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_add_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_SUB_PS: @@ -11007,9 +10631,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_sub_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MUL_PS: @@ -11021,9 +10643,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_mul_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_ABS_PS: @@ -11034,7 +10654,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_abs_ps(fp0, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MOV_PS: @@ -11044,7 +10663,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_NEG_PS: @@ -11055,7 +10673,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_chs_ps(fp0, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MOVCF_PS: @@ -11074,7 +10691,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); gen_set_label(l1); } break; @@ -11089,7 +10705,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); gen_set_label(l1); } } @@ -11103,9 +10718,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, ft); gen_load_fpr64(ctx, fp1, fs); gen_helper_float_addr_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MULR_PS: @@ -11117,9 +10730,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, ft); gen_load_fpr64(ctx, fp1, fs); gen_helper_float_mulr_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_RECIP2_PS: @@ -11131,9 +10742,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_recip2_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_RECIP1_PS: @@ -11144,7 +10753,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_recip1_ps(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_RSQRT1_PS: @@ -11155,7 +10763,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_rsqrt1_ps(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_RSQRT2_PS: @@ -11167,9 +10774,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_rsqrt2_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_CVT_S_PU: @@ -11180,7 +10785,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr32h(ctx, fp0, fs); gen_helper_float_cvts_pu(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_CVT_PW_PS: @@ -11191,7 +10795,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_cvtpw_ps(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_CVT_S_PL: @@ -11202,7 +10805,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_cvts_pl(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_PLL_PS: @@ -11215,8 +10817,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr32(ctx, fp1, ft); gen_store_fpr32h(ctx, fp0, fd); gen_store_fpr32(ctx, fp1, fd); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); } break; case OPC_PLU_PS: @@ -11229,8 +10829,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr32h(ctx, fp1, ft); gen_store_fpr32(ctx, fp1, fd); gen_store_fpr32h(ctx, fp0, fd); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); } break; case OPC_PUL_PS: @@ -11243,8 +10841,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr32(ctx, fp1, ft); gen_store_fpr32(ctx, fp1, fd); gen_store_fpr32h(ctx, fp0, fd); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); } break; case OPC_PUU_PS: @@ -11257,8 +10853,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr32h(ctx, fp1, ft); gen_store_fpr32(ctx, fp1, fd); gen_store_fpr32h(ctx, fp0, fd); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); } break; case OPC_CMP_F_PS: @@ -11316,7 +10910,6 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL); tcg_gen_trunc_tl_i32(fp0, t0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_LDXC1: @@ -11326,7 +10919,6 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, TCGv_i64 fp0 =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_LUXC1: @@ -11337,7 +10929,6 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, =20 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_SWXC1: @@ -11346,7 +10937,6 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, TCGv_i32 fp0 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL); - tcg_temp_free_i32(fp0); } break; case OPC_SDXC1: @@ -11356,7 +10946,6 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, TCGv_i64 fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); - tcg_temp_free_i64(fp0); } break; case OPC_SUXC1: @@ -11366,11 +10955,9 @@ static void gen_flt3_ldst(DisasContext *ctx, uint3= 2_t opc, TCGv_i64 fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); - tcg_temp_free_i64(fp0); } break; } - tcg_temp_free(t0); } =20 static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, @@ -11397,7 +10984,6 @@ static void gen_flt3_arith(DisasContext *ctx, uint3= 2_t opc, tcg_gen_br(l2); gen_set_label(l1); tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2); - tcg_temp_free(t0); if (cpu_is_bigendian(ctx)) { gen_load_fpr32(ctx, fp, fs); gen_load_fpr32h(ctx, fph, ft); @@ -11410,8 +10996,6 @@ static void gen_flt3_arith(DisasContext *ctx, uint3= 2_t opc, gen_store_fpr32h(ctx, fp, fd); } gen_set_label(l2); - tcg_temp_free_i32(fp); - tcg_temp_free_i32(fph); } break; case OPC_MADD_S: @@ -11425,10 +11009,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr32(ctx, fp1, ft); gen_load_fpr32(ctx, fp2, fr); gen_helper_float_madd_s(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); } break; case OPC_MADD_D: @@ -11443,10 +11024,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_madd_d(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_MADD_PS: @@ -11460,10 +11038,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_madd_ps(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_MSUB_S: @@ -11477,10 +11052,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr32(ctx, fp1, ft); gen_load_fpr32(ctx, fp2, fr); gen_helper_float_msub_s(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); } break; case OPC_MSUB_D: @@ -11495,10 +11067,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_msub_d(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_MSUB_PS: @@ -11512,10 +11081,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_msub_ps(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_NMADD_S: @@ -11529,10 +11095,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr32(ctx, fp1, ft); gen_load_fpr32(ctx, fp2, fr); gen_helper_float_nmadd_s(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); } break; case OPC_NMADD_D: @@ -11547,10 +11110,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_nmadd_d(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_NMADD_PS: @@ -11564,10 +11124,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_nmadd_ps(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_NMSUB_S: @@ -11581,10 +11138,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr32(ctx, fp1, ft); gen_load_fpr32(ctx, fp2, fr); gen_helper_float_nmsub_s(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); } break; case OPC_NMSUB_D: @@ -11599,10 +11153,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_nmsub_d(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_NMSUB_PS: @@ -11616,10 +11167,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_nmsub_ps(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; default: @@ -11708,7 +11256,6 @@ void gen_rdhwr(DisasContext *ctx, int rt, int rd, i= nt sel) gen_reserved_instruction(ctx); break; } - tcg_temp_free(t0); } =20 static inline void clear_branch_hflags(DisasContext *ctx) @@ -11767,11 +11314,9 @@ static void gen_branch(DisasContext *ctx, int insn= _bytes) =20 tcg_gen_andi_tl(t0, btarget, 0x1); tcg_gen_trunc_tl_i32(t1, t0); - tcg_temp_free(t0); tcg_gen_andi_i32(hflags, hflags, ~(uint32_t)MIPS_HFLAG_M16= ); tcg_gen_shli_i32(t1, t1, MIPS_HFLAG_M16_SHIFT); tcg_gen_or_i32(hflags, hflags, t1); - tcg_temp_free_i32(t1); =20 tcg_gen_andi_tl(cpu_PC, btarget, ~(target_ulong)0x1); } else { @@ -11801,7 +11346,7 @@ static void gen_compute_compact_branch(DisasContext= *ctx, uint32_t opc, "\n", ctx->base.pc_next); #endif gen_reserved_instruction(ctx); - goto out; + return; } =20 /* Load needed operands and calculate btarget */ @@ -11855,13 +11400,12 @@ static void gen_compute_compact_branch(DisasConte= xt *ctx, uint32_t opc, =20 gen_load_gpr(tbase, rt); gen_op_addr_add(ctx, btarget, tbase, toffset); - tcg_temp_free(tbase); } break; default: MIPS_INVAL("Compact branch/jump"); gen_reserved_instruction(ctx); - goto out; + return; } =20 if (bcond_compute =3D=3D 0) { @@ -11882,7 +11426,7 @@ static void gen_compute_compact_branch(DisasContext= *ctx, uint32_t opc, default: MIPS_INVAL("Compact branch/jump"); gen_reserved_instruction(ctx); - goto out; + return; } =20 /* Generating branch here as compact branches don't have delay slo= t */ @@ -11972,10 +11516,6 @@ static void gen_compute_compact_branch(DisasContex= t *ctx, uint32_t opc, /* OPC_BNVC */ tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t4, 0= , fs); } - tcg_temp_free(input_overflow); - tcg_temp_free(t4); - tcg_temp_free(t3); - tcg_temp_free(t2); } else if (rs < rt && rs =3D=3D 0) { /* OPC_BEQZALC, OPC_BNEZALC */ if (opc =3D=3D OPC_BEQZALC) { @@ -12005,7 +11545,7 @@ static void gen_compute_compact_branch(DisasContext= *ctx, uint32_t opc, default: MIPS_INVAL("Compact conditional branch/jump"); gen_reserved_instruction(ctx); - goto out; + return; } =20 /* Generating branch here as compact branches don't have delay slo= t */ @@ -12014,10 +11554,6 @@ static void gen_compute_compact_branch(DisasContex= t *ctx, uint32_t opc, =20 ctx->hflags |=3D MIPS_HFLAG_FBNSLOT; } - -out: - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 void gen_addiupc(DisasContext *ctx, int rx, int imm, @@ -12037,8 +11573,6 @@ void gen_addiupc(DisasContext *ctx, int rx, int imm, if (!is_64_bit) { tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]); } - - tcg_temp_free(t0); } =20 static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base, @@ -12048,8 +11582,6 @@ static void gen_cache_operation(DisasContext *ctx, = uint32_t op, int base, TCGv t1 =3D tcg_temp_new(); gen_base_offset_addr(ctx, t1, base, offset); gen_helper_cache(cpu_env, t1, t0); - tcg_temp_free(t1); - tcg_temp_free_i32(t0); } =20 static inline bool is_uhi(DisasContext *ctx, int sdbbp_code) @@ -12077,9 +11609,6 @@ void gen_ldxs(DisasContext *ctx, int base, int inde= x, int rd) =20 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); gen_store_gpr(t1, rd); - - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_sync(int stype) @@ -12183,7 +11712,6 @@ static void gen_mips_lx(DisasContext *ctx, uint32_t= opc, break; #endif } - tcg_temp_free(t0); } =20 static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op= 2, @@ -12397,7 +11925,6 @@ static void gen_mipsdsp_arith(DisasContext *ctx, ui= nt32_t op1, uint32_t op2, TCGv_i32 sa_t =3D tcg_const_i32(v2); gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t, v1_t, cpu_gpr[ret]); - tcg_temp_free_i32(sa_t); break; } case OPC_PRECR_SRA_R_PH_W: @@ -12406,7 +11933,6 @@ static void gen_mipsdsp_arith(DisasContext *ctx, ui= nt32_t op1, uint32_t op2, TCGv_i32 sa_t =3D tcg_const_i32(v2); gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t, v1_t, cpu_gpr[ret]); - tcg_temp_free_i32(sa_t); break; } case OPC_PRECRQ_PH_W: @@ -12595,7 +12121,6 @@ static void gen_mipsdsp_arith(DisasContext *ctx, ui= nt32_t op1, uint32_t op2, { TCGv_i32 ret_t =3D tcg_const_i32(ret); gen_helper_precr_sra_qh_pw(v2_t, v1_t, v2_t, ret_t); - tcg_temp_free_i32(ret_t); break; } case OPC_PRECR_SRA_R_QH_PW: @@ -12603,7 +12128,6 @@ static void gen_mipsdsp_arith(DisasContext *ctx, ui= nt32_t op1, uint32_t op2, { TCGv_i32 sa_v =3D tcg_const_i32(ret); gen_helper_precr_sra_r_qh_pw(v2_t, v1_t, v2_t, sa_v); - tcg_temp_free_i32(sa_v); break; } case OPC_PRECRQ_OB_QH: @@ -12630,9 +12154,6 @@ static void gen_mipsdsp_arith(DisasContext *ctx, ui= nt32_t op1, uint32_t op2, break; #endif } - - tcg_temp_free(v1_t); - tcg_temp_free(v2_t); } =20 static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc, @@ -12872,10 +12393,6 @@ static void gen_mipsdsp_shift(DisasContext *ctx, u= int32_t opc, break; #endif } - - tcg_temp_free(t0); - tcg_temp_free(v1_t); - tcg_temp_free(v2_t); } =20 static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t= op2, @@ -13182,10 +12699,6 @@ static void gen_mipsdsp_multiply(DisasContext *ctx= , uint32_t op1, uint32_t op2, break; #endif } - - tcg_temp_free_i32(t0); - tcg_temp_free(v1_t); - tcg_temp_free(v2_t); } =20 static void gen_mipsdsp_bitinsn(DisasContext *ctx, uint32_t op1, uint32_t = op2, @@ -13322,8 +12835,6 @@ static void gen_mipsdsp_bitinsn(DisasContext *ctx, = uint32_t op1, uint32_t op2, break; #endif } - tcg_temp_free(t0); - tcg_temp_free(val_t); } =20 static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx, @@ -13506,10 +13017,6 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext = *ctx, break; #endif } - - tcg_temp_free(t1); - tcg_temp_free(v1_t); - tcg_temp_free(v2_t); } =20 static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx, @@ -13597,7 +13104,6 @@ static void gen_mipsdsp_append(CPUMIPSState *env, D= isasContext *ctx, break; #endif } - tcg_temp_free(t0); } =20 static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t = op2, @@ -13814,10 +13320,6 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx,= uint32_t op1, uint32_t op2, break; #endif } - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(v1_t); } =20 /* End MIPSDSP functions. */ @@ -14668,9 +14170,6 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) gen_load_gpr(t1, rs); =20 gen_helper_insv(cpu_gpr[rt], cpu_env, t1, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); break; } default: /* Invalid */ @@ -14940,9 +14439,6 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) gen_load_gpr(t1, rs); =20 gen_helper_dinsv(cpu_gpr[rt], cpu_env, t1, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); break; } default: /* Invalid */ @@ -15169,8 +14665,6 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) gen_load_gpr(t0, rt); gen_load_gpr(t1, rs); gen_helper_fork(t0, t1); - tcg_temp_free(t0); - tcg_temp_free(t1); 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.30.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:30:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K1ileFl21ILOYbNN9ovAoll/bN96IaNdlVWGUtxEAQo=; b=IAQaN99+tYacpAyS3FYNrMOGwp1LvuIcKcnEdERuzDStzC51VA1NvJn/w+KK7ARSqR fxyn4tGvX4Ktdz8TU++w62gFPaCAW+CcZEv+8wPIQLJuuQIBsQ8sCS6wN0De4j7y/Jsx Dqtm0R4uK90EE2CpcC37FtBNMZToTEVfld/TU/cePEKNriCc7qCsUk/NMqCsfNe1zIKJ bjLfV6vEKiPy6Hd4YmYDcW9m9R7RYa9Rnyollyw4fCY1WjjvzHF2ZHAeNqt0EdvEiPQ+ GlcHoGmDHqL+qKRYkg/0Xqkz33Gc9e9hyckULqOVs7LHXdokihFpP97+vRxFukNsbxkp nWjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K1ileFl21ILOYbNN9ovAoll/bN96IaNdlVWGUtxEAQo=; b=5GYTGwJnMMYsKtJImq4nPDi7RRKyXVy1pt7oU7j+nH3zxBEZiKBZJP31Dhj5mfaNd9 cuKdUgAuV/CbWPmx+fv3ciz0NFfDtVzHsYnU02ZZRiUoyjqybYFpqjgIqI47fI+04kE8 g12yPczYX8kH9PUYwS9h/euuHUUlz86qXHjtnF69vcqDbg7sCY4O6bNWdlQMwCxKi7xO e0n/hbmjnmoympPyoYun2IQ6ykXP0S5sNvoFGgWRcC5fZF6Q4o2Mc9v570SaXd8ghDSP a+VH9A3uz0vLRnJROUTFAk9BVVnKsG3gDGQBkCdIY7vXNm+mMAxGKPCLdV8HR1Er2TmF K93A== X-Gm-Message-State: AO0yUKWY3Y6JGxQfgoEZdthklHGMLxgV1QYv1xsJrFpkmCsvWCIhBxB/ UvEDHnNkC/iGga8WPsIomZA9bI0BoDpk59TSsgeB3w== X-Google-Smtp-Source: AK7set+83fvTqdjAd4U6ztEA2Z36FPlG1ST3dO5Hyc/wlAkGnAHVsJO84Wum3ZlFb+N1Durru5cw+A== X-Received: by 2002:a17:90b:33c8:b0:237:aa9f:968c with SMTP id lk8-20020a17090b33c800b00237aa9f968cmr9357027pjb.34.1677475824069; Sun, 26 Feb 2023 21:30:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 48/76] target/nios2: Drop tcg_temp_free Date: Sun, 26 Feb 2023 19:24:37 -1000 Message-Id: <20230227052505.352889-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677477249974100003 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/nios2/translate.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 140bc31017..6610e22236 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -233,7 +233,6 @@ static void gen_jumpr(DisasContext *dc, int regno, bool= is_call) =20 tcg_gen_andi_tl(test, dest, 3); tcg_gen_brcondi_tl(TCG_COND_NE, test, 0, l); - tcg_temp_free(test); =20 tcg_gen_mov_tl(cpu_pc, dest); if (is_call) { @@ -300,7 +299,6 @@ static void gen_ldx(DisasContext *dc, uint32_t code, ui= nt32_t flags) =20 tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s); tcg_gen_qemu_ld_tl(data, addr, dc->mem_idx, flags); - tcg_temp_free(addr); } =20 /* Store instructions */ @@ -312,7 +310,6 @@ static void gen_stx(DisasContext *dc, uint32_t code, ui= nt32_t flags) TCGv addr =3D tcg_temp_new(); tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s); tcg_gen_qemu_st_tl(val, addr, dc->mem_idx, flags); - tcg_temp_free(addr); } =20 /* Branch instructions */ @@ -500,7 +497,6 @@ static void eret(DisasContext *dc, uint32_t code, uint3= 2_t flags) TCGv tmp =3D tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATU= S])); gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA)); - tcg_temp_free(tmp); } else { gen_helper_eret(cpu_env, load_gpr(dc, R_SSTATUS), load_gpr(dc, R_E= A)); } @@ -530,7 +526,6 @@ static void bret(DisasContext *dc, uint32_t code, uint3= 2_t flags) TCGv tmp =3D tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS])); gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_BA)); - tcg_temp_free(tmp); =20 dc->base.is_jmp =3D DISAS_NORETURN; #endif @@ -597,8 +592,6 @@ static void rdctl(DisasContext *dc, uint32_t code, uint= 32_t flags) tcg_gen_ld_tl(t1, cpu_env, offsetof(CPUNios2State, ctrl[CR_IPENDIN= G])); tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUNios2State, ctrl[CR_IENABLE= ])); tcg_gen_and_tl(dest, t1, t2); - tcg_temp_free(t1); - tcg_temp_free(t2); break; default: tcg_gen_ld_tl(dest, cpu_env, @@ -662,11 +655,9 @@ static void wrctl(DisasContext *dc, uint32_t code, uin= t32_t flags) tcg_gen_ld_tl(o, cpu_env, ofs); tcg_gen_andi_tl(o, o, ro); tcg_gen_or_tl(n, n, o); - tcg_temp_free(o); } =20 tcg_gen_st_tl(n, cpu_env, ofs); - tcg_temp_free(n); } break; } @@ -753,7 +744,6 @@ static void do_rr_mul_high(DisasContext *dc, uint32_t i= nsn, GenFn4 *fn) =20 fn(discard, dest_gpr(dc, instr.c), load_gpr(dc, instr.a), load_gpr(dc, instr.b)); - tcg_temp_free(discard); } =20 #define gen_rr_mul_high(fname, insn) = \ @@ -771,7 +761,6 @@ static void do_rr_shift(DisasContext *dc, uint32_t insn= , GenFn3 *fn) =20 tcg_gen_andi_tl(sh, load_gpr(dc, instr.b), 31); fn(dest_gpr(dc, instr.c), load_gpr(dc, instr.a), sh); - tcg_temp_free(sh); } =20 #define gen_rr_shift(fname, insn) = \ @@ -990,10 +979,6 @@ static void nios2_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) =20 instr =3D &i_type_instructions[op]; instr->handler(dc, code, instr->flags); - - if (dc->sink) { - tcg_temp_free(dc->sink); - } } =20 static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677485926; cv=none; d=zohomail.com; s=zohoarc; b=MO6kMz6KWdhBjcUN2o+4ggZX8kgg7xdJSGS7SHARSZ8UmuejeKNI/FdmjychTr0fWQmRydNBcoarAdee7K5OzFtV6SdRRstrw2YF80n/ZTlbh+yiY/Bb6Q0XZsWtsBRnjzvmkdzDV8rLbPPKfyYIEe+48dsgC98NpXqUYSxwmZw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677485926; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.30.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:30:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UK5XBu9I0qQAdw4Q425WvErokLkPdiRiycNWgpiEkiU=; b=WmAqjwD1PuKe2f7xS4exrvzgYW90qw8kJlV03HSq2I/gXWo5gbG9o6lgKitvbzrcKO MA8vJwv0GTWj47gGDNzSNwven5B9wteVhuBjLYT9AzF8/te25ocfksHYLB6nPSDN5NG1 DRO775S78W0KlEpGhLQEjFwH5J1QZHwIUsoih2vLkU6Wav/oB7QYjtTXWb2w4rP0yoiX o9cWnpMqi6w8fO38G13VZRuKP/FeRraaRZ8HGbX79ZyziFm5SLC0mw5VQ9ehfVwG5aLJ kDOSFC8b+Z5nI272TmfA3a1sqHTPy+TudbsZ63v47ASbtY+PRnofrVYgSel0wE9nafYf AkrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UK5XBu9I0qQAdw4Q425WvErokLkPdiRiycNWgpiEkiU=; b=M1MQ2kZ6Mk2zpV+RESLINLvMmFeOqPnnnXguGCUvOT83eE0K4RyWXgxLtaKaCKMXGZ maeeMNEPZdDkrGgcx2Xfs8vkdGL/uice16RzPOU8cvZNZpygtepq1NvUEq9J924Lyhxi EbX47PyE9XlRXOk9jftjUXibMTfiDuhFIqy+2Cgp4JD5V3Wci7EbN5JNzkgiGzyhvLCa 2fIZCDKuCVJlmYkAN8aYNMUV5j2cER7mj1Oajux3znaX7VGWxkLEh06F0uG36JylayZR aDqTQvBiiJNBmy4OFZzNWwZfm0VITy1xVNk/EtWaEpEfNXjPfFCkDRZiVbLolgHu4XO+ aKhQ== X-Gm-Message-State: AO0yUKX2I8OuzmbPJegnj682K2jzl2zcq1W87K/mRigNzSZn75kIMYTO vyy/siE6+nt+7tmgz1PuAHqM4tLO/z5zATnfexg= X-Google-Smtp-Source: AK7set/IrDK3p9XcSSOBcnGKeOqqXs3fAhcUlVKA3a5Z3jSDV56hr0eTdZLwxzKC9f/aJqNOMo0U4g== X-Received: by 2002:a17:90b:1b4e:b0:237:29b1:1893 with SMTP id nv14-20020a17090b1b4e00b0023729b11893mr21604139pjb.46.1677475826758; Sun, 26 Feb 2023 21:30:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 49/76] target/openrisc: Drop tcg_temp_free Date: Sun, 26 Feb 2023 19:24:38 -1000 Message-Id: <20230227052505.352889-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677485927032100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/openrisc/translate.c | 39 ------------------------------------- 1 file changed, 39 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index b8cd8e0964..76e53c78d4 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -206,10 +206,8 @@ static void gen_add(DisasContext *dc, TCGv dest, TCGv = srca, TCGv srcb) tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); tcg_gen_xor_tl(t0, res, srcb); tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); - tcg_temp_free(t0); =20 tcg_gen_mov_tl(dest, res); - tcg_temp_free(res); =20 gen_ove_cyov(dc); } @@ -224,10 +222,8 @@ static void gen_addc(DisasContext *dc, TCGv dest, TCGv= srca, TCGv srcb) tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); tcg_gen_xor_tl(t0, res, srcb); tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); - tcg_temp_free(t0); =20 tcg_gen_mov_tl(dest, res); - tcg_temp_free(res); =20 gen_ove_cyov(dc); } @@ -243,7 +239,6 @@ static void gen_sub(DisasContext *dc, TCGv dest, TCGv s= rca, TCGv srcb) tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_cy, srca, srcb); =20 tcg_gen_mov_tl(dest, res); - tcg_temp_free(res); =20 gen_ove_cyov(dc); } @@ -255,7 +250,6 @@ static void gen_mul(DisasContext *dc, TCGv dest, TCGv s= rca, TCGv srcb) tcg_gen_muls2_tl(dest, cpu_sr_ov, srca, srcb); tcg_gen_sari_tl(t0, dest, TARGET_LONG_BITS - 1); tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_ov, cpu_sr_ov, t0); - tcg_temp_free(t0); =20 tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); gen_ove_ov(dc); @@ -278,7 +272,6 @@ static void gen_div(DisasContext *dc, TCGv dest, TCGv s= rca, TCGv srcb) Supress the host-side exception by dividing by 1. */ tcg_gen_or_tl(t0, srcb, cpu_sr_ov); tcg_gen_div_tl(dest, srca, t0); - tcg_temp_free(t0); =20 tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); gen_ove_ov(dc); @@ -293,7 +286,6 @@ static void gen_divu(DisasContext *dc, TCGv dest, TCGv = srca, TCGv srcb) Supress the host-side exception by dividing by 1. */ tcg_gen_or_tl(t0, srcb, cpu_sr_cy); tcg_gen_divu_tl(dest, srca, t0); - tcg_temp_free(t0); =20 gen_ove_cy(dc); } @@ -314,14 +306,11 @@ static void gen_muld(DisasContext *dc, TCGv srca, TCG= v srcb) tcg_gen_muls2_i64(cpu_mac, high, t1, t2); tcg_gen_sari_i64(t1, cpu_mac, 63); tcg_gen_setcond_i64(TCG_COND_NE, t1, t1, high); - tcg_temp_free_i64(high); tcg_gen_trunc_i64_tl(cpu_sr_ov, t1); tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); =20 gen_ove_ov(dc); } - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); } =20 static void gen_muldu(DisasContext *dc, TCGv srca, TCGv srcb) @@ -340,12 +329,9 @@ static void gen_muldu(DisasContext *dc, TCGv srca, TCG= v srcb) tcg_gen_mulu2_i64(cpu_mac, high, t1, t2); tcg_gen_setcondi_i64(TCG_COND_NE, high, high, 0); tcg_gen_trunc_i64_tl(cpu_sr_cy, high); - tcg_temp_free_i64(high); =20 gen_ove_cy(dc); } - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); } =20 static void gen_mac(DisasContext *dc, TCGv srca, TCGv srcb) @@ -362,14 +348,12 @@ static void gen_mac(DisasContext *dc, TCGv srca, TCGv= srcb) tcg_gen_add_i64(cpu_mac, cpu_mac, t1); tcg_gen_xor_i64(t1, t1, cpu_mac); tcg_gen_andc_i64(t1, t1, t2); - tcg_temp_free_i64(t2); =20 #if TARGET_LONG_BITS =3D=3D 32 tcg_gen_extrh_i64_i32(cpu_sr_ov, t1); #else tcg_gen_mov_i64(cpu_sr_ov, t1); #endif - tcg_temp_free_i64(t1); =20 gen_ove_ov(dc); } @@ -382,13 +366,11 @@ static void gen_macu(DisasContext *dc, TCGv srca, TCG= v srcb) tcg_gen_extu_tl_i64(t1, srca); tcg_gen_extu_tl_i64(t2, srcb); tcg_gen_mul_i64(t1, t1, t2); - tcg_temp_free_i64(t2); =20 /* Note that overflow is only computed during addition stage. */ tcg_gen_add_i64(cpu_mac, cpu_mac, t1); tcg_gen_setcond_i64(TCG_COND_LTU, t1, cpu_mac, t1); tcg_gen_trunc_i64_tl(cpu_sr_cy, t1); - tcg_temp_free_i64(t1); =20 gen_ove_cy(dc); } @@ -407,14 +389,12 @@ static void gen_msb(DisasContext *dc, TCGv srca, TCGv= srcb) tcg_gen_sub_i64(cpu_mac, cpu_mac, t1); tcg_gen_xor_i64(t1, t1, cpu_mac); tcg_gen_and_i64(t1, t1, t2); - tcg_temp_free_i64(t2); =20 #if TARGET_LONG_BITS =3D=3D 32 tcg_gen_extrh_i64_i32(cpu_sr_ov, t1); #else tcg_gen_mov_i64(cpu_sr_ov, t1); #endif - tcg_temp_free_i64(t1); =20 gen_ove_ov(dc); } @@ -432,8 +412,6 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCGv = srcb) tcg_gen_setcond_i64(TCG_COND_LTU, t2, cpu_mac, t1); tcg_gen_sub_i64(cpu_mac, cpu_mac, t1); tcg_gen_trunc_i64_tl(cpu_sr_cy, t2); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t1); =20 gen_ove_cy(dc); } @@ -672,7 +650,6 @@ static bool trans_l_lwa(DisasContext *dc, arg_load *a) tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, MO_TEUL); tcg_gen_mov_tl(cpu_lock_addr, ea); tcg_gen_mov_tl(cpu_lock_value, cpu_R(dc, a->d)); - tcg_temp_free(ea); return true; } =20 @@ -684,7 +661,6 @@ static void do_load(DisasContext *dc, arg_load *a, MemO= p mop) ea =3D tcg_temp_new(); tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, mop); - tcg_temp_free(ea); } =20 static bool trans_l_lwz(DisasContext *dc, arg_load *a) @@ -734,13 +710,11 @@ static bool trans_l_swa(DisasContext *dc, arg_store *= a) lab_fail =3D gen_new_label(); lab_done =3D gen_new_label(); tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail); - tcg_temp_free(ea); =20 val =3D tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value, cpu_R(dc, a->b), dc->mem_idx, MO_TEUL); tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); - tcg_temp_free(val); =20 tcg_gen_br(lab_done); =20 @@ -757,7 +731,6 @@ static void do_store(DisasContext *dc, arg_store *a, Me= mOp mop) TCGv t0 =3D tcg_temp_new(); tcg_gen_addi_tl(t0, cpu_R(dc, a->a), a->i); tcg_gen_qemu_st_tl(cpu_R(dc, a->b), t0, dc->mem_idx, mop); - tcg_temp_free(t0); } =20 static bool trans_l_sw(DisasContext *dc, arg_store *a) @@ -866,7 +839,6 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr= *a) =20 tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr); - tcg_temp_free(spr); } return true; } @@ -897,7 +869,6 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr= *a) spr =3D tcg_temp_new(); tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); gen_helper_mtspr(cpu_env, spr, cpu_R(dc, a->b)); - tcg_temp_free(spr); } return true; } @@ -1349,8 +1320,6 @@ static bool do_dp3(DisasContext *dc, arg_dab_pair *a, load_pair(dc, t1, a->b, a->bp); fn(t0, cpu_env, t0, t1); save_pair(dc, t0, a->d, a->dp); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); =20 gen_helper_update_fpcsr(cpu_env); return true; @@ -1372,7 +1341,6 @@ static bool do_dp2(DisasContext *dc, arg_da_pair *a, load_pair(dc, t0, a->a, a->ap); fn(t0, cpu_env, t0); save_pair(dc, t0, a->d, a->dp); - tcg_temp_free_i64(t0); =20 gen_helper_update_fpcsr(cpu_env); return true; @@ -1399,8 +1367,6 @@ static bool do_dpcmp(DisasContext *dc, arg_ab_pair *a, } else { fn(cpu_sr_f, cpu_env, t0, t1); } - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); =20 if (inv) { tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); @@ -1457,7 +1423,6 @@ static bool trans_lf_stod_d(DisasContext *dc, arg_lf_= stod_d *a) t0 =3D tcg_temp_new_i64(); gen_helper_stod(t0, cpu_env, cpu_R(dc, a->a)); save_pair(dc, t0, a->d, a->dp); - tcg_temp_free_i64(t0); =20 gen_helper_update_fpcsr(cpu_env); return true; @@ -1476,7 +1441,6 @@ static bool trans_lf_dtos_d(DisasContext *dc, arg_lf_= dtos_d *a) t0 =3D tcg_temp_new_i64(); load_pair(dc, t0, a->a, a->ap); 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Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/ppc/translate.c | 283 ------------------ target/ppc/power8-pmu-regs.c.inc | 16 - target/ppc/translate/dfp-impl.c.inc | 20 -- target/ppc/translate/fixedpoint-impl.c.inc | 16 - target/ppc/translate/fp-impl.c.inc | 122 +------- target/ppc/translate/spe-impl.c.inc | 59 ---- target/ppc/translate/storage-ctrl-impl.c.inc | 2 - target/ppc/translate/vmx-impl.c.inc | 296 +------------------ target/ppc/translate/vsx-impl.c.inc | 287 +----------------- 9 files changed, 7 insertions(+), 1094 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index c179f26f64..f74f3b8f0d 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -266,8 +266,6 @@ static void gen_exception_err(DisasContext *ctx, uint32= _t excp, uint32_t error) t0 =3D tcg_const_i32(excp); t1 =3D tcg_const_i32(error); gen_helper_raise_exception_err(cpu_env, t0, t1); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); ctx->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -282,7 +280,6 @@ static void gen_exception(DisasContext *ctx, uint32_t e= xcp) gen_update_nip(ctx, ctx->cia); t0 =3D tcg_const_i32(excp); gen_helper_raise_exception(cpu_env, t0); - tcg_temp_free_i32(t0); ctx->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -294,7 +291,6 @@ static void gen_exception_nip(DisasContext *ctx, uint32= _t excp, gen_update_nip(ctx, nip); t0 =3D tcg_const_i32(excp); gen_helper_raise_exception(cpu_env, t0); - tcg_temp_free_i32(t0); ctx->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -341,7 +337,6 @@ static uint32_t gen_prep_dbgex(DisasContext *ctx) gen_load_spr(t0, SPR_BOOKE_DBSR); tcg_gen_ori_tl(t0, t0, dbsr); gen_store_spr(SPR_BOOKE_DBSR, t0); - tcg_temp_free(t0); return POWERPC_EXCP_DEBUG; } else { return POWERPC_EXCP_TRACE; @@ -393,7 +388,6 @@ static void spr_load_dump_spr(int sprn) #ifdef PPC_DUMP_SPR_ACCESSES TCGv_i32 t0 =3D tcg_const_i32(sprn); gen_helper_load_dump_spr(cpu_env, t0); - tcg_temp_free_i32(t0); #endif } =20 @@ -408,7 +402,6 @@ static void spr_store_dump_spr(int sprn) #ifdef PPC_DUMP_SPR_ACCESSES TCGv_i32 t0 =3D tcg_const_i32(sprn); gen_helper_store_dump_spr(cpu_env, t0); - tcg_temp_free_i32(t0); #endif } =20 @@ -437,7 +430,6 @@ void spr_write_generic32(DisasContext *ctx, int sprn, i= nt gprn) TCGv t0 =3D tcg_temp_new(); tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); gen_store_spr(sprn, t0); - tcg_temp_free(t0); spr_store_dump_spr(sprn); #else spr_write_generic(ctx, sprn, gprn); @@ -452,8 +444,6 @@ void spr_write_clear(DisasContext *ctx, int sprn, int g= prn) tcg_gen_neg_tl(t1, cpu_gpr[gprn]); tcg_gen_and_tl(t0, t0, t1); gen_store_spr(sprn, t0); - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 void spr_access_nop(DisasContext *ctx, int sprn, int gprn) @@ -483,9 +473,6 @@ void spr_read_xer(DisasContext *ctx, int gprn, int sprn) tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); tcg_gen_or_tl(dst, dst, t0); } - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } =20 void spr_write_xer(DisasContext *ctx, int sprn, int gprn) @@ -687,28 +674,24 @@ void spr_write_ibatu(DisasContext *ctx, int sprn, int= gprn) { TCGv_i32 t0 =3D tcg_const_i32((sprn - SPR_IBAT0U) / 2); gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); } =20 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 =3D tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); } =20 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 =3D tcg_const_i32((sprn - SPR_IBAT0L) / 2); gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); } =20 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 =3D tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); } =20 /* DBAT0U...DBAT7U */ @@ -731,28 +714,24 @@ void spr_write_dbatu(DisasContext *ctx, int sprn, int= gprn) { TCGv_i32 t0 =3D tcg_const_i32((sprn - SPR_DBAT0U) / 2); gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); } =20 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 =3D tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); } =20 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 =3D tcg_const_i32((sprn - SPR_DBAT0L) / 2); gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); } =20 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 =3D tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); } =20 /* SDR1 */ @@ -784,7 +763,6 @@ void spr_write_hior(DisasContext *ctx, int sprn, int gp= rn) TCGv t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); - tcg_temp_free(t0); } void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) { @@ -855,7 +833,6 @@ void spr_write_40x_pid(DisasContext *ctx, int sprn, int= gprn) TCGv t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); gen_helper_store_40x_pid(cpu_env, t0); - tcg_temp_free(t0); } =20 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) @@ -878,7 +855,6 @@ void spr_write_pir(DisasContext *ctx, int sprn, int gpr= n) TCGv t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); gen_store_spr(SPR_PIR, t0); - tcg_temp_free(t0); } #endif =20 @@ -888,7 +864,6 @@ void spr_read_spefscr(DisasContext *ctx, int gprn, int = sprn) TCGv_i32 t0 =3D tcg_temp_new_i32(); tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); - tcg_temp_free_i32(t0); } =20 void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) @@ -896,7 +871,6 @@ void spr_write_spefscr(DisasContext *ctx, int sprn, int= gprn) TCGv_i32 t0 =3D tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); - tcg_temp_free_i32(t0); } =20 #if !defined(CONFIG_USER_ONLY) @@ -908,7 +882,6 @@ void spr_write_excp_prefix(DisasContext *ctx, int sprn,= int gprn) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); gen_store_spr(sprn, t0); - tcg_temp_free(t0); } =20 void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) @@ -933,7 +906,6 @@ void spr_write_excp_vector(DisasContext *ctx, int sprn,= int gprn) tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_off= s])); gen_store_spr(sprn, t0); - tcg_temp_free(t0); } #endif =20 @@ -968,10 +940,6 @@ void spr_write_amr(DisasContext *ctx, int sprn, int gp= rn) tcg_gen_or_tl(t0, t0, t2); gen_store_spr(SPR_AMR, t0); spr_store_dump_spr(SPR_AMR); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } =20 void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) @@ -999,10 +967,6 @@ void spr_write_uamor(DisasContext *ctx, int sprn, int = gprn) tcg_gen_or_tl(t0, t0, t2); gen_store_spr(SPR_UAMOR, t0); spr_store_dump_spr(SPR_UAMOR); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } =20 void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) @@ -1030,10 +994,6 @@ void spr_write_iamr(DisasContext *ctx, int sprn, int = gprn) tcg_gen_or_tl(t0, t0, t2); gen_store_spr(SPR_IAMR, t0); spr_store_dump_spr(SPR_IAMR); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } #endif #endif @@ -1054,7 +1014,6 @@ void spr_write_e500_l1csr0(DisasContext *ctx, int spr= n, int gprn) =20 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); gen_store_spr(sprn, t0); - tcg_temp_free(t0); } =20 void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) @@ -1063,7 +1022,6 @@ void spr_write_e500_l1csr1(DisasContext *ctx, int spr= n, int gprn) =20 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); gen_store_spr(sprn, t0); - tcg_temp_free(t0); } =20 void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) @@ -1073,7 +1031,6 @@ void spr_write_e500_l2csr0(DisasContext *ctx, int spr= n, int gprn) tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2= LFC)); gen_store_spr(sprn, t0); - tcg_temp_free(t0); } =20 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) @@ -1085,7 +1042,6 @@ void spr_write_booke_pid(DisasContext *ctx, int sprn,= int gprn) { TCGv_i32 t0 =3D tcg_const_i32(sprn); gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); - tcg_temp_free_i32(t0); } void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) { @@ -1106,7 +1062,6 @@ void spr_write_mas73(DisasContext *ctx, int sprn, int= gprn) gen_store_spr(SPR_BOOKE_MAS3, val); tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); gen_store_spr(SPR_BOOKE_MAS7, val); - tcg_temp_free(val); } =20 void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) @@ -1117,8 +1072,6 @@ void spr_read_mas73(DisasContext *ctx, int gprn, int = sprn) tcg_gen_shli_tl(mas7, mas7, 32); gen_load_spr(mas3, SPR_BOOKE_MAS3); tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); - tcg_temp_free(mas3); - tcg_temp_free(mas7); } =20 #endif @@ -1132,10 +1085,6 @@ static void gen_fscr_facility_check(DisasContext *ct= x, int facility_sprn, TCGv_i32 t3 =3D tcg_const_i32(cause); =20 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); - - tcg_temp_free_i32(t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t1); } =20 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, @@ -1146,10 +1095,6 @@ static void gen_msr_facility_check(DisasContext *ctx= , int facility_sprn, TCGv_i32 t3 =3D tcg_const_i32(cause); =20 gen_helper_msr_facility_check(cpu_env, t1, t2, t3); - - tcg_temp_free_i32(t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t1); } =20 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) @@ -1160,9 +1105,6 @@ void spr_read_prev_upper32(DisasContext *ctx, int gpr= n, int sprn) gen_load_spr(spr, sprn - 1); tcg_gen_shri_tl(spr_up, spr, 32); tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); - - tcg_temp_free(spr); - tcg_temp_free(spr_up); } =20 void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) @@ -1172,8 +1114,6 @@ void spr_write_prev_upper32(DisasContext *ctx, int sp= rn, int gprn) gen_load_spr(spr, sprn - 1); tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); gen_store_spr(sprn - 1, spr); - - tcg_temp_free(spr); } =20 #if !defined(CONFIG_USER_ONLY) @@ -1185,7 +1125,6 @@ void spr_write_hmer(DisasContext *ctx, int sprn, int = gprn) tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); gen_store_spr(sprn, hmer); spr_store_dump_spr(sprn); - tcg_temp_free(hmer); } =20 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) @@ -1269,8 +1208,6 @@ void spr_read_dexcr_ureg(DisasContext *ctx, int gprn,= int sprn) =20 gen_load_spr(t0, sprn + 16); tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); - - tcg_temp_free(t0); } #endif =20 @@ -1447,17 +1384,12 @@ static inline void gen_op_cmp(TCGv arg0, TCGv arg1,= int s, int crf) tcg_gen_trunc_tl_i32(t, t0); tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free_i32(t); } =20 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int cr= f) { TCGv t0 =3D tcg_const_tl(arg1); gen_op_cmp(arg0, t0, s, crf); - tcg_temp_free(t0); } =20 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) @@ -1473,15 +1405,12 @@ static inline void gen_op_cmp32(TCGv arg0, TCGv arg= 1, int s, int crf) tcg_gen_ext32u_tl(t1, arg1); } gen_op_cmp(t0, t1, s, crf); - tcg_temp_free(t1); - tcg_temp_free(t0); } =20 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int = crf) { TCGv t0 =3D tcg_const_tl(arg1); gen_op_cmp32(arg0, t0, s, crf); - tcg_temp_free(t0); } =20 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) @@ -1525,10 +1454,6 @@ static void gen_cmprb(DisasContext *ctx) tcg_gen_or_i32(crf, crf, src2lo); } tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); - tcg_temp_free_i32(src1); - tcg_temp_free_i32(src2); - tcg_temp_free_i32(src2lo); - tcg_temp_free_i32(src2hi); } =20 #if defined(TARGET_PPC64) @@ -1555,8 +1480,6 @@ static void gen_isel(DisasContext *ctx) tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, cpu_gpr[rB(ctx->opcode)]); - tcg_temp_free(zr); - tcg_temp_free(t0); } =20 /* cmpb: PowerPC 2.05 specification */ @@ -1580,7 +1503,6 @@ static inline void gen_op_arith_compute_ov(DisasConte= xt *ctx, TCGv arg0, } else { tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); } - tcg_temp_free(t0); if (NARROW_MODE(ctx)) { tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); if (is_isa300(ctx)) { @@ -1613,7 +1535,6 @@ static inline void gen_op_arith_compute_ca32(DisasCon= text *ctx, } tcg_gen_xor_tl(t0, t0, res); tcg_gen_extract_tl(ca32, t0, 32, 1); - tcg_temp_free(t0); } =20 /* Common add function */ @@ -1642,7 +1563,6 @@ static inline void gen_op_arith_add(DisasContext *ctx= , TCGv ret, TCGv arg1, tcg_gen_add_tl(t0, t0, ca); } tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ - tcg_temp_free(t1); tcg_gen_extract_tl(ca, ca, 32, 1); if (is_isa300(ctx)) { tcg_gen_mov_tl(ca32, ca); @@ -1656,7 +1576,6 @@ static inline void gen_op_arith_add(DisasContext *ctx= , TCGv ret, TCGv arg1, tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); } gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); - tcg_temp_free(zero); } } else { tcg_gen_add_tl(t0, arg1, arg2); @@ -1674,7 +1593,6 @@ static inline void gen_op_arith_add(DisasContext *ctx= , TCGv ret, TCGv arg1, =20 if (t0 !=3D ret) { tcg_gen_mov_tl(ret, t0); - tcg_temp_free(t0); } } /* Add functions with two operands */ @@ -1696,7 +1614,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ cpu_gpr[rA(ctx->opcode)], t0, = \ ca, glue(ca, 32), = \ add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); = \ - tcg_temp_free(t0); = \ } =20 /* add add. addo addo. */ @@ -1722,7 +1639,6 @@ static inline void gen_op_addic(DisasContext *ctx, bo= ol compute_rc0) TCGv c =3D tcg_const_tl(SIMM(ctx->opcode)); gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode= )], c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); - tcg_temp_free(c); } =20 static void gen_addic(DisasContext *ctx) @@ -1769,10 +1685,6 @@ static inline void gen_op_arith_divw(DisasContext *c= tx, TCGv ret, TCGv arg1, } tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); } - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); =20 if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, ret); @@ -1800,7 +1712,6 @@ static void gen_##name(DisasContext *ctx) = \ TCGv_i32 t0 =3D tcg_const_i32(compute_ov); = \ gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, = \ cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t= 0); \ - tcg_temp_free_i32(t0); = \ if (unlikely(Rc(ctx->opcode) !=3D 0)) { = \ gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); = \ } = \ @@ -1844,10 +1755,6 @@ static inline void gen_op_arith_divd(DisasContext *c= tx, TCGv ret, TCGv arg1, } tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); } - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); =20 if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, ret); @@ -1894,19 +1801,13 @@ static inline void gen_op_arith_modw(DisasContext *= ctx, TCGv ret, TCGv arg1, tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); tcg_gen_rem_i32(t3, t0, t1); tcg_gen_ext_i32_tl(ret, t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } else { TCGv_i32 t2 =3D tcg_const_i32(1); TCGv_i32 t3 =3D tcg_const_i32(0); tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); tcg_gen_remu_i32(t3, t0, t1); tcg_gen_extu_i32_tl(ret, t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); } =20 #define GEN_INT_ARITH_MODW(name, opc3, sign) = \ @@ -1940,18 +1841,12 @@ static inline void gen_op_arith_modd(DisasContext *= ctx, TCGv ret, TCGv arg1, tcg_gen_movi_i64(t3, 0); tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); tcg_gen_rem_i64(ret, t0, t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); } else { TCGv_i64 t2 =3D tcg_const_i64(1); TCGv_i64 t3 =3D tcg_const_i64(0); tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); tcg_gen_remu_i64(ret, t0, t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); } - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 #define GEN_INT_ARITH_MODD(name, opc3, sign) \ @@ -1976,8 +1871,6 @@ static void gen_mulhw(DisasContext *ctx) tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); tcg_gen_muls2_i32(t0, t1, t0, t1); tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); } @@ -1993,8 +1886,6 @@ static void gen_mulhwu(DisasContext *ctx) tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); tcg_gen_mulu2_i32(t0, t1, t0, t1); tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); } @@ -2010,8 +1901,6 @@ static void gen_mullw(DisasContext *ctx) tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); - tcg_temp_free(t0); - tcg_temp_free(t1); #else tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); @@ -2044,8 +1933,6 @@ static void gen_mullwo(DisasContext *ctx) } tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); =20 - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); } @@ -2065,7 +1952,6 @@ static void gen_mulhd(DisasContext *ctx) TCGv lo =3D tcg_temp_new(); tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); - tcg_temp_free(lo); if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); } @@ -2077,7 +1963,6 @@ static void gen_mulhdu(DisasContext *ctx) TCGv lo =3D tcg_temp_new(); tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); - tcg_temp_free(lo); if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); } @@ -2110,9 +1995,6 @@ static void gen_mulldo(DisasContext *ctx) } tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); =20 - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); } @@ -2148,9 +2030,7 @@ static inline void gen_op_arith_subf(DisasContext *ct= x, TCGv ret, TCGv arg1, } tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ tcg_gen_add_tl(t0, t0, inv1); - tcg_temp_free(inv1); tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ car= ry */ - tcg_temp_free(t1); tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); if (is_isa300(ctx)) { tcg_gen_mov_tl(cpu_ca32, cpu_ca); @@ -2162,8 +2042,6 @@ static inline void gen_op_arith_subf(DisasContext *ct= x, TCGv ret, TCGv arg1, tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); - tcg_temp_free(zero); - tcg_temp_free(inv1); } else { tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); tcg_gen_sub_tl(t0, arg2, arg1); @@ -2190,7 +2068,6 @@ static inline void gen_op_arith_subf(DisasContext *ct= x, TCGv ret, TCGv arg1, =20 if (t0 !=3D ret) { tcg_gen_mov_tl(ret, t0); - tcg_temp_free(t0); } } /* Sub functions with Two operands functions */ @@ -2210,7 +2087,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], = \ cpu_gpr[rA(ctx->opcode)], t0, = \ add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); = \ - tcg_temp_free(t0); = \ } /* subf subf. subfo subfo. */ GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) @@ -2234,7 +2110,6 @@ static void gen_subfic(DisasContext *ctx) TCGv c =3D tcg_const_tl(SIMM(ctx->opcode)); gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcod= e)], c, 0, 1, 0, 0); - tcg_temp_free(c); } =20 /* neg neg. nego nego. */ @@ -2243,7 +2118,6 @@ static inline void gen_op_arith_neg(DisasContext *ctx= , bool compute_ov) TCGv zero =3D tcg_const_tl(0); gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcod= e)], zero, 0, 0, compute_ov, Rc(ctx->opcode)); - tcg_temp_free(zero); } =20 static void gen_neg(DisasContext *ctx) @@ -2306,7 +2180,6 @@ static void gen_cntlzw(DisasContext *ctx) tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); tcg_gen_clzi_i32(t, t, 32); tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); - tcg_temp_free_i32(t); =20 if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); @@ -2321,7 +2194,6 @@ static void gen_cnttzw(DisasContext *ctx) tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); tcg_gen_ctzi_i32(t, t, 32); tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); - tcg_temp_free_i32(t); =20 if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); @@ -2345,7 +2217,6 @@ static void gen_pause(DisasContext *ctx) TCGv_i32 t0 =3D tcg_const_i32(0); tcg_gen_st_i32(t0, cpu_env, -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)= ); - tcg_temp_free_i32(t0); =20 /* Stop translation, this gives other CPUs a chance to run */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); @@ -2424,7 +2295,6 @@ static void gen_or(DisasContext *ctx) tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); gen_store_spr(SPR_PPR, t0); - tcg_temp_free(t0); } #if !defined(CONFIG_USER_ONLY) /* @@ -2539,7 +2409,6 @@ static void gen_prtyw(DisasContext *ctx) tcg_gen_shri_tl(t0, ra, 8); tcg_gen_xor_tl(ra, ra, t0); tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); - tcg_temp_free(t0); } =20 #if defined(TARGET_PPC64) @@ -2556,7 +2425,6 @@ static void gen_prtyd(DisasContext *ctx) tcg_gen_shri_tl(t0, ra, 8); tcg_gen_xor_tl(ra, ra, t0); tcg_gen_andi_tl(ra, ra, 1); - tcg_temp_free(t0); } #endif =20 @@ -2645,7 +2513,6 @@ static void gen_rlwimi(DisasContext *ctx) tcg_gen_trunc_tl_i32(t0, t_rs); tcg_gen_rotli_i32(t0, t0, sh); tcg_gen_extu_i32_tl(t1, t0); - tcg_temp_free_i32(t0); } else { #if defined(TARGET_PPC64) tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); @@ -2658,7 +2525,6 @@ static void gen_rlwimi(DisasContext *ctx) tcg_gen_andi_tl(t1, t1, mask); tcg_gen_andi_tl(t_ra, t_ra, ~mask); tcg_gen_or_tl(t_ra, t_ra, t1); - tcg_temp_free(t1); } if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, t_ra); @@ -2702,7 +2568,6 @@ static void gen_rlwinm(DisasContext *ctx) tcg_gen_rotli_i32(t0, t0, sh); tcg_gen_andi_i32(t0, t0, mask); tcg_gen_extu_i32_tl(t_ra, t0); - tcg_temp_free_i32(t0); } } else { #if defined(TARGET_PPC64) @@ -2749,15 +2614,12 @@ static void gen_rlwnm(DisasContext *ctx) tcg_gen_andi_i32(t0, t0, 0x1f); tcg_gen_rotl_i32(t1, t1, t0); tcg_gen_extu_i32_tl(t_ra, t1); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); } else { #if defined(TARGET_PPC64) TCGv_i64 t0 =3D tcg_temp_new_i64(); tcg_gen_andi_i64(t0, t_rb, 0x1f); tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); tcg_gen_rotl_i64(t_ra, t_ra, t0); - tcg_temp_free_i64(t0); #else g_assert_not_reached(); #endif @@ -2865,7 +2727,6 @@ static void gen_rldnm(DisasContext *ctx, int mb, int = me) t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, t_rb, 0x3f); tcg_gen_rotl_tl(t_ra, t_rs, t0); - tcg_temp_free(t0); =20 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); if (unlikely(Rc(ctx->opcode) !=3D 0)) { @@ -2912,7 +2773,6 @@ static void gen_rldimi(DisasContext *ctx, int mbn, in= t shn) tcg_gen_andi_tl(t1, t1, mask); tcg_gen_andi_tl(t_ra, t_ra, ~mask); tcg_gen_or_tl(t_ra, t_ra, t1); - tcg_temp_free(t1); } if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, t_ra); @@ -2941,8 +2801,6 @@ static void gen_slw(DisasContext *ctx) t1 =3D tcg_temp_new(); tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); - tcg_temp_free(t1); - tcg_temp_free(t0); tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); @@ -2978,7 +2836,6 @@ static void gen_srawi(DisasContext *ctx) t0 =3D tcg_temp_new(); tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); tcg_gen_and_tl(cpu_ca, cpu_ca, t0); - tcg_temp_free(t0); tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); if (is_isa300(ctx)) { tcg_gen_mov_tl(cpu_ca32, cpu_ca); @@ -3009,8 +2866,6 @@ static void gen_srw(DisasContext *ctx) t1 =3D tcg_temp_new(); tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); - tcg_temp_free(t1); - tcg_temp_free(t0); if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); } @@ -3030,8 +2885,6 @@ static void gen_sld(DisasContext *ctx) t1 =3D tcg_temp_new(); tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); - tcg_temp_free(t1); - tcg_temp_free(t0); if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); } @@ -3064,7 +2917,6 @@ static inline void gen_sradi(DisasContext *ctx, int n) t0 =3D tcg_temp_new(); tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); tcg_gen_and_tl(cpu_ca, cpu_ca, t0); - tcg_temp_free(t0); tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); if (is_isa300(ctx)) { tcg_gen_mov_tl(cpu_ca32, cpu_ca); @@ -3123,8 +2975,6 @@ static void gen_srd(DisasContext *ctx) t1 =3D tcg_temp_new(); tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); - tcg_temp_free(t1); - tcg_temp_free(t0); if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); } @@ -3296,7 +3146,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) = \ EA =3D tcg_temp_new(); = \ gen_addr_reg_index(ctx, EA); = \ gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); = \ - tcg_temp_free(EA); = \ } =20 #define GEN_LDX(name, ldop, opc2, opc3, type) = \ @@ -3314,7 +3163,6 @@ static void glue(gen_, name##epx)(DisasContext *ctx) = \ EA =3D tcg_temp_new(); = \ gen_addr_reg_index(ctx, EA); = \ tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ld= op);\ - tcg_temp_free(EA); = \ } =20 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) @@ -3342,7 +3190,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) = \ EA =3D tcg_temp_new(); = \ gen_addr_reg_index(ctx, EA); = \ gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); = \ - tcg_temp_free(EA); = \ } #define GEN_STX(name, stop, opc2, opc3, type) = \ GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) @@ -3360,7 +3207,6 @@ static void glue(gen_, name##epx)(DisasContext *ctx) = \ gen_addr_reg_index(ctx, EA); = \ tcg_gen_qemu_st_tl( = \ cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); = \ - tcg_temp_free(EA); = \ } =20 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) @@ -3413,8 +3259,6 @@ static void gen_lmw(DisasContext *ctx) t1 =3D tcg_const_i32(rD(ctx->opcode)); gen_addr_imm_index(ctx, t0, 0); gen_helper_lmw(cpu_env, t0, t1); - tcg_temp_free(t0); - tcg_temp_free_i32(t1); } =20 /* stmw */ @@ -3432,8 +3276,6 @@ static void gen_stmw(DisasContext *ctx) t1 =3D tcg_const_i32(rS(ctx->opcode)); gen_addr_imm_index(ctx, t0, 0); gen_helper_stmw(cpu_env, t0, t1); - tcg_temp_free(t0); - tcg_temp_free_i32(t1); } =20 /*** Integer load and store strings = ***/ @@ -3472,9 +3314,6 @@ static void gen_lswi(DisasContext *ctx) t1 =3D tcg_const_i32(nb); t2 =3D tcg_const_i32(start); gen_helper_lsw(cpu_env, t0, t1, t2); - tcg_temp_free(t0); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); } =20 /* lswx */ @@ -3494,10 +3333,6 @@ static void gen_lswx(DisasContext *ctx) t2 =3D tcg_const_i32(rA(ctx->opcode)); t3 =3D tcg_const_i32(rB(ctx->opcode)); gen_helper_lswx(cpu_env, t0, t1, t2, t3); - tcg_temp_free(t0); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } =20 /* stswi */ @@ -3520,9 +3355,6 @@ static void gen_stswi(DisasContext *ctx) t1 =3D tcg_const_i32(nb); t2 =3D tcg_const_i32(rS(ctx->opcode)); gen_helper_stsw(cpu_env, t0, t1, t2); - tcg_temp_free(t0); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); } =20 /* stswx */ @@ -3543,9 +3375,6 @@ static void gen_stswx(DisasContext *ctx) tcg_gen_andi_i32(t1, t1, 0x7F); t2 =3D tcg_const_i32(rS(ctx->opcode)); gen_helper_stsw(cpu_env, t0, t1, t2); - tcg_temp_free(t0); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); } =20 /*** Memory synchronisation = ***/ @@ -3620,7 +3449,6 @@ static inline void gen_check_tlb_flush(DisasContext *= ctx, bool global) gen_helper_check_tlb_flush_local(cpu_env); } gen_set_label(l); - tcg_temp_free_i32(t); } #else static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } @@ -3653,7 +3481,6 @@ static void gen_load_locked(DisasContext *ctx, MemOp = memop) tcg_gen_mov_tl(cpu_reserve, t0); tcg_gen_mov_tl(cpu_reserve_val, gpr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - tcg_temp_free(t0); } =20 #define LARX(name, memop) \ @@ -3687,10 +3514,6 @@ static void gen_fetch_inc_conditional(DisasContext *= ctx, MemOp memop, /* RT =3D (t !=3D t2 ? t : u =3D 1<<(s*8-1)) */ tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); - - tcg_temp_free(t); - tcg_temp_free(t2); - tcg_temp_free(u); } =20 static void gen_ld_atomic(DisasContext *ctx, MemOp memop) @@ -3753,9 +3576,6 @@ static void gen_ld_atomic(DisasContext *ctx, MemOp me= mop) cpu_gpr[(rt + 2) & 31], t0); tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); tcg_gen_mov_tl(dst, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); } break; =20 @@ -3785,7 +3605,6 @@ static void gen_ld_atomic(DisasContext *ctx, MemOp me= mop) /* invoke data storage error handler */ gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); } - tcg_temp_free(EA); =20 if (need_serial) { /* Restart with exclusive lock. */ @@ -3861,20 +3680,12 @@ static void gen_st_atomic(DisasContext *ctx, MemOp = memop) tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); - - tcg_temp_free(ea_plus_s); - tcg_temp_free(s2); - tcg_temp_free(s); - tcg_temp_free(t2); - tcg_temp_free(t); } break; default: /* invoke data storage error handler */ gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); } - tcg_temp_free(discard); - tcg_temp_free(EA); } =20 static void gen_stwat(DisasContext *ctx) @@ -3899,7 +3710,6 @@ static void gen_conditional_store(DisasContext *ctx, = MemOp memop) gen_set_access_type(ctx, ACCESS_RES); gen_addr_reg_index(ctx, t0); tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); - tcg_temp_free(t0); =20 t0 =3D tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, @@ -3909,7 +3719,6 @@ static void gen_conditional_store(DisasContext *ctx, = MemOp memop) tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); tcg_gen_or_tl(t0, t0, cpu_so); tcg_gen_trunc_tl_i32(cpu_crf[0], t0); - tcg_temp_free(t0); tcg_gen_br(l2); =20 gen_set_label(l1); @@ -3973,13 +3782,11 @@ static void gen_lqarx(DisasContext *ctx) ctx->mem_idx)); gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); } - tcg_temp_free_i32(oi); tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); } else { /* Restart with exclusive lock. */ gen_helper_exit_atomic(cpu_env); ctx->base.is_jmp =3D DISAS_NORETURN; - tcg_temp_free(EA); return; } } else if (ctx->le_mode) { @@ -3993,7 +3800,6 @@ static void gen_lqarx(DisasContext *ctx) gen_addr_add(ctx, EA, EA, 8); tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEUQ); } - tcg_temp_free(EA); =20 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); @@ -4020,7 +3826,6 @@ static void gen_stqcx_(DisasContext *ctx) gen_addr_reg_index(ctx, EA); =20 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); - tcg_temp_free(EA); =20 cmp =3D tcg_temp_new_i128(); val =3D tcg_temp_new_i128(); @@ -4032,23 +3837,19 @@ static void gen_stqcx_(DisasContext *ctx) =20 tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); - tcg_temp_free_i128(cmp); =20 t0 =3D tcg_temp_new(); t1 =3D tcg_temp_new(); tcg_gen_extr_i128_i64(t1, t0, val); - tcg_temp_free_i128(val); =20 tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); tcg_gen_xor_tl(t0, t0, cpu_reserve_val); tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); =20 tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); tcg_gen_or_tl(t0, t0, cpu_so); tcg_gen_trunc_tl_i32(cpu_crf[0], t0); - tcg_temp_free(t0); =20 tcg_gen_br(lab_over); gen_set_label(lab_fail); @@ -4145,7 +3946,6 @@ static void gen_wait(DisasContext *ctx) TCGv_i32 t0 =3D tcg_const_i32(1); tcg_gen_st_i32(t0, cpu_env, -offsetof(PowerPCCPU, env) + offsetof(CPUState, hal= ted)); - tcg_temp_free_i32(t0); /* Stop translation, as the CPU is supposed to sleep from now */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); } @@ -4191,7 +3991,6 @@ static void gen_doze(DisasContext *ctx) CHK_HV(ctx); t =3D tcg_const_i32(PPC_PM_DOZE); gen_helper_pminsn(cpu_env, t); - tcg_temp_free_i32(t); /* Stop translation, as the CPU is supposed to sleep from now */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); #endif /* defined(CONFIG_USER_ONLY) */ @@ -4207,7 +4006,6 @@ static void gen_nap(DisasContext *ctx) CHK_HV(ctx); t =3D tcg_const_i32(PPC_PM_NAP); gen_helper_pminsn(cpu_env, t); - tcg_temp_free_i32(t); /* Stop translation, as the CPU is supposed to sleep from now */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); #endif /* defined(CONFIG_USER_ONLY) */ @@ -4223,7 +4021,6 @@ static void gen_stop(DisasContext *ctx) CHK_HV(ctx); t =3D tcg_const_i32(PPC_PM_STOP); gen_helper_pminsn(cpu_env, t); - tcg_temp_free_i32(t); /* Stop translation, as the CPU is supposed to sleep from now */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); #endif /* defined(CONFIG_USER_ONLY) */ @@ -4239,7 +4036,6 @@ static void gen_sleep(DisasContext *ctx) CHK_HV(ctx); t =3D tcg_const_i32(PPC_PM_SLEEP); gen_helper_pminsn(cpu_env, t); - tcg_temp_free_i32(t); /* Stop translation, as the CPU is supposed to sleep from now */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); #endif /* defined(CONFIG_USER_ONLY) */ @@ -4255,7 +4051,6 @@ static void gen_rvwinkle(DisasContext *ctx) CHK_HV(ctx); t =3D tcg_const_i32(PPC_PM_RVWINKLE); gen_helper_pminsn(cpu_env, t); - tcg_temp_free_i32(t); /* Stop translation, as the CPU is supposed to sleep from now */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); #endif /* defined(CONFIG_USER_ONLY) */ @@ -4309,7 +4104,6 @@ static void pmu_count_insns(DisasContext *ctx) } =20 gen_set_label(l); - tcg_temp_free(t0); } else { gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns= )); } @@ -4324,8 +4118,6 @@ static void pmu_count_insns(DisasContext *ctx) gen_load_spr(t0, SPR_POWER_PMC5); tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); gen_store_spr(SPR_POWER_PMC5, t0); - - tcg_temp_free(t0); #endif /* #if !defined(CONFIG_USER_ONLY) */ } #else @@ -4451,8 +4243,6 @@ static void gen_bcond(DisasContext *ctx, int type) */ if (unlikely(!is_book3s_arch2x(ctx))) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); - tcg_temp_free(temp); - tcg_temp_free(target); return; } =20 @@ -4480,7 +4270,6 @@ static void gen_bcond(DisasContext *ctx, int type) tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); } } - tcg_temp_free(temp); } if ((bo & 0x10) =3D=3D 0) { /* Test CR */ @@ -4495,7 +4284,6 @@ static void gen_bcond(DisasContext *ctx, int type) tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); } - tcg_temp_free_i32(temp); } gen_update_cfar(ctx, ctx->cia); if (type =3D=3D BCOND_IM) { @@ -4512,7 +4300,6 @@ static void gen_bcond(DisasContext *ctx, int type) tcg_gen_andi_tl(cpu_nip, target, ~3); } gen_lookup_and_goto_ptr(ctx); - tcg_temp_free(target); } if ((bo & 0x14) !=3D 0x14) { /* fallthrough case */ @@ -4570,8 +4357,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ tcg_gen_andi_i32(t0, t0, bitmask); = \ tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); = \ tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); = \ - tcg_temp_free_i32(t0); = \ - tcg_temp_free_i32(t1); = \ } =20 /* crand */ @@ -4724,7 +4509,6 @@ static void gen_tw(DisasContext *ctx) t0 =3D tcg_const_i32(TO(ctx->opcode)); gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcod= e)], t0); - tcg_temp_free_i32(t0); } =20 /* twi */ @@ -4739,8 +4523,6 @@ static void gen_twi(DisasContext *ctx) t0 =3D tcg_const_tl(SIMM(ctx->opcode)); t1 =3D tcg_const_i32(TO(ctx->opcode)); gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); - tcg_temp_free(t0); - tcg_temp_free_i32(t1); } =20 #if defined(TARGET_PPC64) @@ -4755,7 +4537,6 @@ static void gen_td(DisasContext *ctx) t0 =3D tcg_const_i32(TO(ctx->opcode)); gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcod= e)], t0); - tcg_temp_free_i32(t0); } =20 /* tdi */ @@ -4770,8 +4551,6 @@ static void gen_tdi(DisasContext *ctx) t0 =3D tcg_const_tl(SIMM(ctx->opcode)); t1 =3D tcg_const_i32(TO(ctx->opcode)); gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); - tcg_temp_free(t0); - tcg_temp_free_i32(t1); } #endif =20 @@ -4792,8 +4571,6 @@ static void gen_mcrxr(DisasContext *ctx) tcg_gen_shli_i32(dst, dst, 1); tcg_gen_or_i32(dst, dst, t0); tcg_gen_or_i32(dst, dst, t1); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); =20 tcg_gen_movi_tl(cpu_so, 0); tcg_gen_movi_tl(cpu_ov, 0); @@ -4817,8 +4594,6 @@ static void gen_mcrxrx(DisasContext *ctx) tcg_gen_or_tl(t1, t1, cpu_ca32); tcg_gen_or_tl(t0, t0, t1); tcg_gen_trunc_tl_i32(dst, t0); - tcg_temp_free(t0); - tcg_temp_free(t1); } #endif =20 @@ -4853,7 +4628,6 @@ static void gen_mfcr(DisasContext *ctx) tcg_gen_shli_i32(t0, t0, 4); tcg_gen_or_i32(t0, t0, cpu_crf[7]); tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); - tcg_temp_free_i32(t0); } } =20 @@ -4950,7 +4724,6 @@ static void gen_mtcrf(DisasContext *ctx) tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); tcg_gen_shri_i32(temp, temp, crn * 4); tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); - tcg_temp_free_i32(temp); } } else { TCGv_i32 temp =3D tcg_temp_new_i32(); @@ -4961,7 +4734,6 @@ static void gen_mtcrf(DisasContext *ctx) tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0= xf); } } - tcg_temp_free_i32(temp); } } =20 @@ -5008,9 +4780,6 @@ static void gen_mtmsrd(DisasContext *ctx) =20 /* Must stop the translation as machine state (may have) changed */ ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; - - tcg_temp_free(t0); - tcg_temp_free(t1); #endif /* !defined(CONFIG_USER_ONLY) */ } #endif /* defined(TARGET_PPC64) */ @@ -5050,9 +4819,6 @@ static void gen_mtmsr(DisasContext *ctx) =20 /* Must stop the translation as machine state (may have) changed */ ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; - - tcg_temp_free(t0); - tcg_temp_free(t1); #endif } =20 @@ -5125,8 +4891,6 @@ static void gen_setb(DisasContext *ctx) tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); - - tcg_temp_free_i32(t0); } #endif =20 @@ -5141,7 +4905,6 @@ static void gen_dcbf(DisasContext *ctx) t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); gen_qemu_ld8u(ctx, t0, t0); - tcg_temp_free(t0); } =20 /* dcbfep (external PID dcbf) */ @@ -5154,7 +4917,6 @@ static void gen_dcbfep(DisasContext *ctx) t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); - tcg_temp_free(t0); } =20 /* dcbi (Supervisor only) */ @@ -5173,8 +4935,6 @@ static void gen_dcbi(DisasContext *ctx) /* XXX: specification says this should be treated as a store by the MM= U */ gen_qemu_ld8u(ctx, val, EA); gen_qemu_st8(ctx, val, EA); - tcg_temp_free(val); - tcg_temp_free(EA); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5187,7 +4947,6 @@ static void gen_dcbst(DisasContext *ctx) t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); gen_qemu_ld8u(ctx, t0, t0); - tcg_temp_free(t0); } =20 /* dcbstep (dcbstep External PID version) */ @@ -5199,7 +4958,6 @@ static void gen_dcbstep(DisasContext *ctx) t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); - tcg_temp_free(t0); } =20 /* dcbt */ @@ -5250,7 +5008,6 @@ static void gen_dcbtls(DisasContext *ctx) gen_load_spr(t0, SPR_Exxx_L1CSR0); tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); gen_store_spr(SPR_Exxx_L1CSR0, t0); - tcg_temp_free(t0); } =20 /* dcbz */ @@ -5264,8 +5021,6 @@ static void gen_dcbz(DisasContext *ctx) tcgv_op =3D tcg_const_i32(ctx->opcode & 0x03FF000); gen_addr_reg_index(ctx, tcgv_addr); gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); - tcg_temp_free(tcgv_addr); - tcg_temp_free_i32(tcgv_op); } =20 /* dcbzep */ @@ -5279,8 +5034,6 @@ static void gen_dcbzep(DisasContext *ctx) tcgv_op =3D tcg_const_i32(ctx->opcode & 0x03FF000); gen_addr_reg_index(ctx, tcgv_addr); gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); - tcg_temp_free(tcgv_addr); - tcg_temp_free_i32(tcgv_op); } =20 /* dst / dstt */ @@ -5318,7 +5071,6 @@ static void gen_icbi(DisasContext *ctx) t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); gen_helper_icbi(cpu_env, t0); - tcg_temp_free(t0); } =20 /* icbiep */ @@ -5329,7 +5081,6 @@ static void gen_icbiep(DisasContext *ctx) t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); gen_helper_icbiep(cpu_env, t0); - tcg_temp_free(t0); } =20 /* Optional: */ @@ -5357,7 +5108,6 @@ static void gen_mfsr(DisasContext *ctx) CHK_SV(ctx); t0 =3D tcg_const_tl(SR(ctx->opcode)); gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); - tcg_temp_free(t0); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5373,7 +5123,6 @@ static void gen_mfsrin(DisasContext *ctx) t0 =3D tcg_temp_new(); tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); - tcg_temp_free(t0); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5388,7 +5137,6 @@ static void gen_mtsr(DisasContext *ctx) CHK_SV(ctx); t0 =3D tcg_const_tl(SR(ctx->opcode)); gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); - tcg_temp_free(t0); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5404,7 +5152,6 @@ static void gen_mtsrin(DisasContext *ctx) t0 =3D tcg_temp_new(); tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); - tcg_temp_free(t0); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5422,7 +5169,6 @@ static void gen_mfsr_64b(DisasContext *ctx) CHK_SV(ctx); t0 =3D tcg_const_tl(SR(ctx->opcode)); gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); - tcg_temp_free(t0); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5438,7 +5184,6 @@ static void gen_mfsrin_64b(DisasContext *ctx) t0 =3D tcg_temp_new(); tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); - tcg_temp_free(t0); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5453,7 +5198,6 @@ static void gen_mtsr_64b(DisasContext *ctx) CHK_SV(ctx); t0 =3D tcg_const_tl(SR(ctx->opcode)); gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); - tcg_temp_free(t0); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5469,7 +5213,6 @@ static void gen_mtsrin_64b(DisasContext *ctx) t0 =3D tcg_temp_new(); tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); - tcg_temp_free(t0); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5523,7 +5266,6 @@ static void gen_eciwx(DisasContext *ctx) gen_addr_reg_index(ctx, t0); tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, DEF_MEMOP(MO_UL | MO_ALIGN)); - tcg_temp_free(t0); } =20 /* ecowx */ @@ -5536,7 +5278,6 @@ static void gen_ecowx(DisasContext *ctx) gen_addr_reg_index(ctx, t0); tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, DEF_MEMOP(MO_UL | MO_ALIGN)); - tcg_temp_free(t0); } =20 /* 602 - 603 - G2 TLB management */ @@ -5584,7 +5325,6 @@ static void gen_tlbiva(DisasContext *ctx) t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); - tcg_temp_free(t0); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5702,8 +5442,6 @@ static inline void gen_405_mulladd_insn(DisasContext = *ctx, int opc2, int opc3, } else { tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); } - tcg_temp_free(t0); - tcg_temp_free(t1); if (unlikely(Rc) !=3D 0) { /* Update Rc0 */ gen_set_Rc0(ctx, cpu_gpr[rt]); @@ -5814,7 +5552,6 @@ static void gen_mfdcr(DisasContext *ctx) CHK_SV(ctx); dcrn =3D tcg_const_tl(SPR(ctx->opcode)); gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); - tcg_temp_free(dcrn); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5829,7 +5566,6 @@ static void gen_mtdcr(DisasContext *ctx) CHK_SV(ctx); dcrn =3D tcg_const_tl(SPR(ctx->opcode)); gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); - tcg_temp_free(dcrn); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5882,9 +5618,7 @@ static void gen_dcread(DisasContext *ctx) gen_addr_reg_index(ctx, EA); val =3D tcg_temp_new(); gen_qemu_ld32u(ctx, val, EA); - tcg_temp_free(val); tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); - tcg_temp_free(EA); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -6002,7 +5736,6 @@ static void gen_tlbsx_40x(DisasContext *ctx) t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); - tcg_temp_free(t0); if (Rc(ctx->opcode)) { TCGLabel *l1 =3D gen_new_label(); tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); @@ -6055,7 +5788,6 @@ static void gen_tlbre_440(DisasContext *ctx) TCGv_i32 t0 =3D tcg_const_i32(rB(ctx->opcode)); gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, t0, cpu_gpr[rA(ctx->opcode)]); - tcg_temp_free_i32(t0); } break; default: @@ -6077,7 +5809,6 @@ static void gen_tlbsx_440(DisasContext *ctx) t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); - tcg_temp_free(t0); if (Rc(ctx->opcode)) { TCGLabel *l1 =3D gen_new_label(); tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); @@ -6103,7 +5834,6 @@ static void gen_tlbwe_440(DisasContext *ctx) TCGv_i32 t0 =3D tcg_const_i32(rB(ctx->opcode)); gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); - tcg_temp_free_i32(t0); } break; default: @@ -6144,7 +5874,6 @@ static void gen_tlbsx_booke206(DisasContext *ctx) =20 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); gen_helper_booke206_tlbsx(cpu_env, t0); - tcg_temp_free(t0); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -6170,7 +5899,6 @@ static void gen_tlbivax_booke206(DisasContext *ctx) t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); gen_helper_booke206_tlbivax(cpu_env, t0); - tcg_temp_free(t0); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -6199,8 +5927,6 @@ static void gen_tlbilx_booke206(DisasContext *ctx) gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); break; } - - tcg_temp_free(t0); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -6218,7 +5944,6 @@ static void gen_wrtee(DisasContext *ctx) tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); tcg_gen_or_tl(cpu_msr, cpu_msr, t0); gen_ppc_maybe_interrupt(ctx); - tcg_temp_free(t0); /* * Stop translation to have a chance to raise an exception if we * just set msr_ee to 1 @@ -6253,7 +5978,6 @@ static void gen_dlmzb(DisasContext *ctx) TCGv_i32 t0 =3D tcg_const_i32(Rc(ctx->opcode)); gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t= 0); - tcg_temp_free_i32(t0); } =20 /* mbar replaces eieio on 440 */ @@ -6290,7 +6014,6 @@ static void gen_maddld(DisasContext *ctx) =20 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]= ); tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]= ); - tcg_temp_free_i64(t1); } =20 /* maddhd maddhdu */ @@ -6311,9 +6034,6 @@ static void gen_maddhd_maddhdu(DisasContext *ctx) } tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, cpu_gpr[rC(ctx->opcode)], t1); - tcg_temp_free_i64(lo); - tcg_temp_free_i64(hi); - tcg_temp_free_i64(t1); } #endif /* defined(TARGET_PPC64) */ =20 @@ -6664,9 +6384,6 @@ static void gen_brh(DisasContext *ctx) tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); tcg_gen_shli_i64(t1, t1, 8); tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); } #endif =20 diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.= c.inc index c3cc919ee4..42f2cd04a1 100644 --- a/target/ppc/power8-pmu-regs.c.inc +++ b/target/ppc/power8-pmu-regs.c.inc @@ -58,8 +58,6 @@ static bool spr_groupA_write_allowed(DisasContext *ctx) /* * Helper function to avoid code repetition between MMCR0 and * MMCR2 problem state write functions. - * - * 'ret' must be tcg_temp_freed() by the caller. */ static TCGv masked_gprn_for_spr_write(int gprn, int sprn, uint64_t spr_mask) @@ -77,8 +75,6 @@ static TCGv masked_gprn_for_spr_write(int gprn, int sprn, /* Add the masked gprn bits into 'ret' */ tcg_gen_or_tl(ret, ret, t0); =20 - tcg_temp_free(t0); - return ret; } =20 @@ -100,8 +96,6 @@ void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, in= t sprn) gen_load_spr(t0, SPR_POWER_MMCR0); tcg_gen_andi_tl(t0, t0, MMCR0_UREG_MASK); tcg_gen_mov_tl(cpu_gpr[gprn], t0); - - tcg_temp_free(t0); } =20 static void write_MMCR0_common(DisasContext *ctx, TCGv val) @@ -137,8 +131,6 @@ void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, = int gprn) masked_gprn =3D masked_gprn_for_spr_write(gprn, SPR_POWER_MMCR0, MMCR0_UREG_MASK); write_MMCR0_common(ctx, masked_gprn); - - tcg_temp_free(masked_gprn); } =20 void spr_read_MMCR2_ureg(DisasContext *ctx, int gprn, int sprn) @@ -164,8 +156,6 @@ void spr_read_MMCR2_ureg(DisasContext *ctx, int gprn, i= nt sprn) gen_load_spr(t0, SPR_POWER_MMCR2); tcg_gen_andi_tl(t0, t0, MMCR2_UREG_MASK); tcg_gen_mov_tl(cpu_gpr[gprn], t0); - - tcg_temp_free(t0); } =20 void spr_write_MMCR2_ureg(DisasContext *ctx, int sprn, int gprn) @@ -183,8 +173,6 @@ void spr_write_MMCR2_ureg(DisasContext *ctx, int sprn, = int gprn) masked_gprn =3D masked_gprn_for_spr_write(gprn, SPR_POWER_MMCR2, MMCR2_UREG_MASK); gen_store_spr(SPR_POWER_MMCR2, masked_gprn); - - tcg_temp_free(masked_gprn); } =20 void spr_read_PMC(DisasContext *ctx, int gprn, int sprn) @@ -193,8 +181,6 @@ void spr_read_PMC(DisasContext *ctx, int gprn, int sprn) =20 gen_icount_io_start(ctx); gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn); - - tcg_temp_free_i32(t_sprn); } =20 void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn) @@ -228,8 +214,6 @@ void spr_write_PMC(DisasContext *ctx, int sprn, int gpr= n) =20 gen_icount_io_start(ctx); gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]); - - tcg_temp_free_i32(t_sprn); } =20 void spr_write_PMC14_ureg(DisasContext *ctx, int sprn, int gprn) diff --git a/target/ppc/translate/dfp-impl.c.inc b/target/ppc/translate/dfp= -impl.c.inc index f9f1d58d44..62911e04c7 100644 --- a/target/ppc/translate/dfp-impl.c.inc +++ b/target/ppc/translate/dfp-impl.c.inc @@ -20,9 +20,6 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a= ) \ if (unlikely(a->rc)) { \ gen_set_cr1_from_fpscr(ctx); \ } \ - tcg_temp_free_ptr(rt); \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_ptr(rb); \ return true; \ } =20 @@ -36,8 +33,6 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a= ) \ rb =3D gen_fprp_ptr(a->rb); \ gen_helper_##NAME(cpu_crf[a->bf], \ cpu_env, ra, rb); \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_ptr(rb); \ return true; \ } =20 @@ -50,7 +45,6 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a= ) \ rb =3D gen_fprp_ptr(a->rb); \ gen_helper_##NAME(cpu_crf[a->bf], \ cpu_env, tcg_constant_i32(a->uim), rb);\ - tcg_temp_free_ptr(rb); \ return true; \ } =20 @@ -63,7 +57,6 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a= ) \ ra =3D gen_fprp_ptr(a->fra); \ gen_helper_##NAME(cpu_crf[a->bf], \ cpu_env, ra, tcg_constant_i32(a->dm)); \ - tcg_temp_free_ptr(ra); \ return true; \ } =20 @@ -81,8 +74,6 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a= ) \ if (unlikely(a->rc)) { \ gen_set_cr1_from_fpscr(ctx); \ } \ - tcg_temp_free_ptr(rt); \ - tcg_temp_free_ptr(rb); \ return true; \ } =20 @@ -100,9 +91,6 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *= a) \ if (unlikely(a->rc)) { \ gen_set_cr1_from_fpscr(ctx); \ } \ - tcg_temp_free_ptr(rt); \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_ptr(rb); \ return true; \ } =20 @@ -118,8 +106,6 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME = *a) \ if (unlikely(a->rc)) { \ gen_set_cr1_from_fpscr(ctx); \ } \ - tcg_temp_free_ptr(rt); \ - tcg_temp_free_ptr(rb); \ return true; \ } =20 @@ -136,8 +122,6 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME = *a) \ if (unlikely(a->rc)) { \ gen_set_cr1_from_fpscr(ctx); \ } \ - tcg_temp_free_ptr(rt); \ - tcg_temp_free_ptr(rx); \ return true; \ } =20 @@ -205,8 +189,6 @@ static bool trans_DCFFIXQQ(DisasContext *ctx, arg_DCFFI= XQQ *a) rt =3D gen_fprp_ptr(a->frtp); rb =3D gen_avr_ptr(a->vrb); gen_helper_DCFFIXQQ(cpu_env, rt, rb); - tcg_temp_free_ptr(rt); - tcg_temp_free_ptr(rb); =20 return true; } @@ -222,8 +204,6 @@ static bool trans_DCTFIXQQ(DisasContext *ctx, arg_DCTFI= XQQ *a) rt =3D gen_avr_ptr(a->vrt); rb =3D gen_fprp_ptr(a->frbp); gen_helper_DCTFIXQQ(cpu_env, rt, rb); - tcg_temp_free_ptr(rt); - tcg_temp_free_ptr(rb); =20 return true; } diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 1ba56cbed5..20ea484c3d 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -42,8 +42,6 @@ static bool do_ldst(DisasContext *ctx, int rt, int ra, TC= Gv displ, bool update, if (update) { tcg_gen_mov_tl(cpu_gpr[ra], ea); } - tcg_temp_free(ea); - return true; } =20 @@ -149,7 +147,6 @@ static bool do_ldst_quad(DisasContext *ctx, arg_D *a, b= ool store, bool prefixed) tcg_gen_qemu_ld_i64(high_addr_gpr, ea, ctx->mem_idx, mop); } } - tcg_temp_free(ea); #else qemu_build_not_reached(); #endif @@ -389,8 +386,6 @@ static bool do_set_bool_cond(DisasContext *ctx, arg_X_b= i *a, bool neg, bool rev) if (neg) { tcg_gen_neg_tl(cpu_gpr[a->rt], cpu_gpr[a->rt]); } - tcg_temp_free(temp); - return true; } =20 @@ -437,9 +432,6 @@ static void do_cntzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_= i64 mask, int64_t trail) } =20 tcg_gen_ctpop_i64(dst, t0); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a) @@ -519,11 +511,6 @@ static bool trans_ADDG6S(DisasContext *ctx, arg_X *a) =20 tcg_gen_xori_tl(carry, carry, (target_long)carry_bits); tcg_gen_muli_tl(cpu_gpr[a->rt], carry, 6); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(carry); - return true; } =20 @@ -564,9 +551,6 @@ static bool do_hash(DisasContext *ctx, arg_X *a, bool p= riv, =20 ea =3D do_ea_calc(ctx, a->ra, tcg_constant_tl(a->rt)); helper(cpu_env, ea, cpu_gpr[a->ra], cpu_gpr[a->rb]); - - tcg_temp_free(ea); - return true; } =20 diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-i= mpl.c.inc index 8d5cf0f982..d5d88e7d49 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -21,7 +21,6 @@ static void gen_set_cr1_from_fpscr(DisasContext *ctx) TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(tmp, cpu_fpscr); tcg_gen_shri_i32(cpu_crf[1], tmp, 28); - tcg_temp_free_i32(tmp); } #else static void gen_set_cr1_from_fpscr(DisasContext *ctx) @@ -58,10 +57,6 @@ static void gen_f##name(DisasContext *ctx) = \ if (unlikely(Rc(ctx->opcode) !=3D 0)) { = \ gen_set_cr1_from_fpscr(ctx); = \ } = \ - tcg_temp_free_i64(t0); = \ - tcg_temp_free_i64(t1); = \ - tcg_temp_free_i64(t2); = \ - tcg_temp_free_i64(t3); = \ } =20 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) = \ @@ -92,9 +87,6 @@ static void gen_f##name(DisasContext *ctx) = \ if (unlikely(Rc(ctx->opcode) !=3D 0)) { = \ gen_set_cr1_from_fpscr(ctx); = \ } = \ - tcg_temp_free_i64(t0); = \ - tcg_temp_free_i64(t1); = \ - tcg_temp_free_i64(t2); = \ } #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) = \ _GEN_FLOAT_AB(name, 0x3F, op2, inval, set_fprf, type); = \ @@ -124,9 +116,6 @@ static void gen_f##name(DisasContext *ctx) = \ if (unlikely(Rc(ctx->opcode) !=3D 0)) { = \ gen_set_cr1_from_fpscr(ctx); = \ } = \ - tcg_temp_free_i64(t0); = \ - tcg_temp_free_i64(t1); = \ - tcg_temp_free_i64(t2); = \ } #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) = \ _GEN_FLOAT_AC(name, 0x3F, op2, inval, set_fprf, type); = \ @@ -154,8 +143,6 @@ static void gen_f##name(DisasContext *ctx) = \ if (unlikely(Rc(ctx->opcode) !=3D 0)) { = \ gen_set_cr1_from_fpscr(ctx); = \ } = \ - tcg_temp_free_i64(t0); = \ - tcg_temp_free_i64(t1); = \ } =20 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) = \ @@ -179,8 +166,6 @@ static void gen_f##name(DisasContext *ctx) = \ if (unlikely(Rc(ctx->opcode) !=3D 0)) { = \ gen_set_cr1_from_fpscr(ctx); = \ } = \ - tcg_temp_free_i64(t0); = \ - tcg_temp_free_i64(t1); = \ } =20 /* fadd - fadds */ @@ -218,8 +203,6 @@ static void gen_frsqrtes(DisasContext *ctx) if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_cr1_from_fpscr(ctx); } - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 static bool trans_FSEL(DisasContext *ctx, arg_A *a) @@ -242,11 +225,6 @@ static bool trans_FSEL(DisasContext *ctx, arg_A *a) if (a->rc) { gen_set_cr1_from_fpscr(ctx); } - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - return true; } =20 @@ -273,10 +251,6 @@ static bool do_helper_fsqrt(DisasContext *ctx, arg_A_t= b *a, if (unlikely(a->rc !=3D 0)) { gen_set_cr1_from_fpscr(ctx); } - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - return true; } =20 @@ -343,8 +317,6 @@ static void gen_ftdiv(DisasContext *ctx) get_fpr(t0, rA(ctx->opcode)); get_fpr(t1, rB(ctx->opcode)); gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], t0, t1); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 static void gen_ftsqrt(DisasContext *ctx) @@ -357,7 +329,6 @@ static void gen_ftsqrt(DisasContext *ctx) t0 =3D tcg_temp_new_i64(); get_fpr(t0, rB(ctx->opcode)); gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], t0); - tcg_temp_free_i64(t0); } =20 =20 @@ -381,10 +352,7 @@ static void gen_fcmpo(DisasContext *ctx) get_fpr(t0, rA(ctx->opcode)); get_fpr(t1, rB(ctx->opcode)); gen_helper_fcmpo(cpu_env, t0, t1, crf); - tcg_temp_free_i32(crf); gen_helper_float_check_status(cpu_env); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 /* fcmpu */ @@ -404,10 +372,7 @@ static void gen_fcmpu(DisasContext *ctx) get_fpr(t0, rA(ctx->opcode)); get_fpr(t1, rB(ctx->opcode)); gen_helper_fcmpu(cpu_env, t0, t1, crf); - tcg_temp_free_i32(crf); gen_helper_float_check_status(cpu_env); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 /*** Floating-point move = ***/ @@ -429,8 +394,6 @@ static void gen_fabs(DisasContext *ctx) if (unlikely(Rc(ctx->opcode))) { gen_set_cr1_from_fpscr(ctx); } - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 /* fmr - fmr. */ @@ -448,7 +411,6 @@ static void gen_fmr(DisasContext *ctx) if (unlikely(Rc(ctx->opcode))) { gen_set_cr1_from_fpscr(ctx); } - tcg_temp_free_i64(t0); } =20 /* fnabs */ @@ -469,8 +431,6 @@ static void gen_fnabs(DisasContext *ctx) if (unlikely(Rc(ctx->opcode))) { gen_set_cr1_from_fpscr(ctx); } - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 /* fneg */ @@ -491,8 +451,6 @@ static void gen_fneg(DisasContext *ctx) if (unlikely(Rc(ctx->opcode))) { gen_set_cr1_from_fpscr(ctx); } - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 /* fcpsgn: PowerPC 2.05 specification */ @@ -516,9 +474,6 @@ static void gen_fcpsgn(DisasContext *ctx) if (unlikely(Rc(ctx->opcode))) { gen_set_cr1_from_fpscr(ctx); } - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); } =20 static void gen_fmrgew(DisasContext *ctx) @@ -538,9 +493,6 @@ static void gen_fmrgew(DisasContext *ctx) get_fpr(t0, rA(ctx->opcode)); tcg_gen_deposit_i64(t1, t0, b0, 0, 32); set_fpr(rD(ctx->opcode), t1); - tcg_temp_free_i64(b0); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 static void gen_fmrgow(DisasContext *ctx) @@ -559,9 +511,6 @@ static void gen_fmrgow(DisasContext *ctx) get_fpr(t1, rA(ctx->opcode)); tcg_gen_deposit_i64(t2, t0, t1, 32, 32); set_fpr(rD(ctx->opcode), t2); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); } =20 /*** Floating-Point status & ctrl register = ***/ @@ -587,7 +536,6 @@ static void gen_mcrfs(DisasContext *ctx) tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp); tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)= ], 0xf); - tcg_temp_free(tmp); tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr); /* Only the exception bits (including FX) should be cleared if read */ tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, @@ -595,8 +543,6 @@ static void gen_mcrfs(DisasContext *ctx) /* FEX and VX need to be updated, so don't set fpscr directly */ tmask =3D tcg_const_i32(1 << nibble); gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask); - tcg_temp_free_i32(tmask); - tcg_temp_free_i64(tnew_fpscr); } =20 static TCGv_i64 place_from_fpscr(int rt, uint64_t mask) @@ -608,8 +554,6 @@ static TCGv_i64 place_from_fpscr(int rt, uint64_t mask) tcg_gen_andi_i64(fpscr_masked, fpscr, mask); set_fpr(rt, fpscr_masked); =20 - tcg_temp_free_i64(fpscr_masked); - return fpscr; } =20 @@ -622,24 +566,17 @@ static void store_fpscr_masked(TCGv_i64 fpscr, uint64= _t clear_mask, tcg_gen_andi_i64(fpscr_masked, fpscr, ~clear_mask); tcg_gen_or_i64(fpscr_masked, fpscr_masked, set_mask); gen_helper_store_fpscr(cpu_env, fpscr_masked, st_mask); - - tcg_temp_free_i64(fpscr_masked); } =20 static bool trans_MFFS(DisasContext *ctx, arg_X_t_rc *a) { - TCGv_i64 fpscr; - REQUIRE_FPU(ctx); =20 gen_reset_fpstatus(); - fpscr =3D place_from_fpscr(a->rt, UINT64_MAX); + place_from_fpscr(a->rt, UINT64_MAX); if (a->rc) { gen_set_cr1_from_fpscr(ctx); } - - tcg_temp_free_i64(fpscr); - return true; } =20 @@ -653,9 +590,6 @@ static bool trans_MFFSCE(DisasContext *ctx, arg_X_t *a) gen_reset_fpstatus(); fpscr =3D place_from_fpscr(a->rt, UINT64_MAX); store_fpscr_masked(fpscr, FP_ENABLES, tcg_constant_i64(0), 0x0003); - - tcg_temp_free_i64(fpscr); - return true; } =20 @@ -673,10 +607,6 @@ static bool trans_MFFSCRN(DisasContext *ctx, arg_X_tb = *a) gen_reset_fpstatus(); fpscr =3D place_from_fpscr(a->rt, FP_DRN | FP_ENABLES | FP_NI | FP_RN); store_fpscr_masked(fpscr, FP_RN, t1, 0x0001); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(fpscr); - return true; } =20 @@ -694,10 +624,6 @@ static bool trans_MFFSCDRN(DisasContext *ctx, arg_X_tb= *a) gen_reset_fpstatus(); fpscr =3D place_from_fpscr(a->rt, FP_DRN | FP_ENABLES | FP_NI | FP_RN); store_fpscr_masked(fpscr, FP_DRN, t1, 0x0100); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(fpscr); - return true; } =20 @@ -714,10 +640,6 @@ static bool trans_MFFSCRNI(DisasContext *ctx, arg_X_im= m2 *a) gen_reset_fpstatus(); fpscr =3D place_from_fpscr(a->rt, FP_DRN | FP_ENABLES | FP_NI | FP_RN); store_fpscr_masked(fpscr, FP_RN, t1, 0x0001); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(fpscr); - return true; } =20 @@ -734,26 +656,16 @@ static bool trans_MFFSCDRNI(DisasContext *ctx, arg_X_= imm3 *a) gen_reset_fpstatus(); fpscr =3D place_from_fpscr(a->rt, FP_DRN | FP_ENABLES | FP_NI | FP_RN); store_fpscr_masked(fpscr, FP_DRN, t1, 0x0100); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(fpscr); - return true; } =20 static bool trans_MFFSL(DisasContext *ctx, arg_X_t *a) { - TCGv_i64 fpscr; - REQUIRE_INSNS_FLAGS2(ctx, ISA300); REQUIRE_FPU(ctx); =20 gen_reset_fpstatus(); - fpscr =3D place_from_fpscr(a->rt, - FP_DRN | FP_STATUS | FP_ENABLES | FP_NI | FP_RN); - - tcg_temp_free_i64(fpscr); - + place_from_fpscr(a->rt, FP_DRN | FP_STATUS | FP_ENABLES | FP_NI | FP_R= N); return true; } =20 @@ -772,7 +684,6 @@ static void gen_mtfsb0(DisasContext *ctx) TCGv_i32 t0; t0 =3D tcg_const_i32(crb); gen_helper_fpscr_clrbit(cpu_env, t0); - tcg_temp_free_i32(t0); } if (unlikely(Rc(ctx->opcode) !=3D 0)) { tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); @@ -795,7 +706,6 @@ static void gen_mtfsb1(DisasContext *ctx) TCGv_i32 t0; t0 =3D tcg_const_i32(crb); gen_helper_fpscr_setbit(cpu_env, t0); - tcg_temp_free_i32(t0); } if (unlikely(Rc(ctx->opcode) !=3D 0)) { tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); @@ -831,14 +741,12 @@ static void gen_mtfsf(DisasContext *ctx) t1 =3D tcg_temp_new_i64(); get_fpr(t1, rB(ctx->opcode)); gen_helper_store_fpscr(cpu_env, t1, t0); - tcg_temp_free_i32(t0); if (unlikely(Rc(ctx->opcode) !=3D 0)) { tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); } /* We can raise a deferred exception */ gen_helper_fpscr_check_status(cpu_env); - tcg_temp_free_i64(t1); } =20 /* mtfsfi */ @@ -862,8 +770,6 @@ static void gen_mtfsfi(DisasContext *ctx) t0 =3D tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh)); t1 =3D tcg_const_i32(1 << sh); gen_helper_store_fpscr(cpu_env, t0, t1); - tcg_temp_free_i64(t0); - tcg_temp_free_i32(t1); if (unlikely(Rc(ctx->opcode) !=3D 0)) { tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); @@ -877,7 +783,6 @@ static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64= dest, TCGv addr) TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_qemu_ld_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL)); gen_helper_todouble(dest, tmp); - tcg_temp_free_i32(tmp); } =20 /* lfdepx (external PID lfdx) */ @@ -896,8 +801,6 @@ static void gen_lfdepx(DisasContext *ctx) gen_addr_reg_index(ctx, EA); tcg_gen_qemu_ld_i64(t0, EA, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UQ)); set_fpr(rD(ctx->opcode), t0); - tcg_temp_free(EA); - tcg_temp_free_i64(t0); } =20 /* lfdp */ @@ -930,8 +833,6 @@ static void gen_lfdp(DisasContext *ctx) gen_qemu_ld64_i64(ctx, t0, EA); set_fpr(rD(ctx->opcode) + 1, t0); } - tcg_temp_free(EA); - tcg_temp_free_i64(t0); } =20 /* lfdpx */ @@ -964,8 +865,6 @@ static void gen_lfdpx(DisasContext *ctx) gen_qemu_ld64_i64(ctx, t0, EA); set_fpr(rD(ctx->opcode) + 1, t0); } - tcg_temp_free(EA); - tcg_temp_free_i64(t0); } =20 /* lfiwax */ @@ -986,9 +885,6 @@ static void gen_lfiwax(DisasContext *ctx) gen_qemu_ld32s(ctx, t0, EA); tcg_gen_ext_tl_i64(t1, t0); set_fpr(rD(ctx->opcode), t1); - tcg_temp_free(EA); - tcg_temp_free(t0); - tcg_temp_free_i64(t1); } =20 /* lfiwzx */ @@ -1006,8 +902,6 @@ static void gen_lfiwzx(DisasContext *ctx) gen_addr_reg_index(ctx, EA); gen_qemu_ld32u_i64(ctx, t0, EA); set_fpr(rD(ctx->opcode), t0); - tcg_temp_free(EA); - tcg_temp_free_i64(t0); } =20 #define GEN_STXF(name, stop, opc2, opc3, type) = \ @@ -1025,8 +919,6 @@ static void glue(gen_, name##x)(DisasContext *ctx) = \ gen_addr_reg_index(ctx, EA); = \ get_fpr(t0, rS(ctx->opcode)); = \ gen_qemu_##stop(ctx, t0, EA); = \ - tcg_temp_free(EA); = \ - tcg_temp_free_i64(t0); = \ } =20 static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr) @@ -1034,7 +926,6 @@ static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i6= 4 src, TCGv addr) TCGv_i32 tmp =3D tcg_temp_new_i32(); gen_helper_tosingle(tmp, src); tcg_gen_qemu_st_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL)); - tcg_temp_free_i32(tmp); } =20 /* stfdepx (external PID lfdx) */ @@ -1053,8 +944,6 @@ static void gen_stfdepx(DisasContext *ctx) gen_addr_reg_index(ctx, EA); get_fpr(t0, rD(ctx->opcode)); tcg_gen_qemu_st_i64(t0, EA, PPC_TLB_EPID_STORE, DEF_MEMOP(MO_UQ)); - tcg_temp_free(EA); - tcg_temp_free_i64(t0); } =20 /* stfdp */ @@ -1087,8 +976,6 @@ static void gen_stfdp(DisasContext *ctx) get_fpr(t0, rD(ctx->opcode) + 1); gen_qemu_st64_i64(ctx, t0, EA); } - tcg_temp_free(EA); - tcg_temp_free_i64(t0); } =20 /* stfdpx */ @@ -1121,8 +1008,6 @@ static void gen_stfdpx(DisasContext *ctx) get_fpr(t0, rD(ctx->opcode) + 1); gen_qemu_st64_i64(ctx, t0, EA); } - tcg_temp_free(EA); - tcg_temp_free_i64(t0); } =20 /* Optional: */ @@ -1131,7 +1016,6 @@ static inline void gen_qemu_st32fiw(DisasContext *ctx= , TCGv_i64 arg1, TCGv arg2) TCGv t0 =3D tcg_temp_new(); tcg_gen_trunc_i64_tl(t0, arg1), gen_qemu_st32(ctx, t0, arg2); - tcg_temp_free(t0); } /* stfiwx */ GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); @@ -1169,8 +1053,6 @@ static bool do_lsfpsd(DisasContext *ctx, int rt, int = ra, TCGv displ, if (update) { tcg_gen_mov_tl(cpu_gpr[ra], ea); } - tcg_temp_free_i64(t0); - tcg_temp_free(ea); return true; } =20 diff --git a/target/ppc/translate/spe-impl.c.inc b/target/ppc/translate/spe= -impl.c.inc index bd8963db2b..f4a858487d 100644 --- a/target/ppc/translate/spe-impl.c.inc +++ b/target/ppc/translate/spe-impl.c.inc @@ -23,7 +23,6 @@ static inline void gen_evmra(DisasContext *ctx) =20 /* spe_acc :=3D tmp */ tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); - tcg_temp_free_i64(tmp); =20 /* rD :=3D rA */ tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); @@ -96,8 +95,6 @@ static inline void gen_##name(DisasContext *ctx) = \ tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); = \ tcg_opi(t0, t0, rB(ctx->opcode)); = \ tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); = \ - = \ - tcg_temp_free_i32(t0); = \ } GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); @@ -122,8 +119,6 @@ static inline void gen_##name(DisasContext *ctx) = \ tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); = \ tcg_op(t0, t0); = \ tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); = \ - = \ - tcg_temp_free_i32(t0); = \ } =20 GEN_SPEOP_ARITH1(evabs, tcg_gen_abs_i32); @@ -159,9 +154,6 @@ static inline void gen_##name(DisasContext *ctx) = \ tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); = \ tcg_op(t0, t0, t1); = \ tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); = \ - = \ - tcg_temp_free_i32(t0); = \ - tcg_temp_free_i32(t1); = \ } =20 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg= 2) @@ -178,7 +170,6 @@ static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32= arg1, TCGv_i32 arg2) gen_set_label(l1); tcg_gen_movi_i32(ret, 0); gen_set_label(l2); - tcg_temp_free_i32(t0); } GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg= 2) @@ -195,7 +186,6 @@ static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32= arg1, TCGv_i32 arg2) gen_set_label(l1); tcg_gen_movi_i32(ret, 0); gen_set_label(l2); - tcg_temp_free_i32(t0); } GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) @@ -212,7 +202,6 @@ static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 = arg1, TCGv_i32 arg2) gen_set_label(l1); tcg_gen_movi_i32(ret, 0); gen_set_label(l2); - tcg_temp_free_i32(t0); } GEN_SPEOP_ARITH2(evslw, gen_op_evslw); static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) @@ -220,7 +209,6 @@ static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 = arg1, TCGv_i32 arg2) TCGv_i32 t0 =3D tcg_temp_new_i32(); tcg_gen_andi_i32(t0, arg2, 0x1F); tcg_gen_rotl_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); } GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); static inline void gen_evmergehi(DisasContext *ctx) @@ -257,8 +245,6 @@ static inline void gen_##name(DisasContext *ctx) = \ tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); = \ tcg_op(t0, t0, rA(ctx->opcode)); = \ tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); = \ - = \ - tcg_temp_free_i32(t0); = \ } GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); @@ -341,7 +327,6 @@ static inline void gen_evmergelohi(DisasContext *ctx) tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]); tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]= ); tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp); - tcg_temp_free(tmp); } else { tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]= ); tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]= ); @@ -394,7 +379,6 @@ static inline void gen_evsel(DisasContext *ctx) gen_set_label(l3); tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); gen_set_label(l4); - tcg_temp_free_i32(t0); } =20 static void gen_evsel0(DisasContext *ctx) @@ -456,9 +440,6 @@ static inline void gen_evmwumi(DisasContext *ctx) tcg_gen_mul_i64(t0, t0, t1); /* t0 :=3D rA * rB */ =20 gen_store_gpr64(rD(ctx->opcode), t0); /* rD :=3D t0 */ - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 static inline void gen_evmwumia(DisasContext *ctx) @@ -477,7 +458,6 @@ static inline void gen_evmwumia(DisasContext *ctx) /* acc :=3D rD */ gen_load_gpr64(tmp, rD(ctx->opcode)); tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); - tcg_temp_free_i64(tmp); } =20 static inline void gen_evmwumiaa(DisasContext *ctx) @@ -509,9 +489,6 @@ static inline void gen_evmwumiaa(DisasContext *ctx) =20 /* rD :=3D acc */ gen_store_gpr64(rD(ctx->opcode), acc); - - tcg_temp_free_i64(acc); - tcg_temp_free_i64(tmp); } =20 static inline void gen_evmwsmi(DisasContext *ctx) @@ -535,9 +512,6 @@ static inline void gen_evmwsmi(DisasContext *ctx) tcg_gen_mul_i64(t0, t0, t1); /* t0 :=3D rA * rB */ =20 gen_store_gpr64(rD(ctx->opcode), t0); /* rD :=3D t0 */ - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 static inline void gen_evmwsmia(DisasContext *ctx) @@ -556,8 +530,6 @@ static inline void gen_evmwsmia(DisasContext *ctx) /* acc :=3D rD */ gen_load_gpr64(tmp, rD(ctx->opcode)); tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); - - tcg_temp_free_i64(tmp); } =20 static inline void gen_evmwsmiaa(DisasContext *ctx) @@ -589,9 +561,6 @@ static inline void gen_evmwsmiaa(DisasContext *ctx) =20 /* rD :=3D acc */ gen_store_gpr64(rD(ctx->opcode), acc); - - tcg_temp_free_i64(acc); - tcg_temp_free_i64(tmp); } =20 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_= SPE); //// @@ -644,7 +613,6 @@ static inline void gen_op_evldd(DisasContext *ctx, TCGv= addr) TCGv_i64 t0 =3D tcg_temp_new_i64(); gen_qemu_ld64_i64(ctx, t0, addr); gen_store_gpr64(rD(ctx->opcode), t0); - tcg_temp_free_i64(t0); } =20 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr) @@ -668,7 +636,6 @@ static inline void gen_op_evldh(DisasContext *ctx, TCGv= addr) gen_addr_add(ctx, addr, addr, 2); gen_qemu_ld16u(ctx, t0, addr); tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); - tcg_temp_free(t0); } =20 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) @@ -678,7 +645,6 @@ static inline void gen_op_evlhhesplat(DisasContext *ctx= , TCGv addr) tcg_gen_shli_tl(t0, t0, 16); tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); - tcg_temp_free(t0); } =20 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) @@ -687,7 +653,6 @@ static inline void gen_op_evlhhousplat(DisasContext *ct= x, TCGv addr) gen_qemu_ld16u(ctx, t0, addr); tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); - tcg_temp_free(t0); } =20 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) @@ -696,7 +661,6 @@ static inline void gen_op_evlhhossplat(DisasContext *ct= x, TCGv addr) gen_qemu_ld16s(ctx, t0, addr); tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); - tcg_temp_free(t0); } =20 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) @@ -707,7 +671,6 @@ static inline void gen_op_evlwhe(DisasContext *ctx, TCG= v addr) gen_addr_add(ctx, addr, addr, 2); gen_qemu_ld16u(ctx, t0, addr); tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); - tcg_temp_free(t0); } =20 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) @@ -730,7 +693,6 @@ static inline void gen_op_evlwwsplat(DisasContext *ctx,= TCGv addr) gen_qemu_ld32u(ctx, t0, addr); tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); - tcg_temp_free(t0); } =20 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) @@ -743,7 +705,6 @@ static inline void gen_op_evlwhsplat(DisasContext *ctx,= TCGv addr) gen_qemu_ld16u(ctx, t0, addr); tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); - tcg_temp_free(t0); } =20 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) @@ -751,7 +712,6 @@ static inline void gen_op_evstdd(DisasContext *ctx, TCG= v addr) TCGv_i64 t0 =3D tcg_temp_new_i64(); gen_load_gpr64(t0, rS(ctx->opcode)); gen_qemu_st64_i64(ctx, t0, addr); - tcg_temp_free_i64(t0); } =20 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) @@ -771,7 +731,6 @@ static inline void gen_op_evstdh(DisasContext *ctx, TCG= v addr) gen_addr_add(ctx, addr, addr, 2); tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); gen_qemu_st16(ctx, t0, addr); - tcg_temp_free(t0); gen_addr_add(ctx, addr, addr, 2); gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); } @@ -784,7 +743,6 @@ static inline void gen_op_evstwhe(DisasContext *ctx, TC= Gv addr) gen_addr_add(ctx, addr, addr, 2); tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); gen_qemu_st16(ctx, t0, addr); - tcg_temp_free(t0); } =20 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) @@ -820,7 +778,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ gen_addr_reg_index(ctx, t0); = \ } = \ gen_op_##name(ctx, t0); = \ - tcg_temp_free(t0); = \ } =20 GEN_SPEOP_LDST(evldd, 0x00, 3); @@ -923,7 +880,6 @@ static inline void gen_##name(DisasContext *ctx) = \ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); = \ gen_helper_##name(t0, cpu_env, t0); = \ tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); = \ - tcg_temp_free_i32(t0); = \ } #define GEN_SPEFPUOP_CONV_32_64(name) = \ static inline void gen_##name(DisasContext *ctx) = \ @@ -939,8 +895,6 @@ static inline void gen_##name(DisasContext *ctx) = \ gen_load_gpr64(t0, rB(ctx->opcode)); = \ gen_helper_##name(t1, cpu_env, t0); = \ tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); = \ - tcg_temp_free_i64(t0); = \ - tcg_temp_free_i32(t1); = \ } #define GEN_SPEFPUOP_CONV_64_32(name) = \ static inline void gen_##name(DisasContext *ctx) = \ @@ -956,8 +910,6 @@ static inline void gen_##name(DisasContext *ctx) = \ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); = \ gen_helper_##name(t0, cpu_env, t1); = \ gen_store_gpr64(rD(ctx->opcode), t0); = \ - tcg_temp_free_i64(t0); = \ - tcg_temp_free_i32(t1); = \ } #define GEN_SPEFPUOP_CONV_64_64(name) = \ static inline void gen_##name(DisasContext *ctx) = \ @@ -971,7 +923,6 @@ static inline void gen_##name(DisasContext *ctx) = \ gen_load_gpr64(t0, rB(ctx->opcode)); = \ gen_helper_##name(t0, cpu_env, t0); = \ gen_store_gpr64(rD(ctx->opcode), t0); = \ - tcg_temp_free_i64(t0); = \ } #define GEN_SPEFPUOP_ARITH2_32_32(name) = \ static inline void gen_##name(DisasContext *ctx) = \ @@ -982,9 +933,6 @@ static inline void gen_##name(DisasContext *ctx) = \ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); = \ gen_helper_##name(t0, cpu_env, t0, t1); = \ tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); = \ - = \ - tcg_temp_free_i32(t0); = \ - tcg_temp_free_i32(t1); = \ } #define GEN_SPEFPUOP_ARITH2_64_64(name) = \ static inline void gen_##name(DisasContext *ctx) = \ @@ -1000,8 +948,6 @@ static inline void gen_##name(DisasContext *ctx) = \ gen_load_gpr64(t1, rB(ctx->opcode)); = \ gen_helper_##name(t0, cpu_env, t0, t1); = \ gen_store_gpr64(rD(ctx->opcode), t0); = \ - tcg_temp_free_i64(t0); = \ - tcg_temp_free_i64(t1); = \ } #define GEN_SPEFPUOP_COMP_32(name) = \ static inline void gen_##name(DisasContext *ctx) = \ @@ -1012,9 +958,6 @@ static inline void gen_##name(DisasContext *ctx) = \ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); = \ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); = \ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); = \ - = \ - tcg_temp_free_i32(t0); = \ - tcg_temp_free_i32(t1); = \ } #define GEN_SPEFPUOP_COMP_64(name) = \ static inline void gen_##name(DisasContext *ctx) = \ @@ -1029,8 +972,6 @@ static inline void gen_##name(DisasContext *ctx) = \ gen_load_gpr64(t0, rA(ctx->opcode)); = \ gen_load_gpr64(t1, rB(ctx->opcode)); = \ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); = \ - tcg_temp_free_i64(t0); = \ - tcg_temp_free_i64(t1); = \ } =20 /* Single precision floating-point vectors operations */ diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/tran= slate/storage-ctrl-impl.c.inc index 6ea1d22ef9..faa7b04bbc 100644 --- a/target/ppc/translate/storage-ctrl-impl.c.inc +++ b/target/ppc/translate/storage-ctrl-impl.c.inc @@ -212,7 +212,6 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a,= bool local) TCGv t0 =3D tcg_temp_new(); tcg_gen_ext32u_tl(t0, cpu_gpr[rb]); gen_helper_tlbie(cpu_env, t0); - tcg_temp_free(t0); =20 #if defined(TARGET_PPC64) /* @@ -240,7 +239,6 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a,= bool local) tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); - tcg_temp_free_i32(t1); =20 return true; #endif diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx= -impl.c.inc index 2dd17ab106..05ba9c9492 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -45,8 +45,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ gen_qemu_ld64_i64(ctx, avr, EA); = \ set_avr64(rD(ctx->opcode), avr, false); = \ } = \ - tcg_temp_free(EA); = \ - tcg_temp_free_i64(avr); = \ } =20 #define GEN_VR_STX(name, opc2, opc3) = \ @@ -80,8 +78,6 @@ static void gen_st##name(DisasContext *ctx) = \ get_avr64(avr, rD(ctx->opcode), false); = \ gen_qemu_st64_i64(ctx, avr, EA); = \ } = \ - tcg_temp_free(EA); = \ - tcg_temp_free_i64(avr); = \ } =20 #define GEN_VR_LVE(name, opc2, opc3, size) \ @@ -101,8 +97,6 @@ static void gen_lve##name(DisasContext *ctx) = \ } \ rs =3D gen_avr_ptr(rS(ctx->opcode)); \ gen_helper_lve##name(cpu_env, rs, EA); \ - tcg_temp_free(EA); \ - tcg_temp_free_ptr(rs); \ } =20 #define GEN_VR_STVE(name, opc2, opc3, size) \ @@ -122,8 +116,6 @@ static void gen_stve##name(DisasContext *ctx) = \ } \ rs =3D gen_avr_ptr(rS(ctx->opcode)); \ gen_helper_stve##name(cpu_env, rs, EA); \ - tcg_temp_free(EA); \ - tcg_temp_free_ptr(rs); \ } =20 GEN_VR_LDX(lvx, 0x07, 0x03); @@ -157,8 +149,6 @@ static void gen_mfvscr(DisasContext *ctx) gen_helper_mfvscr(t, cpu_env); tcg_gen_extu_i32_i64(avr, t); set_avr64(rD(ctx->opcode), avr, false); - tcg_temp_free_i32(t); - tcg_temp_free_i64(avr); } =20 static void gen_mtvscr(DisasContext *ctx) @@ -179,7 +169,6 @@ static void gen_mtvscr(DisasContext *ctx) =20 tcg_gen_ld_i32(val, cpu_env, bofs); gen_helper_mtvscr(cpu_env, val); - tcg_temp_free_i32(val); } =20 #define GEN_VX_VMUL10(name, add_cin, ret_carry) \ @@ -228,13 +217,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ tcg_gen_add_i64(avr, t0, t2); \ set_avr64(rD(ctx->opcode), avr, true); \ } \ - \ - tcg_temp_free_i64(t0); \ - tcg_temp_free_i64(t1); \ - tcg_temp_free_i64(t2); \ - tcg_temp_free_i64(avr); \ - tcg_temp_free_i64(ten); \ - tcg_temp_free_i64(z); \ } \ =20 GEN_VX_VMUL10(vmul10uq, 0, 0); @@ -279,9 +261,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ rb =3D gen_avr_ptr(rB(ctx->opcode)); \ rd =3D gen_avr_ptr(rD(ctx->opcode)); \ gen_helper_##name(rd, ra, rb); \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ } =20 #define GEN_VXFORM_TRANS(name, opc2, opc3) \ @@ -306,9 +285,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ rb =3D gen_avr_ptr(rB(ctx->opcode)); \ rd =3D gen_avr_ptr(rD(ctx->opcode)); \ gen_helper_##name(cpu_env, rd, ra, rb); \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ } =20 #define GEN_VXFORM3(name, opc2, opc3) \ @@ -324,10 +300,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ rc =3D gen_avr_ptr(rC(ctx->opcode)); \ rd =3D gen_avr_ptr(rD(ctx->opcode)); \ gen_helper_##name(rd, ra, rb, rc); \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rc); \ - tcg_temp_free_ptr(rd); \ } =20 /* @@ -400,7 +372,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ } \ rb =3D gen_avr_ptr(rB(ctx->opcode)); \ gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], = rb); \ - tcg_temp_free_ptr(rb); \ } =20 GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0); @@ -457,9 +428,6 @@ static void trans_vmrgew(DisasContext *ctx) get_avr64(avr, VA, false); tcg_gen_deposit_i64(avr, avr, tmp, 0, 32); set_avr64(VT, avr, false); - - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(avr); } =20 static void trans_vmrgow(DisasContext *ctx) @@ -480,10 +448,6 @@ static void trans_vmrgow(DisasContext *ctx) get_avr64(t1, VA, false); tcg_gen_deposit_i64(avr, t0, t1, 32, 32); set_avr64(VT, avr, false); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(avr); } =20 /* @@ -518,10 +482,6 @@ static void trans_lvsl(DisasContext *ctx) */ tcg_gen_addi_i64(result, sh, 0x08090a0b0c0d0e0fULL); set_avr64(VT, result, false); - - tcg_temp_free_i64(result); - tcg_temp_free_i64(sh); - tcg_temp_free(EA); } =20 /* @@ -557,10 +517,6 @@ static void trans_lvsr(DisasContext *ctx) */ tcg_gen_subfi_i64(result, 0x18191a1b1c1d1e1fULL, sh); set_avr64(VT, result, false); - - tcg_temp_free_i64(result); - tcg_temp_free_i64(sh); - tcg_temp_free(EA); } =20 /* @@ -603,11 +559,6 @@ static void trans_vsl(DisasContext *ctx) tcg_gen_shl_i64(avr, avr, sh); tcg_gen_or_i64(avr, avr, carry); set_avr64(VT, avr, true); - - tcg_temp_free_i64(avr); - tcg_temp_free_i64(sh); - tcg_temp_free_i64(carry); - tcg_temp_free_i64(tmp); } =20 /* @@ -649,11 +600,6 @@ static void trans_vsr(DisasContext *ctx) tcg_gen_shr_i64(avr, avr, sh); tcg_gen_or_i64(avr, avr, carry); set_avr64(VT, avr, false); - - tcg_temp_free_i64(avr); - tcg_temp_free_i64(sh); - tcg_temp_free_i64(carry); - tcg_temp_free_i64(tmp); } =20 /* @@ -722,13 +668,6 @@ static void trans_vgbbd(DisasContext *ctx) for (j =3D 0; j < 2; j++) { set_avr64(VT, result[j], j); } - - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tcg_mask); - tcg_temp_free_i64(result[0]); - tcg_temp_free_i64(result[1]); - tcg_temp_free_i64(avr[0]); - tcg_temp_free_i64(avr[1]); } =20 /* @@ -753,8 +692,6 @@ static void trans_vclzw(DisasContext *ctx) tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUPPCState, vsr[32 + VT].u64[0]) + i * 4); } - - tcg_temp_free_i32(tmp); } =20 /* @@ -779,8 +716,6 @@ static void trans_vclzd(DisasContext *ctx) get_avr64(avr, VB, false); tcg_gen_clzi_i64(avr, avr, 64); set_avr64(VT, avr, false); - - tcg_temp_free_i64(avr); } =20 GEN_VXFORM_V(vmuluwm, MO_32, tcg_gen_gvec_mul, 4, 2); @@ -849,9 +784,6 @@ static TCGv_vec do_vrl_mask_vec(unsigned vece, TCGv_vec= vrb) /* negate the mask */ tcg_gen_xor_vec(vece, t0, t0, t2); =20 - tcg_temp_free_vec(t1); - tcg_temp_free_vec(t2); - return t0; } =20 @@ -870,9 +802,6 @@ static void gen_vrlnm_vec(unsigned vece, TCGv_vec vrt, = TCGv_vec vra, /* Rotate and mask */ tcg_gen_rotlv_vec(vece, vrt, vra, n); tcg_gen_and_vec(vece, vrt, vrt, mask); - - tcg_temp_free_vec(n); - tcg_temp_free_vec(mask); } =20 static bool do_vrlnm(DisasContext *ctx, arg_VX *a, int vece) @@ -926,10 +855,6 @@ static void gen_vrlmi_vec(unsigned vece, TCGv_vec vrt,= TCGv_vec vra, /* Rotate and insert */ tcg_gen_rotlv_vec(vece, tmp, vra, n); tcg_gen_bitsel_vec(vece, vrt, mask, tmp, vrt); - - tcg_temp_free_vec(n); - tcg_temp_free_vec(tmp); - tcg_temp_free_vec(mask); } =20 static bool do_vrlmi(DisasContext *ctx, arg_VX *a, int vece) @@ -1024,13 +949,6 @@ static bool do_vector_shift_quad(DisasContext *ctx, a= rg_VX *a, bool right, } tcg_gen_or_i64(hi, hi, lo); set_avr64(a->vrt, hi, !right); - - tcg_temp_free_i64(hi); - tcg_temp_free_i64(lo); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(n); - return true; } =20 @@ -1083,11 +1001,6 @@ static void do_vrlq_mask(TCGv_i64 mh, TCGv_i64 ml, T= CGv_i64 b, TCGv_i64 e) =20 tcg_gen_xor_i64(mh, mh, t0); tcg_gen_xor_i64(ml, ml, t0); - - tcg_temp_free_i64(th); - tcg_temp_free_i64(tl); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 static bool do_vector_rotl_quad(DisasContext *ctx, arg_VX *a, bool mask, @@ -1149,14 +1062,6 @@ static bool do_vector_rotl_quad(DisasContext *ctx, a= rg_VX *a, bool mask, =20 set_avr64(a->vrt, t0, true); set_avr64(a->vrt, t1, false); - - tcg_temp_free_i64(ah); - tcg_temp_free_i64(al); - tcg_temp_free_i64(vrb); - tcg_temp_free_i64(n); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - return true; } =20 @@ -1174,7 +1079,6 @@ static void glue(glue(gen_, NAME), _vec)(unsigned vec= e, TCGv_vec t, \ glue(glue(tcg_gen_, SAT), _vec)(VECE, t, a, b); \ tcg_gen_cmp_vec(TCG_COND_NE, VECE, x, x, t); \ tcg_gen_or_vec(VECE, sat, sat, x); \ - tcg_temp_free_vec(x); \ } \ static void glue(gen_, NAME)(DisasContext *ctx) \ { \ @@ -1266,9 +1170,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ rb =3D gen_avr_ptr(rB(ctx->opcode)); \ rd =3D gen_avr_ptr(rD(ctx->opcode)); \ gen_helper_##opname(cpu_env, rd, ra, rb); \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ } =20 #define GEN_VXRFORM(name, opc2, opc3) \ @@ -1325,10 +1226,6 @@ static void do_vcmp_rc(int vrt) =20 tcg_gen_or_i64(tmp, set, clr); tcg_gen_extrl_i64_i32(cpu_crf[6], tmp); - - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(set); - tcg_temp_free_i64(clr); } =20 static bool do_vcmp(DisasContext *ctx, arg_VC *a, TCGCond cond, int vece) @@ -1377,9 +1274,6 @@ static void gen_vcmpnez_vec(unsigned vece, TCGv_vec t= , TCGv_vec a, TCGv_vec b) =20 tcg_gen_or_vec(vece, t, t, t0); tcg_gen_or_vec(vece, t, t, t1); - - tcg_temp_free_vec(t0); - tcg_temp_free_vec(t1); } =20 static bool do_vcmpnez(DisasContext *ctx, arg_VC *a, int vece) @@ -1453,11 +1347,6 @@ static bool trans_VCMPEQUQ(DisasContext *ctx, arg_VC= *a) tcg_gen_andi_i32(cpu_crf[6], cpu_crf[6], 0xa); tcg_gen_xori_i32(cpu_crf[6], cpu_crf[6], 0x2); } - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - return true; } =20 @@ -1489,11 +1378,6 @@ static bool do_vcmpgtq(DisasContext *ctx, arg_VC *a,= bool sign) tcg_gen_andi_i32(cpu_crf[6], cpu_crf[6], 0xa); tcg_gen_xori_i32(cpu_crf[6], cpu_crf[6], 0x2); } - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - return true; } =20 @@ -1536,9 +1420,6 @@ static bool do_vcmpq(DisasContext *ctx, arg_VX_bf *a,= bool sign) tcg_gen_br(done); =20 gen_set_label(done); - tcg_temp_free_i64(vra); - tcg_temp_free_i64(vrb); - return true; } =20 @@ -1581,8 +1462,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ rb =3D gen_avr_ptr(rB(ctx->opcode)); \ rd =3D gen_avr_ptr(rD(ctx->opcode)); \ gen_helper_##name(rd, rb); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ } =20 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \ @@ -1597,8 +1476,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ rb =3D gen_avr_ptr(rB(ctx->opcode)); \ rd =3D gen_avr_ptr(rD(ctx->opcode)); \ gen_helper_##name(cpu_env, rd, rb); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ } =20 #define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \ @@ -1612,8 +1489,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ rb =3D gen_avr_ptr(rB(ctx->opcode)); \ rd =3D gen_avr_ptr(rD(ctx->opcode)); \ gen_helper_##name(rd, rb); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ } =20 #define GEN_VXFORM_NOA_3(name, opc2, opc3, opc4) \ @@ -1626,7 +1501,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ } \ rb =3D gen_avr_ptr(rB(ctx->opcode)); \ gen_helper_##name(cpu_gpr[rD(ctx->opcode)], rb); \ - tcg_temp_free_ptr(rb); \ } GEN_VXFORM_NOA(vupkhsb, 7, 8); GEN_VXFORM_NOA(vupkhsh, 7, 9); @@ -1655,7 +1529,6 @@ static void gen_vprtyb_vec(unsigned vece, TCGv_vec t,= TCGv_vec b) tcg_gen_xor_vec(vece, b, tmp, b); } tcg_gen_and_vec(vece, t, b, tcg_constant_vec_matching(t, vece, 1)); - tcg_temp_free_vec(tmp); } =20 /* vprtybw */ @@ -1750,9 +1623,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ rb =3D gen_avr_ptr(rB(ctx->opcode)); \ rd =3D gen_avr_ptr(rD(ctx->opcode)); \ gen_helper_##name(cpu_env, rd, rb, uimm); \ - tcg_temp_free_i32(uimm); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ } =20 #define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \ @@ -1773,9 +1643,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ rb =3D gen_avr_ptr(rB(ctx->opcode)); \ rd =3D gen_avr_ptr(rD(ctx->opcode)); \ gen_helper_##name(rd, rb, t0); \ - tcg_temp_free_i32(t0); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ } =20 GEN_VXFORM_VSPLT(vspltb, MO_8, 6, 8); @@ -1922,12 +1789,6 @@ static bool trans_VGNB(DisasContext *ctx, arg_VX_n *= a) tcg_gen_shri_i64(lo, lo, nbits); tcg_gen_or_i64(hi, hi, lo); tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], hi); - - tcg_temp_free_i64(hi); - tcg_temp_free_i64(lo); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - return true; } =20 @@ -1950,11 +1811,6 @@ static bool do_vextdx(DisasContext *ctx, arg_VA *a, = int size, bool right, tcg_gen_subfi_tl(rc, 32 - size, rc); } gen_helper(cpu_env, vrt, vra, vrb, rc); - - tcg_temp_free_ptr(vrt); - tcg_temp_free_ptr(vra); - tcg_temp_free_ptr(vrb); - tcg_temp_free(rc); return true; } =20 @@ -1983,31 +1839,22 @@ static bool do_vinsx(DisasContext *ctx, int vrt, in= t size, bool right, TCGv ra, } =20 gen_helper(cpu_env, t, rb, idx); - - tcg_temp_free_ptr(t); - tcg_temp_free(idx); - return true; } =20 static bool do_vinsvx(DisasContext *ctx, int vrt, int size, bool right, TC= Gv ra, int vrb, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, = TCGv)) { - bool ok; TCGv_i64 val; =20 val =3D tcg_temp_new_i64(); get_avr64(val, vrb, true); - ok =3D do_vinsx(ctx, vrt, size, right, ra, val, gen_helper); - - tcg_temp_free_i64(val); - return ok; + return do_vinsx(ctx, vrt, size, right, ra, val, gen_helper); } =20 static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a, int size, bool right, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, T= CGv)) { - bool ok; TCGv_i64 val; =20 REQUIRE_INSNS_FLAGS2(ctx, ISA310); @@ -2016,10 +1863,7 @@ static bool do_vinsx_VX(DisasContext *ctx, arg_VX *a= , int size, bool right, val =3D tcg_temp_new_i64(); tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]); =20 - ok =3D do_vinsx(ctx, a->vrt, size, right, cpu_gpr[a->vra], val, gen_he= lper); - - tcg_temp_free_i64(val); - return ok; + return do_vinsx(ctx, a->vrt, size, right, cpu_gpr[a->vra], val, gen_he= lper); } =20 static bool do_vinsvx_VX(DisasContext *ctx, arg_VX *a, int size, bool righ= t, @@ -2035,7 +1879,6 @@ static bool do_vinsvx_VX(DisasContext *ctx, arg_VX *a= , int size, bool right, static bool do_vins_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size, void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_i64, T= CGv)) { - bool ok; TCGv_i64 val; =20 REQUIRE_INSNS_FLAGS2(ctx, ISA310); @@ -2059,11 +1902,8 @@ static bool do_vins_VX_uim4(DisasContext *ctx, arg_V= X_uim4 *a, int size, val =3D tcg_temp_new_i64(); tcg_gen_extu_tl_i64(val, cpu_gpr[a->vrb]); =20 - ok =3D do_vinsx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim), val, - gen_helper); - - tcg_temp_free_i64(val); - return ok; + return do_vinsx(ctx, a->vrt, size, false, tcg_constant_tl(a->uim), val, + gen_helper); } =20 static bool do_vinsert_VX_uim4(DisasContext *ctx, arg_VX_uim4 *a, int size, @@ -2122,10 +1962,6 @@ static void gen_vsldoi(DisasContext *ctx) rd =3D gen_avr_ptr(rD(ctx->opcode)); sh =3D tcg_const_i32(VSH(ctx->opcode)); gen_helper_vsldoi(rd, ra, rb, sh); - tcg_temp_free_ptr(ra); - tcg_temp_free_ptr(rb); - tcg_temp_free_ptr(rd); - tcg_temp_free_i32(sh); } =20 static bool trans_VSLDBI(DisasContext *ctx, arg_VN *a) @@ -2148,16 +1984,10 @@ static bool trans_VSLDBI(DisasContext *ctx, arg_VN = *a) =20 tcg_gen_extract2_i64(t0, t1, t0, 64 - a->sh); tcg_gen_extract2_i64(t1, t2, t1, 64 - a->sh); - - tcg_temp_free_i64(t2); } =20 set_avr64(a->vrt, t0, true); set_avr64(a->vrt, t1, false); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - return true; } =20 @@ -2181,16 +2011,10 @@ static bool trans_VSRDBI(DisasContext *ctx, arg_VN = *a) =20 tcg_gen_extract2_i64(t0, t0, t1, a->sh); tcg_gen_extract2_i64(t1, t1, t2, a->sh); - - tcg_temp_free_i64(t2); } =20 set_avr64(a->vrt, t0, false); set_avr64(a->vrt, t1, true); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - return true; } =20 @@ -2223,8 +2047,6 @@ static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX= _tb *a) tcg_gen_sari_i64(tmp, tmp, 63); set_avr64(a->vrt, tmp, false); set_avr64(a->vrt, tmp, true); - - tcg_temp_free_i64(tmp); return true; } =20 @@ -2278,12 +2100,6 @@ static bool do_vextractm(DisasContext *ctx, arg_VX_t= b *a, unsigned vece) tcg_gen_shri_i64(hi, hi, 64 - elem_count_half); tcg_gen_extract2_i64(lo, lo, hi, 64 - elem_count_half); tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], lo); - - tcg_temp_free_i64(hi); - tcg_temp_free_i64(lo); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - return true; } =20 @@ -2304,9 +2120,6 @@ static bool trans_VEXTRACTQM(DisasContext *ctx, arg_V= X_tb *a) get_avr64(tmp, a->vrb, true); tcg_gen_shri_i64(tmp, tmp, 63); tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], tmp); - - tcg_temp_free_i64(tmp); - return true; } =20 @@ -2367,12 +2180,6 @@ static bool do_mtvsrm(DisasContext *ctx, arg_VX_tb *= a, unsigned vece) =20 set_avr64(a->vrt, lo, false); set_avr64(a->vrt, hi, true); - - tcg_temp_free_i64(hi); - tcg_temp_free_i64(lo); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - return true; } =20 @@ -2394,9 +2201,6 @@ static bool trans_MTVSRQM(DisasContext *ctx, arg_VX_t= b *a) tcg_gen_sextract_i64(tmp, tmp, 0, 1); set_avr64(a->vrt, tmp, false); set_avr64(a->vrt, tmp, true); - - tcg_temp_free_i64(tmp); - return true; } =20 @@ -2445,10 +2249,6 @@ static bool do_vcntmb(DisasContext *ctx, arg_VX_mp *= a, int vece) =20 tcg_gen_shli_i64(rt, rt, TARGET_LONG_BITS - 8 + vece); tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], rt); - - tcg_temp_free_i64(vrb); - tcg_temp_free_i64(rt); - return true; } =20 @@ -2473,12 +2273,7 @@ static bool do_vstri(DisasContext *ctx, arg_VX_tb_rc= *a, } else { TCGv_i32 discard =3D tcg_temp_new_i32(); gen_helper(discard, vrt, vrb); - tcg_temp_free_i32(discard); } - - tcg_temp_free_ptr(vrt); - tcg_temp_free_ptr(vrb); - return true; } =20 @@ -2531,12 +2326,6 @@ static bool do_vclrb(DisasContext *ctx, arg_VX *a, b= ool right) get_avr64(tmp, a->vra, false); tcg_gen_and_i64(tmp, tmp, ml); set_avr64(a->vrt, tmp, false); - - tcg_temp_free_i64(rb); - tcg_temp_free_i64(mh); - tcg_temp_free_i64(ml); - tcg_temp_free_i64(tmp); - return true; } =20 @@ -2560,10 +2349,6 @@ static void glue(gen_, name0##_##name1)(DisasContext= *ctx) \ } else { \ gen_helper_##name0(cpu_env, rd, ra, rb, rc); \ } \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rc); \ - tcg_temp_free_ptr(rd); \ } =20 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) @@ -2579,11 +2364,6 @@ static bool do_va_helper(DisasContext *ctx, arg_VA *= a, vrb =3D gen_avr_ptr(a->vrb); vrc =3D gen_avr_ptr(a->rc); gen_helper(vrt, vra, vrb, vrc); - tcg_temp_free_ptr(vrt); - tcg_temp_free_ptr(vra); - tcg_temp_free_ptr(vrb); - tcg_temp_free_ptr(vrc); - return true; } =20 @@ -2654,11 +2434,6 @@ static bool do_va_env_helper(DisasContext *ctx, arg_= VA *a, vrb =3D gen_avr_ptr(a->vrb); vrc =3D gen_avr_ptr(a->rc); gen_helper(cpu_env, vrt, vra, vrb, vrc); - tcg_temp_free_ptr(vrt); - tcg_temp_free_ptr(vra); - tcg_temp_free_ptr(vrb); - tcg_temp_free_ptr(vrc); - return true; } =20 @@ -2751,8 +2526,6 @@ static bool trans_VEXTSD2Q(DisasContext *ctx, arg_VX_= tb *a) set_avr64(a->vrt, tmp, false); tcg_gen_sari_i64(tmp, tmp, 63); set_avr64(a->vrt, tmp, true); - - tcg_temp_free_i64(tmp); return true; } =20 @@ -2799,11 +2572,6 @@ static void gen_##op(DisasContext *ctx) \ ps =3D tcg_const_i32((ctx->opcode & 0x200) !=3D 0); \ \ gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \ - \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ - tcg_temp_free_i32(ps); \ } =20 #define GEN_BCD2(op) \ @@ -2823,10 +2591,6 @@ static void gen_##op(DisasContext *ctx) \ ps =3D tcg_const_i32((ctx->opcode & 0x200) !=3D 0); \ \ gen_helper_##op(cpu_crf[6], rd, rb, ps); \ - \ - tcg_temp_free_ptr(rb); \ - tcg_temp_free_ptr(rd); \ - tcg_temp_free_i32(ps); \ } =20 GEN_BCD(bcdadd) @@ -2933,8 +2697,6 @@ static void gen_vsbox(DisasContext *ctx) ra =3D gen_avr_ptr(rA(ctx->opcode)); rd =3D gen_avr_ptr(rD(ctx->opcode)); gen_helper_vsbox(rd, ra); - tcg_temp_free_ptr(ra); - tcg_temp_free_ptr(rd); } =20 GEN_VXFORM(vcipher, 4, 20) @@ -2960,9 +2722,6 @@ static void gen_##op(DisasContext *ctx) \ rd =3D gen_avr_ptr(rD(ctx->opcode)); \ st_six =3D tcg_const_i32(rB(ctx->opcode)); \ gen_helper_##op(rd, ra, st_six); \ - tcg_temp_free_ptr(ra); \ - tcg_temp_free_ptr(rd); \ - tcg_temp_free_i32(st_six); \ } =20 VSHASIGMA(vshasigmaw) @@ -3077,12 +2836,6 @@ static bool trans_VMSUMUDM(DisasContext *ctx, arg_VA= *a) =20 set_avr64(a->vrt, rl, false); set_avr64(a->vrt, rh, true); - - tcg_temp_free_i64(rl); - tcg_temp_free_i64(rh); - tcg_temp_free_i64(src1); - tcg_temp_free_i64(src2); - return true; } =20 @@ -3128,14 +2881,6 @@ static bool trans_VMSUMCUD(DisasContext *ctx, arg_VA= *a) /* Discard 64 more bits to complete the CHOP128(temp >> 128) */ set_avr64(a->vrt, tmp0, false); set_avr64(a->vrt, zero, true); - - tcg_temp_free_i64(tmp0); - tcg_temp_free_i64(tmp1); - tcg_temp_free_i64(prod1h); - tcg_temp_free_i64(prod1l); - tcg_temp_free_i64(prod0h); - tcg_temp_free_i64(prod0l); - return true; } =20 @@ -3149,10 +2894,6 @@ static bool do_vx_helper(DisasContext *ctx, arg_VX *= a, rb =3D gen_avr_ptr(a->vrb); rd =3D gen_avr_ptr(a->vrt); gen_helper(rd, ra, rb); - tcg_temp_free_ptr(ra); - tcg_temp_free_ptr(rb); - tcg_temp_free_ptr(rd); - return true; } =20 @@ -3237,12 +2978,6 @@ static bool do_vx_vmuleo(DisasContext *ctx, arg_VX *= a, bool even, gen_mul(vrt0, vrt1, vra, vrb); set_avr64(a->vrt, vrt0, false); set_avr64(a->vrt, vrt1, true); - - tcg_temp_free_i64(vra); - tcg_temp_free_i64(vrb); - tcg_temp_free_i64(vrt0); - tcg_temp_free_i64(vrt1); - return true; } =20 @@ -3302,10 +3037,6 @@ static void do_vx_vmulhw_i64(TCGv_i64 t, TCGv_i64 a,= TCGv_i64 b, bool sign) =20 tcg_gen_shri_i64(lh, lh, 32); tcg_gen_deposit_i64(t, hh, lh, 0, 32); - - tcg_temp_free_i64(hh); - tcg_temp_free_i64(lh); - tcg_temp_free_i64(temp); } =20 static void do_vx_vmulhd_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, bool sign) @@ -3318,8 +3049,6 @@ static void do_vx_vmulhd_i64(TCGv_i64 t, TCGv_i64 a, = TCGv_i64 b, bool sign) } else { tcg_gen_mulu2_i64(tlow, t, a, b); } - - tcg_temp_free_i64(tlow); } =20 static bool do_vx_mulh(DisasContext *ctx, arg_VX *a, bool sign, @@ -3344,13 +3073,7 @@ static bool do_vx_mulh(DisasContext *ctx, arg_VX *a,= bool sign, =20 set_avr64(a->vrt, vrt, i); } - - tcg_temp_free_i64(vra); - tcg_temp_free_i64(vrb); - tcg_temp_free_i64(vrt); - return true; - } =20 TRANS(VMULHSW, do_vx_mulh, true , do_vx_vmulhw_i64) @@ -3368,7 +3091,6 @@ static void do_vavg(unsigned vece, TCGv_vec t, TCGv_v= ec a, TCGv_vec b, gen_shr_vec(vece, b, b, 1); tcg_gen_add_vec(vece, t, a, b); tcg_gen_add_vec(vece, t, t, tmp); - tcg_temp_free_vec(tmp); } =20 QEMU_FLATTEN @@ -3538,8 +3260,6 @@ static void NAME(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b) = \ tcg_gen_movi_i32(t1, 0); \ tcg_gen_movcond_i32(TCG_COND_NE, b, t0, t1, t0, b); \ DIV(t, a, b); \ - tcg_temp_free_i32(t0); \ - tcg_temp_free_i32(t1); \ } =20 #define DIVU64(NAME, DIV) \ @@ -3564,8 +3284,6 @@ static void NAME(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b) = \ tcg_gen_movi_i64(t1, 0); \ tcg_gen_movcond_i64(TCG_COND_NE, b, t0, t1, t0, b); \ DIV(t, a, b); \ - tcg_temp_free_i64(t0); \ - tcg_temp_free_i64(t1); \ } =20 DIVS32(do_divsw, tcg_gen_div_i32) @@ -3596,9 +3314,6 @@ static void do_dives_i32(TCGv_i32 t, TCGv_i32 a, TCGv= _i32 b) =20 /* if quotient doesn't fit in 32 bits the result is undefined */ tcg_gen_extrl_i64_i32(t, val1); - - tcg_temp_free_i64(val1); - tcg_temp_free_i64(val2); } =20 static void do_diveu_i32(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b) @@ -3617,9 +3332,6 @@ static void do_diveu_i32(TCGv_i32 t, TCGv_i32 a, TCGv= _i32 b) =20 /* if quotient doesn't fit in 32 bits the result is undefined */ tcg_gen_extrl_i64_i32(t, val1); - - tcg_temp_free_i64(val1); - tcg_temp_free_i64(val2); } =20 DIVS32(do_divesw, do_dives_i32) diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx= -impl.c.inc index 4deb29ee42..6e63403727 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -40,8 +40,6 @@ static void gen_##name(DisasContext *ctx) = \ gen_qemu_##operation(ctx, t0, EA); \ set_cpu_vsr(xT(ctx->opcode), t0, true); \ /* NOTE: cpu_vsrl is undefined */ \ - tcg_temp_free(EA); \ - tcg_temp_free_i64(t0); \ } =20 VSX_LOAD_SCALAR(lxsdx, ld64_i64) @@ -68,8 +66,6 @@ static void gen_lxvd2x(DisasContext *ctx) tcg_gen_addi_tl(EA, EA, 8); gen_qemu_ld64_i64(ctx, t0, EA); set_cpu_vsr(xT(ctx->opcode), t0, false); - tcg_temp_free(EA); - tcg_temp_free_i64(t0); } =20 static void gen_lxvw4x(DisasContext *ctx) @@ -99,8 +95,6 @@ static void gen_lxvw4x(DisasContext *ctx) tcg_gen_qemu_ld_i64(t0, EA, ctx->mem_idx, MO_LEUQ); tcg_gen_shri_i64(t1, t0, 32); tcg_gen_deposit_i64(xtl, t1, t0, 32, 32); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } else { tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEUQ); tcg_gen_addi_tl(EA, EA, 8); @@ -108,9 +102,6 @@ static void gen_lxvw4x(DisasContext *ctx) } set_cpu_vsr(xT(ctx->opcode), xth, true); set_cpu_vsr(xT(ctx->opcode), xtl, false); - tcg_temp_free(EA); - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); } =20 static void gen_lxvwsx(DisasContext *ctx) @@ -138,9 +129,6 @@ static void gen_lxvwsx(DisasContext *ctx) data =3D tcg_temp_new_i32(); tcg_gen_qemu_ld_i32(data, EA, ctx->mem_idx, DEF_MEMOP(MO_UL)); tcg_gen_gvec_dup_i32(MO_UL, vsr_full_offset(xT(ctx->opcode)), 16, 16, = data); - - tcg_temp_free(EA); - tcg_temp_free_i32(data); } =20 static void gen_lxvdsx(DisasContext *ctx) @@ -161,9 +149,6 @@ static void gen_lxvdsx(DisasContext *ctx) data =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, DEF_MEMOP(MO_UQ)); tcg_gen_gvec_dup_i64(MO_UQ, vsr_full_offset(xT(ctx->opcode)), 16, 16, = data); - - tcg_temp_free(EA); - tcg_temp_free_i64(data); } =20 static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl, @@ -186,10 +171,6 @@ static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl, tcg_gen_shri_i64(t1, inl, 8); tcg_gen_and_i64(t1, t1, mask); tcg_gen_or_i64(outl, t0, t1); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(mask); } =20 static void gen_bswap32x4(TCGv_i64 outh, TCGv_i64 outl, @@ -204,10 +185,8 @@ static void gen_bswap32x4(TCGv_i64 outh, TCGv_i64 outl, tcg_gen_deposit_i64(outh, outh, hi, 32, 32); tcg_gen_shri_i64(outl, lo, 32); tcg_gen_deposit_i64(outl, outl, lo, 32, 32); - - tcg_temp_free_i64(hi); - tcg_temp_free_i64(lo); } + static void gen_lxvh8x(DisasContext *ctx) { TCGv EA; @@ -232,9 +211,6 @@ static void gen_lxvh8x(DisasContext *ctx) } set_cpu_vsr(xT(ctx->opcode), xth, true); set_cpu_vsr(xT(ctx->opcode), xtl, false); - tcg_temp_free(EA); - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); } =20 static void gen_lxvb16x(DisasContext *ctx) @@ -257,9 +233,6 @@ static void gen_lxvb16x(DisasContext *ctx) tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEUQ); set_cpu_vsr(xT(ctx->opcode), xth, true); set_cpu_vsr(xT(ctx->opcode), xtl, false); - tcg_temp_free(EA); - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); } =20 #ifdef TARGET_PPC64 @@ -285,8 +258,6 @@ static void gen_##name(DisasContext *ctx) = \ gen_set_access_type(ctx, ACCESS_INT); \ gen_addr_register(ctx, EA); \ gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \ - tcg_temp_free(EA); \ - tcg_temp_free_ptr(xt); \ } =20 VSX_VECTOR_LOAD_STORE_LENGTH(lxvl) @@ -310,8 +281,6 @@ static void gen_##name(DisasContext *ctx) = \ gen_addr_reg_index(ctx, EA); \ get_cpu_vsr(t0, xS(ctx->opcode), true); \ gen_qemu_##operation(ctx, t0, EA); \ - tcg_temp_free(EA); \ - tcg_temp_free_i64(t0); \ } =20 VSX_STORE_SCALAR(stxsdx, st64_i64) @@ -338,8 +307,6 @@ static void gen_stxvd2x(DisasContext *ctx) tcg_gen_addi_tl(EA, EA, 8); get_cpu_vsr(t0, xS(ctx->opcode), false); gen_qemu_st64_i64(ctx, t0, EA); - tcg_temp_free(EA); - tcg_temp_free_i64(t0); } =20 static void gen_stxvw4x(DisasContext *ctx) @@ -370,16 +337,11 @@ static void gen_stxvw4x(DisasContext *ctx) tcg_gen_shri_i64(t0, xsl, 32); tcg_gen_deposit_i64(t1, t0, xsl, 32, 32); tcg_gen_qemu_st_i64(t1, EA, ctx->mem_idx, MO_LEUQ); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } else { tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEUQ); tcg_gen_addi_tl(EA, EA, 8); tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEUQ); } - tcg_temp_free(EA); - tcg_temp_free_i64(xsh); - tcg_temp_free_i64(xsl); } =20 static void gen_stxvh8x(DisasContext *ctx) @@ -407,16 +369,11 @@ static void gen_stxvh8x(DisasContext *ctx) tcg_gen_qemu_st_i64(outh, EA, ctx->mem_idx, MO_BEUQ); tcg_gen_addi_tl(EA, EA, 8); tcg_gen_qemu_st_i64(outl, EA, ctx->mem_idx, MO_BEUQ); - tcg_temp_free_i64(outh); - tcg_temp_free_i64(outl); } else { tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEUQ); tcg_gen_addi_tl(EA, EA, 8); tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEUQ); } - tcg_temp_free(EA); - tcg_temp_free_i64(xsh); - tcg_temp_free_i64(xsl); } =20 static void gen_stxvb16x(DisasContext *ctx) @@ -439,9 +396,6 @@ static void gen_stxvb16x(DisasContext *ctx) tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEUQ); tcg_gen_addi_tl(EA, EA, 8); tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEUQ); - tcg_temp_free(EA); - tcg_temp_free_i64(xsh); - tcg_temp_free_i64(xsl); } =20 static void gen_mfvsrwz(DisasContext *ctx) @@ -462,8 +416,6 @@ static void gen_mfvsrwz(DisasContext *ctx) get_cpu_vsr(xsh, xS(ctx->opcode), true); tcg_gen_ext32u_i64(tmp, xsh); tcg_gen_trunc_i64_tl(cpu_gpr[rA(ctx->opcode)], tmp); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(xsh); } =20 static void gen_mtvsrwa(DisasContext *ctx) @@ -484,8 +436,6 @@ static void gen_mtvsrwa(DisasContext *ctx) tcg_gen_extu_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)]); tcg_gen_ext32s_i64(xsh, tmp); set_cpu_vsr(xT(ctx->opcode), xsh, true); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(xsh); } =20 static void gen_mtvsrwz(DisasContext *ctx) @@ -506,8 +456,6 @@ static void gen_mtvsrwz(DisasContext *ctx) tcg_gen_extu_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)]); tcg_gen_ext32u_i64(xsh, tmp); set_cpu_vsr(xT(ctx->opcode), xsh, true); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(xsh); } =20 #if defined(TARGET_PPC64) @@ -528,7 +476,6 @@ static void gen_mfvsrd(DisasContext *ctx) t0 =3D tcg_temp_new_i64(); get_cpu_vsr(t0, xS(ctx->opcode), true); tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0); - tcg_temp_free_i64(t0); } =20 static void gen_mtvsrd(DisasContext *ctx) @@ -548,7 +495,6 @@ static void gen_mtvsrd(DisasContext *ctx) t0 =3D tcg_temp_new_i64(); tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]); set_cpu_vsr(xT(ctx->opcode), t0, true); - tcg_temp_free_i64(t0); } =20 static void gen_mfvsrld(DisasContext *ctx) @@ -568,7 +514,6 @@ static void gen_mfvsrld(DisasContext *ctx) t0 =3D tcg_temp_new_i64(); get_cpu_vsr(t0, xS(ctx->opcode), false); tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], t0); - tcg_temp_free_i64(t0); } =20 static void gen_mtvsrdd(DisasContext *ctx) @@ -596,7 +541,6 @@ static void gen_mtvsrdd(DisasContext *ctx) =20 tcg_gen_mov_i64(t0, cpu_gpr[rB(ctx->opcode)]); set_cpu_vsr(xT(ctx->opcode), t0, false); - tcg_temp_free_i64(t0); } =20 static void gen_mtvsrws(DisasContext *ctx) @@ -619,7 +563,6 @@ static void gen_mtvsrws(DisasContext *ctx) cpu_gpr[rA(ctx->opcode)], 32, 32); set_cpu_vsr(xT(ctx->opcode), t0, false); set_cpu_vsr(xT(ctx->opcode), t0, true); - tcg_temp_free_i64(t0); } =20 #endif @@ -666,14 +609,11 @@ static void glue(gen_, name)(DisasContext *ctx) = \ tcg_gen_and_i64(xa, xa, sgm); \ tcg_gen_andc_i64(xb, xb, sgm); \ tcg_gen_or_i64(xb, xb, xa); \ - tcg_temp_free_i64(xa); \ break; \ } \ } \ set_cpu_vsr(xT(ctx->opcode), xb, true); \ set_cpu_vsr(xT(ctx->opcode), tcg_constant_i64(0), false); \ - tcg_temp_free_i64(xb); \ - tcg_temp_free_i64(sgm); \ } =20 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP) @@ -717,15 +657,10 @@ static void glue(gen_, name)(DisasContext *ctx) = \ tcg_gen_and_i64(xah, tmp, sgm); \ tcg_gen_andc_i64(xbh, xbh, sgm); \ tcg_gen_or_i64(xbh, xbh, xah); \ - tcg_temp_free_i64(xah); \ break; \ } \ set_cpu_vsr(xt, xbh, true); \ set_cpu_vsr(xt, xbl, false); \ - tcg_temp_free_i64(xbl); \ - tcg_temp_free_i64(xbh); \ - tcg_temp_free_i64(sgm); \ - tcg_temp_free_i64(tmp); \ } =20 VSX_SCALAR_MOVE_QP(xsabsqp, OP_ABS, SGN_MASK_DP) @@ -870,11 +805,7 @@ static void gen_##name(DisasContext *ctx) = \ } else { = \ ignored =3D tcg_temp_new_i32(); = \ gen_helper_##name(ignored, cpu_env, xt, xa, xb); = \ - tcg_temp_free_i32(ignored); = \ } = \ - tcg_temp_free_ptr(xt); = \ - tcg_temp_free_ptr(xa); = \ - tcg_temp_free_ptr(xb); = \ } =20 VSX_CMP(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX) @@ -899,10 +830,6 @@ static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb= _rc *a) xt =3D gen_avr_ptr(a->rt); xb =3D gen_avr_ptr(a->rb); gen_helper_XSCVQPDP(cpu_env, ro, xt, xb); - tcg_temp_free_i32(ro); - tcg_temp_free_ptr(xt); - tcg_temp_free_ptr(xb); - return true; } =20 @@ -917,9 +844,6 @@ static bool do_helper_env_X_tb(DisasContext *ctx, arg_X= _tb *a, xt =3D gen_avr_ptr(a->rt); xb =3D gen_avr_ptr(a->rb); gen_helper(cpu_env, xt, xb); - tcg_temp_free_ptr(xt); - tcg_temp_free_ptr(xb); - return true; } =20 @@ -938,7 +862,6 @@ static void gen_##name(DisasContext *ctx) = \ } = \ opc =3D tcg_const_i32(ctx->opcode); = \ gen_helper_##name(cpu_env, opc); = \ - tcg_temp_free_i32(opc); = \ } =20 #define GEN_VSX_HELPER_X3(name, op1, op2, inval, type) = \ @@ -953,9 +876,6 @@ static void gen_##name(DisasContext *ctx) = \ xa =3D gen_vsr_ptr(xA(ctx->opcode)); = \ xb =3D gen_vsr_ptr(xB(ctx->opcode)); = \ gen_helper_##name(cpu_env, xt, xa, xb); = \ - tcg_temp_free_ptr(xt); = \ - tcg_temp_free_ptr(xa); = \ - tcg_temp_free_ptr(xb); = \ } =20 #define GEN_VSX_HELPER_X2(name, op1, op2, inval, type) = \ @@ -969,8 +889,6 @@ static void gen_##name(DisasContext *ctx) = \ xt =3D gen_vsr_ptr(xT(ctx->opcode)); = \ xb =3D gen_vsr_ptr(xB(ctx->opcode)); = \ gen_helper_##name(cpu_env, xt, xb); = \ - tcg_temp_free_ptr(xt); = \ - tcg_temp_free_ptr(xb); = \ } =20 #define GEN_VSX_HELPER_X2_AB(name, op1, op2, inval, type) = \ @@ -986,9 +904,6 @@ static void gen_##name(DisasContext *ctx) = \ xa =3D gen_vsr_ptr(xA(ctx->opcode)); = \ xb =3D gen_vsr_ptr(xB(ctx->opcode)); = \ gen_helper_##name(cpu_env, opc, xa, xb); = \ - tcg_temp_free_i32(opc); = \ - tcg_temp_free_ptr(xa); = \ - tcg_temp_free_ptr(xb); = \ } =20 #define GEN_VSX_HELPER_X1(name, op1, op2, inval, type) = \ @@ -1003,8 +918,6 @@ static void gen_##name(DisasContext *ctx) = \ opc =3D tcg_const_i32(ctx->opcode); = \ xb =3D gen_vsr_ptr(xB(ctx->opcode)); = \ gen_helper_##name(cpu_env, opc, xb); = \ - tcg_temp_free_i32(opc); = \ - tcg_temp_free_ptr(xb); = \ } =20 #define GEN_VSX_HELPER_R3(name, op1, op2, inval, type) = \ @@ -1021,10 +934,6 @@ static void gen_##name(DisasContext *ctx) = \ xa =3D gen_vsr_ptr(rA(ctx->opcode) + 32); = \ xb =3D gen_vsr_ptr(rB(ctx->opcode) + 32); = \ gen_helper_##name(cpu_env, opc, xt, xa, xb); = \ - tcg_temp_free_i32(opc); = \ - tcg_temp_free_ptr(xt); = \ - tcg_temp_free_ptr(xa); = \ - tcg_temp_free_ptr(xb); = \ } =20 #define GEN_VSX_HELPER_R2(name, op1, op2, inval, type) = \ @@ -1040,9 +949,6 @@ static void gen_##name(DisasContext *ctx) = \ xt =3D gen_vsr_ptr(rD(ctx->opcode) + 32); = \ xb =3D gen_vsr_ptr(rB(ctx->opcode) + 32); = \ gen_helper_##name(cpu_env, opc, xt, xb); = \ - tcg_temp_free_i32(opc); = \ - tcg_temp_free_ptr(xt); = \ - tcg_temp_free_ptr(xb); = \ } =20 #define GEN_VSX_HELPER_R2_AB(name, op1, op2, inval, type) = \ @@ -1058,9 +964,6 @@ static void gen_##name(DisasContext *ctx) = \ xa =3D gen_vsr_ptr(rA(ctx->opcode) + 32); = \ xb =3D gen_vsr_ptr(rB(ctx->opcode) + 32); = \ gen_helper_##name(cpu_env, opc, xa, xb); = \ - tcg_temp_free_i32(opc); = \ - tcg_temp_free_ptr(xa); = \ - tcg_temp_free_ptr(xb); = \ } =20 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \ @@ -1078,8 +981,6 @@ static void gen_##name(DisasContext *ctx) = \ gen_helper_##name(t1, cpu_env, t0); \ set_cpu_vsr(xT(ctx->opcode), t1, true); \ set_cpu_vsr(xT(ctx->opcode), tcg_constant_i64(0), false); \ - tcg_temp_free_i64(t0); \ - tcg_temp_free_i64(t1); \ } =20 GEN_VSX_HELPER_X3(xsadddp, 0x00, 0x04, 0, PPC2_VSX) @@ -1291,8 +1192,6 @@ static bool do_XX2_bf_uim(DisasContext *ctx, arg_XX2_= bf_uim *a, bool vsr, REQUIRE_VSX(ctx); xb =3D vsr ? gen_vsr_ptr(a->xb) : gen_avr_ptr(a->xb); gen_helper(cpu_env, tcg_constant_i32(a->bf), tcg_constant_i32(a->uim),= xb); - tcg_temp_free_ptr(xb); - return true; } =20 @@ -1314,9 +1213,6 @@ bool trans_XSCVSPDPN(DisasContext *ctx, arg_XX2 *a) =20 set_cpu_vsr(a->xt, tmp, true); set_cpu_vsr(a->xt, tcg_constant_i64(0), false); - - tcg_temp_free_i64(tmp); - return true; } =20 @@ -1413,11 +1309,6 @@ static bool trans_XXPERM(DisasContext *ctx, arg_XX3 = *a) xb =3D gen_vsr_ptr(a->xb); =20 gen_helper_VPERM(xt, xa, xt, xb); - - tcg_temp_free_ptr(xt); - tcg_temp_free_ptr(xa); - tcg_temp_free_ptr(xb); - return true; } =20 @@ -1433,11 +1324,6 @@ static bool trans_XXPERMR(DisasContext *ctx, arg_XX3= *a) xb =3D gen_vsr_ptr(a->xb); =20 gen_helper_VPERMR(xt, xa, xt, xb); - - tcg_temp_free_ptr(xt); - tcg_temp_free_ptr(xa); - tcg_temp_free_ptr(xb); - return true; } =20 @@ -1458,8 +1344,6 @@ static bool trans_XXPERMDI(DisasContext *ctx, arg_XX3= _dm *a) =20 set_cpu_vsr(a->xt, t0, true); set_cpu_vsr(a->xt, t1, false); - - tcg_temp_free_i64(t1); } else { get_cpu_vsr(t0, a->xa, (a->dm & 2) =3D=3D 0); set_cpu_vsr(a->xt, t0, true); @@ -1467,9 +1351,6 @@ static bool trans_XXPERMDI(DisasContext *ctx, arg_XX3= _dm *a) get_cpu_vsr(t0, a->xb, (a->dm & 1) =3D=3D 0); set_cpu_vsr(a->xt, t0, false); } - - tcg_temp_free_i64(t0); - return true; } =20 @@ -1486,12 +1367,6 @@ static bool trans_XXPERMX(DisasContext *ctx, arg_8RR= _XX4_uim3 *a) xc =3D gen_vsr_ptr(a->xc); =20 gen_helper_XXPERMX(xt, xa, xb, xc, tcg_constant_tl(a->uim3)); - - tcg_temp_free_ptr(xt); - tcg_temp_free_ptr(xa); - tcg_temp_free_ptr(xb); - tcg_temp_free_ptr(xc); - return true; } =20 @@ -1514,10 +1389,6 @@ static bool do_xxgenpcv(DisasContext *ctx, arg_X_imm= 5 *a, vrb =3D gen_avr_ptr(a->vrb); =20 fn[a->imm](xt, vrb); - - tcg_temp_free_ptr(xt); - tcg_temp_free_ptr(vrb); - return true; } =20 @@ -1550,12 +1421,6 @@ static bool do_xsmadd(DisasContext *ctx, int tgt, in= t src1, int src2, int src3, s3 =3D gen_vsr_ptr(src3); =20 gen_helper(cpu_env, t, s1, s2, s3); - - tcg_temp_free_ptr(t); - tcg_temp_free_ptr(s1); - tcg_temp_free_ptr(s2); - tcg_temp_free_ptr(s3); - return true; } =20 @@ -1636,10 +1501,6 @@ static void gen_##name(DisasContext *ctx) = \ s3 =3D gen_vsr_ptr(xB(ctx->opcode)); = \ } = \ gen_helper_##name(cpu_env, xt, s1, s2, s3); = \ - tcg_temp_free_ptr(xt); = \ - tcg_temp_free_ptr(s1); = \ - tcg_temp_free_ptr(s2); = \ - tcg_temp_free_ptr(s3); = \ } =20 GEN_VSX_HELPER_VSX_MADD(xvmadddp, 0x04, 0x0C, 0x0D, 0, PPC2_VSX) @@ -1673,11 +1534,6 @@ static void gen_xxbrd(DisasContext *ctx) tcg_gen_bswap64_i64(xtl, xbl); set_cpu_vsr(xT(ctx->opcode), xth, true); set_cpu_vsr(xT(ctx->opcode), xtl, false); - - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xbl); } =20 static void gen_xxbrh(DisasContext *ctx) @@ -1701,11 +1557,6 @@ static void gen_xxbrh(DisasContext *ctx) gen_bswap16x8(xth, xtl, xbh, xbl); set_cpu_vsr(xT(ctx->opcode), xth, true); set_cpu_vsr(xT(ctx->opcode), xtl, false); - - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xbl); } =20 static void gen_xxbrq(DisasContext *ctx) @@ -1733,12 +1584,6 @@ static void gen_xxbrq(DisasContext *ctx) set_cpu_vsr(xT(ctx->opcode), xtl, false); tcg_gen_mov_i64(xth, t0); set_cpu_vsr(xT(ctx->opcode), xth, true); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xbl); } =20 static void gen_xxbrw(DisasContext *ctx) @@ -1762,11 +1607,6 @@ static void gen_xxbrw(DisasContext *ctx) gen_bswap32x4(xth, xtl, xbh, xbl); set_cpu_vsr(xT(ctx->opcode), xth, true); set_cpu_vsr(xT(ctx->opcode), xtl, false); - - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xbl); } =20 #define VSX_LOGICAL(name, vece, tcg_op) \ @@ -1813,11 +1653,6 @@ static void glue(gen_, name)(DisasContext *ctx) = \ set_cpu_vsr(xT(ctx->opcode), tmp, true); \ tcg_gen_deposit_i64(tmp, b1, a1, 32, 32); \ set_cpu_vsr(xT(ctx->opcode), tmp, false); \ - tcg_temp_free_i64(a0); \ - tcg_temp_free_i64(a1); \ - tcg_temp_free_i64(b0); \ - tcg_temp_free_i64(b1); \ - tcg_temp_free_i64(tmp); \ } =20 VSX_XXMRG(xxmrghw, 1) @@ -1974,13 +1809,6 @@ static bool trans_XVTLSBB(DisasContext *ctx, arg_XX2= _bf_xb *a) =20 tcg_gen_or_i64(t0, all_false, all_true); tcg_gen_extrl_i64_i32(cpu_crf[a->bf], t0); - - tcg_temp_free_i64(xb); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(all_true); - tcg_temp_free_i64(all_false); - return true; } =20 @@ -2012,7 +1840,6 @@ static void gen_xxsldwi(DisasContext *ctx) get_cpu_vsr(t0, xB(ctx->opcode), true); tcg_gen_shri_i64(t0, t0, 32); tcg_gen_or_i64(xtl, xtl, t0); - tcg_temp_free_i64(t0); break; } case 2: { @@ -2032,16 +1859,12 @@ static void gen_xxsldwi(DisasContext *ctx) get_cpu_vsr(t0, xB(ctx->opcode), false); tcg_gen_shri_i64(t0, t0, 32); tcg_gen_or_i64(xtl, xtl, t0); - tcg_temp_free_i64(t0); break; } } =20 set_cpu_vsr(xT(ctx->opcode), xth, true); set_cpu_vsr(xT(ctx->opcode), xtl, false); - - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); } =20 static bool do_vsx_extract_insert(DisasContext *ctx, arg_XX2_uim *a, @@ -2064,10 +1887,7 @@ static bool do_vsx_extract_insert(DisasContext *ctx,= arg_XX2_uim *a, xt =3D gen_vsr_ptr(a->xt); xb =3D gen_vsr_ptr(a->xb); gen_helper(xt, xb, tcg_constant_i32(a->uim)); - tcg_temp_free_ptr(xb); - tcg_temp_free_ptr(xt); } - return true; } =20 @@ -2086,7 +1906,6 @@ static void gen_xsxexpdp(DisasContext *ctx) t0 =3D tcg_temp_new_i64(); get_cpu_vsr(t0, xB(ctx->opcode), true); tcg_gen_extract_i64(rt, t0, 52, 11); - tcg_temp_free_i64(t0); } =20 static void gen_xsxexpqp(DisasContext *ctx) @@ -2108,10 +1927,6 @@ static void gen_xsxexpqp(DisasContext *ctx) set_cpu_vsr(rD(ctx->opcode) + 32, xth, true); tcg_gen_movi_i64(xtl, 0); set_cpu_vsr(rD(ctx->opcode) + 32, xtl, false); - - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); } =20 static void gen_xsiexpdp(DisasContext *ctx) @@ -2133,8 +1948,6 @@ static void gen_xsiexpdp(DisasContext *ctx) tcg_gen_or_i64(xth, xth, t0); set_cpu_vsr(xT(ctx->opcode), xth, true); set_cpu_vsr(xT(ctx->opcode), tcg_constant_i64(0), false); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(xth); } =20 static void gen_xsiexpqp(DisasContext *ctx) @@ -2167,13 +1980,6 @@ static void gen_xsiexpqp(DisasContext *ctx) set_cpu_vsr(rD(ctx->opcode) + 32, xth, true); tcg_gen_mov_i64(xtl, xal); set_cpu_vsr(rD(ctx->opcode) + 32, xtl, false); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xah); - tcg_temp_free_i64(xal); - tcg_temp_free_i64(xbh); } =20 static void gen_xsxsigdp(DisasContext *ctx) @@ -2198,12 +2004,6 @@ static void gen_xsxsigdp(DisasContext *ctx) tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); get_cpu_vsr(t1, xB(ctx->opcode), true); tcg_gen_deposit_i64(rt, t0, t1, 0, 52); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(exp); - tcg_temp_free_i64(zr); - tcg_temp_free_i64(nan); } =20 static void gen_xsxsigqp(DisasContext *ctx) @@ -2237,15 +2037,6 @@ static void gen_xsxsigqp(DisasContext *ctx) set_cpu_vsr(rD(ctx->opcode) + 32, xth, true); tcg_gen_mov_i64(xtl, xbl); set_cpu_vsr(rD(ctx->opcode) + 32, xtl, false); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(exp); - tcg_temp_free_i64(zr); - tcg_temp_free_i64(nan); - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xbl); } #endif =20 @@ -2285,14 +2076,6 @@ static void gen_xviexpsp(DisasContext *ctx) tcg_gen_shli_i64(t0, t0, 23); tcg_gen_or_i64(xtl, xtl, t0); set_cpu_vsr(xT(ctx->opcode), xtl, false); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xah); - tcg_temp_free_i64(xal); - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xbl); } =20 static void gen_xviexpdp(DisasContext *ctx) @@ -2324,13 +2107,6 @@ static void gen_xviexpdp(DisasContext *ctx) =20 tcg_gen_deposit_i64(xtl, xal, xbl, 52, 11); set_cpu_vsr(xT(ctx->opcode), xtl, false); - - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xah); - tcg_temp_free_i64(xal); - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xbl); } =20 static void gen_xvxexpsp(DisasContext *ctx) @@ -2357,11 +2133,6 @@ static void gen_xvxexpsp(DisasContext *ctx) tcg_gen_shri_i64(xtl, xbl, 23); tcg_gen_andi_i64(xtl, xtl, 0xFF000000FF); set_cpu_vsr(xT(ctx->opcode), xtl, false); - - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xbl); } =20 static void gen_xvxexpdp(DisasContext *ctx) @@ -2386,11 +2157,6 @@ static void gen_xvxexpdp(DisasContext *ctx) set_cpu_vsr(xT(ctx->opcode), xth, true); tcg_gen_extract_i64(xtl, xbl, 52, 11); set_cpu_vsr(xT(ctx->opcode), xtl, false); - - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xbl); } =20 static bool trans_XVXSIGSP(DisasContext *ctx, arg_XX2 *a) @@ -2404,10 +2170,6 @@ static bool trans_XVXSIGSP(DisasContext *ctx, arg_XX= 2 *a) b =3D gen_vsr_ptr(a->xb); =20 gen_helper_XVXSIGSP(t, b); - - tcg_temp_free_ptr(t); - tcg_temp_free_ptr(b); - return true; } =20 @@ -2447,15 +2209,6 @@ static void gen_xvxsigdp(DisasContext *ctx) tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); tcg_gen_deposit_i64(xtl, t0, xbl, 0, 52); set_cpu_vsr(xT(ctx->opcode), xtl, false); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(exp); - tcg_temp_free_i64(zr); - tcg_temp_free_i64(nan); - tcg_temp_free_i64(xth); - tcg_temp_free_i64(xtl); - tcg_temp_free_i64(xbh); - tcg_temp_free_i64(xbl); } =20 static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ, @@ -2510,9 +2263,6 @@ static bool do_lstxv(DisasContext *ctx, int ra, TCGv = displ, set_cpu_vsr(rt2, xt, ctx->le_mode); } } - - tcg_temp_free(ea); - tcg_temp_free_i64(xt); return true; } =20 @@ -2577,10 +2327,6 @@ static bool do_lstxsd(DisasContext *ctx, int rt, int= ra, TCGv displ, bool store) set_cpu_vsr(rt + 32, xt, true); set_cpu_vsr(rt + 32, tcg_constant_i64(0), false); } - - tcg_temp_free(ea); - tcg_temp_free_i64(xt); - return true; } =20 @@ -2620,10 +2366,6 @@ static bool do_lstxssp(DisasContext *ctx, int rt, in= t ra, TCGv displ, bool store set_cpu_vsr(rt + 32, xt, true); set_cpu_vsr(rt + 32, tcg_constant_i64(0), false); } - - tcg_temp_free(ea); - tcg_temp_free_i64(xt); - return true; } =20 @@ -2684,9 +2426,6 @@ static bool do_lstrm(DisasContext *ctx, arg_X *a, Mem= Op mop, bool store) set_cpu_vsr(a->rt, xt, false); set_cpu_vsr(a->rt, tcg_constant_i64(0), true); } - - tcg_temp_free(ea); - tcg_temp_free_i64(xt); return true; } =20 @@ -2741,9 +2480,6 @@ static void gen_xxeval_i64(TCGv_i64 t, TCGv_i64 a, TC= Gv_i64 b, TCGv_i64 c, } =20 tcg_gen_mov_i64(t, disj); - - tcg_temp_free_i64(conj); - tcg_temp_free_i64(disj); } =20 static void gen_xxeval_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec= b, @@ -2788,9 +2524,6 @@ static void gen_xxeval_vec(unsigned vece, TCGv_vec t,= TCGv_vec a, TCGv_vec b, } =20 tcg_gen_mov_vec(t, disj); - - tcg_temp_free_vec(disj); - tcg_temp_free_vec(conj); } =20 static bool trans_XXEVAL(DisasContext *ctx, arg_8RR_XX4_imm *a) @@ -2925,7 +2658,6 @@ static void gen_xxblendv_vec(unsigned vece, TCGv_vec = t, TCGv_vec a, TCGv_vec b, TCGv_vec tmp =3D tcg_temp_new_vec_matching(c); tcg_gen_sari_vec(vece, tmp, c, (8 << vece) - 1); tcg_gen_bitsel_vec(vece, t, tmp, b, a); - tcg_temp_free_vec(tmp); } =20 static bool do_xxblendv(DisasContext *ctx, arg_8RR_XX4 *a, unsigned vece) @@ -2987,11 +2719,6 @@ static bool do_helper_XX3(DisasContext *ctx, arg_XX3= *a, xb =3D gen_vsr_ptr(a->xb); =20 helper(cpu_env, xt, xa, xb); - - tcg_temp_free_ptr(xt); - tcg_temp_free_ptr(xa); - tcg_temp_free_ptr(xb); - return true; } =20 @@ -3013,11 +2740,6 @@ static bool do_helper_X(arg_X *a, rb =3D gen_avr_ptr(a->rb); =20 helper(cpu_env, rt, ra, rb); - - tcg_temp_free_ptr(rt); - tcg_temp_free_ptr(ra); - tcg_temp_free_ptr(rb); - return true; } =20 @@ -3047,10 +2769,6 @@ static bool trans_XVCVSPBF16(DisasContext *ctx, arg_= XX2 *a) xb =3D gen_vsr_ptr(a->xb); =20 gen_helper_XVCVSPBF16(cpu_env, xt, xb); - - tcg_temp_free_ptr(xt); - tcg_temp_free_ptr(xb); - return true; } =20 @@ -3114,9 +2832,6 @@ static bool do_ger(DisasContext *ctx, arg_MMIRR_XX3 *= a, =20 mask =3D ger_pack_masks(a->pmsk, a->ymsk, a->xmsk); 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.30.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:30:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jXzb0wguddcKP79wDFGGeUAakOtFrc7V197g1pVsdMU=; b=LR3Mov5ufwrZg1ODnQVmMK4M0FtsCmAzOG1+uiLQNlDF4J9efiw6Bi3CcRDaki5huj PVO32AD78ep8HoEVCBENqpEDpwKlNO3+U9e3GTR3pp8nqcWeMD7T0v7fDrC1o89b2zgz Zd5oou/HAfJBG/Qe1laK0Mv2RWA02WxTvAC6nPYQ+koh/fkE40gFIhwj/utfgsRVJAZz JMNLhqQOG9eOFlJgth5EdpxKaQLjOgnOmcKKPJx3DV+ItJsUVK5LxgItISB/n59i0f/V PmfQzM1yrui3XydvKN/KeK5yQTwAR8WemDHcCK3taQFO4vKa3JznZGceie9l6MigzuWu 7E8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jXzb0wguddcKP79wDFGGeUAakOtFrc7V197g1pVsdMU=; b=V8gqxI+paMK6ISMzTmxLiGXTXMv5vwl2+hlFY22CbfXT7eXKvq/NojDojoQWw+ybfK Yw33tB2XbbdrSA351Pnl39uQmzHH274PhymlRWWKO7vzt3V4YRn/3ZMcK+k0WZ5tVG+z zEjZOOx05UOMU7io17VXzbH97eXvuXPN6kOWLg7UTaWWT6yPcDaXVVxBfbYc59HRtoA9 CBJhFdmywD1HT98ZD2T1Gr/Vt1qxSesZYJDhyh25X6Qy87sstKkxdkSieTMH/XGILD5J 3wylpwR5wED92AP4A6kXKp7yXFmN3LWfs7i13pAFxMVWG1h19Gps1pC9jjtse40NBVaP c+YQ== X-Gm-Message-State: AO0yUKXCEI/FCC5sRhImnGWfaIbA4XGrWPNQIeWrtT+UtFg7Y0rXDKzo F6wp8yzd3wxQqz99iW2eWlrq8RUQs43UsBmQgGZFEQ== X-Google-Smtp-Source: AK7set+2cybHq0gFkCel5osP8mALq0PJdKb84YjeQSa6Wwycr61rAL6sPvJbfGbb/k6rlaDJyygzHg== X-Received: by 2002:a17:90b:350f:b0:234:86a5:f800 with SMTP id ls15-20020a17090b350f00b0023486a5f800mr25701915pjb.34.1677475832967; Sun, 26 Feb 2023 21:30:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com, Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v2 51/76] target/riscv: Drop ftemp_new Date: Sun, 26 Feb 2023 19:24:40 -1000 Message-Id: <20230227052505.352889-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677485575772100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries, therefore there's no need to record temps for later freeing. Replace the few uses with tcg_temp_new_i64. Reviewed-by: Weiwei Li Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/riscv/translate.c | 24 ++++-------------------- 1 file changed, 4 insertions(+), 20 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f9d5d1097e..273e566d66 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -106,9 +106,6 @@ typedef struct DisasContext { TCGv zero; /* Space for 3 operands plus 1 extra for address computation. */ TCGv temp[4]; - /* Space for 4 operands(1 dest and <=3D3 src) for float point computat= ion */ - TCGv_i64 ftemp[4]; - uint8_t nftemp; /* PointerMasking extension */ bool pm_mask_enabled; bool pm_base_enabled; @@ -431,12 +428,6 @@ static void gen_set_gpr128(DisasContext *ctx, int reg_= num, TCGv rl, TCGv rh) } } =20 -static TCGv_i64 ftemp_new(DisasContext *ctx) -{ - assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp)); - return ctx->ftemp[ctx->nftemp++] =3D tcg_temp_new_i64(); -} - static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) { if (!ctx->cfg_ptr->ext_zfinx) { @@ -450,7 +441,7 @@ static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_n= um) case MXL_RV32: #ifdef TARGET_RISCV32 { - TCGv_i64 t =3D ftemp_new(ctx); + TCGv_i64 t =3D tcg_temp_new_i64(); tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); return t; } @@ -476,7 +467,7 @@ static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_nu= m) switch (get_xl(ctx)) { case MXL_RV32: { - TCGv_i64 t =3D ftemp_new(ctx); + TCGv_i64 t =3D tcg_temp_new_i64(); tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); return t; } @@ -496,12 +487,12 @@ static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_n= um) } =20 if (reg_num =3D=3D 0) { - return ftemp_new(ctx); + return tcg_temp_new_i64(); } =20 switch (get_xl(ctx)) { case MXL_RV32: - return ftemp_new(ctx); + return tcg_temp_new_i64(); #ifdef TARGET_RISCV64 case MXL_RV64: return cpu_gpr[reg_num]; @@ -1207,8 +1198,6 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->cs =3D cs; ctx->ntemp =3D 0; memset(ctx->temp, 0, sizeof(ctx->temp)); - ctx->nftemp =3D 0; - memset(ctx->ftemp, 0, sizeof(ctx->ftemp)); ctx->pm_mask_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLE= D); ctx->pm_base_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLE= D); ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); @@ -1244,11 +1233,6 @@ static void riscv_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cpu) ctx->temp[i] =3D NULL; } ctx->ntemp =3D 0; - for (i =3D ctx->nftemp - 1; i >=3D 0; --i) { - tcg_temp_free_i64(ctx->ftemp[i]); - ctx->ftemp[i] =3D NULL; - } - ctx->nftemp =3D 0; =20 /* Only the first insn within a TB is allowed to cross a page boundary= . */ if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677476150; cv=none; d=zohomail.com; s=zohoarc; b=LkJg7udWR15AEwozciZIyHMKZp15Xr4atJVvT2rKh/bTc9IKoyGNOEJsG6Zo/Smf/G812dnTvtz98n8LzlTxCfSeXJ+E29hHDUJDCmwkGnGshTeIjiJoUy74XVX3j6bnp4xrR4wkPEQNnCnMfL7q4YJCwFSxBPTmDZVykEFAFqA= ARC-Message-Signature: i=1; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.30.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:30:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oKFoOtAQPc4IGDzDI3M0u00e6r6YXRrZmZGvxqeOd94=; b=jP7z65h+OG1mIkfpq/kYCDUlGEMYvKJzAHc1NJZCmjd2FUtZxitdmtjYlLkVmy0ZGD IcLBxmvuSZyXBAsZp/kzBBNuVT7hWME3cwy4ezTqW2UGB0rl2cr2EkcAcmGif77aBipV KRRLFNpYIj6zTBgVplZGAXSXm/0zg78sowevW8pi8iUCfrE7rx24JBkY/ryezWASaVfq DUYqPF6ydaROCfa2H+9XQUEotWSXiRpZSehBUAL+hgoEblwNdURb++Z2mQ7jhcaltwJ+ Zy64OYSxy2PTKMASC+i56hHHAE3EMIwWUtfCpz1jO+MXqJgD0OtRhFtKT27IaujIAd4d 9q7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oKFoOtAQPc4IGDzDI3M0u00e6r6YXRrZmZGvxqeOd94=; b=hhBwqlkMwWvBq8Ve97Mns3Nz1zdCj0aAUwOqPlVNEHHwjkUvjpfRbhQtzMi+ynv01v jnlSMid5AwE/FkV/s5tE/Nm07vAktqQ41h8NY53lxnVTkUhPU81gUGqTlrDimi19ADCT V5jv3k5W8B7KqocNNkFn4WC38a42U/L4Rg6RpKEIZ/hHgySkwMoEdo4adSgTNoyPVPUy HR/5TSEhKU4wpih5aTh0+nADgN+elizidTtw1TweXhaGRhaPs1+EXzm48CQfDA4ISsAl Pn4sqG6K5eEOwLGSw3ZaDXYEw/Vx0b57F6/ZDBvmZWx0yR2tcSnROgvm0J11TfmhW4Pu nvJA== X-Gm-Message-State: AO0yUKXyuAdUouoAwjDVQFChLIo9+Jvc7VeMhb0zzhZMTRHKom+p391t 8LX95fIDy/rD39qeRnOWWRxYHreStjgkVESbDQYnPw== X-Google-Smtp-Source: AK7set9xcOodI6lGwDyuhO7RbFr83Q/tWSDh0yGRTDF5LcH9Djiv2D/O5BmhNwo2PcLUN+slu9ofww== X-Received: by 2002:a17:90b:17c5:b0:236:6a28:f783 with SMTP id me5-20020a17090b17c500b002366a28f783mr8251860pjb.15.1677475835979; Sun, 26 Feb 2023 21:30:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com, Weiwei Li , Daniel Henrique Barboza Subject: [PATCH v2 52/76] target/riscv: Drop temp_new Date: Sun, 26 Feb 2023 19:24:41 -1000 Message-Id: <20230227052505.352889-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476153062100003 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries, therefore there's no need to record temps for later freeing. Replace the few uses with tcg_temp_new. Reviewed-by: Weiwei Li Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/riscv/translate.c | 30 +++++------------------ target/riscv/insn_trans/trans_rvzfh.c.inc | 2 +- 2 files changed, 7 insertions(+), 25 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 273e566d66..b5d8080a6f 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -101,11 +101,8 @@ typedef struct DisasContext { bool cfg_vta_all_1s; target_ulong vstart; bool vl_eq_vlmax; - uint8_t ntemp; CPUState *cs; TCGv zero; - /* Space for 3 operands plus 1 extra for address computation. */ - TCGv temp[4]; /* PointerMasking extension */ bool pm_mask_enabled; bool pm_base_enabled; @@ -312,12 +309,6 @@ static void gen_goto_tb(DisasContext *ctx, int n, targ= et_ulong dest) * * Further, we may provide an extension for word operations. */ -static TCGv temp_new(DisasContext *ctx) -{ - assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); - return ctx->temp[ctx->ntemp++] =3D tcg_temp_new(); -} - static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) { TCGv t; @@ -332,11 +323,11 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, D= isasExtend ext) case EXT_NONE: break; case EXT_SIGN: - t =3D temp_new(ctx); + t =3D tcg_temp_new(); tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); return t; case EXT_ZERO: - t =3D temp_new(ctx); + t =3D tcg_temp_new(); tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); return t; default: @@ -364,7 +355,7 @@ static TCGv get_gprh(DisasContext *ctx, int reg_num) static TCGv dest_gpr(DisasContext *ctx, int reg_num) { if (reg_num =3D=3D 0 || get_olen(ctx) < TARGET_LONG_BITS) { - return temp_new(ctx); + return tcg_temp_new(); } return cpu_gpr[reg_num]; } @@ -372,7 +363,7 @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num) static TCGv dest_gprh(DisasContext *ctx, int reg_num) { if (reg_num =3D=3D 0) { - return temp_new(ctx); + return tcg_temp_new(); } return cpu_gprh[reg_num]; } @@ -575,7 +566,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_u= long imm) /* Compute a canonical address from a register plus offset. */ static TCGv get_address(DisasContext *ctx, int rs1, int imm) { - TCGv addr =3D temp_new(ctx); + TCGv addr =3D tcg_temp_new(); TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); =20 tcg_gen_addi_tl(addr, src1, imm); @@ -593,7 +584,7 @@ static TCGv get_address(DisasContext *ctx, int rs1, int= imm) /* Compute a canonical address from a register plus reg offset. */ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) { - TCGv addr =3D temp_new(ctx); + TCGv addr =3D tcg_temp_new(); TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); =20 tcg_gen_add_tl(addr, src1, offs); @@ -1196,8 +1187,6 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->misa_mxl_max =3D env->misa_mxl_max; ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->cs =3D cs; - ctx->ntemp =3D 0; - memset(ctx->temp, 0, sizeof(ctx->temp)); ctx->pm_mask_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLE= D); ctx->pm_base_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLE= D); ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); @@ -1222,18 +1211,11 @@ static void riscv_tr_translate_insn(DisasContextBas= e *dcbase, CPUState *cpu) DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPURISCVState *env =3D cpu->env_ptr; uint16_t opcode16 =3D translator_lduw(env, &ctx->base, ctx->base.pc_ne= xt); - int i; =20 ctx->ol =3D ctx->xl; decode_opc(env, ctx, opcode16); ctx->base.pc_next =3D ctx->pc_succ_insn; =20 - for (i =3D ctx->ntemp - 1; i >=3D 0; --i) { - tcg_temp_free(ctx->temp[i]); - ctx->temp[i] =3D NULL; - } - ctx->ntemp =3D 0; - /* Only the first insn within a TB is allowed to cross a page boundary= . */ if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next))= { diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_= trans/trans_rvzfh.c.inc index 2ad5716312..5024e6ecab 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -52,7 +52,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a) decode_save_opc(ctx); t0 =3D get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { - TCGv temp =3D temp_new(ctx); + TCGv temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, t0, a->imm); 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Reviewed-by: Weiwei Li Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/riscv/translate.c | 7 --- target/riscv/insn_trans/trans_rvb.c.inc | 24 ---------- target/riscv/insn_trans/trans_rvd.c.inc | 2 - target/riscv/insn_trans/trans_rvf.c.inc | 9 ---- target/riscv/insn_trans/trans_rvi.c.inc | 37 --------------- target/riscv/insn_trans/trans_rvk.c.inc | 15 ------ target/riscv/insn_trans/trans_rvm.c.inc | 33 ------------- target/riscv/insn_trans/trans_rvv.c.inc | 55 ---------------------- target/riscv/insn_trans/trans_rvzfh.c.inc | 10 ---- target/riscv/insn_trans/trans_xthead.c.inc | 24 +--------- 10 files changed, 1 insertion(+), 215 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b5d8080a6f..180fa5d30d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -205,8 +205,6 @@ static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 i= n) TCGv_i64 t_nan =3D tcg_const_i64(0xffffffffffff7e00ull); =20 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); - tcg_temp_free_i64(t_max); - tcg_temp_free_i64(t_nan); } =20 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) @@ -621,7 +619,6 @@ static void mark_fs_dirty(DisasContext *ctx) tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); - tcg_temp_free(tmp); } =20 if (ctx->virt_enabled && ctx->mstatus_hs_fs !=3D MSTATUS_FS) { @@ -632,7 +629,6 @@ static void mark_fs_dirty(DisasContext *ctx) tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); - tcg_temp_free(tmp); } } #else @@ -657,7 +653,6 @@ static void mark_vs_dirty(DisasContext *ctx) tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); - tcg_temp_free(tmp); } =20 if (ctx->virt_enabled && ctx->mstatus_hs_vs !=3D MSTATUS_VS) { @@ -668,7 +663,6 @@ static void mark_vs_dirty(DisasContext *ctx) tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); - tcg_temp_free(tmp); } } #else @@ -1019,7 +1013,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, Di= sasExtend ext, f128(dest, desth, src1, src1h, ext2); gen_set_gpr128(ctx, a->rd, dest, desth); } - tcg_temp_free(ext2); return true; } =20 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 990bc94b98..e4dcc7c991 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -64,7 +64,6 @@ static void gen_clzw(TCGv ret, TCGv arg1) TCGv t =3D tcg_temp_new(); tcg_gen_shli_tl(t, arg1, 32); tcg_gen_clzi_tl(ret, t, 32); - tcg_temp_free(t); } =20 static bool trans_clz(DisasContext *ctx, arg_clz *a) @@ -161,8 +160,6 @@ static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt) =20 gen_sbop_mask(t, shamt); tcg_gen_or_tl(ret, arg1, t); - - tcg_temp_free(t); } =20 static bool trans_bset(DisasContext *ctx, arg_bset *a) @@ -183,8 +180,6 @@ static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt) =20 gen_sbop_mask(t, shamt); tcg_gen_andc_tl(ret, arg1, t); - - tcg_temp_free(t); } =20 static bool trans_bclr(DisasContext *ctx, arg_bclr *a) @@ -205,8 +200,6 @@ static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt) =20 gen_sbop_mask(t, shamt); tcg_gen_xor_tl(ret, arg1, t); - - tcg_temp_free(t); } =20 static bool trans_binv(DisasContext *ctx, arg_binv *a) @@ -252,9 +245,6 @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) =20 /* sign-extend 64-bits */ tcg_gen_ext_i32_tl(ret, t1); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); } =20 static bool trans_ror(DisasContext *ctx, arg_ror *a) @@ -270,8 +260,6 @@ static void gen_roriw(TCGv ret, TCGv arg1, target_long = shamt) tcg_gen_trunc_tl_i32(t1, arg1); tcg_gen_rotri_i32(t1, t1, shamt); tcg_gen_ext_i32_tl(ret, t1); - - tcg_temp_free_i32(t1); } =20 static bool trans_rori(DisasContext *ctx, arg_rori *a) @@ -294,9 +282,6 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) =20 /* sign-extend 64-bits */ tcg_gen_ext_i32_tl(ret, t1); - - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); } =20 static bool trans_rol(DisasContext *ctx, arg_rol *a) @@ -340,8 +325,6 @@ static void gen_orc_b(TCGv ret, TCGv source1) =20 /* Replicate the lsb of each byte across the byte. */ tcg_gen_muli_tl(ret, tmp, 0xff); - - tcg_temp_free(tmp); } =20 static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a) @@ -357,8 +340,6 @@ static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCG= v arg2) \ \ tcg_gen_shli_tl(t, arg1, SHAMT); \ tcg_gen_add_tl(ret, t, arg2); \ - \ - tcg_temp_free(t); \ } =20 GEN_SHADD(1) @@ -446,8 +427,6 @@ static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, = TCGv arg2) \ \ tcg_gen_shli_tl(t, t, SHAMT); \ tcg_gen_add_tl(ret, t, arg2); \ - \ - tcg_temp_free(t); \ } =20 GEN_SHADD_UW(1) @@ -472,7 +451,6 @@ static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2) TCGv t =3D tcg_temp_new(); tcg_gen_ext32u_tl(t, arg1); tcg_gen_add_tl(ret, t, arg2); - tcg_temp_free(t); } =20 static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a) @@ -531,7 +509,6 @@ static void gen_packh(TCGv ret, TCGv src1, TCGv src2) =20 tcg_gen_ext8u_tl(t, src2); tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8); - tcg_temp_free(t); } =20 static void gen_packw(TCGv ret, TCGv src1, TCGv src2) @@ -540,7 +517,6 @@ static void gen_packw(TCGv ret, TCGv src1, TCGv src2) =20 tcg_gen_ext16s_tl(t, src2); tcg_gen_deposit_tl(ret, src1, t, 16, TARGET_LONG_BITS - 16); - tcg_temp_free(t); } =20 static bool trans_brev8(DisasContext *ctx, arg_brev8 *a) diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 6e3159b797..1597bf31d8 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -250,7 +250,6 @@ static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnj= n_d *a) TCGv_i64 t0 =3D tcg_temp_new_i64(); tcg_gen_not_i64(t0, src2); tcg_gen_deposit_i64(dest, t0, src1, 0, 63); - tcg_temp_free_i64(t0); } gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); @@ -273,7 +272,6 @@ static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnj= x_d *a) TCGv_i64 t0 =3D tcg_temp_new_i64(); tcg_gen_andi_i64(t0, src2, INT64_MIN); tcg_gen_xor_i64(dest, src1, t0); - tcg_temp_free_i64(t0); } gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index 965e1f8d11..052408f45c 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -233,9 +233,6 @@ static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_= s *a) =20 /* This formulation retains the nanboxing of rs2 in normal 'F'= . */ tcg_gen_deposit_i64(dest, rs2, rs1, 0, 31); - - tcg_temp_free_i64(rs1); - tcg_temp_free_i64(rs2); } else { tcg_gen_deposit_i64(dest, src2, src1, 0, 31); tcg_gen_ext32s_i64(dest, dest); @@ -281,15 +278,12 @@ static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsg= njn_s *a) tcg_gen_nor_i64(rs2, rs2, mask); tcg_gen_and_i64(dest, mask, rs1); tcg_gen_or_i64(dest, dest, rs2); - - tcg_temp_free_i64(rs2); } /* signed-extended intead of nanboxing for result if enable zfinx */ if (ctx->cfg_ptr->ext_zfinx) { tcg_gen_ext32s_i64(dest, dest); } gen_set_fpr_hs(ctx, a->rd, dest); - tcg_temp_free_i64(rs1); mark_fs_dirty(ctx); return true; } @@ -329,14 +323,11 @@ static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsg= njx_s *a) */ tcg_gen_andi_i64(dest, rs2, MAKE_64BIT_MASK(31, 1)); tcg_gen_xor_i64(dest, rs1, dest); - - tcg_temp_free_i64(rs2); } /* signed-extended intead of nanboxing for result if enable zfinx */ if (ctx->cfg_ptr->ext_zfinx) { tcg_gen_ext32s_i64(dest, dest); } - tcg_temp_free_i64(rs1); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 4496f21266..4ad54e8a49 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -62,7 +62,6 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) misaligned =3D gen_new_label(); tcg_gen_andi_tl(t0, cpu_pc, 0x2); tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned); - tcg_temp_free(t0); } =20 gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn); @@ -108,8 +107,6 @@ static TCGCond gen_compare_i128(bool bz, TCGv rl, tcg_gen_xor_tl(tmp, ah, bh); tcg_gen_and_tl(rl, rl, tmp); tcg_gen_xor_tl(rl, rh, rl); - - tcg_temp_free(tmp); } break; =20 @@ -128,8 +125,6 @@ static TCGCond gen_compare_i128(bool bz, TCGv rl, /* seed third word with 1, which will be result */ tcg_gen_sub2_tl(tmp, rh, ah, one, tmp, zero); tcg_gen_sub2_tl(tmp, rl, tmp, rh, bh, zero); - - tcg_temp_free(tmp); } break; =20 @@ -140,8 +135,6 @@ static TCGCond gen_compare_i128(bool bz, TCGv rl, if (invert) { cond =3D tcg_invert_cond(cond); } - - tcg_temp_free(rh); return cond; } =20 @@ -169,8 +162,6 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCG= Cond cond) cond =3D gen_compare_i128(a->rs2 =3D=3D 0, tmp, src1, src1h, src2, src2h, cond); tcg_gen_brcondi_tl(cond, tmp, 0, l); - - tcg_temp_free(tmp); } else { tcg_gen_brcond_tl(cond, src1, src2, l); } @@ -254,8 +245,6 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a,= MemOp memop) } =20 gen_set_gpr128(ctx, a->rd, destl, desth); - - tcg_temp_free(addrl); return true; } =20 @@ -344,8 +333,6 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a= , MemOp memop) tcg_gen_addi_tl(addrl, addrl, 8); tcg_gen_qemu_st_tl(src2h, addrl, ctx->mem_idx, MO_TEUQ); } - - tcg_temp_free(addrl); return true; } =20 @@ -568,14 +555,6 @@ static void gen_sll_i128(TCGv destl, TCGv desth, =20 tcg_gen_movcond_tl(TCG_COND_NE, destl, hs, zero, zero, ll); tcg_gen_movcond_tl(TCG_COND_NE, desth, hs, zero, ll, h1); - - tcg_temp_free(ls); - tcg_temp_free(rs); - tcg_temp_free(hs); - tcg_temp_free(ll); - tcg_temp_free(lr); - tcg_temp_free(h0); - tcg_temp_free(h1); } =20 static bool trans_sll(DisasContext *ctx, arg_sll *a) @@ -618,14 +597,6 @@ static void gen_srl_i128(TCGv destl, TCGv desth, =20 tcg_gen_movcond_tl(TCG_COND_NE, destl, hs, zero, h1, h0); tcg_gen_movcond_tl(TCG_COND_NE, desth, hs, zero, zero, h1); - - tcg_temp_free(ls); - tcg_temp_free(rs); - tcg_temp_free(hs); - tcg_temp_free(ll); - tcg_temp_free(lr); - tcg_temp_free(h0); - tcg_temp_free(h1); } =20 static bool trans_srl(DisasContext *ctx, arg_srl *a) @@ -659,14 +630,6 @@ static void gen_sra_i128(TCGv destl, TCGv desth, =20 tcg_gen_movcond_tl(TCG_COND_NE, destl, hs, zero, h1, h0); tcg_gen_movcond_tl(TCG_COND_NE, desth, hs, zero, lr, h1); - - tcg_temp_free(ls); - tcg_temp_free(rs); - tcg_temp_free(hs); - tcg_temp_free(ll); - tcg_temp_free(lr); - tcg_temp_free(h0); - tcg_temp_free(h1); } =20 static bool trans_sra(DisasContext *ctx, arg_sra *a) diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_tr= ans/trans_rvk.c.inc index 90f4eeff60..6600c710a7 100644 --- a/target/riscv/insn_trans/trans_rvk.c.inc +++ b/target/riscv/insn_trans/trans_rvk.c.inc @@ -161,9 +161,6 @@ static bool gen_sha256(DisasContext *ctx, arg_r2 *a, Di= sasExtend ext, tcg_gen_ext_i32_tl(dest, t1); =20 gen_set_gpr(ctx, a->rd, dest); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); return true; } =20 @@ -212,9 +209,6 @@ static bool gen_sha512_rv32(DisasContext *ctx, arg_r *a= , DisasExtend ext, tcg_gen_trunc_i64_tl(dest, t1); =20 gen_set_gpr(ctx, a->rd, dest); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); return true; } =20 @@ -271,9 +265,6 @@ static bool gen_sha512h_rv32(DisasContext *ctx, arg_r *= a, DisasExtend ext, tcg_gen_trunc_i64_tl(dest, t1); =20 gen_set_gpr(ctx, a->rd, dest); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); return true; } =20 @@ -310,9 +301,6 @@ static bool gen_sha512_rv64(DisasContext *ctx, arg_r2 *= a, DisasExtend ext, tcg_gen_trunc_i64_tl(dest, t1); =20 gen_set_gpr(ctx, a->rd, dest); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); return true; } =20 @@ -359,9 +347,6 @@ static bool gen_sm3(DisasContext *ctx, arg_r2 *a, int32= _t b, int32_t c) tcg_gen_xor_i32(t1, t1, t0); tcg_gen_ext_i32_tl(dest, t1); gen_set_gpr(ctx, a->rd, dest); - - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); return true; } =20 diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_tr= ans/trans_rvm.c.inc index ec7f705aab..2f0fd1f700 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -45,9 +45,6 @@ static void gen_mulhu_i128(TCGv r2, TCGv r3, TCGv al, TCG= v ah, TCGv bl, TCGv bh) =20 tcg_gen_mulu2_tl(tmpl, tmph, ah, bh); tcg_gen_add2_tl(r2, r3, r2, r3, tmpl, tmph); - - tcg_temp_free(tmpl); - tcg_temp_free(tmph); } =20 static void gen_mul_i128(TCGv rl, TCGv rh, @@ -63,10 +60,6 @@ static void gen_mul_i128(TCGv rl, TCGv rh, tcg_gen_add2_tl(rh, tmpx, rh, zero, tmpl, tmph); tcg_gen_mulu2_tl(tmpl, tmph, rs1h, rs2l); tcg_gen_add2_tl(rh, tmph, rh, tmpx, tmpl, tmph); - - tcg_temp_free(tmpl); - tcg_temp_free(tmph); - tcg_temp_free(tmpx); } =20 static bool trans_mul(DisasContext *ctx, arg_mul *a) @@ -92,11 +85,6 @@ static void gen_mulh_i128(TCGv rl, TCGv rh, tcg_gen_and_tl(t1h, t1h, rs1h); tcg_gen_sub2_tl(t0l, t0h, rl, rh, t0l, t0h); tcg_gen_sub2_tl(rl, rh, t0l, t0h, t1l, t1h); - - tcg_temp_free(t0l); - tcg_temp_free(t0h); - tcg_temp_free(t1l); - tcg_temp_free(t1h); } =20 static void gen_mulh(TCGv ret, TCGv s1, TCGv s2) @@ -104,7 +92,6 @@ static void gen_mulh(TCGv ret, TCGv s1, TCGv s2) TCGv discard =3D tcg_temp_new(); =20 tcg_gen_muls2_tl(discard, ret, s1, s2); - tcg_temp_free(discard); } =20 static void gen_mulh_w(TCGv ret, TCGv s1, TCGv s2) @@ -132,9 +119,6 @@ static void gen_mulhsu_i128(TCGv rl, TCGv rh, tcg_gen_and_tl(t0l, t0h, rs2l); tcg_gen_and_tl(t0h, t0h, rs2h); tcg_gen_sub2_tl(rl, rh, rl, rh, t0l, t0h); - - tcg_temp_free(t0l); - tcg_temp_free(t0h); } =20 static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) @@ -147,9 +131,6 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1); tcg_gen_and_tl(rl, rl, arg2); tcg_gen_sub_tl(ret, rh, rl); - - tcg_temp_free(rl); - tcg_temp_free(rh); } =20 static void gen_mulhsu_w(TCGv ret, TCGv arg1, TCGv arg2) @@ -160,8 +141,6 @@ static void gen_mulhsu_w(TCGv ret, TCGv arg1, TCGv arg2) tcg_gen_ext32s_tl(t1, arg1); tcg_gen_ext32u_tl(t2, arg2); tcg_gen_mul_tl(ret, t1, t2); - tcg_temp_free(t1); - tcg_temp_free(t2); tcg_gen_sari_tl(ret, ret, 32); } =20 @@ -177,7 +156,6 @@ static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2) TCGv discard =3D tcg_temp_new(); =20 tcg_gen_mulu2_tl(discard, ret, s1, s2); - tcg_temp_free(discard); } =20 static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) @@ -223,9 +201,6 @@ static void gen_div(TCGv ret, TCGv source1, TCGv source= 2) tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, temp2); =20 tcg_gen_div_tl(ret, temp1, temp2); - - tcg_temp_free(temp1); - tcg_temp_free(temp2); } =20 static bool trans_div(DisasContext *ctx, arg_div *a) @@ -258,9 +233,6 @@ static void gen_divu(TCGv ret, TCGv source1, TCGv sourc= e2) tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1); tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2); tcg_gen_divu_tl(ret, temp1, temp2); - - tcg_temp_free(temp1); - tcg_temp_free(temp2); } =20 static bool trans_divu(DisasContext *ctx, arg_divu *a) @@ -306,9 +278,6 @@ static void gen_rem(TCGv ret, TCGv source1, TCGv source= 2) =20 /* If div by zero, the required result is the original dividend. */ tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp1); - - tcg_temp_free(temp1); - tcg_temp_free(temp2); } =20 static bool trans_rem(DisasContext *ctx, arg_rem *a) @@ -342,8 +311,6 @@ static void gen_remu(TCGv ret, TCGv source1, TCGv sourc= e2) =20 /* If div by zero, the required result is the original dividend. */ tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp); - - tcg_temp_free(temp); } =20 static bool trans_remu(DisasContext *ctx, arg_remu *a) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index bbb5c3a7b5..0607eff5e6 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -198,11 +198,6 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1= , TCGv s2) gen_set_pc_imm(s, s->pc_succ_insn); lookup_and_goto_ptr(s); s->base.is_jmp =3D DISAS_NORETURN; - - if (rd =3D=3D 0 && rs1 =3D=3D 0) { - tcg_temp_free(s1); - } - return true; } =20 @@ -673,9 +668,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, ui= nt32_t data, =20 fn(dest, mask, base, cpu_env, desc); =20 - tcg_temp_free_ptr(dest); - tcg_temp_free_ptr(mask); - if (!is_store) { mark_vs_dirty(s); } @@ -838,9 +830,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1= , uint32_t rs2, =20 fn(dest, mask, base, stride, cpu_env, desc); =20 - tcg_temp_free_ptr(dest); - tcg_temp_free_ptr(mask); - if (!is_store) { mark_vs_dirty(s); } @@ -949,10 +938,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1= , uint32_t vs2, =20 fn(dest, mask, base, index, cpu_env, desc); =20 - tcg_temp_free_ptr(dest); - tcg_temp_free_ptr(mask); - tcg_temp_free_ptr(index); - if (!is_store) { mark_vs_dirty(s); } @@ -1092,8 +1077,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uin= t32_t data, =20 fn(dest, mask, base, cpu_env, desc); =20 - tcg_temp_free_ptr(dest); - tcg_temp_free_ptr(mask); mark_vs_dirty(s); gen_set_label(over); return true; @@ -1154,8 +1137,6 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs= 1, uint32_t nf, =20 fn(dest, base, cpu_env, desc); =20 - tcg_temp_free_ptr(dest); - if (!is_store) { mark_vs_dirty(s); } @@ -1311,9 +1292,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, uint32_t vm, =20 fn(dest, mask, src1, src2, cpu_env, desc); =20 - tcg_temp_free_ptr(dest); - tcg_temp_free_ptr(mask); - tcg_temp_free_ptr(src2); mark_vs_dirty(s); gen_set_label(over); return true; @@ -1344,7 +1322,6 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2s= Fn *gvec_fn, gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), src1, MAXSZ(s), MAXSZ(s)); =20 - tcg_temp_free_i64(src1); mark_vs_dirty(s); return true; } @@ -1479,9 +1456,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, ui= nt32_t vs2, uint32_t vm, =20 fn(dest, mask, src1, src2, cpu_env, desc); =20 - tcg_temp_free_ptr(dest); - tcg_temp_free_ptr(mask); - tcg_temp_free_ptr(src2); mark_vs_dirty(s); gen_set_label(over); return true; @@ -1850,7 +1824,6 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVe= cGen2sFn32 *gvec_fn, gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), src1, MAXSZ(s), MAXSZ(s)); =20 - tcg_temp_free_i32(src1); mark_vs_dirty(s); return true; } @@ -2145,7 +2118,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_= x *a) tcg_gen_ext_tl_i64(s1_i64, s1); tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), s1_i64); - tcg_temp_free_i64(s1_i64); } else { tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), s1); @@ -2166,9 +2138,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_= x *a) s->cfg_ptr->vlen / 8, data)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); fns[s->sew](dest, s1_i64, cpu_env, desc); - - tcg_temp_free_ptr(dest); - tcg_temp_free_i64(s1_i64); } =20 mark_vs_dirty(s); @@ -2210,7 +2179,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_= i *a) tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); fns[s->sew](dest, s1, cpu_env, desc); =20 - tcg_temp_free_ptr(dest); mark_vs_dirty(s); gen_set_label(over); } @@ -2407,10 +2375,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, u= int32_t vs2, =20 fn(dest, mask, t1, src2, cpu_env, desc); =20 - tcg_temp_free_ptr(dest); - tcg_temp_free_ptr(mask); - tcg_temp_free_ptr(src2); - tcg_temp_free_i64(t1); mark_vs_dirty(s); gen_set_label(over); return true; @@ -2814,11 +2778,9 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv= _v_f *a) =20 fns[s->sew - 1](dest, t1, cpu_env, desc); =20 - tcg_temp_free_ptr(dest); mark_vs_dirty(s); gen_set_label(over); } - tcg_temp_free_i64(t1); return true; } return false; @@ -3200,10 +3162,6 @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *= a) =20 gen_helper_vcpop_m(dst, mask, src2, cpu_env, desc); gen_set_gpr(s, a->rd, dst); - - tcg_temp_free_ptr(mask); - tcg_temp_free_ptr(src2); - return true; } return false; @@ -3233,9 +3191,6 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *= a) =20 gen_helper_vfirst_m(dst, mask, src2, cpu_env, desc); gen_set_gpr(s, a->rd, dst); - - tcg_temp_free_ptr(mask); - tcg_temp_free_ptr(src2); return true; } return false; @@ -3430,8 +3385,6 @@ static void vec_element_loadx(DisasContext *s, TCGv_i= 64 dest, /* Perform the load. */ load_element(dest, base, vreg_ofs(s, vreg), s->sew, false); - tcg_temp_free_ptr(base); - tcg_temp_free_i32(ofs); =20 /* Flush out-of-range indexing to zero. */ t_vlmax =3D tcg_constant_i64(vlmax); @@ -3440,8 +3393,6 @@ static void vec_element_loadx(DisasContext *s, TCGv_i= 64 dest, =20 tcg_gen_movcond_i64(TCG_COND_LTU, dest, t_idx, t_vlmax, dest, t_zero); - - tcg_temp_free_i64(t_idx); } =20 static void vec_element_loadi(DisasContext *s, TCGv_i64 dest, @@ -3501,9 +3452,6 @@ static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_= s *a) vec_element_loadi(s, t1, a->rs2, 0, true); tcg_gen_trunc_i64_tl(dest, t1); gen_set_gpr(s, a->rd, dest); - tcg_temp_free_i64(t1); - tcg_temp_free(dest); - return true; } return false; @@ -3531,7 +3479,6 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_= x *a) s1 =3D get_gpr(s, a->rs1, EXT_NONE); tcg_gen_ext_tl_i64(t1, s1); vec_element_storei(s, a->rd, 0, t1); - tcg_temp_free_i64(t1); mark_vs_dirty(s); gen_set_label(over); return true; @@ -3590,7 +3537,6 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_= s_f *a) do_nanbox(s, t1, cpu_fpr[a->rs1]); =20 vec_element_storei(s, a->rd, 0, t1); - tcg_temp_free_i64(t1); mark_vs_dirty(s); gen_set_label(over); return true; @@ -3703,7 +3649,6 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rm= rr *a) =20 tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), dest); - tcg_temp_free_i64(dest); mark_vs_dirty(s); } else { static gen_helper_opivx * const fns[4] =3D { diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_= trans/trans_rvzfh.c.inc index 5024e6ecab..03773e2aa8 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -257,9 +257,6 @@ static bool trans_fsgnj_h(DisasContext *ctx, arg_fsgnj_= h *a) =20 /* This formulation retains the nanboxing of rs2 in normal 'Zf= h'. */ tcg_gen_deposit_i64(dest, rs2, rs1, 0, 15); - - tcg_temp_free_i64(rs1); - tcg_temp_free_i64(rs2); } else { tcg_gen_deposit_i64(dest, src2, src1, 0, 15); tcg_gen_ext16s_i64(dest, dest); @@ -308,15 +305,11 @@ static bool trans_fsgnjn_h(DisasContext *ctx, arg_fsg= njn_h *a) tcg_gen_andc_i64(rs2, rs2, mask); tcg_gen_and_i64(dest, mask, rs1); tcg_gen_or_i64(dest, dest, rs2); - - tcg_temp_free_i64(mask); - tcg_temp_free_i64(rs2); } /* signed-extended intead of nanboxing for result if enable zfinx */ if (ctx->cfg_ptr->ext_zfinx) { tcg_gen_ext16s_i64(dest, dest); } - tcg_temp_free_i64(rs1); mark_fs_dirty(ctx); return true; } @@ -356,14 +349,11 @@ static bool trans_fsgnjx_h(DisasContext *ctx, arg_fsg= njx_h *a) */ tcg_gen_andi_i64(dest, rs2, MAKE_64BIT_MASK(15, 1)); tcg_gen_xor_i64(dest, rs1, dest); - - tcg_temp_free_i64(rs2); } /* signed-extended intead of nanboxing for result if enable zfinx */ if (ctx->cfg_ptr->ext_zfinx) { tcg_gen_ext16s_i64(dest, dest); } - tcg_temp_free_i64(rs1); mark_fs_dirty(ctx); return true; } diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index be87c34f56..9f76223718 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -100,10 +100,7 @@ static TCGv get_th_address_indexed(DisasContext *ctx, = int rs1, int rs2, tcg_gen_shli_tl(offs, src2, imm2); } =20 - TCGv addr =3D get_address_indexed(ctx, rs1, offs); - - tcg_temp_free(offs); - return addr; + return get_address_indexed(ctx, rs1, offs); } =20 /* XTheadBa */ @@ -120,7 +117,6 @@ static void gen_th_addsl##SHAMT(TCGv ret, TCGv arg1, TC= Gv arg2) \ TCGv t =3D tcg_temp_new(); \ tcg_gen_shli_tl(t, arg2, SHAMT); \ tcg_gen_add_tl(ret, t, arg1); \ - tcg_temp_free(t); \ } =20 GEN_TH_ADDSL(1) @@ -204,7 +200,6 @@ static bool gen_th_ff0(DisasContext *ctx, arg_th_ff0 *a= , DisasExtend ext) gen_clz(dest, t); } =20 - tcg_temp_free(t); gen_set_gpr(ctx, a->rd, dest); =20 return true; @@ -469,7 +464,6 @@ static bool trans_th_fmv_hw_x(DisasContext *ctx, arg_th= _fmv_hw_x *a) =20 tcg_gen_extu_tl_i64(t1, src1); tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], t1, 32, 32); - tcg_temp_free_i64(t1); mark_fs_dirty(ctx); return true; } @@ -489,7 +483,6 @@ static bool trans_th_fmv_x_hw(DisasContext *ctx, arg_th= _fmv_x_hw *a) tcg_gen_extract_i64(t1, cpu_fpr[a->rs1], 32, 32); tcg_gen_trunc_i64_tl(dst, t1); gen_set_gpr(ctx, a->rd, dst); - tcg_temp_free_i64(t1); mark_fs_dirty(ctx); return true; } @@ -511,15 +504,12 @@ static bool gen_th_mac(DisasContext *ctx, arg_r *a, extend_operand_func(tmp, src1); extend_operand_func(tmp2, src2); tcg_gen_mul_tl(tmp, tmp, tmp2); - tcg_temp_free(tmp2); } else { tcg_gen_mul_tl(tmp, src1, src2); } =20 accumulate_func(dest, src0, tmp); gen_set_gpr(ctx, a->rd, dest); - tcg_temp_free(tmp); - return true; } =20 @@ -594,8 +584,6 @@ static bool gen_load_inc(DisasContext *ctx, arg_th_memi= nc *a, MemOp memop, tcg_gen_addi_tl(rs1, rs1, imm); gen_set_gpr(ctx, a->rd, rd); gen_set_gpr(ctx, a->rs1, rs1); - - tcg_temp_free(addr); return true; } =20 @@ -615,8 +603,6 @@ static bool gen_store_inc(DisasContext *ctx, arg_th_mem= inc *a, MemOp memop, tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); tcg_gen_addi_tl(rs1, rs1, imm); gen_set_gpr(ctx, a->rs1, rs1); - - tcg_temp_free(addr); return true; } =20 @@ -950,11 +936,6 @@ static bool gen_loadpair_tl(DisasContext *ctx, arg_th_= pair *a, MemOp memop, tcg_gen_qemu_ld_tl(t2, addr2, ctx->mem_idx, memop); gen_set_gpr(ctx, a->rd1, t1); gen_set_gpr(ctx, a->rd2, t2); - - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(addr1); - tcg_temp_free(addr2); return true; } =20 @@ -995,9 +976,6 @@ static bool gen_storepair_tl(DisasContext *ctx, arg_th_= pair *a, MemOp memop, =20 tcg_gen_qemu_st_tl(data1, addr1, ctx->mem_idx, memop); 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.30.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:30:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SRolyktA3w+T8Flrx64dPXxNwnCw3mO2ZM/b7kcuGZ4=; b=OGnG+lDfrgA+UB4hoOActAP/ZvDR9NuJYv4SXUm67XwWn73Y3NNMeaRpkxgsmG+6hc 4iG+E7JC3Bm+BaLCQzQQ+eepLApvax9jazzQOB0dzBIok3YBjpPHvLfvsCLYL0qG42pn LVbcCX1URQnB4NnxcA7V+0/GsPwFx4Vpy+5Doq5i9qGgJvzM89j3dJIYjq9cmGgJjF2b 6Ksruy1E+GCvNEmNUOU345BUqT4Y05lyuNx3bKFbjPRFo9r4R+16QuNwgZ6AqozE1INz ClEsHqd9gGdVFbrYdbt6WbCxFcKxbtQxc2cEvEGhjBOtwyCPjR7F5MgDTxi1NM7Bg0CT /k7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SRolyktA3w+T8Flrx64dPXxNwnCw3mO2ZM/b7kcuGZ4=; b=N6/d0HBF3JrkMoj9+T+dQMKw5QbhR/L286b2UjRZH/M+Ob+xZT/uUKKj2VIg329JHR LIQJwN4G5yx35toPm7c3FpGxt/M1l7pv6qh0pyKvyOqvUgA0elPc64dCmu4Pfv8KJzHA PWsoGXriCVHv3z2sKAbiec2YfAtYL5VDsrqbDyY5EPOKAztZlEeyC77dYLYMJ3ztSdVT k2XGT+GoXiWcj5hynVr7+h6jrv2ZVRKj1q0Z4lMf4Zkyk2TvmA5B9SQPhJuQtjGbY5IE TBCENYoU+KICrkXnb8X/+0fcAnoGbqhzy7B689zQGR5nneYR5+RjG3KwaPKblv8pOOX5 Y34g== X-Gm-Message-State: AO0yUKWpj0CxyjyhMmA+YLNr2FgmuXTgbE+xWJFDcS4zFRY6mlhII8nz n9Q5ZLpzyqOs4TQGu/JFl3z0cRPc/AyWr1nZuCmRmg== X-Google-Smtp-Source: AK7set99pB3U+DHkT1stElX2NsDd2TVU3lH16vBIO8uoBu31WGjpXI/vDGKNKa9GgPR1LHPVeEUG+A== X-Received: by 2002:a17:90b:3b43:b0:237:cfdb:c251 with SMTP id ot3-20020a17090b3b4300b00237cfdbc251mr5908860pjb.16.1677475841849; Sun, 26 Feb 2023 21:30:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 54/76] target/rx: Drop tcg_temp_free Date: Sun, 26 Feb 2023 19:24:43 -1000 Message-Id: <20230227052505.352889-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x641.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476363733100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/rx/translate.c | 84 ------------------------------------------- 1 file changed, 84 deletions(-) diff --git a/target/rx/translate.c b/target/rx/translate.c index af23876cb3..6624414739 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -429,7 +429,6 @@ static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm = *a) mem =3D tcg_temp_new(); tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); rx_gen_st(a->sz, cpu_regs[a->rs], mem); - tcg_temp_free(mem); return true; } =20 @@ -440,7 +439,6 @@ static bool trans_MOV_mr(DisasContext *ctx, arg_MOV_mr = *a) mem =3D tcg_temp_new(); tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); rx_gen_ld(a->sz, cpu_regs[a->rd], mem); - tcg_temp_free(mem); return true; } =20 @@ -462,8 +460,6 @@ static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im = *a) mem =3D tcg_temp_new(); tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); rx_gen_st(a->sz, imm, mem); - tcg_temp_free(imm); - tcg_temp_free(mem); return true; } =20 @@ -474,7 +470,6 @@ static bool trans_MOV_ar(DisasContext *ctx, arg_MOV_ar = *a) mem =3D tcg_temp_new(); rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); rx_gen_ld(a->sz, cpu_regs[a->rd], mem); - tcg_temp_free(mem); return true; } =20 @@ -485,7 +480,6 @@ static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra = *a) mem =3D tcg_temp_new(); rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); rx_gen_st(a->sz, cpu_regs[a->rs], mem); - tcg_temp_free(mem); return true; } =20 @@ -521,9 +515,7 @@ static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm = *a) rx_gen_ld(a->sz, tmp, addr); addr =3D rx_index_addr(ctx, mem, a->ldd, a->sz, a->rd); rx_gen_st(a->sz, tmp, addr); - tcg_temp_free(tmp); } - tcg_temp_free(mem); return true; } =20 @@ -541,7 +533,6 @@ static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp = *a) if (a->ad =3D=3D 0) { tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); } - tcg_temp_free(val); return true; } =20 @@ -559,7 +550,6 @@ static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr = *a) tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); } tcg_gen_mov_i32(cpu_regs[a->rs], val); - tcg_temp_free(val); return true; } =20 @@ -571,7 +561,6 @@ static bool trans_MOVU_mr(DisasContext *ctx, arg_MOVU_m= r *a) mem =3D tcg_temp_new(); tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); - tcg_temp_free(mem); return true; } =20 @@ -592,7 +581,6 @@ static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_a= r *a) mem =3D tcg_temp_new(); rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); - tcg_temp_free(mem); return true; } =20 @@ -610,7 +598,6 @@ static bool trans_MOVU_pr(DisasContext *ctx, arg_MOVU_p= r *a) tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); } tcg_gen_mov_i32(cpu_regs[a->rs], val); - tcg_temp_free(val); return true; } =20 @@ -635,7 +622,6 @@ static bool trans_POPC(DisasContext *ctx, arg_POPC *a) val =3D tcg_temp_new(); pop(val); move_to_cr(ctx, val, a->cr); - tcg_temp_free(val); return true; } =20 @@ -663,7 +649,6 @@ static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r = *a) tcg_gen_mov_i32(val, cpu_regs[a->rs]); tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); rx_gen_st(a->sz, val, cpu_sp); - tcg_temp_free(val); return true; } =20 @@ -677,8 +662,6 @@ static bool trans_PUSH_m(DisasContext *ctx, arg_PUSH_m = *a) rx_gen_ld(a->sz, val, addr); tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); rx_gen_st(a->sz, val, cpu_sp); - tcg_temp_free(mem); - tcg_temp_free(val); return true; } =20 @@ -689,7 +672,6 @@ static bool trans_PUSHC(DisasContext *ctx, arg_PUSHC *a) val =3D tcg_temp_new(); move_from_cr(ctx, val, a->cr, ctx->pc); push(val); - tcg_temp_free(val); return true; } =20 @@ -717,7 +699,6 @@ static bool trans_XCHG_rr(DisasContext *ctx, arg_XCHG_r= r *a) tcg_gen_mov_i32(tmp, cpu_regs[a->rs]); tcg_gen_mov_i32(cpu_regs[a->rs], cpu_regs[a->rd]); tcg_gen_mov_i32(cpu_regs[a->rd], tmp); - tcg_temp_free(tmp); return true; } =20 @@ -741,7 +722,6 @@ static bool trans_XCHG_mr(DisasContext *ctx, arg_XCHG_m= r *a) } tcg_gen_atomic_xchg_i32(cpu_regs[a->rd], addr, cpu_regs[a->rd], 0, mi_to_mop(a->mi)); - tcg_temp_free(mem); return true; } =20 @@ -753,8 +733,6 @@ static inline void stcond(TCGCond cond, int rd, int imm) _imm =3D tcg_const_i32(imm); tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z, _imm, cpu_regs[rd]); - tcg_temp_free(z); - tcg_temp_free(_imm); } =20 /* stz #imm,rd */ @@ -785,12 +763,9 @@ static bool trans_SCCnd(DisasContext *ctx, arg_SCCnd *= a) tcg_gen_setcondi_i32(dc.cond, val, dc.value, 0); addr =3D rx_index_addr(ctx, mem, a->sz, a->ld, a->rd); rx_gen_st(a->sz, val, addr); - tcg_temp_free(val); - tcg_temp_free(mem); } else { tcg_gen_setcondi_i32(dc.cond, cpu_regs[a->rd], dc.value, 0); } - tcg_temp_free(dc.temp); return true; } =20 @@ -842,7 +817,6 @@ static inline void rx_gen_op_irr(op3fn opr, int dst, in= t src, uint32_t src2) { TCGv imm =3D tcg_const_i32(src2); opr(cpu_regs[dst], cpu_regs[src], imm); - tcg_temp_free(imm); } =20 static inline void rx_gen_op_mr(op3fn opr, DisasContext *ctx, @@ -852,7 +826,6 @@ static inline void rx_gen_op_mr(op3fn opr, DisasContext= *ctx, mem =3D tcg_temp_new(); val =3D rx_load_source(ctx, mem, ld, mi, src); opr(cpu_regs[dst], cpu_regs[dst], val); - tcg_temp_free(mem); } =20 static void rx_and(TCGv ret, TCGv arg1, TCGv arg2) @@ -1003,7 +976,6 @@ static void rx_adc(TCGv ret, TCGv arg1, TCGv arg2) tcg_gen_xor_i32(z, arg1, arg2); tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z); tcg_gen_mov_i32(ret, cpu_psw_s); - tcg_temp_free(z); } =20 /* adc #imm, rd */ @@ -1042,7 +1014,6 @@ static void rx_add(TCGv ret, TCGv arg1, TCGv arg2) tcg_gen_xor_i32(z, arg1, arg2); tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z); tcg_gen_mov_i32(ret, cpu_psw_s); - tcg_temp_free(z); } =20 /* add #uimm4, rd */ @@ -1079,7 +1050,6 @@ static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2) temp =3D tcg_temp_new_i32(); tcg_gen_xor_i32(temp, arg1, arg2); tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp); - tcg_temp_free_i32(temp); /* CMP not required return */ if (ret) { tcg_gen_mov_i32(ret, cpu_psw_s); @@ -1097,7 +1067,6 @@ static void rx_sbb(TCGv ret, TCGv arg1, TCGv arg2) temp =3D tcg_temp_new(); tcg_gen_not_i32(temp, arg2); rx_adc(ret, arg1, temp); - tcg_temp_free(temp); } =20 /* cmp #imm4, rs2 */ @@ -1165,8 +1134,6 @@ static void rx_abs(TCGv ret, TCGv arg1) zero =3D tcg_const_i32(0); tcg_gen_neg_i32(neg, arg1); tcg_gen_movcond_i32(TCG_COND_LT, ret, arg1, zero, neg, arg1); - tcg_temp_free(neg); - tcg_temp_free(zero); } =20 /* abs rd */ @@ -1239,7 +1206,6 @@ static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL= _ir *a) } tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], cpu_regs[a->rd], imm); - tcg_temp_free(imm); return true; } =20 @@ -1255,7 +1221,6 @@ static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL= _mr *a) val =3D rx_load_source(ctx, mem, a->ld, a->mi, a->rs); tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], cpu_regs[a->rd], val); - tcg_temp_free(mem); return true; } =20 @@ -1268,7 +1233,6 @@ static bool trans_EMULU_ir(DisasContext *ctx, arg_EMU= LU_ir *a) } tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], cpu_regs[a->rd], imm); - tcg_temp_free(imm); return true; } =20 @@ -1284,7 +1248,6 @@ static bool trans_EMULU_mr(DisasContext *ctx, arg_EMU= LU_mr *a) val =3D rx_load_source(ctx, mem, a->ld, a->mi, a->rs); tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], cpu_regs[a->rd], val); - tcg_temp_free(mem); return true; } =20 @@ -1381,8 +1344,6 @@ static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL= _rr *a) gen_set_label(done); tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); - tcg_temp_free(count); - tcg_temp_free(tmp); return true; } =20 @@ -1436,7 +1397,6 @@ static inline void shiftr_reg(uint32_t rd, uint32_t r= s, unsigned int alith) tcg_gen_movi_i32(cpu_psw_o, 0); tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); - tcg_temp_free(count); } =20 /* shar #imm:5, rd */ @@ -1480,7 +1440,6 @@ static bool trans_ROLC(DisasContext *ctx, arg_ROLC *a) tcg_gen_mov_i32(cpu_psw_c, tmp); tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); - tcg_temp_free(tmp); return true; } =20 @@ -1570,7 +1529,6 @@ static bool trans_REVW(DisasContext *ctx, arg_REVW *a) tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rs], 8); tcg_gen_andi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 0x00ff00ff); tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); - tcg_temp_free(tmp); return true; } =20 @@ -1592,7 +1550,6 @@ static void rx_bcnd_main(DisasContext *ctx, int cd, i= nt dst) gen_set_label(t); gen_goto_tb(ctx, 1, ctx->pc + dst); gen_set_label(done); - tcg_temp_free(dc.temp); break; case 14: /* always true case */ @@ -1642,7 +1599,6 @@ static inline void rx_save_pc(DisasContext *ctx) { TCGv pc =3D tcg_const_i32(ctx->base.pc_next); push(pc); - tcg_temp_free(pc); } =20 /* jmp rs */ @@ -1726,7 +1682,6 @@ static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB = *a) do { \ TCGv size =3D tcg_const_i32(a->sz); \ gen_helper_##op(cpu_env, size); \ - tcg_temp_free(size); \ } while (0) =20 /* suntile. */ @@ -1767,8 +1722,6 @@ static void rx_mul64hi(TCGv_i64 ret, int rs, int rs2) tcg_gen_sari_i64(tmp1, tmp1, 16); tcg_gen_mul_i64(ret, tmp0, tmp1); tcg_gen_shli_i64(ret, ret, 16); - tcg_temp_free_i64(tmp0); - tcg_temp_free_i64(tmp1); } =20 static void rx_mul64lo(TCGv_i64 ret, int rs, int rs2) @@ -1782,8 +1735,6 @@ static void rx_mul64lo(TCGv_i64 ret, int rs, int rs2) tcg_gen_ext16s_i64(tmp1, tmp1); tcg_gen_mul_i64(ret, tmp0, tmp1); tcg_gen_shli_i64(ret, ret, 16); - tcg_temp_free_i64(tmp0); - tcg_temp_free_i64(tmp1); } =20 /* mulhi rs,rs2 */ @@ -1807,7 +1758,6 @@ static bool trans_MACHI(DisasContext *ctx, arg_MACHI = *a) tmp =3D tcg_temp_new_i64(); rx_mul64hi(tmp, a->rs, a->rs2); tcg_gen_add_i64(cpu_acc, cpu_acc, tmp); - tcg_temp_free_i64(tmp); return true; } =20 @@ -1818,7 +1768,6 @@ static bool trans_MACLO(DisasContext *ctx, arg_MACLO = *a) tmp =3D tcg_temp_new_i64(); rx_mul64lo(tmp, a->rs, a->rs2); tcg_gen_add_i64(cpu_acc, cpu_acc, tmp); - tcg_temp_free_i64(tmp); return true; } =20 @@ -1836,7 +1785,6 @@ static bool trans_MVFACMI(DisasContext *ctx, arg_MVFA= CMI *a) rd64 =3D tcg_temp_new_i64(); tcg_gen_extract_i64(rd64, cpu_acc, 16, 32); tcg_gen_extrl_i64_i32(cpu_regs[a->rd], rd64); - tcg_temp_free_i64(rd64); return true; } =20 @@ -1847,7 +1795,6 @@ static bool trans_MVTACHI(DisasContext *ctx, arg_MVTA= CHI *a) rs64 =3D tcg_temp_new_i64(); tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]); tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 32, 32); - tcg_temp_free_i64(rs64); return true; } =20 @@ -1858,7 +1805,6 @@ static bool trans_MVTACLO(DisasContext *ctx, arg_MVTA= CLO *a) rs64 =3D tcg_temp_new_i64(); tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]); tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 0, 32); - tcg_temp_free_i64(rs64); return true; } =20 @@ -1867,7 +1813,6 @@ static bool trans_RACW(DisasContext *ctx, arg_RACW *a) { TCGv imm =3D tcg_const_i32(a->imm + 1); gen_helper_racw(cpu_env, imm); - tcg_temp_free(imm); return true; } =20 @@ -1883,8 +1828,6 @@ static bool trans_SAT(DisasContext *ctx, arg_SAT *a) tcg_gen_xori_i32(tmp, tmp, 0x80000000); tcg_gen_movcond_i32(TCG_COND_LT, cpu_regs[a->rd], cpu_psw_o, z, tmp, cpu_regs[a->rd]); - tcg_temp_free(tmp); - tcg_temp_free(z); return true; } =20 @@ -1903,7 +1846,6 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a) TCGv imm =3D tcg_const_i32(li(ctx, 0)); \ gen_helper_##op(cpu_regs[a->rd], cpu_env, \ cpu_regs[a->rd], imm); \ - tcg_temp_free(imm); \ return true; \ } \ static bool cat3(trans_, name, _mr)(DisasContext *ctx, \ @@ -1914,7 +1856,6 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a) val =3D rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ gen_helper_##op(cpu_regs[a->rd], cpu_env, \ cpu_regs[a->rd], val); \ - tcg_temp_free(mem); \ return true; \ } =20 @@ -1925,7 +1866,6 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a) mem =3D tcg_temp_new(); \ val =3D rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ gen_helper_##op(cpu_regs[a->rd], cpu_env, val); \ - tcg_temp_free(mem); \ return true; \ } =20 @@ -1939,7 +1879,6 @@ static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP= _ir * a) { TCGv imm =3D tcg_const_i32(li(ctx, 0)); gen_helper_fcmp(cpu_env, cpu_regs[a->rd], imm); - tcg_temp_free(imm); return true; } =20 @@ -1951,7 +1890,6 @@ static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP= _mr *a) mem =3D tcg_temp_new(); val =3D rx_load_source(ctx, mem, a->ld, MO_32, a->rs); gen_helper_fcmp(cpu_env, cpu_regs[a->rd], val); - tcg_temp_free(mem); return true; } =20 @@ -1966,7 +1904,6 @@ static bool trans_ITOF(DisasContext *ctx, arg_ITOF * = a) mem =3D tcg_temp_new(); val =3D rx_load_source(ctx, mem, a->ld, a->mi, a->rs); gen_helper_itof(cpu_regs[a->rd], cpu_env, val); - tcg_temp_free(mem); return true; } =20 @@ -1977,7 +1914,6 @@ static void rx_bsetm(TCGv mem, TCGv mask) rx_gen_ld(MO_8, val, mem); tcg_gen_or_i32(val, val, mask); rx_gen_st(MO_8, val, mem); - tcg_temp_free(val); } =20 static void rx_bclrm(TCGv mem, TCGv mask) @@ -1987,7 +1923,6 @@ static void rx_bclrm(TCGv mem, TCGv mask) rx_gen_ld(MO_8, val, mem); tcg_gen_andc_i32(val, val, mask); rx_gen_st(MO_8, val, mem); - tcg_temp_free(val); } =20 static void rx_btstm(TCGv mem, TCGv mask) @@ -1998,7 +1933,6 @@ static void rx_btstm(TCGv mem, TCGv mask) tcg_gen_and_i32(val, val, mask); tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, val, 0); tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); - tcg_temp_free(val); } =20 static void rx_bnotm(TCGv mem, TCGv mask) @@ -2008,7 +1942,6 @@ static void rx_bnotm(TCGv mem, TCGv mask) rx_gen_ld(MO_8, val, mem); tcg_gen_xor_i32(val, val, mask); rx_gen_st(MO_8, val, mem); - tcg_temp_free(val); } =20 static void rx_bsetr(TCGv reg, TCGv mask) @@ -2028,7 +1961,6 @@ static inline void rx_btstr(TCGv reg, TCGv mask) tcg_gen_and_i32(t0, reg, mask); tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, t0, 0); tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); - tcg_temp_free(t0); } =20 static inline void rx_bnotr(TCGv reg, TCGv mask) @@ -2045,8 +1977,6 @@ static inline void rx_bnotr(TCGv reg, TCGv mask) mask =3D tcg_const_i32(1 << a->imm); \ addr =3D rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ cat3(rx_, op, m)(addr, mask); \ - tcg_temp_free(mask); \ - tcg_temp_free(mem); \ return true; \ } \ static bool cat3(trans_, name, _ir)(DisasContext *ctx, \ @@ -2055,7 +1985,6 @@ static inline void rx_bnotr(TCGv reg, TCGv mask) TCGv mask; \ mask =3D tcg_const_i32(1 << a->imm); \ cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ - tcg_temp_free(mask); \ return true; \ } \ static bool cat3(trans_, name, _rr)(DisasContext *ctx, \ @@ -2067,8 +1996,6 @@ static inline void rx_bnotr(TCGv reg, TCGv mask) tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \ tcg_gen_shl_i32(mask, mask, b); \ cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ - tcg_temp_free(mask); \ - tcg_temp_free(b); \ return true; \ } \ static bool cat3(trans_, name, _rm)(DisasContext *ctx, \ @@ -2082,9 +2009,6 @@ static inline void rx_bnotr(TCGv reg, TCGv mask) mem =3D tcg_temp_new(); \ addr =3D rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ cat3(rx_, op, m)(addr, mask); \ - tcg_temp_free(mem); \ - tcg_temp_free(mask); \ - tcg_temp_free(b); \ return true; \ } =20 @@ -2103,8 +2027,6 @@ static inline void bmcnd_op(TCGv val, TCGCond cond, i= nt pos) tcg_gen_andi_i32(val, val, ~(1 << pos)); tcg_gen_setcondi_i32(dc.cond, bit, dc.value, 0); tcg_gen_deposit_i32(val, val, bit, pos, 1); - tcg_temp_free(bit); - tcg_temp_free(dc.temp); } =20 /* bmcnd #imm, dsp[rd] */ @@ -2117,8 +2039,6 @@ static bool trans_BMCnd_im(DisasContext *ctx, arg_BMC= nd_im *a) rx_gen_ld(MO_8, val, addr); bmcnd_op(val, a->cd, a->imm); rx_gen_st(MO_8, val, addr); - tcg_temp_free(val); - tcg_temp_free(mem); return true; } =20 @@ -2210,7 +2130,6 @@ static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_= i *a) =20 imm =3D tcg_const_i32(a->imm); move_to_cr(ctx, imm, a->cr); - tcg_temp_free(imm); return true; } =20 @@ -2238,7 +2157,6 @@ static bool trans_RTFI(DisasContext *ctx, arg_RTFI *a) tcg_gen_mov_i32(psw, cpu_bpsw); gen_helper_set_psw_rte(cpu_env, psw); ctx->base.is_jmp =3D DISAS_EXIT; - tcg_temp_free(psw); } return true; } @@ -2253,7 +2171,6 @@ static bool trans_RTE(DisasContext *ctx, arg_RTE *a) pop(psw); gen_helper_set_psw_rte(cpu_env, psw); ctx->base.is_jmp =3D DISAS_EXIT; - tcg_temp_free(psw); } return true; } @@ -2276,7 +2193,6 @@ static bool trans_INT(DisasContext *ctx, arg_INT *a) vec =3D tcg_const_i32(a->imm); tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); gen_helper_rxint(cpu_env, vec); - tcg_temp_free(vec); ctx->base.is_jmp =3D DISAS_NORETURN; return true; } --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677476249; cv=none; d=zohomail.com; s=zohoarc; b=QegCK8OdkgWDOcySX/2ZiASjV69kNEbrTDjf0jbDQhIf3IBx8KfSIB5baVkEpH0e7sVvrSzudD9qe7BrC0dbLhCg04NmnW2PArPr6vcxoZ54+IP+d7L0vukzTBtdztaoF0+37bHRb1dORVW0xfDbM/C3YXiO2MiBrnJ0fVE+l6s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677476249; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/s390x/tcg/translate.c | 410 +++++++++++++---------------------- 1 file changed, 147 insertions(+), 263 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 339c1672e9..3e3f685451 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -171,8 +171,6 @@ static uint64_t inline_branch_miss[CC_OP_MAX]; =20 static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc) { - TCGv_i64 tmp; - if (s->base.tb->flags & FLAG_MASK_32) { if (s->base.tb->flags & FLAG_MASK_64) { tcg_gen_movi_i64(out, pc); @@ -181,9 +179,7 @@ static void pc_to_link_info(TCGv_i64 out, DisasContext = *s, uint64_t pc) pc |=3D 0x80000000; } assert(!(s->base.tb->flags & FLAG_MASK_64)); - tmp =3D tcg_const_i64(pc); - tcg_gen_deposit_i64(out, out, tmp, 0, 32); - tcg_temp_free_i64(tmp); + tcg_gen_deposit_i64(out, out, tcg_constant_i64(pc), 0, 32); } =20 static TCGv_i64 psw_addr; @@ -360,11 +356,8 @@ static void per_branch(DisasContext *s, bool to_next) tcg_gen_movi_i64(gbea, s->base.pc_next); =20 if (s->base.tb->flags & FLAG_MASK_PER) { - TCGv_i64 next_pc =3D to_next ? tcg_const_i64(s->pc_tmp) : psw_addr; + TCGv_i64 next_pc =3D to_next ? tcg_constant_i64(s->pc_tmp) : psw_a= ddr; gen_helper_per_branch(cpu_env, gbea, next_pc); - if (to_next) { - tcg_temp_free_i64(next_pc); - } } #endif } @@ -382,9 +375,8 @@ static void per_branch_cond(DisasContext *s, TCGCond co= nd, =20 gen_set_label(lab); } else { - TCGv_i64 pc =3D tcg_const_i64(s->base.pc_next); + TCGv_i64 pc =3D tcg_constant_i64(s->base.pc_next); tcg_gen_movcond_i64(cond, gbea, arg1, arg2, gbea, pc); - tcg_temp_free_i64(pc); } #endif } @@ -438,23 +430,17 @@ static int get_mem_index(DisasContext *s) =20 static void gen_exception(int excp) { - TCGv_i32 tmp =3D tcg_const_i32(excp); - gen_helper_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); + gen_helper_exception(cpu_env, tcg_constant_i32(excp)); } =20 static void gen_program_exception(DisasContext *s, int code) { - TCGv_i32 tmp; + /* Remember what pgm exeption this was. */ + tcg_gen_st_i32(tcg_constant_i32(code), cpu_env, + offsetof(CPUS390XState, int_pgm_code)); =20 - /* Remember what pgm exception this was. */ - tmp =3D tcg_const_i32(code); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code)); - tcg_temp_free_i32(tmp); - - tmp =3D tcg_const_i32(s->ilen); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_ilen)); - tcg_temp_free_i32(tmp); + tcg_gen_st_i32(tcg_constant_i32(s->ilen), cpu_env, + offsetof(CPUS390XState, int_pgm_ilen)); =20 /* update the psw */ update_psw_addr(s); @@ -473,9 +459,7 @@ static inline void gen_illegal_opcode(DisasContext *s) =20 static inline void gen_data_exception(uint8_t dxc) { - TCGv_i32 tmp =3D tcg_const_i32(dxc); - gen_helper_data_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); + gen_helper_data_exception(cpu_env, tcg_constant_i32(dxc)); } =20 static inline void gen_trap(DisasContext *s) @@ -596,13 +580,13 @@ static void gen_op_calc_cc(DisasContext *s) =20 switch (s->cc_op) { default: - dummy =3D tcg_const_i64(0); + dummy =3D tcg_constant_i64(0); /* FALLTHRU */ case CC_OP_ADD_64: case CC_OP_SUB_64: case CC_OP_ADD_32: case CC_OP_SUB_32: - local_cc_op =3D tcg_const_i32(s->cc_op); + local_cc_op =3D tcg_constant_i32(s->cc_op); break; case CC_OP_CONST0: case CC_OP_CONST1: @@ -675,13 +659,6 @@ static void gen_op_calc_cc(DisasContext *s) tcg_abort(); } =20 - if (local_cc_op) { - tcg_temp_free_i32(local_cc_op); - } - if (dummy) { - tcg_temp_free_i64(dummy); - } - /* We now have cc in cc_op as constant */ set_cc_static(s); } @@ -1300,9 +1277,9 @@ static DisasJumpType help_branch(DisasContext *s, Dis= asCompare *c, Most commonly we're single-stepping or some other condition that disables all use of goto_tb. Just update the PC and exit. */ =20 - TCGv_i64 next =3D tcg_const_i64(s->pc_tmp); + TCGv_i64 next =3D tcg_constant_i64(s->pc_tmp); if (is_imm) { - cdest =3D tcg_const_i64(dest); + cdest =3D tcg_constant_i64(dest); } =20 if (c->is_64) { @@ -1312,21 +1289,15 @@ static DisasJumpType help_branch(DisasContext *s, D= isasCompare *c, } else { TCGv_i32 t0 =3D tcg_temp_new_i32(); TCGv_i64 t1 =3D tcg_temp_new_i64(); - TCGv_i64 z =3D tcg_const_i64(0); + TCGv_i64 z =3D tcg_constant_i64(0); tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b); tcg_gen_extu_i32_i64(t1, t0); tcg_temp_free_i32(t0); tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next); per_branch_cond(s, TCG_COND_NE, t1, z); tcg_temp_free_i64(t1); - tcg_temp_free_i64(z); } =20 - if (is_imm) { - tcg_temp_free_i64(cdest); - } - tcg_temp_free_i64(next); - ret =3D DISAS_PC_UPDATED; } =20 @@ -1410,10 +1381,9 @@ static DisasJumpType op_addc64(DisasContext *s, Disa= sOps *o) { compute_carry(s); =20 - TCGv_i64 zero =3D tcg_const_i64(0); + TCGv_i64 zero =3D tcg_constant_i64(0); tcg_gen_add2_i64(o->out, cc_src, o->in1, zero, cc_src, zero); tcg_gen_add2_i64(o->out, cc_src, o->out, cc_src, o->in2, zero); - tcg_temp_free_i64(zero); =20 return DISAS_NEXT; } @@ -2092,9 +2062,8 @@ static DisasJumpType op_clc(DisasContext *s, DisasOps= *o) tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s)); break; default: - vl =3D tcg_const_i32(l); + vl =3D tcg_constant_i32(l); gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2); - tcg_temp_free_i32(vl); set_cc_static(s); return DISAS_NEXT; } @@ -2114,11 +2083,9 @@ static DisasJumpType op_clcl(DisasContext *s, DisasO= ps *o) return DISAS_NORETURN; } =20 - t1 =3D tcg_const_i32(r1); - t2 =3D tcg_const_i32(r2); + t1 =3D tcg_constant_i32(r1); + t2 =3D tcg_constant_i32(r2); gen_helper_clcl(cc_op, cpu_env, t1, t2); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); set_cc_static(s); return DISAS_NEXT; } @@ -2135,11 +2102,9 @@ static DisasJumpType op_clcle(DisasContext *s, Disas= Ops *o) return DISAS_NORETURN; } =20 - t1 =3D tcg_const_i32(r1); - t3 =3D tcg_const_i32(r3); + t1 =3D tcg_constant_i32(r1); + t3 =3D tcg_constant_i32(r3); gen_helper_clcle(cc_op, cpu_env, t1, o->in2, t3); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t3); set_cc_static(s); return DISAS_NEXT; } @@ -2156,24 +2121,22 @@ static DisasJumpType op_clclu(DisasContext *s, Disa= sOps *o) return DISAS_NORETURN; } =20 - t1 =3D tcg_const_i32(r1); - t3 =3D tcg_const_i32(r3); + t1 =3D tcg_constant_i32(r1); + t3 =3D tcg_constant_i32(r3); gen_helper_clclu(cc_op, cpu_env, t1, o->in2, t3); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t3); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_clm(DisasContext *s, DisasOps *o) { - TCGv_i32 m3 =3D tcg_const_i32(get_field(s, m3)); + TCGv_i32 m3 =3D tcg_constant_i32(get_field(s, m3)); TCGv_i32 t1 =3D tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(t1, o->in1); gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2); set_cc_static(s); tcg_temp_free_i32(t1); - tcg_temp_free_i32(m3); return DISAS_NEXT; } =20 @@ -2251,14 +2214,13 @@ static DisasJumpType op_cdsg(DisasContext *s, Disas= Ops *o) static DisasJumpType op_csst(DisasContext *s, DisasOps *o) { int r3 =3D get_field(s, r3); - TCGv_i32 t_r3 =3D tcg_const_i32(r3); + TCGv_i32 t_r3 =3D tcg_constant_i32(r3); =20 if (tb_cflags(s->base.tb) & CF_PARALLEL) { gen_helper_csst_parallel(cc_op, cpu_env, t_r3, o->addr1, o->in2); } else { gen_helper_csst(cc_op, cpu_env, t_r3, o->addr1, o->in2); } - tcg_temp_free_i32(t_r3); =20 set_cc_static(s); return DISAS_NEXT; @@ -2356,9 +2318,9 @@ static DisasJumpType op_cuXX(DisasContext *s, DisasOp= s *o) m3 =3D 0; } =20 - tr1 =3D tcg_const_i32(r1); - tr2 =3D tcg_const_i32(r2); - chk =3D tcg_const_i32(m3); + tr1 =3D tcg_constant_i32(r1); + tr2 =3D tcg_constant_i32(r2); + chk =3D tcg_constant_i32(m3); =20 switch (s->insn->data) { case 12: @@ -2383,9 +2345,6 @@ static DisasJumpType op_cuXX(DisasContext *s, DisasOp= s *o) g_assert_not_reached(); } =20 - tcg_temp_free_i32(tr1); - tcg_temp_free_i32(tr2); - tcg_temp_free_i32(chk); set_cc_static(s); return DISAS_NEXT; } @@ -2393,15 +2352,11 @@ static DisasJumpType op_cuXX(DisasContext *s, Disas= Ops *o) #ifndef CONFIG_USER_ONLY static DisasJumpType op_diag(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 =3D tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 =3D tcg_const_i32(get_field(s, r3)); - TCGv_i32 func_code =3D tcg_const_i32(get_field(s, i2)); + TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 =3D tcg_constant_i32(get_field(s, r3)); + TCGv_i32 func_code =3D tcg_constant_i32(get_field(s, i2)); =20 gen_helper_diag(cpu_env, r1, r3, func_code); - - tcg_temp_free_i32(func_code); - tcg_temp_free_i32(r3); - tcg_temp_free_i32(r1); return DISAS_NEXT; } #endif @@ -2512,18 +2467,13 @@ static DisasJumpType op_ex(DisasContext *s, DisasOp= s *o) update_cc_op(s); =20 if (r1 =3D=3D 0) { - v1 =3D tcg_const_i64(0); + v1 =3D tcg_constant_i64(0); } else { v1 =3D regs[r1]; } =20 - ilen =3D tcg_const_i32(s->ilen); + ilen =3D tcg_constant_i32(s->ilen); gen_helper_ex(cpu_env, ilen, v1, o->in2); - tcg_temp_free_i32(ilen); - - if (r1 =3D=3D 0) { - tcg_temp_free_i64(v1); - } =20 return DISAS_PC_CC_UPDATED; } @@ -2674,12 +2624,11 @@ static DisasJumpType op_idte(DisasContext *s, Disas= Ops *o) TCGv_i32 m4; =20 if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) { - m4 =3D tcg_const_i32(get_field(s, m4)); + m4 =3D tcg_constant_i32(get_field(s, m4)); } else { - m4 =3D tcg_const_i32(0); + m4 =3D tcg_constant_i32(0); } gen_helper_idte(cpu_env, o->in1, o->in2, m4); - tcg_temp_free_i32(m4); return DISAS_NEXT; } =20 @@ -2688,12 +2637,11 @@ static DisasJumpType op_ipte(DisasContext *s, Disas= Ops *o) TCGv_i32 m4; =20 if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) { - m4 =3D tcg_const_i32(get_field(s, m4)); + m4 =3D tcg_constant_i32(get_field(s, m4)); } else { - m4 =3D tcg_const_i32(0); + m4 =3D tcg_constant_i32(0); } gen_helper_ipte(cpu_env, o->in1, o->in2, m4); - tcg_temp_free_i32(m4); return DISAS_NEXT; } =20 @@ -2749,16 +2697,12 @@ static DisasJumpType op_msa(DisasContext *s, DisasO= ps *o) g_assert_not_reached(); }; =20 - t_r1 =3D tcg_const_i32(r1); - t_r2 =3D tcg_const_i32(r2); - t_r3 =3D tcg_const_i32(r3); - type =3D tcg_const_i32(s->insn->data); + t_r1 =3D tcg_constant_i32(r1); + t_r2 =3D tcg_constant_i32(r2); + t_r3 =3D tcg_constant_i32(r3); + type =3D tcg_constant_i32(s->insn->data); gen_helper_msa(cc_op, cpu_env, t_r1, t_r2, t_r3, type); set_cc_static(s); - tcg_temp_free_i32(t_r1); - tcg_temp_free_i32(t_r2); - tcg_temp_free_i32(t_r3); - tcg_temp_free_i32(type); return DISAS_NEXT; } =20 @@ -3017,10 +2961,9 @@ static DisasJumpType op_loc(DisasContext *s, DisasOp= s *o) tcg_gen_extu_i32_i64(t, t32); tcg_temp_free_i32(t32); =20 - z =3D tcg_const_i64(0); + z =3D tcg_constant_i64(0); tcg_gen_movcond_i64(TCG_COND_NE, o->out, t, z, o->in2, o->in1); tcg_temp_free_i64(t); - tcg_temp_free_i64(z); } =20 return DISAS_NEXT; @@ -3029,11 +2972,10 @@ static DisasJumpType op_loc(DisasContext *s, DisasO= ps *o) #ifndef CONFIG_USER_ONLY static DisasJumpType op_lctl(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 =3D tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 =3D tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 =3D tcg_constant_i32(get_field(s, r3)); + gen_helper_lctl(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */ s->exit_to_mainloop =3D true; return DISAS_TOO_MANY; @@ -3041,11 +2983,10 @@ static DisasJumpType op_lctl(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_lctlg(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 =3D tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 =3D tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 =3D tcg_constant_i32(get_field(s, r3)); + gen_helper_lctlg(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */ s->exit_to_mainloop =3D true; return DISAS_TOO_MANY; @@ -3105,11 +3046,10 @@ static DisasJumpType op_lpswe(DisasContext *s, Disa= sOps *o) =20 static DisasJumpType op_lam(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 =3D tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 =3D tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 =3D tcg_constant_i32(get_field(s, r3)); + gen_helper_lam(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); return DISAS_NEXT; } =20 @@ -3319,9 +3259,6 @@ static DisasJumpType op_lcbb(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_mc(DisasContext *s, DisasOps *o) { -#if !defined(CONFIG_USER_ONLY) - TCGv_i32 i2; -#endif const uint16_t monitor_class =3D get_field(s, i2); =20 if (monitor_class & 0xff00) { @@ -3330,9 +3267,8 @@ static DisasJumpType op_mc(DisasContext *s, DisasOps = *o) } =20 #if !defined(CONFIG_USER_ONLY) - i2 =3D tcg_const_i32(monitor_class); - gen_helper_monitor_call(cpu_env, o->addr1, i2); - tcg_temp_free_i32(i2); + gen_helper_monitor_call(cpu_env, o->addr1, + tcg_constant_i32(monitor_class)); #endif /* Defaults to a NOP. */ return DISAS_NEXT; @@ -3396,9 +3332,9 @@ static DisasJumpType op_movx(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_mvc(DisasContext *s, DisasOps *o) { - TCGv_i32 l =3D tcg_const_i32(get_field(s, l1)); + TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); + gen_helper_mvc(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } =20 @@ -3410,9 +3346,9 @@ static DisasJumpType op_mvcrl(DisasContext *s, DisasO= ps *o) =20 static DisasJumpType op_mvcin(DisasContext *s, DisasOps *o) { - TCGv_i32 l =3D tcg_const_i32(get_field(s, l1)); + TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); + gen_helper_mvcin(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } =20 @@ -3428,11 +3364,9 @@ static DisasJumpType op_mvcl(DisasContext *s, DisasO= ps *o) return DISAS_NORETURN; } =20 - t1 =3D tcg_const_i32(r1); - t2 =3D tcg_const_i32(r2); + t1 =3D tcg_constant_i32(r1); + t2 =3D tcg_constant_i32(r2); gen_helper_mvcl(cc_op, cpu_env, t1, t2); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); set_cc_static(s); return DISAS_NEXT; } @@ -3449,11 +3383,9 @@ static DisasJumpType op_mvcle(DisasContext *s, Disas= Ops *o) return DISAS_NORETURN; } =20 - t1 =3D tcg_const_i32(r1); - t3 =3D tcg_const_i32(r3); + t1 =3D tcg_constant_i32(r1); + t3 =3D tcg_constant_i32(r3); gen_helper_mvcle(cc_op, cpu_env, t1, o->in2, t3); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t3); set_cc_static(s); return DISAS_NEXT; } @@ -3470,11 +3402,9 @@ static DisasJumpType op_mvclu(DisasContext *s, Disas= Ops *o) return DISAS_NORETURN; } =20 - t1 =3D tcg_const_i32(r1); - t3 =3D tcg_const_i32(r3); + t1 =3D tcg_constant_i32(r1); + t3 =3D tcg_constant_i32(r3); gen_helper_mvclu(cc_op, cpu_env, t1, o->in2, t3); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t3); set_cc_static(s); return DISAS_NEXT; } @@ -3509,49 +3439,45 @@ static DisasJumpType op_mvcs(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_mvn(DisasContext *s, DisasOps *o) { - TCGv_i32 l =3D tcg_const_i32(get_field(s, l1)); + TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); + gen_helper_mvn(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } =20 static DisasJumpType op_mvo(DisasContext *s, DisasOps *o) { - TCGv_i32 l =3D tcg_const_i32(get_field(s, l1)); + TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); + gen_helper_mvo(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } =20 static DisasJumpType op_mvpg(DisasContext *s, DisasOps *o) { - TCGv_i32 t1 =3D tcg_const_i32(get_field(s, r1)); - TCGv_i32 t2 =3D tcg_const_i32(get_field(s, r2)); + TCGv_i32 t1 =3D tcg_constant_i32(get_field(s, r1)); + TCGv_i32 t2 =3D tcg_constant_i32(get_field(s, r2)); =20 gen_helper_mvpg(cc_op, cpu_env, regs[0], t1, t2); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_mvst(DisasContext *s, DisasOps *o) { - TCGv_i32 t1 =3D tcg_const_i32(get_field(s, r1)); - TCGv_i32 t2 =3D tcg_const_i32(get_field(s, r2)); + TCGv_i32 t1 =3D tcg_constant_i32(get_field(s, r1)); + TCGv_i32 t2 =3D tcg_constant_i32(get_field(s, r2)); =20 gen_helper_mvst(cc_op, cpu_env, t1, t2); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_mvz(DisasContext *s, DisasOps *o) { - TCGv_i32 l =3D tcg_const_i32(get_field(s, l1)); + TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); + gen_helper_mvz(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } =20 @@ -3637,13 +3563,12 @@ static DisasJumpType op_msdb(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_nabs(DisasContext *s, DisasOps *o) { - TCGv_i64 z, n; - z =3D tcg_const_i64(0); - n =3D tcg_temp_new_i64(); + TCGv_i64 z =3D tcg_constant_i64(0); + TCGv_i64 n =3D tcg_temp_new_i64(); + tcg_gen_neg_i64(n, o->in2); tcg_gen_movcond_i64(TCG_COND_GE, o->out, o->in2, z, n, o->in2); tcg_temp_free_i64(n); - tcg_temp_free_i64(z); return DISAS_NEXT; } =20 @@ -3668,9 +3593,9 @@ static DisasJumpType op_nabsf128(DisasContext *s, Dis= asOps *o) =20 static DisasJumpType op_nc(DisasContext *s, DisasOps *o) { - TCGv_i32 l =3D tcg_const_i32(get_field(s, l1)); + TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); + gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } @@ -3702,9 +3627,9 @@ static DisasJumpType op_negf128(DisasContext *s, Disa= sOps *o) =20 static DisasJumpType op_oc(DisasContext *s, DisasOps *o) { - TCGv_i32 l =3D tcg_const_i32(get_field(s, l1)); + TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); + gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } @@ -3754,9 +3679,9 @@ static DisasJumpType op_oi(DisasContext *s, DisasOps = *o) =20 static DisasJumpType op_pack(DisasContext *s, DisasOps *o) { - TCGv_i32 l =3D tcg_const_i32(get_field(s, l1)); + TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); + gen_helper_pack(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } =20 @@ -3770,9 +3695,8 @@ static DisasJumpType op_pka(DisasContext *s, DisasOps= *o) gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - l =3D tcg_const_i32(l2); + l =3D tcg_constant_i32(l2); gen_helper_pka(cpu_env, o->addr1, o->in2, l); - tcg_temp_free_i32(l); return DISAS_NEXT; } =20 @@ -3786,9 +3710,8 @@ static DisasJumpType op_pku(DisasContext *s, DisasOps= *o) gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - l =3D tcg_const_i32(l2); + l =3D tcg_constant_i32(l2); gen_helper_pku(cpu_env, o->addr1, o->in2, l); - tcg_temp_free_i32(l); return DISAS_NEXT; } =20 @@ -4035,9 +3958,8 @@ static DisasJumpType op_sam(DisasContext *s, DisasOps= *o) } s->pc_tmp &=3D mask; =20 - tsam =3D tcg_const_i64(sam); + tsam =3D tcg_constant_i64(sam); tcg_gen_deposit_i64(psw_mask, psw_mask, tsam, 31, 2); - tcg_temp_free_i64(tsam); =20 /* Always exit the TB, since we (may have) changed execution mode. */ return DISAS_TOO_MANY; @@ -4096,12 +4018,11 @@ static DisasJumpType op_servc(DisasContext *s, Disa= sOps *o) =20 static DisasJumpType op_sigp(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 =3D tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 =3D tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 =3D tcg_constant_i32(get_field(s, r3)); + gen_helper_sigp(cc_op, cpu_env, o->in2, r1, r3); set_cc_static(s); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); return DISAS_NEXT; } #endif @@ -4370,21 +4291,19 @@ static DisasJumpType op_stckc(DisasContext *s, Disa= sOps *o) =20 static DisasJumpType op_stctg(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 =3D tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 =3D tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 =3D tcg_constant_i32(get_field(s, r3)); + gen_helper_stctg(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); return DISAS_NEXT; } =20 static DisasJumpType op_stctl(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 =3D tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 =3D tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 =3D tcg_constant_i32(get_field(s, r3)); + gen_helper_stctl(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); return DISAS_NEXT; } =20 @@ -4611,11 +4530,10 @@ static DisasJumpType op_st64(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_stam(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 =3D tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 =3D tcg_const_i32(get_field(s, r3)); + TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 =3D tcg_constant_i32(get_field(s, r3)); + gen_helper_stam(cpu_env, r1, o->in2, r3); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); return DISAS_NEXT; } =20 @@ -4673,7 +4591,7 @@ static DisasJumpType op_stm(DisasContext *s, DisasOps= *o) int r1 =3D get_field(s, r1); int r3 =3D get_field(s, r3); int size =3D s->insn->data; - TCGv_i64 tsize =3D tcg_const_i64(size); + TCGv_i64 tsize =3D tcg_constant_i64(size); =20 while (1) { if (size =3D=3D 8) { @@ -4688,7 +4606,6 @@ static DisasJumpType op_stm(DisasContext *s, DisasOps= *o) r1 =3D (r1 + 1) & 15; } =20 - tcg_temp_free_i64(tsize); return DISAS_NEXT; } =20 @@ -4697,8 +4614,8 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOp= s *o) int r1 =3D get_field(s, r1); int r3 =3D get_field(s, r3); TCGv_i64 t =3D tcg_temp_new_i64(); - TCGv_i64 t4 =3D tcg_const_i64(4); - TCGv_i64 t32 =3D tcg_const_i64(32); + TCGv_i64 t4 =3D tcg_constant_i64(4); + TCGv_i64 t32 =3D tcg_constant_i64(32); =20 while (1) { tcg_gen_shl_i64(t, regs[r1], t32); @@ -4711,8 +4628,6 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOp= s *o) } =20 tcg_temp_free_i64(t); - tcg_temp_free_i64(t4); - tcg_temp_free_i64(t32); return DISAS_NEXT; } =20 @@ -4731,26 +4646,20 @@ static DisasJumpType op_stpq(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_srst(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 =3D tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 =3D tcg_const_i32(get_field(s, r2)); + TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 =3D tcg_constant_i32(get_field(s, r2)); =20 gen_helper_srst(cpu_env, r1, r2); - - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_srstu(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 =3D tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 =3D tcg_const_i32(get_field(s, r2)); + TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 =3D tcg_constant_i32(get_field(s, r2)); =20 gen_helper_srstu(cpu_env, r1, r2); - - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } @@ -4808,10 +4717,9 @@ static DisasJumpType op_subb64(DisasContext *s, Disa= sOps *o) * Borrow is {0, -1}, so add to subtract; replicate the * borrow input to produce 128-bit -1 for the addition. */ - TCGv_i64 zero =3D tcg_const_i64(0); + TCGv_i64 zero =3D tcg_constant_i64(0); tcg_gen_add2_i64(o->out, cc_src, o->in1, zero, cc_src, cc_src); tcg_gen_sub2_i64(o->out, cc_src, o->out, cc_src, o->in2, zero); - tcg_temp_free_i64(zero); =20 return DISAS_NEXT; } @@ -4823,13 +4731,11 @@ static DisasJumpType op_svc(DisasContext *s, DisasO= ps *o) update_psw_addr(s); update_cc_op(s); =20 - t =3D tcg_const_i32(get_field(s, i1) & 0xff); + t =3D tcg_constant_i32(get_field(s, i1) & 0xff); tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code)); - tcg_temp_free_i32(t); =20 - t =3D tcg_const_i32(s->ilen); + t =3D tcg_constant_i32(s->ilen); tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen)); - tcg_temp_free_i32(t); =20 gen_exception(EXCP_SVC); return DISAS_NORETURN; @@ -4886,18 +4792,18 @@ static DisasJumpType op_tprot(DisasContext *s, Disa= sOps *o) =20 static DisasJumpType op_tp(DisasContext *s, DisasOps *o) { - TCGv_i32 l1 =3D tcg_const_i32(get_field(s, l1) + 1); + TCGv_i32 l1 =3D tcg_constant_i32(get_field(s, l1) + 1); + gen_helper_tp(cc_op, cpu_env, o->addr1, l1); - tcg_temp_free_i32(l1); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_tr(DisasContext *s, DisasOps *o) { - TCGv_i32 l =3D tcg_const_i32(get_field(s, l1)); + TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); + gen_helper_tr(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } @@ -4915,27 +4821,27 @@ static DisasJumpType op_tre(DisasContext *s, DisasO= ps *o) =20 static DisasJumpType op_trt(DisasContext *s, DisasOps *o) { - TCGv_i32 l =3D tcg_const_i32(get_field(s, l1)); + TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); + gen_helper_trt(cc_op, cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_trtr(DisasContext *s, DisasOps *o) { - TCGv_i32 l =3D tcg_const_i32(get_field(s, l1)); + TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); + gen_helper_trtr(cc_op, cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_trXX(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 =3D tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 =3D tcg_const_i32(get_field(s, r2)); - TCGv_i32 sizes =3D tcg_const_i32(s->insn->opc & 3); + TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 =3D tcg_constant_i32(get_field(s, r2)); + TCGv_i32 sizes =3D tcg_constant_i32(s->insn->opc & 3); TCGv_i32 tst =3D tcg_temp_new_i32(); int m3 =3D get_field(s, m3); =20 @@ -4954,9 +4860,6 @@ static DisasJumpType op_trXX(DisasContext *s, DisasOp= s *o) } gen_helper_trXX(cc_op, cpu_env, r1, r2, tst, sizes); =20 - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); - tcg_temp_free_i32(sizes); tcg_temp_free_i32(tst); set_cc_static(s); return DISAS_NEXT; @@ -4964,19 +4867,19 @@ static DisasJumpType op_trXX(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_ts(DisasContext *s, DisasOps *o) { - TCGv_i32 t1 =3D tcg_const_i32(0xff); + TCGv_i32 t1 =3D tcg_constant_i32(0xff); + tcg_gen_atomic_xchg_i32(t1, o->in2, t1, get_mem_index(s), MO_UB); tcg_gen_extract_i32(cc_op, t1, 7, 1); - tcg_temp_free_i32(t1); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_unpk(DisasContext *s, DisasOps *o) { - TCGv_i32 l =3D tcg_const_i32(get_field(s, l1)); + TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); + gen_helper_unpk(cpu_env, l, o->addr1, o->in2); - tcg_temp_free_i32(l); return DISAS_NEXT; } =20 @@ -4990,9 +4893,8 @@ static DisasJumpType op_unpka(DisasContext *s, DisasO= ps *o) gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - l =3D tcg_const_i32(l1); + l =3D tcg_constant_i32(l1); gen_helper_unpka(cc_op, cpu_env, o->addr1, l, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } @@ -5007,9 +4909,8 @@ static DisasJumpType op_unpku(DisasContext *s, DisasO= ps *o) gen_program_exception(s, PGM_SPECIFICATION); return DISAS_NORETURN; } - l =3D tcg_const_i32(l1); + l =3D tcg_constant_i32(l1); gen_helper_unpku(cc_op, cpu_env, o->addr1, l, o->in2); - tcg_temp_free_i32(l); set_cc_static(s); return DISAS_NEXT; } @@ -5028,7 +4929,7 @@ static DisasJumpType op_xc(DisasContext *s, DisasOps = *o) =20 /* If the addresses are identical, this is a store/memset of zero. */ if (b1 =3D=3D b2 && d1 =3D=3D d2 && (l + 1) <=3D 32) { - o->in2 =3D tcg_const_i64(0); + o->in2 =3D tcg_constant_i64(0); =20 l++; while (l >=3D 8) { @@ -5061,9 +4962,8 @@ static DisasJumpType op_xc(DisasContext *s, DisasOps = *o) =20 /* But in general we'll defer to a helper. */ o->in2 =3D get_address(s, 0, b2, d2); - t32 =3D tcg_const_i32(l); + t32 =3D tcg_constant_i32(l); gen_helper_xc(cc_op, cpu_env, t32, o->addr1, o->in2); - tcg_temp_free_i32(t32); set_cc_static(s); return DISAS_NEXT; } @@ -5128,46 +5028,39 @@ static DisasJumpType op_zero2(DisasContext *s, Disa= sOps *o) #ifndef CONFIG_USER_ONLY static DisasJumpType op_clp(DisasContext *s, DisasOps *o) { - TCGv_i32 r2 =3D tcg_const_i32(get_field(s, r2)); + TCGv_i32 r2 =3D tcg_constant_i32(get_field(s, r2)); =20 gen_helper_clp(cpu_env, r2); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_pcilg(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 =3D tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 =3D tcg_const_i32(get_field(s, r2)); + TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 =3D tcg_constant_i32(get_field(s, r2)); =20 gen_helper_pcilg(cpu_env, r1, r2); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_pcistg(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 =3D tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 =3D tcg_const_i32(get_field(s, r2)); + TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 =3D tcg_constant_i32(get_field(s, r2)); =20 gen_helper_pcistg(cpu_env, r1, r2); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_stpcifc(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 =3D tcg_const_i32(get_field(s, r1)); - TCGv_i32 ar =3D tcg_const_i32(get_field(s, b2)); + TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); + TCGv_i32 ar =3D tcg_constant_i32(get_field(s, b2)); =20 gen_helper_stpcifc(cpu_env, r1, o->addr1, ar); - tcg_temp_free_i32(ar); - tcg_temp_free_i32(r1); set_cc_static(s); return DISAS_NEXT; } @@ -5180,38 +5073,31 @@ static DisasJumpType op_sic(DisasContext *s, DisasO= ps *o) =20 static DisasJumpType op_rpcit(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 =3D tcg_const_i32(get_field(s, r1)); - TCGv_i32 r2 =3D tcg_const_i32(get_field(s, r2)); + TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r2 =3D tcg_constant_i32(get_field(s, r2)); =20 gen_helper_rpcit(cpu_env, r1, r2); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_pcistb(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 =3D tcg_const_i32(get_field(s, r1)); - TCGv_i32 r3 =3D tcg_const_i32(get_field(s, r3)); - TCGv_i32 ar =3D tcg_const_i32(get_field(s, b2)); + TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); + TCGv_i32 r3 =3D tcg_constant_i32(get_field(s, r3)); + TCGv_i32 ar =3D tcg_constant_i32(get_field(s, b2)); =20 gen_helper_pcistb(cpu_env, r1, r3, o->addr1, ar); - tcg_temp_free_i32(ar); - tcg_temp_free_i32(r1); - tcg_temp_free_i32(r3); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_mpcifc(DisasContext *s, DisasOps *o) { - TCGv_i32 r1 =3D tcg_const_i32(get_field(s, r1)); - TCGv_i32 ar =3D tcg_const_i32(get_field(s, b2)); + TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); + TCGv_i32 ar =3D tcg_constant_i32(get_field(s, b2)); =20 gen_helper_mpcifc(cpu_env, r1, o->addr1, ar); - tcg_temp_free_i32(ar); - tcg_temp_free_i32(r1); set_cc_static(s); return DISAS_NEXT; } @@ -6378,16 +6264,15 @@ static const DisasInsn *extract_insn(CPUS390XState = *env, DisasContext *s) =20 if (unlikely(s->ex_value)) { /* Drop the EX data now, so that it's clear on exception paths. */ - TCGv_i64 zero =3D tcg_const_i64(0); - int i; - tcg_gen_st_i64(zero, cpu_env, offsetof(CPUS390XState, ex_value)); - tcg_temp_free_i64(zero); + tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, + offsetof(CPUS390XState, ex_value)); =20 /* Extract the values saved by EXECUTE. */ insn =3D s->ex_value & 0xffffffffffff0000ull; ilen =3D s->ex_value & 0xf; - /* register insn bytes with translator so plugins work */ - for (i =3D 0; i < ilen; i++) { + + /* Register insn bytes with translator so plugins work. */ + for (int i =3D 0; i < ilen; i++) { uint8_t byte =3D extract64(insn, 56 - (i * 8), 8); translator_fake_ldb(byte, pc + i); } @@ -6512,9 +6397,8 @@ static DisasJumpType translate_one(CPUS390XState *env= , DisasContext *s) =20 #ifndef CONFIG_USER_ONLY if (s->base.tb->flags & FLAG_MASK_PER) { - TCGv_i64 addr =3D tcg_const_i64(s->base.pc_next); + TCGv_i64 addr =3D tcg_constant_i64(s->base.pc_next); gen_helper_per_ifetch(cpu_env, addr); - tcg_temp_free_i64(addr); } #endif =20 --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.30.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:30:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=45/fsZysA6znj3lsxas/Rtz/1l3A7Tl30S+1TTOT2Q4=; b=PFFLnpxbx8LbgoBOnaYmvfylDgfKEq8qJvFnc61Ac5vnuc+KFESW5yehPGAzS0SCb1 1uNhcoP0PA/Yid2010p5BbVGL6pE2T4rRuAuBfToDjbkb3KLdmv7dUEF4G5NRCX7QbHY AIcfCjVDZhMnQYNtYsVeUkf/cLHar1qlVk/2l1n+2MrgqKnX/5/ywTBHePYMgmcHpNJm JLM1GSUOl4/pahTwhy7moFJ4ksNfdKNy74YPLnEC4xOTpukUggiBtRCoD6uHyWXIkuAa 2TaoYG3Iq/leG0RGi7i74aMDlxxS/WlpZ89HrgoQm8TwG7zUxl8YZFGs4PRI13Ed+DDT gGYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=45/fsZysA6znj3lsxas/Rtz/1l3A7Tl30S+1TTOT2Q4=; b=4oXDIFKfdm1rSlBHswwSsRO98/Iq8o5yzbQzxs5x3ayyXQ437dlFUi6lGkAPkFAbQ5 61RDNa7SKzU9ioecjmJhRcChom9YyPeDIkL8DGSfCvM4+QHSQkkgDmZMZ0ipv8LCbyKU Sk7BFu5Z3/pAea/QPB8k6D1GZxlyGOQVeKnshi7xyow/HzWtxICcoguCXpxDng3V9jad pbm2tKpmpj5qfBq8IeqbF1dvoQqZZ+01E2o+ed9nNoBs/cBEnl/30w7D15sZv5C3TW0k SKUoELsaM5eJlm3kICphsDkoCC0nSoN387oiVNwhYVDRwtdpMEVSGWreuX+kakvBS7X2 iQyA== X-Gm-Message-State: AO0yUKXhi30epRchKZpUvBIpu3r47oUFjEVXUugsc7RtGIyE1mHqDTkC 4nvliQb+9+zbqysfKWnMXySqc4lfD4a8gX2rWgc= X-Google-Smtp-Source: AK7set+somlgUi3q0x6Qx0HwGYYk5/XSvRGD3dHGUFlD2hy5tqzBeDzLfsXd+86nLtl8xXVNFy9UDQ== X-Received: by 2002:a17:90b:1e4d:b0:233:e1e6:33d4 with SMTP id pi13-20020a17090b1e4d00b00233e1e633d4mr24713361pjb.47.1677475848005; Sun, 26 Feb 2023 21:30:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v2 56/76] target/s390x: Use tcg_constant_* for DisasCompare Date: Sun, 26 Feb 2023 19:24:45 -1000 Message-Id: <20230227052505.352889-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476618654100001 The a and b fields are not modified by the consumer, and while we need not free a constant, tcg will quietly ignore such frees, so free_compare need not be changed. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/s390x/tcg/translate.c | 44 ++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 3e3f685451..f2f2ea06eb 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -845,7 +845,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) c->is_64 =3D false; c->u.s32.a =3D tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(c->u.s32.a, cc_dst); - c->u.s32.b =3D tcg_const_i32(0); + c->u.s32.b =3D tcg_constant_i32(0); break; case CC_OP_LTGT_32: case CC_OP_LTUGTU_32: @@ -860,7 +860,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) case CC_OP_NZ: case CC_OP_FLOGR: c->u.s64.a =3D cc_dst; - c->u.s64.b =3D tcg_const_i64(0); + c->u.s64.b =3D tcg_constant_i64(0); c->g1 =3D true; break; case CC_OP_LTGT_64: @@ -874,14 +874,14 @@ static void disas_jcc(DisasContext *s, DisasCompare *= c, uint32_t mask) case CC_OP_TM_64: case CC_OP_ICM: c->u.s64.a =3D tcg_temp_new_i64(); - c->u.s64.b =3D tcg_const_i64(0); + c->u.s64.b =3D tcg_constant_i64(0); tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst); break; =20 case CC_OP_ADDU: case CC_OP_SUBU: c->is_64 =3D true; - c->u.s64.b =3D tcg_const_i64(0); + c->u.s64.b =3D tcg_constant_i64(0); c->g1 =3D true; switch (mask) { case 8 | 2: @@ -904,65 +904,65 @@ static void disas_jcc(DisasContext *s, DisasCompare *= c, uint32_t mask) switch (mask) { case 0x8 | 0x4 | 0x2: /* cc !=3D 3 */ cond =3D TCG_COND_NE; - c->u.s32.b =3D tcg_const_i32(3); + c->u.s32.b =3D tcg_constant_i32(3); break; case 0x8 | 0x4 | 0x1: /* cc !=3D 2 */ cond =3D TCG_COND_NE; - c->u.s32.b =3D tcg_const_i32(2); + c->u.s32.b =3D tcg_constant_i32(2); break; case 0x8 | 0x2 | 0x1: /* cc !=3D 1 */ cond =3D TCG_COND_NE; - c->u.s32.b =3D tcg_const_i32(1); + c->u.s32.b =3D tcg_constant_i32(1); break; case 0x8 | 0x2: /* cc =3D=3D 0 || cc =3D=3D 2 =3D> (cc & 1) =3D=3D= 0 */ cond =3D TCG_COND_EQ; c->g1 =3D false; c->u.s32.a =3D tcg_temp_new_i32(); - c->u.s32.b =3D tcg_const_i32(0); + c->u.s32.b =3D tcg_constant_i32(0); tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); break; case 0x8 | 0x4: /* cc < 2 */ cond =3D TCG_COND_LTU; - c->u.s32.b =3D tcg_const_i32(2); + c->u.s32.b =3D tcg_constant_i32(2); break; case 0x8: /* cc =3D=3D 0 */ cond =3D TCG_COND_EQ; - c->u.s32.b =3D tcg_const_i32(0); + c->u.s32.b =3D tcg_constant_i32(0); break; case 0x4 | 0x2 | 0x1: /* cc !=3D 0 */ cond =3D TCG_COND_NE; - c->u.s32.b =3D tcg_const_i32(0); + c->u.s32.b =3D tcg_constant_i32(0); break; case 0x4 | 0x1: /* cc =3D=3D 1 || cc =3D=3D 3 =3D> (cc & 1) !=3D 0= */ cond =3D TCG_COND_NE; c->g1 =3D false; c->u.s32.a =3D tcg_temp_new_i32(); - c->u.s32.b =3D tcg_const_i32(0); + c->u.s32.b =3D tcg_constant_i32(0); tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); break; case 0x4: /* cc =3D=3D 1 */ cond =3D TCG_COND_EQ; - c->u.s32.b =3D tcg_const_i32(1); + c->u.s32.b =3D tcg_constant_i32(1); break; case 0x2 | 0x1: /* cc > 1 */ cond =3D TCG_COND_GTU; - c->u.s32.b =3D tcg_const_i32(1); + c->u.s32.b =3D tcg_constant_i32(1); break; case 0x2: /* cc =3D=3D 2 */ cond =3D TCG_COND_EQ; - c->u.s32.b =3D tcg_const_i32(2); + c->u.s32.b =3D tcg_constant_i32(2); break; case 0x1: /* cc =3D=3D 3 */ cond =3D TCG_COND_EQ; - c->u.s32.b =3D tcg_const_i32(3); + c->u.s32.b =3D tcg_constant_i32(3); break; default: /* CC is masked by something else: (8 >> cc) & mask. */ cond =3D TCG_COND_NE; c->g1 =3D false; - c->u.s32.a =3D tcg_const_i32(8); - c->u.s32.b =3D tcg_const_i32(0); - tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op); + c->u.s32.a =3D tcg_temp_new_i32(); + c->u.s32.b =3D tcg_constant_i32(0); + tcg_gen_shr_i32(c->u.s32.a, tcg_constant_i32(8), cc_op); tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask); break; } @@ -1619,7 +1619,7 @@ static DisasJumpType op_bct32(DisasContext *s, DisasO= ps *o) tcg_gen_subi_i64(t, regs[r1], 1); store_reg32_i64(r1, t); c.u.s32.a =3D tcg_temp_new_i32(); - c.u.s32.b =3D tcg_const_i32(0); + c.u.s32.b =3D tcg_constant_i32(0); tcg_gen_extrl_i64_i32(c.u.s32.a, t); tcg_temp_free_i64(t); =20 @@ -1643,7 +1643,7 @@ static DisasJumpType op_bcth(DisasContext *s, DisasOp= s *o) tcg_gen_subi_i64(t, t, 1); store_reg32h_i64(r1, t); c.u.s32.a =3D tcg_temp_new_i32(); - c.u.s32.b =3D tcg_const_i32(0); + c.u.s32.b =3D tcg_constant_i32(0); tcg_gen_extrl_i64_i32(c.u.s32.a, t); tcg_temp_free_i64(t); =20 @@ -1664,7 +1664,7 @@ static DisasJumpType op_bct64(DisasContext *s, DisasO= ps *o) =20 tcg_gen_subi_i64(regs[r1], regs[r1], 1); c.u.s64.a =3D regs[r1]; - c.u.s64.b =3D tcg_const_i64(0); + c.u.s64.b =3D tcg_constant_i64(0); =20 return help_branch(s, &c, is_imm, imm, o->in2); } --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677476582; cv=none; d=zohomail.com; s=zohoarc; b=kM3xxZwxmi7fSx2ypdttYxyy6w54LISQVIc0S0zIvFwpteH6UKC0GqNOi10IEPBL7zBthGIv4dvNlJUzfPE4n+tXkqGjfz/v3B0F0Fiq7ziUtmlnLR5pZWRVZh4o3A5LMVlUt7HLF0h+f3iutMGyu7aSsbWeTYjtk2T8fVzTpe0= ARC-Message-Signature: i=1; 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/s390x/tcg/translate.c | 26 +------------------------- 1 file changed, 1 insertion(+), 25 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index f2f2ea06eb..811049ea28 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1790,7 +1790,7 @@ static TCGv_i32 fpinst_extract_m34(DisasContext *s, b= ool m3_with_fpe, return NULL; } =20 - return tcg_const_i32(deposit32(m3, 4, 4, m4)); + return tcg_constant_i32(deposit32(m3, 4, 4, m4)); } =20 static DisasJumpType op_cfeb(DisasContext *s, DisasOps *o) @@ -1801,7 +1801,6 @@ static DisasJumpType op_cfeb(DisasContext *s, DisasOp= s *o) return DISAS_NORETURN; } gen_helper_cfeb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1814,7 +1813,6 @@ static DisasJumpType op_cfdb(DisasContext *s, DisasOp= s *o) return DISAS_NORETURN; } gen_helper_cfdb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1827,7 +1825,6 @@ static DisasJumpType op_cfxb(DisasContext *s, DisasOp= s *o) return DISAS_NORETURN; } gen_helper_cfxb(o->out, cpu_env, o->in2_128, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1840,7 +1837,6 @@ static DisasJumpType op_cgeb(DisasContext *s, DisasOp= s *o) return DISAS_NORETURN; } gen_helper_cgeb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1853,7 +1849,6 @@ static DisasJumpType op_cgdb(DisasContext *s, DisasOp= s *o) return DISAS_NORETURN; } gen_helper_cgdb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1866,7 +1861,6 @@ static DisasJumpType op_cgxb(DisasContext *s, DisasOp= s *o) return DISAS_NORETURN; } gen_helper_cgxb(o->out, cpu_env, o->in2_128, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1879,7 +1873,6 @@ static DisasJumpType op_clfeb(DisasContext *s, DisasO= ps *o) return DISAS_NORETURN; } gen_helper_clfeb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1892,7 +1885,6 @@ static DisasJumpType op_clfdb(DisasContext *s, DisasO= ps *o) return DISAS_NORETURN; } gen_helper_clfdb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1905,7 +1897,6 @@ static DisasJumpType op_clfxb(DisasContext *s, DisasO= ps *o) return DISAS_NORETURN; } gen_helper_clfxb(o->out, cpu_env, o->in2_128, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1918,7 +1909,6 @@ static DisasJumpType op_clgeb(DisasContext *s, DisasO= ps *o) return DISAS_NORETURN; } gen_helper_clgeb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1931,7 +1921,6 @@ static DisasJumpType op_clgdb(DisasContext *s, DisasO= ps *o) return DISAS_NORETURN; } gen_helper_clgdb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1944,7 +1933,6 @@ static DisasJumpType op_clgxb(DisasContext *s, DisasO= ps *o) return DISAS_NORETURN; } gen_helper_clgxb(o->out, cpu_env, o->in2_128, m34); - tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; } @@ -1957,7 +1945,6 @@ static DisasJumpType op_cegb(DisasContext *s, DisasOp= s *o) return DISAS_NORETURN; } gen_helper_cegb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } =20 @@ -1969,7 +1956,6 @@ static DisasJumpType op_cdgb(DisasContext *s, DisasOp= s *o) return DISAS_NORETURN; } gen_helper_cdgb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } =20 @@ -1981,7 +1967,6 @@ static DisasJumpType op_cxgb(DisasContext *s, DisasOp= s *o) return DISAS_NORETURN; } gen_helper_cxgb(o->out_128, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } =20 @@ -1993,7 +1978,6 @@ static DisasJumpType op_celgb(DisasContext *s, DisasO= ps *o) return DISAS_NORETURN; } gen_helper_celgb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } =20 @@ -2005,7 +1989,6 @@ static DisasJumpType op_cdlgb(DisasContext *s, DisasO= ps *o) return DISAS_NORETURN; } gen_helper_cdlgb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } =20 @@ -2017,7 +2000,6 @@ static DisasJumpType op_cxlgb(DisasContext *s, DisasO= ps *o) return DISAS_NORETURN; } gen_helper_cxlgb(o->out_128, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } =20 @@ -2486,7 +2468,6 @@ static DisasJumpType op_fieb(DisasContext *s, DisasOp= s *o) return DISAS_NORETURN; } gen_helper_fieb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } =20 @@ -2498,7 +2479,6 @@ static DisasJumpType op_fidb(DisasContext *s, DisasOp= s *o) return DISAS_NORETURN; } gen_helper_fidb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } =20 @@ -2510,7 +2490,6 @@ static DisasJumpType op_fixb(DisasContext *s, DisasOp= s *o) return DISAS_NORETURN; } gen_helper_fixb(o->out_128, cpu_env, o->in2_128, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } =20 @@ -2785,7 +2764,6 @@ static DisasJumpType op_ledb(DisasContext *s, DisasOp= s *o) return DISAS_NORETURN; } gen_helper_ledb(o->out, cpu_env, o->in2, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } =20 @@ -2797,7 +2775,6 @@ static DisasJumpType op_ldxb(DisasContext *s, DisasOp= s *o) return DISAS_NORETURN; } gen_helper_ldxb(o->out, cpu_env, o->in2_128, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } =20 @@ -2809,7 +2786,6 @@ static DisasJumpType op_lexb(DisasContext *s, DisasOp= s *o) return DISAS_NORETURN; } gen_helper_lexb(o->out, cpu_env, o->in2_128, m34); - tcg_temp_free_i32(m34); return DISAS_NEXT; } =20 --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.30.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:30:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dNtcbq+YaAISCksJEqrwoDBG8G3LKrhNUHooAhzADaw=; b=cy2KakmRcc05GU65DCiEeJW37y203tp8VGEbrX1u31ms0cAz8dNItwz00KNwUCzT71 2wJUdC7Vx8DuMVXeFJMNrAcJh9vwM4CC39CzFtEkEyku9wJI04KkLcjAEHLSdsFJq9I5 EK9WlkU5TwlbvaCXq4He55BnmKi1ApIHFvzMhDvV6tEP/NPCJhbb4WSA4rVULhSs/9uM VAHq2UkAykOzNZE7Mqg0VKxtTNg1po23tocQrdr0ubQvtgxcQVVxgUqPamTRWizPZePC bme0SdakNf00E8Gut/u/jSeqw0TO9ORthgyk2oVvk3vjh75ivSt6dFZC8Yr/zsLFVakv dSKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dNtcbq+YaAISCksJEqrwoDBG8G3LKrhNUHooAhzADaw=; b=meVG06F/Sg64ScNTXxBZEHBUgrjdomZVKOW4TftNV9AmmmJlM8MZZpyfnuICHdKUyY JI23UdUuEHjUtTAXo5kMg0BTe/hfEPnVMFG9bRnZwz7sHU+AjXjtOHyxs6BvzrfreVEV UzZsbrgdYRnQ8jtb2OwOP0zNgNZhgXRIj1tXaZAQFsAGWveg2QFDvH21xSqfS8ucGPAG Pw7/68Atf7D+EKTPINPdfsweqrvQ2W0W1bNFDAsqBiaivUydqqd84Tyhc5L2pmi18tG4 CwuGwzKop7CshLgVqNJ70hO2j1cHCMlOod3oSArEjdsiyJ/CaXRGn4adKl5DFpTJqqat BaaQ== X-Gm-Message-State: AO0yUKUR2A8zXqSz4pEUkTL0gPueFG1dIoXYj3v+60ObLuaYjs221QL3 rYKCm+uTF4cqz6b1QFKK52kHdUIJMFiU7QfIfBk= X-Google-Smtp-Source: AK7set8r+oQvD92rznjjrN35ryr7UtVwiQelL/Nmqn3dnxt43nC1C4M9vdcQ2d8m2fVMjirv6B0icw== X-Received: by 2002:a17:90b:3b87:b0:233:fdfd:7122 with SMTP id pc7-20020a17090b3b8700b00233fdfd7122mr24742464pjb.37.1677475853836; Sun, 26 Feb 2023 21:30:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v2 58/76] target/s390x: Use tcg_constant_* in translate_vx.c.inc Date: Sun, 26 Feb 2023 19:24:47 -1000 Message-Id: <20230227052505.352889-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476478186100011 In most cases, this is a simple local allocate and free replaced by tcg_constant_*. In three cases, a variable temp was initialized with a constant value -- reorg to localize the constant. In gen_acc, this fixes a leak. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/s390x/tcg/translate_vx.c.inc | 45 +++++++++++++---------------- 1 file changed, 20 insertions(+), 25 deletions(-) diff --git a/target/s390x/tcg/translate_vx.c.inc b/target/s390x/tcg/transla= te_vx.c.inc index d39ee81cd6..3fadc82e5c 100644 --- a/target/s390x/tcg/translate_vx.c.inc +++ b/target/s390x/tcg/translate_vx.c.inc @@ -319,12 +319,10 @@ static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn= , uint8_t d, uint8_t a, static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 = ah, uint64_t b) { - TCGv_i64 bl =3D tcg_const_i64(b); - TCGv_i64 bh =3D tcg_const_i64(0); + TCGv_i64 bl =3D tcg_constant_i64(b); + TCGv_i64 bh =3D tcg_constant_i64(0); =20 tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); - tcg_temp_free_i64(bl); - tcg_temp_free_i64(bh); } =20 static DisasJumpType op_vbperm(DisasContext *s, DisasOps *o) @@ -609,9 +607,8 @@ static DisasJumpType op_vlei(DisasContext *s, DisasOps = *o) return DISAS_NORETURN; } =20 - tmp =3D tcg_const_i64((int16_t)get_field(s, i2)); + tmp =3D tcg_constant_i64((int16_t)get_field(s, i2)); write_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -1107,11 +1104,13 @@ static DisasJumpType op_vseg(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_vst(DisasContext *s, DisasOps *o) { - TCGv_i64 tmp =3D tcg_const_i64(16); + TCGv_i64 tmp; =20 /* Probe write access before actually modifying memory */ - gen_helper_probe_write_access(cpu_env, o->addr1, tmp); + gen_helper_probe_write_access(cpu_env, o->addr1, + tcg_constant_i64(16)); =20 + tmp =3D tcg_temp_new_i64(); read_vec_element_i64(tmp, get_field(s, v1), 0, ES_64); tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); @@ -1270,9 +1269,10 @@ static DisasJumpType op_vstm(DisasContext *s, DisasO= ps *o) } =20 /* Probe write access before actually modifying memory */ - tmp =3D tcg_const_i64((v3 - v1 + 1) * 16); - gen_helper_probe_write_access(cpu_env, o->addr1, tmp); + gen_helper_probe_write_access(cpu_env, o->addr1, + tcg_constant_i64((v3 - v1 + 1) * 16)); =20 + tmp =3D tcg_temp_new_i64(); for (;; v1++) { read_vec_element_i64(tmp, v1, 0, ES_64); tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); @@ -1359,7 +1359,7 @@ static DisasJumpType op_va(DisasContext *s, DisasOps = *o) static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, uint8_t es) { const uint8_t msb_bit_nr =3D NUM_VEC_ELEMENT_BITS(es) - 1; - TCGv_i64 msb_mask =3D tcg_const_i64(dup_const(es, 1ull << msb_bit_nr)); + TCGv_i64 msb_mask =3D tcg_constant_i64(dup_const(es, 1ull << msb_bit_n= r)); TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); TCGv_i64 t3 =3D tcg_temp_new_i64(); @@ -1416,7 +1416,7 @@ static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TC= Gv_i64 al, { TCGv_i64 th =3D tcg_temp_new_i64(); TCGv_i64 tl =3D tcg_temp_new_i64(); - TCGv_i64 zero =3D tcg_const_i64(0); + TCGv_i64 zero =3D tcg_constant_i64(0); =20 tcg_gen_add2_i64(tl, th, al, zero, bl, zero); tcg_gen_add2_i64(tl, th, th, zero, ah, zero); @@ -1425,7 +1425,6 @@ static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TC= Gv_i64 al, =20 tcg_temp_free_i64(th); tcg_temp_free_i64(tl); - tcg_temp_free_i64(zero); } =20 static DisasJumpType op_vacc(DisasContext *s, DisasOps *o) @@ -1455,15 +1454,14 @@ static void gen_ac2_i64(TCGv_i64 dl, TCGv_i64 dh, T= CGv_i64 al, TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh, TCGv_i64 cl, TCGv_i64 ch) { TCGv_i64 tl =3D tcg_temp_new_i64(); - TCGv_i64 th =3D tcg_const_i64(0); + TCGv_i64 zero =3D tcg_constant_i64(0); =20 /* extract the carry only */ tcg_gen_extract_i64(tl, cl, 0, 1); tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); - tcg_gen_add2_i64(dl, dh, dl, dh, tl, th); + tcg_gen_add2_i64(dl, dh, dl, dh, tl, zero); =20 tcg_temp_free_i64(tl); - tcg_temp_free_i64(th); } =20 static DisasJumpType op_vac(DisasContext *s, DisasOps *o) @@ -1484,7 +1482,7 @@ static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, T= CGv_i64 al, TCGv_i64 ah, { TCGv_i64 tl =3D tcg_temp_new_i64(); TCGv_i64 th =3D tcg_temp_new_i64(); - TCGv_i64 zero =3D tcg_const_i64(0); + TCGv_i64 zero =3D tcg_constant_i64(0); =20 tcg_gen_andi_i64(tl, cl, 1); tcg_gen_add2_i64(tl, th, tl, zero, al, zero); @@ -1495,7 +1493,6 @@ static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, T= CGv_i64 al, TCGv_i64 ah, =20 tcg_temp_free_i64(tl); tcg_temp_free_i64(th); - tcg_temp_free_i64(zero); } =20 static DisasJumpType op_vaccc(DisasContext *s, DisasOps *o) @@ -1597,14 +1594,13 @@ static void gen_avgl_i32(TCGv_i32 d, TCGv_i32 a, TC= Gv_i32 b) static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl) { TCGv_i64 dh =3D tcg_temp_new_i64(); - TCGv_i64 zero =3D tcg_const_i64(0); + TCGv_i64 zero =3D tcg_constant_i64(0); =20 tcg_gen_add2_i64(dl, dh, al, zero, bl, zero); gen_addi2_i64(dl, dh, dl, dh, 1); tcg_gen_extract2_i64(dl, dl, dh, 1); =20 tcg_temp_free_i64(dh); - tcg_temp_free_i64(zero); } =20 static DisasJumpType op_vavgl(DisasContext *s, DisasOps *o) @@ -2440,7 +2436,7 @@ static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, T= CGv_i64 al, { TCGv_i64 th =3D tcg_temp_new_i64(); TCGv_i64 tl =3D tcg_temp_new_i64(); - TCGv_i64 zero =3D tcg_const_i64(0); + TCGv_i64 zero =3D tcg_constant_i64(0); =20 tcg_gen_sub2_i64(tl, th, al, zero, bl, zero); tcg_gen_andi_i64(th, th, 1); @@ -2452,7 +2448,6 @@ static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, T= CGv_i64 al, =20 tcg_temp_free_i64(th); tcg_temp_free_i64(tl); - tcg_temp_free_i64(zero); } =20 static DisasJumpType op_vscbi(DisasContext *s, DisasOps *o) @@ -2572,11 +2567,12 @@ static DisasJumpType op_vsumq(DisasContext *s, Disa= sOps *o) return DISAS_NORETURN; } =20 - sumh =3D tcg_const_i64(0); + sumh =3D tcg_temp_new_i64(); suml =3D tcg_temp_new_i64(); - zero =3D tcg_const_i64(0); + zero =3D tcg_constant_i64(0); tmpl =3D tcg_temp_new_i64(); =20 + tcg_gen_mov_i64(sumh, zero); read_vec_element_i64(suml, get_field(s, v3), max_idx, es); for (idx =3D 0; idx <=3D max_idx; idx++) { read_vec_element_i64(tmpl, get_field(s, v2), idx, es); @@ -2587,7 +2583,6 @@ static DisasJumpType op_vsumq(DisasContext *s, DisasO= ps *o) =20 tcg_temp_free_i64(sumh); tcg_temp_free_i64(suml); - tcg_temp_free_i64(zero); tcg_temp_free_i64(tmpl); return DISAS_NEXT; } --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677475984; cv=none; d=zohomail.com; s=zohoarc; b=YMIu4J1GAbU1KT3ykGcNq82UtX9S9gX1aDu7FF/AQx7fSejO2/u5O3E7uhdk4PAVQn1dO4XbUhf7mNq9akxPfC9SR9lvO6Kk9y2ocDthL2XvhOGzDSA88FKD6q+dS+JWcLCGbGw/OW2Or/7H/KdLNEA2PlL0SMTiXXYJQajwwFo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677475984; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JVVeIuhjPjLUHH6q7jjqGdCcXDfNuJxyB7TieFblvRI=; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.30.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:30:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JVVeIuhjPjLUHH6q7jjqGdCcXDfNuJxyB7TieFblvRI=; b=KZFtDgUF81u4xLAUoPrH1ubwKL151a4Cjw7Q68GOIRg29nFd4p9Rc6hlVdrdjpZrH7 lWFU1TVcjzAwMUina+HfxZnr/SAoZuMe1PwQgQwFtmAQWZ/20lRQjzyc3IXy7As7Azym xB8EYVNZGnV767IYyeUCL+ElWfb0137Ex1xFfJZNR8xiA8EXWG8DX/qV88P+eQZ5UAZ7 VsWfhxTLy1lVpsQ6BHxj0oeD7gzB8y44fAu99RdvyCcLzCiFmDYcv0LnOxVP+IDDzw2P Hfv1Kh0xK7lxOOaNd9Id42qlGb/hZ7BSyPA8SQbhAtuqADNTr9EDEMk9cNrv2BNGxIe0 b0Sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JVVeIuhjPjLUHH6q7jjqGdCcXDfNuJxyB7TieFblvRI=; b=K/P6RXxwTLNboAB3Q80zSE8gsQMkclyj1w/oM6R5LW9QldwQOupKJwCM9oje2dlUhu Pk4yBgHs793+MECikeQ7GtfE6AIOAT7fSLGcFu84T3xo0Xh4QDbyxIS1Cm8f3Ij9chwu 49VLzi31tn3lW3RUpGVEmD+hSuDXgw9qZ+TOgDBBss5jvyNChsnQZ++UJWHxLQyvK11G DAOeXjbqpNFi/9/4e4Zq0lXnmDi+jg70txDGyyZVytGqljIGHnMtc8BShNalcFhnC0n4 RgkGSUXlJ3MI1FUS7oSRAWxB7S/QVGGR6VsNOLiDyfzbQAac745AWu0I8DQEJLINKSYG ECcQ== X-Gm-Message-State: AO0yUKUBdId4k3i1MvlEev3tNfyhAVdsEkocseYNJ+8A1/OMNQI+FKXe 18sj1OhDaq9N76NDXMkDoFlo9KWV9sTgfKrGsuE= X-Google-Smtp-Source: AK7set+Q3hExMVAjt0RzO5a/Jjc2gewA6lNoFZXWks5KpYpSfvvsZ9jEwWKjSvtUgBu0Wle5vxPFVg== X-Received: by 2002:a17:90b:3912:b0:234:41c:74cc with SMTP id ob18-20020a17090b391200b00234041c74ccmr27603196pjb.42.1677475856468; Sun, 26 Feb 2023 21:30:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 59/76] target/s390x: Drop free_compare Date: Sun, 26 Feb 2023 19:24:48 -1000 Message-Id: <20230227052505.352889-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475985770100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Remove the g1 and g2 members of DisasCompare, as they were used to track which temps needed to be freed. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/s390x/tcg/translate.c | 46 +----------------------------------- 1 file changed, 1 insertion(+), 45 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 811049ea28..76a1233946 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -156,8 +156,6 @@ struct DisasContext { typedef struct { TCGCond cond:8; bool is_64; - bool g1; - bool g2; union { struct { TCGv_i64 a, b; } s64; struct { TCGv_i32 a, b; } s32; @@ -722,7 +720,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) c->cond =3D (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER); c->u.s32.a =3D cc_op; c->u.s32.b =3D cc_op; - c->g1 =3D c->g2 =3D true; c->is_64 =3D false; return; } @@ -839,7 +836,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) =20 /* Load up the arguments of the comparison. */ c->is_64 =3D true; - c->g1 =3D c->g2 =3D false; switch (old_cc_op) { case CC_OP_LTGT0_32: c->is_64 =3D false; @@ -861,13 +857,11 @@ static void disas_jcc(DisasContext *s, DisasCompare *= c, uint32_t mask) case CC_OP_FLOGR: c->u.s64.a =3D cc_dst; c->u.s64.b =3D tcg_constant_i64(0); - c->g1 =3D true; break; case CC_OP_LTGT_64: case CC_OP_LTUGTU_64: c->u.s64.a =3D cc_src; c->u.s64.b =3D cc_dst; - c->g1 =3D c->g2 =3D true; break; =20 case CC_OP_TM_32: @@ -882,7 +876,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) case CC_OP_SUBU: c->is_64 =3D true; c->u.s64.b =3D tcg_constant_i64(0); - c->g1 =3D true; switch (mask) { case 8 | 2: case 4 | 1: /* result */ @@ -900,7 +893,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) case CC_OP_STATIC: c->is_64 =3D false; c->u.s32.a =3D cc_op; - c->g1 =3D true; switch (mask) { case 0x8 | 0x4 | 0x2: /* cc !=3D 3 */ cond =3D TCG_COND_NE; @@ -916,7 +908,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) break; case 0x8 | 0x2: /* cc =3D=3D 0 || cc =3D=3D 2 =3D> (cc & 1) =3D=3D= 0 */ cond =3D TCG_COND_EQ; - c->g1 =3D false; c->u.s32.a =3D tcg_temp_new_i32(); c->u.s32.b =3D tcg_constant_i32(0); tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); @@ -935,7 +926,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) break; case 0x4 | 0x1: /* cc =3D=3D 1 || cc =3D=3D 3 =3D> (cc & 1) !=3D 0= */ cond =3D TCG_COND_NE; - c->g1 =3D false; c->u.s32.a =3D tcg_temp_new_i32(); c->u.s32.b =3D tcg_constant_i32(0); tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); @@ -959,7 +949,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) default: /* CC is masked by something else: (8 >> cc) & mask. */ cond =3D TCG_COND_NE; - c->g1 =3D false; c->u.s32.a =3D tcg_temp_new_i32(); c->u.s32.b =3D tcg_constant_i32(0); tcg_gen_shr_i32(c->u.s32.a, tcg_constant_i32(8), cc_op); @@ -974,24 +963,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c= , uint32_t mask) c->cond =3D cond; } =20 -static void free_compare(DisasCompare *c) -{ - if (!c->g1) { - if (c->is_64) { - tcg_temp_free_i64(c->u.s64.a); - } else { - tcg_temp_free_i32(c->u.s32.a); - } - } - if (!c->g2) { - if (c->is_64) { - tcg_temp_free_i64(c->u.s64.b); - } else { - tcg_temp_free_i32(c->u.s32.b); - } - } -} - /* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ /* Define the insn format enumeration. */ #define F0(N) FMT_##N, @@ -1302,7 +1273,6 @@ static DisasJumpType help_branch(DisasContext *s, Dis= asCompare *c, } =20 egress: - free_compare(c); return ret; } =20 @@ -1612,8 +1582,6 @@ static DisasJumpType op_bct32(DisasContext *s, DisasO= ps *o) =20 c.cond =3D TCG_COND_NE; c.is_64 =3D false; - c.g1 =3D false; - c.g2 =3D false; =20 t =3D tcg_temp_new_i64(); tcg_gen_subi_i64(t, regs[r1], 1); @@ -1635,8 +1603,6 @@ static DisasJumpType op_bcth(DisasContext *s, DisasOp= s *o) =20 c.cond =3D TCG_COND_NE; c.is_64 =3D false; - c.g1 =3D false; - c.g2 =3D false; =20 t =3D tcg_temp_new_i64(); tcg_gen_shri_i64(t, regs[r1], 32); @@ -1659,8 +1625,6 @@ static DisasJumpType op_bct64(DisasContext *s, DisasO= ps *o) =20 c.cond =3D TCG_COND_NE; c.is_64 =3D true; - c.g1 =3D true; - c.g2 =3D false; =20 tcg_gen_subi_i64(regs[r1], regs[r1], 1); c.u.s64.a =3D regs[r1]; @@ -1680,8 +1644,6 @@ static DisasJumpType op_bx32(DisasContext *s, DisasOp= s *o) =20 c.cond =3D (s->insn->data ? TCG_COND_LE : TCG_COND_GT); c.is_64 =3D false; - c.g1 =3D false; - c.g2 =3D false; =20 t =3D tcg_temp_new_i64(); tcg_gen_add_i64(t, regs[r1], regs[r3]); @@ -1708,15 +1670,12 @@ static DisasJumpType op_bx64(DisasContext *s, Disas= Ops *o) =20 if (r1 =3D=3D (r3 | 1)) { c.u.s64.b =3D load_reg(r3 | 1); - c.g2 =3D false; } else { c.u.s64.b =3D regs[r3 | 1]; - c.g2 =3D true; } =20 tcg_gen_add_i64(regs[r1], regs[r1], regs[r3]); c.u.s64.a =3D regs[r1]; - c.g1 =3D true; =20 return help_branch(s, &c, is_imm, imm, o->in2); } @@ -1731,7 +1690,7 @@ static DisasJumpType op_cj(DisasContext *s, DisasOps = *o) if (s->insn->data) { c.cond =3D tcg_unsigned_cond(c.cond); } - c.is_64 =3D c.g1 =3D c.g2 =3D true; + c.is_64 =3D true; c.u.s64.a =3D o->in1; c.u.s64.b =3D o->in2; =20 @@ -2925,13 +2884,11 @@ static DisasJumpType op_loc(DisasContext *s, DisasO= ps *o) if (c.is_64) { tcg_gen_movcond_i64(c.cond, o->out, c.u.s64.a, c.u.s64.b, o->in2, o->in1); - free_compare(&c); } else { TCGv_i32 t32 =3D tcg_temp_new_i32(); TCGv_i64 t, z; =20 tcg_gen_setcond_i32(c.cond, t32, c.u.s32.a, c.u.s32.b); - free_compare(&c); =20 t =3D tcg_temp_new_i64(); tcg_gen_extu_i32_i64(t, t32); @@ -4022,7 +3979,6 @@ static DisasJumpType op_soc(DisasContext *s, DisasOps= *o) } else { tcg_gen_brcond_i32(c.cond, c.u.s32.a, c.u.s32.b, lab); } - free_compare(&c); =20 r1 =3D get_field(s, r1); a =3D get_address(s, 0, get_field(s, b2), get_field(s, d2)); --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677476344; cv=none; d=zohomail.com; s=zohoarc; b=nXL1c56Zo5LSu4hszfPF8NnlqC07p6LcfwEt/Oe7hWhTZdpIHbx0pCktjLRzCvMfLlX2183YXeYtiyJhbhK+203WBZDY+zcRtB1koaMDlPo7X+e1p374uZNVRJVk2UvxCSVryLK2awyA66Q9RVRWIXedBL08IjQG0eNeYNYg1I8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677476344; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ed+xbdwaWR3fX4nEbGB5qN69lYoTz9tc29ocx+a8CFw=; b=NVO0ReQml4VVO80ObgqcwoIX6g7CsRGblI/oYaAuXTo+ya0peqgW34qAITaxuA4bTRuUi9nv5PBIL1LuxI+TFfzp78MYuEmH1iwReuZuS4smEWU1ygHnwqJNlsvYKOCScWWOzFXYwRTVwxVkcFk7tlNmaR1RWPg/r3qxTIYelSk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677476344162794.5788400488648; Sun, 26 Feb 2023 21:39:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW7k-0001rO-2R; Mon, 27 Feb 2023 00:32:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW6M-0005CX-7v for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:31:07 -0500 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW6G-0000ls-Rv for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:31:05 -0500 Received: by mail-pl1-x633.google.com with SMTP id i10so5519896plr.9 for ; Sun, 26 Feb 2023 21:31:00 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.30.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:30:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ed+xbdwaWR3fX4nEbGB5qN69lYoTz9tc29ocx+a8CFw=; b=LIHyN5rLwjOaIG9ad1rjJ9Gl4a4I3VYOlRZkZBPwyWVeox22cNFdFLR1TwpJE5kZik Oo4K9Twqvw42qjzsD7w8MacGYeKRhVY3lFKf/UPt9622VtPNSMVC4lBNZqACpk69I7uA Wd2/JESuemc4h98xsTnjRo87csemYvFvFS5wkC1UYTaLjBRhlbbIrXRuGNqf8aoSvYpI TRpz3IM+c1kFHFL4mn8B5qj+p/ofu1CA722ck/pxRXOrwmWfH1wGDYcg/20BgNacsZ+c kp2r9crjlRV1pZOwoOtKF/2c2dY3J9rpP+rrIdz77eWfuiPKANW2qWmAofcPC3Nxir7j 4MXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ed+xbdwaWR3fX4nEbGB5qN69lYoTz9tc29ocx+a8CFw=; b=Cloi52maGEan5IDxR4RAv8pCLYjnLVwKQUmlX4U2NKYB5RzH/klrma1wu7oXY966qF HAdATo6FgwaWsEm5GzcammzTSGngCSBJmz+UoFlguFR+oGg1UTtJgwxmuFfX790CZTgu E8TVYs1T/lrB4Nq/EIrwXU9z4al0xJ/Vnpm07IY7smct2n4kXZJ+tombAbYtX67NLpsp tOgxBrf+Q81EXddDImUX2uHyrulNaIi1MXwziJfMQBtrDqxOu5/m3AfHJg/lxXBM7tlW Hv/j38D+doO9dbp47GIM5gbJwFgZG42hcDUxHhOB6QLID3QQ+cGiYLdLTK2/sA4o79cK OduQ== X-Gm-Message-State: AO0yUKUpV3zqct8+nohnjKjM9FIUtAIbTAsWH9oW+GMI1NSXG3Jo6UuP vWA9wDMv4m7nmHKDpkPcnMRU4539ioi/x9Wl29c= X-Google-Smtp-Source: AK7set8R90btrPAwpZQfkqJugt+YPu1diaBuGqVv2757rLJAKcXXZZwZq2vDCOWreZndUiU+yoxoiA== X-Received: by 2002:a17:90b:3ec6:b0:234:721e:51e5 with SMTP id rm6-20020a17090b3ec600b00234721e51e5mr7748860pjb.10.1677475859259; Sun, 26 Feb 2023 21:30:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 60/76] target/s390x: Drop tcg_temp_free from translate_vx.c.inc Date: Sun, 26 Feb 2023 19:24:49 -1000 Message-Id: <20230227052505.352889-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476345684100005 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/s390x/tcg/translate_vx.c.inc | 143 ---------------------------- 1 file changed, 143 deletions(-) diff --git a/target/s390x/tcg/translate_vx.c.inc b/target/s390x/tcg/transla= te_vx.c.inc index 3fadc82e5c..43dfbfd03f 100644 --- a/target/s390x/tcg/translate_vx.c.inc +++ b/target/s390x/tcg/translate_vx.c.inc @@ -183,8 +183,6 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8= _t reg, TCGv_i64 enr, /* generate the final ptr by adding cpu_env */ tcg_gen_trunc_i64_ptr(ptr, tmp); tcg_gen_add_ptr(ptr, ptr, cpu_env); - - tcg_temp_free_i64(tmp); } =20 #define gen_gvec_2(v1, v2, gen) \ @@ -272,13 +270,6 @@ static void gen_gvec128_3_i64(gen_gvec128_3_i64_fn fn,= uint8_t d, uint8_t a, fn(dl, dh, al, ah, bl, bh); write_vec_element_i64(dh, d, 0, ES_64); write_vec_element_i64(dl, d, 1, ES_64); - - tcg_temp_free_i64(dh); - tcg_temp_free_i64(dl); - tcg_temp_free_i64(ah); - tcg_temp_free_i64(al); - tcg_temp_free_i64(bh); - tcg_temp_free_i64(bl); } =20 typedef void (*gen_gvec128_4_i64_fn)(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, @@ -305,15 +296,6 @@ static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn,= uint8_t d, uint8_t a, fn(dl, dh, al, ah, bl, bh, cl, ch); write_vec_element_i64(dh, d, 0, ES_64); write_vec_element_i64(dl, d, 1, ES_64); - - tcg_temp_free_i64(dh); - tcg_temp_free_i64(dl); - tcg_temp_free_i64(ah); - tcg_temp_free_i64(al); - tcg_temp_free_i64(bh); - tcg_temp_free_i64(bl); - tcg_temp_free_i64(ch); - tcg_temp_free_i64(cl); } =20 static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 = ah, @@ -351,7 +333,6 @@ static DisasJumpType op_vge(DisasContext *s, DisasOps *= o) =20 tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); write_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -386,7 +367,6 @@ static DisasJumpType op_vgbm(DisasContext *s, DisasOps = *o) write_vec_element_i64(t, get_field(s, v1), 0, ES_64); tcg_gen_movi_i64(t, generate_byte_mask(i2)); write_vec_element_i64(t, get_field(s, v1), 1, ES_64); - tcg_temp_free_i64(t); } return DISAS_NEXT; } @@ -427,8 +407,6 @@ static DisasJumpType op_vl(DisasContext *s, DisasOps *o) tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - tcg_temp_free(t0); - tcg_temp_free(t1); return DISAS_NEXT; } =20 @@ -451,7 +429,6 @@ static DisasJumpType op_vlrep(DisasContext *s, DisasOps= *o) tmp =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); gen_gvec_dup_i64(es, get_field(s, v1), tmp); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -469,7 +446,6 @@ static DisasJumpType op_vlebr(DisasContext *s, DisasOps= *o) tmp =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_LE | es); write_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -486,7 +462,6 @@ static DisasJumpType op_vlbrrep(DisasContext *s, DisasO= ps *o) tmp =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_LE | es); gen_gvec_dup_i64(es, get_field(s, v1), tmp); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -518,7 +493,6 @@ static DisasJumpType op_vllebrz(DisasContext *s, DisasO= ps *o) =20 write_vec_element_i64(tmp, get_field(s, v1), 0, ES_64); write_vec_element_i64(tcg_constant_i64(0), get_field(s, v1), 1, ES_64); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -572,9 +546,6 @@ static DisasJumpType op_vlbr(DisasContext *s, DisasOps = *o) write: write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - - tcg_temp_free(t0); - tcg_temp_free(t1); return DISAS_NEXT; } =20 @@ -592,7 +563,6 @@ static DisasJumpType op_vle(DisasContext *s, DisasOps *= o) tmp =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); write_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -647,8 +617,6 @@ static DisasJumpType op_vler(DisasContext *s, DisasOps = *o) =20 write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - tcg_temp_free(t0); - tcg_temp_free(t1); return DISAS_NEXT; } =20 @@ -688,8 +656,6 @@ static DisasJumpType op_vlgv(DisasContext *s, DisasOps = *o) default: g_assert_not_reached(); } - tcg_temp_free_ptr(ptr); - return DISAS_NEXT; } =20 @@ -730,7 +696,6 @@ static DisasJumpType op_vllez(DisasContext *s, DisasOps= *o) tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es); gen_gvec_dup_imm(es, get_field(s, v1), 0); write_vec_element_i64(t, get_field(s, v1), enr, es); - tcg_temp_free_i64(t); return DISAS_NEXT; } =20 @@ -768,9 +733,6 @@ static DisasJumpType op_vlm(DisasContext *s, DisasOps *= o) =20 /* Store the last element, loaded first */ write_vec_element_i64(t0, v1, 1, ES_64); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); return DISAS_NEXT; } =20 @@ -794,8 +756,6 @@ static DisasJumpType op_vlbb(DisasContext *s, DisasOps = *o) =20 tcg_gen_addi_ptr(a0, cpu_env, v1_offs); gen_helper_vll(cpu_env, a0, o->addr1, bytes); - tcg_temp_free_i64(bytes); - tcg_temp_free_ptr(a0); return DISAS_NEXT; } =20 @@ -835,8 +795,6 @@ static DisasJumpType op_vlvg(DisasContext *s, DisasOps = *o) default: g_assert_not_reached(); } - tcg_temp_free_ptr(ptr); - return DISAS_NEXT; } =20 @@ -856,7 +814,6 @@ static DisasJumpType op_vll(DisasContext *s, DisasOps *= o) tcg_gen_addi_i64(o->in2, o->in2, 1); tcg_gen_addi_ptr(a0, cpu_env, v1_offs); gen_helper_vll(cpu_env, a0, o->addr1, o->in2); - tcg_temp_free_ptr(a0); return DISAS_NEXT; } =20 @@ -898,7 +855,6 @@ static DisasJumpType op_vmr(DisasContext *s, DisasOps *= o) write_vec_element_i64(tmp, v1, dst_idx, es); } } - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -974,7 +930,6 @@ static DisasJumpType op_vpk(DisasContext *s, DisasOps *= o) } write_vec_element_i64(tmp, v1, dst_idx, dst_es); } - tcg_temp_free_i64(tmp); } else { gen_gvec_3_ool(v1, v2, v3, 0, vpk[es - 1]); } @@ -1004,8 +959,6 @@ static DisasJumpType op_vpdi(DisasContext *s, DisasOps= *o) read_vec_element_i64(t1, get_field(s, v3), i3, ES_64); write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); return DISAS_NEXT; } =20 @@ -1057,7 +1010,6 @@ static DisasJumpType op_vsce(DisasContext *s, DisasOp= s *o) =20 read_vec_element_i64(tmp, get_field(s, v1), enr, es); tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -1098,7 +1050,6 @@ static DisasJumpType op_vseg(DisasContext *s, DisasOp= s *o) write_vec_element_i64(tmp, get_field(s, v1), 0, ES_64); read_vec_element_i64(tmp, get_field(s, v2), idx2, es | MO_SIGN); write_vec_element_i64(tmp, get_field(s, v1), 1, ES_64); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -1116,7 +1067,6 @@ static DisasJumpType op_vst(DisasContext *s, DisasOps= *o) gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); read_vec_element_i64(tmp, get_field(s, v1), 1, ES_64); tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -1134,7 +1084,6 @@ static DisasJumpType op_vstebr(DisasContext *s, Disas= Ops *o) tmp =3D tcg_temp_new_i64(); read_vec_element_i64(tmp, get_field(s, v1), enr, es); tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_LE | es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -1189,9 +1138,6 @@ write: tcg_gen_qemu_st_i64(t0, o->addr1, get_mem_index(s), MO_LEUQ); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); tcg_gen_qemu_st_i64(t1, o->addr1, get_mem_index(s), MO_LEUQ); - - tcg_temp_free(t0); - tcg_temp_free(t1); return DISAS_NEXT; } =20 @@ -1209,7 +1155,6 @@ static DisasJumpType op_vste(DisasContext *s, DisasOp= s *o) tmp =3D tcg_temp_new_i64(); read_vec_element_i64(tmp, get_field(s, v1), enr, es); tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -1251,9 +1196,6 @@ static DisasJumpType op_vster(DisasContext *s, DisasO= ps *o) tcg_gen_qemu_st_i64(t0, o->addr1, get_mem_index(s), MO_TEUQ); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); tcg_gen_qemu_st_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); - - tcg_temp_free(t0); - tcg_temp_free(t1); return DISAS_NEXT; } =20 @@ -1284,7 +1226,6 @@ static DisasJumpType op_vstm(DisasContext *s, DisasOp= s *o) } gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); } - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -1297,7 +1238,6 @@ static DisasJumpType op_vstl(DisasContext *s, DisasOp= s *o) tcg_gen_addi_i64(o->in2, o->in2, 1); tcg_gen_addi_ptr(a0, cpu_env, v1_offs); gen_helper_vstl(cpu_env, a0, o->addr1, o->in2); - tcg_temp_free_ptr(a0); return DISAS_NEXT; } =20 @@ -1335,7 +1275,6 @@ static DisasJumpType op_vup(DisasContext *s, DisasOps= *o) write_vec_element_i64(tmp, v1, dst_idx, dst_es); } } - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -1377,10 +1316,6 @@ static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64= b, uint8_t es) /* Isolate and shift the carry into position */ tcg_gen_and_i64(d, d, msb_mask); tcg_gen_shri_i64(d, d, msb_bit_nr); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); } =20 static void gen_acc8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) @@ -1399,7 +1334,6 @@ static void gen_acc_i32(TCGv_i32 d, TCGv_i32 a, TCGv_= i32 b) =20 tcg_gen_add_i32(t, a, b); tcg_gen_setcond_i32(TCG_COND_LTU, d, t, b); - tcg_temp_free_i32(t); } =20 static void gen_acc_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) @@ -1408,7 +1342,6 @@ static void gen_acc_i64(TCGv_i64 d, TCGv_i64 a, TCGv_= i64 b) =20 tcg_gen_add_i64(t, a, b); tcg_gen_setcond_i64(TCG_COND_LTU, d, t, b); - tcg_temp_free_i64(t); } =20 static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, @@ -1422,9 +1355,6 @@ static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TC= Gv_i64 al, tcg_gen_add2_i64(tl, th, th, zero, ah, zero); tcg_gen_add2_i64(tl, dl, tl, th, bh, zero); tcg_gen_mov_i64(dh, zero); - - tcg_temp_free_i64(th); - tcg_temp_free_i64(tl); } =20 static DisasJumpType op_vacc(DisasContext *s, DisasOps *o) @@ -1460,8 +1390,6 @@ static void gen_ac2_i64(TCGv_i64 dl, TCGv_i64 dh, TCG= v_i64 al, TCGv_i64 ah, tcg_gen_extract_i64(tl, cl, 0, 1); tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); tcg_gen_add2_i64(dl, dh, dl, dh, tl, zero); - - tcg_temp_free_i64(tl); } =20 static DisasJumpType op_vac(DisasContext *s, DisasOps *o) @@ -1490,9 +1418,6 @@ static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, T= CGv_i64 al, TCGv_i64 ah, tcg_gen_add2_i64(tl, th, th, zero, ah, zero); tcg_gen_add2_i64(tl, dl, tl, th, bh, zero); tcg_gen_mov_i64(dh, zero); - - tcg_temp_free_i64(tl); - tcg_temp_free_i64(th); } =20 static DisasJumpType op_vaccc(DisasContext *s, DisasOps *o) @@ -1533,9 +1458,6 @@ static void gen_avg_i32(TCGv_i32 d, TCGv_i32 a, TCGv_= i32 b) tcg_gen_addi_i64(t0, t0, 1); tcg_gen_shri_i64(t0, t0, 1); tcg_gen_extrl_i64_i32(d, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_avg_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl) @@ -1550,10 +1472,6 @@ static void gen_avg_i64(TCGv_i64 dl, TCGv_i64 al, TC= Gv_i64 bl) tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); gen_addi2_i64(dl, dh, dl, dh, 1); tcg_gen_extract2_i64(dl, dl, dh, 1); - - tcg_temp_free_i64(dh); - tcg_temp_free_i64(ah); - tcg_temp_free_i64(bh); } =20 static DisasJumpType op_vavg(DisasContext *s, DisasOps *o) @@ -1586,9 +1504,6 @@ static void gen_avgl_i32(TCGv_i32 d, TCGv_i32 a, TCGv= _i32 b) tcg_gen_addi_i64(t0, t0, 1); tcg_gen_shri_i64(t0, t0, 1); tcg_gen_extrl_i64_i32(d, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl) @@ -1599,8 +1514,6 @@ static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TC= Gv_i64 bl) tcg_gen_add2_i64(dl, dh, al, zero, bl, zero); gen_addi2_i64(dl, dh, dl, dh, 1); tcg_gen_extract2_i64(dl, dl, dh, 1); - - tcg_temp_free_i64(dh); } =20 static DisasJumpType op_vavgl(DisasContext *s, DisasOps *o) @@ -1635,9 +1548,6 @@ static DisasJumpType op_vcksm(DisasContext *s, DisasO= ps *o) } gen_gvec_dup_imm(ES_32, get_field(s, v1), 0); write_vec_element_i32(sum, get_field(s, v1), 1, ES_32); - - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(sum); return DISAS_NEXT; } =20 @@ -1682,9 +1592,6 @@ static DisasJumpType op_vc(DisasContext *s, DisasOps = *o) read_vec_element_i64(high, get_field(s, v1), 0, ES_64); read_vec_element_i64(low, get_field(s, v1), 1, ES_64); gen_op_update2_cc_i64(s, CC_OP_VC, low, high); - - tcg_temp_free_i64(low); - tcg_temp_free_i64(high); } return DISAS_NEXT; } @@ -1853,8 +1760,6 @@ static void gen_mal_i32(TCGv_i32 d, TCGv_i32 a, TCGv_= i32 b, TCGv_i32 c) =20 tcg_gen_mul_i32(t0, a, b); tcg_gen_add_i32(d, t0, c); - - tcg_temp_free_i32(t0); } =20 static void gen_mah_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c) @@ -1869,10 +1774,6 @@ static void gen_mah_i32(TCGv_i32 d, TCGv_i32 a, TCGv= _i32 b, TCGv_i32 c) tcg_gen_mul_i64(t0, t0, t1); tcg_gen_add_i64(t0, t0, t2); tcg_gen_extrh_i64_i32(d, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } =20 static void gen_malh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c) @@ -1887,10 +1788,6 @@ static void gen_malh_i32(TCGv_i32 d, TCGv_i32 a, TCG= v_i32 b, TCGv_i32 c) tcg_gen_mul_i64(t0, t0, t1); tcg_gen_add_i64(t0, t0, t2); tcg_gen_extrh_i64_i32(d, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } =20 static DisasJumpType op_vma(DisasContext *s, DisasOps *o) @@ -1974,7 +1871,6 @@ static void gen_mh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i= 32 b) TCGv_i32 t =3D tcg_temp_new_i32(); =20 tcg_gen_muls2_i32(t, d, a, b); - tcg_temp_free_i32(t); } =20 static void gen_mlh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) @@ -1982,7 +1878,6 @@ static void gen_mlh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_= i32 b) TCGv_i32 t =3D tcg_temp_new_i32(); =20 tcg_gen_mulu2_i32(t, d, a, b); - tcg_temp_free_i32(t); } =20 static DisasJumpType op_vm(DisasContext *s, DisasOps *o) @@ -2099,11 +1994,6 @@ static DisasJumpType op_vmsl(DisasContext *s, DisasO= ps *o) /* Store final result into v1. */ write_vec_element_i64(h1, get_field(s, v1), 0, ES_64); write_vec_element_i64(l1, get_field(s, v1), 1, ES_64); - - tcg_temp_free_i64(l1); - tcg_temp_free_i64(h1); - tcg_temp_free_i64(l2); - tcg_temp_free_i64(h2); return DISAS_NEXT; } =20 @@ -2169,8 +2059,6 @@ static void gen_rim_i32(TCGv_i32 d, TCGv_i32 a, TCGv_= i32 b, int32_t c) tcg_gen_and_i32(t, t, b); tcg_gen_andc_i32(d, d, b); tcg_gen_or_i32(d, d, t); - - tcg_temp_free_i32(t); } =20 static void gen_rim_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, int64_t c) @@ -2181,8 +2069,6 @@ static void gen_rim_i64(TCGv_i64 d, TCGv_i64 a, TCGv_= i64 b, int64_t c) tcg_gen_and_i64(t, t, b); tcg_gen_andc_i64(d, d, b); tcg_gen_or_i64(d, d, t); - - tcg_temp_free_i64(t); } =20 static DisasJumpType op_verim(DisasContext *s, DisasOps *o) @@ -2291,7 +2177,6 @@ static DisasJumpType op_ves(DisasContext *s, DisasOps= *o) default: g_assert_not_reached(); } - tcg_temp_free_i32(shift); } return DISAS_NEXT; } @@ -2311,7 +2196,6 @@ static DisasJumpType gen_vsh_by_byte(DisasContext *s,= DisasOps *o, read_vec_element_i64(shift, get_field(s, v3), 7, ES_8); tcg_gen_andi_i64(shift, shift, byte ? 0x78 : 7); gen_gvec_2i_ool(get_field(s, v1), get_field(s, v2), shift, 0, gen); - tcg_temp_free_i64(shift); } return DISAS_NEXT; } @@ -2367,10 +2251,6 @@ static DisasJumpType op_vsld(DisasContext *s, DisasO= ps *o) =20 write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); return DISAS_NEXT; } =20 @@ -2397,10 +2277,6 @@ static DisasJumpType op_vsrd(DisasContext *s, DisasO= ps *o) =20 write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); return DISAS_NEXT; } =20 @@ -2445,9 +2321,6 @@ static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, T= CGv_i64 al, /* "invert" the result: -1 -> 0; 0 -> 1 */ tcg_gen_addi_i64(dl, th, 1); tcg_gen_mov_i64(dh, zero); - - tcg_temp_free_i64(th); - tcg_temp_free_i64(tl); } =20 static DisasJumpType op_vscbi(DisasContext *s, DisasOps *o) @@ -2482,8 +2355,6 @@ static void gen_sbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TC= Gv_i64 al, TCGv_i64 ah, tcg_gen_not_i64(tl, bl); tcg_gen_not_i64(th, bh); gen_ac2_i64(dl, dh, al, ah, tl, th, cl, ch); - tcg_temp_free_i64(tl); - tcg_temp_free_i64(th); } =20 static DisasJumpType op_vsbi(DisasContext *s, DisasOps *o) @@ -2508,9 +2379,6 @@ static void gen_sbcbi2_i64(TCGv_i64 dl, TCGv_i64 dh, = TCGv_i64 al, TCGv_i64 ah, tcg_gen_not_i64(tl, bl); tcg_gen_not_i64(th, bh); gen_accc2_i64(dl, dh, al, ah, tl, th, cl, ch); - - tcg_temp_free_i64(tl); - tcg_temp_free_i64(th); } =20 static DisasJumpType op_vsbcbi(DisasContext *s, DisasOps *o) @@ -2550,8 +2418,6 @@ static DisasJumpType op_vsumg(DisasContext *s, DisasO= ps *o) } write_vec_element_i64(sum, get_field(s, v1), dst_idx, ES_64); } - tcg_temp_free_i64(sum); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -2580,10 +2446,6 @@ static DisasJumpType op_vsumq(DisasContext *s, Disas= Ops *o) } write_vec_element_i64(sumh, get_field(s, v1), 0, ES_64); write_vec_element_i64(suml, get_field(s, v1), 1, ES_64); - - tcg_temp_free_i64(sumh); - tcg_temp_free_i64(suml); - tcg_temp_free_i64(tmpl); return DISAS_NEXT; } =20 @@ -2611,8 +2473,6 @@ static DisasJumpType op_vsum(DisasContext *s, DisasOp= s *o) } write_vec_element_i32(sum, get_field(s, v1), dst_idx, ES_32); } - tcg_temp_free_i32(sum); - tcg_temp_free_i32(tmp); return DISAS_NEXT; } =20 @@ -3399,9 +3259,6 @@ static DisasJumpType op_vfpso(DisasContext *s, DisasO= ps *o) read_vec_element_i64(tmp, v2, 1, ES_64); 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Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/s390x/tcg/translate.c | 105 ----------------------------------- 1 file changed, 105 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 76a1233946..beccd3429e 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -306,8 +306,6 @@ static TCGv_i128 load_freg_128(int reg) TCGv_i128 r =3D tcg_temp_new_i128(); =20 tcg_gen_concat_i64_i128(r, l, h); - tcg_temp_free_i64(h); - tcg_temp_free_i64(l); return r; } =20 @@ -1263,10 +1261,8 @@ static DisasJumpType help_branch(DisasContext *s, Di= sasCompare *c, TCGv_i64 z =3D tcg_constant_i64(0); tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b); tcg_gen_extu_i32_i64(t1, t0); - tcg_temp_free_i32(t0); tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next); per_branch_cond(s, TCG_COND_NE, t1, z); - tcg_temp_free_i64(t1); } =20 ret =3D DISAS_PC_UPDATED; @@ -1525,7 +1521,6 @@ static void save_link_info(DisasContext *s, DisasOps = *o) tcg_gen_extu_i32_i64(t, cc_op); tcg_gen_shli_i64(t, t, 28); tcg_gen_or_i64(o->out, o->out, t); - tcg_temp_free_i64(t); } =20 static DisasJumpType op_bal(DisasContext *s, DisasOps *o) @@ -1589,7 +1584,6 @@ static DisasJumpType op_bct32(DisasContext *s, DisasO= ps *o) c.u.s32.a =3D tcg_temp_new_i32(); c.u.s32.b =3D tcg_constant_i32(0); tcg_gen_extrl_i64_i32(c.u.s32.a, t); - tcg_temp_free_i64(t); =20 return help_branch(s, &c, is_imm, imm, o->in2); } @@ -1611,7 +1605,6 @@ static DisasJumpType op_bcth(DisasContext *s, DisasOp= s *o) c.u.s32.a =3D tcg_temp_new_i32(); c.u.s32.b =3D tcg_constant_i32(0); tcg_gen_extrl_i64_i32(c.u.s32.a, t); - tcg_temp_free_i64(t); =20 return help_branch(s, &c, 1, imm, o->in2); } @@ -1652,7 +1645,6 @@ static DisasJumpType op_bx32(DisasContext *s, DisasOp= s *o) tcg_gen_extrl_i64_i32(c.u.s32.a, t); tcg_gen_extrl_i64_i32(c.u.s32.b, regs[r3 | 1]); store_reg32_i64(r1, t); - tcg_temp_free_i64(t); =20 return help_branch(s, &c, is_imm, imm, o->in2); } @@ -1971,11 +1963,9 @@ static DisasJumpType op_cksm(DisasContext *s, DisasO= ps *o) gen_helper_cksm(pair, cpu_env, o->in1, o->in2, regs[r2 + 1]); set_cc_static(s); tcg_gen_extr_i128_i64(o->out, len, pair); - tcg_temp_free_i128(pair); =20 tcg_gen_add_i64(regs[r2], regs[r2], len); tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len); - tcg_temp_free_i64(len); =20 return DISAS_NEXT; } @@ -2077,7 +2067,6 @@ static DisasJumpType op_clm(DisasContext *s, DisasOps= *o) tcg_gen_extrl_i64_i32(t1, o->in1); gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2); set_cc_static(s); - tcg_temp_free_i32(t1); return DISAS_NEXT; } =20 @@ -2087,7 +2076,6 @@ static DisasJumpType op_clst(DisasContext *s, DisasOp= s *o) =20 gen_helper_clst(pair, cpu_env, regs[0], o->in1, o->in2); tcg_gen_extr_i128_i64(o->in2, o->in1, pair); - tcg_temp_free_i128(pair); =20 set_cc_static(s); return DISAS_NEXT; @@ -2099,7 +2087,6 @@ static DisasJumpType op_cps(DisasContext *s, DisasOps= *o) tcg_gen_andi_i64(t, o->in1, 0x8000000000000000ull); tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull); tcg_gen_or_i64(o->out, o->out, t); - tcg_temp_free_i64(t); return DISAS_NEXT; } =20 @@ -2115,14 +2102,12 @@ static DisasJumpType op_cs(DisasContext *s, DisasOp= s *o) addr =3D get_address(s, 0, b2, d2); tcg_gen_atomic_cmpxchg_i64(o->out, addr, o->in2, o->in1, get_mem_index(s), s->insn->data | MO_ALIGN); - tcg_temp_free_i64(addr); =20 /* Are the memory and expected values (un)equal? Note that this setco= nd produces the output CC value, thus the NE sense of the test. */ cc =3D tcg_temp_new_i64(); tcg_gen_setcond_i64(TCG_COND_NE, cc, o->in2, o->out); tcg_gen_extrl_i64_i32(cc_op, cc); - tcg_temp_free_i64(cc); set_cc_static(s); =20 return DISAS_NEXT; @@ -2182,7 +2167,6 @@ static DisasJumpType op_csp(DisasContext *s, DisasOps= *o) tcg_gen_andi_i64(addr, o->in2, -1ULL << (mop & MO_SIZE)); tcg_gen_atomic_cmpxchg_i64(old, addr, o->in1, o->out2, get_mem_index(s), mop | MO_ALIGN); - tcg_temp_free_i64(addr); =20 /* Are the memory and expected values (un)equal? */ cc =3D tcg_temp_new_i64(); @@ -2196,14 +2180,12 @@ static DisasJumpType op_csp(DisasContext *s, DisasO= ps *o) } else { tcg_gen_mov_i64(o->out, old); } - tcg_temp_free_i64(old); =20 /* If the comparison was equal, and the LSB of R2 was set, then we need to flush the TLB (for all cpus). */ tcg_gen_xori_i64(cc, cc, 1); tcg_gen_and_i64(cc, cc, o->in2); tcg_gen_brcondi_i64(TCG_COND_EQ, cc, 0, lab); - tcg_temp_free_i64(cc); =20 gen_helper_purge(cpu_env); gen_set_label(lab); @@ -2218,9 +2200,7 @@ static DisasJumpType op_cvd(DisasContext *s, DisasOps= *o) TCGv_i32 t2 =3D tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(t2, o->in1); gen_helper_cvd(t1, t2); - tcg_temp_free_i32(t2); tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s)); - tcg_temp_free_i64(t1); return DISAS_NEXT; } =20 @@ -2322,7 +2302,6 @@ static DisasJumpType op_divs64(DisasContext *s, Disas= Ops *o) =20 gen_helper_divs64(t, cpu_env, o->in1, o->in2); tcg_gen_extr_i128_i64(o->out2, o->out, t); - tcg_temp_free_i128(t); return DISAS_NEXT; } =20 @@ -2332,7 +2311,6 @@ static DisasJumpType op_divu64(DisasContext *s, Disas= Ops *o) =20 gen_helper_divu64(t, cpu_env, o->out, o->out2, o->in2); tcg_gen_extr_i128_i64(o->out2, o->out, t); - tcg_temp_free_i128(t); return DISAS_NEXT; } =20 @@ -2387,8 +2365,6 @@ static DisasJumpType op_epsw(DisasContext *s, DisasOp= s *o) if (r2 !=3D 0) { store_reg32_i64(r2, psw_mask); } - - tcg_temp_free_i64(t); return DISAS_NEXT; } =20 @@ -2528,7 +2504,6 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps= *o) =20 tcg_gen_movi_i64(tmp, ccm); gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -2551,8 +2526,6 @@ static DisasJumpType op_ipm(DisasContext *s, DisasOps= *o) tcg_gen_extu_i32_i64(t2, cc_op); tcg_gen_deposit_i64(t1, t1, t2, 4, 60); tcg_gen_deposit_i64(o->out, o->out, t1, 24, 8); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); return DISAS_NEXT; } =20 @@ -2892,11 +2865,9 @@ static DisasJumpType op_loc(DisasContext *s, DisasOp= s *o) =20 t =3D tcg_temp_new_i64(); tcg_gen_extu_i32_i64(t, t32); - tcg_temp_free_i32(t32); =20 z =3D tcg_constant_i64(0); tcg_gen_movcond_i64(TCG_COND_NE, o->out, t, z, o->in2, o->in1); - tcg_temp_free_i64(t); } =20 return DISAS_NEXT; @@ -2953,8 +2924,6 @@ static DisasJumpType op_lpsw(DisasContext *s, DisasOp= s *o) /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */ tcg_gen_shli_i64(t1, t1, 32); gen_helper_load_psw(cpu_env, t1, t2); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); return DISAS_NORETURN; } =20 @@ -2971,8 +2940,6 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasO= ps *o) tcg_gen_addi_i64(o->in2, o->in2, 8); tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s)); gen_helper_load_psw(cpu_env, t1, t2); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); return DISAS_NORETURN; } #endif @@ -2997,7 +2964,6 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOp= s *o) if (unlikely(r1 =3D=3D r3)) { tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); store_reg32_i64(r1, t1); - tcg_temp_free(t1); return DISAS_NEXT; } =20 @@ -3012,8 +2978,6 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOp= s *o) =20 /* Only two registers to read. */ if (((r1 + 1) & 15) =3D=3D r3) { - tcg_temp_free(t2); - tcg_temp_free(t1); return DISAS_NEXT; } =20 @@ -3026,9 +2990,6 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOp= s *o) tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); store_reg32_i64(r1, t1); } - tcg_temp_free(t2); - tcg_temp_free(t1); - return DISAS_NEXT; } =20 @@ -3043,7 +3004,6 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps= *o) if (unlikely(r1 =3D=3D r3)) { tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); store_reg32h_i64(r1, t1); - tcg_temp_free(t1); return DISAS_NEXT; } =20 @@ -3058,8 +3018,6 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps= *o) =20 /* Only two registers to read. */ if (((r1 + 1) & 15) =3D=3D r3) { - tcg_temp_free(t2); - tcg_temp_free(t1); return DISAS_NEXT; } =20 @@ -3072,9 +3030,6 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps= *o) tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); store_reg32h_i64(r1, t1); } - tcg_temp_free(t2); - tcg_temp_free(t1); - return DISAS_NEXT; } =20 @@ -3098,11 +3053,9 @@ static DisasJumpType op_lm64(DisasContext *s, DisasO= ps *o) tcg_gen_addi_i64(t2, o->in2, 8 * ((r3 - r1) & 15)); tcg_gen_qemu_ld64(regs[r3], t2, get_mem_index(s)); tcg_gen_mov_i64(regs[r1], t1); - tcg_temp_free(t2); =20 /* Only two registers to read. */ if (((r1 + 1) & 15) =3D=3D r3) { - tcg_temp_free(t1); return DISAS_NEXT; } =20 @@ -3114,8 +3067,6 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOp= s *o) tcg_gen_add_i64(o->in2, o->in2, t1); tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s)); } - tcg_temp_free(t1); - return DISAS_NEXT; } =20 @@ -3137,8 +3088,6 @@ static DisasJumpType op_lpd(DisasContext *s, DisasOps= *o) a2 =3D get_address(s, 0, get_field(s, b2), get_field(s, d2)); tcg_gen_qemu_ld_i64(o->out, a1, get_mem_index(s), mop | MO_ALIGN); tcg_gen_qemu_ld_i64(o->out2, a2, get_mem_index(s), mop | MO_ALIGN); - tcg_temp_free_i64(a1); - tcg_temp_free_i64(a2); =20 /* ... and indicate that we performed them while interlocked. */ gen_op_movi_cc(s, 0); @@ -3246,8 +3195,6 @@ static DisasJumpType op_mov2e(DisasContext *s, DisasO= ps *o) } =20 tcg_gen_st32_i64(ar1, cpu_env, offsetof(CPUS390XState, aregs[1])); - tcg_temp_free_i64(ar1); - return DISAS_NEXT; } =20 @@ -3466,7 +3413,6 @@ static DisasJumpType op_maeb(DisasContext *s, DisasOp= s *o) { TCGv_i64 r3 =3D load_freg32_i64(get_field(s, r3)); gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3); - tcg_temp_free_i64(r3); return DISAS_NEXT; } =20 @@ -3474,7 +3420,6 @@ static DisasJumpType op_madb(DisasContext *s, DisasOp= s *o) { TCGv_i64 r3 =3D load_freg(get_field(s, r3)); gen_helper_madb(o->out, cpu_env, o->in1, o->in2, r3); - tcg_temp_free_i64(r3); return DISAS_NEXT; } =20 @@ -3482,7 +3427,6 @@ static DisasJumpType op_mseb(DisasContext *s, DisasOp= s *o) { TCGv_i64 r3 =3D load_freg32_i64(get_field(s, r3)); gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3); - tcg_temp_free_i64(r3); return DISAS_NEXT; } =20 @@ -3490,7 +3434,6 @@ static DisasJumpType op_msdb(DisasContext *s, DisasOp= s *o) { TCGv_i64 r3 =3D load_freg(get_field(s, r3)); gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, r3); - tcg_temp_free_i64(r3); return DISAS_NEXT; } =20 @@ -3501,7 +3444,6 @@ static DisasJumpType op_nabs(DisasContext *s, DisasOp= s *o) =20 tcg_gen_neg_i64(n, o->in2); tcg_gen_movcond_i64(TCG_COND_GE, o->out, o->in2, z, n, o->in2); - tcg_temp_free_i64(n); return DISAS_NEXT; } =20 @@ -3836,9 +3778,6 @@ static DisasJumpType op_rll32(DisasContext *s, DisasO= ps *o) tcg_gen_extrl_i64_i32(t2, o->in2); tcg_gen_rotl_i32(to, t1, t2); tcg_gen_extu_i32_i64(o->out, to); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(to); return DISAS_NEXT; } =20 @@ -3993,12 +3932,10 @@ static DisasJumpType op_soc(DisasContext *s, DisasO= ps *o) h =3D tcg_temp_new_i64(); tcg_gen_shri_i64(h, regs[r1], 32); tcg_gen_qemu_st32(h, a, get_mem_index(s)); - tcg_temp_free_i64(h); break; default: g_assert_not_reached(); } - tcg_temp_free_i64(a); =20 gen_set_label(lab); return DISAS_NEXT; @@ -4015,9 +3952,6 @@ static DisasJumpType op_sla(DisasContext *s, DisasOps= *o) t =3D o->in1; } gen_op_update2_cc_i64(s, CC_OP_SLA, t, o->in2); - if (s->insn->data =3D=3D 31) { - tcg_temp_free_i64(t); - } tcg_gen_shl_i64(o->out, o->in1, o->in2); /* The arithmetic left shift is curious in that it does not affect the sign bit. Copy that over from the source unchanged. */ @@ -4084,8 +4018,6 @@ static DisasJumpType op_srnmt(DisasContext *s, DisasO= ps *o) tcg_gen_ld32u_i64(tmp, cpu_env, offsetof(CPUS390XState, fpc)); tcg_gen_deposit_i64(tmp, tmp, o->addr1, 4, 3); tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUS390XState, fpc)); - - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -4126,8 +4058,6 @@ static DisasJumpType op_ectg(DisasContext *s, DisasOp= s *o) =20 /* store second operand in GR1 */ tcg_gen_mov_i64(regs[1], o->in2); - - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -4187,9 +4117,6 @@ static DisasJumpType op_stcke(DisasContext *s, DisasO= ps *o) tcg_gen_qemu_st64(c1, o->in2, get_mem_index(s)); tcg_gen_addi_i64(o->in2, o->in2, 8); tcg_gen_qemu_st64(c2, o->in2, get_mem_index(s)); - tcg_temp_free_i64(c1); - tcg_temp_free_i64(c2); - tcg_temp_free_i64(todpr); /* ??? We don't implement clock states. */ gen_op_movi_cc(s, 0); return DISAS_NEXT; @@ -4403,7 +4330,6 @@ static DisasJumpType op_stnosm(DisasContext *s, Disas= Ops *o) t =3D tcg_temp_new_i64(); tcg_gen_shri_i64(t, psw_mask, 56); tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s)); - tcg_temp_free_i64(t); =20 if (s->fields.op =3D=3D 0xac) { tcg_gen_andi_i64(psw_mask, psw_mask, @@ -4514,7 +4440,6 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOp= s *o) } break; } - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -4558,8 +4483,6 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOp= s *o) tcg_gen_add_i64(o->in2, o->in2, t4); r1 =3D (r1 + 1) & 15; } - - tcg_temp_free_i64(t); return DISAS_NEXT; } =20 @@ -4746,7 +4669,6 @@ static DisasJumpType op_tre(DisasContext *s, DisasOps= *o) =20 gen_helper_tre(pair, cpu_env, o->out, o->out2, o->in2); tcg_gen_extr_i128_i64(o->out2, o->out, pair); - tcg_temp_free_i128(pair); set_cc_static(s); return DISAS_NEXT; } @@ -4792,7 +4714,6 @@ static DisasJumpType op_trXX(DisasContext *s, DisasOp= s *o) } gen_helper_trXX(cc_op, cpu_env, r1, r2, tst, sizes); =20 - tcg_temp_free_i32(tst); set_cc_static(s); return DISAS_NEXT; } @@ -5299,7 +5220,6 @@ static void wout_r1_D32(DisasContext *s, DisasOps *o) store_reg32_i64(r1 + 1, o->out); tcg_gen_shri_i64(t, o->out, 32); store_reg32_i64(r1, t); - tcg_temp_free_i64(t); } #define SPEC_wout_r1_D32 SPEC_r1_even =20 @@ -6425,31 +6345,6 @@ static DisasJumpType translate_one(CPUS390XState *en= v, DisasContext *s) } } =20 - /* Free any temporaries created by the helpers. */ - if (o.out && !o.g_out) { - tcg_temp_free_i64(o.out); - } - if (o.out2 && !o.g_out2) { - tcg_temp_free_i64(o.out2); - } - if (o.in1 && !o.g_in1) { - tcg_temp_free_i64(o.in1); - } - if (o.in2 && !o.g_in2) { - tcg_temp_free_i64(o.in2); - } - if (o.addr1) { - tcg_temp_free_i64(o.addr1); - } - if (o.out_128) { - tcg_temp_free_i128(o.out_128); - } - if (o.in1_128) { - tcg_temp_free_i128(o.in1_128); - } - if (o.in2_128) { - tcg_temp_free_i128(o.in2_128); - } /* io should be the last instruction in tb when icount is enabled */ if (unlikely(icount && ret =3D=3D DISAS_NEXT)) { ret =3D DISAS_TOO_MANY; --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677476472; cv=none; d=zohomail.com; s=zohoarc; b=PR0i69enpeZE0KiBtyoCP7O4G/D21OyWnzswwiD/p1RaoDiNQhod+IftM1tXHDC4VA12cgZ48hzNrsAKgq5bkrKiZ3IDuh9f506BgJuUavW1kcwls9HdhUbr55y4xnsDsFSOEY+9LVWDpQh+do3CaYEAzZSB+WoJwIgPNzSEtmo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677476472; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wYL+y8pL8fUeyYxKPpZSV5KcdIFrgA/ShmRzCV44YVg=; b=mit+x3fudb773aHGcqEY+/yqnz4ZP2Y56iOkcap7MKUdyqxfPldQKE3NaQWFnubv2CWnM0AMb4bNiiLEUKB9oOgEAFde2i87qBFXv4nL+pcLBycTM+t+t9ULAs5NvMoXB+6tb5L7c78dDG8LG8FFEVYW05ADdtmlW4XG/6gL5BI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167747647241024.0365729759219; Sun, 26 Feb 2023 21:41:12 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW87-0004KY-2i; Mon, 27 Feb 2023 00:32:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW6P-0005Z9-AT for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:31:09 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW6L-0000HX-IK for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:31:08 -0500 Received: by mail-pj1-x1034.google.com with SMTP id me6-20020a17090b17c600b0023816b0c7ceso922205pjb.2 for ; Sun, 26 Feb 2023 21:31:04 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.31.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:31:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wYL+y8pL8fUeyYxKPpZSV5KcdIFrgA/ShmRzCV44YVg=; b=gY/f9RH0zoGxslOmVnxn5fElATJ1Mu5GqwOu9nQFTT1Z/tQV4RtpXM978qtozChTh7 cAYZ1jFOU0fNvmOOo43Yew+qHc7SIhH2pOFil4tYrfZIl5F1aZmbS3+6ZCNEDu0kWwvo QOrt6S/KElakDkVWfUiMst2RnH8jeWpAOLPCg2Lz4Ikv2CUHAxespFrEkwr53mGEMZx/ tDe+vev1GkaeSrsfCT9cF0sTib4k27/qh1B04GUiuUyLzOOeUs+GZkIXdD4RZvj1A/14 dMmerC41rhPfz+bAB7CHGhbzGs6NpXYcEpEUpxymqXBu0Z6IOasvURdhnUCadSY9x5Hi htKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wYL+y8pL8fUeyYxKPpZSV5KcdIFrgA/ShmRzCV44YVg=; b=yIy4RGR8q0X7c5wRS4NHsCeUpQmMVvqLie0H5K7yZ/+72xtRvKPkgOUpJQwbEkzfgh qkEBocAy8i4yCVsPe264ECgzEc7afT5tx2CFKKI4WKpYWnemhfC6lHi905WJ0S5EI4L+ NbZ5ZQA+T/+RK4YyGXudDplNiqir25MuqdHjAZm3j/8ZOR9KmdvuQVSyPJwUabyNsedu IGg85XaUlE3d7IvoXt3p+Ci93Yy53SEnh7YJRv8gKQQF/dj86H6F3df7kMz27jBhZWtF YPA0rert+AiiRNUgPnXcq2bKcsqiwZcdmFLV56FxPhaEDK8HcG6eKqy4Cn3LSG0e4m+b tZMQ== X-Gm-Message-State: AO0yUKWRXmFRjzmyKyDmAGtXhZdsyn3PcfE1m+DPxm6QLlOBw/EHiYpJ k2igPYllkgQoIy+O53TiQ/b30fkQWB+UvDaJpEQ= X-Google-Smtp-Source: AK7set+MiPgvM3bLJo7lTQ1TaVXF2EZoKpC4bq5hn94QDr18RNOkcUvfKFcxbCSrZ/G3YmhveLml2A== X-Received: by 2002:a17:90b:4a43:b0:233:f365:1d0b with SMTP id lb3-20020a17090b4a4300b00233f3651d0bmr24346398pjb.5.1677475864543; Sun, 26 Feb 2023 21:31:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 62/76] target/s390x: Remove assert vs g_in2 Date: Sun, 26 Feb 2023 19:24:51 -1000 Message-Id: <20230227052505.352889-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476476183100005 Content-Type: text/plain; charset="utf-8" These were trying to determine if o->in2 was available for use as a temporary. It's better to just allocate a new one. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/s390x/tcg/translate.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index beccd3429e..c431903c67 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1428,11 +1428,11 @@ static DisasJumpType op_andi(DisasContext *s, Disas= Ops *o) int shift =3D s->insn->data & 0xff; int size =3D s->insn->data >> 8; uint64_t mask =3D ((1ull << size) - 1) << shift; + TCGv_i64 t =3D tcg_temp_new_i64(); =20 - assert(!o->g_in2); - tcg_gen_shli_i64(o->in2, o->in2, shift); - tcg_gen_ori_i64(o->in2, o->in2, ~mask); - tcg_gen_and_i64(o->out, o->in1, o->in2); + tcg_gen_shli_i64(t, o->in2, shift); + tcg_gen_ori_i64(t, t, ~mask); + tcg_gen_and_i64(o->out, o->in1, t); =20 /* Produce the CC from only the bits manipulated. */ tcg_gen_andi_i64(cc_dst, o->out, mask); @@ -3520,10 +3520,10 @@ static DisasJumpType op_ori(DisasContext *s, DisasO= ps *o) int shift =3D s->insn->data & 0xff; int size =3D s->insn->data >> 8; uint64_t mask =3D ((1ull << size) - 1) << shift; + TCGv_i64 t =3D tcg_temp_new_i64(); =20 - assert(!o->g_in2); - tcg_gen_shli_i64(o->in2, o->in2, shift); - tcg_gen_or_i64(o->out, o->in1, o->in2); + tcg_gen_shli_i64(t, o->in2, shift); + tcg_gen_or_i64(o->out, o->in1, t); =20 /* Produce the CC from only the bits manipulated. */ tcg_gen_andi_i64(cc_dst, o->out, mask); @@ -4832,10 +4832,10 @@ static DisasJumpType op_xori(DisasContext *s, Disas= Ops *o) int shift =3D s->insn->data & 0xff; int size =3D s->insn->data >> 8; uint64_t mask =3D ((1ull << size) - 1) << shift; + TCGv_i64 t =3D tcg_temp_new_i64(); =20 - assert(!o->g_in2); - tcg_gen_shli_i64(o->in2, o->in2, shift); - tcg_gen_xor_i64(o->out, o->in1, o->in2); + tcg_gen_shli_i64(t, o->in2, shift); + tcg_gen_xor_i64(o->out, o->in1, t); =20 /* Produce the CC from only the bits manipulated. */ tcg_gen_andi_i64(cc_dst, o->out, mask); --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677476756; cv=none; d=zohomail.com; s=zohoarc; b=Ia8987rZUhptkEtoHyw8F+HDhhz6Lh37Ryhr50M/Hkvfc1LN1RTQfnT3ZXc/Xw2yoVZ9mJNS06hzslXSIns2QRr1ql9cTcapGIiSz4Q89n7JGETg6X3fpni4/MBw/iSqTAYBGQOnrySgREo3ckA4yt46Bi4Xj86iOaHXewJETEo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677476756; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kKpTWGCLSVG0YS1XFVPlvlmwyJALoBesP8PUrnrIExc=; b=DzsEyPPiTVd6lr3q82HbR6n1f3yKqmoH8EGPVM+xz8rxqmRXXnuhUSWDZ/laKt5m61/AgKWXw2S7aoFwkyMm/5rY08RFxvMTckPaI52u8piecT9UDVpq9FBanXpuYbTYP1NkoW+FmJjNxIrjKI/Hm/UMyfvGhnL8W2OxcbfYMrY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167747675684633.77110697248554; Sun, 26 Feb 2023 21:45:56 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW8A-0004ZR-OJ; Mon, 27 Feb 2023 00:32:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW6R-0005qG-FQ for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:31:11 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW6O-0000rw-Hn for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:31:11 -0500 Received: by mail-pl1-x62a.google.com with SMTP id y11so1390835plg.1 for ; Sun, 26 Feb 2023 21:31:08 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.31.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:31:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kKpTWGCLSVG0YS1XFVPlvlmwyJALoBesP8PUrnrIExc=; b=swQC3ZUKL4jVbwqrUmz6o9ZK+VIasrDt9MBjdUfjc2qYrl8QcgRmYE1Be8/zc3GevO 1R0AtOrpndgFJnJCAeMggZ5qM0nw5ynFSmeuebCu8yWNGjq3rq9qBrrfb2V9PSKBvPcZ 1LFf3dm5LI9fCgzJg8eIr/UJe4KkHaxMv1R2NrAUEXsueMnT6JPKFQWHtj/MldTEQ36E sNPJMpOVB1fRSbc3ORW+M/YUqE9iu/q4cSXxi34ueSQxgN9025Lv8Rg/HT5bsDXWA5Qm T2esBBduAk/aOFECmoIoXKIyb97f3J00HH6/8NipCBrtP4CS1jvDIJtHX4A3LJvZUgvz OW6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kKpTWGCLSVG0YS1XFVPlvlmwyJALoBesP8PUrnrIExc=; b=iKS5GZuxOIAt4GtzTtJ01Rb8SDzrDcvRLGV7hlwKjiZeoR0DrzabbAZcI4LTGdCdLw fKObGvQRo7AE64NmcNV8GoWWlhg913Qq83TSlk8cs3d/YZerhJEjabUGqLtHp8N2k171 4JQyIRhSFM15ZYthxIFHVdt/kF2ZbpHHGGahc7o6PUbquyXF90552NR9w+TnO6yF7Ow4 zA6VGnIgxRRRKq+3viitRUosfa0YLc2kdCCRYuVpiqrHqpNbaIVYIYs/5WmUmIcd4X38 /7pOBe4CVxslbmUk6fV2z+eV9lD+7gnsOfSuAwQ42SeC0178VrTqpQqqKFe/pZktviU9 mlEQ== X-Gm-Message-State: AO0yUKXX6pphDEaoAaJP2DMed3MVed1a65wN3rOh2WGbmAD8/kLRmw5O J8QS4evXwY02QGof99wiopCNxZkEenp/sf0K1p4= X-Google-Smtp-Source: AK7set+vp8jgqcV96FWVXX1VFdTM0RyW/P8NGxD4ao86Ds7D8G7+XwqlR5mluwnaOo10pAzzkfCuSQ== X-Received: by 2002:a17:90b:1a88:b0:237:39b7:68ce with SMTP id ng8-20020a17090b1a8800b0023739b768cemr19721288pjb.45.1677475867150; Sun, 26 Feb 2023 21:31:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 63/76] target/s390x: Remove g_out, g_out2, g_in1, g_in2 from DisasContext Date: Sun, 26 Feb 2023 19:24:52 -1000 Message-Id: <20230227052505.352889-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476757468100006 Content-Type: text/plain; charset="utf-8" These fields are no longer read, so remove them and the writes. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/s390x/tcg/translate.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index c431903c67..9974162527 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1061,7 +1061,6 @@ static const DisasFormatInfo format_info[] =3D { them, and store them back. See the "in1", "in2", "prep", "wout" sets of routines below for more details. */ typedef struct { - bool g_out, g_out2, g_in1, g_in2; TCGv_i64 out, out2, in1, in2; TCGv_i64 addr1; TCGv_i128 out_128, in1_128, in2_128; @@ -3159,9 +3158,7 @@ static DisasJumpType op_mc(DisasContext *s, DisasOps = *o) static DisasJumpType op_mov2(DisasContext *s, DisasOps *o) { o->out =3D o->in2; - o->g_out =3D o->g_in2; o->in2 =3D NULL; - o->g_in2 =3D false; return DISAS_NEXT; } =20 @@ -3171,9 +3168,7 @@ static DisasJumpType op_mov2e(DisasContext *s, DisasO= ps *o) TCGv ar1 =3D tcg_temp_new_i64(); =20 o->out =3D o->in2; - o->g_out =3D o->g_in2; o->in2 =3D NULL; - o->g_in2 =3D false; =20 switch (s->base.tb->flags & FLAG_MASK_ASC) { case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT: @@ -3202,11 +3197,8 @@ static DisasJumpType op_movx(DisasContext *s, DisasO= ps *o) { o->out =3D o->in1; o->out2 =3D o->in2; - o->g_out =3D o->g_in1; - o->g_out2 =3D o->g_in2; o->in1 =3D NULL; o->in2 =3D NULL; - o->g_in1 =3D o->g_in2 =3D false; return DISAS_NEXT; } =20 @@ -3708,7 +3700,6 @@ static DisasJumpType op_rosbg(DisasContext *s, DisasO= ps *o) /* If this is a test-only form, arrange to discard the result. */ if (i3 & 0x80) { o->out =3D tcg_temp_new_i64(); - o->g_out =3D false; } =20 i3 &=3D 63; @@ -4874,7 +4865,6 @@ static DisasJumpType op_zero2(DisasContext *s, DisasO= ps *o) { o->out =3D tcg_const_i64(0); o->out2 =3D o->out; - o->g_out2 =3D true; return DISAS_NEXT; } =20 @@ -5142,7 +5132,6 @@ static void prep_new_x(DisasContext *s, DisasOps *o) static void prep_r1(DisasContext *s, DisasOps *o) { o->out =3D regs[get_field(s, r1)]; - o->g_out =3D true; } #define SPEC_prep_r1 0 =20 @@ -5151,7 +5140,6 @@ static void prep_r1_P(DisasContext *s, DisasOps *o) int r1 =3D get_field(s, r1); o->out =3D regs[r1]; o->out2 =3D regs[r1 + 1]; - o->g_out =3D o->g_out2 =3D true; } #define SPEC_prep_r1_P SPEC_r1_even =20 @@ -5375,7 +5363,6 @@ static void in1_r1(DisasContext *s, DisasOps *o) static void in1_r1_o(DisasContext *s, DisasOps *o) { o->in1 =3D regs[get_field(s, r1)]; - o->g_in1 =3D true; } #define SPEC_in1_r1_o 0 =20 @@ -5409,7 +5396,6 @@ static void in1_r1p1(DisasContext *s, DisasOps *o) static void in1_r1p1_o(DisasContext *s, DisasOps *o) { o->in1 =3D regs[get_field(s, r1) + 1]; - o->g_in1 =3D true; } #define SPEC_in1_r1p1_o SPEC_r1_even =20 @@ -5464,7 +5450,6 @@ static void in1_r3(DisasContext *s, DisasOps *o) static void in1_r3_o(DisasContext *s, DisasOps *o) { o->in1 =3D regs[get_field(s, r3)]; - o->g_in1 =3D true; } #define SPEC_in1_r3_o 0 =20 @@ -5595,7 +5580,6 @@ static void in1_m1_64(DisasContext *s, DisasOps *o) static void in2_r1_o(DisasContext *s, DisasOps *o) { o->in2 =3D regs[get_field(s, r1)]; - o->g_in2 =3D true; } #define SPEC_in2_r1_o 0 =20 @@ -5630,7 +5614,6 @@ static void in2_r2(DisasContext *s, DisasOps *o) static void in2_r2_o(DisasContext *s, DisasOps *o) { o->in2 =3D regs[get_field(s, r2)]; - o->g_in2 =3D true; } #define SPEC_in2_r2_o 0 =20 --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.31.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:31:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=i017TKSUYPFS3C2eJMn5LGB/zmI/ObKEVqMTAqXsooY=; b=sEqOKt63l20etYG8w6LdSa0gtgZlv2B04hGi+OtJTA2Hb4vNsXNt7yhqojzd2zdiAJ Ifp7/5vIZjLIM+RKKz9lWPEwhG89iiepVwg23y19RiIzW5/dppyBID1+z00cmxmuPdNy HDv6BPTClCyI3IhtppNkmIsSViDTD6qYquJycF8sXu/B95k9avrDpAoTU1ViEsunLnFb 3HOMhKka42MRtGCIfvmI01RWTpW2kutYw0q0be54cJrQQKJL2GEvMKQF4Y6xQlPfMe/v ecudVL8nGyp2er9eIfcVep7e8qngCAL8hkQHRpCqleZrcQPGZgQ5uPQFpFElnko2nz/r FyKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i017TKSUYPFS3C2eJMn5LGB/zmI/ObKEVqMTAqXsooY=; b=lrrKZIjWDC2kgsb0a6qmMDvKgOjPgr4j4bPIpsN1W2XI6Elh1jdR0ocMQ21ckcE+ng Fqj43vcwgMhcVMw7f66zkyc2cLRg8NBKKwJ8yESr7+fzhlEKzaQrTocw3IvFCeJhqFi3 jc7YiKhBRksXy/eYvi3Q6zRPF3+cYRpYMARqdPBVZ1yCNxZo2tp1xsKVROWSFuXgZPtx 1teTyXZJBYO0ukBb0P7yNOFxmjIynVycSUJqxjFtInbWxeFE3rmfBQTnm9rS8L4GqpQv kL/a71KgROjTpBnKS1bFoTeaiheIr6up0TTxpRJe6RSOXIlUMPb6lOkLptocf1UBnmyJ n3oQ== X-Gm-Message-State: AO0yUKWnL3Oe87knzzaZp2QVpe7kdE0xp/DU+h2sxiPetBFp1BPHvTo0 9m4KKi5fO6czN+EaHtFgrnqPE2aEcDKdYGVNrj2O3Q== X-Google-Smtp-Source: AK7set/GCQJt9Lx1aSFLKPhCf7R1C/vr91Vc3RmYMk9BTERme5kWKQUDZmbJtpvOR7Rq1dkCM8DXfQ== X-Received: by 2002:a17:90b:3a87:b0:237:75a1:ef39 with SMTP id om7-20020a17090b3a8700b0023775a1ef39mr12360237pjb.27.1677475870001; Sun, 26 Feb 2023 21:31:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 64/76] target/sh4: Drop tcg_temp_free Date: Sun, 26 Feb 2023 19:24:53 -1000 Message-Id: <20230227052505.352889-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677486792097100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/sh4/translate.c | 110 ----------------------------------------- 1 file changed, 110 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 23563024e0..ad6de41712 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -196,7 +196,6 @@ static void gen_read_sr(TCGv dst) tcg_gen_or_i32(dst, dst, t0); tcg_gen_shli_i32(t0, cpu_sr_t, SR_T); tcg_gen_or_i32(dst, cpu_sr, t0); - tcg_temp_free_i32(t0); } =20 static void gen_write_sr(TCGv src) @@ -499,7 +498,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4); tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL | UNALIGN(ctx)); - tcg_temp_free(addr); } return; case 0x5000: /* mov.l @(disp,Rm),Rn */ @@ -508,7 +506,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4); tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL | UNALIGN(ctx)); - tcg_temp_free(addr); } return; case 0xe000: /* mov #imm,Rn */ @@ -531,14 +528,12 @@ static void _decode_opc(DisasContext * ctx) { TCGv addr =3D tcg_const_i32(ctx->base.pc_next + 4 + B7_0 * 2); tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW); - tcg_temp_free(addr); } return; case 0xd000: /* mov.l @(disp,PC),Rn */ { TCGv addr =3D tcg_const_i32((ctx->base.pc_next + 4 + B7_0 * 4)= & ~3); tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); - tcg_temp_free(addr); } return; case 0x7000: /* add #imm,Rn */ @@ -590,7 +585,6 @@ static void _decode_opc(DisasContext * ctx) /* might cause re-execution */ tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_UB); tcg_gen_mov_i32(REG(B11_8), addr); /* modify register status */ - tcg_temp_free(addr); } return; case 0x2005: /* mov.w Rm,@-Rn */ @@ -600,7 +594,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW | UNALIGN(ctx)); tcg_gen_mov_i32(REG(B11_8), addr); - tcg_temp_free(addr); } return; case 0x2006: /* mov.l Rm,@-Rn */ @@ -610,7 +603,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL | UNALIGN(ctx)); tcg_gen_mov_i32(REG(B11_8), addr); - tcg_temp_free(addr); } return; case 0x6004: /* mov.b @Rm+,Rn */ @@ -635,7 +627,6 @@ static void _decode_opc(DisasContext * ctx) TCGv addr =3D tcg_temp_new(); tcg_gen_add_i32(addr, REG(B11_8), REG(0)); tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_UB); - tcg_temp_free(addr); } return; case 0x0005: /* mov.w Rm,@(R0,Rn) */ @@ -644,7 +635,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_add_i32(addr, REG(B11_8), REG(0)); tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW | UNALIGN(ctx)); - tcg_temp_free(addr); } return; case 0x0006: /* mov.l Rm,@(R0,Rn) */ @@ -653,7 +643,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_add_i32(addr, REG(B11_8), REG(0)); tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL | UNALIGN(ctx)); - tcg_temp_free(addr); } return; case 0x000c: /* mov.b @(R0,Rm),Rn */ @@ -661,7 +650,6 @@ static void _decode_opc(DisasContext * ctx) TCGv addr =3D tcg_temp_new(); tcg_gen_add_i32(addr, REG(B7_4), REG(0)); tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_SB); - tcg_temp_free(addr); } return; case 0x000d: /* mov.w @(R0,Rm),Rn */ @@ -670,7 +658,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_add_i32(addr, REG(B7_4), REG(0)); tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW | UNALIGN(ctx)); - tcg_temp_free(addr); } return; case 0x000e: /* mov.l @(R0,Rm),Rn */ @@ -679,7 +666,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_add_i32(addr, REG(B7_4), REG(0)); tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL | UNALIGN(ctx)); - tcg_temp_free(addr); } return; case 0x6008: /* swap.b Rm,Rn */ @@ -687,7 +673,6 @@ static void _decode_opc(DisasContext * ctx) TCGv low =3D tcg_temp_new(); tcg_gen_bswap16_i32(low, REG(B7_4), 0); tcg_gen_deposit_i32(REG(B11_8), REG(B7_4), low, 0, 16); - tcg_temp_free(low); } return; case 0x6009: /* swap.w Rm,Rn */ @@ -701,8 +686,6 @@ static void _decode_opc(DisasContext * ctx) low =3D tcg_temp_new(); tcg_gen_shri_i32(low, REG(B11_8), 16); tcg_gen_or_i32(REG(B11_8), high, low); - tcg_temp_free(low); - tcg_temp_free(high); } return; case 0x300c: /* add Rm,Rn */ @@ -716,8 +699,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0); tcg_gen_add2_i32(REG(B11_8), cpu_sr_t, REG(B11_8), t0, t1, cpu_sr_t); - tcg_temp_free(t0); - tcg_temp_free(t1); } return; case 0x300f: /* addv Rm,Rn */ @@ -730,11 +711,8 @@ static void _decode_opc(DisasContext * ctx) t2 =3D tcg_temp_new(); tcg_gen_xor_i32(t2, REG(B7_4), REG(B11_8)); tcg_gen_andc_i32(cpu_sr_t, t1, t2); - tcg_temp_free(t2); tcg_gen_shri_i32(cpu_sr_t, cpu_sr_t, 31); - tcg_temp_free(t1); tcg_gen_mov_i32(REG(B7_4), t0); - tcg_temp_free(t0); } return; case 0x2009: /* and Rm,Rn */ @@ -764,8 +742,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_andc_i32(cmp1, cmp1, cmp2); tcg_gen_andi_i32(cmp1, cmp1, 0x80808080); tcg_gen_setcondi_i32(TCG_COND_NE, cpu_sr_t, cmp1, 0); - tcg_temp_free(cmp2); - tcg_temp_free(cmp1); } return; case 0x2007: /* div0s Rm,Rn */ @@ -801,11 +777,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_xor_i32(t1, t1, t0); tcg_gen_xori_i32(cpu_sr_t, t1, 1); tcg_gen_xor_i32(cpu_sr_q, cpu_sr_m, t1); - - tcg_temp_free(zero); - tcg_temp_free(t2); - tcg_temp_free(t1); - tcg_temp_free(t0); } return; case 0x300d: /* dmuls.l Rm,Rn */ @@ -834,8 +805,6 @@ static void _decode_opc(DisasContext * ctx) arg1 =3D tcg_temp_new(); tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, MO_TESL); gen_helper_macl(cpu_env, arg0, arg1); - tcg_temp_free(arg1); - tcg_temp_free(arg0); tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); } @@ -848,8 +817,6 @@ static void _decode_opc(DisasContext * ctx) arg1 =3D tcg_temp_new(); tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, MO_TESL); gen_helper_macw(cpu_env, arg0, arg1); - tcg_temp_free(arg1); - tcg_temp_free(arg0); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2); tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); } @@ -865,8 +832,6 @@ static void _decode_opc(DisasContext * ctx) arg1 =3D tcg_temp_new(); tcg_gen_ext16s_i32(arg1, REG(B11_8)); tcg_gen_mul_i32(cpu_macl, arg0, arg1); - tcg_temp_free(arg1); - tcg_temp_free(arg0); } return; case 0x200e: /* mulu.w Rm,Rn */ @@ -877,8 +842,6 @@ static void _decode_opc(DisasContext * ctx) arg1 =3D tcg_temp_new(); tcg_gen_ext16u_i32(arg1, REG(B11_8)); tcg_gen_mul_i32(cpu_macl, arg0, arg1); - tcg_temp_free(arg1); - tcg_temp_free(arg0); } return; case 0x600b: /* neg Rm,Rn */ @@ -892,7 +855,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t, t0, t0, REG(B11_8), cpu_sr_t); tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1); - tcg_temp_free(t0); } return; case 0x6007: /* not Rm,Rn */ @@ -921,10 +883,6 @@ static void _decode_opc(DisasContext * ctx) /* select between the two cases */ tcg_gen_movi_i32(t0, 0); tcg_gen_movcond_i32(TCG_COND_GE, REG(B11_8), REG(B7_4), t0, t1= , t2); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } return; case 0x400d: /* shld Rm,Rn */ @@ -947,10 +905,6 @@ static void _decode_opc(DisasContext * ctx) /* select between the two cases */ tcg_gen_movi_i32(t0, 0); tcg_gen_movcond_i32(TCG_COND_GE, REG(B11_8), REG(B7_4), t0, t1= , t2); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } return; case 0x3008: /* sub Rm,Rn */ @@ -965,8 +919,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t, REG(B11_8), t0, t1, cpu_sr_t); tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1); - tcg_temp_free(t0); - tcg_temp_free(t1); } return; case 0x300b: /* subv Rm,Rn */ @@ -979,11 +931,8 @@ static void _decode_opc(DisasContext * ctx) t2 =3D tcg_temp_new(); tcg_gen_xor_i32(t2, REG(B11_8), REG(B7_4)); tcg_gen_and_i32(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_shri_i32(cpu_sr_t, t1, 31); - tcg_temp_free(t1); tcg_gen_mov_i32(REG(B11_8), t0); - tcg_temp_free(t0); } return; case 0x2008: /* tst Rm,Rn */ @@ -991,7 +940,6 @@ static void _decode_opc(DisasContext * ctx) TCGv val =3D tcg_temp_new(); tcg_gen_and_i32(val, REG(B7_4), REG(B11_8)); tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); - tcg_temp_free(val); } return; case 0x200a: /* xor Rm,Rn */ @@ -1014,7 +962,6 @@ static void _decode_opc(DisasContext * ctx) TCGv_i64 fp =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp, XHACK(B7_4)); tcg_gen_qemu_st_i64(fp, REG(B11_8), ctx->memidx, MO_TEUQ); - tcg_temp_free_i64(fp); } else { tcg_gen_qemu_st_i32(FREG(B7_4), REG(B11_8), ctx->memidx, MO_TE= UL); } @@ -1025,7 +972,6 @@ static void _decode_opc(DisasContext * ctx) TCGv_i64 fp =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(fp, REG(B7_4), ctx->memidx, MO_TEUQ); gen_store_fpr64(ctx, fp, XHACK(B11_8)); - tcg_temp_free_i64(fp); } else { tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TE= UL); } @@ -1036,7 +982,6 @@ static void _decode_opc(DisasContext * ctx) TCGv_i64 fp =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(fp, REG(B7_4), ctx->memidx, MO_TEUQ); gen_store_fpr64(ctx, fp, XHACK(B11_8)); - tcg_temp_free_i64(fp); tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8); } else { tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TE= UL); @@ -1052,13 +997,11 @@ static void _decode_opc(DisasContext * ctx) gen_load_fpr64(ctx, fp, XHACK(B7_4)); tcg_gen_subi_i32(addr, REG(B11_8), 8); tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, MO_TEUQ); - tcg_temp_free_i64(fp); } else { tcg_gen_subi_i32(addr, REG(B11_8), 4); tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL= ); } tcg_gen_mov_i32(REG(B11_8), addr); - tcg_temp_free(addr); } return; case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ @@ -1070,11 +1013,9 @@ static void _decode_opc(DisasContext * ctx) TCGv_i64 fp =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(fp, addr, ctx->memidx, MO_TEUQ); gen_store_fpr64(ctx, fp, XHACK(B11_8)); - tcg_temp_free_i64(fp); } else { tcg_gen_qemu_ld_i32(FREG(B11_8), addr, ctx->memidx, MO_TEU= L); } - tcg_temp_free(addr); } return; case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */ @@ -1086,11 +1027,9 @@ static void _decode_opc(DisasContext * ctx) TCGv_i64 fp =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp, XHACK(B7_4)); tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, MO_TEUQ); - tcg_temp_free_i64(fp); } else { tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL= ); } - tcg_temp_free(addr); } return; case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ @@ -1132,8 +1071,6 @@ static void _decode_opc(DisasContext * ctx) return; } gen_store_fpr64(ctx, fp0, B11_8); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); } else { switch (ctx->opcode & 0xf00f) { case 0xf000: /* fadd Rm,Rn */ @@ -1185,8 +1122,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_qemu_ld_i32(val, addr, ctx->memidx, MO_UB); tcg_gen_andi_i32(val, val, B7_0); tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_UB); - tcg_temp_free(val); - tcg_temp_free(addr); } return; case 0x8b00: /* bf label */ @@ -1217,7 +1152,6 @@ static void _decode_opc(DisasContext * ctx) TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, cpu_gbr, B7_0); tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_SB); - tcg_temp_free(addr); } return; case 0xc500: /* mov.w @(disp,GBR),R0 */ @@ -1225,7 +1159,6 @@ static void _decode_opc(DisasContext * ctx) TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2); tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW); - tcg_temp_free(addr); } return; case 0xc600: /* mov.l @(disp,GBR),R0 */ @@ -1233,7 +1166,6 @@ static void _decode_opc(DisasContext * ctx) TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4); tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESL); - tcg_temp_free(addr); } return; case 0xc000: /* mov.b R0,@(disp,GBR) */ @@ -1241,7 +1173,6 @@ static void _decode_opc(DisasContext * ctx) TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, cpu_gbr, B7_0); tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_UB); - tcg_temp_free(addr); } return; case 0xc100: /* mov.w R0,@(disp,GBR) */ @@ -1249,7 +1180,6 @@ static void _decode_opc(DisasContext * ctx) TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2); tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW); - tcg_temp_free(addr); } return; case 0xc200: /* mov.l R0,@(disp,GBR) */ @@ -1257,7 +1187,6 @@ static void _decode_opc(DisasContext * ctx) TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4); tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUL); - tcg_temp_free(addr); } return; case 0x8000: /* mov.b R0,@(disp,Rn) */ @@ -1265,7 +1194,6 @@ static void _decode_opc(DisasContext * ctx) TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B7_4), B3_0); tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_UB); - tcg_temp_free(addr); } return; case 0x8100: /* mov.w R0,@(disp,Rn) */ @@ -1274,7 +1202,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW | UNALIGN(ctx)); - tcg_temp_free(addr); } return; case 0x8400: /* mov.b @(disp,Rn),R0 */ @@ -1282,7 +1209,6 @@ static void _decode_opc(DisasContext * ctx) TCGv addr =3D tcg_temp_new(); tcg_gen_addi_i32(addr, REG(B7_4), B3_0); tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_SB); - tcg_temp_free(addr); } return; case 0x8500: /* mov.w @(disp,Rn),R0 */ @@ -1291,7 +1217,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW | UNALIGN(ctx)); - tcg_temp_free(addr); } return; case 0xc700: /* mova @(disp,PC),R0 */ @@ -1310,8 +1235,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_qemu_ld_i32(val, addr, ctx->memidx, MO_UB); tcg_gen_ori_i32(val, val, B7_0); tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_UB); - tcg_temp_free(val); - tcg_temp_free(addr); } return; case 0xc300: /* trapa #imm */ @@ -1321,7 +1244,6 @@ static void _decode_opc(DisasContext * ctx) gen_save_cpu_state(ctx, true); imm =3D tcg_const_i32(B7_0); gen_helper_trapa(cpu_env, imm); - tcg_temp_free(imm); ctx->base.is_jmp =3D DISAS_NORETURN; } return; @@ -1330,7 +1252,6 @@ static void _decode_opc(DisasContext * ctx) TCGv val =3D tcg_temp_new(); tcg_gen_andi_i32(val, REG(0), B7_0); tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); - tcg_temp_free(val); } return; case 0xcc00: /* tst.b #imm,@(R0,GBR) */ @@ -1340,7 +1261,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_qemu_ld_i32(val, val, ctx->memidx, MO_UB); tcg_gen_andi_i32(val, val, B7_0); tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); - tcg_temp_free(val); } return; case 0xca00: /* xor #imm,R0 */ @@ -1355,8 +1275,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_qemu_ld_i32(val, addr, ctx->memidx, MO_UB); tcg_gen_xori_i32(val, val, B7_0); tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_UB); - tcg_temp_free(val); - tcg_temp_free(addr); } return; } @@ -1382,7 +1300,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_subi_i32(addr, REG(B11_8), 4); tcg_gen_qemu_st_i32(ALTREG(B6_4), addr, ctx->memidx, MO_TEUL); tcg_gen_mov_i32(REG(B11_8), addr); - tcg_temp_free(addr); } return; } @@ -1430,7 +1347,6 @@ static void _decode_opc(DisasContext * ctx) TCGv val =3D tcg_temp_new(); tcg_gen_andi_i32(val, REG(B11_8), 0x700083f3); gen_write_sr(val); - tcg_temp_free(val); ctx->base.is_jmp =3D DISAS_STOP; } return; @@ -1441,7 +1357,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, MO_TESL); tcg_gen_andi_i32(val, val, 0x700083f3); gen_write_sr(val); - tcg_temp_free(val); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); ctx->base.is_jmp =3D DISAS_STOP; } @@ -1459,8 +1374,6 @@ static void _decode_opc(DisasContext * ctx) gen_read_sr(val); tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_TEUL); tcg_gen_mov_i32(REG(B11_8), addr); - tcg_temp_free(val); - tcg_temp_free(addr); } return; #define LD(reg,ldnum,ldpnum,prechk) \ @@ -1485,7 +1398,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_subi_i32(addr, REG(B11_8), 4); \ tcg_gen_qemu_st_i32(cpu_##reg, addr, ctx->memidx, MO_TEUL); \ tcg_gen_mov_i32(REG(B11_8), addr); \ - tcg_temp_free(addr); \ } \ return; #define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \ @@ -1514,7 +1426,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_qemu_ld_i32(addr, REG(B11_8), ctx->memidx, MO_TESL); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); gen_helper_ld_fpscr(cpu_env, addr); - tcg_temp_free(addr); ctx->base.is_jmp =3D DISAS_STOP; } return; @@ -1532,8 +1443,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_subi_i32(addr, REG(B11_8), 4); tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_TEUL); tcg_gen_mov_i32(REG(B11_8), addr); - tcg_temp_free(addr); - tcg_temp_free(val); } return; case 0x00c3: /* movca.l R0,@Rm */ @@ -1542,7 +1451,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, MO_TEUL); gen_helper_movcal(cpu_env, REG(B11_8), val); tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL); - tcg_temp_free(val); } ctx->has_movcal =3D 1; return; @@ -1586,7 +1494,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_atomic_cmpxchg_i32(tmp, REG(B11_8), cpu_lock_value, REG(0), ctx->memidx, MO_TEUL); tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_t, tmp, cpu_lock_v= alue); - tcg_temp_free(tmp); } else { tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_lock_addr, -1, fail); tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TE= UL); @@ -1617,7 +1524,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL); tcg_gen_mov_i32(cpu_lock_value, REG(0)); tcg_gen_mov_i32(cpu_lock_addr, tmp); - tcg_temp_free(tmp); } else { tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL); tcg_gen_movi_i32(cpu_lock_addr, 0); @@ -1653,7 +1559,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_shri_i32(cpu_sr_t, REG(B11_8), 31); tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); tcg_gen_or_i32(REG(B11_8), REG(B11_8), tmp); - tcg_temp_free(tmp); } return; case 0x4025: /* rotcr Rn */ @@ -1663,7 +1568,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 1); tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1); tcg_gen_or_i32(REG(B11_8), REG(B11_8), tmp); - tcg_temp_free(tmp); } return; case 0x4004: /* rotl Rn */ @@ -1711,7 +1615,6 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_atomic_fetch_or_i32(val, REG(B11_8), val, ctx->memidx, MO_UB); tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); - tcg_temp_free(val); } return; case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ @@ -1732,7 +1635,6 @@ static void _decode_opc(DisasContext * ctx) fp =3D tcg_temp_new_i64(); gen_helper_float_DT(fp, cpu_env, cpu_fpul); gen_store_fpr64(ctx, fp, B11_8); - tcg_temp_free_i64(fp); } else { gen_helper_float_FT(FREG(B11_8), cpu_env, cpu_fpul); @@ -1748,7 +1650,6 @@ static void _decode_opc(DisasContext * ctx) fp =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp, B11_8); gen_helper_ftrc_DT(cpu_fpul, cpu_env, fp); - tcg_temp_free_i64(fp); } else { gen_helper_ftrc_FT(cpu_fpul, cpu_env, FREG(B11_8)); @@ -1772,7 +1673,6 @@ static void _decode_opc(DisasContext * ctx) gen_load_fpr64(ctx, fp, B11_8); gen_helper_fsqrt_DT(fp, cpu_env, fp); gen_store_fpr64(ctx, fp, B11_8); - tcg_temp_free_i64(fp); } else { gen_helper_fsqrt_FT(FREG(B11_8), cpu_env, FREG(B11_8)); } @@ -1798,7 +1698,6 @@ static void _decode_opc(DisasContext * ctx) TCGv_i64 fp =3D tcg_temp_new_i64(); gen_helper_fcnvsd_FT_DT(fp, cpu_env, cpu_fpul); gen_store_fpr64(ctx, fp, B11_8); - tcg_temp_free_i64(fp); } return; case 0xf0bd: /* fcnvds DRn,FPUL */ @@ -1807,7 +1706,6 @@ static void _decode_opc(DisasContext * ctx) TCGv_i64 fp =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp, B11_8); gen_helper_fcnvds_DT_FT(cpu_fpul, cpu_env, fp); - tcg_temp_free_i64(fp); } return; case 0xf0ed: /* fipr FVm,FVn */ @@ -1817,8 +1715,6 @@ static void _decode_opc(DisasContext * ctx) TCGv m =3D tcg_const_i32((ctx->opcode >> 8) & 3); TCGv n =3D tcg_const_i32((ctx->opcode >> 10) & 3); gen_helper_fipr(cpu_env, m, n); - tcg_temp_free(m); - tcg_temp_free(n); return; } break; @@ -1831,7 +1727,6 @@ static void _decode_opc(DisasContext * ctx) } TCGv n =3D tcg_const_i32((ctx->opcode >> 10) & 3); gen_helper_ftrv(cpu_env, n); - tcg_temp_free(n); return; } break; @@ -2220,11 +2115,6 @@ static void decode_gusa(DisasContext *ctx, CPUSH4Sta= te *env) g_assert_not_reached(); } =20 - /* If op_src is not a valid register, then op_arg was a constant. */ - if (op_src < 0 && op_arg) { - tcg_temp_free_i32(op_arg); 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.31.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:31:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gN2ZbLLJMcqwLwLE2rtqtIVte+chcJDZw5IRv13Gn6s=; b=nXGrSXZdtgdkXbfg5IY8ejfww8Opdy9Sxtp6hEbDbgHvoKEbl6L3mGK8Fkue4MgGKE in/NDYC4khaMTRYAAtnIH1czqFRKOv8s7QkV5veqlUvpGgwJSfdFE+F8KN5lVfMfB3RL biIrSPvl/E6mC+hgWKi2l/GrUFxXFKkgwb8fOUlj8x3s+yRrrBfD6NFh9fVSwa+QV8cI 67pfMRPFnAOjDDVHtWPy5NsBvS138r5Cy17Ar+WO2wpy7gtG1j/ZC9k242QgtoGWYtAD NqnRTKupPle0aIOUDZgdiAcOs4glMABVVs9Z1gox98/ZUx3NhfAnEK6pNFceKzlcSqdG ab2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gN2ZbLLJMcqwLwLE2rtqtIVte+chcJDZw5IRv13Gn6s=; b=oaIyp7BOxrkpWRkEe9INsaEBESETMJZcSuibedlBRPq9oWJUgVt83GRWnitK+I7T4/ VEvre01RCvettD5nhXHNtu6nUfMZP2bwdra4XjiCm2Hf3zAkKZ8QwLUcBNMikTQZzplx ny2qdN6eOahWFPC3b2Wi0yFVQlZ0yB4QYmmRqG/uSupweXf06JnBRwMAOtAA1bYxtma5 z94bX6RBcYl7OWuxGopZ1QykZIDDZ88gem3kdYPiH/wrFHo97ic/n3mIpyXmTiPFQjlJ j6QAgdo4ni9UwB/9rg2uZJgvzgqJw7iG64TwU4rJ6ZangsE3sawndvBMZFYJj6ksMKZm S1uA== X-Gm-Message-State: AO0yUKWVGfHNuxtMpEbWpn9TfthiZUukTbirACRM+cT8z7tSvHniSnau 1zXQB5fZ4VUu+NMjiReFcSZOHgSlfEscpTuHuL0= X-Google-Smtp-Source: AK7set9caEI2QJ9ZB1+AyT4slTZJzGuRFGLcS7mYdV8qT7qMt6tnMEPfdFJKbhfKFj6+ZMEE6jM47A== X-Received: by 2002:a17:90b:1b4e:b0:22c:5360:684e with SMTP id nv14-20020a17090b1b4e00b0022c5360684emr26256014pjb.29.1677475872618; Sun, 26 Feb 2023 21:31:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 65/76] target/sparc: Drop get_temp_tl Date: Sun, 26 Feb 2023 19:24:54 -1000 Message-Id: <20230227052505.352889-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476679121100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries, therefore there's no need to record temps for later freeing. Replace the few uses with tcg_temp_new. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/sparc/translate.c | 53 ++++++++++++++-------------------------- 1 file changed, 18 insertions(+), 35 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 3b0044aa66..2b4af692f6 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -85,9 +85,7 @@ typedef struct DisasContext { uint32_t cc_op; /* current CC operation */ sparc_def_t *def; TCGv_i32 t32[3]; - TCGv ttl[5]; int n_t32; - int n_ttl; #ifdef TARGET_SPARC64 int fprs_dirty; int asi; @@ -139,14 +137,6 @@ static inline TCGv_i32 get_temp_i32(DisasContext *dc) return t; } =20 -static inline TCGv get_temp_tl(DisasContext *dc) -{ - TCGv t; - assert(dc->n_ttl < ARRAY_SIZE(dc->ttl)); - dc->ttl[dc->n_ttl++] =3D t =3D tcg_temp_new(); - return t; -} - static inline void gen_update_fprs_dirty(DisasContext *dc, int rd) { #if defined(TARGET_SPARC64) @@ -301,7 +291,7 @@ static inline TCGv gen_load_gpr(DisasContext *dc, int r= eg) assert(reg < 32); return cpu_regs[reg]; } else { - TCGv t =3D get_temp_tl(dc); + TCGv t =3D tcg_temp_new(); tcg_gen_movi_tl(t, 0); return t; } @@ -321,7 +311,7 @@ static inline TCGv gen_dest_gpr(DisasContext *dc, int r= eg) assert(reg < 32); return cpu_regs[reg]; } else { - return get_temp_tl(dc); + return tcg_temp_new(); } } =20 @@ -2897,7 +2887,7 @@ static TCGv get_src2(DisasContext *dc, unsigned int i= nsn) { if (IS_IMM) { /* immediate */ target_long simm =3D GET_FIELDs(insn, 19, 31); - TCGv t =3D get_temp_tl(dc); + TCGv t =3D tcg_temp_new(); tcg_gen_movi_tl(t, simm); return t; } else { /* register */ @@ -3253,7 +3243,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) case 2: /* FPU & Logical Operations */ { unsigned int xop =3D GET_FIELD(insn, 7, 12); - TCGv cpu_dst =3D get_temp_tl(dc); + TCGv cpu_dst =3D tcg_temp_new(); TCGv cpu_tmp0; =20 if (xop =3D=3D 0x3a) { /* generate trap */ @@ -3513,7 +3503,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) if (!supervisor(dc)) { goto priv_insn; } - cpu_tmp0 =3D get_temp_tl(dc); + cpu_tmp0 =3D tcg_temp_new(); #ifdef TARGET_SPARC64 rs1 =3D GET_FIELD(insn, 13, 17); switch (rs1) { @@ -4031,7 +4021,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) } else { /* register */ rs2 =3D GET_FIELD(insn, 27, 31); cpu_src2 =3D gen_load_gpr(dc, rs2); - cpu_tmp0 =3D get_temp_tl(dc); + cpu_tmp0 =3D tcg_temp_new(); if (insn & (1 << 12)) { tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); } else { @@ -4053,7 +4043,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) } else { /* register */ rs2 =3D GET_FIELD(insn, 27, 31); cpu_src2 =3D gen_load_gpr(dc, rs2); - cpu_tmp0 =3D get_temp_tl(dc); + cpu_tmp0 =3D tcg_temp_new(); if (insn & (1 << 12)) { tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0); @@ -4077,7 +4067,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) } else { /* register */ rs2 =3D GET_FIELD(insn, 27, 31); cpu_src2 =3D gen_load_gpr(dc, rs2); - cpu_tmp0 =3D get_temp_tl(dc); + cpu_tmp0 =3D tcg_temp_new(); if (insn & (1 << 12)) { tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0); @@ -4263,7 +4253,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) simm =3D GET_FIELDs(insn, 20, 31); tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f= ); } else { /* register */ - cpu_tmp0 =3D get_temp_tl(dc); + cpu_tmp0 =3D tcg_temp_new(); tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0); } @@ -4274,7 +4264,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) simm =3D GET_FIELDs(insn, 20, 31); tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f= ); } else { /* register */ - cpu_tmp0 =3D get_temp_tl(dc); + cpu_tmp0 =3D tcg_temp_new(); tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0); } @@ -4285,7 +4275,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) simm =3D GET_FIELDs(insn, 20, 31); tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f= ); } else { /* register */ - cpu_tmp0 =3D get_temp_tl(dc); + cpu_tmp0 =3D tcg_temp_new(); tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0); } @@ -4294,7 +4284,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) #endif case 0x30: { - cpu_tmp0 =3D get_temp_tl(dc); + cpu_tmp0 =3D tcg_temp_new(); switch(rd) { case 0: /* wry */ tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src= 2); @@ -4479,7 +4469,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) goto illegal_insn; } #else - cpu_tmp0 =3D get_temp_tl(dc); + cpu_tmp0 =3D tcg_temp_new(); tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); gen_helper_wrpsr(cpu_env, cpu_tmp0); tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); @@ -4495,7 +4485,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) { if (!supervisor(dc)) goto priv_insn; - cpu_tmp0 =3D get_temp_tl(dc); + cpu_tmp0 =3D tcg_temp_new(); tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); #ifdef TARGET_SPARC64 switch (rd) { @@ -4653,7 +4643,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) CHECK_IU_FEATURE(dc, HYPV); if (!hypervisor(dc)) goto priv_insn; - cpu_tmp0 =3D get_temp_tl(dc); + cpu_tmp0 =3D tcg_temp_new(); tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); switch (rd) { case 0: // hpstate @@ -5227,7 +5217,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) } else if (xop =3D=3D 0x39) { /* V9 return */ save_state(dc); cpu_src1 =3D get_src1(dc, insn); - cpu_tmp0 =3D get_temp_tl(dc); + cpu_tmp0 =3D tcg_temp_new(); if (IS_IMM) { /* immediate */ simm =3D GET_FIELDs(insn, 19, 31); tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm); @@ -5249,7 +5239,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) #endif } else { cpu_src1 =3D get_src1(dc, insn); - cpu_tmp0 =3D get_temp_tl(dc); + cpu_tmp0 =3D tcg_temp_new(); if (IS_IMM) { /* immediate */ simm =3D GET_FIELDs(insn, 19, 31); tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm); @@ -5344,7 +5334,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) unsigned int xop =3D GET_FIELD(insn, 7, 12); /* ??? gen_address_mask prevents us from using a source register directly. Always generate a temporary. */ - TCGv cpu_addr =3D get_temp_tl(dc); + TCGv cpu_addr =3D tcg_temp_new(); =20 tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn)); if (xop =3D=3D 0x3c || xop =3D=3D 0x3e) { @@ -5780,13 +5770,6 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) } dc->n_t32 =3D 0; } - if (dc->n_ttl !=3D 0) { - int i; - for (i =3D dc->n_ttl - 1; i >=3D 0; --i) { - tcg_temp_free(dc->ttl[i]); - } - dc->n_ttl =3D 0; - } } =20 static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677476580; cv=none; d=zohomail.com; s=zohoarc; b=XkF3wgwJaX/bVRsNHBy0eG5FguKFLTybH2MZBVMYZ9xVQJGsAOhV/egKpWY9YsSUEnDQMDcKPgKgCUHswfsdNzhXdl8h86BLWXWFKGGncniIaUF7NSAuEeNwywVgpOqG3u8FkZS8b14N81RAijyvy+pcYrR8Q7B6knDwheUXGBg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677476580; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FDr/G0N/cf+m+hkGWa1ktDxEpYaGWUpfy88lZunNdyw=; b=lbOAgof0P8ISq6thCJU12OJU67sBaSLxjgx++5L7tqrIsvQMaIjxeY8vImj2MCOKigZ+jzNJBEobXbMyvM4n7HQHyDBotosKRq7fJfczAU52IW7j/TX02fXeN84EkncKnDUY8bDjKF7X6KPq2y8RouQ/RPF5BLXA1iCOGIzJrCM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677476580683261.4578866385808; Sun, 26 Feb 2023 21:43:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW87-0004MK-Ex; Mon, 27 Feb 2023 00:32:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW6Y-0006j2-Q0 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:31:18 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW6W-0000xl-U6 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:31:18 -0500 Received: by mail-pj1-x1035.google.com with SMTP id cp7-20020a17090afb8700b0023756229427so8898796pjb.1 for ; Sun, 26 Feb 2023 21:31:16 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.31.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:31:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FDr/G0N/cf+m+hkGWa1ktDxEpYaGWUpfy88lZunNdyw=; b=Wq397ahEu0zx/lALFZbph690aHd0waUNwZIu80MsXgUqMEhT071R+/t+P7KBlw5tFk uqAgVfqEdGtiFQu0i2GzPm4dKtLuycFYj4xJ6wUiciNTxLxPiV/65OW2uHH4Jgw7ZZGT RW3iGt5LU7jHKZxTM2+NsCOnLkKnkXCdhxNwyClhQ4cMDCWDsPKTK4SqtZgnHpyXiVUX UZ+TneoTUztHB3NuIBHMIL0STtWquvaWQgTU5p/QhsmdHJ2ww07lVvhDoku5z4YfcQ3X 44GCniwdGQ7KtQt3GiV1zcdRknkFIAkfLgO5BZuGxJ/l4xJky/d3ru1SNxDJ+saNdUOS P/IA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FDr/G0N/cf+m+hkGWa1ktDxEpYaGWUpfy88lZunNdyw=; b=3bZnfl4ckAG7ZlnM7/tue9npGYlYIdZxacNU07t0wHYpW6SluQGO5w95gs6HhXhoV2 SiRNPQMLYAytgOE5BGSdD7GiX7hTei/CWYspTBs12TuELz8QKWyQarZQxOUQgb9gOh+x 2a5crP2EwXXa57Buk5X8Rf2S5vX8bKWuW+/8MM7OFh9yF0x4nywrjoEBfB1ePXm1ZFNN scaDGy7yxwVsSsIgAtmTu2vv1d+A6h2fwQWHnUkPOdrahpW5oeVln7TPvDY8D2Q1OGYf /SRMa/3waGntVgsZoqUEZv0IRe1c3c54vTqCaUaBrlU0VIaUZUXLrv00iPTuNmvgqx7L rnCw== X-Gm-Message-State: AO0yUKXh89zkk0/Hfz89f7AwcMqb1LzQyO8WqD6QDIVxUaXaCQlMTNO6 cAdfp5rr7Lnrsvpj0bHTzJEqVzxUheWe80llACQ= X-Google-Smtp-Source: AK7set+2AYcvaDaYBbJMsQQsTRDIh6wjQqitOTI2wGFmjhd3GI72jKoLotJXOEXegsM3xFkg19IggA== X-Received: by 2002:a17:90b:3906:b0:234:7ccf:3c7c with SMTP id ob6-20020a17090b390600b002347ccf3c7cmr8319993pjb.9.1677475875327; Sun, 26 Feb 2023 21:31:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 66/76] target/sparc: Drop get_temp_i32 Date: Sun, 26 Feb 2023 19:24:55 -1000 Message-Id: <20230227052505.352889-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476582472100007 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries, therefore there's no need to record temps for later freeing. Replace the few uses with tcg_temp_new_i32. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/sparc/translate.c | 25 ++++--------------------- 1 file changed, 4 insertions(+), 21 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 2b4af692f6..bdf464f802 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -84,8 +84,6 @@ typedef struct DisasContext { =20 uint32_t cc_op; /* current CC operation */ sparc_def_t *def; - TCGv_i32 t32[3]; - int n_t32; #ifdef TARGET_SPARC64 int fprs_dirty; int asi; @@ -129,14 +127,6 @@ static int sign_extend(int x, int len) =20 #define IS_IMM (insn & (1<<13)) =20 -static inline TCGv_i32 get_temp_i32(DisasContext *dc) -{ - TCGv_i32 t; - assert(dc->n_t32 < ARRAY_SIZE(dc->t32)); - dc->t32[dc->n_t32++] =3D t =3D tcg_temp_new_i32(); - return t; -} - static inline void gen_update_fprs_dirty(DisasContext *dc, int rd) { #if defined(TARGET_SPARC64) @@ -153,7 +143,7 @@ static inline void gen_update_fprs_dirty(DisasContext *= dc, int rd) /* floating point registers moves */ static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src) { - TCGv_i32 ret =3D get_temp_i32(dc); + TCGv_i32 ret =3D tcg_temp_new_i32(); if (src & 1) { tcg_gen_extrl_i64_i32(ret, cpu_fpr[src / 2]); } else { @@ -175,7 +165,7 @@ static void gen_store_fpr_F(DisasContext *dc, unsigned = int dst, TCGv_i32 v) =20 static TCGv_i32 gen_dest_fpr_F(DisasContext *dc) { - return get_temp_i32(dc); + return tcg_temp_new_i32(); } =20 static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src) @@ -5516,7 +5506,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) break; } #endif - cpu_dst_32 =3D get_temp_i32(dc); + cpu_dst_32 =3D tcg_temp_new_i32(); tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr, dc->mem_idx, MO_TEUL); gen_helper_ldfsr(cpu_fsr, cpu_env, cpu_fsr, cpu_dst_32= ); @@ -5762,14 +5752,7 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) gen_exception(dc, TT_NCP_INSN); goto egress; #endif - egress: - if (dc->n_t32 !=3D 0) { - int i; - for (i =3D dc->n_t32 - 1; i >=3D 0; --i) { - tcg_temp_free_i32(dc->t32[i]); - } - dc->n_t32 =3D 0; - } + egress:; } =20 static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677476975; cv=none; d=zohomail.com; s=zohoarc; b=N/MKkOwiqbbKsFqHV/8z5/zmrf4O3PabgMmxvX34ab1RbolY2oMpI/099rPP9Ol/zdtICJf5LaQUkXFPrx0soFPijNF1AK1MqivzxL+BJ6CCPER90rV23A6pQqvuB0Xk/tpzUwhQSwRlAliTw5dGquU7HZksW5soiOtanatZtWs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677476975; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cc505buS8ZqTwJy0cVRT4/uSaARbJr2+/eIoFYK/Stw=; b=JMItr0Sdb8/yhtIouV60K+p9X4lvM/G4jUFLDI6gauMdPQ78BrFnre7u6hK0OBTYkYJntZ0wxChxxjQcfwsAYJsUaE5wo0WhPFVMjXZLMfq4khqlbSs/uHkp1kTvAF0MVvD/1X32cR1u43Y20WtD+TxEVl+24Y4jKXCyNNMUA60= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677476975896286.1176662610429; Sun, 26 Feb 2023 21:49:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW82-0003cz-Q0; Mon, 27 Feb 2023 00:32:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW6a-0006vp-IM for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:31:20 -0500 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW6Y-0000ru-S9 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:31:20 -0500 Received: by mail-pl1-x62f.google.com with SMTP id ky4so5559570plb.3 for ; Sun, 26 Feb 2023 21:31:18 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.31.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:31:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cc505buS8ZqTwJy0cVRT4/uSaARbJr2+/eIoFYK/Stw=; b=YhcOvwwbiX6cL1Sdo+8L9MSukEeppnPOyBa4IG5upsnYugKpfhDtmgulzQPyY08alC t+J8F+gaWMN50jyk51AkkEUvsN9IU9Ei2o7SF1AwngIp5nMXBeMJJflAFpebcQaTxYmL GUdKqM8tCNjMt49RWemQpVo73gRTLcePqpuhvUofW/q/ROIynWBU+AeaTbkOq7PDbxCW R3lA6lQQeo86L8gbudXyW7xQzxwEGriwlCisYIrR/AFE8d/oFddZXPhDAHmOTFn7MY2a FfWnC0wvlHq89P047NAaUaBwGZ7thI82zdISSvboxOciZg4PBHFaQCEHFtBUaxlbgSxa W4kA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476976392100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/sparc/translate.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index bdf464f802..560fb32e28 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5727,32 +5727,31 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) dc->npc =3D dc->npc + 4; } jmp_insn: - goto egress; + return; illegal_insn: gen_exception(dc, TT_ILL_INSN); - goto egress; + return; unimp_flush: gen_exception(dc, TT_UNIMP_FLUSH); - goto egress; + return; #if !defined(CONFIG_USER_ONLY) priv_insn: gen_exception(dc, TT_PRIV_INSN); - goto egress; + return; #endif nfpu_insn: gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP); - goto egress; + return; #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) nfq_insn: gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR); - goto egress; + return; #endif #ifndef TARGET_SPARC64 ncp_insn: gen_exception(dc, TT_NCP_INSN); - goto egress; + return; #endif - egress:; } =20 static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.31.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:31:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x5RhcaUXSQ5MfMxq0C6EBN7haRQoUvmPfbIAZ3PLMW4=; b=i2C3OtmDKwgtknA4dBebFr4P1ptXuwnqPyYxCAL15EqXIwP1koYmIBdU/Or2wl8FGI uNKtikxkZlG5OvXoskHROlVznFjXOuqRtBcFqQ+qY5XkzQKftr/0ThoWyCXwweJev6EO sXTn35OAwpnbly+V/pxsfPRkH7YK1tLAbct+bwpI+5cE+wSLjJ4d9AgBAhv1Te/GhcjK s1O+0Lhlt/lJEWLEl9GRNWezin8j+8j2aTNrfXaN/IEyh4oLzGfRI90xGMwqJBuN+I8Y dl1FumtdNQ6xTL6a4Cp4p8F9rt9l8G+nUkYz4oYrFA2q71GfmAzWtNXLecBeguOeCqP0 3M4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x5RhcaUXSQ5MfMxq0C6EBN7haRQoUvmPfbIAZ3PLMW4=; b=dDGSmNRiOeFAukVVXiQroxSUpqdN/nsdxowMlQkh9cDYzHQ15nAETHkHJHGK8WlWXg lGMfhe8gTPPQklJFFvqhBbHY1MuWu21kApzr3YH0WknGxnWqfmTPIWIn3hnZZa1hR3Tt f5IuMO+LYGS9Y9nADVmwgaJsW6zPcE/iX0dX9ZQo+AviB+23bymwWP6aSn1+0Ub9Otyq xqFaEeMYJHWDYixIMZ7CQKhONxL4e1pBleYh9CP4Rz0mMRfDjHdhAS9YqoWSf2ickdu1 z7U5O57t0cuhrCDYrcQfjONhIaJk4P2EFND6bdPqfBCpPBHVPTA94JwJOFuV0MNC7rjV H25A== X-Gm-Message-State: AO0yUKWEm+dv38foeOuc/hLMEhNa+B/7WoTnGp6bImLIvu+KuBHDanZC ZXvFnMUctrTXLza3YDNuKyB//vgE3fMte6HNOAU= X-Google-Smtp-Source: AK7set/bBU2N8m6R3kw7PiM6j4kSYGyYo//bmKQ9tiTFvyrYfXNRuxWrAF1T4pf/Z+s3Bba8OPBLXw== X-Received: by 2002:a17:90b:3b4f:b0:233:f394:d83 with SMTP id ot15-20020a17090b3b4f00b00233f3940d83mr23795397pjb.48.1677475880647; Sun, 26 Feb 2023 21:31:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 68/76] target/sparc: Drop free_compare Date: Sun, 26 Feb 2023 19:24:57 -1000 Message-Id: <20230227052505.352889-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476458085100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Remove the g1 and g2 members of DisasCompare, as they were used to track which temps needed to be freed. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/sparc/translate.c | 32 -------------------------------- 1 file changed, 32 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 560fb32e28..f32f237051 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -93,7 +93,6 @@ typedef struct DisasContext { typedef struct { TCGCond cond; bool is_bool; - bool g1, g2; TCGv c1, c2; } DisasCompare; =20 @@ -1066,16 +1065,6 @@ static inline void gen_op_next_insn(void) tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); } =20 -static void free_compare(DisasCompare *cmp) -{ - if (!cmp->g1) { - tcg_temp_free(cmp->c1); - } - if (!cmp->g2) { - tcg_temp_free(cmp->c2); - } -} - static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond, DisasContext *dc) { @@ -1135,17 +1124,14 @@ static void gen_compare(DisasCompare *cmp, bool xcc= , unsigned int cond, cmp->cond =3D logic_cond[cond]; do_compare_dst_0: cmp->is_bool =3D false; - cmp->g2 =3D false; cmp->c2 =3D tcg_const_tl(0); #ifdef TARGET_SPARC64 if (!xcc) { - cmp->g1 =3D false; cmp->c1 =3D tcg_temp_new(); tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst); break; } #endif - cmp->g1 =3D true; cmp->c1 =3D cpu_cc_dst; break; =20 @@ -1167,7 +1153,6 @@ static void gen_compare(DisasCompare *cmp, bool xcc, = unsigned int cond, if (!xcc) { /* Note that sign-extension works for unsigned compares as long as both operands are sign-extended. */ - cmp->g1 =3D cmp->g2 =3D false; cmp->c1 =3D tcg_temp_new(); cmp->c2 =3D tcg_temp_new(); tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src); @@ -1175,7 +1160,6 @@ static void gen_compare(DisasCompare *cmp, bool xcc, = unsigned int cond, break; } #endif - cmp->g1 =3D cmp->g2 =3D true; cmp->c1 =3D cpu_cc_src; cmp->c2 =3D cpu_cc_src2; break; @@ -1192,7 +1176,6 @@ static void gen_compare(DisasCompare *cmp, bool xcc, = unsigned int cond, /* We're going to generate a boolean result. */ cmp->cond =3D TCG_COND_NE; cmp->is_bool =3D true; - cmp->g1 =3D cmp->g2 =3D false; cmp->c1 =3D r_dst =3D tcg_temp_new(); cmp->c2 =3D tcg_const_tl(0); =20 @@ -1258,7 +1241,6 @@ static void gen_fcompare(DisasCompare *cmp, unsigned = int cc, unsigned int cond) /* For now we still generate a straight boolean result. */ cmp->cond =3D TCG_COND_NE; cmp->is_bool =3D true; - cmp->g1 =3D cmp->g2 =3D false; cmp->c1 =3D r_dst =3D tcg_temp_new(); cmp->c2 =3D tcg_const_tl(0); =20 @@ -1342,8 +1324,6 @@ static void gen_cond(TCGv r_dst, unsigned int cc, uns= igned int cond, } else { tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2); } - - free_compare(&cmp); } =20 static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) @@ -1357,8 +1337,6 @@ static void gen_fcond(TCGv r_dst, unsigned int cc, un= signed int cond) } else { tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2); } - - free_compare(&cmp); } =20 #ifdef TARGET_SPARC64 @@ -1378,8 +1356,6 @@ static void gen_compare_reg(DisasCompare *cmp, int co= nd, TCGv r_src) { cmp->cond =3D tcg_invert_cond(gen_tcg_cond_reg[cond]); cmp->is_bool =3D false; - cmp->g1 =3D true; - cmp->g2 =3D false; cmp->c1 =3D r_src; cmp->c2 =3D tcg_const_tl(0); } @@ -1391,8 +1367,6 @@ static inline void gen_cond_reg(TCGv r_dst, int cond,= TCGv r_src) =20 /* The interface is to return a boolean in r_dst. */ tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2); - - free_compare(&cmp); } #endif =20 @@ -3268,7 +3242,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) l1 =3D gen_new_label(); tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond), cmp.c1, cmp.c2, l1); - free_compare(&cmp); } =20 mask =3D ((dc->def->features & CPU_FEATURE_HYPV) && superv= isor(dc) @@ -3827,7 +3800,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) cpu_src1 =3D get_src1(dc, insn); \ gen_compare_reg(&cmp, cond, cpu_src1); \ gen_fmov##sz(dc, &cmp, rd, rs2); \ - free_compare(&cmp); \ } while (0) =20 if ((xop & 0x11f) =3D=3D 0x005) { /* V9 fmovsr */ @@ -3851,7 +3823,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) cond =3D GET_FIELD_SP(insn, 14, 17); \ gen_fcompare(&cmp, fcc, cond); \ gen_fmov##sz(dc, &cmp, rd, rs2); \ - free_compare(&cmp); \ } while (0) =20 case 0x001: /* V9 fmovscc %fcc0 */ @@ -3901,7 +3872,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) cond =3D GET_FIELD_SP(insn, 14, 17); \ gen_compare(&cmp, xcc, cond, dc); \ gen_fmov##sz(dc, &cmp, rd, rs2); \ - free_compare(&cmp); \ } while (0) =20 case 0x101: /* V9 fmovscc %icc */ @@ -4713,7 +4683,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) tcg_gen_movcond_tl(cmp.cond, dst, cmp.c1, cmp.c2, cpu_src2, dst); - free_compare(&cmp); gen_store_gpr(dc, rd, dst); break; } @@ -4745,7 +4714,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) tcg_gen_movcond_tl(cmp.cond, dst, cmp.c1, cmp.c2, cpu_src2, dst); - free_compare(&cmp); gen_store_gpr(dc, rd, dst); break; } --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.31.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:31:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EOzgtxQuRYUCV99sbiOrEE+Favl4yWaCSa9C90hWUEA=; b=ZttB1+TOD9ysQkbOsXimGrHNaSj4/UnD4fdILTdfjrhmgc6RNSjIftr6i6v/GQXJuz d0KtMA0iHGMxQLUxtLOSORJNPZirX3sxbGU+812DIrj3rL+MhdV5+6rhfaRIDTgc5+RC nXqKOzO/1SB/WK7v14K75jQ0rQ2GtD+2R1uB+xbEu80Y2Yj3CWk6+dyadCSc4B6SyGNf h9XxWmnhTUEL1UqflqqFc9qmSa8rdRpkaZNX8CusjmjTrrypHqDcYAhDQClMOX+c5x2r 8C/aXZDdAunp0Lcmadlq0XfbTTZ0kFICiETG0cgQynyHG0lUnmld/qKXXu1Wc3YXr9d2 Sncw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EOzgtxQuRYUCV99sbiOrEE+Favl4yWaCSa9C90hWUEA=; b=PzuVCC05OhUO58x9RUcRdzsgvvPPrX1yb+rRYrQeXCVWofuSTYJyyV8pLGqJ0rZRUb Dyp2btcjlrQ4YdYzCtL0sezI5YrBw+nhPB96Uh432LeJ7yJms/K/tSUQEZHSMZld8dxr vjYROYeKgHSKUfr5XN/QgbG/pQtE4Z8Df6wjOiPJnBoGWapVavagvttUae0YVtPAH2RT XsqmNx5B2Rq0ra5ivkgBdOKh9tDBEYkb6GlV89nvw/LBu9aybUrrOARz58b+inn8SqgB rAeV6Wf0svoLuRyRj5w7TBJIF1QTcEJyred76Guo4YlRNOGI7yEB51Yf6RNvTeYVd0W2 PLag== X-Gm-Message-State: AO0yUKUfPIgBcKajljyDO4Uke5gDnmKH3zVgnZJXfXQCpbzMlO2rJktg Vi1DUgtD1H7HKK8bNfd47/lBq1CScOYO/SgvSXFFkQ== X-Google-Smtp-Source: AK7set9/Gojb8cCWsIQ0eMuwSSs60Fxzbs3QZBsr1vslVAnhKfUqmJihF4YBdRiYpLWIMbvnDMKTJQ== X-Received: by 2002:a17:90a:ea05:b0:237:7149:b333 with SMTP id w5-20020a17090aea0500b002377149b333mr12816363pjy.43.1677475883390; Sun, 26 Feb 2023 21:31:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 69/76] target/sparc: Drop tcg_temp_free Date: Sun, 26 Feb 2023 19:24:58 -1000 Message-Id: <20230227052505.352889-70-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x641.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476524372100009 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- target/sparc/translate.c | 136 --------------------------------------- 1 file changed, 136 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index f32f237051..814f3f8b1e 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -158,7 +158,6 @@ static void gen_store_fpr_F(DisasContext *dc, unsigned = int dst, TCGv_i32 v) tcg_gen_extu_i32_i64(t, v); tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t, (dst & 1 ? 0 : 32), 32); - tcg_temp_free_i64(t); gen_update_fprs_dirty(dc, dst); } =20 @@ -378,11 +377,6 @@ static TCGv_i32 gen_add32_carry32(void) carry_32 =3D tcg_temp_new_i32(); tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32); =20 -#if TARGET_LONG_BITS =3D=3D 64 - tcg_temp_free_i32(cc_src1_32); - tcg_temp_free_i32(cc_src2_32); -#endif - return carry_32; } =20 @@ -404,11 +398,6 @@ static TCGv_i32 gen_sub32_carry32(void) carry_32 =3D tcg_temp_new_i32(); tcg_gen_setcond_i32(TCG_COND_LTU, carry_32, cc_src1_32, cc_src2_32); =20 -#if TARGET_LONG_BITS =3D=3D 64 - tcg_temp_free_i32(cc_src1_32); - tcg_temp_free_i32(cc_src2_32); -#endif - return carry_32; } =20 @@ -439,7 +428,6 @@ static void gen_op_addx_int(DisasContext *dc, TCGv dst,= TCGv src1, generated the carry in the first place. */ carry =3D tcg_temp_new(); tcg_gen_add2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src= 2); - tcg_temp_free(carry); goto add_done; } carry_32 =3D gen_add32_carry32(); @@ -468,11 +456,6 @@ static void gen_op_addx_int(DisasContext *dc, TCGv dst= , TCGv src1, tcg_gen_add_tl(dst, src1, src2); tcg_gen_add_tl(dst, dst, carry); =20 - tcg_temp_free_i32(carry_32); -#if TARGET_LONG_BITS =3D=3D 64 - tcg_temp_free(carry); -#endif - add_done: if (update_cc) { tcg_gen_mov_tl(cpu_cc_src, src1); @@ -524,7 +507,6 @@ static void gen_op_subx_int(DisasContext *dc, TCGv dst,= TCGv src1, generated the carry in the first place. */ carry =3D tcg_temp_new(); tcg_gen_sub2_tl(carry, dst, cpu_cc_src, src1, cpu_cc_src2, src= 2); - tcg_temp_free(carry); goto sub_done; } carry_32 =3D gen_sub32_carry32(); @@ -547,11 +529,6 @@ static void gen_op_subx_int(DisasContext *dc, TCGv dst= , TCGv src1, tcg_gen_sub_tl(dst, src1, src2); tcg_gen_sub_tl(dst, dst, carry); =20 - tcg_temp_free_i32(carry_32); -#if TARGET_LONG_BITS =3D=3D 64 - tcg_temp_free(carry); -#endif - sub_done: if (update_cc) { tcg_gen_mov_tl(cpu_cc_src, src1); @@ -579,7 +556,6 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, T= CGv src2) tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff); tcg_gen_movcond_tl(TCG_COND_EQ, cpu_cc_src2, r_temp, zero, zero, cpu_cc_src2); - tcg_temp_free(zero); =20 // b2 =3D T0 & 1; // env->y =3D (b2 << 31) | (env->y >> 1); @@ -590,14 +566,12 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1,= TCGv src2) gen_mov_reg_N(t0, cpu_psr); gen_mov_reg_V(r_temp, cpu_psr); tcg_gen_xor_tl(t0, t0, r_temp); - tcg_temp_free(r_temp); =20 // T0 =3D (b1 << 31) | (T0 >> 1); // src1 =3D T0; tcg_gen_shli_tl(t0, t0, 31); tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1); tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); - tcg_temp_free(t0); =20 tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); =20 @@ -625,9 +599,6 @@ static inline void gen_op_multiply(TCGv dst, TCGv src1,= TCGv src2, int sign_ext) } =20 tcg_gen_mul_i64(dst, t0, t1); - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_gen_shri_i64(cpu_y, dst, 32); #endif } @@ -665,7 +636,6 @@ static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 s= rc) tcg_gen_xor_tl(dst, dst, t0); gen_mov_reg_Z(t0, src); tcg_gen_or_tl(dst, dst, t0); - tcg_temp_free(t0); } =20 // N ^ V @@ -675,7 +645,6 @@ static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 sr= c) gen_mov_reg_V(t0, src); gen_mov_reg_N(dst, src); tcg_gen_xor_tl(dst, dst, t0); - tcg_temp_free(t0); } =20 // C | Z @@ -685,7 +654,6 @@ static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 = src) gen_mov_reg_Z(t0, src); gen_mov_reg_C(dst, src); tcg_gen_or_tl(dst, dst, t0); - tcg_temp_free(t0); } =20 // C @@ -790,7 +758,6 @@ static inline void gen_op_eval_fbne(TCGv dst, TCGv src, gen_mov_reg_FCC0(dst, src, fcc_offset); gen_mov_reg_FCC1(t0, src, fcc_offset); tcg_gen_or_tl(dst, dst, t0); - tcg_temp_free(t0); } =20 // 1 or 2: FCC0 ^ FCC1 @@ -801,7 +768,6 @@ static inline void gen_op_eval_fblg(TCGv dst, TCGv src, gen_mov_reg_FCC0(dst, src, fcc_offset); gen_mov_reg_FCC1(t0, src, fcc_offset); tcg_gen_xor_tl(dst, dst, t0); - tcg_temp_free(t0); } =20 // 1 or 3: FCC0 @@ -819,7 +785,6 @@ static inline void gen_op_eval_fbl(TCGv dst, TCGv src, gen_mov_reg_FCC0(dst, src, fcc_offset); gen_mov_reg_FCC1(t0, src, fcc_offset); tcg_gen_andc_tl(dst, dst, t0); - tcg_temp_free(t0); } =20 // 2 or 3: FCC1 @@ -837,7 +802,6 @@ static inline void gen_op_eval_fbg(TCGv dst, TCGv src, gen_mov_reg_FCC0(dst, src, fcc_offset); gen_mov_reg_FCC1(t0, src, fcc_offset); tcg_gen_andc_tl(dst, t0, dst); - tcg_temp_free(t0); } =20 // 3: FCC0 & FCC1 @@ -848,7 +812,6 @@ static inline void gen_op_eval_fbu(TCGv dst, TCGv src, gen_mov_reg_FCC0(dst, src, fcc_offset); gen_mov_reg_FCC1(t0, src, fcc_offset); tcg_gen_and_tl(dst, dst, t0); - tcg_temp_free(t0); } =20 // 0: !(FCC0 | FCC1) @@ -860,7 +823,6 @@ static inline void gen_op_eval_fbe(TCGv dst, TCGv src, gen_mov_reg_FCC1(t0, src, fcc_offset); tcg_gen_or_tl(dst, dst, t0); tcg_gen_xori_tl(dst, dst, 0x1); - tcg_temp_free(t0); } =20 // 0 or 3: !(FCC0 ^ FCC1) @@ -872,7 +834,6 @@ static inline void gen_op_eval_fbue(TCGv dst, TCGv src, gen_mov_reg_FCC1(t0, src, fcc_offset); tcg_gen_xor_tl(dst, dst, t0); tcg_gen_xori_tl(dst, dst, 0x1); - tcg_temp_free(t0); } =20 // 0 or 2: !FCC0 @@ -892,7 +853,6 @@ static inline void gen_op_eval_fbuge(TCGv dst, TCGv src, gen_mov_reg_FCC1(t0, src, fcc_offset); tcg_gen_andc_tl(dst, dst, t0); tcg_gen_xori_tl(dst, dst, 0x1); - tcg_temp_free(t0); } =20 // 0 or 1: !FCC1 @@ -912,7 +872,6 @@ static inline void gen_op_eval_fbule(TCGv dst, TCGv src, gen_mov_reg_FCC1(t0, src, fcc_offset); tcg_gen_andc_tl(dst, t0, dst); tcg_gen_xori_tl(dst, dst, 0x1); - tcg_temp_free(t0); } =20 // !3: !(FCC0 & FCC1) @@ -924,7 +883,6 @@ static inline void gen_op_eval_fbo(TCGv dst, TCGv src, gen_mov_reg_FCC1(t0, src, fcc_offset); tcg_gen_and_tl(dst, dst, t0); tcg_gen_xori_tl(dst, dst, 0x1); - tcg_temp_free(t0); } =20 static inline void gen_branch2(DisasContext *dc, target_ulong pc1, @@ -973,8 +931,6 @@ static void gen_branch_n(DisasContext *dc, target_ulong= pc1) t =3D tcg_const_tl(pc1); z =3D tcg_const_tl(0); tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, z, t, cpu_npc); - tcg_temp_free(t); - tcg_temp_free(z); =20 dc->pc =3D DYNAMIC_PC; } @@ -987,10 +943,6 @@ static inline void gen_generic_branch(DisasContext *dc) TCGv zero =3D tcg_const_tl(0); =20 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1); - - tcg_temp_free(npc0); - tcg_temp_free(npc1); - tcg_temp_free(zero); } =20 /* call this function before using the condition register as it may @@ -1034,7 +986,6 @@ static void gen_exception(DisasContext *dc, int which) save_state(dc); t =3D tcg_const_i32(which); gen_helper_raise_exception(cpu_env, t); - tcg_temp_free_i32(t); dc->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -1042,7 +993,6 @@ static void gen_check_align(TCGv addr, int mask) { TCGv_i32 r_mask =3D tcg_const_i32(mask); gen_helper_check_align(cpu_env, addr, r_mask); - tcg_temp_free_i32(r_mask); } =20 static inline void gen_mov_pc_npc(DisasContext *dc) @@ -1961,7 +1911,6 @@ static void gen_ldstub(DisasContext *dc, TCGv dst, TC= Gv addr, int mmu_idx) TCGv m1 =3D tcg_const_tl(0xff); gen_address_mask(dc, addr); tcg_gen_atomic_xchg_tl(dst, addr, m1, mmu_idx, MO_UB); - tcg_temp_free(m1); } =20 /* asi moves */ @@ -2225,11 +2174,8 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, T= CGv addr, TCGv_i64 t64 =3D tcg_temp_new_i64(); gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop); tcg_gen_trunc_i64_tl(dst, t64); - tcg_temp_free_i64(t64); } #endif - tcg_temp_free_i32(r_mop); - tcg_temp_free_i32(r_asi); } break; } @@ -2285,11 +2231,6 @@ static void gen_st_asi(DisasContext *dc, TCGv src, T= CGv addr, tcg_gen_add_tl(saddr, saddr, four); tcg_gen_add_tl(daddr, daddr, four); } - - tcg_temp_free(saddr); - tcg_temp_free(daddr); - tcg_temp_free(four); - tcg_temp_free_i32(tmp); } break; #endif @@ -2306,11 +2247,8 @@ static void gen_st_asi(DisasContext *dc, TCGv src, T= CGv addr, TCGv_i64 t64 =3D tcg_temp_new_i64(); tcg_gen_extu_tl_i64(t64, src); gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop); - tcg_temp_free_i64(t64); } #endif - tcg_temp_free_i32(r_mop); - tcg_temp_free_i32(r_asi); =20 /* A write to a TLB register may alter page maps. End the TB.= */ dc->npc =3D DYNAMIC_PC; @@ -2351,7 +2289,6 @@ static void gen_cas_asi(DisasContext *dc, TCGv addr, = TCGv cmpv, tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd), da.mem_idx, da.memop); gen_store_gpr(dc, rd, oldv); - tcg_temp_free(oldv); break; default: /* ??? Should be DAE_invalid_asi. */ @@ -2386,12 +2323,8 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv ds= t, TCGv addr, int insn) =20 s64 =3D tcg_const_i64(0xff); gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_mop); - tcg_temp_free_i64(s64); - tcg_temp_free_i32(r_mop); - tcg_temp_free_i32(r_asi); =20 tcg_gen_trunc_i64_tl(dst, t64); - tcg_temp_free_i64(t64); =20 /* End the TB. */ dc->npc =3D DYNAMIC_PC; @@ -2432,7 +2365,6 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr, tcg_gen_qemu_ld_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, da.memop | MO_ALIGN_4); tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); - tcg_temp_free_i64(d64); break; default: g_assert_not_reached(); @@ -2460,7 +2392,6 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr, tcg_gen_add_tl(addr, addr, eight); memop =3D da.memop; } - tcg_temp_free(eight); } else { gen_exception(dc, TT_ILL_INSN); } @@ -2492,7 +2423,6 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr, gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_mop); d32 =3D gen_dest_fpr_F(dc); tcg_gen_extrl_i64_i32(d32, d64); - tcg_temp_free_i64(d64); gen_store_fpr_F(dc, rd, d32); break; case 8: @@ -2504,13 +2434,10 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr, tcg_gen_addi_tl(addr, addr, 8); gen_helper_ld_asi(cpu_fpr[rd/2+1], cpu_env, addr, r_asi, r= _mop); tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); - tcg_temp_free_i64(d64); break; default: g_assert_not_reached(); } - tcg_temp_free_i32(r_mop); - tcg_temp_free_i32(r_asi); } break; } @@ -2574,7 +2501,6 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr, tcg_gen_add_tl(addr, addr, eight); memop =3D da.memop; } - tcg_temp_free(eight); } else { gen_exception(dc, TT_ILL_INSN); } @@ -2631,7 +2557,6 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr,= int insn, int rd) } else { tcg_gen_extr32_i64(hi, lo, tmp); } - tcg_temp_free_i64(tmp); } break; =20 @@ -2647,8 +2572,6 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr,= int insn, int rd) =20 save_state(dc); gen_helper_ld_asi(tmp, cpu_env, addr, r_asi, r_mop); - tcg_temp_free_i32(r_asi); - tcg_temp_free_i32(r_mop); =20 /* See above. */ if ((da.memop & MO_BSWAP) =3D=3D MO_TE) { @@ -2656,7 +2579,6 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr,= int insn, int rd) } else { tcg_gen_extr32_i64(hi, lo, tmp); } - tcg_temp_free_i64(tmp); } break; } @@ -2696,7 +2618,6 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, T= CGv addr, } gen_address_mask(dc, addr); tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop); - tcg_temp_free_i64(t64); } break; =20 @@ -2717,9 +2638,6 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, T= CGv addr, =20 save_state(dc); gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop); - tcg_temp_free_i32(r_mop); - tcg_temp_free_i32(r_asi); - tcg_temp_free_i64(t64); } break; } @@ -2739,7 +2657,6 @@ static void gen_casx_asi(DisasContext *dc, TCGv addr,= TCGv cmpv, tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd), da.mem_idx, da.memop); gen_store_gpr(dc, rd, oldv); - tcg_temp_free(oldv); break; default: /* ??? Should be DAE_invalid_asi. */ @@ -2762,7 +2679,6 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr,= int insn, int rd) =20 switch (da.type) { case GET_ASI_EXCP: - tcg_temp_free_i64(t64); return; case GET_ASI_DIRECT: gen_address_mask(dc, addr); @@ -2775,14 +2691,11 @@ static void gen_ldda_asi(DisasContext *dc, TCGv add= r, int insn, int rd) =20 save_state(dc); gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop); - tcg_temp_free_i32(r_mop); - tcg_temp_free_i32(r_asi); } break; } =20 tcg_gen_extr_i64_i32(lo, hi, t64); - tcg_temp_free_i64(t64); gen_store_gpr(dc, rd | 1, lo); gen_store_gpr(dc, rd, hi); } @@ -2819,9 +2732,6 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, T= CGv addr, tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop); tcg_gen_add_tl(d_addr, d_addr, eight); } - - tcg_temp_free(d_addr); - tcg_temp_free(eight); } break; default: @@ -2831,13 +2741,9 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, = TCGv addr, =20 save_state(dc); gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop); - tcg_temp_free_i32(r_mop); - tcg_temp_free_i32(r_asi); } break; } - - tcg_temp_free_i64(t64); } #endif =20 @@ -2875,7 +2781,6 @@ static void gen_fmovs(DisasContext *dc, DisasCompare = *cmp, int rd, int rs) TCGv_i64 c64 =3D tcg_temp_new_i64(); tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2); tcg_gen_extrl_i64_i32(c32, c64); - tcg_temp_free_i64(c64); } =20 s1 =3D gen_load_fpr_F(dc, rs); @@ -2885,8 +2790,6 @@ static void gen_fmovs(DisasContext *dc, DisasCompare = *cmp, int rd, int rs) =20 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2); =20 - tcg_temp_free_i32(c32); - tcg_temp_free_i32(zero); gen_store_fpr_F(dc, rd, dst); } =20 @@ -2932,10 +2835,7 @@ static inline void gen_load_trap_state_at_tl(TCGv_pt= r r_tsptr, TCGv_env cpu_env) TCGv_ptr r_tl_tmp =3D tcg_temp_new_ptr(); tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl); tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp); - tcg_temp_free_ptr(r_tl_tmp); } - - tcg_temp_free_i32(r_tl); } #endif =20 @@ -3035,11 +2935,6 @@ static void gen_edge(DisasContext *dc, TCGv dst, TCG= v s1, TCGv s2, tcg_gen_neg_tl(t1, t1); tcg_gen_or_tl(lo2, lo2, t1); tcg_gen_and_tl(dst, dst, lo2); - - tcg_temp_free(lo1); - tcg_temp_free(lo2); - tcg_temp_free(t1); - tcg_temp_free(t2); } =20 static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left) @@ -3052,8 +2947,6 @@ static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2,= bool left) tcg_gen_neg_tl(tmp, tmp); } tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3); - - tcg_temp_free(tmp); } =20 static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) @@ -3075,10 +2968,6 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv = s1, TCGv s2) tcg_gen_shri_tl(t2, t2, 1); =20 tcg_gen_or_tl(dst, t1, t2); - - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(shift); } #endif =20 @@ -3278,7 +3167,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) } =20 gen_helper_raise_exception(cpu_env, trap); - tcg_temp_free_i32(trap); =20 if (cond =3D=3D 8) { /* An unconditional trap ends the TB. */ @@ -3337,8 +3225,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) } gen_helper_tick_get_count(cpu_dst, cpu_env, r_tick= ptr, r_const); - tcg_temp_free_ptr(r_tickptr); - tcg_temp_free_i32(r_const); gen_store_gpr(dc, rd, cpu_dst); if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { /* I/O operations in icount mode must end the = TB */ @@ -3391,8 +3277,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) } gen_helper_tick_get_count(cpu_dst, cpu_env, r_tick= ptr, r_const); - tcg_temp_free_ptr(r_tickptr); - tcg_temp_free_i32(r_const); gen_store_gpr(dc, rd, cpu_dst); if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { /* I/O operations in icount mode must end the = TB */ @@ -3478,7 +3362,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) gen_load_trap_state_at_tl(r_tsptr, cpu_env); tcg_gen_ld_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tpc)); - tcg_temp_free_ptr(r_tsptr); } break; case 1: // tnpc @@ -3489,7 +3372,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) gen_load_trap_state_at_tl(r_tsptr, cpu_env); tcg_gen_ld_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tnpc)); - tcg_temp_free_ptr(r_tsptr); } break; case 2: // tstate @@ -3500,7 +3382,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) gen_load_trap_state_at_tl(r_tsptr, cpu_env); tcg_gen_ld_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tstate)); - tcg_temp_free_ptr(r_tsptr); } break; case 3: // tt @@ -3510,7 +3391,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) gen_load_trap_state_at_tl(r_tsptr, cpu_env); tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tt)); - tcg_temp_free_ptr(r_tsptr); } break; case 4: // tick @@ -3527,8 +3407,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) } gen_helper_tick_get_count(cpu_tmp0, cpu_env, r_tickptr, r_const); - tcg_temp_free_ptr(r_tickptr); - tcg_temp_free_i32(r_const); if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { /* I/O operations in icount mode must end the = TB */ dc->base.is_jmp =3D DISAS_EXIT; @@ -4343,7 +4221,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) } gen_helper_tick_set_limit(r_tickptr, cpu_tick_cmp= r); - tcg_temp_free_ptr(r_tickptr); /* End TB to handle timer interrupt */ dc->base.is_jmp =3D DISAS_EXIT; } @@ -4367,7 +4244,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) } gen_helper_tick_set_count(r_tickptr, cpu_tmp0); - tcg_temp_free_ptr(r_tickptr); /* End TB to handle timer interrupt */ dc->base.is_jmp =3D DISAS_EXIT; } @@ -4391,7 +4267,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) } gen_helper_tick_set_limit(r_tickptr, cpu_stick_cm= pr); - tcg_temp_free_ptr(r_tickptr); /* End TB to handle timer interrupt */ dc->base.is_jmp =3D DISAS_EXIT; } @@ -4457,7 +4332,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) gen_load_trap_state_at_tl(r_tsptr, cpu= _env); tcg_gen_st_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tpc= )); - tcg_temp_free_ptr(r_tsptr); } break; case 1: // tnpc @@ -4468,7 +4342,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) gen_load_trap_state_at_tl(r_tsptr, cpu= _env); tcg_gen_st_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tnp= c)); - tcg_temp_free_ptr(r_tsptr); } break; case 2: // tstate @@ -4480,7 +4353,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) tcg_gen_st_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tstate)); - tcg_temp_free_ptr(r_tsptr); } break; case 3: // tt @@ -4491,7 +4363,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) gen_load_trap_state_at_tl(r_tsptr, cpu= _env); tcg_gen_st32_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, t= t)); - tcg_temp_free_ptr(r_tsptr); } break; case 4: // tick @@ -4507,7 +4378,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) } gen_helper_tick_set_count(r_tickptr, cpu_tmp0); - tcg_temp_free_ptr(r_tickptr); /* End TB to handle timer interrupt */ dc->base.is_jmp =3D DISAS_EXIT; } @@ -4638,7 +4508,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) } gen_helper_tick_set_limit(r_tickptr, cpu_hstick_c= mpr); - tcg_temp_free_ptr(r_tickptr); /* End TB to handle timer interrupt */ dc->base.is_jmp =3D DISAS_EXIT; } @@ -5340,7 +5209,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) gen_store_gpr(dc, rd + 1, cpu_val); tcg_gen_shri_i64(t64, t64, 32); tcg_gen_trunc_i64_tl(cpu_val, t64); - tcg_temp_free_i64(t64); tcg_gen_ext32u_tl(cpu_val, cpu_val); } break; @@ -5470,7 +5338,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) tcg_gen_qemu_ld_i64(t64, cpu_addr, dc->mem_idx, MO_TEUQ); gen_helper_ldxfsr(cpu_fsr, cpu_env, cpu_fsr, t64); - tcg_temp_free_i64(t64); break; } #endif @@ -5490,8 +5357,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) tcg_gen_qemu_ld_i64(cpu_src2_64, cpu_addr, dc->mem_idx, MO_TEUQ | MO_ALIGN_4); gen_store_fpr_Q(dc, rd, cpu_src1_64, cpu_src2_64); - tcg_temp_free_i64(cpu_src1_64); - tcg_temp_free_i64(cpu_src2_64); break; case 0x23: /* lddf, load double fpreg */ gen_address_mask(dc, cpu_addr); @@ -5532,7 +5397,6 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) t64 =3D tcg_temp_new_i64(); tcg_gen_concat_tl_i64(t64, lo, cpu_val); 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.31.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:31:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hhu6BTqgBT2mQSY+4n4fD9nQI+aXC68pwtEhdchFB+0=; b=NVxm+eiK/Y33CO98XKRfv3TTzn1FYl6e/SM6Etw0rfOHhvSRVGSVbQN3FlX66xHAp1 hQuZpcUvpgHSZToEbHKWz1Qgq1GhyFoQEhK3cyHSDcQtEMTk4AAlRVw1s/ZUowQhRpur gFqVsOSr8hkm+yLXIoeapU4xtVHAB0oVmWXR8FaukKyzB6mQtJbAEyxvr94NeaFPn4YP Pvm0uWJtQIbVDw7PG2sK1qRi/JCXCPqTtfk6JR8ZNf4XrofMPe7pQJ4XM6D56ibRUaBn ktlPsztmZ6gJAU73gKpPvzKjjiWDTv6igYh+VnZhk+ui4D91aOhx6iG4IYQGpC8xLYLL 07aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hhu6BTqgBT2mQSY+4n4fD9nQI+aXC68pwtEhdchFB+0=; b=KNlYajWBTmTEd85BDiB7bWfQ+ziy+HVMFvPNt4JcRh8xvBboBlXwu5Bm/NPB150Wa8 455EJbkIrIEeijNiBLrgYHAlrEiXC5zcPKiuHCEBdhIbcqH5FxD22nhS1Y8cBP4p/6U8 U84TnCk1imMLyHWdf97PfMm8xS2t29xvSV3ssevQsYWkosZ6EtARywLCjOrMBZdNlhMa 89CpOPxWBL0ssGYaJgo//+0XASzrfMIzDzxl7rHOkivp57LdFvCFzWhaSTmH1v5XUF5U xWy95pBtDexLKAtZ77hH6fxeMFqbKR9th2VlOHghbqMgOXKRw+DOdaCh3wrT3L1PdXAF L/tg== X-Gm-Message-State: AO0yUKWvxVrW7YdhmTu8H5BL5mVPR5PQfy43Nghc1Z252PENkGoWIK/X zUw8mcwpyDdz3ihJTsYvgnHXcMKx8HdN8H/80Fo6LQ== X-Google-Smtp-Source: AK7set/9diuGkef0kVPbTTImwPQbrCyIxehG4bTcdyfr33tY4HhoLYq+5hHwAETxMv7gHoT95vVDYg== X-Received: by 2002:a17:90b:1b09:b0:233:c3e7:bd37 with SMTP id nu9-20020a17090b1b0900b00233c3e7bd37mr7792495pjb.10.1677475888092; Sun, 26 Feb 2023 21:31:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 70/76] target/tricore: Drop tcg_temp_free Date: Sun, 26 Feb 2023 19:24:59 -1000 Message-Id: <20230227052505.352889-71-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x641.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476574541100005 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/tricore/translate.c | 540 +------------------------------------ 1 file changed, 4 insertions(+), 536 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 176ea96b2b..127f9a989a 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -126,7 +126,6 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int = flags) #define gen_helper_1arg(name, arg) do { \ TCGv_i32 helper_tmp =3D tcg_const_i32(arg); \ gen_helper_##name(cpu_env, helper_tmp); \ - tcg_temp_free_i32(helper_tmp); \ } while (0) =20 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \ @@ -137,9 +136,6 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int = flags) tcg_gen_ext16s_tl(arg01, arg0); \ tcg_gen_ext16s_tl(arg11, arg1); \ gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ - tcg_temp_free(arg00); \ - tcg_temp_free(arg01); \ - tcg_temp_free(arg11); \ } while (0) =20 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \ @@ -152,10 +148,6 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int= flags) tcg_gen_sari_tl(arg11, arg1, 16); \ tcg_gen_ext16s_tl(arg10, arg1); \ gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ - tcg_temp_free(arg00); \ - tcg_temp_free(arg01); \ - tcg_temp_free(arg10); \ - tcg_temp_free(arg11); \ } while (0) =20 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \ @@ -168,10 +160,6 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int= flags) tcg_gen_sari_tl(arg10, arg1, 16); \ tcg_gen_ext16s_tl(arg11, arg1); \ gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ - tcg_temp_free(arg00); \ - tcg_temp_free(arg01); \ - tcg_temp_free(arg10); \ - tcg_temp_free(arg11); \ } while (0) =20 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \ @@ -182,9 +170,6 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int = flags) tcg_gen_ext16s_tl(arg00, arg0); \ tcg_gen_sari_tl(arg11, arg1, 16); \ gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ - tcg_temp_free(arg00); \ - tcg_temp_free(arg01); \ - tcg_temp_free(arg11); \ } while (0) =20 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \ @@ -194,9 +179,6 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int = flags) tcg_gen_concat_i32_i64(arg1, al1, ah1); \ gen_helper_##name(ret, arg1, arg2); \ tcg_gen_extr_i64_i32(rl, rh, ret); \ - \ - tcg_temp_free_i64(ret); \ - tcg_temp_free_i64(arg1); \ } while (0) =20 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \ @@ -204,8 +186,6 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int = flags) \ gen_helper_##name(ret, cpu_env, arg1, arg2); \ tcg_gen_extr_i64_i32(rl, rh, ret); \ - \ - tcg_temp_free_i64(ret); \ } while (0) =20 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF)) @@ -229,7 +209,6 @@ static inline void gen_offset_ld(DisasContext *ctx, TCG= v r1, TCGv r2, TCGv temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, r2, con); tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); - tcg_temp_free(temp); } =20 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, @@ -238,7 +217,6 @@ static inline void gen_offset_st(DisasContext *ctx, TCG= v r1, TCGv r2, TCGv temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, r2, con); tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); - tcg_temp_free(temp); } =20 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *= ctx) @@ -247,8 +225,6 @@ static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv addr= ess, DisasContext *ctx) =20 tcg_gen_concat_i32_i64(temp, rl, rh); tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEUQ); - - tcg_temp_free_i64(temp); } =20 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, @@ -257,7 +233,6 @@ static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv = base, int16_t con, TCGv temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, base, con); gen_st_2regs_64(rh, rl, temp, ctx); - tcg_temp_free(temp); } =20 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *= ctx) @@ -267,8 +242,6 @@ static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv addr= ess, DisasContext *ctx) tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEUQ); /* write back to two 32 bit regs */ tcg_gen_extr_i64_i32(rl, rh, temp); - - tcg_temp_free_i64(temp); } =20 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, @@ -277,7 +250,6 @@ static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv = base, int16_t con, TCGv temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, base, con); gen_ld_2regs_64(rh, rl, temp, ctx); - tcg_temp_free(temp); } =20 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t of= f, @@ -287,7 +259,6 @@ static void gen_st_preincr(DisasContext *ctx, TCGv r1, = TCGv r2, int16_t off, tcg_gen_addi_tl(temp, r2, off); tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); tcg_gen_mov_tl(r2, temp); - tcg_temp_free(temp); } =20 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t of= f, @@ -297,7 +268,6 @@ static void gen_ld_preincr(DisasContext *ctx, TCGv r1, = TCGv r2, int16_t off, tcg_gen_addi_tl(temp, r2, off); tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); tcg_gen_mov_tl(r2, temp); - tcg_temp_free(temp); } =20 /* M(EA, word) =3D (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32= ]); */ @@ -317,9 +287,6 @@ static void gen_ldmst(DisasContext *ctx, int ereg, TCGv= ea) tcg_gen_or_tl(temp, temp, temp2); /* M(EA, word) =3D temp; */ tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 /* tmp =3D M(EA, word); @@ -332,8 +299,6 @@ static void gen_swap(DisasContext *ctx, int reg, TCGv e= a) tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL); tcg_gen_mov_tl(cpu_gpr_d[reg], temp); - - tcg_temp_free(temp); } =20 static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea) @@ -345,9 +310,6 @@ static void gen_cmpswap(DisasContext *ctx, int reg, TCG= v ea) cpu_gpr_d[reg], temp); tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); tcg_gen_mov_tl(cpu_gpr_d[reg], temp); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea) @@ -362,10 +324,6 @@ static void gen_swapmsk(DisasContext *ctx, int reg, TC= Gv ea) tcg_gen_or_tl(temp2, temp2, temp3); tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); tcg_gen_mov_tl(cpu_gpr_d[reg], temp); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); } =20 =20 @@ -447,9 +405,6 @@ static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2) tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* write back result */ tcg_gen_mov_tl(ret, result); - - tcg_temp_free(result); - tcg_temp_free(t0); } =20 static inline void @@ -476,11 +431,6 @@ gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* write back result */ tcg_gen_mov_i64(ret, result); - - tcg_temp_free(temp); - tcg_temp_free_i64(result); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 static inline void @@ -527,11 +477,6 @@ gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_lo= w, TCGv r1_high, TCGv r2, tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); /* calc SAV bit */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); - tcg_temp_free(temp4); } =20 /* ret =3D r2 + (r1 * r3); */ @@ -564,17 +509,12 @@ static inline void gen_madd32_d(TCGv ret, TCGv r1, TC= Gv r2, TCGv r3) tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); /* calc SAV */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); } =20 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_madd32_d(ret, r1, r2, temp); - tcg_temp_free(temp); } =20 static inline void @@ -603,11 +543,6 @@ gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCG= v r2_low, TCGv r2_high, /* write back the result */ tcg_gen_mov_tl(ret_low, t3); tcg_gen_mov_tl(ret_high, t4); - - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(t3); - tcg_temp_free(t4); } =20 static inline void @@ -638,10 +573,6 @@ gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TC= Gv r2_low, TCGv r2_high, tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); /* calc SAV */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); } =20 static inline void @@ -650,7 +581,6 @@ gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCG= v r2_low, TCGv r2_high, { TCGv temp =3D tcg_const_i32(con); gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); - tcg_temp_free(temp); } =20 static inline void @@ -659,7 +589,6 @@ gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TC= Gv r2_low, TCGv r2_high, { TCGv temp =3D tcg_const_i32(con); gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); - tcg_temp_free(temp); } =20 static inline void @@ -686,9 +615,6 @@ gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TC= Gv r1_high, TCGv r2, tcg_gen_extr_i64_i32(temp, temp2, temp64); gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, tcg_gen_add_tl, tcg_gen_add_tl); - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -715,9 +641,6 @@ gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, = TCGv r1_high, TCGv r2, tcg_gen_extr_i64_i32(temp, temp2, temp64); gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, tcg_gen_sub_tl, tcg_gen_add_tl); - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -751,11 +674,6 @@ gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low= , TCGv r1_high, TCGv r2, gen_add64_d(temp64_2, temp64_3, temp64); /* write back result */ tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); - tcg_temp_free_i64(temp64_2); - tcg_temp_free_i64(temp64_3); } =20 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2); @@ -792,12 +710,6 @@ gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, = TCGv r1_high, TCGv r2, tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); /* combine av bits */ tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); - tcg_temp_free_i64(temp64); - } =20 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2); @@ -834,12 +746,6 @@ gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low= , TCGv r1_high, TCGv r2, tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); /* combine av bits */ tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); - tcg_temp_free_i64(temp64); - } =20 static inline void @@ -872,10 +778,6 @@ gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_lo= w, TCGv r1_high, TCGv r2, =20 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); - tcg_temp_free_i64(temp64_2); } =20 =20 @@ -905,11 +807,6 @@ gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, = TCGv r1_high, TCGv r2, gen_add64_d(temp64_3, temp64_2, temp64); /* write back result */ tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); - tcg_temp_free_i64(temp64_2); - tcg_temp_free_i64(temp64_3); } =20 static inline void @@ -936,10 +833,6 @@ gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low,= TCGv r1_high, TCGv r2, tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); - tcg_temp_free_i64(temp64_2); } =20 static inline void @@ -963,9 +856,6 @@ gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv= r2, TCGv r3, uint32_t n, break; } gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -977,9 +867,6 @@ gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint= 32_t n, uint32_t mode) tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_shli_tl(temp, r1, 16); gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -1005,10 +892,6 @@ gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, = uint32_t n, uint32_t mode) tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_shli_tl(temp, r1, 16); gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free_i64(temp64); } =20 =20 @@ -1033,9 +916,6 @@ gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TC= Gv r2, TCGv r3, break; } gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -1047,9 +927,6 @@ gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, ui= nt32_t n, uint32_t mode) tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_shli_tl(temp, r1, 16); gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -1075,10 +952,6 @@ gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3,= uint32_t n, uint32_t mode) tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_shli_tl(temp, r1, 16); gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -1086,7 +959,6 @@ gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint3= 2_t n) { TCGv temp =3D tcg_const_i32(n); gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, temp); - tcg_temp_free(temp); } =20 static inline void @@ -1094,7 +966,6 @@ gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint= 32_t n) { TCGv temp =3D tcg_const_i32(n); gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, temp); - tcg_temp_free(temp); } =20 static inline void @@ -1145,13 +1016,6 @@ gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv ar= g3, uint32_t n, tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* write back result */ tcg_gen_mov_tl(ret, temp3); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); } =20 static inline void @@ -1169,9 +1033,6 @@ gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv a= rg3, uint32_t n) tcg_gen_sub_tl(temp, temp, temp2); } gen_add_d(ret, arg1, temp); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -1189,9 +1050,6 @@ gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv = arg3, uint32_t n) tcg_gen_sub_tl(temp, temp, temp2); } gen_adds(ret, arg1, temp); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -1219,12 +1077,6 @@ gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv= arg1_high, TCGv arg2, gen_add64_d(t3, t1, t2); /* write back result */ tcg_gen_extr_i64_i32(rl, rh, t3); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -1251,11 +1103,6 @@ gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCG= v arg1_high, TCGv arg2, =20 gen_helper_add64_ssov(t1, cpu_env, t1, t2); tcg_gen_extr_i64_i32(rl, rh, t1); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); } =20 static inline void @@ -1294,9 +1141,6 @@ gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv ar= g1_high, TCGv arg2, tcg_gen_shli_tl(temp, temp, 31); /* negate v bit, if special condition */ tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } /* write back result */ tcg_gen_extr_i64_i32(rl, rh, t4); @@ -1307,11 +1151,6 @@ gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv a= rg1_high, TCGv arg2, tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); /* calc SAV */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); - tcg_temp_free_i64(t4); } =20 static inline void @@ -1330,10 +1169,6 @@ gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv a= rg3, uint32_t n, tcg_gen_sari_i64(t2, t2, up_shift - n); =20 gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); } =20 static inline void @@ -1346,10 +1181,8 @@ gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv = arg1_high, TCGv arg2, tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp); tcg_gen_extr_i64_i32(rl, rh, r1); - - tcg_temp_free_i64(r1); - tcg_temp_free(temp); } + /* ret =3D r2 - (r1 * r3); */ static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) { @@ -1381,17 +1214,12 @@ static inline void gen_msub32_d(TCGv ret, TCGv r1, = TCGv r2, TCGv r3) tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); /* calc SAV */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); } =20 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_msub32_d(ret, r1, r2, temp); - tcg_temp_free(temp); } =20 static inline void @@ -1420,11 +1248,6 @@ gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, T= CGv r2_low, TCGv r2_high, /* write back the result */ tcg_gen_mov_tl(ret_low, t3); tcg_gen_mov_tl(ret_high, t4); - - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(t3); - tcg_temp_free(t4); } =20 static inline void @@ -1433,7 +1256,6 @@ gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, T= CGv r2_low, TCGv r2_high, { TCGv temp =3D tcg_const_i32(con); gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); - tcg_temp_free(temp); } =20 static inline void @@ -1462,10 +1284,6 @@ gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, = TCGv r2_low, TCGv r2_high, tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); /* calc SAV */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); } =20 static inline void @@ -1474,15 +1292,14 @@ gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1= , TCGv r2_low, TCGv r2_high, { TCGv temp =3D tcg_const_i32(con); gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); - tcg_temp_free(temp); } =20 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2) { TCGv temp =3D tcg_const_i32(r2); gen_add_d(ret, r1, temp); - tcg_temp_free(temp); } + /* calculate the carry bit too */ static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2) { @@ -1505,16 +1322,12 @@ static inline void gen_add_CC(TCGv ret, TCGv r1, TC= Gv r2) tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* write back result */ tcg_gen_mov_tl(ret, result); - - tcg_temp_free(result); - tcg_temp_free(t0); } =20 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_add_CC(ret, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2) @@ -1541,17 +1354,12 @@ static inline void gen_addc_CC(TCGv ret, TCGv r1, T= CGv r2) tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* write back result */ tcg_gen_mov_tl(ret, result); - - tcg_temp_free(result); - tcg_temp_free(t0); - tcg_temp_free(carry); } =20 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_addc_CC(ret, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, @@ -1585,12 +1393,6 @@ static inline void gen_cond_add(TCGCond cond, TCGv r= 1, TCGv r2, TCGv r3, tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); /* write back result */ tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); - - tcg_temp_free(t0); - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(result); - tcg_temp_free(mask); } =20 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2, @@ -1598,7 +1400,6 @@ static inline void gen_condi_add(TCGCond cond, TCGv r= 1, int32_t r2, { TCGv temp =3D tcg_const_i32(r2); gen_cond_add(cond, r1, temp, r3, r4); - tcg_temp_free(temp); } =20 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2) @@ -1620,9 +1421,6 @@ static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv = r2) tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* write back result */ tcg_gen_mov_tl(ret, result); - - tcg_temp_free(temp); - tcg_temp_free(result); } =20 static inline void @@ -1649,11 +1447,6 @@ gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* write back result */ tcg_gen_mov_i64(ret, result); - - tcg_temp_free(temp); - tcg_temp_free_i64(result); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2) @@ -1677,9 +1470,6 @@ static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv= r2) tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* write back result */ tcg_gen_mov_tl(ret, result); - - tcg_temp_free(result); - tcg_temp_free(temp); } =20 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2) @@ -1687,7 +1477,6 @@ static inline void gen_subc_CC(TCGv ret, TCGv r1, TCG= v r2) TCGv temp =3D tcg_temp_new(); tcg_gen_not_tl(temp, r2); gen_addc_CC(ret, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, @@ -1721,12 +1510,6 @@ static inline void gen_cond_sub(TCGCond cond, TCGv r= 1, TCGv r2, TCGv r3, tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); /* write back result */ tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); - - tcg_temp_free(t0); - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(result); - tcg_temp_free(mask); } =20 static inline void @@ -1753,9 +1536,6 @@ gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, = TCGv r1_high, TCGv r2, tcg_gen_extr_i64_i32(temp, temp2, temp64); gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, tcg_gen_sub_tl, tcg_gen_sub_tl); - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -1790,11 +1570,6 @@ gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low= , TCGv r1_high, TCGv r2, tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); /* combine av bits */ tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -1823,11 +1598,6 @@ gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low= , TCGv r1_high, TCGv r2, gen_sub64_d(temp64_3, temp64_2, temp64); /* write back result */ tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); - tcg_temp_free_i64(temp64_2); - tcg_temp_free_i64(temp64_3); } =20 static inline void @@ -1854,10 +1624,6 @@ gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_lo= w, TCGv r1_high, TCGv r2, tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); - tcg_temp_free_i64(temp64_2); } =20 static inline void @@ -1881,9 +1647,6 @@ gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TC= Gv r2, TCGv r3, uint32_t n, break; } gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -1895,9 +1658,6 @@ gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, ui= nt32_t n, uint32_t mode) tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_shli_tl(temp, r1, 16); gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -1921,9 +1681,6 @@ gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, T= CGv r2, TCGv r3, break; } gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -1935,9 +1692,6 @@ gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, u= int32_t n, uint32_t mode) tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_shli_tl(temp, r1, 16); gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -1945,7 +1699,6 @@ gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint= 32_t n) { TCGv temp =3D tcg_const_i32(n); gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp); - tcg_temp_free(temp); } =20 static inline void @@ -1953,15 +1706,12 @@ gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, u= int32_t n) { TCGv temp =3D tcg_const_i32(n); gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp); - tcg_temp_free(temp); } =20 static inline void gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, uint32_t up_shift) { - TCGv temp =3D tcg_temp_new(); - TCGv temp2 =3D tcg_temp_new(); TCGv temp3 =3D tcg_temp_new(); TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); @@ -1997,14 +1747,6 @@ gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv ar= g3, uint32_t n, tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* write back result */ tcg_gen_mov_tl(ret, temp3); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); - tcg_temp_free_i64(t4); } =20 static inline void @@ -2022,9 +1764,6 @@ gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv a= rg3, uint32_t n) tcg_gen_sub_tl(temp, temp, temp2); } gen_sub_d(ret, arg1, temp); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -2042,9 +1781,6 @@ gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv = arg3, uint32_t n) tcg_gen_sub_tl(temp, temp, temp2); } gen_subs(ret, arg1, temp); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -2072,12 +1808,6 @@ gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv= arg1_high, TCGv arg2, gen_sub64_d(t3, t1, t2); /* write back result */ tcg_gen_extr_i64_i32(rl, rh, t3); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -2104,11 +1834,6 @@ gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCG= v arg1_high, TCGv arg2, =20 gen_helper_sub64_ssov(t1, cpu_env, t1, t2); tcg_gen_extr_i64_i32(rl, rh, t1); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); } =20 static inline void @@ -2147,9 +1872,6 @@ gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv ar= g1_high, TCGv arg2, tcg_gen_shli_tl(temp, temp, 31); /* negate v bit, if special condition */ tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } /* write back result */ tcg_gen_extr_i64_i32(rl, rh, t4); @@ -2160,11 +1882,6 @@ gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv a= rg1_high, TCGv arg2, tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); /* calc SAV */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); - tcg_temp_free_i64(t4); } =20 static inline void @@ -2188,11 +1905,6 @@ gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv a= rg3, uint32_t n, tcg_gen_add_i64(t3, t3, t4); =20 gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); - tcg_temp_free_i64(t4); } =20 static inline void @@ -2205,9 +1917,6 @@ gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv a= rg1_high, TCGv arg2, tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp); tcg_gen_extr_i64_i32(rl, rh, r1); - - tcg_temp_free_i64(r1); - tcg_temp_free(temp); } =20 static inline void @@ -2234,9 +1943,6 @@ gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low= , TCGv r1_high, TCGv r2, tcg_gen_extr_i64_i32(temp, temp2, temp64); gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, tcg_gen_add_tl, tcg_gen_sub_tl); - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -2270,11 +1976,6 @@ gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_l= ow, TCGv r1_high, TCGv r2, gen_sub64_d(temp64_2, temp64_3, temp64); /* write back result */ tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); - tcg_temp_free_i64(temp64_2); - tcg_temp_free_i64(temp64_3); } =20 static inline void @@ -2300,10 +2001,6 @@ gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3,= uint32_t n, uint32_t mode) tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_shli_tl(temp, r1, 16); gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -2338,11 +2035,6 @@ gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_l= ow, TCGv r1_high, TCGv r2, tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); /* combine av bits */ tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -2375,10 +2067,6 @@ gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_= low, TCGv r1_high, TCGv r2, =20 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); - tcg_temp_free_i64(temp64_2); } =20 static inline void @@ -2404,10 +2092,6 @@ gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3= , uint32_t n, uint32_t mode) tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_shli_tl(temp, r1, 16); gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free_i64(temp64); } =20 static inline void gen_abs(TCGv ret, TCGv r1) @@ -2449,23 +2133,18 @@ static inline void gen_absdif(TCGv ret, TCGv r1, TC= Gv r2) tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* write back result */ tcg_gen_mov_tl(ret, result); - - tcg_temp_free(temp); - tcg_temp_free(result); } =20 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_absdif(ret, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_helper_absdif_ssov(ret, cpu_env, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2) @@ -2486,16 +2165,12 @@ static inline void gen_mul_i32s(TCGv ret, TCGv r1, = TCGv r2) tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); /* calc SAV bit */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free(high); - tcg_temp_free(low); } =20 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_mul_i32s(ret, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv= r2) @@ -2517,7 +2192,6 @@ static inline void gen_muli_i64s(TCGv ret_low, TCGv r= et_high, TCGv r1, { TCGv temp =3D tcg_const_i32(con); gen_mul_i64s(ret_low, ret_high, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv= r2) @@ -2539,41 +2213,35 @@ static inline void gen_muli_i64u(TCGv ret_low, TCGv= ret_high, TCGv r1, { TCGv temp =3D tcg_const_i32(con); gen_mul_i64u(ret_low, ret_high, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_helper_mul_ssov(ret, cpu_env, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_helper_mul_suov(ret, cpu_env, r1, temp); - tcg_temp_free(temp); } /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */ static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp); - tcg_temp_free(temp); } =20 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp); - tcg_temp_free(temp); } =20 static void gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_= shift) { - TCGv temp =3D tcg_temp_new(); TCGv_i64 temp_64 =3D tcg_temp_new_i64(); TCGv_i64 temp2_64 =3D tcg_temp_new_i64(); =20 @@ -2626,9 +2294,6 @@ gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uin= t32_t n, uint32_t up_shift) } /* calc sav overflow bit */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - tcg_temp_free(temp); - tcg_temp_free_i64(temp_64); - tcg_temp_free_i64(temp2_64); } =20 static void @@ -2651,8 +2316,6 @@ gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t= n) tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); /* calc sav overflow bit */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free(temp); } =20 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) @@ -2679,8 +2342,6 @@ static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2= , uint32_t n) tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* cut halfword off */ tcg_gen_andi_tl(ret, ret, 0xffff0000); - - tcg_temp_free(temp); } =20 static inline void @@ -2691,7 +2352,6 @@ gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TC= Gv r2_low, TCGv r2_high, tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -2700,7 +2360,6 @@ gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, T= CGv r2_low, TCGv r2_high, { TCGv temp =3D tcg_const_i32(con); gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp); - tcg_temp_free(temp); } =20 static inline void @@ -2711,7 +2370,6 @@ gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, T= CGv r2_low, TCGv r2_high, tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -2720,21 +2378,18 @@ gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1= , TCGv r2_low, TCGv r2_high, { TCGv temp =3D tcg_const_i32(con); gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); - tcg_temp_free(temp); } =20 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp); - tcg_temp_free(temp); } =20 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp); - tcg_temp_free(temp); } =20 static inline void @@ -2745,7 +2400,6 @@ gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TC= Gv r2_low, TCGv r2_high, tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -2754,7 +2408,6 @@ gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, T= CGv r2_low, TCGv r2_high, { TCGv temp =3D tcg_const_i32(con); gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp); - tcg_temp_free(temp); } =20 static inline void @@ -2765,7 +2418,6 @@ gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, T= CGv r2_low, TCGv r2_high, tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -2774,7 +2426,6 @@ gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, = TCGv r2_low, TCGv r2_high, { TCGv temp =3D tcg_const_i32(con); gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); - tcg_temp_free(temp); } =20 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low) @@ -2787,9 +2438,6 @@ static void gen_saturate(TCGv ret, TCGv arg, int32_t = up, int32_t low) =20 /* ret =3D (sat_neg > up ) ? up : sat_neg; */ tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg); - - tcg_temp_free(sat_neg); - tcg_temp_free(temp); } =20 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up) @@ -2797,7 +2445,6 @@ static void gen_saturate_u(TCGv ret, TCGv arg, int32_= t up) TCGv temp =3D tcg_const_i32(up); /* sat_neg =3D (arg > up ) ? up : arg; */ tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg); - tcg_temp_free(temp); } =20 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count) @@ -2826,9 +2473,6 @@ static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shif= tcount) gen_shi(temp_low, temp_low, shiftcount); gen_shi(ret, temp_high, shiftcount); tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16); - - tcg_temp_free(temp_low); - tcg_temp_free(temp_high); } } =20 @@ -2837,7 +2481,6 @@ static void gen_shaci(TCGv ret, TCGv r1, int32_t shif= t_count) uint32_t msk, msk_start; TCGv temp =3D tcg_temp_new(); TCGv temp2 =3D tcg_temp_new(); - TCGv t_0 =3D tcg_const_i32(0); =20 if (shift_count =3D=3D 0) { /* Clear PSW.C and PSW.V */ @@ -2868,9 +2511,6 @@ static void gen_shaci(TCGv ret, TCGv r1, int32_t shif= t_count) tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV); /* do shift */ tcg_gen_shli_tl(ret, r1, shift_count); - - tcg_temp_free(t_max); - tcg_temp_free(t_min); } else { /* clear PSW.V */ tcg_gen_movi_tl(cpu_PSW_V, 0); @@ -2885,10 +2525,6 @@ static void gen_shaci(TCGv ret, TCGv r1, int32_t shi= ft_count) tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); /* calc sav overflow bit */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(t_0); } =20 static void gen_shas(TCGv ret, TCGv r1, TCGv r2) @@ -2900,7 +2536,6 @@ static void gen_shasi(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_shas(ret, r1, temp); - tcg_temp_free(temp); } =20 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count) @@ -2917,9 +2552,6 @@ static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shi= ft_count) tcg_gen_shli_tl(low, r1, shift_count); tcg_gen_shli_tl(ret, high, shift_count); tcg_gen_deposit_tl(ret, ret, low, 0, 16); - - tcg_temp_free(low); - tcg_temp_free(high); } else { low =3D tcg_temp_new(); high =3D tcg_temp_new(); @@ -2928,11 +2560,7 @@ static void gen_sha_hi(TCGv ret, TCGv r1, int32_t sh= ift_count) tcg_gen_sari_tl(low, low, -shift_count); tcg_gen_sari_tl(ret, r1, -shift_count); tcg_gen_deposit_tl(ret, ret, low, 0, 16); - - tcg_temp_free(low); - tcg_temp_free(high); } - } =20 /* ret =3D {ret[30:0], (r1 cond r2)}; */ @@ -2944,16 +2572,12 @@ static void gen_sh_cond(int cond, TCGv ret, TCGv r1= , TCGv r2) tcg_gen_shli_tl(temp, ret, 1); tcg_gen_setcond_tl(cond, temp2, r1, r2); tcg_gen_or_tl(ret, temp, temp2); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_sh_cond(cond, ret, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2) @@ -2965,14 +2589,12 @@ static inline void gen_addsi(TCGv ret, TCGv r1, int= 32_t con) { TCGv temp =3D tcg_const_i32(con); gen_helper_add_ssov(ret, cpu_env, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_helper_add_suov(ret, cpu_env, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2) @@ -3002,9 +2624,6 @@ static inline void gen_bit_2op(TCGv ret, TCGv r1, TCG= v r2, (*op2)(temp1 , ret, temp1); =20 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1); - - tcg_temp_free(temp1); - tcg_temp_free(temp2); } =20 /* ret =3D r1[pos1] op1 r2[pos2]; */ @@ -3023,9 +2642,6 @@ static inline void gen_bit_1op(TCGv ret, TCGv r1, TCG= v r2, (*op1)(ret, temp1, temp2); =20 tcg_gen_andi_tl(ret, ret, 0x1); - - tcg_temp_free(temp1); - tcg_temp_free(temp2); } =20 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv= r2, @@ -3041,9 +2657,6 @@ static inline void gen_accumulating_cond(int cond, TC= Gv ret, TCGv r1, TCGv r2, (*op)(temp, temp, temp2); /* ret =3D {ret[31:1], temp} */ tcg_gen_deposit_tl(ret, ret, temp, 0, 1); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -3052,7 +2665,6 @@ gen_accumulating_condi(int cond, TCGv ret, TCGv r1, i= nt32_t con, { TCGv temp =3D tcg_const_i32(con); gen_accumulating_cond(cond, ret, r1, temp, op); - tcg_temp_free(temp); } =20 /* ret =3D (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/ @@ -3089,11 +2701,6 @@ static inline void gen_eqany_bi(TCGv ret, TCGv r1, i= nt32_t con) tcg_gen_or_tl(ret, b0, b1); tcg_gen_or_tl(ret, ret, b2); tcg_gen_or_tl(ret, ret, b3); - - tcg_temp_free(b0); - tcg_temp_free(b1); - tcg_temp_free(b2); - tcg_temp_free(b3); } =20 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con) @@ -3111,10 +2718,8 @@ static inline void gen_eqany_hi(TCGv ret, TCGv r1, i= nt32_t con) =20 /* combine them */ tcg_gen_or_tl(ret, h0, h1); - - tcg_temp_free(h0); - tcg_temp_free(h1); } + /* mask =3D ((1 << width) -1) << pos; ret =3D (r1 & ~mask) | (r2 << pos) & mask); */ static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv= pos) @@ -3132,10 +2737,6 @@ static inline void gen_insert(TCGv ret, TCGv r1, TCG= v r2, TCGv width, TCGv pos) tcg_gen_and_tl(temp, temp, mask); tcg_gen_andc_tl(temp2, r1, mask); tcg_gen_or_tl(ret, temp, temp2); - - tcg_temp_free(mask); - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1) @@ -3144,8 +2745,6 @@ static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv = r1) =20 gen_helper_bsplit(temp, r1); tcg_gen_extr_i64_i32(rl, rh, temp); - - tcg_temp_free_i64(temp); } =20 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1) @@ -3154,8 +2753,6 @@ static inline void gen_unpack(TCGv rl, TCGv rh, TCGv = r1) =20 gen_helper_unpack(temp, r1); tcg_gen_extr_i64_i32(rl, rh, temp); - - tcg_temp_free_i64(temp); } =20 static inline void @@ -3169,8 +2766,6 @@ gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCG= v r1, TCGv r2) gen_helper_dvinit_b_131(ret, cpu_env, r1, r2); } tcg_gen_extr_i64_i32(rl, rh, ret); - - tcg_temp_free_i64(ret); } =20 static inline void @@ -3184,8 +2779,6 @@ gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCG= v r1, TCGv r2) gen_helper_dvinit_h_131(ret, cpu_env, r1, r2); } tcg_gen_extr_i64_i32(rl, rh, ret); - - tcg_temp_free_i64(ret); } =20 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high) @@ -3200,7 +2793,6 @@ static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg= _high) /* calc SAV bit */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); tcg_gen_movi_tl(cpu_PSW_V, 0); - tcg_temp_free(temp); } =20 static void gen_calc_usb_mulr_h(TCGv arg) @@ -3215,7 +2807,6 @@ static void gen_calc_usb_mulr_h(TCGv arg) tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* clear V bit */ tcg_gen_movi_tl(cpu_PSW_V, 0); - tcg_temp_free(temp); } =20 /* helpers for generating program flow micro-ops */ @@ -3245,9 +2836,6 @@ static void generate_trap(DisasContext *ctx, int clas= s, int tin) gen_save_pc(ctx->base.pc_next); gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp); ctx->base.is_jmp =3D DISAS_NORETURN; - - tcg_temp_free(classtemp); - tcg_temp_free(tintemp); } =20 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r= 1, @@ -3267,7 +2855,6 @@ static inline void gen_branch_condi(DisasContext *ctx= , TCGCond cond, TCGv r1, { TCGv temp =3D tcg_const_i32(r2); gen_branch_cond(ctx, cond, r1, temp, address); - tcg_temp_free(temp); } =20 static void gen_loop(DisasContext *ctx, int r1, int32_t offset) @@ -3289,8 +2876,6 @@ static void gen_fcall_save_ctx(DisasContext *ctx) tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL); tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); tcg_gen_mov_tl(cpu_gpr_a[10], temp); - - tcg_temp_free(temp); } =20 static void gen_fret(DisasContext *ctx) @@ -3303,8 +2888,6 @@ static void gen_fret(DisasContext *ctx) tcg_gen_mov_tl(cpu_PC, temp); tcg_gen_exit_tb(NULL, 0); ctx->base.is_jmp =3D DISAS_NORETURN; - - tcg_temp_free(temp); } =20 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, @@ -3350,13 +2933,11 @@ static void gen_compute_branch(DisasContext *ctx, u= int32_t opc, int r1, temp =3D tcg_temp_new(); tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); - tcg_temp_free(temp); break; case OPC1_16_SBRN_JNZ_T: temp =3D tcg_temp_new(); tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); - tcg_temp_free(temp); break; /* SBR-format jumps */ case OPC1_16_SBR_JEQ: @@ -3474,7 +3055,6 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, int r1, tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); } - tcg_temp_free(temp); break; /* BRN format */ case OPCM_32_BRN_JTT: @@ -3488,7 +3068,6 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, int r1, } else { gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); } - tcg_temp_free(temp); break; /* BRR Format */ case OPCM_32_BRR_EQ_NEQ: @@ -3553,8 +3132,6 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, int r1, tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); } - tcg_temp_free(temp); - tcg_temp_free(temp2); break; case OPCM_32_BRR_JNZ: if (MASK_OP_BRR_OP2(ctx->opcode) =3D=3D OPC2_32_BRR_JNZ_A) { @@ -3609,16 +3186,12 @@ static void decode_src_opc(DisasContext *ctx, int o= p1) temp2 =3D tcg_const_tl(const4); tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, temp2, cpu_gpr_d[r1]); - tcg_temp_free(temp); - tcg_temp_free(temp2); break; case OPC1_16_SRC_CMOVN: temp =3D tcg_const_tl(0); temp2 =3D tcg_const_tl(const4); tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, temp2, cpu_gpr_d[r1]); - tcg_temp_free(temp); - tcg_temp_free(temp2); break; case OPC1_16_SRC_EQ: tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], @@ -3685,13 +3258,11 @@ static void decode_srr_opc(DisasContext *ctx, int o= p1) temp =3D tcg_const_tl(0); tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, cpu_gpr_d[r2], cpu_gpr_d[r1]); - tcg_temp_free(temp); break; case OPC1_16_SRR_CMOVN: temp =3D tcg_const_tl(0); tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, cpu_gpr_d[r2], cpu_gpr_d[r1]); - tcg_temp_free(temp); break; case OPC1_16_SRR_EQ: tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], @@ -3952,7 +3523,6 @@ static void decode_sr_accu(DisasContext *ctx) tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV); /* calc sav */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - tcg_temp_free(temp); break; case OPC2_16_SR_SAT_B: gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80); @@ -4047,7 +3617,6 @@ static void decode_16Bit_opc(DisasContext *ctx) temp =3D tcg_temp_new(); tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16); tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp); - tcg_temp_free(temp); break; /* SLRO-format */ case OPC1_16_SLRO_LD_A: @@ -4239,8 +3808,6 @@ static void decode_abs_ldw(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - - tcg_temp_free(temp); } =20 static void decode_abs_ldb(DisasContext *ctx) @@ -4272,8 +3839,6 @@ static void decode_abs_ldb(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - - tcg_temp_free(temp); } =20 static void decode_abs_ldst_swap(DisasContext *ctx) @@ -4299,8 +3864,6 @@ static void decode_abs_ldst_swap(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - - tcg_temp_free(temp); } =20 static void decode_abs_ldst_context(DisasContext *ctx) @@ -4360,7 +3923,6 @@ static void decode_abs_store(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); } =20 static void decode_abs_storeb_h(DisasContext *ctx) @@ -4386,7 +3948,6 @@ static void decode_abs_storeb_h(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); } =20 /* Bit-format */ @@ -4486,7 +4047,6 @@ static void decode_bit_insert(DisasContext *ctx) tcg_gen_not_tl(temp, temp); } tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1); - tcg_temp_free(temp); } =20 static void decode_bit_logical_t2(DisasContext *ctx) @@ -4604,7 +4164,6 @@ static void decode_bit_sh_logic1(DisasContext *ctx) } tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); - tcg_temp_free(temp); } =20 static void decode_bit_sh_logic2(DisasContext *ctx) @@ -4645,7 +4204,6 @@ static void decode_bit_sh_logic2(DisasContext *ctx) } tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); - tcg_temp_free(temp); } =20 /* BO-format */ @@ -4743,7 +4301,6 @@ static void decode_bo_addrmode_post_pre_base(DisasCon= text *ctx) tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); tcg_gen_mov_tl(cpu_gpr_a[r2], temp); - tcg_temp_free(temp); break; case OPC2_32_BO_ST_DA_SHORTOFF: CHECK_REG_PAIR(r1); @@ -4761,7 +4318,6 @@ static void decode_bo_addrmode_post_pre_base(DisasCon= text *ctx) tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); tcg_gen_mov_tl(cpu_gpr_a[r2], temp); - tcg_temp_free(temp); break; case OPC2_32_BO_ST_H_SHORTOFF: gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); @@ -4778,7 +4334,6 @@ static void decode_bo_addrmode_post_pre_base(DisasCon= text *ctx) temp =3D tcg_temp_new(); tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); - tcg_temp_free(temp); break; case OPC2_32_BO_ST_Q_POSTINC: temp =3D tcg_temp_new(); @@ -4786,13 +4341,11 @@ static void decode_bo_addrmode_post_pre_base(DisasC= ontext *ctx) tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); - tcg_temp_free(temp); break; case OPC2_32_BO_ST_Q_PREINC: temp =3D tcg_temp_new(); tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); - tcg_temp_free(temp); break; case OPC2_32_BO_ST_W_SHORTOFF: gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); @@ -4915,9 +4468,6 @@ static void decode_bo_addrmode_bitreverse_circular(Di= sasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); } =20 static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx) @@ -4982,7 +4532,6 @@ static void decode_bo_addrmode_ld_post_pre_base(Disas= Context *ctx) tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); tcg_gen_mov_tl(cpu_gpr_a[r2], temp); - tcg_temp_free(temp); break; case OPC2_32_BO_LD_DA_SHORTOFF: CHECK_REG_PAIR(r1); @@ -5000,7 +4549,6 @@ static void decode_bo_addrmode_ld_post_pre_base(Disas= Context *ctx) tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); tcg_gen_mov_tl(cpu_gpr_a[r2], temp); - tcg_temp_free(temp); break; case OPC2_32_BO_LD_H_SHORTOFF: gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); @@ -5167,9 +4715,6 @@ static void decode_bo_addrmode_ld_bitreverse_circular= (DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); } =20 static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx) @@ -5178,7 +4723,7 @@ static void decode_bo_addrmode_stctx_post_pre_base(Di= sasContext *ctx) uint32_t off10; int r1, r2; =20 - TCGv temp, temp2; + TCGv temp; =20 r1 =3D MASK_OP_BO_S1D(ctx->opcode); r2 =3D MASK_OP_BO_S2(ctx->opcode); @@ -5187,7 +4732,6 @@ static void decode_bo_addrmode_stctx_post_pre_base(Di= sasContext *ctx) =20 =20 temp =3D tcg_temp_new(); - temp2 =3D tcg_temp_new(); =20 switch (op2) { case OPC2_32_BO_LDLCX_SHORTOFF: @@ -5260,8 +4804,6 @@ static void decode_bo_addrmode_stctx_post_pre_base(Di= sasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx) @@ -5320,10 +4862,6 @@ static void decode_bo_addrmode_ldmst_bitreverse_circ= ular(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); } =20 static void decode_bol_opc(DisasContext *ctx, int32_t op1) @@ -5341,13 +4879,11 @@ static void decode_bol_opc(DisasContext *ctx, int32= _t op1) temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL); - tcg_temp_free(temp); break; case OPC1_32_BOL_LD_W_LONGOFF: temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL); - tcg_temp_free(temp); break; case OPC1_32_BOL_LEA_LONGOFF: tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address); @@ -5474,7 +5010,6 @@ static void decode_rc_logical_shift(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); } =20 static void decode_rc_accumulator(DisasContext *ctx) @@ -5674,7 +5209,6 @@ static void decode_rc_accumulator(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); } =20 static void decode_rc_serviceroutine(DisasContext *ctx) @@ -5764,7 +5298,6 @@ static void decode_rcpw_insert(DisasContext *ctx) if (pos + width <=3D 32) { temp =3D tcg_const_i32(const4); tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, wi= dth); - tcg_temp_free(temp); } break; default: @@ -5807,14 +5340,10 @@ static void decode_rcrw_insert(DisasContext *ctx) tcg_gen_movi_tl(temp2, const4); tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3); - - tcg_temp_free(temp3); break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 /* RCR format */ @@ -5847,16 +5376,12 @@ static void decode_rcr_cond_select(DisasContext *ct= x) temp2 =3D tcg_const_i32(const9); tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp2); - tcg_temp_free(temp); - tcg_temp_free(temp2); break; case OPC2_32_RCR_SELN: temp =3D tcg_const_i32(0); temp2 =3D tcg_const_i32(const9); tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp2); - tcg_temp_free(temp); - tcg_temp_free(temp2); break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); @@ -6236,8 +5761,6 @@ static void decode_rr_accumulator(DisasContext *ctx) tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); - - tcg_temp_free(temp); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } @@ -6377,13 +5900,10 @@ static void decode_rr_logical_shift(DisasContext *c= tx) { uint32_t op2; int r3, r2, r1; - TCGv temp; =20 r3 =3D MASK_OP_RR_D(ctx->opcode); r2 =3D MASK_OP_RR_S2(ctx->opcode); r1 =3D MASK_OP_RR_S1(ctx->opcode); - - temp =3D tcg_temp_new(); op2 =3D MASK_OP_RR_OP2(ctx->opcode); =20 switch (op2) { @@ -6448,7 +5968,6 @@ static void decode_rr_logical_shift(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); } =20 static void decode_rr_address(DisasContext *ctx) @@ -6471,14 +5990,12 @@ static void decode_rr_address(DisasContext *ctx) temp =3D tcg_temp_new(); tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n); tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp); - tcg_temp_free(temp); break; case OPC2_32_RR_ADDSC_AT: temp =3D tcg_temp_new(); tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3); tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp); tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC); - tcg_temp_free(temp); break; case OPC2_32_RR_EQ_A: tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], @@ -6598,10 +6115,6 @@ static void decode_rr_divide(DisasContext *ctx) /* write result */ tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24); tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); break; case OPC2_32_RR_DVINIT_H: CHECK_REG_PAIR(r3); @@ -6631,9 +6144,6 @@ static void decode_rr_divide(DisasContext *ctx) /* write result */ tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16); tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); break; case OPC2_32_RR_DVINIT: temp =3D tcg_temp_new(); @@ -6655,8 +6165,6 @@ static void decode_rr_divide(DisasContext *ctx) tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); /* sign extend to high reg */ tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31); - tcg_temp_free(temp); - tcg_temp_free(temp2); break; case OPC2_32_RR_DVINIT_U: /* overflow =3D (D[b] =3D=3D 0) */ @@ -6758,7 +6266,6 @@ static void decode_rr1_mul(DisasContext *ctx) GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); - tcg_temp_free_i64(temp64); break; case OPC2_32_RR1_MUL_H_32_LU: temp64 =3D tcg_temp_new_i64(); @@ -6766,7 +6273,6 @@ static void decode_rr1_mul(DisasContext *ctx) GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); - tcg_temp_free_i64(temp64); break; case OPC2_32_RR1_MUL_H_32_UL: temp64 =3D tcg_temp_new_i64(); @@ -6774,7 +6280,6 @@ static void decode_rr1_mul(DisasContext *ctx) GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); - tcg_temp_free_i64(temp64); break; case OPC2_32_RR1_MUL_H_32_UU: temp64 =3D tcg_temp_new_i64(); @@ -6782,7 +6287,6 @@ static void decode_rr1_mul(DisasContext *ctx) GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); - tcg_temp_free_i64(temp64); break; case OPC2_32_RR1_MULM_H_64_LL: temp64 =3D tcg_temp_new_i64(); @@ -6793,7 +6297,6 @@ static void decode_rr1_mul(DisasContext *ctx) tcg_gen_movi_tl(cpu_PSW_V, 0); /* reset AV bit */ tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); - tcg_temp_free_i64(temp64); break; case OPC2_32_RR1_MULM_H_64_LU: temp64 =3D tcg_temp_new_i64(); @@ -6804,7 +6307,6 @@ static void decode_rr1_mul(DisasContext *ctx) tcg_gen_movi_tl(cpu_PSW_V, 0); /* reset AV bit */ tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); - tcg_temp_free_i64(temp64); break; case OPC2_32_RR1_MULM_H_64_UL: temp64 =3D tcg_temp_new_i64(); @@ -6815,7 +6317,6 @@ static void decode_rr1_mul(DisasContext *ctx) tcg_gen_movi_tl(cpu_PSW_V, 0); /* reset AV bit */ tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); - tcg_temp_free_i64(temp64); break; case OPC2_32_RR1_MULM_H_64_UU: temp64 =3D tcg_temp_new_i64(); @@ -6826,8 +6327,6 @@ static void decode_rr1_mul(DisasContext *ctx) tcg_gen_movi_tl(cpu_PSW_V, 0); /* reset AV bit */ tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); - tcg_temp_free_i64(temp64); - break; case OPC2_32_RR1_MULR_H_16_LL: GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],= n); @@ -6848,7 +6347,6 @@ static void decode_rr1_mul(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(n); } =20 static void decode_rr1_mulq(DisasContext *ctx) @@ -6918,8 +6416,6 @@ static void decode_rr1_mulq(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 /* RR2 format */ @@ -7009,7 +6505,6 @@ static void decode_rrpw_extract_insert(DisasContext *= ctx) tcg_gen_movi_tl(temp, ((1u << width) - 1) << pos); tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos); tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); - tcg_temp_free(temp); } =20 break; @@ -7058,13 +6553,11 @@ static void decode_rrr_cond_select(DisasContext *ct= x) temp =3D tcg_const_i32(0); tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2]); - tcg_temp_free(temp); break; case OPC2_32_RRR_SELN: temp =3D tcg_const_i32(0); tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2]); - tcg_temp_free(temp); break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); @@ -7577,8 +7070,6 @@ static void decode_rrr1_maddq_h(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static void decode_rrr1_maddsu_h(DisasContext *ctx) @@ -8061,8 +7552,6 @@ static void decode_rrr1_msubq_h(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static void decode_rrr1_msubad_h(DisasContext *ctx) @@ -8257,7 +7746,6 @@ static void decode_rrrr_extract_insert(DisasContext *= ctx) */ tcg_gen_movcond_tl(TCG_COND_EQ, msw, tmp_pos, zero, zero, msw); tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, msw); - tcg_temp_free(msw); } break; case OPC2_32_RRRR_EXTR: @@ -8285,8 +7773,6 @@ static void decode_rrrr_extract_insert(DisasContext *= ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(tmp_pos); - tcg_temp_free(tmp_width); } =20 /* RRRW format */ @@ -8332,8 +7818,6 @@ static void decode_rrrw_extract_insert(DisasContext *= ctx) tcg_gen_shl_tl(temp2, temp2, temp); tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp); tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2); - - tcg_temp_free(temp2); break; case OPC2_32_RRRW_INSERT: temp2 =3D tcg_temp_new(); @@ -8341,13 +7825,10 @@ static void decode_rrrw_extract_insert(DisasContext= *ctx) tcg_gen_movi_tl(temp, width); tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f); gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp= 2); - - tcg_temp_free(temp2); break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); } =20 /* SYS Format*/ @@ -8400,7 +7881,6 @@ static void decode_sys_interrupts(DisasContext *ctx) gen_set_label(l1); tcg_gen_exit_tb(NULL, 0); ctx->base.is_jmp =3D DISAS_NORETURN; - tcg_temp_free(tmp); } else { /* generate privilege trap */ } @@ -8482,9 +7962,6 @@ static void decode_32Bit_opc(DisasContext *ctx) =20 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16); tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW); - - tcg_temp_free(temp2); - tcg_temp_free(temp); break; case OPC1_32_ABS_LD_Q: address =3D MASK_OP_ABS_OFF18(ctx->opcode); @@ -8493,8 +7970,6 @@ static void decode_32Bit_opc(DisasContext *ctx) =20 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); - - tcg_temp_free(temp); break; case OPC1_32_ABS_LEA: address =3D MASK_OP_ABS_OFF18(ctx->opcode); @@ -8514,9 +7989,6 @@ static void decode_32Bit_opc(DisasContext *ctx) tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos)); tcg_gen_ori_tl(temp2, temp2, (b << bpos)); tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB); - - tcg_temp_free(temp); - tcg_temp_free(temp2); break; /* B-format */ case OPC1_32_B_CALL: @@ -8647,10 +8119,6 @@ static void decode_32Bit_opc(DisasContext *ctx) tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); =20 gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3); - - tcg_temp_free(temp); - tcg_temp_free(temp2); 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.31.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:31:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=agy/u0GMKA+XJZ7eZrr4m/SwvDijeZedhgSDznlTFuI=; b=fuzeETEEiQNzPI/I3KBVJ2gdT9a3y7Fyf1C1b8rQsWfmz46+tqtnXPdBMD9rBztO0s qW5KJLjvnr2Ym7HGWF51s1XPMnN0sybTDOC7v86zLOcZnZrVGvZ4952exU3Lz2vQL6bn BkcfMO5q/XS6qM5lxvLovvw8YYiX6GQARJ/i85DvFDsBjVX6K7ZPQdMWix015b+JZnZX 52sVGZpBAPvNnjPfMVan4GlQq1DSEWBOdVU61rrkUAxYesEp1MGu0vN5GYurR9AsiWZZ de5dD/u2/QGVHGlZRiHTh/+nUUbrSvM+z0STomXVGS9AMOufo7t+VCMCXUfV6J8CICnG 9X7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=agy/u0GMKA+XJZ7eZrr4m/SwvDijeZedhgSDznlTFuI=; b=AKV8HcBidu5CFNSuokN7p4vosaJvKV2l9EmeJ3WdxpeLruAS5tYz1dYIfai8uyuxfR YbBDIv9lOkLpN+GmcZ4jQJelSj/Em+cQbvxXaIwsTo59R1+gak2/oC6WJAPifh6DVDjU Fk4x5S/8mw5i4//rkx2tG2Hrtu9HhYuyx9NBZbtaHJkgWXQEwFCEy7IwelkyqrmXkeaL A+e/qyLdteW4BxkUP3f8UneIj3RQ3quMsI+nhJD/7VjsPQnwQ9TkYZ/eQK4PEkrBsNgb OE4Z9XxoicpbssuGiBdB/6AgyH84nHL3YPGw6V+cm2FEhbngJ3G2+aJXq8o6GuiYQ4l0 dY9g== X-Gm-Message-State: AO0yUKXPbofXncXHndbeJMd0ZFWKMhSBNF9yv0sXx8QcNi7LOVF5S9D5 jqHPFrc4UlMTIp9q0P4QyiWUe4zKHU+EYi/Vbjk= X-Google-Smtp-Source: AK7set9bYL8FG+IZiUFnUy/jQO+95TRQp33CwPaBWy9mx+7DkeYE0bT0UXX6oMVnBI8UQ2zoSQqXxQ== X-Received: by 2002:a17:90b:180c:b0:237:d867:222c with SMTP id lw12-20020a17090b180c00b00237d867222cmr5447629pjb.42.1677475890878; Sun, 26 Feb 2023 21:31:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 71/76] target/xtensa: Drop reset_sar_tracker Date: Sun, 26 Feb 2023 19:25:00 -1000 Message-Id: <20230227052505.352889-72-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476329626100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Remove sar_m32_allocated, as sar_m32 non-null is equivalent. Reviewed-by: Max Filippov Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/xtensa/translate.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 4af0650deb..910350dec6 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -57,7 +57,6 @@ struct DisasContext { =20 bool sar_5bit; bool sar_m32_5bit; - bool sar_m32_allocated; TCGv_i32 sar_m32; =20 unsigned window; @@ -284,14 +283,7 @@ static void init_sar_tracker(DisasContext *dc) { dc->sar_5bit =3D false; dc->sar_m32_5bit =3D false; - dc->sar_m32_allocated =3D false; -} - -static void reset_sar_tracker(DisasContext *dc) -{ - if (dc->sar_m32_allocated) { - tcg_temp_free(dc->sar_m32); - } + dc->sar_m32 =3D NULL; } =20 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa) @@ -306,9 +298,8 @@ static void gen_right_shift_sar(DisasContext *dc, TCGv_= i32 sa) =20 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa) { - if (!dc->sar_m32_allocated) { + if (!dc->sar_m32) { dc->sar_m32 =3D tcg_temp_new_i32(); - dc->sar_m32_allocated =3D true; } tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f); tcg_gen_sub_i32(cpu_SR[SAR], tcg_constant_i32(32), dc->sar_m32); @@ -1247,7 +1238,6 @@ static void xtensa_tr_tb_stop(DisasContextBase *dcbas= e, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 - reset_sar_tracker(dc); if (dc->icount) { tcg_temp_free(dc->next_icount); } --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677476058; cv=none; d=zohomail.com; s=zohoarc; b=lX/1x3C0CWaExarZApAiBGvI+KKUgNGf+1Id4M+Z+E3uZn1NPWDb7NJ7ez3GNO0UcWvMsPO0tUnIIdLITCfMLeS1dBDPwojtGX6f36pqmKv6oA9b7zUZo9uJ3gEXGB9eOSAZYh2qwCLwAYbgkWAFEToJ/yaCGL7sAWh9qCjeZY8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677476058; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=36+6c6XhddMEyIhn3+S9l0econtu2Qbbfj3zvO3qr6w=; b=T+3EI/ZmD5lLDo/G6CxTKwlEesUgxGcqBqE9Df2qQBqUhJ645eNiB2zqK0Mgxl+/zKe2rRSQOsegFGsFoEb4CvNLJVbe3lsKSr0fe4bFOtSsv4S+Fa6GowFCdTNrR88C8oJsKLeJwJxKqcKYx5Yo8oF3olV9Dca/PDJXxvEVg5g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677476058971719.7217453473947; Sun, 26 Feb 2023 21:34:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW8J-0004v1-1D; Mon, 27 Feb 2023 00:33:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW6u-0008Ue-85 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:31:41 -0500 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW6p-00015n-J3 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:31:39 -0500 Received: by mail-pj1-x1043.google.com with SMTP id m3-20020a17090ade0300b00229eec90a7fso10975743pjv.0 for ; Sun, 26 Feb 2023 21:31:34 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.31.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:31:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=36+6c6XhddMEyIhn3+S9l0econtu2Qbbfj3zvO3qr6w=; b=d7KDUAEmH2YMRMJY/9bGIXI+gQqAK5MF8dsbuecvsf46BWeAkj5bXreDJVuoDoKkm3 kEgaIQEFU0O0bUrnCUfBEgMr0ogOYr7Au9A17/ny3pfVK1vw2I2bcnXlwULPymOjlfnk vDEZDZvARIR2v1xxpnBznFPIuzbvC8hoF9Im+KbPSecgIhY+GqehxEUzcw5xhmhIcpCP hGKZ7xFb8JuufOZf6PoBgVS9ffxmYdz3IoTj9EAbbNpA+glVjDD4FpscDaPXPYX1PSrU /d6Yto+cCYZvSi+fXt61BbZXT55vT3rYaJBJJWdmn60Xt+FAOudgXx3s9dgVg8d6NnuV miWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=36+6c6XhddMEyIhn3+S9l0econtu2Qbbfj3zvO3qr6w=; b=1Q8kIbOCda5q3BabILf6T2n1ysKDHKDuYV/VRl/6eJndl53Jpa60/XJm12As2PPOT2 8Zyv1bRgSUfCi+5ifyAl4NK//OzHBpleY7KKHCISRtAmkoMS68pEHyWDypIAyBqvi8aL 45tc3ph0SVWgw6M+yeesYWr4XJQvzrMn/kbboohrxRwmqr9kWLnyHftl0B4K5HtYsix0 sn8P4B6zTpDmZn3L7VP5qfQiL4oBOGaXvdxj0l0LAxIaGe0pNmR4AvZMheBIim4KoB8b iDEhRirusaFACTCRx8fMZuPCycR3d3pmb4mjloowpOZToEo+FgRvfFWtz7odXAlypBbm k7jw== X-Gm-Message-State: AO0yUKW8x2EeYfHK8KDxW2ktvPG9aqvWnsf1I7lrv5OWQeanFl83o30K aR85gWcK9bNBi4zKyVxKDxc9O2M+C1ahDP5/CuODLA== X-Google-Smtp-Source: AK7set8+swk1gqzDC4KAxoM06/7wxDBwiZzG3fCPGPh0vYX6Fpia7rR+/SaL6rSD9tgoNkMGoLA52Q== X-Received: by 2002:a17:90b:3892:b0:237:aade:444 with SMTP id mu18-20020a17090b389200b00237aade0444mr9018394pjb.42.1677475893649; Sun, 26 Feb 2023 21:31:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 72/76] target/xtensa: Drop tcg_temp_free Date: Sun, 26 Feb 2023 19:25:01 -1000 Message-Id: <20230227052505.352889-73-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476060297100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Reviewed-by: Max Filippov Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- target/xtensa/translate.c | 107 -------------------------------------- 1 file changed, 107 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 910350dec6..3ea50d8bc3 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1102,16 +1102,6 @@ static void disas_xtensa_insn(CPUXtensaState *env, D= isasContext *dc) ops->translate(dc, pslot->arg, ops->par); } =20 - for (i =3D 0; i < n_arg_copy; ++i) { - if (arg_copy[i].arg->num_bits <=3D 32) { - tcg_temp_free_i32(arg_copy[i].temp); - } else if (arg_copy[i].arg->num_bits <=3D 64) { - tcg_temp_free_i64(arg_copy[i].temp); - } else { - g_assert_not_reached(); - } - } - if (dc->base.is_jmp =3D=3D DISAS_NEXT) { gen_postprocess(dc, 0); dc->op_flags =3D 0; @@ -1238,10 +1228,6 @@ static void xtensa_tr_tb_stop(DisasContextBase *dcba= se, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 - if (dc->icount) { - tcg_temp_free(dc->next_icount); - } - switch (dc->base.is_jmp) { case DISAS_NORETURN: break; @@ -1369,7 +1355,6 @@ static void translate_addx(DisasContext *dc, const Op= codeArg arg[], TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_shli_i32(tmp, arg[1].in, par[0]); tcg_gen_add_i32(arg[0].out, tmp, arg[2].in); - tcg_temp_free(tmp); } =20 static void translate_all(DisasContext *dc, const OpcodeArg arg[], @@ -1388,8 +1373,6 @@ static void translate_all(DisasContext *dc, const Opc= odeArg arg[], tcg_gen_shri_i32(tmp, tmp, arg[1].imm + shift); tcg_gen_deposit_i32(arg[0].out, arg[0].out, tmp, arg[0].imm, 1); - tcg_temp_free(mask); - tcg_temp_free(tmp); } =20 static void translate_and(DisasContext *dc, const OpcodeArg arg[], @@ -1404,7 +1387,6 @@ static void translate_ball(DisasContext *dc, const Op= codeArg arg[], TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_and_i32(tmp, arg[0].in, arg[1].in); gen_brcond(dc, par[0], tmp, arg[1].in, arg[2].imm); - tcg_temp_free(tmp); } =20 static void translate_bany(DisasContext *dc, const OpcodeArg arg[], @@ -1413,7 +1395,6 @@ static void translate_bany(DisasContext *dc, const Op= codeArg arg[], TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_and_i32(tmp, arg[0].in, arg[1].in); gen_brcondi(dc, par[0], tmp, 0, arg[2].imm); - tcg_temp_free(tmp); } =20 static void translate_b(DisasContext *dc, const OpcodeArg arg[], @@ -1439,8 +1420,6 @@ static void translate_bb(DisasContext *dc, const Opco= deArg arg[], #endif tcg_gen_and_i32(tmp, arg[0].in, bit); gen_brcondi(dc, par[0], tmp, 0, arg[2].imm); - tcg_temp_free(tmp); - tcg_temp_free(bit); } =20 static void translate_bbi(DisasContext *dc, const OpcodeArg arg[], @@ -1453,7 +1432,6 @@ static void translate_bbi(DisasContext *dc, const Opc= odeArg arg[], tcg_gen_andi_i32(tmp, arg[0].in, 0x00000001u << arg[1].imm); #endif gen_brcondi(dc, par[0], tmp, 0, arg[2].imm); - tcg_temp_free(tmp); } =20 static void translate_bi(DisasContext *dc, const OpcodeArg arg[], @@ -1494,8 +1472,6 @@ static void translate_boolean(DisasContext *dc, const= OpcodeArg arg[], tcg_gen_shri_i32(tmp2, arg[2].in, arg[2].imm); op[par[0]](tmp1, tmp1, tmp2); tcg_gen_deposit_i32(arg[0].out, arg[0].out, tmp1, arg[0].imm, 1); - tcg_temp_free(tmp1); - tcg_temp_free(tmp2); } =20 static void translate_bp(DisasContext *dc, const OpcodeArg arg[], @@ -1505,7 +1481,6 @@ static void translate_bp(DisasContext *dc, const Opco= deArg arg[], =20 tcg_gen_andi_i32(tmp, arg[0].in, 1 << arg[0].imm); gen_brcondi(dc, par[0], tmp, 0, arg[1].imm); - tcg_temp_free(tmp); } =20 static void translate_call0(DisasContext *dc, const OpcodeArg arg[], @@ -1520,7 +1495,6 @@ static void translate_callw(DisasContext *dc, const O= pcodeArg arg[], { TCGv_i32 tmp =3D tcg_const_i32(arg[0].imm); gen_callw_slot(dc, par[0], tmp, adjust_jump_slot(dc, arg[0].imm, 0)); - tcg_temp_free(tmp); } =20 static void translate_callx0(DisasContext *dc, const OpcodeArg arg[], @@ -1530,7 +1504,6 @@ static void translate_callx0(DisasContext *dc, const = OpcodeArg arg[], tcg_gen_mov_i32(tmp, arg[0].in); tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next); gen_jump(dc, tmp); - tcg_temp_free(tmp); } =20 static void translate_callxw(DisasContext *dc, const OpcodeArg arg[], @@ -1540,7 +1513,6 @@ static void translate_callxw(DisasContext *dc, const = OpcodeArg arg[], =20 tcg_gen_mov_i32(tmp, arg[0].in); gen_callw_slot(dc, par[0], tmp, -1); - tcg_temp_free(tmp); } =20 static void translate_clamps(DisasContext *dc, const OpcodeArg arg[], @@ -1551,8 +1523,6 @@ static void translate_clamps(DisasContext *dc, const = OpcodeArg arg[], =20 tcg_gen_smax_i32(tmp1, tmp1, arg[1].in); tcg_gen_smin_i32(arg[0].out, tmp1, tmp2); - tcg_temp_free(tmp1); - tcg_temp_free(tmp2); } =20 static void translate_clrb_expstate(DisasContext *dc, const OpcodeArg arg[= ], @@ -1574,7 +1544,6 @@ static void translate_const16(DisasContext *dc, const= OpcodeArg arg[], TCGv_i32 c =3D tcg_const_i32(arg[1].imm); =20 tcg_gen_deposit_i32(arg[0].out, c, arg[0].in, 16, 16); - tcg_temp_free(c); } =20 static void translate_dcache(DisasContext *dc, const OpcodeArg arg[], @@ -1585,8 +1554,6 @@ static void translate_dcache(DisasContext *dc, const = OpcodeArg arg[], =20 tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm); tcg_gen_qemu_ld8u(res, addr, dc->cring); - tcg_temp_free(addr); - tcg_temp_free(res); } =20 static void translate_depbits(DisasContext *dc, const OpcodeArg arg[], @@ -1637,7 +1604,6 @@ static void translate_extui(DisasContext *dc, const O= pcodeArg arg[], TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_shri_i32(tmp, arg[1].in, arg[2].imm); tcg_gen_andi_i32(arg[0].out, tmp, maskimm); - tcg_temp_free(tmp); } =20 static void translate_getex(DisasContext *dc, const OpcodeArg arg[], @@ -1648,7 +1614,6 @@ static void translate_getex(DisasContext *dc, const O= pcodeArg arg[], tcg_gen_extract_i32(tmp, cpu_SR[ATOMCTL], 8, 1); tcg_gen_deposit_i32(cpu_SR[ATOMCTL], cpu_SR[ATOMCTL], arg[0].in, 8, 1); tcg_gen_mov_i32(arg[0].out, tmp); - tcg_temp_free(tmp); } =20 static void translate_icache(DisasContext *dc, const OpcodeArg arg[], @@ -1660,7 +1625,6 @@ static void translate_icache(DisasContext *dc, const = OpcodeArg arg[], tcg_gen_movi_i32(cpu_pc, dc->pc); tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm); gen_helper_itlb_hit_test(cpu_env, addr); - tcg_temp_free(addr); #endif } =20 @@ -1695,7 +1659,6 @@ static void translate_l32e(DisasContext *dc, const Op= codeArg arg[], tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm); mop =3D gen_load_store_alignment(dc, MO_TEUL, addr); tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->ring, mop); - tcg_temp_free(addr); } =20 #ifdef CONFIG_USER_ONLY @@ -1726,7 +1689,6 @@ static void translate_l32ex(DisasContext *dc, const O= pcodeArg arg[], tcg_gen_qemu_ld_i32(arg[0].out, addr, dc->cring, mop); tcg_gen_mov_i32(cpu_exclusive_addr, addr); tcg_gen_mov_i32(cpu_exclusive_val, arg[0].out); - tcg_temp_free(addr); } =20 static void translate_ldst(DisasContext *dc, const OpcodeArg arg[], @@ -1749,7 +1711,6 @@ static void translate_ldst(DisasContext *dc, const Op= codeArg arg[], tcg_gen_mb(TCG_BAR_LDAQ | TCG_MO_ALL); } } - tcg_temp_free(addr); } =20 static void translate_lct(DisasContext *dc, const OpcodeArg arg[], @@ -1770,7 +1731,6 @@ static void translate_l32r(DisasContext *dc, const Op= codeArg arg[], tmp =3D tcg_const_i32(arg[1].imm); } tcg_gen_qemu_ld32u(arg[0].out, tmp, dc->cring); - tcg_temp_free(tmp); } =20 static void translate_loop(DisasContext *dc, const OpcodeArg arg[], @@ -1856,19 +1816,12 @@ static void translate_mac16(DisasContext *dc, const= OpcodeArg arg[], lo, hi); } tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); - - tcg_temp_free_i32(lo); - tcg_temp_free_i32(hi); } - tcg_temp_free(m1); - tcg_temp_free(m2); } if (ld_offset) { tcg_gen_mov_i32(arg[1].out, vaddr); tcg_gen_mov_i32(cpu_SR[MR + arg[0].imm], mem32); } - tcg_temp_free(vaddr); - tcg_temp_free(mem32); } =20 static void translate_memw(DisasContext *dc, const OpcodeArg arg[], @@ -1932,7 +1885,6 @@ static void translate_movp(DisasContext *dc, const Op= codeArg arg[], tcg_gen_movcond_i32(par[0], arg[0].out, tmp, zero, arg[1].in, arg[0].in); - tcg_temp_free(tmp); } =20 static void translate_movsp(DisasContext *dc, const OpcodeArg arg[], @@ -1955,8 +1907,6 @@ static void translate_mul16(DisasContext *dc, const O= pcodeArg arg[], tcg_gen_ext16u_i32(v2, arg[2].in); } tcg_gen_mul_i32(arg[0].out, v1, v2); - tcg_temp_free(v2); - tcg_temp_free(v1); } =20 static void translate_mull(DisasContext *dc, const OpcodeArg arg[], @@ -1975,7 +1925,6 @@ static void translate_mulh(DisasContext *dc, const Op= codeArg arg[], } else { tcg_gen_mulu2_i32(lo, arg[0].out, arg[1].in, arg[2].in); } - tcg_temp_free(lo); } =20 static void translate_neg(DisasContext *dc, const OpcodeArg arg[], @@ -2110,7 +2059,6 @@ static void translate_retw(DisasContext *dc, const Op= codeArg arg[], tcg_gen_deposit_i32(tmp, tmp, cpu_R[0], 0, 30); gen_helper_retw(cpu_env, cpu_R[0]); gen_jump(dc, tmp); - tcg_temp_free(tmp); } =20 static void translate_rfde(DisasContext *dc, const OpcodeArg arg[], @@ -2149,7 +2097,6 @@ static void translate_rfw(DisasContext *dc, const Opc= odeArg arg[], cpu_SR[WINDOW_START], tmp); } =20 - tcg_temp_free(tmp); gen_helper_restore_owb(cpu_env); gen_jump(dc, cpu_SR[EPC1]); } @@ -2199,7 +2146,6 @@ static void translate_rsr_ptevaddr(DisasContext *dc, = const OpcodeArg arg[], tcg_gen_shri_i32(tmp, cpu_SR[EXCVADDR], 10); tcg_gen_or_i32(tmp, tmp, cpu_SR[PTEVADDR]); tcg_gen_andi_i32(arg[0].out, tmp, 0xfffffffc); - tcg_temp_free(tmp); #endif } =20 @@ -2273,8 +2219,6 @@ static void translate_s32c1i(DisasContext *dc, const = OpcodeArg arg[], gen_check_atomctl(dc, addr); tcg_gen_atomic_cmpxchg_i32(arg[0].out, addr, cpu_SR[SCOMPARE1], tmp, dc->cring, mop); - tcg_temp_free(addr); - tcg_temp_free(tmp); } =20 static void translate_s32e(DisasContext *dc, const OpcodeArg arg[], @@ -2286,7 +2230,6 @@ static void translate_s32e(DisasContext *dc, const Op= codeArg arg[], tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm); mop =3D gen_load_store_alignment(dc, MO_TEUL, addr); tcg_gen_qemu_st_tl(arg[0].in, addr, dc->ring, mop); - tcg_temp_free(addr); } =20 static void translate_s32ex(DisasContext *dc, const OpcodeArg arg[], @@ -2312,9 +2255,6 @@ static void translate_s32ex(DisasContext *dc, const O= pcodeArg arg[], gen_set_label(label); tcg_gen_extract_i32(arg[0].out, cpu_SR[ATOMCTL], 8, 1); tcg_gen_deposit_i32(cpu_SR[ATOMCTL], cpu_SR[ATOMCTL], res, 8, 1); - tcg_temp_free(prev); - tcg_temp_free(addr); - tcg_temp_free(res); } =20 static void translate_salt(DisasContext *dc, const OpcodeArg arg[], @@ -2338,7 +2278,6 @@ static void translate_sext(DisasContext *dc, const Op= codeArg arg[], TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_shli_i32(tmp, arg[1].in, shift); tcg_gen_sari_i32(arg[0].out, tmp, shift); - tcg_temp_free(tmp); } } =20 @@ -2378,8 +2317,6 @@ static void translate_simcall(DisasContext *dc, const= OpcodeArg arg[], tcg_gen_extu_i32_i64(tmp, reg); \ tcg_gen_##cmd##_i64(v, v, tmp); \ tcg_gen_extrl_i64_i32(arg[0].out, v); \ - tcg_temp_free_i64(v); \ - tcg_temp_free_i64(tmp); \ } while (0) =20 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR]) @@ -2396,7 +2333,6 @@ static void translate_sll(DisasContext *dc, const Opc= odeArg arg[], tcg_gen_andi_i32(s, s, 0x3f); tcg_gen_extu_i32_i64(v, arg[1].in); gen_shift_reg(shl, s); - tcg_temp_free(s); } } =20 @@ -2463,7 +2399,6 @@ static void translate_ssa8b(DisasContext *dc, const O= pcodeArg arg[], TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_shli_i32(tmp, arg[0].in, 3); gen_left_shift_sar(dc, tmp); - tcg_temp_free(tmp); } =20 static void translate_ssa8l(DisasContext *dc, const OpcodeArg arg[], @@ -2472,7 +2407,6 @@ static void translate_ssa8l(DisasContext *dc, const O= pcodeArg arg[], TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_shli_i32(tmp, arg[0].in, 3); gen_right_shift_sar(dc, tmp); - tcg_temp_free(tmp); } =20 static void translate_ssai(DisasContext *dc, const OpcodeArg arg[], @@ -2505,7 +2439,6 @@ static void translate_subx(DisasContext *dc, const Op= codeArg arg[], TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_shli_i32(tmp, arg[1].in, par[0]); tcg_gen_sub_i32(arg[0].out, tmp, arg[2].in); - tcg_temp_free(tmp); } =20 static void translate_waiti(DisasContext *dc, const OpcodeArg arg[], @@ -2757,7 +2690,6 @@ static void translate_xsr(DisasContext *dc, const Opc= odeArg arg[], tcg_gen_mov_i32(tmp, arg[0].in); tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]); tcg_gen_mov_i32(cpu_SR[par[0]], tmp); - tcg_temp_free(tmp); } else { tcg_gen_movi_i32(arg[0].out, 0); } @@ -2772,7 +2704,6 @@ static void translate_xsr_mask(DisasContext *dc, cons= t OpcodeArg arg[], tcg_gen_mov_i32(tmp, arg[0].in); tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]); tcg_gen_andi_i32(cpu_SR[par[0]], tmp, par[2]); - tcg_temp_free(tmp); } else { tcg_gen_movi_i32(arg[0].out, 0); } @@ -2792,7 +2723,6 @@ static void translate_xsr_ccount(DisasContext *dc, co= nst OpcodeArg arg[], tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); gen_helper_wsr_ccount(cpu_env, arg[0].in); tcg_gen_mov_i32(arg[0].out, tmp); - tcg_temp_free(tmp); =20 #endif } @@ -2810,7 +2740,6 @@ static void translate_xsr_ccount(DisasContext *dc, co= nst OpcodeArg arg[], } \ translate_wsr_##name(dc, arg, par); \ tcg_gen_mov_i32(arg[0].out, tmp); \ - tcg_temp_free(tmp); \ } =20 gen_translate_xsr(acchi) @@ -6297,16 +6226,6 @@ static inline void put_f32_o1_i3(const OpcodeArg *ar= g, const OpcodeArg *arg32, (o0 >=3D 0 && arg[o0].num_bits =3D=3D 64)) { if (o0 >=3D 0) { tcg_gen_extu_i32_i64(arg[o0].out, arg32[o0].out); - tcg_temp_free_i32(arg32[o0].out); - } - if (i0 >=3D 0) { - tcg_temp_free_i32(arg32[i0].in); - } - if (i1 >=3D 0) { - tcg_temp_free_i32(arg32[i1].in); - } - if (i2 >=3D 0) { - tcg_temp_free_i32(arg32[i2].in); } } } @@ -6430,9 +6349,6 @@ static void translate_compare_d(DisasContext *dc, con= st OpcodeArg arg[], tcg_gen_movcond_i32(TCG_COND_NE, arg[0].out, res, zero, set_br, clr_br); - tcg_temp_free(res); - tcg_temp_free(set_br); - tcg_temp_free(clr_br); } =20 static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[], @@ -6463,9 +6379,6 @@ static void translate_compare_s(DisasContext *dc, con= st OpcodeArg arg[], arg[0].out, res, zero, set_br, clr_br); put_f32_i2(arg, arg32, 1, 2); - tcg_temp_free(res); - tcg_temp_free(set_br); - tcg_temp_free(clr_br); } =20 static void translate_const_d(DisasContext *dc, const OpcodeArg arg[], @@ -6584,7 +6497,6 @@ static void translate_ldsti(DisasContext *dc, const O= pcodeArg arg[], if (par[1]) { tcg_gen_mov_i32(arg[1].out, addr); } - tcg_temp_free(addr); } =20 static void translate_ldstx(DisasContext *dc, const OpcodeArg arg[], @@ -6603,7 +6515,6 @@ static void translate_ldstx(DisasContext *dc, const O= pcodeArg arg[], if (par[1]) { tcg_gen_mov_i32(arg[1].out, addr); } - tcg_temp_free(addr); } =20 static void translate_fpu2k_madd_s(DisasContext *dc, const OpcodeArg arg[], @@ -6639,7 +6550,6 @@ static void translate_movcond_d(DisasContext *dc, con= st OpcodeArg arg[], tcg_gen_movcond_i64(par[0], arg[0].out, arg2, zero, arg[1].in, arg[0].in); - tcg_temp_free_i64(arg2); } =20 static void translate_movcond_s(DisasContext *dc, const OpcodeArg arg[], @@ -6668,8 +6578,6 @@ static void translate_movp_d(DisasContext *dc, const = OpcodeArg arg[], tcg_gen_movcond_i64(par[0], arg[0].out, tmp2, zero, arg[1].in, arg[0].in); - tcg_temp_free_i32(tmp1); - tcg_temp_free_i64(tmp2); } =20 static void translate_movp_s(DisasContext *dc, const OpcodeArg arg[], @@ -6683,7 +6591,6 @@ static void translate_movp_s(DisasContext *dc, const = OpcodeArg arg[], tcg_gen_movcond_i32(par[0], arg[0].out, tmp, zero, arg[1].in, arg[0].in); - tcg_temp_free(tmp); } else { translate_movp_d(dc, arg, par); } @@ -7015,7 +6922,6 @@ static void translate_cvtd_s(DisasContext *dc, const = OpcodeArg arg[], =20 tcg_gen_extrl_i64_i32(v, arg[1].in); gen_helper_cvtd_s(arg[0].out, cpu_env, v); - tcg_temp_free_i32(v); } =20 static void translate_cvts_d(DisasContext *dc, const OpcodeArg arg[], @@ -7025,7 +6931,6 @@ static void translate_cvts_d(DisasContext *dc, const = OpcodeArg arg[], =20 gen_helper_cvts_d(v, cpu_env, arg[1].in); tcg_gen_extu_i32_i64(arg[0].out, v); - tcg_temp_free_i32(v); } =20 static void translate_ldsti_d(DisasContext *dc, const OpcodeArg arg[], @@ -7053,9 +6958,6 @@ static void translate_ldsti_d(DisasContext *dc, const= OpcodeArg arg[], tcg_gen_addi_i32(arg[1].out, arg[1].in, arg[2].imm); } } - if (par[1]) { - tcg_temp_free(addr); - } } =20 static void translate_ldsti_s(DisasContext *dc, const OpcodeArg arg[], @@ -7088,9 +6990,6 @@ static void translate_ldsti_s(DisasContext *dc, const= OpcodeArg arg[], tcg_gen_addi_i32(arg[1].out, arg[1].in, arg[2].imm); } } - if (par[1]) { - tcg_temp_free(addr); - } } =20 static void translate_ldstx_d(DisasContext *dc, const OpcodeArg arg[], @@ -7118,9 +7017,6 @@ static void translate_ldstx_d(DisasContext *dc, const= OpcodeArg arg[], tcg_gen_add_i32(arg[1].out, arg[1].in, arg[2].in); } } - if (par[1]) { - tcg_temp_free(addr); - } } =20 static void translate_ldstx_s(DisasContext *dc, const OpcodeArg arg[], @@ -7153,9 +7049,6 @@ static void translate_ldstx_s(DisasContext *dc, const= OpcodeArg arg[], tcg_gen_add_i32(arg[1].out, arg[1].in, arg[2].in); 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.31.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:31:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+Wc1hlFKIswkkOoSzlvhTQxjrrbSS+xMNCJHLW8hOEw=; b=eyRpL5pLnUx2CSsFS+1XTRS1ln1JMc4Wno++twKo123HrbFr83X4bGnb298DuobnbR j3CuN4u1dDkJ9IpDio7mwkoGIF9rq+5lYm+1CP5kK8VmnAbpwperLc2kzxO17rV8wlKr 7B/mLFMPhtWFpxtsMrpG9nmpIGUjy2J4WfpBFdTceBZb9LraiG+kb8ryUTQn82T279yy 0u0z/gAfDvVuwA71ZJMn+jBJpm0aEAVqX7kdQYaGLjMmPf5lMV/y0ZT/a6j0p+aoeVeN pLBvcI3W48fs64ufpE1SJv/uG8XbHXXNbezN20emfBhK9oGdSUpnmtfjCqS8X9PwtrjB yTkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+Wc1hlFKIswkkOoSzlvhTQxjrrbSS+xMNCJHLW8hOEw=; b=h7WY6pUSdO/aqkqyUt5mFrd3G+nx4Xo2yDPtZBqk09WN3kmsG6L1/8IXRHignqowpm IqfRvEnykL0jedawwuHKclXFtfYAdcmXuCCy9QKshQyQUmADUNO0J+8b9RVOmmR+pr1f c3cM36LHkbS02c2xvTcNydJaJmjpNsrHG2KQR1nA8GtBS456m80JJ5pkgyAeU8eESQQM uREdRpUXyBwbHjvGuNcxMWEShsfgLqEElEL+lhbIliy1nCqfwXIXRyTyRE2Bi+pk3mIX BsQhF3pIE1RYecXCX0P64IU2pjN8afosBP+/m98lQi1cy16brIuNX1TuF0dFPlSx4QC2 rsJA== X-Gm-Message-State: AO0yUKVR0pbpIisla2zOzXZ1kXAF5mIYM2CKXnc/I0FC2UUvzLZQ0Vb8 7csxn1k7PdnnLHIoQS9s4p2r+wfiz9z1pdEVl94= X-Google-Smtp-Source: AK7set/a8R81gE8fHnFaat+IgA9u8AlqWM0lRk3Q1bHr35eMct4nQ26Y4dS89Z9IqxJg8+VHY9QbjA== X-Received: by 2002:a17:90a:1e:b0:236:70e6:ef08 with SMTP id 30-20020a17090a001e00b0023670e6ef08mr23185655pja.49.1677475896237; Sun, 26 Feb 2023 21:31:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 73/76] include/exec/gen-icount: Drop tcg_temp_free in gen_tb_start Date: Sun, 26 Feb 2023 19:25:02 -1000 Message-Id: <20230227052505.352889-74-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476168817100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- include/exec/gen-icount.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 733a2fb228..bbeb85832e 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -62,8 +62,6 @@ static inline void gen_tb_start(const TranslationBlock *t= b) offsetof(ArchCPU, parent_obj.can_do_io) - offsetof(ArchCPU, env)); } - - tcg_temp_free_i32(count); } =20 static inline void gen_tb_end(const TranslationBlock *tb, int num_insns) --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677476492; cv=none; d=zohomail.com; s=zohoarc; b=WSHj+h3JoOtVw5y9UzS47WYw98aq7RR/10OZ39Tl9VX3cPKUaPVYD0t165y49ShYxS/Nb3ZXSX2KMmbA1jtSr9T2t2zySxyhLnAg707NwJkB1mCSYLsE98IW5/LUvWZuF00G2qmKD8smrte40Kq+WFoiofoc4qzcXZLrf+/YISM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677476492; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Mto8gZo3djU/h+euQ02hp/2HLo7eYXM2X3ttNgQzbL0=; b=WlzfB7P/1ajqFPQrNrcLGPGIj6idYrvGLVX/KYoAXorG7tYeS6XIoYluQSOsJlys1y9+2VwQq/3xthUKCAy03ACgJKRyOti3GOSLhDV5cnb+NYnKiO/Nq8gxtr7qZxWzG4EW2qASocPSg+0XoFb/nQ0DJSdDHMxVTYryXuLGfis= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677476492880496.46094902925745; Sun, 26 Feb 2023 21:41:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWW8M-0004w7-OL; Mon, 27 Feb 2023 00:33:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWW6y-0000Fs-2I for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:31:47 -0500 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWW6u-00017h-C6 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 00:31:43 -0500 Received: by mail-pj1-x1043.google.com with SMTP id y15-20020a17090aa40f00b00237ad8ee3a0so5052260pjp.2 for ; Sun, 26 Feb 2023 21:31:39 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.31.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:31:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Mto8gZo3djU/h+euQ02hp/2HLo7eYXM2X3ttNgQzbL0=; b=dPMjuN51uwbpJ4JmQ8SW7crleXCdFGo1x9CSDSYZra3JOiBT+/WAyRyZLkK5lVhY/h 8UoV0j0SIW5ynF0sHAeGj9BaR/U6CcNUDCCdYyDABGht9IY/gzgwmB/tzWEn7kSXb39D 3O2LdU2fsyviWlioVImh9/v1k/WhTokm9aWDFwMnGxVKK6OdG85HmfGCJ50goOcWAXI6 +bVUUDUxyThZZY6Uiv1z5tqPZl4syciaEYk1sUb0GOOaFuZeldQhfQCo27cOBOPKf6fJ OaP3VIQ+QhDgATQIbyhhrPhe0clKDDN8YPInBKojC+7ERsAujgIm5agFdn0QBa8R+X44 4+1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mto8gZo3djU/h+euQ02hp/2HLo7eYXM2X3ttNgQzbL0=; b=8M1Heo+mGtVr3JN344/c9XgiDaKb03jUa4N90c21clMwF6rjpWM4E7afrSVLdgI3YI HvnM+tnth7DHMeVqOukU6PAH7HQxNWhsEW3q5XIN0kipCmSDoNNFieJe5BpKgf8nPFE3 ZO821CZ3nXY0FpXFVcuOSyrvAwp9oOgjUH6+1bedNO7LQ+GfcWsg+WMxaf88KeTU8BWT S85Ylupw2bfbirB2X+pic+F5JqK0UQckUyVmIq7xErqDhkamcqnVYibtgSvLX1JHf5wj EQdLvvzowtF+dOLOcoACNdkFE98ddxcoxJ/tpjyHNh1txuUEcHN61ZsKy2b5nmJoLC3R bRXQ== X-Gm-Message-State: AO0yUKXnhA6wCvkOhXNLUuFlNANgquT6GnACVG9qXFDf3Q61txapNZvt bOV0N9+9en1dY87tgIh3bkIDdVPlNFL3RRY3kElfaw== X-Google-Smtp-Source: AK7set90O85UfQt7TwehI8ptmrVIzhQfI92kmfbROxj5iSCGOjg3DyrZ70/UoLTSO46h41R6qGqh0w== X-Received: by 2002:a17:90b:1b09:b0:233:c3e7:bd37 with SMTP id nu9-20020a17090b1b0900b00233c3e7bd37mr7792845pjb.10.1677475898982; Sun, 26 Feb 2023 21:31:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 74/76] tracing: remove transform.py Date: Sun, 26 Feb 2023 19:25:03 -1000 Message-Id: <20230227052505.352889-75-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476494254100005 This file, and a couple of uses, got left behind when the tcg stuff was removed from tracetool. Fixes: 126d4123c50a ("tracing: excise the tcg related from tracetool") Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- meson.build | 1 - scripts/tracetool/__init__.py | 23 ----- scripts/tracetool/transform.py | 168 --------------------------------- 3 files changed, 192 deletions(-) delete mode 100644 scripts/tracetool/transform.py diff --git a/meson.build b/meson.build index 6cb2b1a42f..275399b8c2 100644 --- a/meson.build +++ b/meson.build @@ -2861,7 +2861,6 @@ tracetool_depends =3D files( 'scripts/tracetool/format/log_stap.py', 'scripts/tracetool/format/stap.py', 'scripts/tracetool/__init__.py', - 'scripts/tracetool/transform.py', 'scripts/tracetool/vcpu.py' ) =20 diff --git a/scripts/tracetool/__init__.py b/scripts/tracetool/__init__.py index 5393c7fc5c..33cf85e2b0 100644 --- a/scripts/tracetool/__init__.py +++ b/scripts/tracetool/__init__.py @@ -18,7 +18,6 @@ =20 import tracetool.format import tracetool.backend -import tracetool.transform =20 =20 def error_write(*lines): @@ -190,18 +189,6 @@ def casted(self): """List of argument names casted to their type.""" return ["(%s)%s" % (type_, name) for type_, name in self._args] =20 - def transform(self, *trans): - """Return a new Arguments instance with transformed types. - - The types in the resulting Arguments instance are transformed acco= rding - to tracetool.transform.transform_type. - """ - res =3D [] - for type_, name in self._args: - res.append((tracetool.transform.transform_type(type_, *trans), - name)) - return Arguments(res) - =20 class Event(object): """Event description. @@ -358,16 +345,6 @@ def api(self, fmt=3DNone): fmt =3D Event.QEMU_TRACE return fmt % {"name": self.name, "NAME": self.name.upper()} =20 - def transform(self, *trans): - """Return a new Event with transformed Arguments.""" - return Event(self.name, - list(self.properties), - self.fmt, - self.args.transform(*trans), - self.lineno, - self.filename, - self) - =20 def read_events(fobj, fname): """Generate the output for the given (format, backends) pair. diff --git a/scripts/tracetool/transform.py b/scripts/tracetool/transform.py deleted file mode 100644 index ea8b27799d..0000000000 --- a/scripts/tracetool/transform.py +++ /dev/null @@ -1,168 +0,0 @@ -# -*- coding: utf-8 -*- - -""" -Type-transformation rules. -""" - -__author__ =3D "Llu=C3=ADs Vilanova " -__copyright__ =3D "Copyright 2012-2016, Llu=C3=ADs Vilanova " -__license__ =3D "GPL version 2 or (at your option) any later version" - -__maintainer__ =3D "Stefan Hajnoczi" -__email__ =3D "stefanha@redhat.com" - - -def _transform_type(type_, trans): - if isinstance(trans, str): - return trans - elif isinstance(trans, dict): - if type_ in trans: - return _transform_type(type_, trans[type_]) - elif None in trans: - return _transform_type(type_, trans[None]) - else: - return type_ - elif callable(trans): - return trans(type_) - else: - raise ValueError("Invalid type transformation rule: %s" % trans) - - -def transform_type(type_, *trans): - """Return a new type transformed according to the given rules. - - Applies each of the transformation rules in trans in order. - - If an element of trans is a string, return it. - - If an element of trans is a function, call it with type_ as its only - argument. - - If an element of trans is a dict, search type_ in its keys. If type_ is - a key, use the value as a transformation rule for type_. Otherwise, if - None is a key use the value as a transformation rule for type_. - - Otherwise, return type_. - - Parameters - ---------- - type_ : str - Type to transform. - trans : list of function or dict - Type transformation rules. - """ - if len(trans) =3D=3D 0: - raise ValueError - res =3D type_ - for t in trans: - res =3D _transform_type(res, t) - return res - - -################################################## -# tcg -> host - -def _tcg_2_host(type_): - if type_ =3D=3D "TCGv": - # force a fixed-size type (target-independent) - return "uint64_t" - else: - return type_ - -TCG_2_HOST =3D { - "TCGv_i32": "uint32_t", - "TCGv_i64": "uint64_t", - "TCGv_ptr": "void *", - None: _tcg_2_host, - } - - -################################################## -# host -> host compatible with tcg sizes - -HOST_2_TCG_COMPAT =3D { - "uint8_t": "uint32_t", - "uint16_t": "uint32_t", - } - - -################################################## -# host/tcg -> tcg - -def _host_2_tcg(type_): - if type_.startswith("TCGv"): - return type_ - raise ValueError("Don't know how to translate '%s' into a TCG type\n" = % type_) - -HOST_2_TCG =3D { - "uint32_t": "TCGv_i32", - "uint64_t": "TCGv_i64", - "void *" : "TCGv_ptr", - "CPUArchState *": "TCGv_env", - None: _host_2_tcg, - } - - -################################################## -# tcg -> tcg helper definition - -def _tcg_2_helper_def(type_): - if type_ =3D=3D "TCGv": - return "target_ulong" - else: - return type_ - -TCG_2_TCG_HELPER_DEF =3D { - "TCGv_i32": "uint32_t", - "TCGv_i64": "uint64_t", - "TCGv_ptr": "void *", - None: _tcg_2_helper_def, - } - - -################################################## -# tcg -> tcg helper declaration - -def _tcg_2_tcg_helper_decl_error(type_): - raise ValueError("Don't know how to translate type '%s' into a TCG hel= per declaration type\n" % type_) - -TCG_2_TCG_HELPER_DECL =3D { - "TCGv" : "tl", - "TCGv_ptr": "ptr", - "TCGv_i32": "i32", - "TCGv_i64": "i64", - "TCGv_env": "env", - None: _tcg_2_tcg_helper_decl_error, - } - - -################################################## -# host/tcg -> tcg temporal constant allocation - -def _host_2_tcg_tmp_new(type_): - if type_.startswith("TCGv"): - return "tcg_temp_new_nop" - raise ValueError("Don't know how to translate type '%s' into a TCG tem= poral allocation" % type_) - -HOST_2_TCG_TMP_NEW =3D { - "uint32_t": "tcg_const_i32", - "uint64_t": "tcg_const_i64", - "void *" : "tcg_const_ptr", - None: _host_2_tcg_tmp_new, - } - - -################################################## -# host/tcg -> tcg temporal constant deallocation - -def _host_2_tcg_tmp_free(type_): - if type_.startswith("TCGv"): - return "tcg_temp_free_nop" - raise ValueError("Don't know how to translate type '%s' into a TCG tem= poral deallocation" % type_) - -HOST_2_TCG_TMP_FREE =3D { - "uint32_t": "tcg_temp_free_i32", - "uint64_t": "tcg_temp_free_i64", - "void *" : "tcg_temp_free_ptr", - None: _host_2_tcg_tmp_free, - } --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.31.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:31:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gP1FaZV2jwIFaxfD+zljAWbUZCjQNTs1C1nJUdyENMk=; b=f4NIbzjlpOAYCyVriH3M7UqW19rm5g1zhb8Vg0zjrAq3A/Ny3mUR5FwkHcNn2ZClPO iu3zAHqSnQW8QNbrVe93guF0+QqlMC91EKNjVOf16+h7lHI1qw2x+u1DCoMwLSjNprPt NdTKomWTAHL8BOMgvsqKAK2OzJSnZlIagSmHIWaFif7l2m5QBnv94WfUQxoWi5Y26LDh S0cjIRMjyuW94oTNt4K6HcZthYJZlUTKLcwNV3MhqVJaNYhbGUTCGh2AtT4/TMbUPqMD 3RUuepvtxphbahSAkDoGmVD0lTaIfWmogV5BdHEbcFzq0XyO6dH7BD5cifsr02DS2qKH 4qiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gP1FaZV2jwIFaxfD+zljAWbUZCjQNTs1C1nJUdyENMk=; b=e2aQEWL6EeLFE065GHnX/PhHhzjph+J0HIi5bUowhpP/+bbVYkbHyyma5Tum5WrUV0 pN75sq6L4mSeRs+i3cX3wZjqP3VG0VRfBu+VmaPjn0VVqT0muv1mYYoIscRaQGf9kD2Z r+8ZhOZOpNbByQToThnU7M3C2yihuzPGoDnRoMQmg+RHt/aoEC39wk4OrFiMSskUKQ7E apssET6Q0GopMjmYcivtD4H0GTmgFNqrLISOUy3G2u8zZcRBpQgml+X2imHTQTGR8cWL zUgvH0wDgMxTJnzn7lIUuBFlGQ+qaorptk14pwB4lN8NJW8SBc2Mlr7PitekthxH+yGb cexQ== X-Gm-Message-State: AO0yUKW3UCJ7fzp2WMdd6cSk/jbuGXWYWcpAjLTTrXqCkhVJUgZcWKPc +D1wrpXMuZi1S8ViK8buLk2nydHKvREJN0Yoedc= X-Google-Smtp-Source: AK7set+AbJzjGMaSNL/r0t5DJ1tz1MFCQ4SvTMsWCpryhyAfVOTlLDfYe4A0Ijm9hoA91q9Ug3w28Q== X-Received: by 2002:a17:90b:4a03:b0:233:457f:e71c with SMTP id kk3-20020a17090b4a0300b00233457fe71cmr26671400pjb.38.1677475901653; Sun, 26 Feb 2023 21:31:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 75/76] tcg: Create tcg/tcg-temp-internal.h Date: Sun, 26 Feb 2023 19:25:04 -1000 Message-Id: <20230227052505.352889-76-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: 23 X-Spam_score: 2.3 X-Spam_bar: ++ X-Spam_report: (2.3 / 5.0 requ) BAYES_00=-1.9, BITCOIN_OBFU_SUBJ=3.375, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FUZZY_BITCOIN=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476261334100002 Content-Type: text/plain; charset="utf-8" Move the tcg_temp_free_* and tcg_temp_ebb_new_* declarations and inlines to the new header. These are private to the implementation, and will prevent tcg_temp_free_* from creaping back into the guest front ends. Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland Reviewed-by: Peter Maydell --- include/tcg/tcg-temp-internal.h | 83 +++++++++++++++++++++++++++++++++ include/tcg/tcg.h | 54 --------------------- accel/tcg/plugin-gen.c | 1 + tcg/tcg-op-gvec.c | 1 + tcg/tcg-op-vec.c | 1 + tcg/tcg-op.c | 1 + tcg/tcg.c | 1 + 7 files changed, 88 insertions(+), 54 deletions(-) create mode 100644 include/tcg/tcg-temp-internal.h diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-interna= l.h new file mode 100644 index 0000000000..dded2917e5 --- /dev/null +++ b/include/tcg/tcg-temp-internal.h @@ -0,0 +1,83 @@ +/* + * TCG internals related to TCG temp allocation + * + * Copyright (c) 2008 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef TCG_TEMP_INTERNAL_H +#define TCG_TEMP_INTERNAL_H + +/* + * Allocation and freeing of EBB temps is reserved to TCG internals + */ + +void tcg_temp_free_internal(TCGTemp *); + +static inline void tcg_temp_free_i32(TCGv_i32 arg) +{ + tcg_temp_free_internal(tcgv_i32_temp(arg)); +} + +static inline void tcg_temp_free_i64(TCGv_i64 arg) +{ + tcg_temp_free_internal(tcgv_i64_temp(arg)); +} + +static inline void tcg_temp_free_i128(TCGv_i128 arg) +{ + tcg_temp_free_internal(tcgv_i128_temp(arg)); +} + +static inline void tcg_temp_free_ptr(TCGv_ptr arg) +{ + tcg_temp_free_internal(tcgv_ptr_temp(arg)); +} + +static inline void tcg_temp_free_vec(TCGv_vec arg) +{ + tcg_temp_free_internal(tcgv_vec_temp(arg)); +} + +static inline TCGv_i32 tcg_temp_ebb_new_i32(void) +{ + TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I32, TEMP_EBB); + return temp_tcgv_i32(t); +} + +static inline TCGv_i64 tcg_temp_ebb_new_i64(void) +{ + TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I64, TEMP_EBB); + return temp_tcgv_i64(t); +} + +static inline TCGv_i128 tcg_temp_ebb_new_i128(void) +{ + TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I128, TEMP_EBB); + return temp_tcgv_i128(t); +} + +static inline TCGv_ptr tcg_temp_ebb_new_ptr(void) +{ + TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_EBB); + return temp_tcgv_ptr(t); +} + +#endif /* TCG_TEMP_FREE_H */ diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index e8f73115ec..43ce4bfa7d 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -855,35 +855,9 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t= start, intptr_t size); TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, intptr_t, const char *); TCGTemp *tcg_temp_new_internal(TCGType, TCGTempKind); -void tcg_temp_free_internal(TCGTemp *); TCGv_vec tcg_temp_new_vec(TCGType type); TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); =20 -static inline void tcg_temp_free_i32(TCGv_i32 arg) -{ - tcg_temp_free_internal(tcgv_i32_temp(arg)); -} - -static inline void tcg_temp_free_i64(TCGv_i64 arg) -{ - tcg_temp_free_internal(tcgv_i64_temp(arg)); -} - -static inline void tcg_temp_free_i128(TCGv_i128 arg) -{ - tcg_temp_free_internal(tcgv_i128_temp(arg)); -} - -static inline void tcg_temp_free_ptr(TCGv_ptr arg) -{ - tcg_temp_free_internal(tcgv_ptr_temp(arg)); -} - -static inline void tcg_temp_free_vec(TCGv_vec arg) -{ - tcg_temp_free_internal(tcgv_vec_temp(arg)); -} - static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offse= t, const char *name) { @@ -891,13 +865,6 @@ static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr= reg, intptr_t offset, return temp_tcgv_i32(t); } =20 -/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */ -static inline TCGv_i32 tcg_temp_ebb_new_i32(void) -{ - TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I32, TEMP_EBB); - return temp_tcgv_i32(t); -} - static inline TCGv_i32 tcg_temp_new_i32(void) { TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I32, TEMP_TB); @@ -911,26 +878,12 @@ static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_pt= r reg, intptr_t offset, return temp_tcgv_i64(t); } =20 -/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */ -static inline TCGv_i64 tcg_temp_ebb_new_i64(void) -{ - TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I64, TEMP_EBB); - return temp_tcgv_i64(t); -} - static inline TCGv_i64 tcg_temp_new_i64(void) { TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I64, TEMP_TB); return temp_tcgv_i64(t); } =20 -/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */ -static inline TCGv_i128 tcg_temp_ebb_new_i128(void) -{ - TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I128, TEMP_EBB); - return temp_tcgv_i128(t); -} - static inline TCGv_i128 tcg_temp_new_i128(void) { TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I128, TEMP_TB); @@ -944,13 +897,6 @@ static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr= reg, intptr_t offset, return temp_tcgv_ptr(t); } =20 -/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */ -static inline TCGv_ptr tcg_temp_ebb_new_ptr(void) -{ - TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_EBB); - return temp_tcgv_ptr(t); -} - static inline TCGv_ptr tcg_temp_new_ptr(void) { TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_TB); diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index c42a436c0c..5efb8db258 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -44,6 +44,7 @@ */ #include "qemu/osdep.h" #include "tcg/tcg.h" +#include "tcg/tcg-temp-internal.h" #include "tcg/tcg-op.h" #include "exec/exec-all.h" #include "exec/plugin-gen.h" diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 877b0b659b..f7072b213f 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "tcg/tcg.h" +#include "tcg/tcg-temp-internal.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "qemu/main-loop.h" diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 966d41d65a..0f023f42c6 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "tcg/tcg.h" +#include "tcg/tcg-temp-internal.h" #include "tcg/tcg-op.h" #include "tcg/tcg-mo.h" #include "tcg-internal.h" diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index f2269a1b91..53e96b5b69 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -25,6 +25,7 @@ #include "qemu/osdep.h" #include "exec/exec-all.h" #include "tcg/tcg.h" +#include "tcg/tcg-temp-internal.h" #include "tcg/tcg-op.h" #include "tcg/tcg-mo.h" #include "exec/plugin-gen.h" diff --git a/tcg/tcg.c b/tcg/tcg.c index e3c0fa1012..4d3fb6aee2 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -60,6 +60,7 @@ #include "elf.h" #include "exec/log.h" #include "tcg/tcg-ldst.h" +#include "tcg/tcg-temp-internal.h" #include "tcg-internal.h" #include "accel/tcg/perf.h" =20 --=20 2.34.1 From nobody Fri May 10 13:58:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.31.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:31:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6I7Tkr0gEn5C9IQe3ln5Tw/bG/eqeOfdkUEZ9u/mHS8=; b=mCNFkg1KAEm6JAKFnd8Dj1uDhojomv3wDz7YeWWJxTZR56LZxsYGvCSSpTDNh//A+w 6+ybr0XnCqwgrnapWtMr1nRSpuPRLsgTLnTad/ysGXM54NjZyTy8qMBFrQDsGSsmpOjg 0JyerYruIwtvdMWjRMTe1kuTk72gBqKZJyP3JqXHzK7lAHicWuXA6JGGVdijfSMxlkMd 3BHN4uLUS7k0IjusWqDcP/7oZhChoRF65UMmFWr9pb5NLifbXMNfrbKgaHZp7ANjVod4 aDJSaNnGsGtX/ww+MPPVoHJYkIsNrPLb/ZZfme5yZ7MDmR18LsB/4ShqaFvPlNyaCpFn TGiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6I7Tkr0gEn5C9IQe3ln5Tw/bG/eqeOfdkUEZ9u/mHS8=; b=JHUOGgZapY/i/m7tFrMuMEjsDexcVYc9WDaOKqKZZeeb7oIJAugtZb0Oe5FVoIb6Ga BnojLgZrvPqMrSn8uapx7kE7DbvJC7bJ+g+Jo8QmtTppglrR9iuuth2WzyKckk9RrfP6 2fcA3j8kvnu9cx2NgYZqRs/bbyVG+PRvYllTApba82CmlbDIYD37QOJDGNQgTyx/fcWI wfUccazP0wqOMXaQFrzm6yvOUpSYZB2YFB/nMq3g3DSx9/8m+jGIzf8ftGTyDUJeZYL/ iwoXwZsCqW/UglMiKYB/+kY3ae3m7GioQK0sXcaU1iaNrxzCc3uMh2eESiUnVFdJGZTd zH6A== X-Gm-Message-State: AO0yUKWw0+W8QVgMruIKE9AFfXvqDR1dIE8A0yJtX4SlTRj3BfAw+hZO /Qxvyw9gNqW5IEYX3oN5vx6vJmlHZKQ8qsnS2dI= X-Google-Smtp-Source: AK7set9YRmZ5/P5MlijVmSzd9iM2zPOk2StbY7weZLH3FndmWE3gZsYRHAn8TCOCgcIw/57QRe3XmQ== X-Received: by 2002:a17:90b:4f8f:b0:234:190d:e636 with SMTP id qe15-20020a17090b4f8f00b00234190de636mr25563686pjb.8.1677475904448; Sun, 26 Feb 2023 21:31:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com, Daniel Henrique Barboza Subject: [PATCH v2 76/76] docs/devel/tcg-ops: Drop recommendation to free temps Date: Sun, 26 Feb 2023 19:25:05 -1000 Message-Id: <20230227052505.352889-77-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476757430100005 Content-Type: text/plain; charset="utf-8" Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson Acked-by: Mark Cave-Ayland --- docs/devel/tcg-ops.rst | 4 ---- 1 file changed, 4 deletions(-) diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst index 561c416574..f3f451b77f 100644 --- a/docs/devel/tcg-ops.rst +++ b/docs/devel/tcg-ops.rst @@ -951,10 +951,6 @@ Recommended coding rules for best performance often modified, e.g. the integer registers and the condition codes. TCG will be able to use host registers to store them. =20 -- Free temporaries when they are no longer used (``tcg_temp_free``). - Since ``tcg_const_x`` also creates a temporary, you should free it - after it is used. - - Don't hesitate to use helpers for complicated or seldom used guest instructions. There is little performance advantage in using TCG to implement guest instructions taking more than about twenty TCG --=20 2.34.1