From nobody Sun May 19 00:17:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1677431182; cv=none; d=zohomail.com; s=zohoarc; b=jskDBb+c039vlKR4Uzaj4t3a5OLLvSFtn6iWck8DoKAvS4A7S0hzVlxY65eicCB1cWclmKBX2TWwA0XMbLIWAvDfTcpbAYG2rSwjoCIWBoVsNzqGhK2brHzyFaEAu3kW+6w5Mi1HNRNfu6OUlPV0kybKDEvfq524Hfz6sBBuv9A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677431182; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ejl0lWpG19j5guDTl5f5eWDqwqvkWZyhyou5WK2+ZZE=; b=hq9zWXRZHkVQgk5aLTbXHB4MFnuhOpgHXBqmoAUuKGDtSL0JzVKFan2uW7QXNn8NNB3MdMuq7GXv3iWx/9d3GsSBqAHjGVaqZl5H/0T964dSZXoKuSIDSU7Jz8KQNGJjKXoVSUj8vkGDBjQusuU4gsOY5AvquoiXSbdYyINogNU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677431182647409.3123866231268; Sun, 26 Feb 2023 09:06:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWKSm-0007wr-3l; Sun, 26 Feb 2023 12:05:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWKSk-0007w0-I7 for qemu-devel@nongnu.org; Sun, 26 Feb 2023 12:05:26 -0500 Received: from mail-oi1-x236.google.com ([2607:f8b0:4864:20::236]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWKSi-0001hW-Dg for qemu-devel@nongnu.org; Sun, 26 Feb 2023 12:05:26 -0500 Received: by mail-oi1-x236.google.com with SMTP id bk32so3482726oib.10 for ; Sun, 26 Feb 2023 09:05:24 -0800 (PST) Received: from grind.. ([189.110.112.117]) by smtp.gmail.com with ESMTPSA id n83-20020acaef56000000b00383b8011881sm2142406oih.18.2023.02.26.09.05.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 09:05:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ejl0lWpG19j5guDTl5f5eWDqwqvkWZyhyou5WK2+ZZE=; b=X0Y64Q94rihSI6V5UW5j8Gi2TpcnFk493IaeLkoggPXzGFjwF6w9kuWok4q0PjxYet p93xuYVArKzGLXqbQf7eTH00nr0JCFLyZNgYrWzt1ghixJEzyXc725ePZG5vGgp1UO/d 6g9PXRwrrSidKu1BMkBa/StyTVbTZRCpgyD3h7dCWJ2sdfUwnYzp7xBejHTRaAO1Zvr4 CmtahcPWJMAdR2A12nahd/+5nP8qHhVsNBfrzW8j+exksXHIBgWzH61qT00ja2sxS90p /ZLEPd2bYhh/ZPAw6EnYJyhJWjqiHHZy1WzXrSm4bwUfGRm4gEF/OSTMpfo6DyrTBsOz /ONQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ejl0lWpG19j5guDTl5f5eWDqwqvkWZyhyou5WK2+ZZE=; b=O3I8VDkNcD1jauGm8TAnJl6Bh7MlTZtx5PbyS209bplg9bfVl+YLOLnqFjTsuAtOV8 WhmK6p71gigX+ed1Vm0Az3AGY6OJe09WGk6n4Ys4LSIBqu3Pq9MoXV1FRpsi3lrQ83b0 pVbccx/Rc1eqT3KFvehh5SnmlOT6bkZqaJ+ZsbpdOHqzJeV1QK3+0TesonACC8Y36fp1 v5+KArp4ZPhukYQa+BscPMCwf7ZlFxedr5DybLoDwiD6b3bYswWSql5AkMPeIyNQPpID 36lLl3n4swjAPTCZ4o4lIv1Yl7V41xd6W8t6IZQ7EQuVz8A8+8bGtiXDNsIGtxWdI6Iq 6CFA== X-Gm-Message-State: AO0yUKWEvPNm5KgDszNRtlzRKLHypaJkT6A7QtuerJS4HXvH1usYjBd4 QViLJuGKitFFQzH+33Z5rCPSCzNsLSniHBTq X-Google-Smtp-Source: AK7set9lBaAJL+NWDeMFPT0DOV3lSU8kLSWJhSbQWPcT2dJ58eh8ZTyBowQqiDEtt9dCXxT0WIePSQ== X-Received: by 2002:a05:6808:6087:b0:378:6da:6d4f with SMTP id de7-20020a056808608700b0037806da6d4fmr6023503oib.28.1677431123364; Sun, 26 Feb 2023 09:05:23 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, Daniel Henrique Barboza , Frank Chang Subject: [PATCH 1/2] target/riscv/vector_helper.c: create vext_set_tail_elems_1s() Date: Sun, 26 Feb 2023 14:05:13 -0300 Message-Id: <20230226170514.588071-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230226170514.588071-1-dbarboza@ventanamicro.com> References: <20230226170514.588071-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1677431184801100003 Content-Type: text/plain; charset="utf-8" Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector load / store instructions") added code to set the tail elements to 1 in the end of vext_ldst_stride(), vext_ldst_us(), vext_ldst_index() and vext_ldff(). Aside from a env->vl versus an evl value being used in the first loop, the code is being repeated 4 times. Create a helper to avoid code repetition in all those functions. Arguments that are used in the callers (nf, esz and max_elems) are passed as arguments. All other values are being derived inside the helper. Reviewed-by: Weiwei Li Reviewed-by: Frank Chang Signed-off-by: Daniel Henrique Barboza --- target/riscv/vector_helper.c | 86 +++++++++++++----------------------- 1 file changed, 30 insertions(+), 56 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 00de879787..7d2e3978f1 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -267,6 +267,28 @@ GEN_VEXT_ST_ELEM(ste_h, int16_t, H2, stw) GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl) GEN_VEXT_ST_ELEM(ste_d, int64_t, H8, stq) =20 +static void vext_set_tail_elems_1s(CPURISCVState *env, target_ulong vl, + void *vd, uint32_t desc, uint32_t nf, + uint32_t esz, uint32_t max_elems) +{ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; + uint32_t vta =3D vext_vta(desc); + uint32_t registers_used; + int k; + + for (k =3D 0; k < nf; ++k) { + vext_set_elems_1s(vd, vta, (k * max_elems + vl) * esz, + (k * max_elems + max_elems) * esz); + } + + if (nf * max_elems % total_elems !=3D 0) { + registers_used =3D ((nf * max_elems) * esz + (vlenb - 1)) / vlenb; + vext_set_elems_1s(vd, vta, (nf * max_elems) * esz, + registers_used * vlenb); + } +} + /* *** stride: access vector element from strided memory */ @@ -281,8 +303,6 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, uint32_t nf =3D vext_nf(desc); uint32_t max_elems =3D vext_max_elems(desc, log2_esz); uint32_t esz =3D 1 << log2_esz; - uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); - uint32_t vta =3D vext_vta(desc); uint32_t vma =3D vext_vma(desc); =20 for (i =3D env->vstart; i < env->vl; i++, env->vstart++) { @@ -301,18 +321,8 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, } } env->vstart =3D 0; - /* set tail elements to 1s */ - for (k =3D 0; k < nf; ++k) { - vext_set_elems_1s(vd, vta, (k * max_elems + env->vl) * esz, - (k * max_elems + max_elems) * esz); - } - if (nf * max_elems % total_elems !=3D 0) { - uint32_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; - uint32_t registers_used =3D - ((nf * max_elems) * esz + (vlenb - 1)) / vlenb; - vext_set_elems_1s(vd, vta, (nf * max_elems) * esz, - registers_used * vlenb); - } + + vext_set_tail_elems_1s(env, env->vl, vd, desc, nf, esz, max_elems); } =20 #define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN) \ @@ -359,8 +369,6 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState= *env, uint32_t desc, uint32_t nf =3D vext_nf(desc); uint32_t max_elems =3D vext_max_elems(desc, log2_esz); uint32_t esz =3D 1 << log2_esz; - uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); - uint32_t vta =3D vext_vta(desc); =20 /* load bytes from guest memory */ for (i =3D env->vstart; i < evl; i++, env->vstart++) { @@ -372,18 +380,8 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVStat= e *env, uint32_t desc, } } env->vstart =3D 0; - /* set tail elements to 1s */ - for (k =3D 0; k < nf; ++k) { - vext_set_elems_1s(vd, vta, (k * max_elems + evl) * esz, - (k * max_elems + max_elems) * esz); - } - if (nf * max_elems % total_elems !=3D 0) { - uint32_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; - uint32_t registers_used =3D - ((nf * max_elems) * esz + (vlenb - 1)) / vlenb; - vext_set_elems_1s(vd, vta, (nf * max_elems) * esz, - registers_used * vlenb); - } + + vext_set_tail_elems_1s(env, evl, vd, desc, nf, esz, max_elems); } =20 /* @@ -484,8 +482,6 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, uint32_t vm =3D vext_vm(desc); uint32_t max_elems =3D vext_max_elems(desc, log2_esz); uint32_t esz =3D 1 << log2_esz; - uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); - uint32_t vta =3D vext_vta(desc); uint32_t vma =3D vext_vma(desc); =20 /* load bytes from guest memory */ @@ -505,18 +501,8 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, } } env->vstart =3D 0; - /* set tail elements to 1s */ - for (k =3D 0; k < nf; ++k) { - vext_set_elems_1s(vd, vta, (k * max_elems + env->vl) * esz, - (k * max_elems + max_elems) * esz); - } - if (nf * max_elems % total_elems !=3D 0) { - uint32_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; - uint32_t registers_used =3D - ((nf * max_elems) * esz + (vlenb - 1)) / vlenb; - vext_set_elems_1s(vd, vta, (nf * max_elems) * esz, - registers_used * vlenb); - } + + vext_set_tail_elems_1s(env, env->vl, vd, desc, nf, esz, max_elems); } =20 #define GEN_VEXT_LD_INDEX(NAME, ETYPE, INDEX_FN, LOAD_FN) = \ @@ -585,8 +571,6 @@ vext_ldff(void *vd, void *v0, target_ulong base, uint32_t vm =3D vext_vm(desc); uint32_t max_elems =3D vext_max_elems(desc, log2_esz); uint32_t esz =3D 1 << log2_esz; - uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); - uint32_t vta =3D vext_vta(desc); uint32_t vma =3D vext_vma(desc); target_ulong addr, offset, remain; =20 @@ -647,18 +631,8 @@ ProbeSuccess: } } env->vstart =3D 0; - /* set tail elements to 1s */ - for (k =3D 0; k < nf; ++k) { - vext_set_elems_1s(vd, vta, (k * max_elems + env->vl) * esz, - (k * max_elems + max_elems) * esz); - } - if (nf * max_elems % total_elems !=3D 0) { - uint32_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; - uint32_t registers_used =3D - ((nf * max_elems) * esz + (vlenb - 1)) / vlenb; - vext_set_elems_1s(vd, vta, (nf * max_elems) * esz, - registers_used * vlenb); - } + + vext_set_tail_elems_1s(env, env->vl, vd, desc, nf, esz, max_elems); } =20 #define GEN_VEXT_LDFF(NAME, ETYPE, LOAD_FN) \ --=20 2.39.2 From nobody Sun May 19 00:17:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1677431173; cv=none; d=zohomail.com; s=zohoarc; b=GFpc4v9vQeMHAQgIKlRG8EqhuH1+CpCUxs3ArYwGpsSrQlZjnU0H/mpt6/LfW0J9HAy7uxllBV0bFSj0xbgaA/mpz9ed1vSyOxR6IJ+P9ZzQ9TWlViaBignpqLgFtxW8NN8CezP1D9ZbqBtnTNfnMli0kwlueYzqTqachRFKgpI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677431173; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=swJuKWdeVhFHYkb694oGvFxPgjTud+ZVJxPB7OT3+aU=; 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([189.110.112.117]) by smtp.gmail.com with ESMTPSA id n83-20020acaef56000000b00383b8011881sm2142406oih.18.2023.02.26.09.05.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 09:05:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=swJuKWdeVhFHYkb694oGvFxPgjTud+ZVJxPB7OT3+aU=; b=I2vHLO0/JgYI1BIED176ZgQ7+SOvYRPTb4WCRqpEmyViWjhW7L42CaHisrl3pKC94D 0bpM84E6DHv8WbtM+PwkWJQCyWVV2fp0Ahg8plBcJEHiBu3u/pwc5Fx0J2YyD9HS1fRA t1zF1SNWDgXx9/vYE5s0COlGbqt4N1v9XJL7x0B9DFMcNDL1stb4v2Ovw/27cyn9sYl9 79fu/kjLqiJGZ7yqlDY6Ez41M1zICm1JIMwbV6FlBz724nImImhUzUrZz7u8tJIu90PZ ce7BEBaJ1Eq6iw1znoRKSL7i0U4bdaoYswbgAb/d5TqU4vuX0OfuIjZZAGKFTgiI72sz 1W3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=swJuKWdeVhFHYkb694oGvFxPgjTud+ZVJxPB7OT3+aU=; b=IPihbAqVaBnZRSJF+I+5/NOVJRmcs0PdWRcrK30g+JTpDupr892Qka6yU4Uga3GcDu SExr5+H0G/Dn+8+EUTJ1HjBCAPMCms5v1rUZCsYSUccXU0HYCh5b/A5EOc8rEeAFGNEm uFNcFK8XkiKTgLxen/0MDlD6hrOr7IfXZdaOc6L8hEb0bwZvOHOQUcPXT0NOY7NwWFe4 lxC3YFbDo5xYsJbGijFw0DPqEnFC7aBFpzXzwg06VJOVHhWvcH23gz+jPRHabc9uDBcC vFQNNVdZ8k65nbujuOLacA16jwqiBgyvh19tVtBps07/dgDC7Y0MzBY2ilyrZU/0Fv/I XUrA== X-Gm-Message-State: AO0yUKVX0r1CNbUyLE+lH4V+oc+DWu5CXTFFaB8B61wbXjbF/u2G3Qu+ g7Jm5ZXmY2q4bbmP6sHZRD8D3XcMm/iWaCWY X-Google-Smtp-Source: AK7set+XnMZd9Pv0CtBIT2OMeKBIsHyhXCz1nP0nI4ZDeLNIxLHjT8rDCg5MoATjWFc2WYICeasqRg== X-Received: by 2002:a05:6808:4294:b0:37f:b041:b6ee with SMTP id dq20-20020a056808429400b0037fb041b6eemr6781294oib.16.1677431126366; Sun, 26 Feb 2023 09:05:26 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, Daniel Henrique Barboza Subject: [PATCH 2/2] target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig Date: Sun, 26 Feb 2023 14:05:14 -0300 Message-Id: <20230226170514.588071-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230226170514.588071-1-dbarboza@ventanamicro.com> References: <20230226170514.588071-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1677431175133100003 Content-Type: text/plain; charset="utf-8" This file has several uses of env_archcpu() that are used solely to read cfg->vlen. Use the new riscv_cpu_cfg() inline instead. Suggested-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Weiwei Li --- target/riscv/vector_helper.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 7d2e3978f1..a7fb09efa3 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -272,7 +272,7 @@ static void vext_set_tail_elems_1s(CPURISCVState *env, = target_ulong vl, uint32_t esz, uint32_t max_elems) { uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); - uint32_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; + uint32_t vlenb =3D riscv_cpu_cfg(env)->vlen >> 3; uint32_t vta =3D vext_vta(desc); uint32_t registers_used; int k; @@ -671,7 +671,7 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVSt= ate *env, uint32_t desc, { uint32_t i, k, off, pos; uint32_t nf =3D vext_nf(desc); - uint32_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; + uint32_t vlenb =3D riscv_cpu_cfg(env)->vlen >> 3; uint32_t max_elems =3D vlenb >> log2_esz; =20 k =3D env->vstart / max_elems; @@ -1141,7 +1141,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ { \ uint32_t vl =3D env->vl; \ uint32_t vm =3D vext_vm(desc); \ - uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; \ + uint32_t total_elems =3D riscv_cpu_cfg(env)->vlen; \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ uint32_t i; \ \ @@ -1177,7 +1177,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , \ { \ uint32_t vl =3D env->vl; \ uint32_t vm =3D vext_vm(desc); \ - uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; \ + uint32_t total_elems =3D riscv_cpu_cfg(env)->vlen; \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ uint32_t i; \ \ @@ -1376,7 +1376,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ { \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ - uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; \ + uint32_t total_elems =3D riscv_cpu_cfg(env)->vlen; \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ @@ -1439,7 +1439,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ { \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ - uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; \ + uint32_t total_elems =3D riscv_cpu_cfg(env)->vlen; \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ @@ -4152,7 +4152,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ { \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ - uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; \ + uint32_t total_elems =3D riscv_cpu_cfg(env)->vlen; \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ @@ -4190,7 +4190,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, vo= id *vs2, \ { \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ - uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; \ + uint32_t total_elems =3D riscv_cpu_cfg(env)->vlen; \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ @@ -4721,7 +4721,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t desc) \ { \ uint32_t vl =3D env->vl; \ - uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; \ + uint32_t total_elems =3D riscv_cpu_cfg(env)->vlen; \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ uint32_t i; \ int a, b; \ @@ -4808,7 +4808,7 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPU= RISCVState *env, { uint32_t vm =3D vext_vm(desc); uint32_t vl =3D env->vl; - uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; + uint32_t total_elems =3D riscv_cpu_cfg(env)->vlen; uint32_t vta_all_1s =3D vext_vta_all_1s(desc); uint32_t vma =3D vext_vma(desc); int i; --=20 2.39.2