target/riscv: Add support for Svadu extension

[PATCH 0/6] target/riscv: Add support for Svadu extension

Weiwei Li posted 6 patches 1 year, 2 months ago

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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20230224040852.37109-1-liweiwei@iscas.ac.cn

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>

target/riscv/cpu.c        |  8 ++++++++
target/riscv/cpu.h        |  1 +
target/riscv/cpu_bits.h   |  4 ++++
target/riscv/cpu_helper.c | 16 ++++++++++++++--
target/riscv/csr.c        | 26 ++++++++++++++++++++------
5 files changed, 47 insertions(+), 8 deletions(-)

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[PATCH 0/6] target/riscv: Add support for Svadu extension

Posted by Weiwei Li 1 year, 2 months ago

This patchset adds support svadu extension. It also fixes some relationship between *envcfg fields and Svpbmt/Sstc extensions.

Specification for Svadu extension can be found in:

https://github.com/riscv/riscv-svadu

The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-svadu-upstream

Weiwei Li (6):
  target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and
    Svpbmt/Sstc extensions
  target/riscv: Fix the relationship of PBMTE/STCE fields between
    menvcfg and henvcfg
  target/riscv: Add csr support for svadu
  target/riscv: Add *envcfg.PBMTE related check in address translation
  target/riscv: Add *envcfg.HADE related check in address translation
  target/riscv: Export Svadu property

 target/riscv/cpu.c        |  8 ++++++++
 target/riscv/cpu.h        |  1 +
 target/riscv/cpu_bits.h   |  4 ++++
 target/riscv/cpu_helper.c | 16 ++++++++++++++--
 target/riscv/csr.c        | 26 ++++++++++++++++++++------
 5 files changed, 47 insertions(+), 8 deletions(-)

-- 
2.25.1

Re: [PATCH 0/6] target/riscv: Add support for Svadu extension

Posted by Palmer Dabbelt 1 year, 1 month ago

On Thu, 23 Feb 2023 20:08:46 PST (-0800), liweiwei@iscas.ac.cn wrote:
> This patchset adds support svadu extension. It also fixes some relationship between *envcfg fields and Svpbmt/Sstc extensions.
>
> Specification for Svadu extension can be found in:
>
> https://github.com/riscv/riscv-svadu
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-svadu-upstream
>
> Weiwei Li (6):
>   target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and
>     Svpbmt/Sstc extensions
>   target/riscv: Fix the relationship of PBMTE/STCE fields between
>     menvcfg and henvcfg
>   target/riscv: Add csr support for svadu
>   target/riscv: Add *envcfg.PBMTE related check in address translation
>   target/riscv: Add *envcfg.HADE related check in address translation
>   target/riscv: Export Svadu property
>
>  target/riscv/cpu.c        |  8 ++++++++
>  target/riscv/cpu.h        |  1 +
>  target/riscv/cpu_bits.h   |  4 ++++
>  target/riscv/cpu_helper.c | 16 ++++++++++++++--
>  target/riscv/csr.c        | 26 ++++++++++++++++++++------
>  5 files changed, 47 insertions(+), 8 deletions(-)

Thanks, this is queued up on riscv-to-apply.next .