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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033426081100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 12b1082537..7a2f804aeb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2426,6 +2426,9 @@ static inline bool arm_is_el3_or_mon(CPUARMState *env) /* Return true if the processor is in secure state */ static inline bool arm_is_secure(CPUARMState *env) { + if (arm_feature(env, ARM_FEATURE_M)) { + return env->v7m.secure; + } if (arm_is_el3_or_mon(env)) { return true; } --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677033274; cv=none; d=zohomail.com; s=zohoarc; b=BvrXaGog+K++R1ZVbS4lNcpdMnwkktJND/vosc+UKy5sOTnDzCpteWfcJfizf+9snNi1ByxFHeGirrsBhGapTctM4bsrdAyNK4tsxqtWvJ3wTNxtauZq7uNiPummabWIVlzI196OWi+ZszgJ5NudQj25WQTXh0JKSrAHSDIODUg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677033274; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LyJ1TFoD8DKR6NPPurEInLjBprHxsrJkr+brbjdIpWE=; b=kyM8U+N8PBUFUlRw3GOspV7K861ZYZ5zwqH+DOI7F6BDRCq9o5hKGbXqeb0QtpoKoxMTu42idRphJhu6GjWxog2HFrAcPBct83GW3USnbnAAoggDy8lcLCmIQQKQDmLOaXvrYI2ZovqQXsIqVbfhX6ArwQasIP/i3pUVXTYCgno= ARC-Authentication-Results: i=1; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LyJ1TFoD8DKR6NPPurEInLjBprHxsrJkr+brbjdIpWE=; b=KoYka+m3MnB3Dh407pkL/LSp1/Yj40RAX6G8yCRm/DMOmXJXvS0Bo+ObKisZUrmQqM 651KugXF3JOFzOnuXCp52oAU23Vcl5BD6z0tjx9iuOy7blx+igbxbvOu4BlbaGP74lMY bV0WYRtkN6Kv27c7sR8eH6/Cr8f4hSvH5aquKMX8j3TvXtUEnQ45zsG7bvk7iFzoXplO RIk85Rf3ok1sTkx0iPDnGkwjzW1HCWCnHEoHrkOMFJjbTrmQTyY+6uZw95vHvvaIkdMR /CqFPy3kWSWgSzwuClyzHlWj7IQTp7bVRlBXfHS9bIiQ8IIL0bFh1W2zaarEWKQnWTo8 83TA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LyJ1TFoD8DKR6NPPurEInLjBprHxsrJkr+brbjdIpWE=; b=oEY5xIVf/lKEgLiJn+CtMgMo2XQpPsRoNJYlDWts/SnQwIQi5XY9an/cU10hYIsqt3 lGb+ep2U5sdL6IQKRH0KQzD+ZZZdFhn7UEKMj0fvTU4Lw/rhSIS5yYTQSc6T6tV0Rjp2 g3wkMJSIFfOzUWhflrmYJ0mKS6VM1/lefVdW8RWdNNpTZ3LxZD3Mg38Lkyi3HawFuuxU Nvk5ghZu7nsg6C3mDW0bFRvssLjDnX5AoepRsf+W8orGRiI45in88ZErCe8ti+Gwz0ae YCG40b8xeeRNId0I8CKIeh7+sxleWP5hr8iYgukMyzX22sS5pBBeR8PCWbdA8Pix5N7S Wj2w== X-Gm-Message-State: AO0yUKXO+t7hG5zZ5ZZHCDoe/bH+r2vo2U7z9YMb1Nt86WQ6acqqcIeN AmeEnJQpuL6Qt+n51jcc0OCFC/D8bRfaxzmycv0= X-Google-Smtp-Source: AK7set8+Uu0Mb+UMQmpNtl4S/TumEjebIttJrniVHnMSfrI+cuOSkkQbXYe1BhDoUnwmrYzvOTYJWg== X-Received: by 2002:a17:902:f60e:b0:19a:aaac:f4d1 with SMTP id n14-20020a170902f60e00b0019aaaacf4d1mr6007893plg.13.1677033222242; Tue, 21 Feb 2023 18:33:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 02/25] target/arm: Stub arm_hcr_el2_eff for m-profile Date: Tue, 21 Feb 2023 16:33:13 -1000 Message-Id: <20230222023336.915045-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033275765100009 Content-Type: text/plain; charset="utf-8" M-profile doesn't have HCR_EL2. While we could test features before each call, zero is a generally safe return value to disable the code in the caller. This test is required to avoid an assert in arm_is_secure_below_el3. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 07d4100365..37d9267fb4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5788,6 +5788,9 @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, b= ool secure) =20 uint64_t arm_hcr_el2_eff(CPUARMState *env) { + if (arm_feature(env, ARM_FEATURE_M)) { + return 0; + } return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env)); } =20 --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677033274; cv=none; d=zohomail.com; s=zohoarc; b=NerYxPeEG0pLVodMGrOIlfPbdJuTIKpkXRRb9gzdy+QAEiKb2XHYvS/2GpwIov/BESkaKVpaov5E4g9whm3VBDMedJMNbP3lg0AC0ZTtCUjGtiMBEd3Fv9n9imgFi2Ouvd6Sr674mZ5nReVc24YxswReeZhqBc+kOFCNiT32JGM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677033274; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=t0f34z6IL5G95kj5EqfJsxy6GdEQaM54Gjt8GKtIdDA=; b=f2XjkNzBvzRz1ANEB7cvCJLQzj+xU9/7AAyCAZ+t+uh85QK9vQ9hzY5LMz+aGU+6JYOkvKt//mYhX1awvNEW4mLduk7Sk+zHtmtfjnMmg/6vJ6CEqoTIYKrq81LHsooWMoVAJH71cnmPOqdZM5l+LpLJ74G7pf0A7CeGHPxcH8Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677033274054699.1909324759715; Tue, 21 Feb 2023 18:34:34 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pUexL-0007Nj-Ga; Tue, 21 Feb 2023 21:34:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pUex2-0007If-01 for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:33:50 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pUewy-0001Xy-WC for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:33:47 -0500 Received: by mail-pl1-x62a.google.com with SMTP id c1so7463488plg.4 for ; Tue, 21 Feb 2023 18:33:44 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=t0f34z6IL5G95kj5EqfJsxy6GdEQaM54Gjt8GKtIdDA=; b=AuC22R+l7H/gFLprHvlABcs5KoaOKiHdp+Ft4gk3lknEB7S+hchsvMCpsKVh936Rvq 7EFm9e1PpCW8CljkqeknlkvxlT1tKVvkw8d73T/vlUyRsHRRX3I2DC4dQfpPtPGBg7Bz QVLFuTOXYcCpNHnJt7kIEIaF3+/IkSR65lWhRCXhZNHSsTqV91QgK/uCmzWYxOIZcvD0 1w25ABthNL2dkFv/iKZAQR9HJSEx9oI4PefRzSPFBmPyHAdR1LZUZez5Mjo4qBQOVJY8 vMuj9BHGD7sT/qdpWKAaiYAHIVuJUg/stNS51pKstR8gxVRchfD33QJmpm/O1+tdaPn1 W64g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t0f34z6IL5G95kj5EqfJsxy6GdEQaM54Gjt8GKtIdDA=; b=e6NJwJ2J56TNuiICX/HyLWi1Hd9S1WhJg9wdn8SEo0ZeltDVtrn1pJdWju2+BSfJRh n2AObDYQ7dwd4SaY95oPtkC1VFiS/Znq566xxi61zw0hRYiGAPe7arjkkVtVsxTm6mHD BqqnbIC+BqBCW2qVjSd1Jz6DgcL5/VHhjB3wIUGL1mcFU3p5n6Dq73TG/w7ifTlyl9M/ d7fr1kAyYsL6k0vkuPMTsZJDQ5aaWzP3pwGlwcsHoltky0vLyBk9iyUEo0ZIumoHiYgx ySjiCnZk9xQHSz7Az/SFZo1JjOAKPb4YZTX7XZTup065D0z4wpIt7aPDb/ek1dGYRWvp ECuw== X-Gm-Message-State: AO0yUKUJEdBltWu7l1lPttf+61HUt/dTPfztMgOAVJ8W4Bc7snPyslNB gTJeviWtlSECSA4c48wJ0WS3h/2YVSSX48A5RH0= X-Google-Smtp-Source: AK7set/9o9LgpS4PYvz3W0SQyLyix60OpPn9GUj19itKlZLn8Scsj7Qps/Jin+Bv4zLxRUQYXnL0UQ== X-Received: by 2002:a17:903:1d2:b0:19a:a815:2868 with SMTP id e18-20020a17090301d200b0019aa8152868mr7401408plh.44.1677033223575; Tue, 21 Feb 2023 18:33:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 03/25] target/arm: Diagnose incorrect usage of arm_is_secure subroutines Date: Tue, 21 Feb 2023 16:33:14 -1000 Message-Id: <20230222023336.915045-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033275732100007 Content-Type: text/plain; charset="utf-8" In several places we use arm_is_secure_below_el3 and arm_is_el3_or_mon separately from arm_is_secure. These functions make no sense for m-profile, and would indicate prior incorrect feature testing. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7a2f804aeb..cb4e405f04 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2389,7 +2389,8 @@ static inline int arm_feature(CPUARMState *env, int f= eature) void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); =20 #if !defined(CONFIG_USER_ONLY) -/* Return true if exception levels below EL3 are in secure state, +/* + * Return true if exception levels below EL3 are in secure state, * or would be following an exception return to that level. * Unlike arm_is_secure() (which is always a question about the * _current_ state of the CPU) this doesn't care about the current @@ -2397,6 +2398,7 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **e= rrp); */ static inline bool arm_is_secure_below_el3(CPUARMState *env) { + assert(!arm_feature(env, ARM_FEATURE_M)); if (arm_feature(env, ARM_FEATURE_EL3)) { return !(env->cp15.scr_el3 & SCR_NS); } else { @@ -2410,6 +2412,7 @@ static inline bool arm_is_secure_below_el3(CPUARMStat= e *env) /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ static inline bool arm_is_el3_or_mon(CPUARMState *env) { + assert(!arm_feature(env, ARM_FEATURE_M)); if (arm_feature(env, ARM_FEATURE_EL3)) { if (is_a64(env) && extract32(env->pstate, 2, 2) =3D=3D 3) { /* CPU currently in AArch64 state and EL3 */ --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677033533; cv=none; d=zohomail.com; s=zohoarc; b=mxoMTnqwfHjIJ/Xq/zUnoOxrLhUcx6bL4hX+7lJpdAJvQVkO5BfioJeWf/HHZLKzZclFoEdGKBdm+K/jPYsGYjrnJoCEEmOFSxW1xDzNjpISC6fiTVwoqAYZ3uirUShSOd3EF9WZ1Q1o/5nyNpz0pTKOTdq0cKbw0MIH0fMJxiU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677033533; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Hddjs2iU8lgJmQnwAvhIIZw97YOfc6Ski+WodJ2W4+A=; b=ReiurPeGEobguvvfy1WAI9mdqDZg4sUg4cBlDcSK1uvGMy7a+OCmXjWdcIEQea+VgtnHVZFguPg9sYmfk0HerNI1rdNCPrSE4sS24ElZo4NOLybLvrzzIN7KQ5oY1OWeUvVH1/kqo716y35A6u3EagNS3qtUR1GEPSrt+ToDOhQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677033533109834.0038190058452; Tue, 21 Feb 2023 18:38:53 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pUexO-0007We-F2; Tue, 21 Feb 2023 21:34:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pUex2-0007JA-E9 for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:33:50 -0500 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pUex0-0001XJ-Ae for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:33:48 -0500 Received: by mail-pl1-x643.google.com with SMTP id e5so8270990plg.8 for ; Tue, 21 Feb 2023 18:33:45 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hddjs2iU8lgJmQnwAvhIIZw97YOfc6Ski+WodJ2W4+A=; b=SROkWP7xABQfwPhAkR5n+ne6j8I64FnaMwmyfz2VxyA0+hwBBVFXdFZzyWAuWXXhLU 2VNufgp8zyZ4SbTjlvnP2s2Y4pcSl0OfD+Kctvg+SdGsZJQmawFVPeyIcPYDAXJy2W5A Y/O6iEa0AaL08H0YdicxgTpOIXtzUqI2VUb+hzdznxMWxL2eFveayOiI1qE5hcbI1ECQ k1caLhiEUZmpS4gjnS/L2zFiPGEI0m8nNNoa9sXqoS1ubnVej94BRiV64kP69w+msN1X 39d69W+OLXlc87cBWEVWuWcTpCTYIKo8L6JMemyUemKM4vbCajr1KTyyK2Doj5PB3Gn0 bwPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hddjs2iU8lgJmQnwAvhIIZw97YOfc6Ski+WodJ2W4+A=; b=uPhMIhe8ccHZfeqRWbLGeNP7ey2RBalQkJe4wyXnXwVJmzrqu9Tub83NptQbLNz0ye 4HKO+IxOGrdPRfPER0/zT3GgSJflDMtvbc1ANVC7lT2TWYZtZ6ZJ20TyTOKxF1TOMMWi 0CXheQ1uNTBv5egahrzsmTtLlzREiBt4FZ6q6pQdGp24g/9JEbruf0+/MbVtvfToUkN0 g4wyLlcVr1HH931FOGf0vuzooDCQthGZmBc7azvuwlWLTTnLmmYvA/qsOO2vJbqlP9pY AADvtRVATlOtHd25ljAYPhwVUvyVCyvtPmazR4WAb5zCORL1n/DbTvRgoICLDN2KHZQy UGwg== X-Gm-Message-State: AO0yUKXITKNFD30X1BZuZ44Fcwvaqd2LOnaPLqtkxFZpsNSkta7J+WYM u+ApCOaNe713vH5hn1+ufqizHbt4cHysFfyl0HX9Lw== X-Google-Smtp-Source: AK7set+PF6dIDEnjvBpJAzYc6J0LCD26OQuaXdXsImCAo8Lzr/JjGXfvQp0EO7teGPCrh5eQohsz0g== X-Received: by 2002:a17:902:f68e:b0:196:7bfb:f0d1 with SMTP id l14-20020a170902f68e00b001967bfbf0d1mr10084978plg.34.1677033225221; Tue, 21 Feb 2023 18:33:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 04/25] target/arm: Rewrite check_s2_mmu_setup Date: Tue, 21 Feb 2023 16:33:15 -1000 Message-Id: <20230222023336.915045-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x643.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033534594100001 Content-Type: text/plain; charset="utf-8" Integrate neighboring code from get_phys_addr_lpae which computed starting level, as it is easier to validate when doing both at the same time. Mirror the checks at the start of AArch{64,32}.S2Walk, especially S2InvalidSL and S2InconsistentSL. This reverts 49ba115bb74, which was incorrect -- there is nothing in the ARM pseudocode that depends on TxSZ, i.e. outputsize; the pseudocode is consistent in referencing PAMax. Fixes: 49ba115bb74 ("target/arm: Pass outputsize down to check_s2_mmu_setup= ") Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 173 ++++++++++++++++++++++++++--------------------- 1 file changed, 97 insertions(+), 76 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 2b125fff44..6fb72fb086 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1077,70 +1077,119 @@ static ARMVAParameters aa32_va_parameters(CPUARMSt= ate *env, uint32_t va, * check_s2_mmu_setup * @cpu: ARMCPU * @is_aa64: True if the translation regime is in AArch64 state - * @startlevel: Suggested starting level - * @inputsize: Bitsize of IPAs + * @tcr: VTCR_EL2 or VSTCR_EL2 + * @ds: Effective value of TCR.DS. + * @iasize: Bitsize of IPAs * @stride: Page-table stride (See the ARM ARM) * - * Returns true if the suggested S2 translation parameters are OK and - * false otherwise. + * Decode the starting level of the S2 lookup, returning INT_MIN if + * the configuration is invalid. */ -static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, - int inputsize, int stride, int outputsize) +static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr, + bool ds, int iasize, int stride) { - const int grainsize =3D stride + 3; - int startsizecheck; - - /* - * Negative levels are usually not allowed... - * Except for FEAT_LPA2, 4k page table, 52-bit address space, which - * begins with level -1. Note that previous feature tests will have - * eliminated this combination if it is not enabled. - */ - if (level < (inputsize =3D=3D 52 && stride =3D=3D 9 ? -1 : 0)) { - return false; - } - - startsizecheck =3D inputsize - ((3 - level) * stride + grainsize); - if (startsizecheck < 1 || startsizecheck > stride + 4) { - return false; - } + int sl0, sl2, startlevel, granulebits, levels; + int s1_min_iasize, s1_max_iasize; =20 + sl0 =3D extract32(tcr, 6, 2); if (is_aa64) { + /* + * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of + * get_phys_addr_lpae, that used aa64_va_parameters which apply + * to aarch64. If Stage1 is aarch32, the min_txsz is larger. + * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to + * inputsize is 64 - 24 =3D 40. + */ + if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) { + goto fail; + } + + /* + * AArch64.S2InvalidSL: Interpretation of SL depends on the page s= ize, + * so interleave AArch64.S2StartLevel. + */ switch (stride) { - case 13: /* 64KB Pages. */ - if (level =3D=3D 0 || (level =3D=3D 1 && outputsize <=3D 42)) { - return false; + case 9: /* 4KB */ + /* SL2 is RES0 unless DS=3D1 & 4KB granule. */ + sl2 =3D extract64(tcr, 33, 1); + if (ds && sl2) { + if (sl0 !=3D 0) { + goto fail; + } + startlevel =3D -1; + } else { + startlevel =3D 2 - sl0; + switch (sl0) { + case 2: + if (arm_pamax(cpu) < 44) { + goto fail; + } + break; + case 3: + if (!cpu_isar_feature(aa64_st, cpu)) { + goto fail; + } + startlevel =3D 3; + break; + } } break; - case 11: /* 16KB Pages. */ - if (level =3D=3D 0 || (level =3D=3D 1 && outputsize <=3D 40)) { - return false; + case 11: /* 16KB */ + switch (sl0) { + case 2: + if (arm_pamax(cpu) < 42) { + goto fail; + } + break; + case 3: + if (!ds) { + goto fail; + } + break; } + startlevel =3D 3 - sl0; break; - case 9: /* 4KB Pages. */ - if (level =3D=3D 0 && outputsize <=3D 42) { - return false; + case 13: /* 64KB */ + switch (sl0) { + case 2: + if (arm_pamax(cpu) < 44) { + goto fail; + } + break; + case 3: + goto fail; } + startlevel =3D 3 - sl0; break; default: g_assert_not_reached(); } - - /* Inputsize checks. */ - if (inputsize > outputsize && - (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) { - /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. = */ - return false; - } } else { - /* AArch32 only supports 4KB pages. Assert on that. */ + /* + * Things are simpler for AArch32 EL2, with only 4k pages. + * There is no separate S2InvalidSL function, but AArch32.S2Walk + * begins with walkparms.sl0 in {'1x'}. + */ assert(stride =3D=3D 9); - - if (level =3D=3D 0) { - return false; + if (sl0 >=3D 2) { + goto fail; } + startlevel =3D 2 - sl0; } - return true; + + /* AArch{64,32}.S2InconsistentSL are functionally equivalent. */ + levels =3D 3 - startlevel; + granulebits =3D stride + 3; + + s1_min_iasize =3D levels * stride + granulebits + 1; + s1_max_iasize =3D s1_min_iasize + (stride - 1) + 4; + + if (iasize >=3D s1_min_iasize && iasize <=3D s1_max_iasize) { + return startlevel; + } + + fail: + return INT_MIN; } =20 /** @@ -1296,38 +1345,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, */ level =3D 4 - (inputsize - 4) / stride; } else { - /* - * For stage 2 translations the starting level is specified by the - * VTCR_EL2.SL0 field (whose interpretation depends on the page si= ze) - */ - uint32_t sl0 =3D extract32(tcr, 6, 2); - uint32_t sl2 =3D extract64(tcr, 33, 1); - int32_t startlevel; - bool ok; - - /* SL2 is RES0 unless DS=3D1 & 4kb granule. */ - if (param.ds && stride =3D=3D 9 && sl2) { - if (sl0 !=3D 0) { - level =3D 0; - goto do_translation_fault; - } - startlevel =3D -1; - } else if (!aarch64 || stride =3D=3D 9) { - /* AArch32 or 4KB pages */ - startlevel =3D 2 - sl0; - - if (cpu_isar_feature(aa64_st, cpu)) { - startlevel &=3D 3; - } - } else { - /* 16KB or 64KB pages */ - startlevel =3D 3 - sl0; - } - - /* Check that the starting level is valid. */ - ok =3D check_s2_mmu_setup(cpu, aarch64, startlevel, - inputsize, stride, outputsize); - if (!ok) { + int startlevel =3D check_s2_mmu_setup(cpu, aarch64, tcr, param.ds, + inputsize, stride); + if (startlevel =3D=3D INT_MIN) { + level =3D 0; goto do_translation_fault; } level =3D startlevel; --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677033354; cv=none; d=zohomail.com; s=zohoarc; b=KeUWoYPcmMNIgPWZFX+SZLZKn/eEKX4PvxXKDgXUQL5Mti1d5zdrSFhQ5uK9C5Uq5AFGDD2CqeMxavK+gBP5V2qsBGxPub1plU63gGevnTbWsek2MCNTrDWvXtJmOXjsYPaYsVpwjVzvMhuNfM8vk/VlUAnhL9redAIiMfuU9Jc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677033354; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jhdYZZcA+QihWdoYLAkQ3l5owX/qDX7C/pLuLVYgynI=; b=NASNLPLZcp5rNl+e1LDiRlctKSbUtkb3GASaVGCnJ73ya+8eDr4LLqqvfw3KBXR7N/a7MDJHm5RnJOKTNFKhoXCdPtG8fxY+biJzeJ+mPR40z3dNpICyMQie2wcT+75cXTjloQMrQbyyebO/x9vQelHIFFm5ddfYUwS8oFQ0bYc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677033354201312.9088556736916; Tue, 21 Feb 2023 18:35:54 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pUexN-0007U7-1v; Tue, 21 Feb 2023 21:34:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pUex3-0007JH-GO for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:33:50 -0500 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pUex1-0001aS-Uo for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:33:49 -0500 Received: by mail-pj1-x1041.google.com with SMTP id pt11so7906699pjb.1 for ; Tue, 21 Feb 2023 18:33:47 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jhdYZZcA+QihWdoYLAkQ3l5owX/qDX7C/pLuLVYgynI=; b=sFuMbbqKDsHUnhkyXGAU36DJ5Z8J6UCbNI4zZrm/FEGgyBm8lXkxW30ErX5QoUWAiC Gh20cwwJFl76iDDcqbLRJ6Q8oErdAYhF00UhfBjUnvppAFvqXp1GsrnLx4No7yBVcZi0 6JIYFrGqo9/B/ZTDl8osPtF3IkJ8WA5PNWTgOduMjTY0RdTLp6PgqZEYQpya0LCx2Wqi GS+xTSWXpwjNkmXAJm7mGaXJ9pvmDSoqYR70wRhj18gkwkYk3lyyJYX93jDDkm1fJqxx Yw56EJWCx7nd4Nufjs9LVeCPdGSAXv6X7dTdPfWlpOJz3Kyzy5deEdR24B73+4TL8C9P b6xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jhdYZZcA+QihWdoYLAkQ3l5owX/qDX7C/pLuLVYgynI=; b=pFwud1eFFhcghnwiFyu9/uHEKniujuwipAY2vjSsmXPy3JHnxrh8m/dBjq3WC4up/X 01nCKEc1nHknmMLlJZPBbyix9oOGl2Lgs0u8RJCnN3GsGuN/4hQHYkMaIlES6bK2qN5f Gm8VZE6TDzXaTZO0FYKGetXiQJCugce9SPvP9uTgUjHJx6ENOX5jmwIkE4ZxEtJPdVif C9LkdTwDlKjaUYnCZVAFm4VU2OgL7AOXX4UzKH3ZOuShd0b711ptbim9ew2x6xJGiEZV bPKiyFY+aKB4MqfzMtbtYja7yC8rsOEwbKCZFlasDDpxStbXI93SRGiYA+BR6tivnq5Z zxkw== X-Gm-Message-State: AO0yUKWjJOPRnV3pubaiUPpoICfDGDT9UehlK+Jh9aNSM0JHLTqolZ77 zTXQon1ID6086MJL7Svx+xQB9pMtI23uC6KkyElk8g== X-Google-Smtp-Source: AK7set+QAmBsQiumlHst5jf/YQEf4Cg/vFpFdJ7dp9VU9zq3nWJDzYey6rhE4YKhl/Qu7YObqanDmg== X-Received: by 2002:a17:903:11cd:b0:19c:32a6:a362 with SMTP id q13-20020a17090311cd00b0019c32a6a362mr9723313plh.6.1677033226573; Tue, 21 Feb 2023 18:33:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 05/25] target/arm: Add isar_feature_aa64_rme Date: Tue, 21 Feb 2023 16:33:16 -1000 Message-Id: <20230222023336.915045-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033355798100001 Content-Type: text/plain; charset="utf-8" Add the missing field for ID_AA64PFR0, and the predicate. Disable it if EL3 is forced off by the board or command-line. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 6 ++++++ target/arm/cpu.c | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cb4e405f04..b046f96e4e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2190,6 +2190,7 @@ FIELD(ID_AA64PFR0, SEL2, 36, 4) FIELD(ID_AA64PFR0, MPAM, 40, 4) FIELD(ID_AA64PFR0, AMU, 44, 4) FIELD(ID_AA64PFR0, DIT, 48, 4) +FIELD(ID_AA64PFR0, RME, 52, 4) FIELD(ID_AA64PFR0, CSV2, 56, 4) FIELD(ID_AA64PFR0, CSV3, 60, 4) =20 @@ -3808,6 +3809,11 @@ static inline bool isar_feature_aa64_sel2(const ARMI= SARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) !=3D 0; } =20 +static inline bool isar_feature_aa64_rme(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) !=3D 0; +} + static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) !=3D 0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 876ab8f3bf..83685ed247 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1947,6 +1947,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSD= BG, 0); cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL3, 0); + + /* Disable the realm management extension, which requires EL3. */ + cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, RME, 0); } =20 if (!cpu->has_el2) { --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677033561; cv=none; d=zohomail.com; s=zohoarc; b=Ps4lZP0fq7tHPcIEMXFA9XMEpX2Ijz3evslpXEbdLnBU0nkCaqhssm0dRNYu6zre3lzBWoRd/svRWvXVILRtSNvvlZRecS1fdcgqhtqTR4Qq0FBNKV4MDAsd2EAt2nvdWhfBGWJUxVRs3uVK7AqxZ0kSGln+LM5C4W9/s0+h4LQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677033561; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KKaBXNzHKh4bdHhJlKN/7Fy/mzP8VfMexwZIdNSvfng=; b=ej86LIZuVnsfbDUPgiyldic3OL+5JoBpqzhesQ2xrpDO9hIpA/TdtYFpJgK7h6cd8hdQRwJObRrUiOIMrZfsJogo8F/ErQxRfWOiqap8Be4qWwTM9xDSyRVLj8bhCxDbNE3Se92289b9c03ar2YkePcBG06svfb69S3bBQ12wtg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677033561987236.37164739243042; Tue, 21 Feb 2023 18:39:21 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pUexO-0007Wd-Er; Tue, 21 Feb 2023 21:34:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pUex4-0007Ji-QE for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:33:55 -0500 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pUex3-0001az-98 for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:33:50 -0500 Received: by mail-pj1-x1032.google.com with SMTP id g14so7277439pjb.2 for ; Tue, 21 Feb 2023 18:33:48 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KKaBXNzHKh4bdHhJlKN/7Fy/mzP8VfMexwZIdNSvfng=; b=yncxQCT4inSEoDthgyE/SBkvxB32BvDmaE7dIfJPgEpiebJ25Y0xQggyDCtm0OGpDT FV0GQqtM9QB3YefHWbC/hWm2N0YetDG1ISMHYxYLgSKuwCUNpB0CeTd0DSqP+dFS/IPP ZbbsGwDfSOMPM5/f6QYOQYU3xY2M7GhgM5wAqZ7kt+Kv98WQ7LQA8YelMMJwTV5Ygn98 eQcCBO7GNm8NhUMtxOSe+32qKGv7m/Xay0xE/zbpNHr/1l7yAp1gXKG4h31SWZklBiOE G2F2G1kJrDB5b8PJOcbhhXgBYycjmXW6sU7jxiCgczELQK41MhLPDzbqD0wSVNwyQjlV JiEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KKaBXNzHKh4bdHhJlKN/7Fy/mzP8VfMexwZIdNSvfng=; b=5hSHdSdtUtegaiNVchZBHVD+D2f2M0fUtaurLo+KHWtfu6AmTmY/KuDTV5RKBnXcQ1 1WOt+ijjVsem/IRHfip2iXV7LWuAOEPTEg7h03M6YVJ20+vKD3+9XGvdO6AmvTtKw7Xd HSYc547tD5Dk4tpaF8VXPkwcWN0H2CHxnG6teq9bFQz8tzegVoJ7zTP7iI1fNYcWhfYv dmTK2uqM4rzoPeL3oGQrGpq9Tr2ZvVe81c1rfiTZh7sMUVISbJkW3OSnKn+E0ckxfKmU VD7hkrcrFLZgG3ibTHRP+WIC4bmtIR5fIHu+P/MHrTnv2Qt5PonSD+V3UtDKEUP2Ryoi IMbw== X-Gm-Message-State: AO0yUKXJtTwHRwQdklw3qjhfCA/y/72TdDeW94odVMJvbZFkKyj1oDwO X86GJHK8+QU7XrO+dyNPPPuoyBz+dBxBkAdT7JA= X-Google-Smtp-Source: AK7set8VXDB1CiwBp1SY6C9xJO5wgQ9WtdbFTnlTaljeyJ3tCFbwQ7a6NIOmTdfYj95pyM2c99boHw== X-Received: by 2002:a17:902:d481:b0:19a:a701:693f with SMTP id c1-20020a170902d48100b0019aa701693fmr9485203plg.9.1677033227966; Tue, 21 Feb 2023 18:33:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 06/25] target/arm: Update SCR and HCR for RME Date: Tue, 21 Feb 2023 16:33:17 -1000 Message-Id: <20230222023336.915045-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033562727100001 Content-Type: text/plain; charset="utf-8" Define the missing SCR and HCR bits, allow SCR_NSE and {SCR,HCR}_GPF to be set, and invalidate TLBs when NSE changes. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++-- target/arm/helper.c | 10 ++++++++-- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b046f96e4e..230241cf93 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1650,7 +1650,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define HCR_TERR (1ULL << 36) #define HCR_TEA (1ULL << 37) #define HCR_MIOCNCE (1ULL << 38) -/* RES0 bit 39 */ +#define HCR_TME (1ULL << 39) #define HCR_APK (1ULL << 40) #define HCR_API (1ULL << 41) #define HCR_NV (1ULL << 42) @@ -1659,7 +1659,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define HCR_NV2 (1ULL << 45) #define HCR_FWB (1ULL << 46) #define HCR_FIEN (1ULL << 47) -/* RES0 bit 48 */ +#define HCR_GPF (1ULL << 48) #define HCR_TID4 (1ULL << 49) #define HCR_TICAB (1ULL << 50) #define HCR_AMVOFFEN (1ULL << 51) @@ -1724,6 +1724,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) #define SCR_GPF (1ULL << 48) +#define SCR_NSE (1ULL << 62) =20 #define HSTR_TTEE (1 << 16) #define HSTR_TJDBX (1 << 17) diff --git a/target/arm/helper.c b/target/arm/helper.c index 37d9267fb4..3650234c73 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1875,6 +1875,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_fgt, cpu)) { valid_mask |=3D SCR_FGTEN; } + if (cpu_isar_feature(aa64_rme, cpu)) { + valid_mask |=3D SCR_NSE | SCR_GPF; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -1904,10 +1907,10 @@ static void scr_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) env->cp15.scr_el3 =3D value; =20 /* - * If SCR_EL3.NS changes, i.e. arm_is_secure_below_el3, then + * If SCR_EL3.{NS,NSE} changes, i.e. change of security state, * we must invalidate all TLBs below EL3. */ - if (changed & SCR_NS) { + if (changed & (SCR_NS | SCR_NSE)) { tlb_flush_by_mmuidx(env_cpu(env), (ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E10_1 | @@ -5655,6 +5658,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) if (cpu_isar_feature(aa64_fwb, cpu)) { valid_mask |=3D HCR_FWB; } + if (cpu_isar_feature(aa64_rme, cpu)) { + valid_mask |=3D HCR_GPF; + } } =20 if (cpu_isar_feature(any_evt, cpu)) { --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677033348; cv=none; d=zohomail.com; s=zohoarc; b=Lhj2tdcxfHLGM0Q0slw7Qiy696fMQKR2UbGHTcPzel3628LbunWR0QVCW7NERXbgq7Y5tV6WBFQ6ICwOCwsFm1cyaAjbxxDyu1SQ+NU2UhYHzNtn4JTEj3oItVSnouomdW+KRrmwTgy62TxrUAoJ4eLyzPqBlvsaxYctjQyxmqk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677033348; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eh6Hd17AKGFWk8yBVtARAQj9lZij9aVa5jyFKRWxRtQ=; b=kbsemD+Lug6Fi/0ugma7vio3aWXcNpIbKTzaAweOFVKKcYQgEow+k2F977pwr17E8lHOXQxcEnqZWyc/dyAIpvOCO4A2gKxkME8fFekS2bJj8GhwJFDrsQT7HZusUv+2qEp57z1qxsd6/IiTAAOWvRiRQ5s+BH/zCUVUf3XqKjk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677033348354105.73851489644767; Tue, 21 Feb 2023 18:35:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pUexP-0007Zd-Nk; Tue, 21 Feb 2023 21:34:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pUex6-0007Jy-51 for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:33:55 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pUex4-0001bT-MU for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:33:51 -0500 Received: by mail-pj1-x102b.google.com with SMTP id qi12-20020a17090b274c00b002341621377cso6969169pjb.2 for ; Tue, 21 Feb 2023 18:33:50 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eh6Hd17AKGFWk8yBVtARAQj9lZij9aVa5jyFKRWxRtQ=; b=TfPmPXGZysN96bsM6EUpb9vA4/oGjhgDcNfpnqvcf0aXTqa+LAflL68DYHumj/SCED 3TKYlpYwDyRuUU82kH2cMr+Zd5aYuvcJxZVIZqEo/ozIZQ8HxH3H/W/zojk9vTS6uM5Y 5+496PPOT1N27GKiFoxvMfeb/e9nbHCIqI90IDPYUJ7FX20Ge+KPc7QNhvM6FAXODn/Z iLAbIhX8H9i4Mp/ieSecEuCOtJ6kEOLVbVcZUe4+U3vmxJIMVDldfqC/pF8MDp2u1MMv Sdv998KI+vn7GVMhseZN3w9LNkCdlE56es/yVSVM4ZTmUcEfCDmUdc7jH2q82Qvgktuf +9pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eh6Hd17AKGFWk8yBVtARAQj9lZij9aVa5jyFKRWxRtQ=; b=RwoYZL9qMpaHU6c6RUhir0AoPIyMeBkdBIoOGxvkYbYfJPYrhHpZHw/6D/g/jIIk1u V5FgVrc1UF5mmgG6n2FyEFXyD+1boGwiNxh83zN1jyxYRNYac2jOCwWSQSFtSNpnYgZF PdvaMQ/bvkFawEVpdrdHWEa24oflum6MX2KHxnYe5TczD5PxR0TvAdKLoaKXQ5x4vkUi x6Q+if0zA26IB+kZrRl0Jn9TKgKTjy8iH8BF2cNJoPVLhkl/qr/WzF8Ni6FyzctsSO8O gG4meBp7l8w8u3FAPZlUbkhWOgYDLo72MbboH0O8WGnbghZa9Bosppk3jwX5+C//sVsx Kn3w== X-Gm-Message-State: AO0yUKViQwS5myo1tMLQCfbUoK91nxTRJyNvLF43c03hgdGWclANCR/r L96rgyPbIBJXnBGT5Y9Zrq9CU7NxAhTypSvq6iU= X-Google-Smtp-Source: AK7set/wVPROGO6CTRqRbRD/uZNkqtxA7DDBLiM4+vJa5couLmahcfO+8UcweL+AjqueJ/WoNN/mdg== X-Received: by 2002:a17:902:e545:b0:198:ec2c:d4e6 with SMTP id n5-20020a170902e54500b00198ec2cd4e6mr9377571plf.38.1677033229298; Tue, 21 Feb 2023 18:33:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 07/25] target/arm: SCR_EL3.NS may be RES1 Date: Tue, 21 Feb 2023 16:33:18 -1000 Message-Id: <20230222023336.915045-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033349735100001 Content-Type: text/plain; charset="utf-8" With RME, SEL2 must also be present to support secure state. The NS bit is RES1 if SEL2 is not present. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3650234c73..ae8b3f6a48 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1856,6 +1856,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) } if (cpu_isar_feature(aa64_sel2, cpu)) { valid_mask |=3D SCR_EEL2; + } else if (cpu_isar_feature(aa64_rme, cpu)) { + /* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */ + value |=3D SCR_NS; } if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |=3D SCR_ATA; --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677033310; cv=none; d=zohomail.com; s=zohoarc; b=KJIbE39VFwnDV+ybV7v9xvUdgz9OTsJ4JbhKbxZZMBsFJ0aNyvAqY7V92vEAaHehbgqqVgrjI3v5vAQUCGWd3wBy85CqCTEo61PPDT2UFeBfTddI+t/IYwFHEMr3qI0zSEEWgDjJjmNK21wgx+o6r5u15cZNxL8yWNxT3gDuWVQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677033310; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BxdGjf2oqnzrJHeRZJSywTpPyzmxqXK2LnQoNrr8F7g=; b=Fyesb7q4Z8Dzn+BB5OmWZbU6TH/mgLMCMSuSqZ/skaks6R4jAkQrLIzjx4jL7NXOS2GhS18aHdB4Cy23vfY6eAYHnX6ikwRDVqQhhVbVfDT57Ii9qQHaGx5yVvW8UmmsZLP2BenFShfgqoHeD2Vmn4O6ErFxl+ZlLDSSutkqWy8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677033310708694.044873962117; Tue, 21 Feb 2023 18:35:10 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pUexP-0007Zc-O7; Tue, 21 Feb 2023 21:34:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pUex8-0007KT-37 for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:33:55 -0500 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pUex6-0001cU-Ah for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:33:53 -0500 Received: by mail-pj1-x102f.google.com with SMTP id d1-20020a17090a3b0100b00229ca6a4636so7324057pjc.0 for ; Tue, 21 Feb 2023 18:33:51 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BxdGjf2oqnzrJHeRZJSywTpPyzmxqXK2LnQoNrr8F7g=; b=hSFH0qMYkVQ/qCWSDKNo6IZuZi+hiMsb6woGHdpGBHb9bfIYLzjxP9BlXU/MVWyJNT XiVl8w72fBFnbs/2OZzgr0PPdG/GAArgdOfany4RTizTQjmuIGJCTCcmr6/0QBuDH0Cb 3bI59LR7V9uWtRtXZoqyR6T7FzUAqudo/DRJHfrLn7xAP+0FrZM/GLEc2Q5P3+kJ2AjQ tiATiMTSNXw3lrny6QauYPomFSByTVi5yVnckg3u8YqmRFMXIC0jD2dmc7tIspRDjyx0 idU8ygn2ORlNVHeiubhtp7pxdg25OgdamPfoG+Lx5Jr0XWtN9llPNpGgRHapBfJE0t7r BRlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BxdGjf2oqnzrJHeRZJSywTpPyzmxqXK2LnQoNrr8F7g=; b=dOBtSNi/vy30VoZZDElzggfkQgtbN9gIpr/CWSzFN1iEl/lGRlGWAhqcA2Xaz8djtV giA9N17kZOBr+3mEFingAo1RhgnXfynE42Yd//7QMrbCOvyyzmHiAr5pKENv38SAiwsz WA+6mRriYBjyxzmqafvq8Bz342guzeO03HijGiia78GKHuZdWSQGZEuouNlkvE3EUaoa 17mYwISQW28NriMCOC3mF2LfEvCFNfexRxPO1YLahumudX48WhTvDzjFh/RHseHEbANB XF3FZKGrAwGKcP7wtLsAHNbC5IvDGHrwtIZyN2U3H4Y5s/Ayto2yk2/h5nat9vd1owhV li/A== X-Gm-Message-State: AO0yUKWI2I0VAeZBYefBp6mdHxCXGhnpwktxaNFM/72JkvMXnZ2jMmxx 1fYAz9x1L7oUuM3IwvAQp0KTJR6AAB0qwWR8BrU= X-Google-Smtp-Source: AK7set/14rmt3XnZppnGfUtWMQTaggw4RnsB4/BqWyHlYlxpCzHXWgguXTJV39f/3j3KatkL1nKFrw== X-Received: by 2002:a17:902:c40d:b0:19a:b312:bf3f with SMTP id k13-20020a170902c40d00b0019ab312bf3fmr11739291plk.47.1677033230638; Tue, 21 Feb 2023 18:33:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 08/25] target/arm: Add RME cpregs Date: Tue, 21 Feb 2023 16:33:19 -1000 Message-Id: <20230222023336.915045-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033311637100002 Content-Type: text/plain; charset="utf-8" This includes GPCCR, GPTBR, MFAR, the TLB flush insns PAALL, PAALLOS, RPALOS, RPAOS, and the cache flush insns CIPAPA and CIGDPAPA. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 19 +++++++++++ target/arm/helper.c | 83 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 230241cf93..8d18d98350 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -541,6 +541,11 @@ typedef struct CPUArchState { uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ uint64_t fgt_exec[1]; /* HFGITR */ + + /* RME registers */ + uint64_t gpccr_el3; + uint64_t gptbr_el3; + uint64_t mfar_el3; } cp15; =20 struct { @@ -1043,6 +1048,7 @@ struct ArchCPU { uint64_t reset_cbar; uint32_t reset_auxcr; bool reset_hivecs; + uint8_t reset_l0gptsz; =20 /* * Intermediate values used during property parsing. @@ -2336,6 +2342,19 @@ FIELD(MVFR1, SIMDFMAC, 28, 4) FIELD(MVFR2, SIMDMISC, 0, 4) FIELD(MVFR2, FPMISC, 4, 4) =20 +FIELD(GPCCR, PPS, 0, 3) +FIELD(GPCCR, IRGN, 8, 2) +FIELD(GPCCR, ORGN, 10, 2) +FIELD(GPCCR, SH, 12, 2) +FIELD(GPCCR, PGS, 14, 2) +FIELD(GPCCR, GPC, 16, 1) +FIELD(GPCCR, GPCP, 17, 1) +FIELD(GPCCR, L0GPTSZ, 20, 4) + +FIELD(MFAR, FPA, 12, 40) +FIELD(MFAR, NSE, 62, 1) +FIELD(MFAR, NS, 63, 1) + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=3D R_V7M_CSSELR_INDE= X_MASK); =20 /* If adding a feature bit which corresponds to a Linux ELF diff --git a/target/arm/helper.c b/target/arm/helper.c index ae8b3f6a48..eff109f83c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6935,6 +6935,83 @@ static const ARMCPRegInfo sme_reginfo[] =3D { .access =3D PL2_RW, .accessfn =3D access_esm, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; + +static void tlbi_aa64_paall_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + + tlb_flush(cs); +} + +static void gpccr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* L0GPTSZ is RO; other bits not mentioned are RES0. */ + uint64_t rw_mask =3D R_GPCCR_PPS_MASK | R_GPCCR_IRGN_MASK | + R_GPCCR_ORGN_MASK | R_GPCCR_SH_MASK | R_GPCCR_PGS_MASK | + R_GPCCR_GPC_MASK | R_GPCCR_GPCP_MASK; + + env->cp15.gpccr_el3 =3D (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw= _mask); +} + +static void gpccr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + env->cp15.gpccr_el3 =3D FIELD_DP64(0, GPCCR, L0GPTSZ, + env_archcpu(env)->reset_l0gptsz); +} + +static void tlbi_aa64_paallos_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + + tlb_flush_all_cpus_synced(cs); +} + +static const ARMCPRegInfo rme_reginfo[] =3D { + { .name =3D "GPCCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 6, + .access =3D PL3_RW, .writefn =3D gpccr_write, .resetfn =3D gpccr_res= et, + .fieldoffset =3D offsetof(CPUARMState, cp15.gpccr_el3) }, + { .name =3D "GPTBR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 4, + .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.gptb= r_el3) }, + { .name =3D "MFAR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 6, .crm =3D 0, .opc2 =3D 5, + .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mfar= _el3) }, + { .name =3D "TLBI_PAALL", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 4, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_paall_write }, + { .name =3D "TLBI_PAALLOS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 4, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_paallos_write }, + /* + * QEMU does not have a way to invalidate by physical address, thus + * invalidating a range of physical addresses is accomplished by + * flushing all tlb entries in the outer sharable domain, + * just like PAALLOS. + */ + { .name =3D "TLBI_RPALOS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 4, .opc2 =3D 7, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_paallos_write }, + { .name =3D "TLBI_RPAOS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 4, .opc2 =3D 3, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_paallos_write }, + { .name =3D "DC_CIPAPA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NOP }, +}; + +static const ARMCPRegInfo rme_mte_reginfo[] =3D { + { .name =3D "DC_CIGDPAPA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 14, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NOP }, +}; #endif /* TARGET_AARCH64 */ =20 static void define_pmu_regs(ARMCPU *cpu) @@ -9126,6 +9203,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_tlbios, cpu)) { define_arm_cp_regs(cpu, tlbios_reginfo); } + if (cpu_isar_feature(aa64_rme, cpu)) { + define_arm_cp_regs(cpu, rme_reginfo); + if (cpu_isar_feature(aa64_mte, cpu)) { + define_arm_cp_regs(cpu, rme_mte_reginfo); + } + } #ifndef CONFIG_USER_ONLY /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LCT/fSAV3XnG4vQxoADZTo0VUdiQb+WSD16G+rIZbRY=; b=pyy/9X+Av7g82uHRt7KodaVmZa36WGarxM/R3ow/7ZtUNUlCbcXE60WBoPyoqbnl3J 3ZcwtgdqSpEW2ouC+amzTDUFWy8a0SnZ1y1Wot6cYZwbSUebCOiG6jc9PTJ6GIOl1md5 eFbhRRuUoLrobdPqx3XcsbGS1wRUymTdV5d9BWtZqIl3/kvX4AzsUFsNIfuy66DdrTYe 2ZyFtDpfsqhTQEPjHKO2gmBda64EIP7M0nEB5MKPnpuvabbr7dtSRtYsMhuGkGj7x2KH phJhmco64BIqqctO34oH0NCZx3soJxhn3+aE+qCfoMTYHknnA9qR7zue6nH+uG2v2HPO 9aPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LCT/fSAV3XnG4vQxoADZTo0VUdiQb+WSD16G+rIZbRY=; b=TDEz6mbf4JqvyERf2d75ItHVPhIW8izWZcBQWYlczFxJ92trc44zJm4tkfE5zQCo5L J3lPyoII7lK37CLdB3hSVyZmMCwIMJjUKyhnBpqwajrRIsZXNfgOr36Svjn+FT6C0lN1 rmKs+AZhx87MpJbeeZauVJ5H4GnXA/WtD5c2KEcIgguuBdHKMjn2R0/cWE9q3PnYJQ2X 57GMjPYA4KXZZXU4RRjcKO8GywAmeCZoYJJdycfuWvpgkHtGxQs4Cq4sKz1WBgeo8ubR OaI0sOAVcXQm8Qt5wv0m3vmrr50YDrF6IcK5LDlD7QsmBCSsDTaXc/its65tL2O2x2zq 83UA== X-Gm-Message-State: AO0yUKXW1g1pDUZ6yhyU4VQMeyUSAW3vmkVqvKe/mlMLA7J1etTyIE9c DF7KNL9k1017xeTxfBWzdC7BNaMvFsmAkKwiFS0= X-Google-Smtp-Source: AK7set/pEXLkOdlpIvsKYkPrMrV3FUhQVfnRs/5V+dcAYM2A+KvUWKoHbeYWXGZULj9Ixs2zAAQYXw== X-Received: by 2002:a17:902:d2c3:b0:19a:80c9:2cd7 with SMTP id n3-20020a170902d2c300b0019a80c92cd7mr7661147plc.47.1677033232182; Tue, 21 Feb 2023 18:33:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 09/25] target/arm: Introduce ARMSecuritySpace Date: Tue, 21 Feb 2023 16:33:20 -1000 Message-Id: <20230222023336.915045-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033512423100001 Content-Type: text/plain; charset="utf-8" Introduce both the enumeration and functions to retrieve the current state, and state outside of EL3. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 89 ++++++++++++++++++++++++++++++++++----------- target/arm/helper.c | 60 ++++++++++++++++++++++++++++++ 2 files changed, 127 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8d18d98350..203a3e0046 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2409,25 +2409,53 @@ static inline int arm_feature(CPUARMState *env, int= feature) =20 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); =20 -#if !defined(CONFIG_USER_ONLY) /* + * ARM v9 security states. + * The ordering of the enumeration corresponds to the low 2 bits + * of the GPI value, and (except for Root) the concat of NSE:NS. + */ + +typedef enum ARMSecuritySpace { + ARMSS_Secure =3D 0, + ARMSS_NonSecure =3D 1, + ARMSS_Root =3D 2, + ARMSS_Realm =3D 3, +} ARMSecuritySpace; + +/* Return true if @space is secure, in the pre-v9 sense. */ +static inline bool arm_space_is_secure(ARMSecuritySpace space) +{ + return space =3D=3D ARMSS_Secure || space =3D=3D ARMSS_Root; +} + +/* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ +static inline ARMSecuritySpace arm_secure_to_space(bool secure) +{ + return secure ? ARMSS_Secure : ARMSS_NonSecure; +} + +#if !defined(CONFIG_USER_ONLY) +/** + * arm_security_space_below_el3: + * @env: cpu context + * + * Return the security space of exception levels below EL3, following + * an exception return to those levels. Unlike arm_security_space, + * this doesn't care about the current EL. + */ +ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); + +/** + * arm_is_secure_below_el3: + * @env: cpu context + * * Return true if exception levels below EL3 are in secure state, - * or would be following an exception return to that level. - * Unlike arm_is_secure() (which is always a question about the - * _current_ state of the CPU) this doesn't care about the current - * EL or mode. + * or would be following an exception return to those levels. */ static inline bool arm_is_secure_below_el3(CPUARMState *env) { - assert(!arm_feature(env, ARM_FEATURE_M)); - if (arm_feature(env, ARM_FEATURE_EL3)) { - return !(env->cp15.scr_el3 & SCR_NS); - } else { - /* If EL3 is not supported then the secure state is implementation - * defined, in which case QEMU defaults to non-secure. - */ - return false; - } + ARMSecuritySpace ss =3D arm_security_space_below_el3(env); + return ss =3D=3D ARMSS_Secure; } =20 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ @@ -2447,16 +2475,23 @@ static inline bool arm_is_el3_or_mon(CPUARMState *e= nv) return false; } =20 -/* Return true if the processor is in secure state */ +/** + * arm_security_space: + * @env: cpu context + * + * Return the current security space of the cpu. + */ +ARMSecuritySpace arm_security_space(CPUARMState *env); + +/** + * arm_is_secure: + * @env: cpu context + * + * Return true if the processor is in secure state. + */ static inline bool arm_is_secure(CPUARMState *env) { - if (arm_feature(env, ARM_FEATURE_M)) { - return env->v7m.secure; - } - if (arm_is_el3_or_mon(env)) { - return true; - } - return arm_is_secure_below_el3(env); + return arm_space_is_secure(arm_security_space(env)); } =20 /* @@ -2475,11 +2510,21 @@ static inline bool arm_is_el2_enabled(CPUARMState *= env) } =20 #else +static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *e= nv) +{ + return ARMSS_NonSecure; +} + static inline bool arm_is_secure_below_el3(CPUARMState *env) { return false; } =20 +static inline ARMSecuritySpace arm_security_space(CPUARMState *env) +{ + return ARMSS_NonSecure; +} + static inline bool arm_is_secure(CPUARMState *env) { return false; diff --git a/target/arm/helper.c b/target/arm/helper.c index eff109f83c..9e1c1ed6d8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12538,3 +12538,63 @@ void aarch64_sve_change_el(CPUARMState *env, int o= ld_el, } } #endif + +#ifndef CONFIG_USER_ONLY +ARMSecuritySpace arm_security_space(CPUARMState *env) +{ + if (arm_feature(env, ARM_FEATURE_M)) { + return arm_secure_to_space(env->v7m.secure); + } + + /* + * If EL3 is not supported then the secure state is implementation + * defined, in which case QEMU defaults to non-secure. + */ + if (!arm_feature(env, ARM_FEATURE_EL3)) { + return ARMSS_NonSecure; + } + + /* Check for AArch64 EL3 or AArch32 Mon. */ + if (is_a64(env)) { + if (extract32(env->pstate, 2, 2) =3D=3D 3) { + if (cpu_isar_feature(aa64_rme, env_archcpu(env))) { + return ARMSS_Root; + } else { + return ARMSS_Secure; + } + } + } else { + if ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_MON) { + return ARMSS_Secure; + } + } + + return arm_security_space_below_el3(env); +} + +ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) +{ + assert(!arm_feature(env, ARM_FEATURE_M)); + + /* + * If EL3 is not supported then the secure state is implementation + * defined, in which case QEMU defaults to non-secure. + */ + if (!arm_feature(env, ARM_FEATURE_EL3)) { + return ARMSS_NonSecure; + } + + /* + * Note NSE cannot be set without RME, and NSE & !NS is Reserved. + * Ignoring NSE when !NS retains consistency without having to + * modify other predicates. + */ + if (!(env->cp15.scr_el3 & SCR_NS)) { + return ARMSS_Secure; + } else if (env->cp15.scr_el3 & SCR_NSE) { + return ARMSS_Realm; + } else { + return ARMSS_NonSecure; + } +} +#endif /* !CONFIG_USER_ONLY */ --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0zAr88doy4l35/U8kOUIKFNAL46N655Bwwt/mOy9kK4=; b=vAE0hyoLpcAzZ+66jQHG/RI//FDINCq6r7xYdlYqWVeK/KErV1uSa5x5YR+dsSC7ti K1ZaAmZvUUo1lvDa9es7zsZePW743U3IVZvYMJhT+a6dzzoCJfb7jHkTt13f8PZ/W/MM TwQlphHupr+Eig1uiaCmEybcBMCAe4mVU4rHXxPWUIrdg2kxwS/KJGhvUaMULPbnRQ6G OedEN+PaP4ERedfKjTDikVDD3hxYCAJOSfWJObn8hQtm7D+ixJbz1VlG2Gzi/iCNZXb5 uNvEI6FCjcj13fd0SlRhGL02P3eSKnhftJxqabqo4vXo0fUXJL17tHQojiTWNaW3NVgO ggZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0zAr88doy4l35/U8kOUIKFNAL46N655Bwwt/mOy9kK4=; b=p6t71Or00dh9WxldjBTVSp/ukzlPHs4E17ftVQdpu2E4vd9p0yI0TlenBF7zutlecv bE5ZDO0PDVrrJ6hsFQK0y2FOBy7yvtSBZaU2ParfZLRPJn6fcy5ZCv8AVlh7/N2s2bqG Ay0tiqBKwdr99/oBx4OekgQat39KsMrHLj3hLXxNm3QLTJcwkLrOtOrrCqi363Ib7Gqt lcqgw4RlnRV15VdpY5TZnFDghq/HHMlEj8KhDYnD0tK7DtNWZQ7DUXjUMDWZs0bfG/N2 qIRUI60RZKuDwMLY4mgBJaAewhJZFec81OW4qX5QzNalIwPVP+quGHkUeprzo2xqA7P7 w2qg== X-Gm-Message-State: AO0yUKW9VJRd9ChG/OrqKMmRh/nAXFJfF4srkI9dyNpMSrNo1MekvFSL jRv4X/quN5RXHS+pv6T1I24qbjp9TmR+GPzwyR8= X-Google-Smtp-Source: AK7set/1vAi6F1WPLLZ6urPvrUQetmEnypxUpqtKOVw6UV3iDStcpUgP1Ch/rx5e39NByVmADwjHTw== X-Received: by 2002:a17:902:ecc3:b0:19a:9880:1764 with SMTP id a3-20020a170902ecc300b0019a98801764mr9517722plh.59.1677033233683; Tue, 21 Feb 2023 18:33:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 10/25] include/exec/memattrs: Add two bits of space to MemTxAttrs Date: Tue, 21 Feb 2023 16:33:21 -1000 Message-Id: <20230222023336.915045-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033536569100007 Content-Type: text/plain; charset="utf-8" We will need 2 bits to represent ARMSecurityState. Do not attempt to replace or widen secure, even though it logically overlaps the new field -- there are uses within e.g. hw/block/pflash_cfi01.c, which don't know anything specific about ARM. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/memattrs.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 9fb98bc1ef..d04170aa27 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -29,10 +29,17 @@ typedef struct MemTxAttrs { * "didn't specify" if necessary. */ unsigned int unspecified:1; - /* ARM/AMBA: TrustZone Secure access + /* + * ARM/AMBA: TrustZone Secure access * x86: System Management Mode access */ unsigned int secure:1; + /* + * ARM: ArmSecuritySpace. This partially overlaps secure, but it is + * easier to have both fields to assist code that does not understand + * ARMv9 RME, or no specific knowledge of ARM at all (e.g. pflash). + */ + unsigned int space:2; /* Memory access is usermode (unprivileged) */ unsigned int user:1; /* --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677033278; cv=none; d=zohomail.com; s=zohoarc; b=kho/BkQ4QuC2117YGk6g7T8iA372pEwRS2sOW9rIvZ9NXiBff1VSACQYecB3GGcyX5HpAGYI4GmsD1WPpQzaSd4ob+MSrgCpzhLQnA3GAkfzcYqSbiFMpV2OgQaqIQhNX1d5rEZfZBFxHRyOg6r0WF7VuTG7WmDKcYwNgEjR7XQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677033278; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=EWyoKLNYT7BI4DSP24uw6KDK1ZUmKKpGpsEn941WxC4=; b=m6OUDwI8MQm7DLphYs70erJj6GhFqTgusa/MDYxoC056EHEI7XuN63NBv0Yn9qron8d96KzPv+VbmJumWO9UW8KGTDh2d3NogOsgqh05kWRZTf7xpKvTIzGSjoSrqgR2v3zdlVbFD3K/M4JjpKBSxo0pLCKe5iOBexDliikAI4w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677033278197831.7332948325143; Tue, 21 Feb 2023 18:34:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pUexP-0007Yx-GQ; Tue, 21 Feb 2023 21:34:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pUexC-0007MV-CM for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:33:59 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pUexA-0001dh-NP for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:33:58 -0500 Received: by mail-pl1-x62e.google.com with SMTP id q11so7541726plx.5 for ; Tue, 21 Feb 2023 18:33:56 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EWyoKLNYT7BI4DSP24uw6KDK1ZUmKKpGpsEn941WxC4=; b=trnRBCr44khClTf+xyrSp69kwRpab7DowFPT2nUP3pTaydCXixSMiQWxS6lWEcq+wh +qBDdVewl4Qlb/WPf3jLRsWI7vhhfzuCACWWgKm65bs/Chj58IcsI9fZLCpkR4vvZfAX gNwGzFq0DOmzbqmBUR7eaJyDYVYwmTpmH5RvugsV0FyeDFjcOtEET63ExPSqvpdL4Hgm mqwmSwcja0MEBLwozr27Fy0OCn9Gb8K5CDgvXl1Z1aMV/nd33JD5vFKTcW0KsWD/PSWT LKLlVVP1xJDVRXqiLUiWUGiT+irz1i7Hi0jAl3WLv66tZh7PKxOk9pTmn05GPf8p6zcq zwJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EWyoKLNYT7BI4DSP24uw6KDK1ZUmKKpGpsEn941WxC4=; b=pEMWEnHygTVHlj1jIilONwTL07JeNoGGlmA+r0ZNzMZtAjN/8TOMc2TbeR59UUMG59 MEgPEST7vh8pEAWdvAYkjXFa6XXY0dHJ7RrVLNngsDiWtJW0eKB1UlPYzacY7sQbs4ns 9SG0PXb7Z7+aVuPiyCXPIMG9t6t6lvDu3tQjKb7bMP+YwWdCqfMffjjf4bgcKeklUyhd RVntOXsrfawzV7UrTsLBDtHgFYD2LZokDIYu7FtB/HqVS/e765E60DOZqzte4LDVUzge fmr6S79QeA8OQpI/nvKKO6EPs3oHj94QJ101UALcxySEAwVzNSpolgk3MT7hXNgtnr+1 sgjA== X-Gm-Message-State: AO0yUKVAsPsFYt62KfRS1RBZ3WNb8FVRzPbt1XsSU9WUi3Lk/6uPs/1R jH4bXFNm4AOxX60mOIhOt9fW7NAjcFOE+czWfdM= X-Google-Smtp-Source: AK7set91TxQHzJ2oMRMf53k98YV3JdcyQqgwB70X3Hx7ll7pqZ/ylZqZuL89G4iHTE3ija+WIwiJ/g== X-Received: by 2002:a17:903:32cf:b0:19a:b092:b31a with SMTP id i15-20020a17090332cf00b0019ab092b31amr7161337plr.8.1677033235240; Tue, 21 Feb 2023 18:33:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 11/25] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx Date: Tue, 21 Feb 2023 16:33:22 -1000 Message-Id: <20230222023336.915045-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033279518100002 Content-Type: text/plain; charset="utf-8" It will be helpful to have ARMMMUIdx_Phys_* to be in the same relative order as ARMSecuritySpace enumerators. This requires the adjustment to the nstable check. While there, check for being in secure state rather than rely on clearing the low bit making no change to non-secure state. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 12 ++++++------ target/arm/ptw.c | 12 +++++------- 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 203a3e0046..c5fc475cf8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2855,18 +2855,18 @@ typedef enum ARMMMUIdx { ARMMMUIdx_E2 =3D 6 | ARM_MMU_IDX_A, ARMMMUIdx_E3 =3D 7 | ARM_MMU_IDX_A, =20 - /* TLBs with 1-1 mapping to the physical address spaces. */ - ARMMMUIdx_Phys_NS =3D 8 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_S =3D 9 | ARM_MMU_IDX_A, - /* * Used for second stage of an S12 page table walk, or for descriptor * loads during first stage of an S1 page table walk. Note that both * are in use simultaneously for SecureEL2: the security state for * the S2 ptw is selected by the NS bit from the S1 ptw. */ - ARMMMUIdx_Stage2 =3D 10 | ARM_MMU_IDX_A, - ARMMMUIdx_Stage2_S =3D 11 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2_S =3D 8 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2 =3D 9 | ARM_MMU_IDX_A, + + /* TLBs with 1-1 mapping to the physical address spaces. */ + ARMMMUIdx_Phys_S =3D 10 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_NS =3D 11 | ARM_MMU_IDX_A, =20 /* * These are not allocated TLBs and are used only for AT system diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6fb72fb086..5ed5bb5039 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1410,16 +1410,14 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, descaddr |=3D (address >> (stride * (4 - level))) & indexmask; descaddr &=3D ~7ULL; nstable =3D extract32(tableattrs, 4, 1); - if (nstable) { + if (nstable && ptw->in_secure) { /* * Stage2_S -> Stage2 or Phys_S -> Phys_NS - * Assert that the non-secure idx are even, and relative order. + * Assert the relative order of the secure/non-secure indexes. */ - QEMU_BUILD_BUG_ON((ARMMMUIdx_Phys_NS & 1) !=3D 0); - QEMU_BUILD_BUG_ON((ARMMMUIdx_Stage2 & 1) !=3D 0); - QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS + 1 !=3D ARMMMUIdx_Phys_S); - QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2 + 1 !=3D ARMMMUIdx_Stage2_S); - ptw->in_ptw_idx &=3D ~1; + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_S + 1 !=3D ARMMMUIdx_Phys_NS); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 !=3D ARMMMUIdx_Stage2); + ptw->in_ptw_idx +=3D 1; ptw->in_secure =3D false; } if (!S1_ptw_translate(env, ptw, descaddr, fi)) { --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677033483; cv=none; d=zohomail.com; s=zohoarc; b=CM7RJG66LAQyKK+yYfO5nyf4Vr/85oPQ8EhpafaTuXxgfnhtrTZMKrxBJw8nwLVUOZUnAoFl8tCZJVKaLLSWq+jSpkM1PSL5yqC/ubSRTXBUwKnMuY7gTpeM70lExdvSYcEaYIZ3hVlJi+mOxN0A5BObK8K916ec+/QkQ/k0FaQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677033483; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ManreqguuHsU2H8Z3wJmlF43bUQxuUikBGpUaE6IsMg=; b=hPPzqfkVtVYxeo+oCOuR7/tXnYqOG8pMvMaokU0100F8GzQC/DA2Bby3RjcL49ZG4x0A7sEYNHMqQVEC7GqWtWFs8JnaTk0isPwELP6paiKsnanHeQM583RnJ/tQrPMR9RH8thebSHTKYgiqQhATlKUHoLCpzOpA0Vn8ZP9vV/0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677033483935733.1777005511777; Tue, 21 Feb 2023 18:38:03 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pUexR-0007cE-62; Tue, 21 Feb 2023 21:34:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pUexC-0007Me-U8 for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:33:59 -0500 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pUexB-0001bU-9I for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:33:58 -0500 Received: by mail-pj1-x102a.google.com with SMTP id pt11so7907002pjb.1 for ; Tue, 21 Feb 2023 18:33:56 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ManreqguuHsU2H8Z3wJmlF43bUQxuUikBGpUaE6IsMg=; b=AocALbKhIYvuNsOUP/0nu8WLrw99RivhRd9ADiuobvqEf0OQjBBfObn4Hb9advEU/x LNau8XUsMhF4LjZRz/ojZajfEJY+LjTY3YPZbu3jtZl4tY4CkzHQqZ5F41JPx0rnnaEi 1AchgoEsD+vF7gWzmlhnUJuSFinUFTTcdY0Ql6VqVl4PavafqwHZzlXFVHzl86cc7Ugj bzNF40XFXXVJgEG7eKsYfGEEIWGQo79fxJiQaEFDE3d2gAlx5eIYuVUche3s07sgHKEO DxP+uvdxAt+oLleOjyQ9bBIyHH0VAY1MiMKoI6hNBh98JwncSbD0/zMqhhhbNKNc2GwL KO5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ManreqguuHsU2H8Z3wJmlF43bUQxuUikBGpUaE6IsMg=; b=XRpskHfhoghz9QiK5ffDTFW3EzdyKGnn8qZ0+8LTWhkR7KlC4EO33HhtUiQQszuQ0A zsGoimsBUkhOcJ6p+tcBj25XXMhEFt0dk/GG5jZIJiwkXuFvorfyNn/VFiSegoaMZGhu 06gZ2EjjG9Tn45x9pbR4acWXCZa6+Tib+T6qVV8ekeB44DcrVpEyR/HFm3osNEqYjZdZ 2o+ZP1HLvoWn02hGqNoGSWaZtKTQHyXrpXuC+DIMv+fdYj1QWY9jDwLJo3VmBQOppUbY w5T91RTR/vuPmi9soDt+ehCJ6LmxxF3zr4HNk/rX4LaZpP3KmvfVLDOImO8fEulyhcFy s11g== X-Gm-Message-State: AO0yUKUF/CXJdHMcr7N/mIveofQNZ+DwT2yozPc/FZNdHMMfrxEgrtLW hd7yRGj3BauvrQfnJ94kmx0iY+tKwDBgFsWw0eU= X-Google-Smtp-Source: AK7set+l1Uqb/Uf/5/A88P/27LddBEYW5lHHnsdB/x8DigOqf5x4pPwmSE5JR96+Qd1x85xtP49Qzw== X-Received: by 2002:a17:902:e80f:b0:19b:afb:b92e with SMTP id u15-20020a170902e80f00b0019b0afbb92emr11077986plg.40.1677033236537; Tue, 21 Feb 2023 18:33:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 12/25] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root} Date: Tue, 21 Feb 2023 16:33:23 -1000 Message-Id: <20230222023336.915045-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033484352100001 Content-Type: text/plain; charset="utf-8" With FEAT_RME, there are four physical address spaces. For now, just define the symbols, and mention them in the same spots as the other Phys indexes in ptw.c. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 23 +++++++++++++++++++++-- target/arm/ptw.c | 10 ++++++++-- 3 files changed, 30 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 53cac9c89b..8dfd7a0bb6 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -47,6 +47,6 @@ bool guarded; #endif =20 -#define NB_MMU_MODES 12 +#define NB_MMU_MODES 14 =20 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c5fc475cf8..05fd6e61aa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2865,8 +2865,10 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage2 =3D 9 | ARM_MMU_IDX_A, =20 /* TLBs with 1-1 mapping to the physical address spaces. */ - ARMMMUIdx_Phys_S =3D 10 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_NS =3D 11 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_S =3D 10 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_NS =3D 11 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_Root =3D 12 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_Realm =3D 13 | ARM_MMU_IDX_A, =20 /* * These are not allocated TLBs and are used only for AT system @@ -2930,6 +2932,23 @@ typedef enum ARMASIdx { ARMASIdx_TagS =3D 3, } ARMASIdx; =20 +static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) +{ + /* Assert the relative order of the physical mmu indexes. */ + QEMU_BUILD_BUG_ON(ARMSS_Secure !=3D 0); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS !=3D ARMMMUIdx_Phys_S + ARMSS_NonS= ecure); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root !=3D ARMMMUIdx_Phys_S + ARMSS_Ro= ot); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm !=3D ARMMMUIdx_Phys_S + ARMSS_R= ealm); + + return ARMMMUIdx_Phys_S + space; +} + +static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) +{ + assert(idx >=3D ARMMMUIdx_Phys_S && idx <=3D ARMMMUIdx_Phys_Realm); + return idx - ARMMMUIdx_Phys_S; +} + static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) { /* If all the CLIDR.Ctypem bits are 0 there are no caches, and diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5ed5bb5039..5a0c5edc88 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -182,8 +182,10 @@ static bool regime_translation_disabled(CPUARMState *e= nv, ARMMMUIdx mmu_idx, case ARMMMUIdx_E3: break; =20 - case ARMMMUIdx_Phys_NS: case ARMMMUIdx_Phys_S: + case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_Root: + case ARMMMUIdx_Phys_Realm: /* No translation for physical address spaces. */ return true; =20 @@ -2632,8 +2634,10 @@ static bool get_phys_addr_disabled(CPUARMState *env,= target_ulong address, switch (mmu_idx) { case ARMMMUIdx_Stage2: case ARMMMUIdx_Stage2_S: - case ARMMMUIdx_Phys_NS: case ARMMMUIdx_Phys_S: + case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_Root: + case ARMMMUIdx_Phys_Realm: break; =20 default: @@ -2830,6 +2834,8 @@ static bool get_phys_addr_with_struct(CPUARMState *en= v, S1Translate *ptw, switch (mmu_idx) { case ARMMMUIdx_Phys_S: case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_Root: + case ARMMMUIdx_Phys_Realm: /* Checking Phys early avoids special casing later vs regime_el. */ return get_phys_addr_disabled(env, address, access_type, mmu_idx, is_secure, result, fi); --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9iG9/NOmHP3MVj9nzPcx5U3Tkz40AHCYrjm18zTuNT0=; b=Bw6iPzI43P5H9s9qs63KgiGr4M6bWw6o1rWU47REeYdFGsXCUVWYjUs1lNaEgUZqJ+ hmmrla5PtZsYOK3KPDDD4y2wAtz15vBzqKl8I05NGfSy5z3l5VJifbwJCrI8Ph5oTTBf TKHqoesEPjYpA8e4v5b42O1ofO4MUw+mQV1zFi8MYN2qcKiG83HF0uI5ytN+RqftTvfy dnByXPruz9+1op97yz2eIf93RIWLOu5SwfnKU6MBBzokREkcxBuH5E/TgRHMNBzPNFYP AaCGkY2xbZs2I3E1s3ZgHOKEUPQLGC1uWDGGJlLfPWZcY24oRYnqJ5oIxXbGB3hVDa6q 6w7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9iG9/NOmHP3MVj9nzPcx5U3Tkz40AHCYrjm18zTuNT0=; b=CQaUTU3The40z4MjRK0N8QZ746vuzSTGpZ2yvf5Gm3EoMI+ZYnIiCKGxtTG1dpZrr7 DJ3x1Y0eofQnAmoumF2R17D8sX1m76oS4W/S4om6IgmPGqQdK5b18M6EY8h4pi5WeLC3 td0JDqdM3BUt8n4Hew2XZxtSzvzdW1eJw1WNJYrYbB+5VPnh4Tjpygs+qujKphRRlbYp aghNxpk2m9NIPEJ6uYXwLjKDVsyDH6dqzD7u+GHQMID9ikvKpehrDr75JQOZTHh4kQzp pJtupbNZI6fphBNAP+CX2iq8tifZZ475x3rs/XwjykxDZspCbSnSmPbWt86F2VeLIUwX q5Tg== X-Gm-Message-State: AO0yUKVzGgXTFbkRrhrzBKsLmQFED38gTruBOZAG6MlpxyOUDrnocTw2 ZaMHnsvxwHAWpxAZhRqKgbNbO7ypeuW8cB9lmNg= X-Google-Smtp-Source: AK7set+U0dRCrtUmqxO8aDlQXVBOTpSYOBn3aq20pGHlPuHOAYPXAlzdblIkf98b6JfqdtrIcb8K9w== X-Received: by 2002:a17:903:2291:b0:19a:b427:2335 with SMTP id b17-20020a170903229100b0019ab4272335mr9823248plh.56.1677033237914; Tue, 21 Feb 2023 18:33:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 13/25] target/arm: Remove __attribute__((nonnull)) from ptw.c Date: Tue, 21 Feb 2023 16:33:24 -1000 Message-Id: <20230222023336.915045-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033407964100001 Content-Type: text/plain; charset="utf-8" This was added in 7e98e21c098 as part of a reorg in which one of the argument had been legally NULL, and this caught actual instances. Now that the reorg is complete, this serves little purpose. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/ptw.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5a0c5edc88..9f608b12b2 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -32,15 +32,13 @@ typedef struct S1Translate { static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, uint64_t address, MMUAccessType access_type, bool s1_is_el0, - GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) - __attribute__((nonnull)); + GetPhysAddrResult *result, ARMMMUFaultInfo = *fi); =20 static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, target_ulong address, MMUAccessType access_type, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) - __attribute__((nonnull)); + ARMMMUFaultInfo *fi); =20 /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. = */ static const uint8_t pamax_map[] =3D { --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677033534; cv=none; d=zohomail.com; s=zohoarc; b=mXWY/pW+g7kchkO1JvrXsVvb6dGHQswGA9XHebfz/YVudGdoDQkJP/tO+L3htViudlGGAncr1GlGpS3ciVfo0Qjv4z+Kld8wYrYB4bjZAJ4TQ39AIlshfQlkxOZWMUOLeCqpjm3jELZShjqjwtWxDi2WutLJHZxRep1aK1jmjZw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677033534; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NEdCUdHrW00WmG0Jrfmbg8ARsi/ZJepNVs1RVZlJouA=; b=KSxBVDVIMQgjjvOJaXvNM3960V9wuJpCYWswhVUB09TOy8OCrTF8qgZvDFrYXxVYg0IYRLPio5nuLwDMAVoYhMB5/T4darF10Wb8q1WE9XAq2kZ/zBQzZ5jH/smwir6TtEwukbDoy6/DYSmQFy20BsBtn6jRTxPlcHEBoDQYZy8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677033534606503.7836203291474; Tue, 21 Feb 2023 18:38:54 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pUexR-0007dn-Tl; Tue, 21 Feb 2023 21:34:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pUexH-0007OM-5t for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:34:03 -0500 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pUexF-0001fH-26 for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:34:02 -0500 Received: by mail-pl1-x642.google.com with SMTP id h14so7359266plf.10 for ; Tue, 21 Feb 2023 18:34:00 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:33:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NEdCUdHrW00WmG0Jrfmbg8ARsi/ZJepNVs1RVZlJouA=; b=IdhEnL4HpdFdXUKFf4DDSZTYw18TZ4qvAcMidmbkSjOVDrNmHjVE0JYDBZE2+GgEqF 1s/8voxeJTppPX2H5IqzEnt+qni00t41iNCJ/8UlM+2tJitPcwf+ctybFheNbUeUqrin cg5H7pzuAmUiXaQs7QB5l0R8JblV+89faA+fVkh12PELOHHgbDF0Aajj1I0ePl9wG2Gz DDOYt5R4B2ZhOU7vHt2DbeZqZdyCHd/2xj1LxZhSJkfBKL2G4c8W8aTi9wO3WLO6VfmJ PXS6PTu7EbUMCNaslDw2mEnAAms6Xi3zvqPhED3V7jhTZU2EtL2dUljbOIIGdsrNNYVF TxRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NEdCUdHrW00WmG0Jrfmbg8ARsi/ZJepNVs1RVZlJouA=; b=ScP7MYHZ5NLxLL2+rsrfOJgKCIjl1beXxgPvxW3e8+1Lo28ZLYzgx+yY5YcD/RHjc4 XY29yhMewfWU8u+/9dsCtN9oZEo2sIpyWxKWT/N3kgMVD+pZDx5t5NYz0rjL0BBPJalo A5oxadytoAjZa+XfE75va3Q6y7hBmGIN06bVQ7BHrSIcy+4EQw1uJ81gi6ve1JUwNqCS Ad8MAAemubekWNBX8E2DX1u9UAyCWLiv5Wo9vE8AwVy6T996fy6Tb0rWO9vLgumPRwbx bnZ3741cosvP+ab8vukh7umWwvxbtwhCE2XANetSt9+x+Y1lyb/+M/HVHDY2s4sWnNCI Xsrg== X-Gm-Message-State: AO0yUKUl3KAjdJtKMzhYDwDGNmehRxzVGK/H8MchTaFwgEBnwdnmqliL 0y+1VM/eUnEbpMpKmFv6BXo4gSqwr6xjGDzTuBbSyQ== X-Google-Smtp-Source: AK7set8GJkupQW++FuEsFvL7+4Eq4Oag6CZkmggn2vRDzzkQNyzyLj7bBh7RDoAocoWXuaEys9cAtQ== X-Received: by 2002:a17:903:786:b0:19a:8338:703b with SMTP id kn6-20020a170903078600b0019a8338703bmr5491282plb.57.1677033239280; Tue, 21 Feb 2023 18:33:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 14/25] target/arm: Pipe ARMSecuritySpace through ptw.c Date: Tue, 21 Feb 2023 16:33:25 -1000 Message-Id: <20230222023336.915045-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033536606100009 Content-Type: text/plain; charset="utf-8" Add input and output space members to S1Translate. Set and adjust them in S1_ptw_translate, and the various points at which we drop secure state. Initialize the space in get_phys_addr; for now leave get_phys_addr_with_secure considering only secure vs non-secure spaces. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 98 ++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 78 insertions(+), 20 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 9f608b12b2..a77db3dd43 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -19,11 +19,13 @@ typedef struct S1Translate { ARMMMUIdx in_mmu_idx; ARMMMUIdx in_ptw_idx; + ARMSecuritySpace in_space; bool in_secure; bool in_debug; bool out_secure; bool out_rw; bool out_be; + ARMSecuritySpace out_space; hwaddr out_virt; hwaddr out_phys; void *out_host; @@ -216,6 +218,7 @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t a= ttrs) static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, hwaddr addr, ARMMMUFaultInfo *fi) { + ARMSecuritySpace space =3D ptw->in_space; bool is_secure =3D ptw->in_secure; ARMMMUIdx mmu_idx =3D ptw->in_mmu_idx; ARMMMUIdx s2_mmu_idx =3D ptw->in_ptw_idx; @@ -232,7 +235,8 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl= ate *ptw, if (regime_is_stage2(s2_mmu_idx)) { S1Translate s2ptw =3D { .in_mmu_idx =3D s2_mmu_idx, - .in_ptw_idx =3D is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_P= hys_NS, + .in_ptw_idx =3D arm_space_to_phys(space), + .in_space =3D space, .in_secure =3D is_secure, .in_debug =3D true, }; @@ -290,10 +294,17 @@ static bool S1_ptw_translate(CPUARMState *env, S1Tran= slate *ptw, } =20 /* Check if page table walk is to secure or non-secure PA space. */ - ptw->out_secure =3D (is_secure - && !(pte_secure + if (is_secure) { + bool out_secure =3D !(pte_secure ? env->cp15.vstcr_el2 & VSTCR_SW - : env->cp15.vtcr_el2 & VTCR_NSW)); + : env->cp15.vtcr_el2 & VTCR_NSW); + if (!out_secure) { + is_secure =3D false; + space =3D ARMSS_NonSecure; + } + } + ptw->out_secure =3D is_secure; + ptw->out_space =3D space; ptw->out_be =3D regime_translation_big_endian(env, mmu_idx); return true; =20 @@ -324,7 +335,10 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, S1Transl= ate *ptw, } } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs =3D { .secure =3D ptw->out_secure }; + MemTxAttrs attrs =3D { + .secure =3D ptw->out_secure, + .space =3D ptw->out_space, + }; AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; =20 @@ -367,7 +381,10 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Transl= ate *ptw, #endif } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs =3D { .secure =3D ptw->out_secure }; + MemTxAttrs attrs =3D { + .secure =3D ptw->out_secure, + .space =3D ptw->out_space, + }; AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; =20 @@ -873,6 +890,7 @@ static bool get_phys_addr_v6(CPUARMState *env, S1Transl= ate *ptw, * regime, because the attribute will already be non-secure. */ result->f.attrs.secure =3D false; + result->f.attrs.space =3D ARMSS_NonSecure; } result->f.phys_addr =3D phys_addr; return false; @@ -1577,6 +1595,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, * regime, because the attribute will already be non-secure. */ result->f.attrs.secure =3D false; + result->f.attrs.space =3D ARMSS_NonSecure; } =20 /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. = */ @@ -2361,6 +2380,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, */ if (sattrs.ns) { result->f.attrs.secure =3D false; + result->f.attrs.space =3D ARMSS_NonSecure; } else if (!secure) { /* * NS access to S memory must fault. @@ -2710,6 +2730,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, bool is_secure =3D ptw->in_secure; bool ret, ipa_secure, s2walk_secure; ARMCacheAttrs cacheattrs1; + ARMSecuritySpace ipa_space, s2walk_space; bool is_el0; uint64_t hcr; =20 @@ -2722,20 +2743,24 @@ static bool get_phys_addr_twostage(CPUARMState *env= , S1Translate *ptw, =20 ipa =3D result->f.phys_addr; ipa_secure =3D result->f.attrs.secure; + ipa_space =3D result->f.attrs.space; if (is_secure) { /* Select TCR based on the NS bit from the S1 walk. */ s2walk_secure =3D !(ipa_secure ? env->cp15.vstcr_el2 & VSTCR_SW : env->cp15.vtcr_el2 & VTCR_NSW); + s2walk_space =3D arm_secure_to_space(s2walk_secure); } else { assert(!ipa_secure); s2walk_secure =3D false; + s2walk_space =3D ipa_space; } =20 is_el0 =3D ptw->in_mmu_idx =3D=3D ARMMMUIdx_Stage1_E0; ptw->in_mmu_idx =3D s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Sta= ge2; - ptw->in_ptw_idx =3D s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_= NS; + ptw->in_ptw_idx =3D arm_space_to_phys(s2walk_space); ptw->in_secure =3D s2walk_secure; + ptw->in_space =3D s2walk_space; =20 /* * S1 is done, now do S2 translation. @@ -2823,11 +2848,12 @@ static bool get_phys_addr_with_struct(CPUARMState *= env, S1Translate *ptw, ARMMMUIdx s1_mmu_idx; =20 /* - * The page table entries may downgrade secure to non-secure, but - * cannot upgrade an non-secure translation regime's attributes - * to secure. + * The page table entries may downgrade Secure to NonSecure, but + * cannot upgrade a NonSecure translation regime's attributes + * to Secure or Realm. */ result->f.attrs.secure =3D is_secure; + result->f.attrs.space =3D ptw->in_space; =20 switch (mmu_idx) { case ARMMMUIdx_Phys_S: @@ -2869,7 +2895,7 @@ static bool get_phys_addr_with_struct(CPUARMState *en= v, S1Translate *ptw, =20 default: /* Single stage and second stage uses physical for ptw. */ - ptw->in_ptw_idx =3D is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_= NS; + ptw->in_ptw_idx =3D arm_space_to_phys(ptw->in_space); break; } =20 @@ -2944,6 +2970,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, S1Translate ptw =3D { .in_mmu_idx =3D mmu_idx, .in_secure =3D is_secure, + .in_space =3D arm_secure_to_space(is_secure), }; return get_phys_addr_with_struct(env, &ptw, address, access_type, result, fi); @@ -2953,7 +2980,10 @@ bool get_phys_addr(CPUARMState *env, target_ulong ad= dress, MMUAccessType access_type, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { - bool is_secure; + S1Translate ptw =3D { + .in_mmu_idx =3D mmu_idx, + }; + ARMSecuritySpace ss; =20 switch (mmu_idx) { case ARMMMUIdx_E10_0: @@ -2966,30 +2996,55 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E2: - is_secure =3D arm_is_secure_below_el3(env); + ss =3D arm_security_space_below_el3(env); break; case ARMMMUIdx_Stage2: + /* + * For Secure EL2, we need this index to be NonSecure; + * otherwise this will already be NonSecure or Realm. + */ + ss =3D arm_security_space_below_el3(env); + if (ss =3D=3D ARMSS_Secure) { + ss =3D ARMSS_NonSecure; + } + break; case ARMMMUIdx_Phys_NS: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: case ARMMMUIdx_MUser: - is_secure =3D false; + ss =3D ARMSS_NonSecure; break; - case ARMMMUIdx_E3: case ARMMMUIdx_Stage2_S: case ARMMMUIdx_Phys_S: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: case ARMMMUIdx_MSUser: - is_secure =3D true; + ss =3D ARMSS_Secure; + break; + case ARMMMUIdx_E3: + if (arm_feature(env, ARM_FEATURE_AARCH64) && + cpu_isar_feature(aa64_rme, env_archcpu(env))) { + ss =3D ARMSS_Root; + } else { + ss =3D ARMSS_Secure; + } + break; + case ARMMMUIdx_Phys_Root: + ss =3D ARMSS_Root; + break; + case ARMMMUIdx_Phys_Realm: + ss =3D ARMSS_Realm; break; default: g_assert_not_reached(); } - return get_phys_addr_with_secure(env, address, access_type, mmu_idx, - is_secure, result, fi); + + ptw.in_space =3D ss; + ptw.in_secure =3D arm_space_is_secure(ss); + return get_phys_addr_with_struct(env, &ptw, address, access_type, + result, fi); } =20 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, @@ -2997,9 +3052,12 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *c= s, vaddr addr, { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; + ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); + ARMSecuritySpace ss =3D arm_security_space(env); S1Translate ptw =3D { - .in_mmu_idx =3D arm_mmu_idx(env), - .in_secure =3D arm_is_secure(env), + .in_mmu_idx =3D mmu_idx, + .in_space =3D ss, + .in_secure =3D arm_space_is_secure(ss), .in_debug =3D true, }; GetPhysAddrResult res =3D {}; --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.33.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vZ42O5SQoIJotc7B0HupvbG77824SBhRrElE1X3jpLY=; b=pce8Ec/SaTsZ2O46hf0UgbCiRNOnqhvwbiZVSuSjFzOQlyzH73UYBlQ+VnArCsoGcg KrisqGapxxhprtrnm5hAbC+sR1N2B9vlz6mSYs1Y7TdfHdqzlFx7swA3MrJqHU4lc4/7 KTCGwhOw5Mxur67/2Qfow5S15a1nmUZE+hMP8Pf1CG4deM2cDhccNQSDr6AvyYFpPfTF wELHHHvEtST2ra196AcQFYfSO7xMSbs7ECBpZLTfukI61dCbQGLJZw400zMJj/sjwE8d AZPfgFSX7lwxaA02Pa1qYCsbJQcR+1/MxB2vt8S5YW13uuDAbdIl5SZsDrm25xvqE0XQ JO9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vZ42O5SQoIJotc7B0HupvbG77824SBhRrElE1X3jpLY=; b=ENcEVXAVjDlKKce+H8bxGeY/OSf3z9stY3DjfVh77jIPbg1xNGz1XXSUpJeespbB+i NfdFbm33qFClcXOJH5PHMM8OERSPwWtzeCmGxRDJyotAw8yFAUdgpXMieEBt56LBr0T3 iL6wQbgFogV1j0gV5d7gz+c97L2J8CJIJ/HA8aRZWSwb27/XqDr4R6L8VU/aPkV0oj/K OCrh0Mvx0S+jirwmwzknwH4a0HHJrQW23S3Zlv67HS9KMiaKJrIXSLi0MdGjV4ctu6F1 9KgtwsHZDD11nsL/b74NlydOVqrNjCn9rTGC+IWVhZgSM7f70Su3k9StFfyZQBv4OAue BkcQ== X-Gm-Message-State: AO0yUKW9hTUwI6eRgoWE/uv4bC9pcfqOMa99Hah/zzu18WcO9Fqq1Nkt 7UmV/bPE1mNzUm996qMe3TGPEkHg4wg+4lvQz1U= X-Google-Smtp-Source: AK7set/n1QWvo7DkTD66RrSUlnnihuW+30r7XNSc8653a4Tp6Z7FqyWFLt6RNOIsKyq7IJrAOzBLJA== X-Received: by 2002:a17:902:facd:b0:19a:9b87:e73f with SMTP id ld13-20020a170902facd00b0019a9b87e73fmr7466085plb.1.1677033240587; Tue, 21 Feb 2023 18:34:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 15/25] target/arm: NSTable is RES0 for the RME EL3 regime Date: Tue, 21 Feb 2023 16:33:26 -1000 Message-Id: <20230222023336.915045-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033426095100004 Content-Type: text/plain; charset="utf-8" Test in_space instead of in_secure so that we don't switch out of Root space. Handle the output space change immediately, rather than try and combine the NSTable and NS bits later. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a77db3dd43..8b3deb0884 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1238,7 +1238,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, { ARMCPU *cpu =3D env_archcpu(env); ARMMMUIdx mmu_idx =3D ptw->in_mmu_idx; - bool is_secure =3D ptw->in_secure; int32_t level; ARMVAParameters param; uint64_t ttbr; @@ -1254,7 +1253,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); uint64_t descriptor, new_descriptor; - bool nstable; =20 /* TODO: This code does not support shareability levels. */ if (aarch64) { @@ -1415,20 +1413,19 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, descaddrmask =3D MAKE_64BIT_MASK(0, 40); } descaddrmask &=3D ~indexmask_grainsize; - - /* - * Secure accesses start with the page table in secure memory and - * can be downgraded to non-secure at any step. Non-secure accesses - * remain non-secure. We implement this by just ORing in the NSTable/NS - * bits at each step. - */ - tableattrs =3D is_secure ? 0 : (1 << 4); + tableattrs =3D 0; =20 next_level: descaddr |=3D (address >> (stride * (4 - level))) & indexmask; descaddr &=3D ~7ULL; - nstable =3D extract32(tableattrs, 4, 1); - if (nstable && ptw->in_secure) { + + /* + * Process the NSTable bit from the previous level. This changes + * the table address space and the output space from Secure to + * NonSecure. With RME, the EL3 translation regime does not change + * from Root to NonSecure. + */ + if (extract32(tableattrs, 4, 1) && ptw->in_space =3D=3D ARMSS_Secure) { /* * Stage2_S -> Stage2 or Phys_S -> Phys_NS * Assert the relative order of the secure/non-secure indexes. @@ -1437,7 +1434,11 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 !=3D ARMMMUIdx_Stage2); ptw->in_ptw_idx +=3D 1; ptw->in_secure =3D false; + ptw->in_space =3D ARMSS_NonSecure; + result->f.attrs.secure =3D false; + result->f.attrs.space =3D ARMSS_NonSecure; } + if (!S1_ptw_translate(env, ptw, descaddr, fi)) { goto do_fault; } @@ -1540,7 +1541,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, */ attrs =3D new_descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(5= 0, 14)); if (!regime_is_stage2(mmu_idx)) { - attrs |=3D nstable << 5; /* NS */ + attrs |=3D !ptw->in_secure << 5; /* NS */ if (!param.hpd) { attrs |=3D extract64(tableattrs, 0, 2) << 53; /* XN, PXN */ /* --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677033290; cv=none; d=zohomail.com; s=zohoarc; b=ase5BM7GzyHTezsxqmPrFcz3SdDr+sr5yhpDyKdhue+lKj/O8m4R1oOLzncXYasVwjWd6MaG4IqCW6rp6vDmxNs7ofM+CHtgsIKzVF9uS1utOF2G8vG9NsrcYl6esHLnmq9QKjI5AzbArZ9YjPUv5qgRXvcDEcotIFEJNv8KECQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677033290; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Sp5dyg/bRPedb4z1tKWhvvEgmxz3Z+nJXy57x/hLb5A=; b=bg7/1czx6sV1sQUaOatYVLdM1C4T/usfip4Ai8lxqd9oMsxt8JEUB0MgwuGemYVxVfKfA72gs23hr5zDFKYy3dS1NUgyTQQWWaEwrhSDFYQ5VvU0pVgBcDfj/QEAbflyxY/Ut9V0QbdkEj9LStZG1ECkD3ZGdy0dVsjIznCLXec= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677033290155220.16427582760264; Tue, 21 Feb 2023 18:34:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pUexS-0007em-Dy; Tue, 21 Feb 2023 21:34:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pUexL-0007Om-EM for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:34:07 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pUexG-0001bT-Ld for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:34:04 -0500 Received: by mail-pj1-x102b.google.com with SMTP id qi12-20020a17090b274c00b002341621377cso6969591pjb.2 for ; Tue, 21 Feb 2023 18:34:02 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.34.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Sp5dyg/bRPedb4z1tKWhvvEgmxz3Z+nJXy57x/hLb5A=; b=JnFxYy3ho8EVDHT1UkQEBFABlBuKjIsOffvpqqizLYQaPPmnNPK+qkBxvoe+7ZPOmh hSuGnmh0u4q/2CSqH2S1TUHAXda7aRK55R7PgUygiS/2Uk2HmLCWZO8mMN/sljzUE9fU o9604fCrBHWqd9ecoUjyCHvID4oFe0fA3zL0UeWkoRlFDyKkTnqEkeKD1n5fwGitBI2w pD4W2Ofme85/kAD1B8tsnjLZCZXho14wGH/oMpGeyeRoJ+GP8WeFrl9Jew6ZUVONRmA/ 8Tf+dbAuEpSxLJEnArZv7nkVfbj53e6GNzzFlEVYf524YAUv+2fldOhAvDGgzYPhVlTM 34Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Sp5dyg/bRPedb4z1tKWhvvEgmxz3Z+nJXy57x/hLb5A=; b=GvB/eMDrq+MZOrBN3Qe4Pbb1uPgP2Zr5rxqv2fl65lU9yh1BxByAo+1gTyOjCxxGce bIGe9O6segTUUfsJm3y4TljH75TM707uKUCmusxgTcy+xej8bsbQh0FuLYgZPgxNp2ic u0XezvpjhUyBGhkOwcR8FJYLFgOOhfzgrWt/Nh61Mu+cMHqzBLykDbTotT/cSa2XsWF/ K61Jv3j9mN7hXsjCjbVOEgF6QZ5+bZHAcByFTPGnngJiaGdyXeJ418SJEWUMQOn/o16Q eD0jCMpe0Efj3Sg97CdP5Wc0SE0GcirNNfFGjpxpMwu23q5UmeEetNozmPb/6uytGAzO FYHA== X-Gm-Message-State: AO0yUKV1j20ft1fmwqNhTNXFOiLkgsSajWhd7ExXdzbOAQAwBfqQsO8p jsOuYx3jlFc1m/rvuakkaBVLP6P6ntMJjtgTIKg= X-Google-Smtp-Source: AK7set9ZGLK1flp+h+IiD3erYTSGrRMICYsEq/V6KB2amiVGCO0g0shLqKxNXiY301G9BNR2gPCl1g== X-Received: by 2002:a17:902:b286:b0:19c:a9b8:4349 with SMTP id u6-20020a170902b28600b0019ca9b84349mr329469plr.32.1677033241915; Tue, 21 Feb 2023 18:34:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 16/25] target/arm: Handle Block and Page bits for security space Date: Tue, 21 Feb 2023 16:33:27 -1000 Message-Id: <20230222023336.915045-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033291606100001 Content-Type: text/plain; charset="utf-8" With Realm security state, bit 55 of a block or page descriptor during the stage2 walk becomes the NS bit; during the stage1 walk the bit 5 NS bit is RES0. With Root security state, bit 11 of the block or page descriptor during the stage1 walk becomes the NSE bit. Rather than collecting an NS bit and applying it later, compute the output pa space from the input pa space and unconditionally assign. This means that we no longer need to adjust the output space earlier for the NSTable bit. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 91 ++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 73 insertions(+), 18 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8b3deb0884..61c1227578 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -954,12 +954,14 @@ static int get_S2prot(CPUARMState *env, int s2ap, int= xn, bool s1_is_el0) * @mmu_idx: MMU index indicating required translation regime * @is_aa64: TRUE if AArch64 * @ap: The 2-bit simple AP (AP[2:1]) - * @ns: NS (non-secure) bit * @xn: XN (execute-never) bit * @pxn: PXN (privileged execute-never) bit + * @in_pa: The original input pa space + * @out_pa: The output pa space, modified by NSTable, NS, and NSE */ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, - int ap, int ns, int xn, int pxn) + int ap, int xn, int pxn, + ARMSecuritySpace in_pa, ARMSecuritySpace out_pa) { bool is_user =3D regime_is_user(env, mmu_idx); int prot_rw, user_rw; @@ -980,7 +982,8 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_i= dx, bool is_aa64, } } =20 - if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { + if (out_pa =3D=3D ARMSS_NonSecure && in_pa =3D=3D ARMSS_Secure && + (env->cp15.scr_el3 & SCR_SIF)) { return prot_rw; } =20 @@ -1248,11 +1251,12 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, int32_t stride; int addrsize, inputsize, outputsize; uint64_t tcr =3D regime_tcr(env, mmu_idx); - int ap, ns, xn, pxn; + int ap, xn, pxn; uint32_t el =3D regime_el(env, mmu_idx); uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); uint64_t descriptor, new_descriptor; + ARMSecuritySpace out_space; =20 /* TODO: This code does not support shareability levels. */ if (aarch64) { @@ -1435,8 +1439,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, ptw->in_ptw_idx +=3D 1; ptw->in_secure =3D false; ptw->in_space =3D ARMSS_NonSecure; - result->f.attrs.secure =3D false; - result->f.attrs.space =3D ARMSS_NonSecure; } =20 if (!S1_ptw_translate(env, ptw, descaddr, fi)) { @@ -1554,15 +1556,75 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, } =20 ap =3D extract32(attrs, 6, 2); + out_space =3D ptw->in_space; if (regime_is_stage2(mmu_idx)) { - ns =3D mmu_idx =3D=3D ARMMMUIdx_Stage2; + /* + * R_GYNXY: For stage2 in Realm security state, bit 55 is NS. + * The bit remains ignored for other security states. + */ + if (out_space =3D=3D ARMSS_Realm && extract64(attrs, 55, 1)) { + out_space =3D ARMSS_NonSecure; + } xn =3D extract64(attrs, 53, 2); result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); } else { - ns =3D extract32(attrs, 5, 1); + int nse, ns =3D extract32(attrs, 5, 1); + switch (out_space) { + case ARMSS_Root: + /* + * R_GVZML: Bit 11 becomes the NSE field in the EL3 regime. + * R_XTYPW: NSE and NS together select the output pa space. + */ + nse =3D extract32(attrs, 11, 1); + out_space =3D (nse << 1) | ns; + if (out_space =3D=3D ARMSS_Secure && + !cpu_isar_feature(aa64_sel2, cpu)) { + out_space =3D ARMSS_NonSecure; + } + break; + case ARMSS_Secure: + if (ns) { + out_space =3D ARMSS_NonSecure; + } + break; + case ARMSS_Realm: + switch (mmu_idx) { + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: + /* I_CZPRF: For Realm EL1&0 stage1, NS bit is RES0. */ + break; + case ARMMMUIdx_E2: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + /* + * R_LYKFZ, R_WGRZN: For Realm EL2 and EL2&1, + * NS changes the output to non-secure space. + */ + if (ns) { + out_space =3D ARMSS_NonSecure; + } + break; + default: + g_assert_not_reached(); + } + break; + case ARMSS_NonSecure: + /* R_QRMFF: For NonSecure state, the NS bit is RES0. */ + break; + default: + g_assert_not_reached(); + } xn =3D extract64(attrs, 54, 1); pxn =3D extract64(attrs, 53, 1); - result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, p= xn); + + /* + * Note that we modified ptw->in_space earlier for NSTable, but + * result->f.attrs retains a copy of the original security space. + */ + result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, xn, pxn, + result->f.attrs.space, out_space); } =20 if (!(result->f.prot & (1 << access_type))) { @@ -1589,15 +1651,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, } } =20 - if (ns) { - /* - * The NS bit will (as required by the architecture) have no effec= t if - * the CPU doesn't support TZ or this is a non-secure translation - * regime, because the attribute will already be non-secure. - */ - result->f.attrs.secure =3D false; - result->f.attrs.space =3D ARMSS_NonSecure; - } + result->f.attrs.space =3D out_space; + result->f.attrs.secure =3D arm_space_is_secure(out_space); =20 /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. = */ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.34.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q5sZk2IQIjptsv3a3XcSVTDNnG9U0oFxOYLINCyR7ko=; b=xwJzYDfi8qSAHPy8IfXKGBLidXWxZ9rzcQLWq1j0CEDpTBjugcbn9jdWZorZWRkBPx uVP6aqME2MiKdx6ZQ501Th7FkZhcVQZnky+b6sR+R1SdhcD+BJK+QLabYablDPPuP0ik Htj0VQ19t1HjYNDvIvYMfr1VfTb3XO+C3JYb8Qvur9jL0U8FXTFFlTlnuL2hRJng1+0t yI9tTFU8AjNow2mnXDOtfKwBBDBCZJ83srQqOJ0Tqm78YD2fKAfqMQ3j5n/lvjGDUf6E 3MUEk0eACJjdcbgE3OsUcW1a8gqKZM6BJ0SmFSEfGklG1mszSOT9VIBtUG6UxgpUxD+M CUdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q5sZk2IQIjptsv3a3XcSVTDNnG9U0oFxOYLINCyR7ko=; b=H82dwe59VgLMtwX+rjmqexad9Cf6r9KDP8IplLJOlMNz8CoyaNTH1x5SwBe+R3dJwM ULFhKP0O08eGG7dFvwldyfyJwFY+TWJKK7A0sRM5HmlRcN1OKO8nIdpHtN0UeBDFiRMs wH5vrl7xLOWnz9UEmuQ7BuXDN2eMMgkiIttRagjZF20/+ZVDGrR4+/VzddmFF96duoaE lJ3l1JHyeU8gwmGToGwItuWxkaMlKleitT4pyNche78uI2l5bn8WX2sk8GuRvYCmUiRD XwWAuZsggyNVsF/f3kTiatog5V36ZS+PJTfRqYj3aauRp0subbgd2y/D3Jhs7ZL99ThK H5jA== X-Gm-Message-State: AO0yUKUSDLaa7Z4Vm8jKUv41tIMca8fIDp+dmrao9R/YhETuKk3jXkFC i0aFQLGQCU3aQxrciyThCBh2kdCgl9yvTIeTnss= X-Google-Smtp-Source: AK7set93O/qzdokFmXeahEnSgyrY3TzQ/zMI0gMACigz23kRTXqExtsLjxvsXyzyUekoVirFeMEXJw== X-Received: by 2002:a17:902:d50f:b0:19a:a9d8:e480 with SMTP id b15-20020a170902d50f00b0019aa9d8e480mr7726350plg.68.1677033243206; Tue, 21 Feb 2023 18:34:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 17/25] target/arm: Handle no-execute for Realm and Root regimes Date: Tue, 21 Feb 2023 16:33:28 -1000 Message-Id: <20230222023336.915045-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033480319100001 Content-Type: text/plain; charset="utf-8" While Root and Realm may read and write data from other spaces, neither may execute from other pa spaces. This happens for Stage1 EL3, EL2, EL2&0, but stage2 EL1&0. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 52 ++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 46 insertions(+), 6 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 61c1227578..fc4c1ccf54 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -907,7 +907,7 @@ do_fault: * @xn: XN (execute-never) bits * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0 */ -static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) +static int get_S2prot_noexecute(int s2ap) { int prot =3D 0; =20 @@ -917,6 +917,12 @@ static int get_S2prot(CPUARMState *env, int s2ap, int = xn, bool s1_is_el0) if (s2ap & 2) { prot |=3D PAGE_WRITE; } + return prot; +} + +static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) +{ + int prot =3D get_S2prot_noexecute(s2ap); =20 if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) { switch (xn) { @@ -982,9 +988,39 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_= idx, bool is_aa64, } } =20 - if (out_pa =3D=3D ARMSS_NonSecure && in_pa =3D=3D ARMSS_Secure && - (env->cp15.scr_el3 & SCR_SIF)) { - return prot_rw; + if (in_pa !=3D out_pa) { + switch (in_pa) { + case ARMSS_Root: + /* + * R_ZWRVD: permission fault for insn fetched from non-Root, + * I_WWBFB: SIF has no effect in EL3. + */ + return prot_rw; + case ARMSS_Realm: + /* + * R_PKTDS: permission fault for insn fetched from non-Realm, + * for Realm EL2 or EL2&0. The corresponding fault for EL1&0 + * happens during any stage2 translation. + */ + switch (mmu_idx) { + case ARMMMUIdx_E2: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + return prot_rw; + default: + break; + } + break; + case ARMSS_Secure: + if (env->cp15.scr_el3 & SCR_SIF) { + return prot_rw; + } + break; + default: + /* Input NonSecure must have output NonSecure. */ + g_assert_not_reached(); + } } =20 /* TODO have_wxn should be replaced with @@ -1561,12 +1597,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, /* * R_GYNXY: For stage2 in Realm security state, bit 55 is NS. * The bit remains ignored for other security states. + * R_YMCSL: Executing an insn fetched from non-Realm causes + * a stage2 permission fault. */ if (out_space =3D=3D ARMSS_Realm && extract64(attrs, 55, 1)) { out_space =3D ARMSS_NonSecure; + result->f.prot =3D get_S2prot_noexecute(ap); + } else { + xn =3D extract64(attrs, 53, 2); + result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); } - xn =3D extract64(attrs, 53, 2); - result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); } else { int nse, ns =3D extract32(attrs, 5, 1); switch (out_space) { --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677033291; cv=none; d=zohomail.com; s=zohoarc; b=KFNe/GwANyHCy1bd0ulLo1A+Ku8Thp7CaTtvbqvPDjfQySyXKCJeawsvM6qUyR2SRw4B0IdXYqGVp3XtGke+RgdkgnUJL1l0X2YenCuaXFpkBv/BjUuPnaw5BdD0X8phtJCRPoa+A87UJ9jHDCPbXWLsSnkIuhiKU4ZtucNhj2M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677033291; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Q+0eq15fAwExTOnJJP3OmVXwymVtdfUriRFeQ7/we5Q=; b=L3sgfthhVo156X+5RtjkRD48neG64xAX/HEgHjSAus4J8dmgzYtkSayB8nnyUHikyvVMbegV1NkBH2ackSI8HOtRI5s7dc863p7eT/a18vXbADase95e4f5ilr3zQbHtUhoRZ48lLHhzZjaJjk7Zjgfd2Z1lFTFsSvfDX73Guj4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677033291606431.38706503304627; Tue, 21 Feb 2023 18:34:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pUexT-0007gU-Gb; Tue, 21 Feb 2023 21:34:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pUexO-0007XK-M5 for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:34:10 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pUexL-0001hW-5l for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:34:10 -0500 Received: by mail-pl1-x62b.google.com with SMTP id z2so7364134plf.12 for ; Tue, 21 Feb 2023 18:34:05 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.34.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q+0eq15fAwExTOnJJP3OmVXwymVtdfUriRFeQ7/we5Q=; b=QOrSOeJq/rkXq46oJl7o3x/XrDMyw7N7OEO5LBmI4fmYu+zyGt9vFUcgdnjDtK5VaR flXTgYpiAAGF7jaoMZvIqmgyMtx69rBzQpTlwoh438PQKKnTh5m+OK8w8SOcsCckv6sP EGxwYN8tRdcgn/9VmRctLzD/celBjtgn0bbRiFOY8LxVN7Ep9N3JIGDCnTS9+h6sC5zq pSpI/YdJ/ckTc1DAn1dMrODrfFFgaE4yxiTASMZu6FKFdRUKoPKssZ6dMvPiOTvUCmdD AS/OvDjT2NCLUoAVe6OwDA2LyN3eMTLHf9oQyVAVwgdKdJBmMEqca9bxTTV7PeTdUl2u JPqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q+0eq15fAwExTOnJJP3OmVXwymVtdfUriRFeQ7/we5Q=; b=HczJuvl5I/vF/UBqQVoEXeyarhrdqjGg2bY1K1akDF6WCyh3TTO2byFdaKHndNY33H JGKySMR/NfqKlzhnkhvfanqCjfI+z4lqkIHWpjqw5wVXGnoXw4sF5AUxfpakXG8ewJwl QNRh4AfTDuBS5mk5fyCxsha0gXDYUQa724CdAHDMA+D1swtZ2j5dOWeXcwz9y+kCtXBI +DH3U0XSthiAB1fks7mJUCm2+wcXZxmWJHcYSf2MghM+yoG8hmWwM8OHZJCGUyShomAs 4WlUhq8fuQ06pETBUQe5imvCnQ4Vkt186kUsyRA/fgxJEFI+gEo5u8SnfmBL/T8brY7n sXmg== X-Gm-Message-State: AO0yUKVOMA++udgWtQoAYXCJV4KshyykjYqDQNi9ANiamf55/10+p5YL J6ShSjbDbXTZ5PN1HzMRnEwGOSR3RC/7uHMCZB8= X-Google-Smtp-Source: AK7set8Lr/8uIQoUr0I3Y/lGSnSZGmz57IBpQMDC94QxPWvgJDZ/nIiEn0Fuh1n4UcEGXT3b8eTgRw== X-Received: by 2002:a17:903:2804:b0:196:1c45:6fc8 with SMTP id kp4-20020a170903280400b001961c456fc8mr7074025plb.60.1677033244687; Tue, 21 Feb 2023 18:34:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 18/25] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate Date: Tue, 21 Feb 2023 16:33:29 -1000 Message-Id: <20230222023336.915045-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033293538100005 Content-Type: text/plain; charset="utf-8" Do not provide a fast-path for physical addresses, as those will need to be validated for GPC. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 35 ++++++++++++++--------------------- 1 file changed, 14 insertions(+), 21 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index fc4c1ccf54..8a31af60c9 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -232,29 +232,22 @@ static bool S1_ptw_translate(CPUARMState *env, S1Tran= slate *ptw, * From gdbstub, do not use softmmu so that we don't modify the * state of the cpu at all, including softmmu tlb contents. */ - if (regime_is_stage2(s2_mmu_idx)) { - S1Translate s2ptw =3D { - .in_mmu_idx =3D s2_mmu_idx, - .in_ptw_idx =3D arm_space_to_phys(space), - .in_space =3D space, - .in_secure =3D is_secure, - .in_debug =3D true, - }; - GetPhysAddrResult s2 =3D { }; + S1Translate s2ptw =3D { + .in_mmu_idx =3D s2_mmu_idx, + .in_ptw_idx =3D arm_space_to_phys(space), + .in_space =3D space, + .in_secure =3D is_secure, + .in_debug =3D true, + }; + GetPhysAddrResult s2 =3D { }; =20 - if (get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD, - false, &s2, fi)) { - goto fail; - } - ptw->out_phys =3D s2.f.phys_addr; - pte_attrs =3D s2.cacheattrs.attrs; - pte_secure =3D s2.f.attrs.secure; - } else { - /* Regime is physical. */ - ptw->out_phys =3D addr; - pte_attrs =3D 0; - pte_secure =3D is_secure; + if (get_phys_addr_with_struct(env, &s2ptw, addr, + MMU_DATA_LOAD, &s2, fi)) { + goto fail; } + ptw->out_phys =3D s2.f.phys_addr; + pte_attrs =3D s2.cacheattrs.attrs; + pte_secure =3D s2.f.attrs.secure; ptw->out_host =3D NULL; ptw->out_rw =3D false; } else { --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677033371; cv=none; d=zohomail.com; s=zohoarc; b=Dj7GTlgbm4jWroW8hgpnc1V51ofpyb2W+GaOH7LCRQ12IO+8VK3vCT1AHNvLPl5oCQpB1yNRcKb/hzpQ7NWJVzERNX7M3qZpIazYbxQoFP56v6C3sQNQQRvCI27l2EiaGRTCpqtlbJnzp9DXGgLHxq/h7OjtyqYU/OzhsXy6nT8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677033371; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AEaPa3mWe3IpmNaEY7zBYHLgHnvDHdVZm/A7K3Apt8Y=; b=ixVBJdN+5MhzcVGd5eomURpE7S6adPHhDq07LRh9o8vmgNQz0NkoX2dUcb/fXGJAGulsqWxA9pCMv21UsOBdkv73BVpCnuealAmPTbmwL2uwZjIaw57e+IhDG5JlzTiR4ZgaPMzgYq7XX1ocG7Ic/b3wVXcsEx9TZZ0hTCf2eLY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677033371182885.1416448800984; Tue, 21 Feb 2023 18:36:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pUexS-0007en-DE; Tue, 21 Feb 2023 21:34:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pUexN-0007UM-25 for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:34:09 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pUexL-0001cv-5H for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:34:08 -0500 Received: by mail-pj1-x102c.google.com with SMTP id co23-20020a17090afe9700b002341fadc370so7074443pjb.1 for ; Tue, 21 Feb 2023 18:34:06 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.34.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AEaPa3mWe3IpmNaEY7zBYHLgHnvDHdVZm/A7K3Apt8Y=; b=slrKf1w6o8G4NW/9zKU1h5yPBXZfsL4a0cJB1a6Ukz/H9WhpisMiKUYSScCVykneJa pRoF2/UjqnD/Y234vXIg0/TfY/3B+I703ZaKROmjWTtEcMBYSKKy/Vpsf0AxVrNormEU aoMQruspCfS9lmKN5tFry+n9QemaobUjq888g5uH1HJGBm9ndf9/cLj0UgIssG5qImYs xPLTfuO0v9kveGUfFoW94jiEeeBZIrZ8nsgXIUMyJaqrEgH85VYzzu9vlqqc8PPA3/Y0 KASd27EMjIEsnnabDaNan28JO1hKNMLbuEGUd6HRJ/xXPpMTbsG2dv+v7OrrpxS6OaNg /YpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AEaPa3mWe3IpmNaEY7zBYHLgHnvDHdVZm/A7K3Apt8Y=; b=SwIcUKIJf5ncCMTZ4pBU7XfcrSrUBViTpf4QgrtdYVmcrbDsuCcDZpp8qFUmsuuZlQ ANwJ+RIW9VNFAFmojMxNYCtJZqiaAwts4vUy5nmmuyOhPWdvOgG1Ma19IObb42+mXkkr NVAWIWOi/LptKizLQEc+IjMTzoObotnsDOl6b1cRqnHAhTh55ot+nw9ZwEkZ47+c2HRV 2GK37BjkQaZ+xefhe9euHcRTM7tdOjWpEjkOu3VjwRRKzNgOYafjhIkHrG4hRKoGNt5H Ladr96+cRv0Bj9MkvJZKfkbA7IiqxzKXgNWBfmNC9KAmWpp3sklaKriT2EfG+RN4cYRS j4Zw== X-Gm-Message-State: AO0yUKWvNaHGiysZMHeIXBPvWBPzX8iqcHUGp5Am+FMo6v3FVwFhc6f0 PEM8Rwhm5ggmnmwZkjee8bHmUJbOW3yZNamZnHo= X-Google-Smtp-Source: AK7set9W7TU+isBsZ3L1PR8crxpUKb4fcNr2tSSqQ7O86wLIkYOqVdVN4nO7hQ0FcJqfbuNV5OE+gw== X-Received: by 2002:a17:902:f98d:b0:19a:ac93:64a with SMTP id ky13-20020a170902f98d00b0019aac93064amr6549667plb.18.1677033246130; Tue, 21 Feb 2023 18:34:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 19/25] target/arm: Move s1_is_el0 into S1Translate Date: Tue, 21 Feb 2023 16:33:30 -1000 Message-Id: <20230222023336.915045-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033371860100001 Content-Type: text/plain; charset="utf-8" Instead of passing this to get_phys_addr_lpae, stash it in the S1Translate structure. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/ptw.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8a31af60c9..6fa3d33a4e 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -22,6 +22,12 @@ typedef struct S1Translate { ARMSecuritySpace in_space; bool in_secure; bool in_debug; + /* + * If this is stage 2 of a stage 1+2 page table walk, then this must + * be true if stage 1 is an EL0 access; otherwise this is ignored. + * Stage 2 is indicated by in_mmu_idx set to ARMMMUIdx_Stage2{,_S}. + */ + bool in_s1_is_el0; bool out_secure; bool out_rw; bool out_be; @@ -32,8 +38,7 @@ typedef struct S1Translate { } S1Translate; =20 static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, - uint64_t address, - MMUAccessType access_type, bool s1_is_el0, + uint64_t address, MMUAccessType access_type, GetPhysAddrResult *result, ARMMMUFaultInfo = *fi); =20 static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, @@ -1255,17 +1260,12 @@ static int check_s2_mmu_setup(ARMCPU *cpu, bool is_= aa64, uint64_t tcr, * @ptw: Current and next stage parameters for the walk. * @address: virtual address to get physical address for * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH - * @s1_is_el0: if @ptw->in_mmu_idx is ARMMMUIdx_Stage2 - * (so this is a stage 2 page table walk), - * must be true if this is stage 2 of a stage 1+2 - * walk for an EL0 access. If @mmu_idx is anything else, - * @s1_is_el0 is ignored. * @result: set on translation success, * @fi: set to fault info if the translation fails */ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, uint64_t address, - MMUAccessType access_type, bool s1_is_el0, + MMUAccessType access_type, GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) { ARMCPU *cpu =3D env_archcpu(env); @@ -1598,7 +1598,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, result->f.prot =3D get_S2prot_noexecute(ap); } else { xn =3D extract64(attrs, 53, 2); - result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); + result->f.prot =3D get_S2prot(env, ap, xn, ptw->in_s1_is_el0); } } else { int nse, ns =3D extract32(attrs, 5, 1); @@ -2820,7 +2820,6 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, bool ret, ipa_secure, s2walk_secure; ARMCacheAttrs cacheattrs1; ARMSecuritySpace ipa_space, s2walk_space; - bool is_el0; uint64_t hcr; =20 ret =3D get_phys_addr_with_struct(env, ptw, address, access_type, resu= lt, fi); @@ -2845,7 +2844,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, s2walk_space =3D ipa_space; } =20 - is_el0 =3D ptw->in_mmu_idx =3D=3D ARMMMUIdx_Stage1_E0; + ptw->in_s1_is_el0 =3D ptw->in_mmu_idx =3D=3D ARMMMUIdx_Stage1_E0; ptw->in_mmu_idx =3D s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Sta= ge2; ptw->in_ptw_idx =3D arm_space_to_phys(s2walk_space); ptw->in_secure =3D s2walk_secure; @@ -2864,8 +2863,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, ret =3D get_phys_addr_pmsav8(env, ipa, access_type, ptw->in_mmu_idx, is_secure, result, fi); } else { - ret =3D get_phys_addr_lpae(env, ptw, ipa, access_type, - is_el0, result, fi); + ret =3D get_phys_addr_lpae(env, ptw, ipa, access_type, result, fi); } fi->s2addr =3D ipa; =20 @@ -3041,8 +3039,7 @@ static bool get_phys_addr_with_struct(CPUARMState *en= v, S1Translate *ptw, } =20 if (regime_using_lpae_format(env, mmu_idx)) { - return get_phys_addr_lpae(env, ptw, address, access_type, false, - result, fi); + return get_phys_addr_lpae(env, ptw, address, access_type, result, = fi); } else if (arm_feature(env, ARM_FEATURE_V7) || regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, ptw, address, access_type, result, fi= ); --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677033484; cv=none; d=zohomail.com; s=zohoarc; b=n0mr55s1V0Zl+hsGJnNKsa4XHyKSr7jIanM8Ibhs0Iryz/IQMY46F87Ll/ZwndhqbzyEWPuZxldVPi48rwlwukITWM+8iJ8Z6nubSuRk0/9AeQa5ObncD5H0R2pwQs88GsNdZEY/SRFMonbP/c4++/3heZ6rZYPV97MDTR/ZSj8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677033484; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PhxQ9e9pVV9RyCPmKQ2M0WUBfbr0akWOWFlqn9fFR48=; b=G0pPyquevwhWAol5N8aSMlBeoFkt13oW2CV90IyqAc1C3/i5TsvufA34Kb+T5ZEW81YkqeYN4WWR32APndNASD7h48rfDWLl4lRMON+vHjPpG+79Y4oqkvh9HPy9LoWegT2CIOYTtiGP3knp1Y0vBZgwgHXVV60xYCL/vdwQb+c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677033484012936.1272567200907; Tue, 21 Feb 2023 18:38:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pUexU-0007ht-By; Tue, 21 Feb 2023 21:34:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pUexP-0007Zh-NS for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:34:11 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pUexM-0001iL-Jy for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:34:11 -0500 Received: by mail-pj1-x1031.google.com with SMTP id c23so2379442pjo.4 for ; Tue, 21 Feb 2023 18:34:08 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.34.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PhxQ9e9pVV9RyCPmKQ2M0WUBfbr0akWOWFlqn9fFR48=; b=ElH/lQgU1lUWROxso2hhGUR7CpV70Htl3OQkwUrxntluMvqtXu1LEXdAgvT7zKyLRX /MlM1+ziqlBbBW/h+IEW81iHMA9xey0wm2VmmfS6puPIooLD8ntrnmBtwZpkYRlXO3Yt g4olycpluVe2VZBc7VJCVgq3NeEQ+mYsfQk8N8h2Y9HRGybbMgjlc1VKPd6PtTc8R+H2 mX+hMFn+Q4qe6neYvl4w9bUKEm4RC4rzsFaoMAVM9xM0yh88dQa8zcL7dM00M1q7lrTG pZl3YIEAOflwR2kX/qchxoHxiYyg5McGWiBsEbn6yZLSA1pG7Rtn75drpf+VTxYvL1nx izHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PhxQ9e9pVV9RyCPmKQ2M0WUBfbr0akWOWFlqn9fFR48=; b=RJMI9aPpgjCU+5gqPTFkAayHwlNKC5ArshN6MlCqKUbszp9M/5r1RmUrc6nx52QXos oTqPkl73Uo4knXYyuQkbKQO4p+yPZz/S3lIHUIa7qvRelou5QrE2CyK8lFyyyU8Jz/Lf 6ZA6uMYGjdJJkyT/GN4NBg8/6NdfwGzwUCRXzGKIso2d/TJRy55CNlLYSIN/0viMGa0V HTvn92/5kw8LRGrLBrhOD8/UerPkOrA23G/qth5HVaGmimfDSI3/HUBqaNrcNwHVDKOQ mJcaFIRqcJ93RToqAB5Pk+F1lYAbt5YkJwkYRRyMruRLBaej7Pj8mtUn1WodN7EEzMSr N+Kw== X-Gm-Message-State: AO0yUKWeLZcu2thdlXxylpNsd708joq4FPS7wQr4jpndcDoHoPjnCNRD lGNHzVgkv9COOHWeEFbKv9vFmDEClw0vnELB/Do= X-Google-Smtp-Source: AK7set8d5hS4pvCS7C5xzLtUJ+at+eJxfQTeFT/w5wXNFojPqt+bmm9FWQBSeiQs6VMwSCQR5u9/JA== X-Received: by 2002:a17:903:2345:b0:196:3feb:1f1e with SMTP id c5-20020a170903234500b001963feb1f1emr9489627plh.47.1677033247402; Tue, 21 Feb 2023 18:34:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v3 20/25] target/arm: Use get_phys_addr_with_struct for stage2 Date: Tue, 21 Feb 2023 16:33:31 -1000 Message-Id: <20230222023336.915045-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033484357100002 Content-Type: text/plain; charset="utf-8" This fixes a bug in which we failed to initialize the result attributes properly after the memset. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/ptw.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6fa3d33a4e..7e1aa34d24 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -37,10 +37,6 @@ typedef struct S1Translate { void *out_host; } S1Translate; =20 -static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, - uint64_t address, MMUAccessType access_type, - GetPhysAddrResult *result, ARMMMUFaultInfo = *fi); - static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, target_ulong address, MMUAccessType access_type, @@ -2859,12 +2855,7 @@ static bool get_phys_addr_twostage(CPUARMState *env,= S1Translate *ptw, cacheattrs1 =3D result->cacheattrs; memset(result, 0, sizeof(*result)); =20 - if (arm_feature(env, ARM_FEATURE_PMSA)) { - ret =3D get_phys_addr_pmsav8(env, ipa, access_type, - ptw->in_mmu_idx, is_secure, result, fi); - } else { - ret =3D get_phys_addr_lpae(env, ptw, ipa, access_type, result, fi); - } + ret =3D get_phys_addr_with_struct(env, ptw, ipa, access_type, result, = fi); fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677033464; cv=none; d=zohomail.com; s=zohoarc; b=YvdVZLYazoIMn0lRNn/b9wM4LhYQN7yMON8yU8XaqypAEUP2ZT00bjAI+Ud6HB0KF9veS0BWWZikj6deSzEGdbQVqeBQtNlxVayxaDJabkrYN6XX3OJXDTqsAL13KVuBZjMwYhp5mI72hnWddAMGyZjgOezReB8nNb/QUdicnr8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677033464; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BdnIrBC/vjhypfMOEhRm01STyDVGWe2QDHvXiznUOKk=; b=LIBfE75StY73UU5fwuIvdaygtxsN64eWeUcFngtYBnD/EXIRhVY8TuHTDmCpONpuDs05X+c6uHW7AIAy5ax6FwAfUF/ZioiLXW7qiOkGWza0OhYh8s7SMFIcTXIrnYoYeM3I0vd46FQQ9TJmIFNLWOW5tvWhT7TdjD03RqZ49o4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167703346491060.15356866101172; Tue, 21 Feb 2023 18:37:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pUexV-0007iV-Pp; Tue, 21 Feb 2023 21:34:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pUexQ-0007b5-Cy for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:34:12 -0500 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pUexO-0001ic-9Q for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:34:12 -0500 Received: by mail-pl1-x634.google.com with SMTP id h14so7359574plf.10 for ; Tue, 21 Feb 2023 18:34:09 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.34.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BdnIrBC/vjhypfMOEhRm01STyDVGWe2QDHvXiznUOKk=; b=zso61bsFfah/MWT18NzTF8AtAjKsks4Cy/ph/tOiuBaHnIsiuTMfL5WUCUkzGw197O AU12Noq9Gk+EddplGG2EKL4PxO2XGm33hnyig73x57Rf2WYR7II8HvgvdfIxGq1F0hvu HJo0N3OMq9CVRT0wYmD/Y2VPFAGsLIW6MQsIP7Vhf2LLZ7sQJza/J2Fr7PCwZwQJNN/o zluuikVoSg47bYg3Amolmamt4K0fHji+DfDRkeKrCc+SWh+iRVZwEEcqu9kAdTy85tCP Hu1sZjgzbzr9X2sf84JKxAExnpv1jk2fFq9KuH4HBFZXjic8BfwG0VpuS7sC0DcwL5es 6fGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BdnIrBC/vjhypfMOEhRm01STyDVGWe2QDHvXiznUOKk=; b=rwZsVhAAxumSmiFvB6sqkgx9SckCFgQAPwpnZy+6eIWOmJbT9IYGlG32Cgq34OwDQR Ah4X69HZzoBOn01H+cxZte4SV9Yb/VcwKB/enqa5N34325iY6xm2vLYhuyGb29PEIV0w TPGtli+CHlwX4I+BT65LckxCvd9tz0Lz5ae2f3XmSVtPeKh/9iKo67u3/aat2xhb/0lr jgRLt0f/wa2SRm5bQuZ5lvTCVy6mPRCdteGctWVdD8rPiKfpd5EKrNFB1MRRIxPHoufg uH+9mp1czr5sCmjdZFuIbQQjbtoiNe2531jjHNw4gi4gpd9tZPad87hNYmxfajwq6I5z hYEw== X-Gm-Message-State: AO0yUKXJ8MEli/SrjAoKINqjsCXeWj2tgu9hy/iyO9VGFDBqaHaCjPBy cReCvc0n3WnvitOfIiW1WkJFyqjuo+ZHPluc+d0= X-Google-Smtp-Source: AK7set/H/Z7/geyaZqHx19OYK7JmcWtcp8/w8mI1+53aQ3rA0PpCkw3XR8QBtPET8eNw2y60V5tYdQ== X-Received: by 2002:a17:902:6bcb:b0:19a:ae81:b09b with SMTP id m11-20020a1709026bcb00b0019aae81b09bmr7346310plt.11.1677033248751; Tue, 21 Feb 2023 18:34:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 21/25] target/arm: Add GPC syndrome Date: Tue, 21 Feb 2023 16:33:32 -1000 Message-Id: <20230222023336.915045-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033466189100001 Content-Type: text/plain; charset="utf-8" The function takes the fields as filled in by the Arm ARM pseudocode for TakeGPCException. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/syndrome.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index d27d1bc31f..62254d0e51 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -50,6 +50,7 @@ enum arm_exception_class { EC_SVEACCESSTRAP =3D 0x19, EC_ERETTRAP =3D 0x1a, EC_SMETRAP =3D 0x1d, + EC_GPC =3D 0x1e, EC_INSNABORT =3D 0x20, EC_INSNABORT_SAME_EL =3D 0x21, EC_PCALIGNMENT =3D 0x22, @@ -247,6 +248,15 @@ static inline uint32_t syn_bxjtrap(int cv, int cond, i= nt rm) (cv << 24) | (cond << 20) | rm; } =20 +static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, + int cm, int s1ptw, int wnr, int fsc) +{ + /* TODO: FEAT_NV2 adds VNCR */ + return (EC_GPC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (s2ptw << 21) + | (ind << 20) | (gpcsc << 14) | (cm << 8) | (s1ptw << 7) + | (wnr << 6) | fsc; +} + static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int = fsc) { return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677033428; cv=none; d=zohomail.com; s=zohoarc; b=JpHuot0jT3SLD7Ajlt/M5a6UrpGuHrfSN4H00hG2HqWJ0lwcVbNr8rDESawXi/kPw3amS+1Hsg+vW9yRp6m46wTvDCbDAFgOlYZbtU0fWOy1NAXrXyylQ1QWi2nbVPHrKOwXAlINhMVeNt4IyjZzdcxqy9/Eew6yqt7XpDtZpJo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677033428; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OvOoJ884ZN5PW2Z4ZXukQZSOfuuCRAHBihmEoUNUOLo=; b=n1BX1xP3Ar0+Z8r+iV628D2prgAkt6eRhf1NpcVlEhdA2m5yAhvYySfg9ZZrKxvggMuNjub66gitKt5Kiu3U0UEtIVELJYzvFVMP//ROk7QBBjIVZVzZWzS0saeMKtMSidlmK0cK7JeFcsIhxWGoJiqOdzoWPBUSk4ZEUxdb3ug= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677033428614252.5141911725117; Tue, 21 Feb 2023 18:37:08 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pUexV-0007iN-Do; Tue, 21 Feb 2023 21:34:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pUexR-0007d7-MP for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:34:13 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pUexP-0001j9-Gy for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:34:13 -0500 Received: by mail-pl1-x636.google.com with SMTP id h14so7359616plf.10 for ; Tue, 21 Feb 2023 18:34:11 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.34.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OvOoJ884ZN5PW2Z4ZXukQZSOfuuCRAHBihmEoUNUOLo=; b=N6jHqZ4aZDKf3nxPsVs+hE4snZTvXqicPTWd6nIP+SlqH5PVVluW/KeQre+PFG+gLf nvy/jj8XyO4p3qe2pwzMHmEqqNxVr2s6vZ7dwlhq74ggoUsNjRMp90EdVvonTHMnUYYW vQKuu3vMxgLTjclfYYcITA7Yg/0ptvK6MxJGevmPkSj4IRabFGiFmRtJpE2YyEPET9Jy ZIbYCviFcSqe7UeGwpWnVQXBSuA8vaDFC5mmxOtlqAlQOCXxhQXa0FdNcfFmIg/cE+3h k5vSkkf4XrNi5DznIqxQejcs/fmmCGqV45kTc+WWqCwjCYrqxNhOzFQzxyf0hI0RwKr4 X9gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OvOoJ884ZN5PW2Z4ZXukQZSOfuuCRAHBihmEoUNUOLo=; b=ULWzCZqvi83aemeN4aYY3VWoJFsxiZkaLDR9UorfcsEtfRCeJSfMrxhofrXk2ijcfD Qy0JmjLN9uTAgCJrMB3KG5eOEUCIgjujFZucDwOZyXFT1PnLS2HWErzsnsq2oicrALF2 MwRg2s+JPhlGtD9kJjzHvXziaCmyqeDWcXPH/MiBcRZa6F/Fu4cIX5JvNq7mwB3tZb6T AJXGEkYqlhFMvKPVFHNf+UNXcBzrMExgZ1Q0rxwLPrTbath3hNOErfArIK82HvUUyhmq FlyFmtsjA7jl8ceusfpCScUzEQ4ZmRzwzrTQxbfLissNZcsnVvZO9yvSNGGtnMeGXJ+y wR6w== X-Gm-Message-State: AO0yUKWtq2NylajCCUL3r+z+UP3MZi+RW2yu67tIPppACpQvNHSMw/PQ dtrCdvO2Tgc/pNdbTet8eBrXseAM9Aog5Eoompk= X-Google-Smtp-Source: AK7set+a/gkpGKG0LHR0r2G05OOzmAxui9UDD936taIZnapyezuYyVjafeFKphKRgS4m07999bVZWg== X-Received: by 2002:a17:902:c404:b0:19a:81cd:a385 with SMTP id k4-20020a170902c40400b0019a81cda385mr7309733plk.19.1677033250115; Tue, 21 Feb 2023 18:34:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 22/25] target/arm: Implement GPC exceptions Date: Tue, 21 Feb 2023 16:33:33 -1000 Message-Id: <20230222023336.915045-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033430080100001 Content-Type: text/plain; charset="utf-8" Handle GPC Fault types in arm_deliver_fault, reporting as either a GPC exception at EL3, or falling through to insn or data aborts at various exception levels. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/internals.h | 27 ++++++++++++ target/arm/helper.c | 5 +++ target/arm/tlb_helper.c | 96 +++++++++++++++++++++++++++++++++++++++-- 4 files changed, 126 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 05fd6e61aa..b189efadf8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -57,6 +57,7 @@ #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ #define EXCP_VSERR 24 +#define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ =20 #define ARMV7M_EXCP_RESET 1 diff --git a/target/arm/internals.h b/target/arm/internals.h index 759b70c646..5e88649fea 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -352,14 +352,27 @@ typedef enum ARMFaultType { ARMFault_ICacheMaint, ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */ ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */ + ARMFault_GPCFOnWalk, + ARMFault_GPCFOnOutput, } ARMFaultType; =20 +typedef enum ARMGPCF { + GPCF_None, + GPCF_AddressSize, + GPCF_Walk, + GPCF_EABT, + GPCF_Fail, +} ARMGPCF; + /** * ARMMMUFaultInfo: Information describing an ARM MMU Fault * @type: Type of fault + * @gpcf: Subtype of ARMFault_GPCFOn{Walk,Output}. * @level: Table walk level (for translation, access flag and permission f= aults) * @domain: Domain of the fault address (for non-LPAE CPUs only) * @s2addr: Address that caused a fault at stage 2 + * @paddr: physical address that caused a fault for gpc + * @paddr_space: physical address space that caused a fault for gpc * @stage2: True if we faulted at stage 2 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table = walk * @s1ns: True if we faulted on a non-secure IPA while in secure state @@ -368,7 +381,10 @@ typedef enum ARMFaultType { typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; struct ARMMMUFaultInfo { ARMFaultType type; + ARMGPCF gpcf; target_ulong s2addr; + target_ulong paddr; + ARMSecuritySpace paddr_space; int level; int domain; bool stage2; @@ -542,6 +558,17 @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo = *fi) case ARMFault_Exclusive: fsc =3D 0x35; break; + case ARMFault_GPCFOnWalk: + assert(fi->level >=3D -1 && fi->level <=3D 3); + if (fi->level < 0) { + fsc =3D 0b100011; + } else { + fsc =3D 0b100100 | fi->level; + } + break; + case ARMFault_GPCFOnOutput: + fsc =3D 0b101000; + break; default: /* Other faults can't occur in a context that requires a * long-format status code. diff --git a/target/arm/helper.c b/target/arm/helper.c index 9e1c1ed6d8..dc97dc120b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10238,6 +10238,7 @@ void arm_log_exception(CPUState *cs) [EXCP_UNALIGNED] =3D "v7M UNALIGNED UsageFault", [EXCP_DIVBYZERO] =3D "v7M DIVBYZERO UsageFault", [EXCP_VSERR] =3D "Virtual SERR", + [EXCP_GPC] =3D "Granule Protection Check", }; =20 if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { @@ -10966,6 +10967,10 @@ static void arm_cpu_do_interrupt_aarch64(CPUState = *cs) } =20 switch (cs->exception_index) { + case EXCP_GPC: + qemu_log_mask(CPU_LOG_INT, "...with MFAR 0x%" PRIx64 "\n", + env->cp15.mfar_el3); + /* fall through */ case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: /* diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 60abcbebe6..aa03d3f8dc 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -109,17 +109,106 @@ static uint32_t compute_fsr_fsc(CPUARMState *env, AR= MMMUFaultInfo *fi, return fsr; } =20 +static bool report_as_gpc_exception(ARMCPU *cpu, int current_el, + ARMMMUFaultInfo *fi) +{ + bool ret; + + switch (fi->gpcf) { + case GPCF_None: + return false; + case GPCF_AddressSize: + case GPCF_Walk: + case GPCF_EABT: + /* R_PYTGX: GPT faults are reported as GPC. */ + ret =3D true; + break; + case GPCF_Fail: + /* + * R_BLYPM: A GPF at EL3 is reported as insn or data abort. + * R_VBZMW, R_LXHQR: A GPF at EL[0-2] is reported as a GPC + * if SCR_EL3.GPF is set, otherwise an insn or data abort. + */ + ret =3D (cpu->env.cp15.scr_el3 & SCR_GPF) && current_el !=3D 3; + break; + default: + g_assert_not_reached(); + } + + assert(cpu_isar_feature(aa64_rme, cpu)); + assert(fi->type =3D=3D ARMFault_GPCFOnWalk || + fi->type =3D=3D ARMFault_GPCFOnOutput); + if (fi->gpcf =3D=3D GPCF_AddressSize) { + assert(fi->level =3D=3D 0); + } else { + assert(fi->level >=3D 0 && fi->level <=3D 1); + } + + return ret; +} + +static unsigned encode_gpcsc(ARMMMUFaultInfo *fi) +{ + static uint8_t const gpcsc[] =3D { + [GPCF_AddressSize] =3D 0b000000, + [GPCF_Walk] =3D 0b000100, + [GPCF_Fail] =3D 0b001100, + [GPCF_EABT] =3D 0b010100, + }; + + /* Note that we've validated fi->gpcf and fi->level above. */ + return gpcsc[fi->gpcf] | fi->level; +} + static G_NORETURN void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, ARMMMUFaultInfo *fi) { CPUARMState *env =3D &cpu->env; - int target_el; + int target_el =3D exception_target_el(env); + int current_el =3D arm_current_el(env); bool same_el; uint32_t syn, exc, fsr, fsc; =20 - target_el =3D exception_target_el(env); + if (report_as_gpc_exception(cpu, current_el, fi)) { + target_el =3D 3; + + fsr =3D compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); + + syn =3D syn_gpc(fi->stage2 && fi->type =3D=3D ARMFault_GPCFOnWalk, + access_type =3D=3D MMU_INST_FETCH, + encode_gpcsc(fi), 0, fi->s1ptw, + access_type =3D=3D MMU_DATA_STORE, fsc); + + env->cp15.mfar_el3 =3D fi->paddr; + switch (fi->paddr_space) { + case ARMSS_Secure: + break; + case ARMSS_NonSecure: + env->cp15.mfar_el3 |=3D R_MFAR_NS_MASK; + break; + case ARMSS_Root: + env->cp15.mfar_el3 |=3D R_MFAR_NSE_MASK; + break; + case ARMSS_Realm: + env->cp15.mfar_el3 |=3D R_MFAR_NSE_MASK | R_MFAR_NS_MASK; + break; + default: + g_assert_not_reached(); + } + + exc =3D EXCP_GPC; + goto do_raise; + } + + /* If SCR_EL3.GPF is unset, GPF may still be routed to EL2. */ + if (fi->gpcf =3D=3D GPCF_Fail && target_el < 2) { + if (arm_hcr_el2_eff(env) & HCR_GPF) { + target_el =3D 2; + } + } + if (fi->stage2) { target_el =3D 2; env->cp15.hpfar_el2 =3D extract64(fi->s2addr, 12, 47) << 4; @@ -127,8 +216,8 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, env->cp15.hpfar_el2 |=3D HPFAR_NS; } } - same_el =3D (arm_current_el(env) =3D=3D target_el); =20 + same_el =3D current_el =3D=3D target_el; fsr =3D compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); =20 if (access_type =3D=3D MMU_INST_FETCH) { @@ -146,6 +235,7 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, exc =3D EXCP_DATA_ABORT; } =20 + do_raise: env->exception.vaddress =3D addr; env->exception.fsr =3D fsr; raise_exception(env, exc, syn, target_el); --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677033295; cv=none; d=zohomail.com; s=zohoarc; b=eAX69kJtT4/FE5rh6k3ew6vTOlE6+q1N5Iypw5KU9RozyRRk7FJJFpP6P4K6o4Vpwb5geCzkQ5K2D74KKgVh+X4xfZVy+sFaL8zNfOGgSKcNC+Avmdj6lMhPAfImr6sbdGCLoQtY938EWZZHdHlNBcpcWGkoCBHFHb+MOJd4YPg= ARC-Message-Signature: i=1; a=rsa-sha256; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.34.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oqSxlFeqnksS26HlRcUCdvEjkW4madPTcppYBetzNJs=; b=DI223kiD+93tF49qXoPYwZyOnIFs3CKSXx8QELIZv4F4A+6yR3JlyZiw8Po5HNx4Ph Q4rZ0wVLXyWYB6AHBjsXtcfpQBAuobgdGm7O9Mf0qJXLsBBNxE7sUjdg/ejif3ygejHG 6lt1Pb+vNJg3Cb2esS/M2Kk/y1wP7KIZDEVxOJZzQJiPosZhosfxVPn+iwCdiETufOFb YkXfSSzHqm/lxezxxKdakKQNdz6BP314ojqSRxVDGlPbcriduFI3kc3nGwcJNL3zTLor 0k3vwHqPitjNKrOF28Ttacx0gLN2Mf9/s17FPomkOXEPVM2KfG0dTIDk0Q5nqc8qS8KE N8bQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oqSxlFeqnksS26HlRcUCdvEjkW4madPTcppYBetzNJs=; b=3EplBhy94DHPD8+JyO1WYu17nIb692Ms8Alw952lcf4WU1k8EAJGyqJGSB5ybKQQpa tQDVIJe9CDB9cnzP8tlpGhZKeiq4DtdVdh+RL4V6BonMl+GLdP2dxMgP9vnGdoYFsKix Vo105RTX+QCbPCD1EChOfwBWmNg6L9fpHHK+EWlqEKsNe8wgWirYk8d7N0Fa12OjGnMx YUHzYs08DXqgLgQvYEZRH0u/8QhWLjqN7Y+AivJIPNe2fifYWrsDqg54wgznghNzEZD3 3yfR4YBaBy73T5BtBRzsNoXkMUwQHLkIklc96vxstTktOhVb0P/TRO9+pUNaqhLuI79i KqeA== X-Gm-Message-State: AO0yUKVoghQZ34W+lO5MwmVeuwYHSxCVP6s4Y2cXTxI95nELv8XpIk00 EJlt3OlSJyGkbReCPuhbphfsgXMP4aaWb7aJ+MZVUQ== X-Google-Smtp-Source: AK7set8/9p+ptpTSYSNtMWhUu66do95UxBlLVvHepLWQIz1bSkuEAw7E7XOUzh588DmKXeb6mIERmw== X-Received: by 2002:a17:903:247:b0:19a:80fe:1f4 with SMTP id j7-20020a170903024700b0019a80fe01f4mr10994329plh.12.1677033251713; Tue, 21 Feb 2023 18:34:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v3 23/25] target/arm: Implement the granule protection check Date: Tue, 21 Feb 2023 16:33:34 -1000 Message-Id: <20230222023336.915045-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x643.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033297582100001 Content-Type: text/plain; charset="utf-8" Place the check at the end of get_phys_addr_with_struct, so that we check all physical results. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 249 +++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 232 insertions(+), 17 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 7e1aa34d24..8fa4849aaa 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -37,11 +37,17 @@ typedef struct S1Translate { void *out_host; } S1Translate; =20 -static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, - target_ulong address, - MMUAccessType access_type, - GetPhysAddrResult *result, - ARMMMUFaultInfo *fi); +static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, + target_ulong address, + MMUAccessType access_type, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi); + +static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, + target_ulong address, + MMUAccessType access_type, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi); =20 /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. = */ static const uint8_t pamax_map[] =3D { @@ -197,6 +203,197 @@ static bool regime_translation_disabled(CPUARMState *= env, ARMMMUIdx mmu_idx, return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; } =20 +static bool granule_protection_check(CPUARMState *env, uint64_t paddress, + ARMSecuritySpace pspace, + ARMMMUFaultInfo *fi) +{ + MemTxAttrs attrs =3D { + .secure =3D true, + .space =3D ARMSS_Root, + }; + ARMCPU *cpu =3D env_archcpu(env); + uint64_t gpccr =3D env->cp15.gpccr_el3; + unsigned pps, pgs, l0gptsz, level =3D 0; + uint64_t tableaddr, pps_mask, align, entry, index; + AddressSpace *as; + MemTxResult result; + int gpi; + + if (!FIELD_EX64(gpccr, GPCCR, GPC)) { + return true; + } + + /* + * GPC Priority 1 (R_GMGRR): + * R_JWCSM: If the configuration of GPCCR_EL3 is invalid, + * the access fails as GPT walk fault at level 0. + */ + + /* + * Configuration of PPS to a value exceeding the implemented + * physical address size is invalid. + */ + pps =3D FIELD_EX64(gpccr, GPCCR, PPS); + if (pps > FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE)) { + goto fault_walk; + } + pps =3D pamax_map[pps]; + pps_mask =3D MAKE_64BIT_MASK(0, pps); + + switch (FIELD_EX64(gpccr, GPCCR, SH)) { + case 0b10: /* outer shareable */ + break; + case 0b00: /* non-shareable */ + case 0b11: /* inner shareable */ + /* Inner and Outer non-cacheable requires Outer shareable. */ + if (FIELD_EX64(gpccr, GPCCR, ORGN) =3D=3D 0 && + FIELD_EX64(gpccr, GPCCR, IRGN) =3D=3D 0) { + goto fault_walk; + } + break; + default: /* reserved */ + goto fault_walk; + } + + switch (FIELD_EX64(gpccr, GPCCR, PGS)) { + case 0b00: /* 4KB */ + pgs =3D 12; + break; + case 0b01: /* 64KB */ + pgs =3D 16; + break; + case 0b10: /* 16KB */ + pgs =3D 14; + break; + default: /* reserved */ + goto fault_walk; + } + + /* Note this field is read-only and fixed at reset. */ + l0gptsz =3D 30 + FIELD_EX64(gpccr, GPCCR, L0GPTSZ); + + /* + * GPC Priority 2: Secure, Realm or Root address exceeds PPS. + * R_CPDSB: A NonSecure physical address input exceeding PPS + * does not experience any fault. + */ + if (paddress & ~pps_mask) { + if (pspace =3D=3D ARMSS_NonSecure) { + return true; + } + goto fault_size; + } + + /* GPC Priority 3: the base address of GPTBR_EL3 exceeds PPS. */ + tableaddr =3D env->cp15.gptbr_el3 << 12; + if (tableaddr & ~pps_mask) { + goto fault_size; + } + + /* + * BADDR is aligned per a function of PPS and L0GPTSZ. + * These bits of GPTBR_EL3 are RES0, but are not a configuration error, + * unlike the RES0 bits of the GPT entries (R_XNKFZ). + */ + align =3D MAX(pps - l0gptsz + 3, 12); + align =3D MAKE_64BIT_MASK(0, align); + tableaddr &=3D ~align; + + as =3D arm_addressspace(env_cpu(env), attrs); + + /* Level 0 lookup. */ + index =3D extract64(paddress, l0gptsz, pps - l0gptsz); + tableaddr +=3D index * 8; + entry =3D address_space_ldq_le(as, tableaddr, attrs, &result); + if (result !=3D MEMTX_OK) { + goto fault_eabt; + } + + switch (extract32(entry, 0, 4)) { + case 1: /* block descriptor */ + if (entry >> 8) { + goto fault_walk; /* RES0 bits not 0 */ + } + gpi =3D extract32(entry, 4, 4); + goto found; + case 3: /* table descriptor */ + tableaddr =3D entry & ~0xf; + align =3D MAX(l0gptsz - pgs - 1, 12); + align =3D MAKE_64BIT_MASK(0, align); + if (tableaddr & (~pps_mask | align)) { + goto fault_walk; /* RES0 bits not 0 */ + } + break; + default: /* invalid */ + goto fault_walk; + } + + /* Level 1 lookup */ + level =3D 1; + index =3D extract64(paddress, pgs + 4, l0gptsz - pgs - 4); + tableaddr +=3D index * 8; + entry =3D address_space_ldq_le(as, tableaddr, attrs, &result); + if (result !=3D MEMTX_OK) { + goto fault_eabt; + } + + switch (extract32(entry, 0, 4)) { + case 1: /* contiguous descriptor */ + if (entry >> 10) { + goto fault_walk; /* RES0 bits not 0 */ + } + /* + * Because the softmmu tlb only works on units of TARGET_PAGE_SIZE, + * and because we cannot invalidate by pa, and thus will always + * flush entire tlbs, we don't actually care about the range here + * and can simply extract the GPI as the result. + */ + if (extract32(entry, 8, 2) =3D=3D 0) { + goto fault_walk; /* reserved contig */ + } + gpi =3D extract32(entry, 4, 4); + break; + default: + index =3D extract64(paddress, pgs, 4); + gpi =3D extract64(entry, index * 4, 4); + break; + } + + found: + switch (gpi) { + case 0b0000: /* no access */ + break; + case 0b1111: /* all access */ + return true; + case 0b1000: + case 0b1001: + case 0b1010: + case 0b1011: + if (pspace =3D=3D (gpi & 3)) { + return true; + } + break; + default: + goto fault_walk; /* reserved */ + } + + fi->gpcf =3D GPCF_Fail; + goto fault_common; + fault_eabt: + fi->gpcf =3D GPCF_EABT; + goto fault_common; + fault_size: + fi->gpcf =3D GPCF_AddressSize; + goto fault_common; + fault_walk: + fi->gpcf =3D GPCF_Walk; + fault_common: + fi->level =3D level; + fi->paddr =3D paddress; + fi->paddr_space =3D pspace; + return false; +} + static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) { /* @@ -242,10 +439,10 @@ static bool S1_ptw_translate(CPUARMState *env, S1Tran= slate *ptw, }; GetPhysAddrResult s2 =3D { }; =20 - if (get_phys_addr_with_struct(env, &s2ptw, addr, - MMU_DATA_LOAD, &s2, fi)) { + if (get_phys_addr_gpc(env, &s2ptw, addr, MMU_DATA_LOAD, &s2, fi)) { goto fail; } + ptw->out_phys =3D s2.f.phys_addr; pte_attrs =3D s2.cacheattrs.attrs; pte_secure =3D s2.f.attrs.secure; @@ -304,6 +501,9 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl= ate *ptw, =20 fail: assert(fi->type !=3D ARMFault_None); + if (fi->type =3D=3D ARMFault_GPCFOnOutput) { + fi->type =3D ARMFault_GPCFOnWalk; + } fi->s2addr =3D addr; fi->stage2 =3D true; fi->s1ptw =3D true; @@ -2731,7 +2931,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, = target_ulong address, ARMMMUFaultInfo *fi) { uint8_t memattr =3D 0x00; /* Device nGnRnE */ - uint8_t shareability =3D 0; /* non-sharable */ + uint8_t shareability =3D 0; /* non-shareable */ int r_el; =20 switch (mmu_idx) { @@ -2790,7 +2990,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, = target_ulong address, } else { memattr =3D 0x44; /* Normal, NC, No */ } - shareability =3D 2; /* outer sharable */ + shareability =3D 2; /* outer shareable */ } result->cacheattrs.is_s2_format =3D false; break; @@ -2818,7 +3018,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, ARMSecuritySpace ipa_space, s2walk_space; uint64_t hcr; =20 - ret =3D get_phys_addr_with_struct(env, ptw, address, access_type, resu= lt, fi); + ret =3D get_phys_addr_nogpc(env, ptw, address, access_type, result, fi= ); =20 /* If S1 fails, return early. */ if (ret) { @@ -2855,7 +3055,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, cacheattrs1 =3D result->cacheattrs; memset(result, 0, sizeof(*result)); =20 - ret =3D get_phys_addr_with_struct(env, ptw, ipa, access_type, result, = fi); + ret =3D get_phys_addr_nogpc(env, ptw, ipa, access_type, result, fi); fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ @@ -2915,7 +3115,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, return false; } =20 -static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, +static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, target_ulong address, MMUAccessType access_type, GetPhysAddrResult *result, @@ -3039,6 +3239,23 @@ static bool get_phys_addr_with_struct(CPUARMState *e= nv, S1Translate *ptw, } } =20 +static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, + target_ulong address, + MMUAccessType access_type, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) +{ + if (get_phys_addr_nogpc(env, ptw, address, access_type, result, fi)) { + return true; + } + if (!granule_protection_check(env, result->f.phys_addr, + result->f.attrs.space, fi)) { + fi->type =3D ARMFault_GPCFOnOutput; + return true; + } + return false; +} + bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, bool is_secure, GetPhysAddrResult *result, @@ -3049,8 +3266,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, .in_secure =3D is_secure, .in_space =3D arm_secure_to_space(is_secure), }; - return get_phys_addr_with_struct(env, &ptw, address, access_type, - result, fi); + return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); } =20 bool get_phys_addr(CPUARMState *env, target_ulong address, @@ -3120,8 +3336,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, =20 ptw.in_space =3D ss; ptw.in_secure =3D arm_space_is_secure(ss); - return get_phys_addr_with_struct(env, &ptw, address, access_type, - result, fi); + return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); } =20 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, @@ -3141,7 +3356,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs= , vaddr addr, ARMMMUFaultInfo fi =3D {}; bool ret; =20 - ret =3D get_phys_addr_with_struct(env, &ptw, addr, MMU_DATA_LOAD, &res= , &fi); + ret =3D get_phys_addr_gpc(env, &ptw, addr, MMU_DATA_LOAD, &res, &fi); *attrs =3D res.f.attrs; =20 if (ret) { --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677033502; cv=none; d=zohomail.com; s=zohoarc; b=S+ySkkt9kk4Ph76TDUYwGcwp7qFnPS3X4nNG2x7R0gG1oj8IupiId5n8jFRt4z7fTLf2qLOuKnsYkkq21LaQKNXg4ZzePo8XD7HaJEhDnBGicWSqE2RHgug2WrXcQ1fTU3Zdu3UmMlLcadacVS/Z+nyGujJUrn7/64fpu1IFUjs= ARC-Message-Signature: i=1; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.34.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/Ut/aS2oezKic9UZ9DAK+e9x8VNxmPUkA0viJdZ3AGc=; b=D/KwGTISZqqO7gR78XhTb4eOCbAoyguUE3dZK/gmYFTyFmSaupf90u95syivnLb8Qa i7+I1UIujJRs0ruYu5ovbgPTXGU4WPDBp7hRxO8AbRhXoWJliZmpt75ZgXtc1z6vm93J ouhqxE7VVpbzc9Xdbjpc8Aj/KNgWx8hKUWW8sn0J+vzbGpe2pUDR6eWGOC8N5/wYfTjr 6v5VLNvSpHhfPhXvo02DsWLUwkrt+AU1Q+/+Y9ChSI/JbWu/sSJzM3U7hpjOqBAcGWLl DcrrH3+UB3EQTCKmOM3CfvshNWGraEQv/7+7F89z3kzjhn8zqZHHE1LtCmhwslGmhZHF LceA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/Ut/aS2oezKic9UZ9DAK+e9x8VNxmPUkA0viJdZ3AGc=; b=NyhDfbPx3UoploZLgGoC4JOrUbWgWK96VFErsxU714ki1LOVgZ7YtMPObMLDpOFuok UZ25h15fAV5j2xCCiFjQ0wsfT1C2OmGw4Stw7JdqbzMaXtVgh2qsOPcxfsZfVtjOGYUL JotGRWL2X7EFHVuOyaJz2iquLqipForvmkrWqS0AvoQnC7ZHopm5AzSwsEtO7ppw9jek UX9q8G18OXMNaj+Exmkwi4+164xtKJ0UTWbnNC0z+2pSOg7iAymWH/xaRE1khJXm3hX3 pvnMG6tWoZer4io0160S6+TnLngdYLVfh7BLpQQJRkeX546wsM5uOhqZ63C1blxpH7aL +fIw== X-Gm-Message-State: AO0yUKVww8wx31M48Cj12KhuxPaT2oTjam0ZC85UzZXBYBfqlOHO1WXq a1IQFDq2+QMkMYLJj2VufO4WJGqdUsHtHRNoFuNplw== X-Google-Smtp-Source: AK7set/LySYPepSWuVWPiPC+SEXU2BgDfjX+naD3k+zGNP47vu7m2dwqOevAbTJAIIaas74H1RUiCQ== X-Received: by 2002:a17:902:e545:b0:198:ec2c:d4e6 with SMTP id n5-20020a170902e54500b00198ec2cd4e6mr9378851plf.38.1677033252978; Tue, 21 Feb 2023 18:34:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH NOTFORMERGE v3 24/25] target/arm: Enable RME for -cpu max Date: Tue, 21 Feb 2023 16:33:35 -1000 Message-Id: <20230222023336.915045-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1041.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033504401100003 Content-Type: text/plain; charset="utf-8" Add a cpu property to set GPCCR_EL3.L0GPTSZ, for testing various possible configurations. Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4066950da1..70c173ee3d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -672,6 +672,40 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) cpu->isar.id_aa64mmfr0 =3D t; } =20 +static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + uint32_t value; + + if (!visit_type_uint32(v, name, &value, errp)) { + return; + } + + /* Encode the value for the GPCCR_EL3 field. */ + switch (value) { + case 30: + case 34: + case 36: + case 39: + cpu->reset_l0gptsz =3D value - 30; + break; + default: + error_setg(errp, "invalid value for l0gptsz"); + error_append_hint(errp, "valid values are 30, 34, 36, 39\n"); + break; + } +} + +static void cpu_max_get_l0gptsz(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + uint32_t value =3D cpu->reset_l0gptsz + 30; + + visit_type_uint32(v, name, &value, errp); +} + static void aarch64_a57_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -1200,6 +1234,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ + t =3D FIELD_DP64(t, ID_AA64PFR0, RME, 1); /* FEAT_RME */ t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ cpu->isar.id_aa64pfr0 =3D t; @@ -1301,6 +1336,8 @@ static void aarch64_max_initfn(Object *obj) object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_v= q, cpu_max_set_sve_max_vq, NULL, NULL); qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); + object_property_add(obj, "l0gptsz", "uint32", cpu_max_get_l0gptsz, + cpu_max_set_l0gptsz, NULL, NULL); } =20 static const ARMCPUInfo aarch64_cpus[] =3D { --=20 2.34.1 From nobody Sun May 19 03:54:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677033457; cv=none; d=zohomail.com; s=zohoarc; b=d+d/Rv8hANRBNHtUDekvrihW5OgF6DM2fqpFRUlAKD8rYBJQYaaWchAd4vawyF4ps+ySOW42SdhA4oRiKaSRIyjvCUU1fuOn1+Gs1/VHOZfuXpoxZnhHB6QlLxquab3rmj6lEK/E6YRdbdBD88I0UmsXUHBHPdXcVS3m4mumC9M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677033457; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=H9Qr7wA8wSIkfPgh/j+3hKBpjrPyoBLV3ksLdpb2kIs=; b=DhXMJAnndQGW3FzEPu7VCjodfSPmC80IkQ/B6C3uQ5gpzqlxrjXTbA8i8tYnI2CI7Bju1yczsNIApqQW8dEtKzIfcezJkF2EDI/GctC72yYBOCEKHlTmwC/bwJj3EJ97DXaYAVTMB5EJddY1I45KptokU/gU8ZOBdUK/aeAgOv0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677033456780116.99897018820741; Tue, 21 Feb 2023 18:37:36 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pUexW-0007ir-GH; Tue, 21 Feb 2023 21:34:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pUexU-0007iA-PN for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:34:16 -0500 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pUexT-0001XQ-0R for qemu-devel@nongnu.org; Tue, 21 Feb 2023 21:34:16 -0500 Received: by mail-pl1-x62f.google.com with SMTP id bh1so7212330plb.11 for ; Tue, 21 Feb 2023 18:34:14 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id k3-20020a170902e90300b00198fde9178csm10520112pld.197.2023.02.21.18.34.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:34:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H9Qr7wA8wSIkfPgh/j+3hKBpjrPyoBLV3ksLdpb2kIs=; b=dC2VB4qKDFvarrMYl1iKtvs/JH0i3HaDsZ7jv6B3wp7QjJUb3JvAUi/ko5r0ZAUg7Y BKRI/N7d5EWZdhmUJ/wtX9+x2AJOQqn1NBV/UnBAlk9rrPCRmDKkwQH7d6k2n94hIPjd L4rLMdzfJQSoXPJO0EOg3Qp9xm7AqbWMvGRYeb9ax3sen4Xe6DBuU9NmL4U8MuWnYlKA f8ahPFfnxT1lOCs2H05xPNJunPgmyEpB2gMKhq8/MbfmaZH2StQ41gaSZbw7/j8pzfam ngclVeUHglR4e1CACm6m8OeoLWzeFC1sRLSYl5bwzlQ/gsGH+qgID4KPKEdpvV0fuWSS ErIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H9Qr7wA8wSIkfPgh/j+3hKBpjrPyoBLV3ksLdpb2kIs=; b=ZhCC7nTI5ja5x5GjAt8wiER5OUHzUVDbujcooQFf4VglRYLpDtqeCsemVcAG4aE4M4 x/8osIdeFlqOJbu0ZaQtDraJJI+0VJ2JGigfJDgkGYklQL1qQK2/xFuTwEvxFNZa4QS1 O9q4mwEoNuC898c2Hm4ANWjtfaOJZXQkPO5sjeVJVMwwFDdqtitTecSYRz1q/w/mKnV7 60PRSw1lBASWn/haPDLnsrYQ2pGDfIQMzr7Vo46tczQyY+5SgkXaEuGY+zx1Vldxp5t7 lrQrupnLRx1Q8ipGn2IfTITHdCF+dSCx94uMeeY8K/kF2pWVI48Iv5tZLa19mgpM96eM hL/g== X-Gm-Message-State: AO0yUKUgT54Y7WgfOvc07HcaS7HFSynCnLWaogU0e6n5TB9c1MH1ZdQv PvHqdaqvYXcqbk0WV2hfGETFzJL9hZrEzZ+q8M0= X-Google-Smtp-Source: AK7set9QK1bKIAz9Jfhh5NZrNyXnPCbJffUoeHkZsttLWf0LNwl9SSNf+JLfP7gee84d06dWU9zPKg== X-Received: by 2002:a17:902:e5c9:b0:19c:355c:6eb5 with SMTP id u9-20020a170902e5c900b0019c355c6eb5mr9614923plf.30.1677033254215; Tue, 21 Feb 2023 18:34:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH NOTFORMERGE v3 25/25] hw/arm/virt: Add some memory for Realm Management Monitor Date: Tue, 21 Feb 2023 16:33:36 -1000 Message-Id: <20230222023336.915045-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222023336.915045-1-richard.henderson@linaro.org> References: <20230222023336.915045-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677033458177100001 Content-Type: text/plain; charset="utf-8" This is arbitrary, but used by the Huawei TF-A test code. Signed-off-by: Richard Henderson --- include/hw/arm/virt.h | 2 ++ hw/arm/virt.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index e1ddbea96b..5c0c8a67e4 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -86,6 +86,7 @@ enum { VIRT_ACPI_GED, VIRT_NVDIMM_ACPI, VIRT_PVTIME, + VIRT_RMM_MEM, VIRT_LOWMEMMAP_LAST, }; =20 @@ -159,6 +160,7 @@ struct VirtMachineState { bool virt; bool ras; bool mte; + bool rmm; bool dtb_randomness; OnOffAuto acpi; VirtGICType gic_version; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ac626b3bef..067f16cd77 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -159,6 +159,7 @@ static const MemMapEntry base_memmap[] =3D { /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that siz= e */ [VIRT_PLATFORM_BUS] =3D { 0x0c000000, 0x02000000 }, [VIRT_SECURE_MEM] =3D { 0x0e000000, 0x01000000 }, + [VIRT_RMM_MEM] =3D { 0x0f000000, 0x00100000 }, [VIRT_PCIE_MMIO] =3D { 0x10000000, 0x2eff0000 }, [VIRT_PCIE_PIO] =3D { 0x3eff0000, 0x00010000 }, [VIRT_PCIE_ECAM] =3D { 0x3f000000, 0x01000000 }, @@ -1602,6 +1603,25 @@ static void create_secure_ram(VirtMachineState *vms, g_free(nodename); } =20 +static void create_rmm_ram(VirtMachineState *vms, + MemoryRegion *sysmem, + MemoryRegion *tag_sysmem) +{ + MemoryRegion *rmm_ram =3D g_new(MemoryRegion, 1); + hwaddr base =3D vms->memmap[VIRT_RMM_MEM].base; + hwaddr size =3D vms->memmap[VIRT_RMM_MEM].size; + + memory_region_init_ram(rmm_ram, NULL, "virt.rmm-ram", size, + &error_fatal); + memory_region_add_subregion(sysmem, base, rmm_ram); + + /* do not fill in fdt to hide rmm from normal world guest */ + + if (tag_sysmem) { + create_tag_ram(tag_sysmem, base, size, "mach-virt.rmm-tag"); + } +} + static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) { const VirtMachineState *board =3D container_of(binfo, VirtMachineState, @@ -2283,6 +2303,10 @@ static void machvirt_init(MachineState *machine) machine->ram_size, "mach-virt.tag"); } =20 + if (vms->rmm) { + create_rmm_ram(vms, sysmem, tag_sysmem); + } + vms->highmem_ecam &=3D (!firmware_loaded || aarch64); =20 create_rtc(vms); @@ -2562,6 +2586,20 @@ static void virt_set_mte(Object *obj, bool value, Er= ror **errp) vms->mte =3D value; } =20 +static bool virt_get_rmm(Object *obj, Error **errp) +{ + VirtMachineState *vms =3D VIRT_MACHINE(obj); + + return vms->rmm; +} + +static void virt_set_rmm(Object *obj, bool value, Error **errp) +{ + VirtMachineState *vms =3D VIRT_MACHINE(obj); + + vms->rmm =3D value; +} + static char *virt_get_gic_version(Object *obj, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); @@ -3115,6 +3153,11 @@ static void virt_machine_class_init(ObjectClass *oc,= void *data) "guest CPU which implements the = ARM " "Memory Tagging Extension"); =20 + object_class_property_add_bool(oc, "rmm", virt_get_rmm, virt_set_rmm); + object_class_property_set_description(oc, "rmm", + "Set on/off to enable/disable ra= m " + "for the Realm Management Monito= r"); + object_class_property_add_bool(oc, "its", virt_get_its, virt_set_its); object_class_property_set_description(oc, "its", --=20 2.34.1