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Tsirkin" , Marcel Apfelbaum , Bui Quang Minh Subject: [PATCH 1/4] apic: add support for x2APIC mode Date: Tue, 21 Feb 2023 23:04:57 +0700 Message-Id: <20230221160500.30336-2-minhquangbui99@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230221160500.30336-1-minhquangbui99@gmail.com> References: <20230221160500.30336-1-minhquangbui99@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=minhquangbui99@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 21 Feb 2023 11:46:13 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1676998007152100003 Content-Type: text/plain; charset="utf-8" This commit refactors APIC registers read/write function to support both MMIO read/write in xAPIC mode and MSR read/write in x2APIC mode. Also, support larger APIC ID, self IPI, new IPI destination determination in x2APIC mode. Signed-off-by: Bui Quang Minh --- hw/intc/apic.c | 211 +++++++++++++++++++++++++------- hw/intc/apic_common.c | 2 +- include/hw/i386/apic.h | 5 +- include/hw/i386/apic_internal.h | 2 +- 4 files changed, 172 insertions(+), 48 deletions(-) diff --git a/hw/intc/apic.c b/hw/intc/apic.c index 2d3e55f4e2..205d5923ec 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -30,6 +30,7 @@ #include "hw/i386/apic-msidef.h" #include "qapi/error.h" #include "qom/object.h" +#include "tcg/helper-tcg.h" =20 #define MAX_APICS 255 #define MAX_APIC_WORDS 8 @@ -48,7 +49,7 @@ DECLARE_INSTANCE_CHECKER(APICCommonState, APIC, static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_m= ode); static void apic_update_irq(APICCommonState *s); static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, - uint8_t dest, uint8_t dest_mode); + uint32_t dest, uint8_t dest_mode); =20 /* Find first bit starting from msb */ static int apic_fls_bit(uint32_t value) @@ -275,7 +276,7 @@ static void apic_bus_deliver(const uint32_t *deliver_bi= tmask, apic_set_irq(apic_iter, vector_num, trigger_mode) ); } =20 -void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mo= de, +void apic_deliver_irq(uint32_t dest, uint8_t dest_mode, uint8_t delivery_m= ode, uint8_t vector_num, uint8_t trigger_mode) { uint32_t deliver_bitmask[MAX_APIC_WORDS]; @@ -287,8 +288,38 @@ void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,= uint8_t delivery_mode, apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_m= ode); } =20 +bool is_x2apic_mode(DeviceState *dev) +{ + APICCommonState *s =3D APIC(dev); + + return s->apicbase & MSR_IA32_APICBASE_EXTD; +} + static void apic_set_base(APICCommonState *s, uint64_t val) { + /* + * Transition into invalid state + * (s->apicbase & MSR_IA32_APICBASE_ENABLE =3D=3D 0) && + * (s->apicbase & MSR_IA32_APICBASE_EXTD) =3D=3D 1 + */ + if (!(val & MSR_IA32_APICBASE_ENABLE) && + (val & MSR_IA32_APICBASE_EXTD)) + raise_exception_ra(&s->cpu->env, EXCP0D_GPF, GETPC()); + + /* Invalid transition from disabled mode to x2APIC */ + if (!(s->apicbase & MSR_IA32_APICBASE_ENABLE) && + !(s->apicbase & MSR_IA32_APICBASE_EXTD) && + (val & MSR_IA32_APICBASE_ENABLE) && + (val & MSR_IA32_APICBASE_EXTD)) + raise_exception_ra(&s->cpu->env, EXCP0D_GPF, GETPC()); + + /* Invalid transition from x2APIC to xAPIC */ + if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) && + (s->apicbase & MSR_IA32_APICBASE_EXTD) && + (val & MSR_IA32_APICBASE_ENABLE) && + !(val & MSR_IA32_APICBASE_EXTD)) + raise_exception_ra(&s->cpu->env, EXCP0D_GPF, GETPC()); + s->apicbase =3D (val & 0xfffff000) | (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); /* if disabled, cannot be enabled again */ @@ -297,6 +328,21 @@ static void apic_set_base(APICCommonState *s, uint64_t= val) cpu_clear_apic_feature(&s->cpu->env); s->spurious_vec &=3D ~APIC_SV_ENABLE; } + + /* Transition from xAPIC to x2APIC */ + if (cpu_has_x2apic_feature(&s->cpu->env) && + !(s->apicbase & MSR_IA32_APICBASE_EXTD) && + (val & MSR_IA32_APICBASE_EXTD)) { + s->apicbase |=3D MSR_IA32_APICBASE_EXTD; + + s->log_dest =3D ((s->initial_apic_id & 0xffff0) << 16) | + (1 << (s->initial_apic_id & 0xf)); + + /* disable MMIO interface */ + qemu_mutex_lock_iothread(); + memory_region_set_enabled(&s->io_memory, false); + qemu_mutex_unlock_iothread(); + } } =20 static void apic_set_tpr(APICCommonState *s, uint8_t val) @@ -454,7 +500,7 @@ static int apic_find_dest(uint8_t dest) } =20 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, - uint8_t dest, uint8_t dest_mode) + uint32_t dest, uint8_t dest_mode) { APICCommonState *apic_iter; int i; @@ -474,14 +520,22 @@ static void apic_get_delivery_bitmask(uint32_t *deliv= er_bitmask, for(i =3D 0; i < MAX_APICS; i++) { apic_iter =3D local_apics[i]; if (apic_iter) { - if (apic_iter->dest_mode =3D=3D 0xf) { - if (dest & apic_iter->log_dest) - apic_set_bit(deliver_bitmask, i); - } else if (apic_iter->dest_mode =3D=3D 0x0) { - if ((dest & 0xf0) =3D=3D (apic_iter->log_dest & 0xf0) = && - (dest & apic_iter->log_dest & 0x0f)) { + /* x2APIC mode */ + if (apic_iter->apicbase & MSR_IA32_APICBASE_EXTD) { + if ((dest & 0xffff0000) =3D=3D (apic_iter->log_dest & = 0xffff0000) && + (dest & apic_iter->log_dest & 0xffff)) { apic_set_bit(deliver_bitmask, i); } + } else { + if (apic_iter->dest_mode =3D=3D 0xf) { + if (dest & apic_iter->log_dest) + apic_set_bit(deliver_bitmask, i); + } else if (apic_iter->dest_mode =3D=3D 0x0) { + if ((dest & 0xf0) =3D=3D (apic_iter->log_dest & 0x= f0) && + (dest & apic_iter->log_dest & 0x0f)) { + apic_set_bit(deliver_bitmask, i); + } + } } } else { break; @@ -508,13 +562,12 @@ void apic_sipi(DeviceState *dev) s->wait_for_sipi =3D 0; } =20 -static void apic_deliver(DeviceState *dev, uint8_t dest, uint8_t dest_mode, +static void apic_deliver(DeviceState *dev, uint32_t dest, uint8_t dest_mod= e, uint8_t delivery_mode, uint8_t vector_num, - uint8_t trigger_mode) + uint8_t trigger_mode, uint8_t dest_shorthand) { APICCommonState *s =3D APIC(dev); uint32_t deliver_bitmask[MAX_APIC_WORDS]; - int dest_shorthand =3D (s->icr[0] >> 18) & 3; APICCommonState *apic_iter; =20 switch (dest_shorthand) { @@ -635,16 +688,11 @@ static void apic_timer(void *opaque) apic_timer_update(s, s->next_time); } =20 -static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size) +uint64_t apic_register_read(int index) { DeviceState *dev; APICCommonState *s; - uint32_t val; - int index; - - if (size < 4) { - return 0; - } + uint64_t val; =20 dev =3D cpu_get_current_apic(); if (!dev) { @@ -652,10 +700,12 @@ static uint64_t apic_mem_read(void *opaque, hwaddr ad= dr, unsigned size) } s =3D APIC(dev); =20 - index =3D (addr >> 4) & 0xff; switch(index) { case 0x02: /* id */ - val =3D s->id << 24; + if (is_x2apic_mode(dev)) + val =3D s->initial_apic_id; + else + val =3D s->id << 24; break; case 0x03: /* version */ val =3D s->version | ((APIC_LVT_NB - 1) << 16); @@ -678,9 +728,16 @@ static uint64_t apic_mem_read(void *opaque, hwaddr add= r, unsigned size) val =3D 0; break; case 0x0d: - val =3D s->log_dest << 24; + if (is_x2apic_mode(dev)) + val =3D s->log_dest; + else + val =3D s->log_dest << 24; break; case 0x0e: + if (is_x2apic_mode(dev)) { + raise_exception_ra(&s->cpu->env, EXCP0D_GPF, GETPC()); + } + val =3D (s->dest_mode << 28) | 0xfffffff; break; case 0x0f: @@ -719,6 +776,22 @@ static uint64_t apic_mem_read(void *opaque, hwaddr add= r, unsigned size) val =3D 0; break; } + + return val; +} + +static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size) +{ + uint32_t val; + int index; + + if (size < 4) { + return 0; + } + + index =3D (addr >> 4) & 0xff; + val =3D (uint32_t) apic_register_read(index); + trace_apic_mem_readl(addr, val); return val; } @@ -736,27 +809,10 @@ static void apic_send_msi(MSIMessage *msi) apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); } =20 -static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val, - unsigned size) +void apic_register_write(int index, uint64_t val) { DeviceState *dev; APICCommonState *s; - int index =3D (addr >> 4) & 0xff; - - if (size < 4) { - return; - } - - if (addr > 0xfff || !index) { - /* MSI and MMIO APIC are at the same memory location, - * but actually not on the global bus: MSI is on PCI bus - * APIC is connected directly to the CPU. - * Mapping them on the global bus happens to work because - * MSI registers are reserved in APIC MMIO and vice versa. */ - MSIMessage msi =3D { .address =3D addr, .data =3D val }; - apic_send_msi(&msi); - return; - } =20 dev =3D cpu_get_current_apic(); if (!dev) { @@ -764,10 +820,12 @@ static void apic_mem_write(void *opaque, hwaddr addr,= uint64_t val, } s =3D APIC(dev); =20 - trace_apic_mem_writel(addr, val); - switch(index) { case 0x02: + if (is_x2apic_mode(dev)) { + raise_exception_ra(&s->cpu->env, EXCP0D_GPF, GETPC()); + } + s->id =3D (val >> 24); break; case 0x03: @@ -787,9 +845,17 @@ static void apic_mem_write(void *opaque, hwaddr addr, = uint64_t val, apic_eoi(s); break; case 0x0d: + if (is_x2apic_mode(dev)) { + raise_exception_ra(&s->cpu->env, EXCP0D_GPF, GETPC()); + } + s->log_dest =3D val >> 24; break; case 0x0e: + if (is_x2apic_mode(dev)) { + raise_exception_ra(&s->cpu->env, EXCP0D_GPF, GETPC()); + } + s->dest_mode =3D val >> 28; break; case 0x0f: @@ -801,13 +867,27 @@ static void apic_mem_write(void *opaque, hwaddr addr,= uint64_t val, case 0x20 ... 0x27: case 0x28: break; - case 0x30: + case 0x30: { + uint32_t dest; + s->icr[0] =3D val; - apic_deliver(dev, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, + if (is_x2apic_mode(dev)) { + s->icr[1] =3D val >> 32; + dest =3D s->icr[1]; + } else { + dest =3D (s->icr[1] >> 24) & 0xff; + } + + apic_deliver(dev, dest, (s->icr[0] >> 11) & 1, (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), - (s->icr[0] >> 15) & 1); + (s->icr[0] >> 15) & 1, (s->icr[0] >> 18) & 3); break; + } case 0x31: + if (is_x2apic_mode(dev)) { + raise_exception_ra(&s->cpu->env, EXCP0D_GPF, GETPC()); + } + s->icr[1] =3D val; break; case 0x32 ... 0x37: @@ -836,12 +916,53 @@ static void apic_mem_write(void *opaque, hwaddr addr,= uint64_t val, s->count_shift =3D (v + 1) & 7; } break; + case 0x3f: { + int vector =3D val & 0xff; + + if (is_x2apic_mode(dev)) { + raise_exception_ra(&s->cpu->env, EXCP0D_GPF, GETPC()); + } + + /* + * Self IPI is identical to IPI with + * - Destination shorthand: 1 (Self) + * - Trigger mode: 0 (Edge) + * - Delivery mode: 0 (Fixed) + */ + apic_deliver(dev, 0, 0, APIC_DM_FIXED, vector, 0, 1); + + break; + } default: s->esr |=3D APIC_ESR_ILLEGAL_ADDRESS; break; } } =20 +static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + int index =3D (addr >> 4) & 0xff; + + if (size < 4) { + return; + } + + if (addr > 0xfff || !index) { + /* MSI and MMIO APIC are at the same memory location, + * but actually not on the global bus: MSI is on PCI bus + * APIC is connected directly to the CPU. + * Mapping them on the global bus happens to work because + * MSI registers are reserved in APIC MMIO and vice versa. */ + MSIMessage msi =3D { .address =3D addr, .data =3D val }; + apic_send_msi(&msi); + return; + } + + trace_apic_mem_writel(addr, val); + apic_register_write(index, val); +} + static void apic_pre_save(APICCommonState *s) { apic_sync_vapic(s, SYNC_FROM_VAPIC); diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 4a34f03047..9ea1397530 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -366,7 +366,7 @@ static const VMStateDescription vmstate_apic_common =3D= { VMSTATE_UINT8(arb_id, APICCommonState), VMSTATE_UINT8(tpr, APICCommonState), VMSTATE_UINT32(spurious_vec, APICCommonState), - VMSTATE_UINT8(log_dest, APICCommonState), + VMSTATE_UINT32(log_dest, APICCommonState), VMSTATE_UINT8(dest_mode, APICCommonState), VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8), VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8), diff --git a/include/hw/i386/apic.h b/include/hw/i386/apic.h index bdc15a7a73..871ca94c5c 100644 --- a/include/hw/i386/apic.h +++ b/include/hw/i386/apic.h @@ -3,7 +3,7 @@ =20 =20 /* apic.c */ -void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mo= de, +void apic_deliver_irq(uint32_t dest, uint8_t dest_mode, uint8_t delivery_m= ode, uint8_t vector_num, uint8_t trigger_mode); int apic_accept_pic_intr(DeviceState *s); void apic_deliver_pic_intr(DeviceState *s, int level); @@ -18,6 +18,9 @@ void apic_sipi(DeviceState *s); void apic_poll_irq(DeviceState *d); void apic_designate_bsp(DeviceState *d, bool bsp); int apic_get_highest_priority_irr(DeviceState *dev); +uint64_t apic_register_read(int index); +void apic_register_write(int index, uint64_t val); +bool is_x2apic_mode(DeviceState *d); =20 /* pc.c */ DeviceState *cpu_get_current_apic(void); diff --git a/include/hw/i386/apic_internal.h b/include/hw/i386/apic_interna= l.h index 5f2ba24bfc..5f60cd5e78 100644 --- a/include/hw/i386/apic_internal.h +++ b/include/hw/i386/apic_internal.h @@ -164,7 +164,7 @@ struct APICCommonState { uint8_t arb_id; uint8_t tpr; uint32_t spurious_vec; - uint8_t log_dest; + uint32_t log_dest; uint8_t dest_mode; uint32_t isr[8]; /* in service register */ uint32_t tmr[8]; /* trigger mode register */ --=20 2.25.1 From nobody Tue May 14 23:07:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Marcel Apfelbaum , Bui Quang Minh Subject: [PATCH 2/4] i386/tcg: implement x2APIC registers MSR access Date: Tue, 21 Feb 2023 23:04:58 +0700 Message-Id: <20230221160500.30336-3-minhquangbui99@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230221160500.30336-1-minhquangbui99@gmail.com> References: <20230221160500.30336-1-minhquangbui99@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=minhquangbui99@gmail.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 21 Feb 2023 11:46:13 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1676998037004100004 Content-Type: text/plain; charset="utf-8" i386 TCG now supports MSR access to x2APIC registers. The MRS address ranges from 0x800 to 0x8ff. Signed-off-by: Bui Quang Minh --- target/i386/cpu-sysemu.c | 5 +++++ target/i386/cpu.c | 5 +++-- target/i386/cpu.h | 4 ++++ target/i386/tcg/sysemu/misc_helper.c | 27 +++++++++++++++++++++++++++ 4 files changed, 39 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu-sysemu.c b/target/i386/cpu-sysemu.c index 28115edf44..73f14161e9 100644 --- a/target/i386/cpu-sysemu.c +++ b/target/i386/cpu-sysemu.c @@ -235,6 +235,11 @@ void cpu_clear_apic_feature(CPUX86State *env) env->features[FEAT_1_EDX] &=3D ~CPUID_APIC; } =20 +bool cpu_has_x2apic_feature(CPUX86State *env) +{ + return env->features[FEAT_1_ECX] & CPUID_EXT_X2APIC; +} + bool cpu_is_bsp(X86CPU *cpu) { return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 4d2b8d0444..ce9ec460f4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -626,12 +626,13 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t ven= dor1, CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ - CPUID_EXT_FMA) + CPUID_EXT_FMA | CPUID_EXT_X2APIC) /* missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, - CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER */ + CPUID_EXT_TSC_DEADLINE_TIMER + */ =20 #ifdef TARGET_X86_64 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d4bc19577a..e163d9a136 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -542,6 +542,9 @@ typedef enum X86Seg { #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 #define MSR_IA32_VMX_VMFUNC 0x00000491 =20 +#define MSR_APIC_START 0x00000800 +#define MSR_APIC_END 0x000008ff + #define XSTATE_FP_BIT 0 #define XSTATE_SSE_BIT 1 #define XSTATE_YMM_BIT 2 @@ -2128,6 +2131,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, void cpu_clear_apic_feature(CPUX86State *env); void host_cpuid(uint32_t function, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx= ); +bool cpu_has_x2apic_feature(CPUX86State *env); =20 /* helper.c */ void x86_cpu_set_a20(X86CPU *cpu, int a20_state); diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/= misc_helper.c index e1528b7f80..1fce2076a3 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -25,6 +25,7 @@ #include "exec/address-spaces.h" #include "exec/exec-all.h" #include "tcg/helper-tcg.h" +#include "hw/i386/apic.h" =20 void helper_outb(CPUX86State *env, uint32_t port, uint32_t data) { @@ -289,6 +290,19 @@ void helper_wrmsr(CPUX86State *env) env->msr_bndcfgs =3D val; cpu_sync_bndcs_hflags(env); break; + case MSR_APIC_START ... MSR_APIC_END: { + int index =3D (uint32_t)env->regs[R_ECX] - MSR_APIC_START; + + if (!is_x2apic_mode(env_archcpu(env)->apic_state)) { + goto error; + } + + qemu_mutex_lock_iothread(); + apic_register_write(index, val); + qemu_mutex_unlock_iothread(); + + break; + } default: if ((uint32_t)env->regs[R_ECX] >=3D MSR_MC0_CTL && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + @@ -455,6 +469,19 @@ void helper_rdmsr(CPUX86State *env) val =3D (cs->nr_threads * cs->nr_cores) | (cs->nr_cores << 16); break; } + case MSR_APIC_START ... MSR_APIC_END: { + int index =3D (uint32_t)env->regs[R_ECX] - MSR_APIC_START; + + if (!is_x2apic_mode(env_archcpu(env)->apic_state)) { + raise_exception_ra(env, EXCP0D_GPF, GETPC()); + } + + qemu_mutex_lock_iothread(); + val =3D apic_register_read(index); + qemu_mutex_unlock_iothread(); + + break; + } default: if ((uint32_t)env->regs[R_ECX] >=3D MSR_MC0_CTL && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + --=20 2.25.1 From nobody Tue May 14 23:07:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1676998037; cv=none; d=zohomail.com; s=zohoarc; b=Lry459ctxEF1C+tUVxS2S9FoBwhmVET9Pp8b39wxPslCnGtvMueAxkoF4ZBf/Op3OUaIoegeJwxghp/dSQR0MZkYjLRxZu4tiB+RLzTFkCkSJa+RFy3RgOtktc+sS2/lVQHcQy7VP9zUF2pFTaju7po6B22Mvt12vLCYKqwn5F0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676998037; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wWTW2+Ca/8ToXaJenUu+hnPBUwSEF/3VL/OdDDLKkQY=; b=AtdLZb3dHbenEroWKivY7F+tjPOU8jst/wzYn8Th4BCyrIOfRkGJVZsU16W/yYc58lEBV+AaOUbX5ugRcqvDmyDnPKsRu7JDhED28oioCyJpqMLob4EDPQsxv4j5c7bKhLyjQ8SZInmpNdrGtOK8MttNPsbUXjnwyrTiphR9dCo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1676998037322706.6633570488501; Tue, 21 Feb 2023 08:47:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pUVma-00009b-B7; Tue, 21 Feb 2023 11:46:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pUV9A-0001pQ-09 for qemu-devel@nongnu.org; Tue, 21 Feb 2023 11:05:40 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pUV98-0007us-9v for qemu-devel@nongnu.org; Tue, 21 Feb 2023 11:05:39 -0500 Received: by mail-pl1-x62c.google.com with SMTP id u14so1620671ple.7 for ; Tue, 21 Feb 2023 08:05:37 -0800 (PST) Received: from localhost.localdomain ([113.173.97.170]) by smtp.googlemail.com with ESMTPSA id b15-20020a170902650f00b001943d58268csm10076295plk.55.2023.02.21.08.05.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 08:05:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wWTW2+Ca/8ToXaJenUu+hnPBUwSEF/3VL/OdDDLKkQY=; b=AzgcEAGesvcr286TzK6pR7aaG70kJVFaGt8yGdM83r9y+bPBcTkdp9jiGFCYaQkCkr 6LmMm/hgToCUfhGHRoKsATWp1TMal/0HoWV1IgmZjyzgZy37j3Ze5L00HAfOuf5gX0gA aT8ihlJAk8+Fn/tgQaN19qkt3Mm0d0j9DD/AuH6wz4Xat8g36svvyngFj+0aKznmOdzT Xo6g0+Ot1cNVI+En6iNdB7FHQ6k4y54kLktU4IV0yqiu9UeLPER3w52h4vYIfOARC0kX /y6KZp7mfq8xQ9Di9iHrzAdQm6hG+hfM+vhThfToaJXK1zh5S4ddalxD7ITQtPeODluJ T1nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wWTW2+Ca/8ToXaJenUu+hnPBUwSEF/3VL/OdDDLKkQY=; b=vPSLi9jJtUvsb+G86mrAS+fDGjGsL4KMzsIAwNckkncw760ayHyxPGxXOxaZzrsF22 95i/DJNKsfGJOvCoDIki9h//2vkiT9FMMqmwLbCIMI1YaUJfx8rtQ7njrgXyXl96Vf7T 33wZHTb3JlnVAmYwUp4Gex4K20H7efZXsSgYgj1wjvTQJinmtL/QVSiF5vFrOBVAs4Wu BXYwCxo46hD9MTxQm4lfTvLH3T/LyFCUy+TIP5IMmQhetK3dH1DYotOeLf7cb6WWnYyb goVAOiogrxCZixk+8q0oWxlfmkYnqAe+8RXxHPEj7b88kDCKWdunfahJ4V3YBnpZTlLi qrwQ== X-Gm-Message-State: AO0yUKUzLw9P9zfkK9Wz2z3Tv2f1dMap3Wg/f2Xbe8nLU/UzmE3ZCO6w 94ylQsCYT6AhgYGdmVhAYrmkPq+muDA/iw== X-Google-Smtp-Source: AK7set9yAwU9lBee3KmH2MmjGn2/wgxwTgtr3NftUJ4JrRHTJkda/oJs03yQgMcXRFVGmC0ihyo/nA== X-Received: by 2002:a17:902:e84b:b0:199:1160:956c with SMTP id t11-20020a170902e84b00b001991160956cmr5618795plg.31.1676995536159; Tue, 21 Feb 2023 08:05:36 -0800 (PST) From: Bui Quang Minh To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson , Eduardo Habkost , "Michael S . Tsirkin" , Marcel Apfelbaum , Bui Quang Minh Subject: [PATCH 3/4] intel_iommu: allow Extended Interrupt Mode when using userspace local APIC Date: Tue, 21 Feb 2023 23:04:59 +0700 Message-Id: <20230221160500.30336-4-minhquangbui99@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230221160500.30336-1-minhquangbui99@gmail.com> References: <20230221160500.30336-1-minhquangbui99@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=minhquangbui99@gmail.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 21 Feb 2023 11:46:13 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1676998039031100008 Content-Type: text/plain; charset="utf-8" As userspace local APIC now supports x2APIC, intel interrupt remapping hardware can be set to EIM mode when userspace local APIC is used. Signed-off-by: Bui Quang Minh --- hw/i386/intel_iommu.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 98a5c304a7..228a944bce 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4026,17 +4026,6 @@ static bool vtd_decide_config(IntelIOMMUState *s, Er= ror **errp) && x86_iommu_ir_supported(x86_iommu) ? ON_OFF_AUTO_ON : ON_OFF_AUTO= _OFF; } - if (s->intr_eim =3D=3D ON_OFF_AUTO_ON && !s->buggy_eim) { - if (!kvm_irqchip_is_split()) { - error_setg(errp, "eim=3Don requires accel=3Dkvm,kernel-irqchip= =3Dsplit"); - return false; - } - if (!kvm_enable_x2apic()) { - error_setg(errp, "eim=3Don requires support on the KVM side" - "(X2APIC_API, first shipped in v4.7)"); - return false; - } - } =20 /* Currently only address widths supported are 39 and 48 bits */ if ((s->aw_bits !=3D VTD_HOST_AW_39BIT) && --=20 2.25.1 From nobody Tue May 14 23:07:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1676998043; cv=none; d=zohomail.com; s=zohoarc; b=Hz7Kjkm3sM55JfpKDdA5Pf21at/HcTe2xA1gB47KZ6DGGxsd412d2hi83OYwjzTubkZyz2u5hyQDwghFHQksgUBe+9N3wDI/Rczb/u6zTPCnad57qNGhpAkjhEUMHrwF7gXiT4/EeJC+97e1GO0Qtazdj8Fjs1NmIWlSKOmAefs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676998043; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=loUKCpodH6rrX01BvhuMU1Hj1SqzrWBHPXyBozd3Y40=; b=MuqiGh6cic34VCOT1FwHQEsqIpnCOWfAaYaVHMhYT+ryDMO3cp1MCDfrNjvvDPGBUX508aI72VORUPx6jR+PIK9hc2XsecCPPDQzIAFnyQEjeBQp+6QOSpyQSFyvCxHxq3mPmZRauTzM8jBC+e1Y2+7kLPsBe29bIvXO9TjQ/II= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1676998043268141.24785779100114; Tue, 21 Feb 2023 08:47:23 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pUVmX-00005a-15; Tue, 21 Feb 2023 11:46:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pUV9E-0001t6-8Q for qemu-devel@nongnu.org; Tue, 21 Feb 2023 11:05:44 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pUV9C-0007vE-79 for qemu-devel@nongnu.org; Tue, 21 Feb 2023 11:05:43 -0500 Received: by mail-pj1-x1031.google.com with SMTP id h17-20020a17090aea9100b0023739b10792so45999pjz.1 for ; Tue, 21 Feb 2023 08:05:41 -0800 (PST) Received: from localhost.localdomain ([113.173.97.170]) by smtp.googlemail.com with ESMTPSA id b15-20020a170902650f00b001943d58268csm10076295plk.55.2023.02.21.08.05.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 08:05:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=loUKCpodH6rrX01BvhuMU1Hj1SqzrWBHPXyBozd3Y40=; b=M4QY1zsxHOkzkXuv2Dzdfu4kORbiL6sH3ToGmAshTWCPwREQ8WHuZL6s+kPsqDc7LY onOfgtMlUpINkDowxFQHBXZ6tA9cf6P04jD8s/hZAWDV/cIDa64tBHAt23CK2S3HhzQI L+RpfuA6zn7GnqYHr6V/8gKsfF4D22GFHdHU7SCAqtsb/W7gt4OWFW4ItZA3xhQydeqT aN8NX0xTBmaFcVIApFXmoKVqpdXRFTmhQ3PSd4GT67U4ZwEHlKJoasDb4qqlnqBbK/XB jJp/MvI6weZieOlEIw65tZCW1b2Mky4/1q3arg9EbHDdLsSeKFbc78PlorZt8BBW4M89 qUrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=loUKCpodH6rrX01BvhuMU1Hj1SqzrWBHPXyBozd3Y40=; b=TMO9yokW7q5+3La9vurC/nZxyiO7vA6aBKbkIyy3/ZJnOmF/Cjcc3wphrLiT9mTbRU LF04ts7od+zwU5iwj0R3Fzk3ol1n0CsDQmfp4BOM4YOo/UycjZMqAnPwEgu1+NJpf4iJ yjIfXBR2dtpnasaMm/MvQEXz/2wMRak9miq0mGoUQME+Bl1VUayxKTSM/nTB+Ud01pwo Qj2XldW+VmDNdTa76YuPxjVzv7Zl1S5HxUM7S6Bum8q/lWXVn1vuBQHP/hemNe73xRma 1Frvm01qy10bEM/DPzhqwj5hWru+D2N0/lR5iBZp5hIiDUo5j8F01lRl3fkmy9OnqSdc F88Q== X-Gm-Message-State: AO0yUKV0SuppnC6ycFlLYmkUf5NcObcx60Sl4T8mh24Iw/SDFW1iKpOO K8T+6TgBMEcbpjzlOjSkuc26r8mOrjiGIg== X-Google-Smtp-Source: AK7set8pVwho9BucX/V6+1IYCJuNV1JWspjNmLdi1vWoOBu5NWMrqIAnl24MInB0w7Aw9w+i784MhQ== X-Received: by 2002:a17:902:e888:b0:19a:95ab:6b2b with SMTP id w8-20020a170902e88800b0019a95ab6b2bmr8113439plg.69.1676995540452; Tue, 21 Feb 2023 08:05:40 -0800 (PST) From: Bui Quang Minh To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson , Eduardo Habkost , "Michael S . Tsirkin" , Marcel Apfelbaum , Bui Quang Minh Subject: [PATCH 4/4] test/avocado: test Linux boot up in x2APIC with userspace local APIC Date: Tue, 21 Feb 2023 23:05:00 +0700 Message-Id: <20230221160500.30336-5-minhquangbui99@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230221160500.30336-1-minhquangbui99@gmail.com> References: <20230221160500.30336-1-minhquangbui99@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=minhquangbui99@gmail.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 21 Feb 2023 11:46:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1676998045064100002 Content-Type: text/plain; charset="utf-8" Simple test to check Linux boot up in x2APIC with userspace local APIC and TCG accelerator. Signed-off-by: Bui Quang Minh --- tests/avocado/tcg_x2apic.py | 91 +++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 tests/avocado/tcg_x2apic.py diff --git a/tests/avocado/tcg_x2apic.py b/tests/avocado/tcg_x2apic.py new file mode 100644 index 0000000000..ff4f27017c --- /dev/null +++ b/tests/avocado/tcg_x2apic.py @@ -0,0 +1,91 @@ +# x2APIC with TCG accelerator tests +# Based on intel_iommu.py, INTEL_IOMMU Functional tests +# +# Copyright (c) Bui Quang Minh +# +# This work is licensed under the terms of the GNU GPL, version 2 or +# later. See the COPYING file in the top-level directory. +import os + +from avocado import skipIf +from avocado_qemu import LinuxTest + +@skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab') +class TCGx2APIC(LinuxTest): + """ + :avocado: tags=3Darch:x86_64 + :avocado: tags=3Ddistro:fedora + :avocado: tags=3Ddistro_version:31 + :avocado: tags=3Dmachine:q35 + :avocado: tags=3Daccel:tcg + :avocado: tags=3Dx2apic + """ + + IOMMU_ADDON =3D ',iommu_platform=3Don,disable-modern=3Doff,disable-leg= acy=3Don' + kernel_path =3D None + initrd_path =3D None + kernel_params =3D None + + def set_up_boot(self): + path =3D self.download_boot() + self.vm.add_args('-device', 'virtio-blk-pci,bus=3Dpcie.0,scsi=3Dof= f,' + + 'drive=3Ddrv0,id=3Dvirtio-disk0,bootindex=3D1,' + 'werror=3Dstop,rerror=3Dstop' + self.IOMMU_ADDON) + self.vm.add_args('-device', 'virtio-gpu-pci' + self.IOMMU_ADDON) + self.vm.add_args('-drive', + 'file=3D%s,if=3Dnone,cache=3Dwritethrough,id=3Ddr= v0' % path) + + def setUp(self): + super(TCGx2APIC, self).setUp(None, 'virtio-net-pci' + self.IOMMU_A= DDON) + + def add_common_args(self): + self.vm.add_args('-device', 'virtio-rng-pci,rng=3Drng0') + self.vm.add_args('-object', + 'rng-random,id=3Drng0,filename=3D/dev/urandom') + + def common_vm_setup(self, custom_kernel=3DNone): + self.require_accelerator('tcg') + self.add_common_args() + self.vm.add_args('-accel', 'tcg') + self.vm.add_args('-device', 'intel-iommu,intremap=3Don,eim=3Don') + self.vm.add_args('-cpu', 'qemu64,+x2apic') + + if custom_kernel is None: + return + + kernel_url =3D self.distro.pxeboot_url + 'vmlinuz' + initrd_url =3D self.distro.pxeboot_url + 'initrd.img' + self.kernel_path =3D self.fetch_asset(kernel_url) + self.initrd_path =3D self.fetch_asset(initrd_url) + + def run_and_check(self): + if self.kernel_path: + self.vm.add_args('-kernel', self.kernel_path, + '-append', self.kernel_params, + '-initrd', self.initrd_path) + self.launch_and_wait() + self.ssh_command('cat /proc/cmdline') + self.ssh_command('dmesg | grep "x2apic enabled"') + + def test_physical_x2apic(self): + """ + :avocado: tags=3Dphysical_x2apic + """ + + self.common_vm_setup(True) + + self.kernel_params =3D (self.distro.default_kernel_params + + ' quiet intel_iommu=3Don x2apic_phys') + self.run_and_check() + self.ssh_command('dmesg | grep "Switched APIC routing to physical = x2apic"') + + def test_cluster_x2apic(self): + """ + :avocado: tags=3Dcluster_x2apic + """ + + self.common_vm_setup(True) + self.kernel_params =3D (self.distro.default_kernel_params + + ' quiet intel_iommu=3Don') + self.run_and_check() + self.ssh_command('dmesg | grep "Switched APIC routing to cluster x= 2apic"') --=20 2.25.1