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bh=LgxqwaxiolQtVNA7/arrNKztezL1tC9Ut/TMgeuYP2U=; b=ZSRvD1zcGtTrJ6ZDZdfdu61Dr2cAv4zK6LSwrP3br5mmo6JXenyfyVAHUSoKjJDVLdz4FN ActwrqUStekByor16Er3ZSMoAPWX2bETxPtNrM4cvpPH/x9zJcspdECp1lSTXQvp0mA97T AOmXSUCGzXpu7rvOMSGS3WgNwz092Rg= X-MC-Unique: f_7-ah3IPQKZhWuN5-GHeQ-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, richard.henderson@linaro.org, peter.maydell@linaro.org, pbonzini@redhat.com, qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH v2] target/arm: Add raw_writes ops for register whose write induce TLB maintenance Date: Mon, 13 Feb 2023 19:38:03 +0100 Message-Id: <20230213183803.3239258-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.1 on 10.11.54.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1676313515902100003 Content-Type: text/plain; charset="utf-8" Some registers whose 'cooked' writefns induce TLB maintenance do not have raw_writefn ops defined. If only the writefn ops is set (ie. no raw_writefn is provided), it is assumed the cooked also work as the raw one. For those registers it is not obvious the tlb_flush works on KVM mode so better/safer setting the raw write. Signed-off-by: Eric Auger Suggested-by: Peter Maydell --- v1 -> v2: - do not add raw_writefn if type is set to ARM_CP_NO_RAW [Peter] I am not familiar with those callbacks. I am not sure whether the .raw_writefn must be set only for registers only doing some TLB maintenance or shall be set safely on other registers doing TLB maintenance + other state settings. --- target/arm/helper.c | 39 +++++++++++++++++++++++---------------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c62ed05c12..0bd8806999 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -719,16 +719,20 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] =3D { * the unified TLB ops but also the dside/iside/inner-shareable varian= ts. */ { .name =3D "TLBIALL", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D 0, .access =3D PL1_W, .writefn =3D tlbia= ll_write, + .opc1 =3D CP_ANY, .opc2 =3D 0, .access =3D PL1_W, + .writefn =3D tlbiall_write, .raw_writefn =3D raw_write, .type =3D ARM_CP_NO_RAW }, { .name =3D "TLBIMVA", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D 1, .access =3D PL1_W, .writefn =3D tlbim= va_write, + .opc1 =3D CP_ANY, .opc2 =3D 1, .access =3D PL1_W, + .writefn =3D tlbimva_write, .raw_writefn =3D raw_write, .type =3D ARM_CP_NO_RAW }, { .name =3D "TLBIASID", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D 2, .access =3D PL1_W, .writefn =3D tlbia= sid_write, + .opc1 =3D CP_ANY, .opc2 =3D 2, .access =3D PL1_W, + .writefn =3D tlbiasid_write, .raw_writefn =3D raw_write, .type =3D ARM_CP_NO_RAW }, { .name =3D "TLBIMVAA", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D 3, .access =3D PL1_W, .writefn =3D tlbim= vaa_write, + .opc1 =3D CP_ANY, .opc2 =3D 3, .access =3D PL1_W, + .writefn =3D tlbimvaa_write, .raw_writefn =3D raw_write, .type =3D ARM_CP_NO_RAW }, { .name =3D "PRRR", .cp =3D 15, .crn =3D 10, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_NOP }, @@ -4183,14 +4187,14 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_TTBR0_EL1, - .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .raw_writefn =3D ra= w_write, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, { .name =3D "TTBR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_TTBR1_EL1, - .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .raw_writefn =3D ra= w_write, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, @@ -4450,13 +4454,13 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) }, - .writefn =3D vmsa_ttbr_write, }, + .writefn =3D vmsa_ttbr_write, .raw_writefn =3D raw_write }, { .name =3D "TTBR1", .cp =3D 15, .crm =3D 2, .opc1 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) }, - .writefn =3D vmsa_ttbr_write, }, + .writefn =3D vmsa_ttbr_write, .raw_writefn =3D raw_write }, }; =20 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -5899,12 +5903,12 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .type =3D ARM_CP_IO, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_= el2), - .writefn =3D hcr_write }, + .writefn =3D hcr_write, .raw_writefn =3D raw_write }, { .name =3D "HCR", .state =3D ARM_CP_STATE_AA32, .type =3D ARM_CP_ALIAS | ARM_CP_IO, .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_= el2), - .writefn =3D hcr_writelow }, + .writefn =3D hcr_writelow, .raw_writefn =3D raw_write }, { .name =3D "HACR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 7, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, @@ -5971,6 +5975,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, .access =3D PL2_RW, .writefn =3D vmsa_tcr_el12_write, + .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[2]) }, { .name =3D "VTCR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, @@ -5987,10 +5992,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, .fieldoffset =3D offsetof(CPUARMState, cp15.vttbr_el2), - .writefn =3D vttbr_write }, + .writefn =3D vttbr_write, .raw_writefn =3D raw_write }, { .name =3D "VTTBR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .writefn =3D vttbr_write, + .access =3D PL2_RW, .writefn =3D vttbr_write, .raw_writefn =3D raw_w= rite, .fieldoffset =3D offsetof(CPUARMState, cp15.vttbr_el2) }, { .name =3D "SCTLR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, @@ -6002,7 +6007,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[2]) }, { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .resetvalue =3D 0, .writefn =3D vmsa_tcr_ttbr_el= 2_write, + .access =3D PL2_RW, .resetvalue =3D 0, + .writefn =3D vmsa_tcr_ttbr_el2_write, .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[2]) }, { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2, .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, @@ -6139,7 +6145,7 @@ static const ARMCPRegInfo el2_v8_cp_reginfo[] =3D { .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, .access =3D PL2_RW, .fieldoffset =3D offsetofhigh32(CPUARMState, cp15.hcr_el2), - .writefn =3D hcr_writehigh }, + .writefn =3D hcr_writehigh, .raw_writefn =3D raw_write }, }; =20 static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri, @@ -6189,12 +6195,12 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { { .name =3D "SCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.scr_= el3), - .resetfn =3D scr_reset, .writefn =3D scr_write }, + .resetfn =3D scr_reset, .writefn =3D scr_write, .raw_writefn =3D raw= _write }, { .name =3D "SCR", .type =3D ARM_CP_ALIAS | ARM_CP_NEWEL, .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.scr_el3), - .writefn =3D scr_write }, + .writefn =3D scr_write, .raw_writefn =3D raw_write }, { .name =3D "SDER32_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, .access =3D PL3_RW, .resetvalue =3D 0, @@ -7862,6 +7868,7 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { { .name =3D "TTBR1_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, + .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr1_el[2]) }, #ifndef CONFIG_USER_ONLY { .name =3D "CNTHV_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, --=20 2.37.3