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Date: Sun, 12 Feb 2023 00:28:12 -0800 Message-Id: <20230212082812.55101-1-ricky@rzhou.org> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=ricky.zhou@gmail.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1676190568213100003 Content-Type: text/plain; charset="utf-8" Fix the exception classes for some SSE/AVX instructions to match what is documented in the Intel manual. Most of these changes have no functional effect on the behavior that qemu implements (primarily >=3D 16-byte memory alignment checks). For example, since qemu does not implement the AC flag, there is no difference in behavior between Exception Classes 4 and 5 for instructions where the SSE version only takes <16 byte memory operands. There is one functional change: Before this change, MOVNTPS and MOVNTPD were labeled as Exception Class 4 (only requiring alignment for legacy SSE instructions). This changes them to Exception Class 1 (always requiring memory alignment), as documented in the Intel manual. Signed-off-by: Ricky Zhou --- target/i386/tcg/decode-new.c.inc | 79 ++++++++++++++++---------------- 1 file changed, 40 insertions(+), 39 deletions(-) diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index d5fd8d965c..a9060c3268 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -237,7 +237,7 @@ static void decode_group14(DisasContext *s, CPUX86State= *env, X86OpEntry *entry, static void decode_0F6F(DisasContext *s, CPUX86State *env, X86OpEntry *ent= ry, uint8_t *b) { static const X86OpEntry opcodes_0F6F[4] =3D { - X86_OP_ENTRY3(MOVDQ, P,q, None,None, Q,q, vex1 mmx), /* mov= q */ + X86_OP_ENTRY3(MOVDQ, P,q, None,None, Q,q, vex5 mmx), /* mov= q */ X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1), /* mov= dqa */ X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* mov= dqu */ {}, @@ -274,9 +274,9 @@ static void decode_0F78(DisasContext *s, CPUX86State *e= nv, X86OpEntry *entry, ui { static const X86OpEntry opcodes_0F78[4] =3D { {}, - X86_OP_ENTRY3(EXTRQ_i, V,x, None,None, I,w, cpuid(SSE4A)), + X86_OP_ENTRY3(EXTRQ_i, V,x, None,None, I,w, cpuid(SSE4A)), = /* AMD extension */ {}, - X86_OP_ENTRY3(INSERTQ_i, V,x, U,x, I,w, cpuid(SSE4A)), + X86_OP_ENTRY3(INSERTQ_i, V,x, U,x, I,w, cpuid(SSE4A)), = /* AMD extension */ }; *entry =3D *decode_by_prefix(s, opcodes_0F78); } @@ -284,9 +284,9 @@ static void decode_0F78(DisasContext *s, CPUX86State *e= nv, X86OpEntry *entry, ui static void decode_0F79(DisasContext *s, CPUX86State *env, X86OpEntry *ent= ry, uint8_t *b) { if (s->prefix & PREFIX_REPNZ) { - entry->gen =3D gen_INSERTQ_r; + entry->gen =3D gen_INSERTQ_r; /* AMD extension */ } else if (s->prefix & PREFIX_DATA) { - entry->gen =3D gen_EXTRQ_r; + entry->gen =3D gen_EXTRQ_r; /* AMD extension */ } else { entry->gen =3D NULL; }; @@ -306,7 +306,7 @@ static void decode_0F7E(DisasContext *s, CPUX86State *e= nv, X86OpEntry *entry, ui static void decode_0F7F(DisasContext *s, CPUX86State *env, X86OpEntry *ent= ry, uint8_t *b) { static const X86OpEntry opcodes_0F7F[4] =3D { - X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 mmx), /* movq= */ + X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex5 mmx), /* movq= */ X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1), /* movdqa */ X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4_unal), /* mov= dqu */ {}, @@ -639,15 +639,15 @@ static void decode_0F10(DisasContext *s, CPUX86State = *env, X86OpEntry *entry, ui static const X86OpEntry opcodes_0F10_reg[4] =3D { X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPS= */ X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPD= */ - X86_OP_ENTRY3(VMOVSS, V,x, H,x, W,x, vex4), - X86_OP_ENTRY3(VMOVLPx, V,x, H,x, W,x, vex4), /* MOVSD */ + X86_OP_ENTRY3(VMOVSS, V,x, H,x, W,x, vex5), + X86_OP_ENTRY3(VMOVLPx, V,x, H,x, W,x, vex5), /* MOVSD */ }; =20 static const X86OpEntry opcodes_0F10_mem[4] =3D { X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MO= VUPS */ X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MO= VUPD */ - X86_OP_ENTRY3(VMOVSS_ld, V,x, H,x, M,ss, vex4), - X86_OP_ENTRY3(VMOVSD_ld, V,x, H,x, M,sd, vex4), + X86_OP_ENTRY3(VMOVSS_ld, V,x, H,x, M,ss, vex5), + X86_OP_ENTRY3(VMOVSD_ld, V,x, H,x, M,sd, vex5), }; =20 if ((get_modrm(s, env) >> 6) =3D=3D 3) { @@ -660,17 +660,17 @@ static void decode_0F10(DisasContext *s, CPUX86State = *env, X86OpEntry *entry, ui static void decode_0F11(DisasContext *s, CPUX86State *env, X86OpEntry *ent= ry, uint8_t *b) { static const X86OpEntry opcodes_0F11_reg[4] =3D { - X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVPS */ - X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVPD */ - X86_OP_ENTRY3(VMOVSS, W,x, H,x, V,x, vex4), - X86_OP_ENTRY3(VMOVLPx, W,x, H,x, V,q, vex4), /* MOVSD */ + X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPS */ + X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPD */ + X86_OP_ENTRY3(VMOVSS, W,x, H,x, V,x, vex5), + X86_OP_ENTRY3(VMOVLPx, W,x, H,x, V,q, vex5), /* MOVSD */ }; =20 static const X86OpEntry opcodes_0F11_mem[4] =3D { - X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVPS */ - X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVPD */ - X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex4), - X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex4), /* MOVSD */ + X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPS */ + X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPD */ + X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex5), + X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex5), /* MOVSD */ }; =20 if ((get_modrm(s, env) >> 6) =3D=3D 3) { @@ -687,16 +687,16 @@ static void decode_0F12(DisasContext *s, CPUX86State = *env, X86OpEntry *entry, ui * Use dq for operand for compatibility with gen_MOVSD and * to allow VEX128 only. */ - X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex4), /* MOVLPS */ - X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex4), /* MOVLPD */ + X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex5), /* MOVLPS */ + X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex5), /* MOVLPD */ X86_OP_ENTRY3(VMOVSLDUP, V,x, None,None, W,x, vex4 cpuid(SSE3)), - X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, WM,q, vex4 cpuid(SSE3))= , /* qq if VEX.256 */ + X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, WM,q, vex5 cpuid(SSE3))= , /* qq if VEX.256 */ }; static const X86OpEntry opcodes_0F12_reg[4] =3D { - X86_OP_ENTRY3(VMOVHLPS, V,dq, H,dq, U,dq, vex4), - X86_OP_ENTRY3(VMOVLPx, W,x, H,x, U,q, vex4), /* MOVLPD = */ + X86_OP_ENTRY3(VMOVHLPS, V,dq, H,dq, U,dq, vex7), + X86_OP_ENTRY3(VMOVLPx, W,x, H,x, U,q, vex5), /* MOVLPD = */ X86_OP_ENTRY3(VMOVSLDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)), - X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)), + X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, U,x, vex5 cpuid(SSE3)), }; =20 if ((get_modrm(s, env) >> 6) =3D=3D 3) { @@ -716,15 +716,15 @@ static void decode_0F16(DisasContext *s, CPUX86State = *env, X86OpEntry *entry, ui * Operand 1 technically only reads the low 64 bits, but uses dq s= o that * it is easier to check for op0 =3D=3D op1 in an endianness-neutr= al manner. */ - X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex4), /* MOVHPS */ - X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex4), /* MOVHPD */ + X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex5), /* MOVHPS */ + X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex5), /* MOVHPD */ X86_OP_ENTRY3(VMOVSHDUP, V,x, None,None, W,x, vex4 cpuid(SSE3)), {}, }; static const X86OpEntry opcodes_0F16_reg[4] =3D { /* Same as above, operand 1 could be Hq if it wasn't for big-endia= n. */ - X86_OP_ENTRY3(VMOVLHPS, V,dq, H,dq, U,q, vex4), - X86_OP_ENTRY3(VMOVHPx, V,x, H,x, U,x, vex4), /* MOVHPD */ + X86_OP_ENTRY3(VMOVLHPS, V,dq, H,dq, U,q, vex7), + X86_OP_ENTRY3(VMOVHPx, V,x, H,x, U,x, vex5), /* MOVHPD */ X86_OP_ENTRY3(VMOVSHDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)), {}, }; @@ -750,8 +750,9 @@ static void decode_0F2A(DisasContext *s, CPUX86State *e= nv, X86OpEntry *entry, ui static void decode_0F2B(DisasContext *s, CPUX86State *env, X86OpEntry *ent= ry, uint8_t *b) { static const X86OpEntry opcodes_0F2B[4] =3D { - X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex4), /* MOVNTPS = */ - X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex4), /* MOVNTPD = */ + X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex1), /* MOVNTPS = */ + X86_OP_ENTRY3(MOVDQ, M,x, None,None, V,x, vex1), /* MOVNTPD = */ + /* AMD extensions */ X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex4 cpuid(SSE4A))= , /* MOVNTSS */ X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex4 cpuid(SSE4A))= , /* MOVNTSD */ }; @@ -813,7 +814,7 @@ static void decode_0FE6(DisasContext *s, CPUX86State *e= nv, X86OpEntry *entry, ui static const X86OpEntry opcodes_0FE6[4] =3D { {}, X86_OP_ENTRY2(VCVTTPD2DQ, V,x, W,x, vex2), - X86_OP_ENTRY2(VCVTDQ2PD, V,x, W,x, vex2), + X86_OP_ENTRY2(VCVTDQ2PD, V,x, W,x, vex5), X86_OP_ENTRY2(VCVTPD2DQ, V,x, W,x, vex2), }; *entry =3D *decode_by_prefix(s, opcodes_0FE6); @@ -831,17 +832,17 @@ static const X86OpEntry opcodes_0F[256] =3D { [0x10] =3D X86_OP_GROUP0(0F10), [0x11] =3D X86_OP_GROUP0(0F11), [0x12] =3D X86_OP_GROUP0(0F12), - [0x13] =3D X86_OP_ENTRY3(VMOVLPx_st, M,q, None,None, V,q, vex4 p_00_= 66), + [0x13] =3D X86_OP_ENTRY3(VMOVLPx_st, M,q, None,None, V,q, vex5 p_00_= 66), [0x14] =3D X86_OP_ENTRY3(VUNPCKLPx, V,x, H,x, W,x, vex4 p_00_= 66), [0x15] =3D X86_OP_ENTRY3(VUNPCKHPx, V,x, H,x, W,x, vex4 p_00_= 66), [0x16] =3D X86_OP_GROUP0(0F16), /* Incorrectly listed as Mq,Vq in the manual */ - [0x17] =3D X86_OP_ENTRY3(VMOVHPx_st, M,q, None,None, V,dq, vex4 p_00_= 66), + [0x17] =3D X86_OP_ENTRY3(VMOVHPx_st, M,q, None,None, V,dq, vex5 p_00_= 66), =20 [0x50] =3D X86_OP_ENTRY3(MOVMSK, G,y, None,None, U,x, vex7 p_00_66= ), - [0x51] =3D X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_= f3_f2), - [0x52] =3D X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3), - [0x53] =3D X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3), + [0x51] =3D X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_= f3_f2), /* sqrtps */ + [0x52] =3D X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3)= , /* rsqrtps */ + [0x53] =3D X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3)= , /* rcpps */ [0x54] =3D X86_OP_ENTRY3(PAND, V,x, H,x, W,x, vex4 p_00_66), /*= vand */ [0x55] =3D X86_OP_ENTRY3(PANDN, V,x, H,x, W,x, vex4 p_00_66), /*= vandn */ [0x56] =3D X86_OP_ENTRY3(POR, V,x, H,x, W,x, vex4 p_00_66), /*= vor */ @@ -871,15 +872,15 @@ static const X86OpEntry opcodes_0F[256] =3D { [0x2B] =3D X86_OP_GROUP0(0F2B), [0x2C] =3D X86_OP_GROUP0(0F2C), [0x2D] =3D X86_OP_GROUP0(0F2D), - [0x2E] =3D X86_OP_ENTRY3(VUCOMI, None,None, V,x, W,x, vex4 p_00_6= 6), - [0x2F] =3D X86_OP_ENTRY3(VCOMI, None,None, V,x, W,x, vex4 p_00_6= 6), + [0x2E] =3D X86_OP_ENTRY3(VUCOMI, None,None, V,x, W,x, vex3 p_00_6= 6), + [0x2F] =3D X86_OP_ENTRY3(VCOMI, None,None, V,x, W,x, vex3 p_00_6= 6), =20 [0x38] =3D X86_OP_GROUP0(0F38), [0x3a] =3D X86_OP_GROUP0(0F3A), =20 [0x58] =3D X86_OP_ENTRY3(VADD, V,x, H,x, W,x, vex2_rep3 p_00_66_= f3_f2), [0x59] =3D X86_OP_ENTRY3(VMUL, V,x, H,x, W,x, vex2_rep3 p_00_66_= f3_f2), - [0x5a] =3D X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_= f3_f2), + [0x5a] =3D X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_= f3_f2), /* CVTPS2PD */ [0x5b] =3D X86_OP_GROUP0(0F5B), [0x5c] =3D X86_OP_ENTRY3(VSUB, V,x, H,x, W,x, vex2_rep3 p_00_66_= f3_f2), [0x5d] =3D X86_OP_ENTRY3(VMIN, V,x, H,x, W,x, vex2_rep3 p_00_66_= f3_f2), --=20 2.39.1