From nobody Sun May 19 14:40:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1676071902; cv=none; d=zohomail.com; s=zohoarc; b=IyjsOAhY7hA7+zBW6FDJnNXIB1LvdbFyvWU7xInEdRGylvlEf+KuJHYit0/H2U9XSa6e2lZkgVV/UY2ZTYi6bj8oe7zdAKRu/HOsgZ3ySodOMr0//fEhE/aOsmSf/P95WB15sw+Ll0noAE43dmp+w4wXVkeh6Lrzor3W39U5xKE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676071902; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QGuPT6na6ZOMImjVznTFeUyZRr+VxZ3/v7FhbrE4GUA=; b=Mr3HcNg5WOs4zpo6kZDpYJZJvxfLMumku7sCilDgYKRvAmk1LqdV5z7Sr6lblPRKTwoqQWljG4LWdF5afDqjr4MoPmkDrgnmIJ9hQTEeuVz5XsX6leBPz4GUSg7Ynr4bmi/FvgrC6hue3maxoYOoowKNb8F3enbH/hQTwmGlEqY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1676071902737454.48451224278585; Fri, 10 Feb 2023 15:31:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pQcrc-00068d-TI; Fri, 10 Feb 2023 18:31:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pQcrb-000684-4s for qemu-devel@nongnu.org; Fri, 10 Feb 2023 18:31:31 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pQcrY-0007qE-NT for qemu-devel@nongnu.org; Fri, 10 Feb 2023 18:31:30 -0500 Received: by mail-wr1-x42d.google.com with SMTP id y1so6690053wru.2 for ; Fri, 10 Feb 2023 15:31:25 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id g16-20020adfe410000000b002bfae1398bbsm4629060wrm.42.2023.02.10.15.31.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Feb 2023 15:31:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QGuPT6na6ZOMImjVznTFeUyZRr+VxZ3/v7FhbrE4GUA=; b=cs5rtO/wNZRV/JQHntB3KRY+mQg/0TVskuXfDXiP0dp3C5E6vv4hAzlO+T6FassBXZ GNMrzPFL5hDOdKjD+Xt8ukJg3Ftmr9CV5SuS9nSvb2vfYnKvRsKegsqp6R0rG+8SmM7u NxX6qJfBGJzvvyZfKItdJdzJzbWwSYEQn5kgnHc0GPgwZb74jAb8QT+ffboPUl+3AtRY UEcjlVLqBz0dWKxQdkX5hGk6ksYtZWneS3jrCRJ2A8pX8IZSTVFpveyjGb8yNiGaV7Ok ho7iFeAFY2eNDjsDLz96MxhoK1kKUgJ+eywfSVZAN9XxFP4TU+t9QiNSSHWzZnuq++2i 8GKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QGuPT6na6ZOMImjVznTFeUyZRr+VxZ3/v7FhbrE4GUA=; b=RxlL0Clv4CLWuY4KLV9/6TqXyvElJ3PWr/8EkhOryr+zus5OpGvbv7fZVcToehhjmX 2Qfd6wuT+7b1iPKM70ST2cdEVVtKUqC3/zrY3Mh9wRN/xB2kMHNuA6HA6jpdT6Xg+tv1 BmbqJ+9nuMsmZGYriXBheSYsjjawU8F41sxfdex/tDGCM+Vh/4Hr12+lT8sQvXo/JIZp tRZ9ZttEIsAoveF5yUAMsVY9KPyfezOSn4nya/tmVqUSB6WQDrPBFzNRXX/JPfa24jDb nb8u9e9aO7wDFmBlZM2I1BS5dlMGDN2Av1A6t2RvNVlYW6pHFjcbAw5bpFLVjIP34iH6 Fz8g== X-Gm-Message-State: AO0yUKXHwWn6pmXkCz7BDPz5an8okWGRwmzJM1geNrspHNYLS4mPQZBr wUSSbAx7tTep3oFJxsDAOitzJfRy3J4ep4y7 X-Google-Smtp-Source: AK7set9J4w/OnNqpxaLBd2r+/TjsfNGNdp9aE2YDg7/KTrN+fvAWVwz2kWKGVZHCZYx6lW1Ua3O34A== X-Received: by 2002:a5d:4b90:0:b0:2c4:848:bbd4 with SMTP id b16-20020a5d4b90000000b002c40848bbd4mr7425919wrt.36.1676071884213; Fri, 10 Feb 2023 15:31:24 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Richard Henderson , "Michael S. Tsirkin" , Thomas Huth , Eduardo Habkost , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Huacai Chen , Jiaxun Yang Subject: [PATCH 1/3] hw/rtc/mc146818rtc: Rename RTCState -> MC146818RtcState Date: Sat, 11 Feb 2023 00:31:14 +0100 Message-Id: <20230210233116.80311-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230210233116.80311-1-philmd@linaro.org> References: <20230210233116.80311-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1676071903881100001 RTCState only represents a Motorola MC146818 model, not any RTC chipset. Rename the structure as MC146818RtcState using: $ sed -i -e s/RTCState/MC146818RtcState/g $(git grep -wl RTCState) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/isa/piix4.c | 2 +- hw/isa/vt82c686.c | 2 +- hw/rtc/mc146818rtc.c | 116 +++++++++++++++++------------------ include/hw/rtc/mc146818rtc.h | 6 +- 4 files changed, 63 insertions(+), 63 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index de60ceef73..e2fafc3b13 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -47,7 +47,7 @@ struct PIIX4State { qemu_irq cpu_intr; qemu_irq *isa; =20 - RTCState rtc; + MC146818RtcState rtc; PCIIDEState ide; UHCIState uhci; PIIX4PMState pm; diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 3f9bd0c04d..67cbb658aa 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -550,7 +550,7 @@ struct ViaISAState { qemu_irq cpu_intr; qemu_irq *isa_irqs; ViaSuperIOState via_sio; - RTCState rtc; + MC146818RtcState rtc; PCIIDEState ide; UHCIState uhci[2]; ViaPMState pm; diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c index ba612a151d..08f6c0e0c5 100644 --- a/hw/rtc/mc146818rtc.c +++ b/hw/rtc/mc146818rtc.c @@ -71,19 +71,19 @@ =20 #define RTC_ISA_BASE 0x70 =20 -static void rtc_set_time(RTCState *s); -static void rtc_update_time(RTCState *s); -static void rtc_set_cmos(RTCState *s, const struct tm *tm); -static inline int rtc_from_bcd(RTCState *s, int a); -static uint64_t get_next_alarm(RTCState *s); +static void rtc_set_time(MC146818RtcState *s); +static void rtc_update_time(MC146818RtcState *s); +static void rtc_set_cmos(MC146818RtcState *s, const struct tm *tm); +static inline int rtc_from_bcd(MC146818RtcState *s, int a); +static uint64_t get_next_alarm(MC146818RtcState *s); =20 -static inline bool rtc_running(RTCState *s) +static inline bool rtc_running(MC146818RtcState *s) { return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) && (s->cmos_data[RTC_REG_A] & 0x70) <=3D 0x20); } =20 -static uint64_t get_guest_rtc_ns(RTCState *s) +static uint64_t get_guest_rtc_ns(MC146818RtcState *s) { uint64_t guest_clock =3D qemu_clock_get_ns(rtc_clock); =20 @@ -91,7 +91,7 @@ static uint64_t get_guest_rtc_ns(RTCState *s) guest_clock - s->last_update + s->offset; } =20 -static void rtc_coalesced_timer_update(RTCState *s) +static void rtc_coalesced_timer_update(MC146818RtcState *s) { if (s->irq_coalesced =3D=3D 0) { timer_del(s->coalesced_timer); @@ -104,19 +104,19 @@ static void rtc_coalesced_timer_update(RTCState *s) } } =20 -static QLIST_HEAD(, RTCState) rtc_devices =3D +static QLIST_HEAD(, MC146818RtcState) rtc_devices =3D QLIST_HEAD_INITIALIZER(rtc_devices); =20 void qmp_rtc_reset_reinjection(Error **errp) { - RTCState *s; + MC146818RtcState *s; =20 QLIST_FOREACH(s, &rtc_devices, link) { s->irq_coalesced =3D 0; } } =20 -static bool rtc_policy_slew_deliver_irq(RTCState *s) +static bool rtc_policy_slew_deliver_irq(MC146818RtcState *s) { kvm_reset_irq_delivered(); qemu_irq_raise(s->irq); @@ -125,7 +125,7 @@ static bool rtc_policy_slew_deliver_irq(RTCState *s) =20 static void rtc_coalesced_timer(void *opaque) { - RTCState *s =3D opaque; + MC146818RtcState *s =3D opaque; =20 if (s->irq_coalesced !=3D 0) { s->cmos_data[RTC_REG_C] |=3D 0xc0; @@ -140,7 +140,7 @@ static void rtc_coalesced_timer(void *opaque) rtc_coalesced_timer_update(s); } =20 -static uint32_t rtc_periodic_clock_ticks(RTCState *s) +static uint32_t rtc_periodic_clock_ticks(MC146818RtcState *s) { int period_code; =20 @@ -158,7 +158,7 @@ static uint32_t rtc_periodic_clock_ticks(RTCState *s) * is just due to period adjustment. */ static void -periodic_timer_update(RTCState *s, int64_t current_time, uint32_t old_peri= od, bool period_change) +periodic_timer_update(MC146818RtcState *s, int64_t current_time, uint32_t = old_period, bool period_change) { uint32_t period; int64_t cur_clock, next_irq_clock, lost_clock =3D 0; @@ -234,7 +234,7 @@ periodic_timer_update(RTCState *s, int64_t current_time= , uint32_t old_period, bo =20 static void rtc_periodic_timer(void *opaque) { - RTCState *s =3D opaque; + MC146818RtcState *s =3D opaque; =20 periodic_timer_update(s, s->next_periodic_time, s->period, false); s->cmos_data[RTC_REG_C] |=3D REG_C_PF; @@ -255,7 +255,7 @@ static void rtc_periodic_timer(void *opaque) } =20 /* handle update-ended timer */ -static void check_update_timer(RTCState *s) +static void check_update_timer(MC146818RtcState *s) { uint64_t next_update_time; uint64_t guest_nsec; @@ -306,7 +306,7 @@ static void check_update_timer(RTCState *s) } } =20 -static inline uint8_t convert_hour(RTCState *s, uint8_t hour) +static inline uint8_t convert_hour(MC146818RtcState *s, uint8_t hour) { if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) { hour %=3D 12; @@ -317,7 +317,7 @@ static inline uint8_t convert_hour(RTCState *s, uint8_t= hour) return hour; } =20 -static uint64_t get_next_alarm(RTCState *s) +static uint64_t get_next_alarm(MC146818RtcState *s) { int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec; int32_t hour, min, sec; @@ -410,7 +410,7 @@ static uint64_t get_next_alarm(RTCState *s) =20 static void rtc_update_timer(void *opaque) { - RTCState *s =3D opaque; + MC146818RtcState *s =3D opaque; int32_t irqs =3D REG_C_UF; int32_t new_irqs; =20 @@ -439,7 +439,7 @@ static void rtc_update_timer(void *opaque) static void cmos_ioport_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { - RTCState *s =3D opaque; + MC146818RtcState *s =3D opaque; uint32_t old_period; bool update_periodic_timer; =20 @@ -557,7 +557,7 @@ static void cmos_ioport_write(void *opaque, hwaddr addr, } } =20 -static inline int rtc_to_bcd(RTCState *s, int a) +static inline int rtc_to_bcd(MC146818RtcState *s, int a) { if (s->cmos_data[RTC_REG_B] & REG_B_DM) { return a; @@ -566,7 +566,7 @@ static inline int rtc_to_bcd(RTCState *s, int a) } } =20 -static inline int rtc_from_bcd(RTCState *s, int a) +static inline int rtc_from_bcd(MC146818RtcState *s, int a) { if ((a & 0xc0) =3D=3D 0xc0) { return -1; @@ -578,7 +578,7 @@ static inline int rtc_from_bcd(RTCState *s, int a) } } =20 -static void rtc_get_time(RTCState *s, struct tm *tm) +static void rtc_get_time(MC146818RtcState *s, struct tm *tm) { tm->tm_sec =3D rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); tm->tm_min =3D rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); @@ -597,7 +597,7 @@ static void rtc_get_time(RTCState *s, struct tm *tm) rtc_from_bcd(s, s->cmos_data[RTC_CENTURY]) * 100 - 1900; } =20 -static void rtc_set_time(RTCState *s) +static void rtc_set_time(MC146818RtcState *s) { struct tm tm; g_autofree const char *qom_path =3D object_get_canonical_path(OBJECT(s= )); @@ -609,7 +609,7 @@ static void rtc_set_time(RTCState *s) qapi_event_send_rtc_change(qemu_timedate_diff(&tm), qom_path); } =20 -static void rtc_set_cmos(RTCState *s, const struct tm *tm) +static void rtc_set_cmos(MC146818RtcState *s, const struct tm *tm) { int year; =20 @@ -633,7 +633,7 @@ static void rtc_set_cmos(RTCState *s, const struct tm *= tm) s->cmos_data[RTC_CENTURY] =3D rtc_to_bcd(s, year / 100); } =20 -static void rtc_update_time(RTCState *s) +static void rtc_update_time(MC146818RtcState *s) { struct tm ret; time_t guest_sec; @@ -649,7 +649,7 @@ static void rtc_update_time(RTCState *s) } } =20 -static int update_in_progress(RTCState *s) +static int update_in_progress(MC146818RtcState *s) { int64_t guest_nsec; =20 @@ -678,7 +678,7 @@ static int update_in_progress(RTCState *s) static uint64_t cmos_ioport_read(void *opaque, hwaddr addr, unsigned size) { - RTCState *s =3D opaque; + MC146818RtcState *s =3D opaque; int ret; if ((addr & 1) =3D=3D 0) { return 0xff; @@ -741,21 +741,21 @@ static uint64_t cmos_ioport_read(void *opaque, hwaddr= addr, =20 void rtc_set_memory(ISADevice *dev, int addr, int val) { - RTCState *s =3D MC146818_RTC(dev); + MC146818RtcState *s =3D MC146818_RTC(dev); if (addr >=3D 0 && addr <=3D 127) s->cmos_data[addr] =3D val; } =20 int rtc_get_memory(ISADevice *dev, int addr) { - RTCState *s =3D MC146818_RTC(dev); + MC146818RtcState *s =3D MC146818_RTC(dev); assert(addr >=3D 0 && addr <=3D 127); return s->cmos_data[addr]; } =20 static void rtc_set_date_from_host(ISADevice *dev) { - RTCState *s =3D MC146818_RTC(dev); + MC146818RtcState *s =3D MC146818_RTC(dev); struct tm tm; =20 qemu_get_timedate(&tm, 0); @@ -770,7 +770,7 @@ static void rtc_set_date_from_host(ISADevice *dev) =20 static int rtc_pre_save(void *opaque) { - RTCState *s =3D opaque; + MC146818RtcState *s =3D opaque; =20 rtc_update_time(s); =20 @@ -779,7 +779,7 @@ static int rtc_pre_save(void *opaque) =20 static int rtc_post_load(void *opaque, int version_id) { - RTCState *s =3D opaque; + MC146818RtcState *s =3D opaque; =20 if (version_id <=3D 2 || rtc_clock =3D=3D QEMU_CLOCK_REALTIME) { rtc_set_time(s); @@ -810,7 +810,7 @@ static int rtc_post_load(void *opaque, int version_id) =20 static bool rtc_irq_reinject_on_ack_count_needed(void *opaque) { - RTCState *s =3D (RTCState *)opaque; + MC146818RtcState *s =3D (MC146818RtcState *)opaque; return s->irq_reinject_on_ack_count !=3D 0; } =20 @@ -820,7 +820,7 @@ static const VMStateDescription vmstate_rtc_irq_reinjec= t_on_ack_count =3D { .minimum_version_id =3D 1, .needed =3D rtc_irq_reinject_on_ack_count_needed, .fields =3D (VMStateField[]) { - VMSTATE_UINT16(irq_reinject_on_ack_count, RTCState), + VMSTATE_UINT16(irq_reinject_on_ack_count, MC146818RtcState), VMSTATE_END_OF_LIST() } }; @@ -832,19 +832,19 @@ static const VMStateDescription vmstate_rtc =3D { .pre_save =3D rtc_pre_save, .post_load =3D rtc_post_load, .fields =3D (VMStateField[]) { - VMSTATE_BUFFER(cmos_data, RTCState), - VMSTATE_UINT8(cmos_index, RTCState), + VMSTATE_BUFFER(cmos_data, MC146818RtcState), + VMSTATE_UINT8(cmos_index, MC146818RtcState), VMSTATE_UNUSED(7*4), - VMSTATE_TIMER_PTR(periodic_timer, RTCState), - VMSTATE_INT64(next_periodic_time, RTCState), + VMSTATE_TIMER_PTR(periodic_timer, MC146818RtcState), + VMSTATE_INT64(next_periodic_time, MC146818RtcState), VMSTATE_UNUSED(3*8), - VMSTATE_UINT32_V(irq_coalesced, RTCState, 2), - VMSTATE_UINT32_V(period, RTCState, 2), - VMSTATE_UINT64_V(base_rtc, RTCState, 3), - VMSTATE_UINT64_V(last_update, RTCState, 3), - VMSTATE_INT64_V(offset, RTCState, 3), - VMSTATE_TIMER_PTR_V(update_timer, RTCState, 3), - VMSTATE_UINT64_V(next_alarm_time, RTCState, 3), + VMSTATE_UINT32_V(irq_coalesced, MC146818RtcState, 2), + VMSTATE_UINT32_V(period, MC146818RtcState, 2), + VMSTATE_UINT64_V(base_rtc, MC146818RtcState, 3), + VMSTATE_UINT64_V(last_update, MC146818RtcState, 3), + VMSTATE_INT64_V(offset, MC146818RtcState, 3), + VMSTATE_TIMER_PTR_V(update_timer, MC146818RtcState, 3), + VMSTATE_UINT64_V(next_alarm_time, MC146818RtcState, 3), VMSTATE_END_OF_LIST() }, .subsections =3D (const VMStateDescription*[]) { @@ -857,7 +857,7 @@ static const VMStateDescription vmstate_rtc =3D { BIOS will read it and start S3 resume at POST Entry */ static void rtc_notify_suspend(Notifier *notifier, void *data) { - RTCState *s =3D container_of(notifier, RTCState, suspend_notifier); + MC146818RtcState *s =3D container_of(notifier, MC146818RtcState, suspe= nd_notifier); rtc_set_memory(ISA_DEVICE(s), 0xF, 0xFE); } =20 @@ -873,7 +873,7 @@ static const MemoryRegionOps cmos_ops =3D { =20 static void rtc_get_date(Object *obj, struct tm *current_tm, Error **errp) { - RTCState *s =3D MC146818_RTC(obj); + MC146818RtcState *s =3D MC146818_RTC(obj); =20 rtc_update_time(s); rtc_get_time(s, current_tm); @@ -882,7 +882,7 @@ static void rtc_get_date(Object *obj, struct tm *curren= t_tm, Error **errp) static void rtc_realizefn(DeviceState *dev, Error **errp) { ISADevice *isadev =3D ISA_DEVICE(dev); - RTCState *s =3D MC146818_RTC(dev); + MC146818RtcState *s =3D MC146818_RTC(dev); =20 s->cmos_data[RTC_REG_A] =3D 0x26; s->cmos_data[RTC_REG_B] =3D 0x02; @@ -949,7 +949,7 @@ ISADevice *mc146818_rtc_init(ISABus *bus, int base_year= , qemu_irq intercept_irq) { DeviceState *dev; ISADevice *isadev; - RTCState *s; + MC146818RtcState *s; =20 isadev =3D isa_new(TYPE_MC146818_RTC); dev =3D DEVICE(isadev); @@ -969,17 +969,17 @@ ISADevice *mc146818_rtc_init(ISABus *bus, int base_ye= ar, qemu_irq intercept_irq) } =20 static Property mc146818rtc_properties[] =3D { - DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980), - DEFINE_PROP_UINT16("iobase", RTCState, io_base, RTC_ISA_BASE), - DEFINE_PROP_UINT8("irq", RTCState, isairq, RTC_ISA_IRQ), - DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState, + DEFINE_PROP_INT32("base_year", MC146818RtcState, base_year, 1980), + DEFINE_PROP_UINT16("iobase", MC146818RtcState, io_base, RTC_ISA_BASE), + DEFINE_PROP_UINT8("irq", MC146818RtcState, isairq, RTC_ISA_IRQ), + DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", MC146818RtcState, lost_tick_policy, LOST_TICK_POLICY_DISCARD), DEFINE_PROP_END_OF_LIST(), }; =20 static void rtc_reset_enter(Object *obj, ResetType type) { - RTCState *s =3D MC146818_RTC(obj); + MC146818RtcState *s =3D MC146818_RTC(obj); =20 /* Reason: VM do suspend self will set 0xfe * Reset any values other than 0xfe(Guest suspend case) */ @@ -1000,14 +1000,14 @@ static void rtc_reset_enter(Object *obj, ResetType = type) =20 static void rtc_reset_hold(Object *obj) { - RTCState *s =3D MC146818_RTC(obj); + MC146818RtcState *s =3D MC146818_RTC(obj); =20 qemu_irq_lower(s->irq); } =20 static void rtc_build_aml(AcpiDevAmlIf *adev, Aml *scope) { - RTCState *s =3D MC146818_RTC(adev); + MC146818RtcState *s =3D MC146818_RTC(adev); Aml *dev; Aml *crs; =20 @@ -1045,7 +1045,7 @@ static void rtc_class_initfn(ObjectClass *klass, void= *data) static const TypeInfo mc146818rtc_info =3D { .name =3D TYPE_MC146818_RTC, .parent =3D TYPE_ISA_DEVICE, - .instance_size =3D sizeof(RTCState), + .instance_size =3D sizeof(MC146818RtcState), .class_init =3D rtc_class_initfn, .interfaces =3D (InterfaceInfo[]) { { TYPE_ACPI_DEV_AML_IF }, diff --git a/include/hw/rtc/mc146818rtc.h b/include/hw/rtc/mc146818rtc.h index 45bcd6f040..11631af7e3 100644 --- a/include/hw/rtc/mc146818rtc.h +++ b/include/hw/rtc/mc146818rtc.h @@ -16,9 +16,9 @@ #include "qom/object.h" =20 #define TYPE_MC146818_RTC "mc146818rtc" -OBJECT_DECLARE_SIMPLE_TYPE(RTCState, MC146818_RTC) +OBJECT_DECLARE_SIMPLE_TYPE(MC146818RtcState, MC146818_RTC) =20 -struct RTCState { +struct MC146818RtcState { ISADevice parent_obj; =20 MemoryRegion io; @@ -46,7 +46,7 @@ struct RTCState { Notifier clock_reset_notifier; LostTickPolicy lost_tick_policy; Notifier suspend_notifier; - QLIST_ENTRY(RTCState) link; + QLIST_ENTRY(MC146818RtcState) link; }; =20 #define RTC_ISA_IRQ 8 --=20 2.38.1 From nobody Sun May 19 14:40:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1676071929; cv=none; d=zohomail.com; s=zohoarc; b=Giggsu0C5Qs7HKAi0/6OBbIAW3p1A+5zQ8EJjdyXTar6F6BJSt2+K41+tNl1Pk88WXzZ5dfZ6rbgG75tg+om57JSAYeKBqeoeD0nL6sRIJ+4Cxrz4S3gn0/q/qV6l9Bcr770jo7Or4YunnPL/MV9VdEdSDkHtu3eNAfimWZ9I6w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676071929; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Hr4ahbd9BnJloRVtV9Nrdh7BCCM/TxPydcu4B3q+EU0=; b=L3G6Pptq7Ev+j2svyQ8yjBN7e85uHn8mdz3mOvfQ17QghtQWAG8AR6Ue4sPCdcprnYobOcgPd0UkptngAemcGGnBMwV2YPzsar2Gt56N6UCFyUKwLrwp4tNTR38E4D3+bp1L6ooins1toQJbUMsrWlJjFYAqNfcJMD6jungG7OE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1676071929366276.3376748050956; Fri, 10 Feb 2023 15:32:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pQcrf-0006AC-HL; Fri, 10 Feb 2023 18:31:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pQcrd-00068m-6E for qemu-devel@nongnu.org; Fri, 10 Feb 2023 18:31:33 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pQcrb-0007qf-5p for qemu-devel@nongnu.org; Fri, 10 Feb 2023 18:31:32 -0500 Received: by mail-wr1-x431.google.com with SMTP id ba1so6673932wrb.5 for ; Fri, 10 Feb 2023 15:31:30 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id w11-20020adff9cb000000b002c54e9f6bc2sm225092wrr.77.2023.02.10.15.31.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Feb 2023 15:31:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hr4ahbd9BnJloRVtV9Nrdh7BCCM/TxPydcu4B3q+EU0=; b=H7Ewl9LOwb8k2lnQujRAsbyCbsV8F+3pJoQFvNNix/r+aXrATJ2QKmy91yD46KYvJg +sIS9voAERzJEOQz4nlAeT1mhV532DPMumyDtwpwoSU2PUjjnsxQclwOpLhHgTXLZWH4 zZKbl4cDG968H57uMtpRhMCQCkq+Jxm4DC7dqwVhHbgvR7+M4z+LhYie3eBKpAWbwZlf Gzm4WTlcZrtr/8tRJK3lIVEr0Nd49X/OhF4P/2xu/dp5Zu7SIqQJdv2lnsv+IfWVUTnt XhU4xJR2AbywsumMMgwef5E2WCzE6O7vizCVvVggvdrq+RHa5W31LVBZXU4Y9ROZhh7D eQ6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hr4ahbd9BnJloRVtV9Nrdh7BCCM/TxPydcu4B3q+EU0=; b=fbOpGmeKJbThndFiJbdZhPYqkDrXXn9tjjNOq9/LMyFcMscc7WkjW0CV/yTqyDgzo+ MGXY3s7QVuENrY3/+Ac3cHla/qc2HNMsRS6EU4Tzqer4x/IRmT2aLbdsmsRUYdYB7LNu CAgejf8FcRANWrKvMNl5wgEvIuKYDBZdM+hwUrqAsHW8ObVLg4Ygsaj7zMBWvfVsQJl3 +EIB58VfLaiEf0aHNmKtRxHuSUjawLD+07dXcjauLiIGw1liIXg36h6y3ueC3pvw4uWP ojRK2i8JmfNg5EJUDNsZV5F20O0RqqCgz6S6OEX5ez4LofzMGkZdfcKL2iExFFx/uUIz N+YQ== X-Gm-Message-State: AO0yUKUYcMXOoMp0B6mW8hbOxoR+oiXUqQc/DDGH/hs2hchcSfDd2T4g YhvrUykn112RgkAq88R0JMZgd8W1PGx0JINZ X-Google-Smtp-Source: AK7set99duLDnKur1Azi5jhivWRtpDyGd4qyKoU549+2c0zi/naOMsKIK68JPV2QEyXwLuwpE7JSUw== X-Received: by 2002:a5d:6203:0:b0:2c1:28dc:1561 with SMTP id y3-20020a5d6203000000b002c128dc1561mr14901627wru.44.1676071889536; Fri, 10 Feb 2023 15:31:29 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Richard Henderson , "Michael S. Tsirkin" , Thomas Huth , Eduardo Habkost , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Sergio Lopez , Marcel Apfelbaum Subject: [PATCH 2/3] hw/rtc/mc146818rtc: Pass MC146818RtcState instead of ISADevice argument Date: Sat, 11 Feb 2023 00:31:15 +0100 Message-Id: <20230210233116.80311-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230210233116.80311-1-philmd@linaro.org> References: <20230210233116.80311-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1676071931209100003 rtc_get_memory() and rtc_set_memory() methods can not take any TYPE_ISA_DEVICE object. They expect a TYPE_MC146818_RTC one. Simplify the API by passing a MC146818RtcState. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/i386/microvm.c | 6 ++---- hw/i386/pc.c | 16 +++++++++------- hw/i386/x86.c | 4 +++- hw/ppc/prep.c | 3 +-- hw/rtc/mc146818rtc.c | 13 ++++++------- include/hw/rtc/mc146818rtc.h | 8 ++++---- 6 files changed, 25 insertions(+), 25 deletions(-) diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index 29f30dd6d3..04b453cde5 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -57,7 +57,7 @@ #define MICROVM_QBOOT_FILENAME "qboot.rom" #define MICROVM_BIOS_FILENAME "bios-microvm.bin" =20 -static void microvm_set_rtc(MicrovmMachineState *mms, ISADevice *s) +static void microvm_set_rtc(MicrovmMachineState *mms, MC146818RtcState *s) { X86MachineState *x86ms =3D X86_MACHINE(mms); int val; @@ -161,7 +161,6 @@ static void microvm_devices_init(MicrovmMachineState *m= ms) const char *default_firmware; X86MachineState *x86ms =3D X86_MACHINE(mms); ISABus *isa_bus; - ISADevice *rtc_state; GSIState *gsi_state; int ioapics; int i; @@ -267,8 +266,7 @@ static void microvm_devices_init(MicrovmMachineState *m= ms) =20 if (mms->rtc =3D=3D ON_OFF_AUTO_ON || (mms->rtc =3D=3D ON_OFF_AUTO_AUTO && !kvm_enabled())) { - rtc_state =3D mc146818_rtc_init(isa_bus, 2000, NULL); - microvm_set_rtc(mms, rtc_state); + microvm_set_rtc(mms, mc146818_rtc_init(isa_bus, 2000, NULL)); } =20 if (mms->isa_serial) { diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 6e592bd969..606686dafc 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -439,7 +439,7 @@ static uint64_t ioportF0_read(void *opaque, hwaddr addr= , unsigned size) =20 #define REG_EQUIPMENT_BYTE 0x14 =20 -static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, +static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, int16_t cylinders, int8_t heads, int8_t sectors) { rtc_set_memory(s, type_ofs, 47); @@ -471,7 +471,8 @@ static int boot_device2nibble(char boot_device) return 0; } =20 -static void set_boot_dev(ISADevice *s, const char *boot_device, Error **er= rp) +static void set_boot_dev(MC146818RtcState *s, const char *boot_device, + Error **errp) { #define PC_MAX_BOOT_DEVICES 3 int nbds, bds[3] =3D { 0, }; @@ -499,7 +500,7 @@ static void pc_boot_set(void *opaque, const char *boot_= device, Error **errp) set_boot_dev(opaque, boot_device, errp); } =20 -static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) +static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *fl= oppy) { int val, nb, i; FloppyDriveType fd_type[2] =3D { FLOPPY_DRIVE_TYPE_NONE, @@ -537,7 +538,7 @@ static void pc_cmos_init_floppy(ISADevice *rtc_state, I= SADevice *floppy) } =20 typedef struct pc_cmos_init_late_arg { - ISADevice *rtc_state; + MC146818RtcState *rtc_state; BusState *idebus[2]; } pc_cmos_init_late_arg; =20 @@ -604,7 +605,7 @@ static ISADevice *pc_find_fdc0(void) static void pc_cmos_init_late(void *opaque) { pc_cmos_init_late_arg *arg =3D opaque; - ISADevice *s =3D arg->rtc_state; + MC146818RtcState *s =3D arg->rtc_state; int16_t cylinders; int8_t heads, sectors; int val; @@ -646,11 +647,12 @@ static void pc_cmos_init_late(void *opaque) =20 void pc_cmos_init(PCMachineState *pcms, BusState *idebus0, BusState *idebus1, - ISADevice *s) + ISADevice *rtc) { int val; static pc_cmos_init_late_arg arg; X86MachineState *x86ms =3D X86_MACHINE(pcms); + MC146818RtcState *s =3D MC146818_RTC(rtc); =20 /* various important CMOS locations needed by PC/Bochs bios */ =20 @@ -1304,7 +1306,7 @@ void pc_basic_device_init(struct PCMachineState *pcms, pit_alt_irq =3D qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); rtc_irq =3D qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); } - *rtc_state =3D mc146818_rtc_init(isa_bus, 2000, rtc_irq); + *rtc_state =3D ISA_DEVICE(mc146818_rtc_init(isa_bus, 2000, rtc_irq)); =20 qemu_register_boot_set(pc_boot_set, *rtc_state); =20 diff --git a/hw/i386/x86.c b/hw/i386/x86.c index eaff4227bd..5dbdd75bfc 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -151,8 +151,10 @@ void x86_cpus_init(X86MachineState *x86ms, int default= _cpu_version) } } =20 -void x86_rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) +void x86_rtc_set_cpus_count(ISADevice *s, uint16_t cpus_count) { + MC146818RtcState *rtc =3D MC146818_RTC(s); + if (cpus_count > 0xff) { /* * If the number of CPUs can't be represented in 8 bits, the diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index fcbe4c5837..076e2d0d22 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -212,10 +212,9 @@ static int PPC_NVRAM_set_params (Nvram *nvram, uint16_= t NVRAM_size, static int prep_set_cmos_checksum(DeviceState *dev, void *opaque) { uint16_t checksum =3D *(uint16_t *)opaque; - ISADevice *rtc; =20 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { - rtc =3D ISA_DEVICE(dev); + MC146818RtcState *rtc =3D MC146818_RTC(dev); rtc_set_memory(rtc, 0x2e, checksum & 0xff); rtc_set_memory(rtc, 0x3e, checksum & 0xff); rtc_set_memory(rtc, 0x2f, checksum >> 8); diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c index 08f6c0e0c5..478eee97e4 100644 --- a/hw/rtc/mc146818rtc.c +++ b/hw/rtc/mc146818rtc.c @@ -739,16 +739,14 @@ static uint64_t cmos_ioport_read(void *opaque, hwaddr= addr, } } =20 -void rtc_set_memory(ISADevice *dev, int addr, int val) +void rtc_set_memory(MC146818RtcState *s, int addr, int val) { - MC146818RtcState *s =3D MC146818_RTC(dev); if (addr >=3D 0 && addr <=3D 127) s->cmos_data[addr] =3D val; } =20 -int rtc_get_memory(ISADevice *dev, int addr) +int rtc_get_memory(MC146818RtcState *s, int addr) { - MC146818RtcState *s =3D MC146818_RTC(dev); assert(addr >=3D 0 && addr <=3D 127); return s->cmos_data[addr]; } @@ -858,7 +856,7 @@ static const VMStateDescription vmstate_rtc =3D { static void rtc_notify_suspend(Notifier *notifier, void *data) { MC146818RtcState *s =3D container_of(notifier, MC146818RtcState, suspe= nd_notifier); - rtc_set_memory(ISA_DEVICE(s), 0xF, 0xFE); + rtc_set_memory(s, 0xF, 0xFE); } =20 static const MemoryRegionOps cmos_ops =3D { @@ -945,7 +943,8 @@ static void rtc_realizefn(DeviceState *dev, Error **err= p) QLIST_INSERT_HEAD(&rtc_devices, s, link); } =20 -ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercep= t_irq) +MC146818RtcState *mc146818_rtc_init(ISABus *bus, int base_year, + qemu_irq intercept_irq) { DeviceState *dev; ISADevice *isadev; @@ -965,7 +964,7 @@ ISADevice *mc146818_rtc_init(ISABus *bus, int base_year= , qemu_irq intercept_irq) object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(isade= v), "date"); =20 - return isadev; + return s; } =20 static Property mc146818rtc_properties[] =3D { diff --git a/include/hw/rtc/mc146818rtc.h b/include/hw/rtc/mc146818rtc.h index 11631af7e3..a6b0c135c0 100644 --- a/include/hw/rtc/mc146818rtc.h +++ b/include/hw/rtc/mc146818rtc.h @@ -51,10 +51,10 @@ struct MC146818RtcState { =20 #define RTC_ISA_IRQ 8 =20 -ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, - qemu_irq intercept_irq); -void rtc_set_memory(ISADevice *dev, int addr, int val); -int rtc_get_memory(ISADevice *dev, int addr); +MC146818RtcState *mc146818_rtc_init(ISABus *bus, int base_year, + qemu_irq intercept_irq); +void rtc_set_memory(MC146818RtcState *s, int addr, int val); +int rtc_get_memory(MC146818RtcState *s, int addr); void qmp_rtc_reset_reinjection(Error **errp); =20 #endif /* HW_RTC_MC146818RTC_H */ --=20 2.38.1 From nobody Sun May 19 14:40:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1676071980; cv=none; d=zohomail.com; s=zohoarc; b=ckjU2AOnwiJdh7oX3gwLdoJouzPmg75kiZsW0DmSE6OwXbJsVa/pPUcB2BpAcQQOjaUTiacnnYc5+3j0mPOSYxheDmmTtHu3dxjYACNpzgG4TnIZbvbKfrCQTlbgCNtc345EBhsufw6DdN3/y68hbMaeqgaVp30mX4Y5zZjFob4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676071980; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=X5wXhLnzsqClbhoVFkPexTF9c4fLCApBCEoKfoI/Dzk=; b=eteShSqIyyE8cYI34tv39BLvRs5PzXCHERh8aGNo6RsiT3lz0gDlX5hNFWMTgPQNia8UjUOkA7GXZqA6n/ZjYI+F3ulCy6pN94xMbOCWBn2bIC/9kTWOxg6n/kdktrnCsQX8xV4o7JzZaIwbevU1IYUrtJYcUtaU2KH325ipBU8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167607198096066.3729019051824; Fri, 10 Feb 2023 15:33:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pQcrp-0006FB-Ll; Fri, 10 Feb 2023 18:31:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pQcrk-0006Ak-VH for qemu-devel@nongnu.org; Fri, 10 Feb 2023 18:31:43 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pQcrh-0007rm-8M for qemu-devel@nongnu.org; Fri, 10 Feb 2023 18:31:40 -0500 Received: by mail-wm1-x332.google.com with SMTP id n28-20020a05600c3b9c00b003ddca7a2bcbso5221268wms.3 for ; Fri, 10 Feb 2023 15:31:36 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id h33-20020a05600c49a100b003dc54eef495sm5925947wmp.24.2023.02.10.15.31.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Feb 2023 15:31:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X5wXhLnzsqClbhoVFkPexTF9c4fLCApBCEoKfoI/Dzk=; b=YUjfS/pyYabGAvOjbFDw3r/1IDx0dKBYvhzubeNLZS2D8/M2tnAgELEEGN9vbeePYV vp5vHz73vVMWt+0/sZyf9I6NVFvIDcHMaCLf2asPuzln8jraaW4iXA5wTZnC4NG3gKU4 ne/f+uNg7nJtpgN30BvOkbMDGEGab1nteqD3HAOC7XkomTETiCOBfZfY8UEEw/XEpfc5 Ac305LdDaGDBiXS2mYrbZ3pnvLiHS5v31mlAAaviDEFkCkiof94QE4+0SNEoveGXfuJi m+i5KOcUDGUXvX8gmDbueTBq3WyH3ov1Gq213WY3EaDw1RiuVJG0WBFx0zk8PpBA75Yu h8Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X5wXhLnzsqClbhoVFkPexTF9c4fLCApBCEoKfoI/Dzk=; b=TYgFpehdaA3dA0Vtsa04hTeJE65kPBbjPtpdtJ8nJ7o9gS5dWm/XDCi+JIVU9pNCn4 E59VjM70p04QV5Q/4jEHZfxwK0gNpSXHrsjBq+/CQ7BG7/0Gnu1H0MVO1CuIFDJ7ja7b tBz0LOIhi3o8NlsTOWich+B3KD/8hI5QCycu4iCMaLCUVNni+A3acsrfbcjEMdR7HW1G 6uqQ3bxLcH5l8y0qahTEG2aCnlvH6a/T/IokB84W2XqCYhS4NNdFOsMZnau3qT0Ysyjd xoGhF8dEIXJxctNovie0X8nHtSbw09hqSLgrp8VLnhxpX0scBOcbLl8TVVIHQQRAjS1+ E1Hg== X-Gm-Message-State: AO0yUKU+g5jCFdJSq2ON/f0DOP37nPZvg6PjMO93yY399+v8v8/qnU4q hOzEhhS7hv4KIuiL5VHAAVg0TfOuMSC4V4oP X-Google-Smtp-Source: AK7set/d8YHwmaXNeBBQgHh6o4BiWnWlQICzzqT4ZxLNzPkBuidAoGrzO7N+MM7b37G70YPbLcXLxQ== X-Received: by 2002:a05:600c:a686:b0:3e0:fad:5fa8 with SMTP id ip6-20020a05600ca68600b003e00fad5fa8mr13941796wmb.33.1676071895449; Fri, 10 Feb 2023 15:31:35 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Richard Henderson , "Michael S. Tsirkin" , Thomas Huth , Eduardo Habkost , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Sergio Lopez , Marcel Apfelbaum Subject: [PATCH 3/3] hw/rtc: Rename rtc_[get|set]_memory -> mc146818rtc_[get|set]_cmos_data Date: Sat, 11 Feb 2023 00:31:16 +0100 Message-Id: <20230210233116.80311-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230210233116.80311-1-philmd@linaro.org> References: <20230210233116.80311-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1676071981421100001 rtc_get_memory() and rtc_set_memory() helpers only work with TYPE_MC146818_RTC devices. 'memory' in their name refer to the CMOS region. Rename them as mc146818rtc_get_cmos_data() and mc146818rtc_set_cmos_data() to be explicit about what they are doing. Mechanical change doing: $ sed -i -e 's/rtc_set_memory/mc146818rtc_set_cmos_data/g' \ $(git grep -wl rtc_set_memory) $ sed -i -e 's/rtc_get_memory/mc146818rtc_get_cmos_data/g' \ $(git grep -wl rtc_get_memory) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/i386/microvm.c | 22 +++++++------- hw/i386/pc.c | 58 ++++++++++++++++++------------------ hw/i386/x86.c | 4 +-- hw/ppc/prep.c | 8 ++--- hw/rtc/mc146818rtc.c | 6 ++-- include/hw/rtc/mc146818rtc.h | 4 +-- 6 files changed, 51 insertions(+), 51 deletions(-) diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index 04b453cde5..2302810117 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -63,8 +63,8 @@ static void microvm_set_rtc(MicrovmMachineState *mms, MC1= 46818RtcState *s) int val; =20 val =3D MIN(x86ms->below_4g_mem_size / KiB, 640); - rtc_set_memory(s, 0x15, val); - rtc_set_memory(s, 0x16, val >> 8); + mc146818rtc_set_cmos_data(s, 0x15, val); + mc146818rtc_set_cmos_data(s, 0x16, val >> 8); /* extended memory (next 64MiB) */ if (x86ms->below_4g_mem_size > 1 * MiB) { val =3D (x86ms->below_4g_mem_size - 1 * MiB) / KiB; @@ -74,10 +74,10 @@ static void microvm_set_rtc(MicrovmMachineState *mms, M= C146818RtcState *s) if (val > 65535) { val =3D 65535; } - rtc_set_memory(s, 0x17, val); - rtc_set_memory(s, 0x18, val >> 8); - rtc_set_memory(s, 0x30, val); - rtc_set_memory(s, 0x31, val >> 8); + mc146818rtc_set_cmos_data(s, 0x17, val); + mc146818rtc_set_cmos_data(s, 0x18, val >> 8); + mc146818rtc_set_cmos_data(s, 0x30, val); + mc146818rtc_set_cmos_data(s, 0x31, val >> 8); /* memory between 16MiB and 4GiB */ if (x86ms->below_4g_mem_size > 16 * MiB) { val =3D (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); @@ -87,13 +87,13 @@ static void microvm_set_rtc(MicrovmMachineState *mms, M= C146818RtcState *s) if (val > 65535) { val =3D 65535; } - rtc_set_memory(s, 0x34, val); - rtc_set_memory(s, 0x35, val >> 8); + mc146818rtc_set_cmos_data(s, 0x34, val); + mc146818rtc_set_cmos_data(s, 0x35, val >> 8); /* memory above 4GiB */ val =3D x86ms->above_4g_mem_size / 65536; - rtc_set_memory(s, 0x5b, val); - rtc_set_memory(s, 0x5c, val >> 8); - rtc_set_memory(s, 0x5d, val >> 16); + mc146818rtc_set_cmos_data(s, 0x5b, val); + mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); + mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); } =20 static void create_gpex(MicrovmMachineState *mms) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 606686dafc..71aaa3875f 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -442,16 +442,16 @@ static uint64_t ioportF0_read(void *opaque, hwaddr ad= dr, unsigned size) static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, int16_t cylinders, int8_t heads, int8_t sectors) { - rtc_set_memory(s, type_ofs, 47); - rtc_set_memory(s, info_ofs, cylinders); - rtc_set_memory(s, info_ofs + 1, cylinders >> 8); - rtc_set_memory(s, info_ofs + 2, heads); - rtc_set_memory(s, info_ofs + 3, 0xff); - rtc_set_memory(s, info_ofs + 4, 0xff); - rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); - rtc_set_memory(s, info_ofs + 6, cylinders); - rtc_set_memory(s, info_ofs + 7, cylinders >> 8); - rtc_set_memory(s, info_ofs + 8, sectors); + mc146818rtc_set_cmos_data(s, type_ofs, 47); + mc146818rtc_set_cmos_data(s, info_ofs, cylinders); + mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); + mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); + mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); + mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); + mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); + mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); + mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); + mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); } =20 /* convert boot_device letter to something recognizable by the bios */ @@ -491,8 +491,8 @@ static void set_boot_dev(MC146818RtcState *s, const cha= r *boot_device, return; } } - rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); - rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); + mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); + mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 := 0x1)); } =20 static void pc_boot_set(void *opaque, const char *boot_device, Error **err= p) @@ -514,9 +514,9 @@ static void pc_cmos_init_floppy(MC146818RtcState *rtc_s= tate, ISADevice *floppy) } val =3D (cmos_get_fd_drive_type(fd_type[0]) << 4) | cmos_get_fd_drive_type(fd_type[1]); - rtc_set_memory(rtc_state, 0x10, val); + mc146818rtc_set_cmos_data(rtc_state, 0x10, val); =20 - val =3D rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); + val =3D mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); nb =3D 0; if (fd_type[0] !=3D FLOPPY_DRIVE_TYPE_NONE) { nb++; @@ -534,7 +534,7 @@ static void pc_cmos_init_floppy(MC146818RtcState *rtc_s= tate, ISADevice *floppy) val |=3D 0x41; /* 2 drives, ready for boot */ break; } - rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); + mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); } =20 typedef struct pc_cmos_init_late_arg { @@ -622,7 +622,7 @@ static void pc_cmos_init_late(void *opaque) cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); val |=3D 0x0f; } - rtc_set_memory(s, 0x12, val); + mc146818rtc_set_cmos_data(s, 0x12, val); =20 val =3D 0; for (i =3D 0; i < 4; i++) { @@ -638,7 +638,7 @@ static void pc_cmos_init_late(void *opaque) val |=3D trans << (i * 2); } } - rtc_set_memory(s, 0x39, val); + mc146818rtc_set_cmos_data(s, 0x39, val); =20 pc_cmos_init_floppy(s, pc_find_fdc0()); =20 @@ -659,8 +659,8 @@ void pc_cmos_init(PCMachineState *pcms, /* memory size */ /* base memory (first MiB) */ val =3D MIN(x86ms->below_4g_mem_size / KiB, 640); - rtc_set_memory(s, 0x15, val); - rtc_set_memory(s, 0x16, val >> 8); + mc146818rtc_set_cmos_data(s, 0x15, val); + mc146818rtc_set_cmos_data(s, 0x16, val >> 8); /* extended memory (next 64MiB) */ if (x86ms->below_4g_mem_size > 1 * MiB) { val =3D (x86ms->below_4g_mem_size - 1 * MiB) / KiB; @@ -669,10 +669,10 @@ void pc_cmos_init(PCMachineState *pcms, } if (val > 65535) val =3D 65535; - rtc_set_memory(s, 0x17, val); - rtc_set_memory(s, 0x18, val >> 8); - rtc_set_memory(s, 0x30, val); - rtc_set_memory(s, 0x31, val >> 8); + mc146818rtc_set_cmos_data(s, 0x17, val); + mc146818rtc_set_cmos_data(s, 0x18, val >> 8); + mc146818rtc_set_cmos_data(s, 0x30, val); + mc146818rtc_set_cmos_data(s, 0x31, val >> 8); /* memory between 16MiB and 4GiB */ if (x86ms->below_4g_mem_size > 16 * MiB) { val =3D (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); @@ -681,13 +681,13 @@ void pc_cmos_init(PCMachineState *pcms, } if (val > 65535) val =3D 65535; - rtc_set_memory(s, 0x34, val); - rtc_set_memory(s, 0x35, val >> 8); + mc146818rtc_set_cmos_data(s, 0x34, val); + mc146818rtc_set_cmos_data(s, 0x35, val >> 8); /* memory above 4GiB */ val =3D x86ms->above_4g_mem_size / 65536; - rtc_set_memory(s, 0x5b, val); - rtc_set_memory(s, 0x5c, val >> 8); - rtc_set_memory(s, 0x5d, val >> 16); + mc146818rtc_set_cmos_data(s, 0x5b, val); + mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); + mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); =20 object_property_add_link(OBJECT(pcms), "rtc_state", TYPE_ISA_DEVICE, @@ -702,7 +702,7 @@ void pc_cmos_init(PCMachineState *pcms, val =3D 0; val |=3D 0x02; /* FPU is there */ val |=3D 0x04; /* PS/2 mouse installed */ - rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); + mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); =20 /* hard drives and FDC */ arg.rtc_state =3D s; diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 5dbdd75bfc..05b16fb349 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -161,9 +161,9 @@ void x86_rtc_set_cpus_count(ISADevice *s, uint16_t cpus= _count) * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just * to make old BIOSes fail more predictably. */ - rtc_set_memory(rtc, 0x5f, 0); + mc146818rtc_set_cmos_data(rtc, 0x5f, 0); } else { - rtc_set_memory(rtc, 0x5f, cpus_count - 1); + mc146818rtc_set_cmos_data(rtc, 0x5f, cpus_count - 1); } } =20 diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index 076e2d0d22..d00280c0f8 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -215,10 +215,10 @@ static int prep_set_cmos_checksum(DeviceState *dev, v= oid *opaque) =20 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { MC146818RtcState *rtc =3D MC146818_RTC(dev); - rtc_set_memory(rtc, 0x2e, checksum & 0xff); - rtc_set_memory(rtc, 0x3e, checksum & 0xff); - rtc_set_memory(rtc, 0x2f, checksum >> 8); - rtc_set_memory(rtc, 0x3f, checksum >> 8); + mc146818rtc_set_cmos_data(rtc, 0x2e, checksum & 0xff); + mc146818rtc_set_cmos_data(rtc, 0x3e, checksum & 0xff); + mc146818rtc_set_cmos_data(rtc, 0x2f, checksum >> 8); + mc146818rtc_set_cmos_data(rtc, 0x3f, checksum >> 8); =20 object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(r= tc), "date"); diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c index 478eee97e4..7b09c3144f 100644 --- a/hw/rtc/mc146818rtc.c +++ b/hw/rtc/mc146818rtc.c @@ -739,13 +739,13 @@ static uint64_t cmos_ioport_read(void *opaque, hwaddr= addr, } } =20 -void rtc_set_memory(MC146818RtcState *s, int addr, int val) +void mc146818rtc_set_cmos_data(MC146818RtcState *s, int addr, int val) { if (addr >=3D 0 && addr <=3D 127) s->cmos_data[addr] =3D val; } =20 -int rtc_get_memory(MC146818RtcState *s, int addr) +int mc146818rtc_get_cmos_data(MC146818RtcState *s, int addr) { assert(addr >=3D 0 && addr <=3D 127); return s->cmos_data[addr]; @@ -856,7 +856,7 @@ static const VMStateDescription vmstate_rtc =3D { static void rtc_notify_suspend(Notifier *notifier, void *data) { MC146818RtcState *s =3D container_of(notifier, MC146818RtcState, suspe= nd_notifier); - rtc_set_memory(s, 0xF, 0xFE); + mc146818rtc_set_cmos_data(s, 0xF, 0xFE); } =20 static const MemoryRegionOps cmos_ops =3D { diff --git a/include/hw/rtc/mc146818rtc.h b/include/hw/rtc/mc146818rtc.h index a6b0c135c0..97cec0b3e8 100644 --- a/include/hw/rtc/mc146818rtc.h +++ b/include/hw/rtc/mc146818rtc.h @@ -53,8 +53,8 @@ struct MC146818RtcState { =20 MC146818RtcState *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq); -void rtc_set_memory(MC146818RtcState *s, int addr, int val); -int rtc_get_memory(MC146818RtcState *s, int addr); +void mc146818rtc_set_cmos_data(MC146818RtcState *s, int addr, int val); +int mc146818rtc_get_cmos_data(MC146818RtcState *s, int addr); void qmp_rtc_reset_reinjection(Error **errp); =20 #endif /* HW_RTC_MC146818RTC_H */ --=20 2.38.1