From nobody Fri May 17 03:13:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1675726567; cv=none; d=zohomail.com; s=zohoarc; b=T6Cy3ELATOn9BqpjG/f/Q5x9SF2Q6ohMUtmwGDkh7TQbQwY2HaS0graUz1J0ogzQhrjThLpNWHMdu6n1NKCr81M1A1da1u+4XhPKetKIrvXp6aybZRBtG5eUp4fHxCKILBCnCnnEuBBgnFEb8egWSBv48Ax0fmVFJqBAoEy+s2Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675726567; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vFsWxZhA6QPnt4GsI20du9iPkTYQvxuV4k70tA62ahM=; b=RkUYwYt1wPggxUq2ZesaN2NUsmqOj6RwEzRHdkg4AVlhp5athHHqLIrffgV7op1UjK5Iku+eAKGD0sZU8Zu4sQ8uVvFLUNYiBjHZJlZX1o/xvNlDrkueLFE3/24pEC2wRlyLbl6zSxxeP7Byz7/eG+T6KGANqFfnmMweULg/4Ao= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675726567275891.3076740967649; Mon, 6 Feb 2023 15:36:07 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pPB1E-0000mY-NH; Mon, 06 Feb 2023 18:35:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3jY7hYwgKClYKI5yCHG54CC492.0CAE2AI-12J29BCB4BI.CF4@flex--wuhaotsh.bounces.google.com>) id 1pPB0a-0000Kq-IR for qemu-devel@nongnu.org; Mon, 06 Feb 2023 18:34:55 -0500 Received: from mail-pg1-x549.google.com ([2607:f8b0:4864:20::549]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3jY7hYwgKClYKI5yCHG54CC492.0CAE2AI-12J29BCB4BI.CF4@flex--wuhaotsh.bounces.google.com>) id 1pPB0U-0006ER-Iv for qemu-devel@nongnu.org; Mon, 06 Feb 2023 18:34:48 -0500 Received: by mail-pg1-x549.google.com with SMTP id p27-20020a631e5b000000b004f3880f6673so4097068pgm.14 for ; Mon, 06 Feb 2023 15:34:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=vFsWxZhA6QPnt4GsI20du9iPkTYQvxuV4k70tA62ahM=; b=RFI05uy+DHANnC3nOXUHf2gufeA55tqe3i9o8XkotRXFMPZrERW/Xcrrb+UKqObrFk UeGdH9pPEWGMxE8w2AjuzoxA3brVewFpPAXraj1UPDUvjQifyf4VbtQ5uJj3KLohCq5T IKk8YBp4fSXlBI4eGTw0eemN04078SOaIAtmypdiPhX9+sxlKc8KhPICS5teheCBC7aL /IHC5EuptooSdaoRJVsvL9LlhKzKiWE5FGXPpVsgwbeX+uEA++SxE+IUZL8gOF6RsCVT xynr4Ix8DwDi78b5OH2APw/0gq5DQ3/KRxSVzLgxUD207mkIit30eBdFEe9QPqMZmaNV knhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=vFsWxZhA6QPnt4GsI20du9iPkTYQvxuV4k70tA62ahM=; b=JrQx7bHVA9kxXdUO0hjO5g0tDJxiqHPFmecJXQfTvKila4Zg4jfVPEb1PafivKYpGZ WVhQJspl2SKkm1e4Kxhw+zW+vkGOHRkIeUMYeWHFbyOdcLhl9JXbLPwV3HZGSKtyYjtC NxCrEHRfgh2bWLAFRlsJ+yogQ/MO1jh1aIThFeG4F7hCMObU+NV3XKAKCPIvUR18Xs3f AUc8pTTOMPA3YiDRpo36nChd+dhA7Tg0f5DihGcxH/rI37bp86Db0JGCEekqyBGPSkDm 4XXOyLeIh/WN35KUx5AK5UifkMxT9bc1xmc7q4/3lIPESBsBJVENmGk6GidZLM9gXlyK vI/A== X-Gm-Message-State: AO0yUKXDNjpraXLKM27eui4QvfC8pGR1NIHyQYJOaE0HH2iRIRxcrzaR L4H+3yAbC3s4c+L60EhiEIJWyN3m1tkPkQ== X-Google-Smtp-Source: AK7set/n51hrglSFjEw9m5xPUHjt9U3J/KSzhiLvPRnOUSUD3U3wq+IfDAOaYIjElze5rrms/lMOW+ku9cqdbw== X-Received: from mimik.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:4e]) (user=wuhaotsh job=sendgmr) by 2002:a62:2784:0:b0:58e:2111:9c42 with SMTP id n126-20020a622784000000b0058e21119c42mr282874pfn.22.1675726477964; Mon, 06 Feb 2023 15:34:37 -0800 (PST) Date: Mon, 6 Feb 2023 15:34:26 -0800 In-Reply-To: <20230206233428.2772669-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20230206233428.2772669-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.39.1.519.gcb327c4b5f-goog Message-ID: <20230206233428.2772669-2-wuhaotsh@google.com> Subject: [PATCH 1/3] MAINTAINERS: Add myself to maintainers and remove Havard From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, wuhaotsh@google.com, venture@google.com, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, hskinnemoen@google.com, titusr@google.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::549; envelope-from=3jY7hYwgKClYKI5yCHG54CC492.0CAE2AI-12J29BCB4BI.CF4@flex--wuhaotsh.bounces.google.com; helo=mail-pg1-x549.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1675726567473100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Havard is no longer working on the Nuvoton systems for a while and won't be able to do any work on it in the future. So I'll take over maintaining the Nuvoton system from him. Signed-off-by: Hao Wu Acked-by: Havard Skinnemoen Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index fa10ecaeb9..347936e41c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -799,8 +799,8 @@ F: include/hw/net/mv88w8618_eth.h F: docs/system/arm/musicpal.rst =20 Nuvoton NPCM7xx -M: Havard Skinnemoen M: Tyrone Ting +M: Hao Wu L: qemu-arm@nongnu.org S: Supported F: hw/*/npcm7xx* --=20 2.39.1.519.gcb327c4b5f-goog From nobody Fri May 17 03:13:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1675726588; cv=none; d=zohomail.com; s=zohoarc; b=BWaET7hqAqzwZ/ChvGk+aeFgLgATVk/VQtxsGQuM3I78Dp3UDLC+1SRcFv8ibL7WWWiEOGpqPFXqX9+0XV+bThBKWQqGjBG3bQOcZR1BoXtLWigVePmKi3JoknzCyCsHe6Eac8meVCXgzbVgQPYs5AfBzVEMwn6liY15f+c806k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675726588; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=e/piuFO7fKbYCx5pmj7hkpJxVFL+4/FWYiX0T7OuXxs=; b=iAEGS5I+28RHAdpuGUzzYoHnT1k25M1+u50y1EKriJ4JtBDtT0PWC0LtbS0UzRm/N0xdgOmGmTcdxrUfRoOQKPrCJblczZSD685HCWS7EeVImS1a6+XeXjtReT34TRZ+PpunjfUxJ4RYFGdZwzQkrsq4ArXD5AskMU8t1lXl7UI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675726588759302.7669658884006; Mon, 6 Feb 2023 15:36:28 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pPB18-0000h4-DQ; Mon, 06 Feb 2023 18:35:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3j47hYwgKClgMK70EJI76EE6B4.2ECG4CK-34L4BDED6DK.EH6@flex--wuhaotsh.bounces.google.com>) id 1pPB0e-0000N5-CJ for qemu-devel@nongnu.org; Mon, 06 Feb 2023 18:34:57 -0500 Received: from mail-pf1-x449.google.com ([2607:f8b0:4864:20::449]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3j47hYwgKClgMK70EJI76EE6B4.2ECG4CK-34L4BDED6DK.EH6@flex--wuhaotsh.bounces.google.com>) id 1pPB0U-0006F7-1G for qemu-devel@nongnu.org; Mon, 06 Feb 2023 18:34:50 -0500 Received: by mail-pf1-x449.google.com with SMTP id k14-20020aa7972e000000b00593a8232ac3so7226307pfg.22 for ; Mon, 06 Feb 2023 15:34:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=e/piuFO7fKbYCx5pmj7hkpJxVFL+4/FWYiX0T7OuXxs=; b=IDNikXGq4ugSZZq4DsSzesM5eg6V5+M9s0xp6evQspzkbz1q4fwNH6yZCGjAwiXwPl eWE4gCQ5UMJ/w2Hkmce7UVhJFh3K9oRnQ3+Mn0fjEMGIdD9xyjQQf2NkosiUmx92qYr6 hQBkSDbQ3cL6kCceWLoZ5lsgbJZvRVvCpvOvzluifVy8Fs63Pjij690m3e4agiNHlytS 6ZSGRT3hhaP5DKus1+0zEL7l9aomOeJmNttbBBNJZqNprJN8qVjLZb6btajjire/2oW2 5Qb1Wmt19bCXGCSzbVArZ6fg+bUJmcPPhVJDMO+mAqqNgL2iA7I/GuSHDXPEHEI7hQf8 XAmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=e/piuFO7fKbYCx5pmj7hkpJxVFL+4/FWYiX0T7OuXxs=; b=xyom4dDgYf6RjrUWKWoZgrobsS61PQENVtyCSW19ikg0KNVdFeijIq1afyTmSUrolo 8jXTVegCZzkzqVPyl70XupfsPwDK7pvvAaph04G6LTEew6FA0BeJgIbdFnOceMV8YDqk xL3FV8Ehnim6ccP6+mewen/INkiOLhHtkE6GaxpBTenK6GNR5QGr1kqL+BnsWuXtYrpI IjgJhhaHA/dC1pT4GKRSqL9lAt2nLWe0GFue9RJPzetiEdD4JlpHiadoVjXNxlc+sT/I POZugrPMLRoP/hJc8RLE/iFyH2uETW12ehOBlu/bkoMtsQ+5eiPt7OM8IBZR9XmZPf6s NTVA== X-Gm-Message-State: AO0yUKV42MxIGZO/8SCyBi8SihLI4OdF23ebj9VF7pGeZMbZEIzNqO/W WMAkVrkn5ILmKGa7jx6+JUCxXrzLYviZjQ== X-Google-Smtp-Source: AK7set8HPxyMdHDAAJHYoO0N2eBZvWMtwdtybdMiTZ/9itBROhxjNcl7ysqaYxTOc922rQWCSsTvDnLR9r+fFQ== X-Received: from mimik.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:4e]) (user=wuhaotsh job=sendgmr) by 2002:a17:90a:1617:b0:22c:5a14:7e9c with SMTP id n23-20020a17090a161700b0022c5a147e9cmr317676pja.48.1675726479608; Mon, 06 Feb 2023 15:34:39 -0800 (PST) Date: Mon, 6 Feb 2023 15:34:27 -0800 In-Reply-To: <20230206233428.2772669-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20230206233428.2772669-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.39.1.519.gcb327c4b5f-goog Message-ID: <20230206233428.2772669-3-wuhaotsh@google.com> Subject: [PATCH 2/3] hw/ssi: Add Nuvoton PSPI Module From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, wuhaotsh@google.com, venture@google.com, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, hskinnemoen@google.com, titusr@google.com, Chris Rauer Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::449; envelope-from=3j47hYwgKClgMK70EJI76EE6B4.2ECG4CK-34L4BDED6DK.EH6@flex--wuhaotsh.bounces.google.com; helo=mail-pf1-x449.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1675726589610100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Nuvoton's PSPI is a general purpose SPI module which enables connections to SPI-based peripheral devices. Signed-off-by: Hao Wu Reviewed-by: Chris Rauer Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 6 +- hw/ssi/meson.build | 2 +- hw/ssi/npcm_pspi.c | 216 +++++++++++++++++++++++++++++++++++++ hw/ssi/trace-events | 5 + include/hw/ssi/npcm_pspi.h | 53 +++++++++ 5 files changed, 278 insertions(+), 4 deletions(-) create mode 100644 hw/ssi/npcm_pspi.c create mode 100644 include/hw/ssi/npcm_pspi.h diff --git a/MAINTAINERS b/MAINTAINERS index 347936e41c..1e2a711373 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -803,9 +803,9 @@ M: Tyrone Ting M: Hao Wu L: qemu-arm@nongnu.org S: Supported -F: hw/*/npcm7xx* -F: include/hw/*/npcm7xx* -F: tests/qtest/npcm7xx* +F: hw/*/npcm* +F: include/hw/*/npcm* +F: tests/qtest/npcm* F: pc-bios/npcm7xx_bootrom.bin F: roms/vbootrom F: docs/system/arm/nuvoton.rst diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build index 702aa5e4df..904a47161a 100644 --- a/hw/ssi/meson.build +++ b/hw/ssi/meson.build @@ -1,6 +1,6 @@ softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c')) softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c')) -softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c')) +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c', 'np= cm_pspi.c')) softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_SPI', if_true: files('sifive_spi.c')) softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c')) diff --git a/hw/ssi/npcm_pspi.c b/hw/ssi/npcm_pspi.c new file mode 100644 index 0000000000..565bba5282 --- /dev/null +++ b/hw/ssi/npcm_pspi.c @@ -0,0 +1,216 @@ +/* + * Nuvoton NPCM Peripheral SPI Module (PSPI) + * + * Copyright 2023 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" + +#include "hw/irq.h" +#include "hw/registerfields.h" +#include "hw/ssi/npcm_pspi.h" +#include "migration/vmstate.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/units.h" + +#include "trace.h" + +REG16(PSPI_DATA, 0x0) +REG16(PSPI_CTL1, 0x2) + FIELD(PSPI_CTL1, SPIEN, 0, 1) + FIELD(PSPI_CTL1, MOD, 2, 1) + FIELD(PSPI_CTL1, EIR, 5, 1) + FIELD(PSPI_CTL1, EIW, 6, 1) + FIELD(PSPI_CTL1, SCM, 7, 1) + FIELD(PSPI_CTL1, SCIDL, 8, 1) + FIELD(PSPI_CTL1, SCDV, 9, 7) +REG16(PSPI_STAT, 0x4) + FIELD(PSPI_STAT, BSY, 0, 1) + FIELD(PSPI_STAT, RBF, 1, 1) + +static void npcm_pspi_update_irq(NPCMPSPIState *s) +{ + int level =3D 0; + + /* Only fire IRQ when the module is enabled. */ + if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, SPIEN)) { + /* Update interrupt as BSY is cleared. */ + if ((!FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, BSY)) && + FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIW)) { + level =3D 1; + } + + /* Update interrupt as RBF is set. */ + if (FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, RBF) && + FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIR)) { + level =3D 1; + } + } + qemu_set_irq(s->irq, level); +} + +static uint16_t npcm_pspi_read_data(NPCMPSPIState *s) +{ + uint16_t value =3D s->regs[R_PSPI_DATA]; + + /* Clear stat bits as the value are read out. */ + s->regs[R_PSPI_STAT] =3D 0; + + return value; +} + +static void npcm_pspi_write_data(NPCMPSPIState *s, uint16_t data) +{ + uint16_t value =3D 0; + + if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, MOD)) { + value =3D ssi_transfer(s->spi, extract16(data, 8, 8)) << 8; + } + value |=3D ssi_transfer(s->spi, extract16(data, 0, 8)); + s->regs[R_PSPI_DATA] =3D value; + + /* Mark data as available */ + s->regs[R_PSPI_STAT] =3D R_PSPI_STAT_BSY_MASK | R_PSPI_STAT_RBF_MASK; +} + +/* Control register read handler. */ +static uint64_t npcm_pspi_ctrl_read(void *opaque, hwaddr addr, + unsigned int size) +{ + NPCMPSPIState *s =3D opaque; + uint16_t value; + + switch (addr) { + case A_PSPI_DATA: + value =3D npcm_pspi_read_data(s); + break; + + case A_PSPI_CTL1: + value =3D s->regs[R_PSPI_CTL1]; + break; + + case A_PSPI_STAT: + value =3D s->regs[R_PSPI_STAT]; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to invalid offset 0x%" PRIx64 "\n", + DEVICE(s)->canonical_path, addr); + return 0; + } + trace_npcm_pspi_ctrl_read(DEVICE(s)->canonical_path, addr, value); + npcm_pspi_update_irq(s); + + return value; +} + +/* Control register write handler. */ +static void npcm_pspi_ctrl_write(void *opaque, hwaddr addr, uint64_t v, + unsigned int size) +{ + NPCMPSPIState *s =3D opaque; + uint16_t value =3D v; + + trace_npcm_pspi_ctrl_write(DEVICE(s)->canonical_path, addr, value); + + switch (addr) { + case A_PSPI_DATA: + npcm_pspi_write_data(s, value); + break; + + case A_PSPI_CTL1: + s->regs[R_PSPI_CTL1] =3D value; + break; + + case A_PSPI_STAT: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to read-only register PSPI_STAT: 0x%08" + PRIx64 "\n", DEVICE(s)->canonical_path, v); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to invalid offset 0x%" PRIx64 "\n", + DEVICE(s)->canonical_path, addr); + return; + } + npcm_pspi_update_irq(s); +} + +static const MemoryRegionOps npcm_pspi_ctrl_ops =3D { + .read =3D npcm_pspi_ctrl_read, + .write =3D npcm_pspi_ctrl_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 2, + .unaligned =3D false, + }, +}; + +static void npcm_pspi_enter_reset(Object *obj, ResetType type) +{ + NPCMPSPIState *s =3D NPCM_PSPI(obj); + + trace_npcm_pspi_enter_reset(DEVICE(obj)->canonical_path, type); + memset(s->regs, 0, sizeof(s->regs)); +} + +static void npcm_pspi_realize(DeviceState *dev, Error **errp) +{ + NPCMPSPIState *s =3D NPCM_PSPI(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + Object *obj =3D OBJECT(dev); + + s->spi =3D ssi_create_bus(dev, "pspi"); + memory_region_init_io(&s->mmio, obj, &npcm_pspi_ctrl_ops, s, + "mmio", 4 * KiB); + sysbus_init_mmio(sbd, &s->mmio); + sysbus_init_irq(sbd, &s->irq); +} + +static const VMStateDescription vmstate_npcm_pspi =3D { + .name =3D "npcm-pspi", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT16_ARRAY(regs, NPCMPSPIState, NPCM_PSPI_NR_REGS), + VMSTATE_END_OF_LIST(), + }, +}; + + +static void npcm_pspi_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "NPCM Peripheral SPI Module"; + dc->realize =3D npcm_pspi_realize; + dc->vmsd =3D &vmstate_npcm_pspi; + rc->phases.enter =3D npcm_pspi_enter_reset; +} + +static const TypeInfo npcm_pspi_types[] =3D { + { + .name =3D TYPE_NPCM_PSPI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NPCMPSPIState), + .class_init =3D npcm_pspi_class_init, + }, +}; +DEFINE_TYPES(npcm_pspi_types); diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events index c707d4aaba..16ea9954c4 100644 --- a/hw/ssi/trace-events +++ b/hw/ssi/trace-events @@ -21,6 +21,11 @@ npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, ui= nt32_t data) "%s offset: npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int= size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%"= PRIx64 npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsign= ed int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value= : 0x%" PRIx64 =20 +# npcm_pspi.c +npcm_pspi_enter_reset(const char *id, int reset_type) "%s reset type: %d" +npcm_pspi_ctrl_read(const char *id, uint64_t addr, uint16_t data) "%s offs= et: 0x%04" PRIx64 " value: 0x%08" PRIx16 +npcm_pspi_ctrl_write(const char *id, uint64_t addr, uint16_t data) "%s off= set: 0x%04" PRIx64 " value: 0x%08" PRIx16 + # ibex_spi_host.c =20 ibex_spi_host_reset(const char *msg) "%s" diff --git a/include/hw/ssi/npcm_pspi.h b/include/hw/ssi/npcm_pspi.h new file mode 100644 index 0000000000..37cc784d96 --- /dev/null +++ b/include/hw/ssi/npcm_pspi.h @@ -0,0 +1,53 @@ +/* + * Nuvoton Peripheral SPI Module + * + * Copyright 2023 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ +#ifndef NPCM_PSPI_H +#define NPCM_PSPI_H + +#include "hw/ssi/ssi.h" +#include "hw/sysbus.h" + +/* + * Number of registers in our device state structure. Don't change this wi= thout + * incrementing the version_id in the vmstate. + */ +#define NPCM_PSPI_NR_REGS 3 + +/** + * NPCMPSPIState - Device state for one Flash Interface Unit. + * @parent: System bus device. + * @mmio: Memory region for register access. + * @spi: The SPI bus mastered by this controller. + * @regs: Register contents. + * @irq: The interrupt request queue for this module. + * + * Each PSPI has a shared bank of registers, and controls up to four chip + * selects. Each chip select has a dedicated memory region which may be us= ed to + * read and write the flash connected to that chip select as if it were me= mory. + */ +typedef struct NPCMPSPIState { + SysBusDevice parent; + + MemoryRegion mmio; + + SSIBus *spi; + uint16_t regs[NPCM_PSPI_NR_REGS]; + qemu_irq irq; +} NPCMPSPIState; + +#define TYPE_NPCM_PSPI "npcm-pspi" +OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI) + +#endif /* NPCM_PSPI_H */ --=20 2.39.1.519.gcb327c4b5f-goog From nobody Fri May 17 03:13:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1675726540; cv=none; d=zohomail.com; s=zohoarc; b=ehIErXwhX/aqmD9MCGJqevlE+HNfGCxfYcHj3dcq629FFbcX+Yaufis9ZhujcBia2GjX+EL97QSYDhGYVQA4ILlwHBf3oVY1rMZuF4t1UMwtx+7ZwmyolmpekH+4lgjZ2/ErReYv4SA4dWJA9XXkX3wgl10Blp+Qjon2UGZDQMs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675726540; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0BCzLce21K9mc/aCDcKh55LLs04zCBy5vm60f0Sem2M=; b=jlrxsDQAu4W6f6Jv2zyR+HoFJe9g38XrR2z70hi2sunrZRQRdtarLBy5Q84TsNwjzqFQo9p11nDpoN/D5Ex/FFzubl4yn+m+mX2cTJ4MREWFdW9A+nGNhxXcnY/RhxsZTPE+PknBNhKrZejpb8jgqNolLeGps/Jr/bZGE9x42oU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167572654062045.11192335457815; Mon, 6 Feb 2023 15:35:40 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pPB17-0000g7-Bz; Mon, 06 Feb 2023 18:35:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3kI7hYwgKClkNL81FKJ87FF7C5.3FDH5DL-45M5CEFE7EL.FI7@flex--wuhaotsh.bounces.google.com>) id 1pPB0e-0000N4-Cl for qemu-devel@nongnu.org; Mon, 06 Feb 2023 18:34:56 -0500 Received: from mail-pl1-x649.google.com ([2607:f8b0:4864:20::649]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3kI7hYwgKClkNL81FKJ87FF7C5.3FDH5DL-45M5CEFE7EL.FI7@flex--wuhaotsh.bounces.google.com>) id 1pPB0W-0006GW-1j for qemu-devel@nongnu.org; Mon, 06 Feb 2023 18:34:48 -0500 Received: by mail-pl1-x649.google.com with SMTP id jw1-20020a170903278100b00199292fdbe0so751663plb.7 for ; Mon, 06 Feb 2023 15:34:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=0BCzLce21K9mc/aCDcKh55LLs04zCBy5vm60f0Sem2M=; b=GsaAIoPaKSyacHvS26ZOoTfoyaNd6Yp0pZCi3w1r2iw9l//90TH4AE9wg9cgvO8Ee2 DM7U6dhcBFRk/N3j2RS/IzTlum038AngQus70/TkVHr+FwqnUbroWBdMYYTLkYMsqgQB 1cYyXCTks+d+4PWgWwZE0HaDH2ZZcD55X+fye6CDPfp2jsTazu8gdQznorcLimGdR09Y 0VkYBt7j7lXuN2vzAN2Ho6sACxa0MnmuwCi3MEN/WLrsfG8w88VcHuYpqksdxHPlfJiN 71K61gawLpZE5QMSlJ11JxyVEmMjUDoMV8hdKI6XR00VvQwvIFLFZFCsuB4MVy9eL2nm Q+qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=0BCzLce21K9mc/aCDcKh55LLs04zCBy5vm60f0Sem2M=; b=NCb+YFJ9cdMJhq/AJCdNiyxxV70RRXVJNRDUc29iMdZ20CO6YTmz8yNB5rK91fXecU XRB0nf028FQMsJ5aFV6rkMnEYK/p/RYWZZDNsSFSKPJ240fiByEyjlJ4zUloctJoc5Lx 0V1f61BbHxFgEBHCm9bRppxIPgyv8BKG5Wy5tvbz64nQVnvCheVSqnf/8xcVyx4Titdu ebzw6PMUghl8dUgp6lS5u9vQTXKgj9O7mosP1Grzcld9eUUzk1WUMiJxFohZH+5TeynS z6mrnzKYOmAw8syrg+NpSmFwhianWlvWtyRB11s77oZCJJBQl+WiHkMU8/nbppWfxSON umxQ== X-Gm-Message-State: AO0yUKWOtY2hIFy1tcvcC9QuSuT5XvUkiw9bvr6MSvE31FNVK6vHB8LJ uNx09Na14kNRyrI6uAl8aL2doUtQ1SuGOg== X-Google-Smtp-Source: AK7set8UymnC6JWq5b0DlpWdN7K0pZqxgCIJ7TKwSevAHqg8XYrQSnJUzm7fbFtGie88w9StJHMHMm3QHh87nw== X-Received: from mimik.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:4e]) (user=wuhaotsh job=sendgmr) by 2002:a17:903:32ce:b0:198:b624:f4c2 with SMTP id i14-20020a17090332ce00b00198b624f4c2mr177167plr.6.1675726480884; Mon, 06 Feb 2023 15:34:40 -0800 (PST) Date: Mon, 6 Feb 2023 15:34:28 -0800 In-Reply-To: <20230206233428.2772669-1-wuhaotsh@google.com> Mime-Version: 1.0 References: <20230206233428.2772669-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.39.1.519.gcb327c4b5f-goog Message-ID: <20230206233428.2772669-4-wuhaotsh@google.com> Subject: [PATCH 3/3] hw/arm: Attach PSPI module to NPCM7XX SoC From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, wuhaotsh@google.com, venture@google.com, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, hskinnemoen@google.com, titusr@google.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::649; envelope-from=3kI7hYwgKClkNL81FKJ87FF7C5.3FDH5DL-45M5CEFE7EL.FI7@flex--wuhaotsh.bounces.google.com; helo=mail-pl1-x649.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1675726541497100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Signed-off-by: Hao Wu Reviewed-by: Titus Rwantare Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- docs/system/arm/nuvoton.rst | 2 +- hw/arm/npcm7xx.c | 25 +++++++++++++++++++++++-- include/hw/arm/npcm7xx.h | 2 ++ 3 files changed, 26 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst index c38df32bde..0424cae4b0 100644 --- a/docs/system/arm/nuvoton.rst +++ b/docs/system/arm/nuvoton.rst @@ -49,6 +49,7 @@ Supported devices * SMBus controller (SMBF) * Ethernet controller (EMC) * Tachometer + * Peripheral SPI controller (PSPI) =20 Missing devices --------------- @@ -64,7 +65,6 @@ Missing devices =20 * Ethernet controller (GMAC) * USB device (USBD) - * Peripheral SPI controller (PSPI) * SD/MMC host * PECI interface * PCI and PCIe root complex and bridges diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index d85cc02765..15ff21d047 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -86,6 +86,8 @@ enum NPCM7xxInterrupt { NPCM7XX_EMC1RX_IRQ =3D 15, NPCM7XX_EMC1TX_IRQ, NPCM7XX_MMC_IRQ =3D 26, + NPCM7XX_PSPI2_IRQ =3D 28, + NPCM7XX_PSPI1_IRQ =3D 31, NPCM7XX_TIMER0_IRQ =3D 32, /* Timer Module 0 */ NPCM7XX_TIMER1_IRQ, NPCM7XX_TIMER2_IRQ, @@ -220,6 +222,12 @@ static const hwaddr npcm7xx_emc_addr[] =3D { 0xf0826000, }; =20 +/* Register base address for each PSPI Module */ +static const hwaddr npcm7xx_pspi_addr[] =3D { + 0xf0200000, + 0xf0201000, +}; + static const struct { hwaddr regs_addr; uint32_t unconnected_pins; @@ -444,6 +452,10 @@ static void npcm7xx_init(Object *obj) object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EM= C); } =20 + for (i =3D 0; i < ARRAY_SIZE(s->pspi); i++) { + object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSP= I); + } + object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); } =20 @@ -715,6 +727,17 @@ static void npcm7xx_realize(DeviceState *dev, Error **= errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0, npcm7xx_irq(s, NPCM7XX_MMC_IRQ)); =20 + /* PSPI */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) !=3D ARRAY_SIZE(s->psp= i)); + for (i =3D 0; i < ARRAY_SIZE(s->pspi); i++) { + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->pspi[i]); + int irq =3D (i =3D=3D 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ; + + sysbus_realize(sbd, &error_abort); + sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]); + sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq)); + } + create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * = KiB); create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * = KiB); create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * = KiB); @@ -724,8 +747,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **e= rrp) create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * = KiB); create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * = KiB); create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * = KiB); - create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * = KiB); - create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * = KiB); create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * = MiB); create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * = KiB); create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * = KiB); diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index f1b7e4a48d..72c7722096 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -32,6 +32,7 @@ #include "hw/nvram/npcm7xx_otp.h" #include "hw/timer/npcm7xx_timer.h" #include "hw/ssi/npcm7xx_fiu.h" +#include "hw/ssi/npcm_pspi.h" #include "hw/usb/hcd-ehci.h" #include "hw/usb/hcd-ohci.h" #include "target/arm/cpu.h" @@ -104,6 +105,7 @@ struct NPCM7xxState { NPCM7xxFIUState fiu[2]; NPCM7xxEMCState emc[2]; NPCM7xxSDHCIState mmc; + NPCMPSPIState pspi[2]; }; =20 #define TYPE_NPCM7XX "npcm7xx" --=20 2.39.1.519.gcb327c4b5f-goog