From nobody Fri May 17 05:00:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1675692125; cv=none; d=zohomail.com; s=zohoarc; b=M1vwY0gRL7P2525jP6GvOloqlcOWfHq3+9Tts9vHMr9eNmbUhU7ik8HDF2sfdujrm/FngNfb57vPU3cvbZjWxG/JyATceczGwkBHbYEr3brfVtnA/16GBDrHWyZfmqnx3o9zW35YlBRZoSE4ZjvUoYDlADTb7GynFvR1D8np6So= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1675692125; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YYfgTmuHqj4FSbQ6gJJL7ipbwcWk9NAr+xPSjb70rYE=; b=cXZKtU6iQpNXQ/21Z7bWMhLNmCfnovQFpdln2utnLRcu9haICozLznZrR0L8FinFWLsbLXCf9K0p+SwM7ax8X/MqKSPA/w1Pqq6L3F8SgG8inkTJfdEG0mAhCBxW6BB3jTcd0fXqnvmUdRZ7s9aQznHusfl40nliK7WI7cAWyYw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1675692125359534.2138740716421; Mon, 6 Feb 2023 06:02:05 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pP22u-0007nB-96; Mon, 06 Feb 2023 09:00:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pP22s-0007lC-Ex for qemu-devel@nongnu.org; Mon, 06 Feb 2023 09:00:34 -0500 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pP22p-0000ds-MQ for qemu-devel@nongnu.org; Mon, 06 Feb 2023 09:00:34 -0500 Received: by mail-oi1-x243.google.com with SMTP id bj22so9753043oib.11 for ; Mon, 06 Feb 2023 06:00:30 -0800 (PST) Received: from grind.. ([191.19.125.138]) by smtp.gmail.com with ESMTPSA id s13-20020a0568080b0d00b00364e8f85c08sm4151177oij.21.2023.02.06.06.00.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 06:00:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YYfgTmuHqj4FSbQ6gJJL7ipbwcWk9NAr+xPSjb70rYE=; b=EMk1baUqEe5Aj04m7KC3v/vzRTUTrzIGZFtFfOSD9sMbv8Cut8iwrkngzD3TpQit7Y YJUMtaiFMVEpZI/XgEhm1tggWdILiuH7Pb+DflOQD+ZgNuOmq8V0wMAxTgIRl/jjPCHd rCLFC6TH40DnrMbEi3LFkcd3eQUQmsQmHaEzXNqEvKFVrr0Woulx7nn/zgaVHd9dXnd+ baSgJx5aEd8vvZxUw1Vk5L+Rlv6X8AhQ+6gdNOHwIoisRA0q53wzYyOYCcwzVY7RE4OY i395HLqQbnpJpzlJboIWb+snahz6HViZPrqS9Uu5h9m5MjMNd+vhvIp2a4LvJALrNMzP Iv9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YYfgTmuHqj4FSbQ6gJJL7ipbwcWk9NAr+xPSjb70rYE=; b=3WKs6fAja7gfkoEdfYcg+Qs0pLygYk0OMeVqN9ArI8QGNkEBIXKADdcAdThq5b68mn fFCFIS6hdJRpZrMQd512DUvSNzPCV6zgOzcs09IzS8oBo2U5Jb9SXrIeJ4SFP6HWY3/L 6NYlJg8KZ+03C6Q/908KKrlqkRgPBuFeuF6pHSo77YMe0AV0hWzV2EjPO5dTgmU6FuUw pc+eBp6tGilxJZb8GxRl1rrFVdD8S6y5LM/bZzdc7nXaMEgJFYXU+sZWh8AzYDwgtxdn /zacMpJJRsebvBjjYzKeEvEVgINmyhDDCA1DH8n/fLs2bZYyK9bWsjzZFRvmMp1ZTURL yUfg== X-Gm-Message-State: AO0yUKXCD6odX+ANqYoJxJ1rgV46X28/uuP9vndYCZ8ZA/Wx+gYJB2dm 3OZnb2cJ+5g/rI5vid+0ExlWKp+BO3kLDsmWqAc= X-Google-Smtp-Source: AK7set+myyAqFYWkp0w///9al7eZVJvoCc6YcqCmZAoUL+pQRSswJIPzTZ+EfrU0Nhc/W2m3cL0irw== X-Received: by 2002:a05:6808:1414:b0:378:9dba:143e with SMTP id w20-20020a056808141400b003789dba143emr5979399oiv.37.1675692029828; Mon, 06 Feb 2023 06:00:29 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v11 1/3] hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel() Date: Mon, 6 Feb 2023 11:00:20 -0300 Message-Id: <20230206140022.2748401-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206140022.2748401-1-dbarboza@ventanamicro.com> References: <20230206140022.2748401-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::243; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x243.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1675692129404100003 Content-Type: text/plain; charset="utf-8" Next patch will move all calls to riscv_load_initrd() to riscv_load_kernel(). Machines that want to load initrd will be able to do via an extra flag to riscv_load_kernel(). This change will expose a sign-extend behavior that is happening in load_elf_ram_sym() when running 32 bit guests [1]. This is currently obscured by the fact that riscv_load_initrd() is using the return of riscv_load_kernel(), defined as target_ulong, and this return type will crop the higher 32 bits that would be padded with 1s by the sign extension when running in 32 bit targets. The changes to be done will force riscv_load_initrd() to use an uint64_t instead, exposing it to the padding when dealing with 32 bit CPUs. There is a discussion about whether load_elf_ram_sym() should or should not sign extend the value returned by 'lowaddr'. What we can do is to prevent the behavior change that the next patch will end up doing. riscv_load_initrd() wasn't dealing with 64 bit kernel entries when running 32 bit CPUs, and we want to keep it that way. One way of doing it is to use target_ulong in 'kernel_entry' in riscv_load_kernel() and rely on the fact that this var will not be sign extended for 32 bit targets. Another way is to explictly clear the higher 32 bits when running 32 bit CPUs for all possibilities of kernel_entry. We opted for the later. This will allow us to be clear about the design choices made in the function, while also allowing us to add a small comment about what load_elf_ram_sym() is doing. With this change, the consolation patch can do its job without worrying about unintended behavioral changes. [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/boot.c | 20 +++++++++++++++++--- hw/riscv/microchip_pfsoc.c | 3 ++- hw/riscv/opentitan.c | 3 ++- hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 3 ++- hw/riscv/spike.c | 3 ++- hw/riscv/virt.c | 3 ++- include/hw/riscv/boot.h | 1 + 8 files changed, 30 insertions(+), 9 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index c7e0e50bd8..df6b4a1fba 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -174,6 +174,7 @@ target_ulong riscv_load_firmware(const char *firmware_f= ilename, } =20 target_ulong riscv_load_kernel(MachineState *machine, + RISCVHartArrayState *harts, target_ulong kernel_start_addr, symbol_fn_t sym_cb) { @@ -192,21 +193,34 @@ target_ulong riscv_load_kernel(MachineState *machine, if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL, &kernel_load_base, NULL, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { - return kernel_load_base; + kernel_entry =3D kernel_load_base; + goto out; } =20 if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, NULL, NULL, NULL) > 0) { - return kernel_entry; + goto out; } =20 if (load_image_targphys_as(kernel_filename, kernel_start_addr, current_machine->ram_size, NULL) > 0) { - return kernel_start_addr; + kernel_entry =3D kernel_start_addr; + goto out; } =20 error_report("could not load kernel '%s'", kernel_filename); exit(1); + +out: + /* + * For 32 bit CPUs 'kernel_entry' can be sign-extended by + * load_elf_ram_sym(). + */ + if (riscv_is_32bit(harts)) { + kernel_entry =3D extract64(kernel_entry, 0, 32); + } + + return kernel_entry; } =20 void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 2b91e49561..712625d2a4 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -629,7 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineSt= ate *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); + kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, + kernel_start_addr, NULL); =20 if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 353f030d80..7fe4fb5628 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -101,7 +101,8 @@ static void opentitan_board_init(MachineState *machine) } =20 if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); + riscv_load_kernel(machine, &s->soc.cpus, + memmap[IBEX_DEV_RAM].base, NULL); } } =20 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 3e3f4b0088..1a7d381514 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DEV_MROM].base, &address_space_m= emory); =20 if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL); + riscv_load_kernel(machine, &s->soc.cpus, + memmap[SIFIVE_E_DEV_DTIM].base, NULL); } } =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index d3ab7a9cda..71be442a50 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -598,7 +598,8 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); + kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, + kernel_start_addr, NULL); =20 if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index cc3f6dac17..1fa91167ab 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -305,7 +305,8 @@ static void spike_board_init(MachineState *machine) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, + kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], + kernel_start_addr, htif_symbol_callback); =20 if (machine->initrd_filename) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index a061151a6f..d0531cc641 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1277,7 +1277,8 @@ static void virt_machine_done(Notifier *notifier, voi= d *data) kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, NUL= L); + kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], + kernel_start_addr, NULL); =20 if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 511390f60e..6295316afb 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -44,6 +44,7 @@ target_ulong riscv_load_firmware(const char *firmware_fil= ename, hwaddr firmware_load_addr, symbol_fn_t sym_cb); target_ulong riscv_load_kernel(MachineState *machine, + RISCVHartArrayState *harts, target_ulong firmware_end_addr, symbol_fn_t sym_cb); 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([191.19.125.138]) by smtp.gmail.com with ESMTPSA id s13-20020a0568080b0d00b00364e8f85c08sm4151177oij.21.2023.02.06.06.00.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 06:00:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ej3buoG/6zvWg00S1uIz5Ky93qCjuGd9hss5PMY0erg=; b=ZhYsbqadGYWIJ9dpHAaYsXCurc6XF7gzkMbEhurTklOBc+iCSiYmLja1WWDKU3W3te i0X9bvX9gtqktAWHVdh+aKCADqLz3C3ophLphWq6nHix1iItq2Y39yCXtY4ncQoW8/tn cOe5B8TIOX9aSy5o2FCtyDm3Sp+bGp7d8HTYbN2eog7FucxUGJGJgG1UmSuJW4q/v1mI rb9mtxDp+iA/KvsSipr0isUhyTtpM3ujBcFBnJgkUiDW47RrAvPKWVjqCaw5fHy4xkdT me4zEv44EM/kdnU8CVW/TUHS4sZp7rH2DEkSEDGglMgxNt9KhjBN+9qQ/Y4ZG+MWkb6V qGlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ej3buoG/6zvWg00S1uIz5Ky93qCjuGd9hss5PMY0erg=; b=SbUEYXQGHgpSIzPSX56HvGTCg9/5JCIekOclrZ2bggH1wdCcwlSKD0TWwGOhrlaSms PpUj/w5Of+g1bQUet6vX4Vp+gFAfTHaEZcx/5gQ51cmsAW5julz5E/lEiPZb4zTxuekR E772me0eoJmk02fY5gDtLvyFi7mhLuUe8ei1CtcsJ9vgz1/8cUg9mzFiUpkvLTUYZflx JyzpBqliQwwq0H7QFrnEt+j1DtZE+7/GWCDNeDC8ehstuic8KSv5OohbZUw2fbzFbv00 Ham/Jb8cUZOlFPIetNhz2mr296OHjgwCK9uYNUU9Xvbx3O8EFd5uvs/PkxrYuRCGSQ4A rUEA== X-Gm-Message-State: AO0yUKWu1TZnehzJwUJFFASaweokUUs3DCWHqXY3dEKJHxbF4LKu/dbN Vn+z7KcxDkXGonW/JoGx4j0ZqSZyHgZYKcsamSg= X-Google-Smtp-Source: AK7set8toyu2nClKqSW2R+wuICDEyOf6kNleiKkgy531Ev8MsWFVyvHRZ04qdG+ZTtxUAQuH0lDs1A== X-Received: by 2002:a05:6808:2d1:b0:37a:2bf0:5021 with SMTP id a17-20020a05680802d100b0037a2bf05021mr5104374oid.15.1675692032277; Mon, 06 Feb 2023 06:00:32 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Palmer Dabbelt , Bin Meng Subject: [PATCH v11 2/3] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() Date: Mon, 6 Feb 2023 11:00:21 -0300 Message-Id: <20230206140022.2748401-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206140022.2748401-1-dbarboza@ventanamicro.com> References: <20230206140022.2748401-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1675692249786100001 Content-Type: text/plain; charset="utf-8" The microchip_icicle_kit, sifive_u, spike and virt boards are now doing the same steps when '-kernel' is used: - execute load_kernel() - load init_rd() - write kernel_cmdline Let's fold everything inside riscv_load_kernel() to avoid code repetition. To not change the behavior of boards that aren't calling riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and allow these boards to opt out from initrd loading. Cc: Palmer Dabbelt Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/boot.c | 11 +++++++++++ hw/riscv/microchip_pfsoc.c | 11 +---------- hw/riscv/opentitan.c | 3 ++- hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 11 +---------- hw/riscv/spike.c | 11 +---------- hw/riscv/virt.c | 11 +---------- include/hw/riscv/boot.h | 1 + 8 files changed, 20 insertions(+), 42 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index df6b4a1fba..4954bb9d4b 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -176,10 +176,12 @@ target_ulong riscv_load_firmware(const char *firmware= _filename, target_ulong riscv_load_kernel(MachineState *machine, RISCVHartArrayState *harts, target_ulong kernel_start_addr, + bool load_initrd, symbol_fn_t sym_cb) { const char *kernel_filename =3D machine->kernel_filename; uint64_t kernel_load_base, kernel_entry; + void *fdt =3D machine->fdt; =20 g_assert(kernel_filename !=3D NULL); =20 @@ -220,6 +222,15 @@ out: kernel_entry =3D extract64(kernel_entry, 0, 32); } =20 + if (load_initrd && machine->initrd_filename) { + riscv_load_initrd(machine, kernel_entry); + } + + if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } + return kernel_entry; } =20 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 712625d2a4..e81bbd12df 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -630,16 +630,7 @@ static void microchip_icicle_kit_machine_init(MachineS= tate *machine) firmware_end_addr= ); =20 kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, - kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", - "bootargs", machine->kernel_cmdline); - } + kernel_start_addr, true, NULL); =20 /* Compute the fdt load address in dram */ fdt_load_addr =3D riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DR= AM_LO].base, diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 7fe4fb5628..b06944d382 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -102,7 +102,8 @@ static void opentitan_board_init(MachineState *machine) =20 if (machine->kernel_filename) { riscv_load_kernel(machine, &s->soc.cpus, - memmap[IBEX_DEV_RAM].base, NULL); + memmap[IBEX_DEV_RAM].base, + false, NULL); } } =20 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 1a7d381514..04939b60c3 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -115,7 +115,8 @@ static void sifive_e_machine_init(MachineState *machine) =20 if (machine->kernel_filename) { riscv_load_kernel(machine, &s->soc.cpus, - memmap[SIFIVE_E_DEV_DTIM].base, NULL); + memmap[SIFIVE_E_DEV_DTIM].base, + false, NULL); } } =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 71be442a50..ad3bb35b34 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -599,16 +599,7 @@ static void sifive_u_machine_init(MachineState *machin= e) firmware_end_addr= ); =20 kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, - kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + kernel_start_addr, true, NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 1fa91167ab..a584d5b3a2 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -307,16 +307,7 @@ static void spike_board_init(MachineState *machine) =20 kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], kernel_start_addr, - htif_symbol_callback); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + true, htif_symbol_callback); } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d0531cc641..2f2c82e8df 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1278,16 +1278,7 @@ static void virt_machine_done(Notifier *notifier, vo= id *data) firmware_end_addr= ); =20 kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], - kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + kernel_start_addr, true, NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 6295316afb..ea1de8b020 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -46,6 +46,7 @@ target_ulong riscv_load_firmware(const char *firmware_fil= ename, target_ulong riscv_load_kernel(MachineState *machine, RISCVHartArrayState *harts, target_ulong firmware_end_addr, + bool load_initrd, symbol_fn_t sym_cb); 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([191.19.125.138]) by smtp.gmail.com with ESMTPSA id s13-20020a0568080b0d00b00364e8f85c08sm4151177oij.21.2023.02.06.06.00.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 06:00:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PQ1DGt6dxRvvCfgagSgAnk05yahbN85wZ/YBnPu3ZTQ=; b=HC+NUtEqJTNncCMRzh1urqr7TVZNiCHpvxiYAGnLY2P2GsnNujRtFXwaQ3AddqLm// eDrKU+DFb8E+lFYcMRCMF1/MJCNyNDl6NC2qptkegYetxmlvUFk5DOmCch7+whwQFEfS ViJJPUd79QWJI2ZmEMGqiqUYYTrL3FWoGoiD5l67hWxQF30DSnjavwY1qms/NBvxxsph PamcBQXUUNYln6pWr2TDYckJLCwEL0MK8XQPI7vkvV9m/5lOlX0tIo6/AGjag/t1UlJI 2jiZJAwAD9vWJVhwgrJcCPR1ugu8pajg0P6d9vgUrEliugi5JUJzergF5ULOGNxT7JX+ 5pNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PQ1DGt6dxRvvCfgagSgAnk05yahbN85wZ/YBnPu3ZTQ=; b=1/Yec/d8MsEjJQSHGsxF7Dva4bQcXQ6NdnbDgpO677/G9PJgU4KpyfDzDON9ipxVQ5 OFz3bqxEobi4lkJ4otHkG3+Xd3i/NyjKdDF15jl3lKh704CHZTWCkhzVrzk2fBIB4Xep aLOj/7KHDWFZApZtFEX1mEs8H7WT8G0dTlfpqRuH17l6t6xD7PVQBUtXjJBq7rElyfOh y02iMSe6JKPceaYNVX1sbUAXHIwrTki2I1okiWF4LKobw4KCErJ76+3dRNugwJ5Fxe8Q VHoqD90552EhLXSwS/8lVwRGaI37bLfpQilo4B4PMQZjgS8kmBeATz7CQF90nEu0vceM NH3Q== X-Gm-Message-State: AO0yUKVwLOD8MjHz2dMGBMlZHbaJWU6Zltu45ZUDOeLdmJw+PEJeSzU5 IXuVStBkyuJJ44ZbfpUZwrAAPEgZLqO1QbuJAYA= X-Google-Smtp-Source: AK7set8x7lt76J/Yy6Qx2LsKLvisXjc0mq9fnW7TRMscyd8hiELCFn/DzsjFt4KLCdogNAgCkV4FCw== X-Received: by 2002:a05:6808:a98:b0:364:fc2c:687a with SMTP id q24-20020a0568080a9800b00364fc2c687amr10910921oij.57.1675692035276; Mon, 06 Feb 2023 06:00:35 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v11 3/3] hw/riscv/boot.c: make riscv_load_initrd() static Date: Mon, 6 Feb 2023 11:00:22 -0300 Message-Id: <20230206140022.2748401-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206140022.2748401-1-dbarboza@ventanamicro.com> References: <20230206140022.2748401-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1675692128107100001 The only remaining caller is riscv_load_kernel_and_initrd() which belongs to the same file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/boot.c | 80 ++++++++++++++++++++--------------------- include/hw/riscv/boot.h | 1 - 2 files changed, 40 insertions(+), 41 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 4954bb9d4b..52bf8e67de 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -173,6 +173,46 @@ target_ulong riscv_load_firmware(const char *firmware_= filename, exit(1); } =20 +static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) +{ + const char *filename =3D machine->initrd_filename; + uint64_t mem_size =3D machine->ram_size; + void *fdt =3D machine->fdt; + hwaddr start, end; + ssize_t size; + + g_assert(filename !=3D NULL); + + /* + * We want to put the initrd far enough into RAM that when the + * kernel is uncompressed it will not clobber the initrd. However + * on boards without much RAM we must ensure that we still leave + * enough room for a decent sized initrd, and on boards with large + * amounts of RAM we must avoid the initrd being so far up in RAM + * that it is outside lowmem and inaccessible to the kernel. + * So for boards with less than 256MB of RAM we put the initrd + * halfway into RAM, and for boards with 256MB of RAM or more we put + * the initrd at 128MB. + */ + start =3D kernel_entry + MIN(mem_size / 2, 128 * MiB); + + size =3D load_ramdisk(filename, start, mem_size - start); + if (size =3D=3D -1) { + size =3D load_image_targphys(filename, start, mem_size - start); + if (size =3D=3D -1) { + error_report("could not load ramdisk '%s'", filename); + exit(1); + } + } + + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ + if (fdt) { + end =3D start + size; + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); + } +} + target_ulong riscv_load_kernel(MachineState *machine, RISCVHartArrayState *harts, target_ulong kernel_start_addr, @@ -234,46 +274,6 @@ out: return kernel_entry; } =20 -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) -{ - const char *filename =3D machine->initrd_filename; - uint64_t mem_size =3D machine->ram_size; - void *fdt =3D machine->fdt; - hwaddr start, end; - ssize_t size; - - g_assert(filename !=3D NULL); - - /* - * We want to put the initrd far enough into RAM that when the - * kernel is uncompressed it will not clobber the initrd. However - * on boards without much RAM we must ensure that we still leave - * enough room for a decent sized initrd, and on boards with large - * amounts of RAM we must avoid the initrd being so far up in RAM - * that it is outside lowmem and inaccessible to the kernel. - * So for boards with less than 256MB of RAM we put the initrd - * halfway into RAM, and for boards with 256MB of RAM or more we put - * the initrd at 128MB. - */ - start =3D kernel_entry + MIN(mem_size / 2, 128 * MiB); - - size =3D load_ramdisk(filename, start, mem_size - start); - if (size =3D=3D -1) { - size =3D load_image_targphys(filename, start, mem_size - start); - if (size =3D=3D -1) { - error_report("could not load ramdisk '%s'", filename); - exit(1); - } - } - - /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ - if (fdt) { - end =3D start + size; - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); - } -} - /* * This function makes an assumption that the DRAM interval * 'dram_base' + 'dram_size' is contiguous. diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index ea1de8b020..a2e4ae9cb0 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -48,7 +48,6 @@ target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, bool load_initrd, symbol_fn_t sym_cb); -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, MachineState *ms); void riscv_load_fdt(hwaddr fdt_addr, void *fdt); --=20 2.39.1