From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674518464; cv=none; d=zohomail.com; s=zohoarc; b=kK29rgi4HJ2jvHLXvJQak/xALEXvF1yBaD/NFxViuZw2BAkspWtp+3TF5JpXWUsNm8JwJdg7M1E3rbodUiuyzUNLUaOCAZ1oOAYCKUCjS6i392zH7GhmxXpzJIPR8+X2323iryGuBXamVN+pNGOm5zIYONIconj97U8ksO3Rd0E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674518464; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WHiUfCNScuj5b8UaTFKcutwQlH91thfqJKII3X2ibc0=; b=GkqaqEbDSmhD7GQZtimDLIPGorICgbotFFbWxB6nv37QbX4clXQlFaF54mW1o9urlyCYBqy1HFN1tBiepDZKV6A5a5ypMaGp5m6MnE8AFOWoUdx6Nvr3hiOekW/FfOjvP8BRpxQPHuCvGPxmIEi9/1i+tao28cAfwQvuPJ2GGX4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674518464769181.5277390612356; Mon, 23 Jan 2023 16:01:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pK6kB-0007yn-87; Mon, 23 Jan 2023 19:00:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK6k8-0007mi-8H for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:00:52 -0500 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK6k5-0001qI-Q8 for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:00:52 -0500 Received: by mail-pf1-x431.google.com with SMTP id 20so10083392pfu.13 for ; Mon, 23 Jan 2023 16:00:49 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.00.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:00:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WHiUfCNScuj5b8UaTFKcutwQlH91thfqJKII3X2ibc0=; b=AQNAHJLCyoCkg074RzrDdBWr27u1dLXHQp4dCNyWB4U7vd1eCsSoMtRUUCe0ZlDfNg IEC/lWygI6T/Xkq9PIwsPwxO5eWJss1npOumWERbYaV1hS/9Sj1kzxjjDtl4IAo9CbTj 9S/I/8vE3NIf/l7kXoK/O3uNe6f+qjKXmjKpUxcKRUfADmpsUL/KujG0Pb3Yi6sUmtGm NscBqqid2cu9rpOGOy0hb3J8ZdHp30loWHL3nW8rCwswfonV890lfW4N+P49gLIcGrsT 8wB6U+boad38BOUKeKOWLDQKriWoFm1+VVbguXNYimm9K/vU/xuXyLreEhxdSqxHV519 h54w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WHiUfCNScuj5b8UaTFKcutwQlH91thfqJKII3X2ibc0=; b=g2FbghyL/IWipRHMcNETpSbKjbEhfkFm8lfRIJTLHwF07xWhaZvpx/cc0miW5uq5Te CKql62pR/R7lQTPkREbvVxa4z+qJ6VI3J4d/WtZjf1bMKecDN8kZAWimKgTrWEvSsCtW xPZaxNG8CJ8HDtqTbMHnZJTVKQ832jxL7ttAllqlR28oVZ9HS0JdaOGW4up5tN3ikm+k l95lNbIYPQG1uEZr6W9g8Q5SyBQZmWUHgiMrUi32A5+kfYw427ywMApO9DvbTxsHbe0B r/UuCd7udbM6m4F5ZdXQm6P4aS8OK9cB2kkRF9rH6Y6JFxqQlcNkN1F10dxIjjwyg4TB BHQw== X-Gm-Message-State: AFqh2koPVcGFsBcRXgYo2+59b5DsW8yukFROsfhv0d6cGokpAG81cFRv DZOxE1KAbq5SjiglcGh3+gGKjKnq6jk+pp/s X-Google-Smtp-Source: AMrXdXttokHTtdyQoEQr4Jqp7QNHYN7yk5uLR6E0WaCS+gXW7RdhPhv+IVs34LqaH+GV42sXsPifeg== X-Received: by 2002:a05:6a00:300f:b0:58d:94a2:f404 with SMTP id ay15-20020a056a00300f00b0058d94a2f404mr30318795pfb.12.1674518448351; Mon, 23 Jan 2023 16:00:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 01/22] target/arm: Fix pmsav8 stage2 secure parameter Date: Mon, 23 Jan 2023 14:00:06 -1000 Message-Id: <20230124000027.3565716-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518467022100003 Content-Type: text/plain; charset="utf-8" We have computed the security state for the stage2 lookup into s2walk_secure -- use it. Fixes: fca45e3467f ("target/arm: Add PMSAv8r functionality") Signed-off-by: Richard Henderson --- target/arm/ptw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 57f3615a66..b0f8c59767 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2727,7 +2727,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, =20 if (arm_feature(env, ARM_FEATURE_PMSA)) { ret =3D get_phys_addr_pmsav8(env, ipa, access_type, - ptw->in_mmu_idx, is_secure, result, fi); + ptw->in_mmu_idx, s2walk_secure, result,= fi); } else { ret =3D get_phys_addr_lpae(env, ptw, ipa, access_type, is_el0, result, fi); --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674518493; cv=none; d=zohomail.com; s=zohoarc; b=SOSa1UwBKmQGHur4UcF4r1rwIdXJOejIMUyQzlmTOhH0V4nc8eyEOltIPkbmTq7ZVHSQZ/g8uoT3n4hSINE+ReN3WYS7+QmPBWnbGJfXP+aj+P7XwC7GserG+EdDI07hcjKgGfAaDJoRQ0kHyt7B+1fCCmUInotpipvSL4EroZ8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674518493; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QFtg05tnMoQbda+pdmKHzaqxzHXCvc/zyUatL7UKJGo=; b=d5L8SRCilVK5lpOhxOF33zVd9oOLvXo3wx73XoHzOyykirFK/qkwwREnfgE7UbXAunDlQXQdhf2CIR+O8Pp7rozEc5tdIlnhVv9qhyxu0ILitiwzPdQuhRNGlQEJ80xc7GEy2r9gUbLT+kbKAnBQrOY8g4cSlrHhLYQdcj/in40= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674518493822475.49449032639575; Mon, 23 Jan 2023 16:01:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pK6kC-000860-Qi; Mon, 23 Jan 2023 19:00:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK6kB-0007zc-56 for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:00:55 -0500 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK6k7-0001qY-MF for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:00:54 -0500 Received: by mail-pf1-x429.google.com with SMTP id s3so10082576pfd.12 for ; Mon, 23 Jan 2023 16:00:51 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.00.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:00:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QFtg05tnMoQbda+pdmKHzaqxzHXCvc/zyUatL7UKJGo=; b=TFJTT63Q32h0RPFn5vpwT6oN4dPiuhk6QriCs8aekolb+D/IpCyfPtXP4GnEA66Zq5 XHocpe+mrwj0VqEqXJrh2uE8dt05J1LH6MRrpcPXwoB2XoxfNNdC3KqxghH7iK0pNYCC +kBh9sRwJI1bMHJ7UQQgW0jNn6EtBoDHt1FeucNjFvOiHBPJtjXSfIsCcfTANdQoqsF3 V+wwXayNSCIhHJIP+pSIHpmvBLsQElkROKx7xCj5PNPH4XoXF/jkgbGun9gYBR/6Tz3a qwKPnlnNpKbhq6vXG7yoUoctNh6sfUVNH+1XxAAgQmAZOQvVs0M4DLsmay09Bs4HmLgn pdXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QFtg05tnMoQbda+pdmKHzaqxzHXCvc/zyUatL7UKJGo=; b=ZAJbfaORJtcyez9vRUcdxfn2rqVpOLbR78lLr+Qm1XCJ9VA0gBpjGyH92GBZGGAyfv yrLmvt+kZPAgyLdVzZgEj0CA6lkGqIX1dIN7F4EivihN0C70s9ovodP8rw/fuUMTT9CM nVJlGmQAIkYsbuQYbhrGd6URRlxCleYibLzRAX1wJWf0RYH2gp/3IFMXPBaoIzSQ4l/y x9fkiw2pJGZqmu9c5mMdAPsYqvor+jBpp+C1VUjNP5DiKICq97cpaDhXqfsaBqRco0qi SaMGQN1phvVYVpFLEtDbvSPWd35U97sekHnlyu4Y/bSeCsazr2/gc3RoekXgkQWic5bz k2RA== X-Gm-Message-State: AFqh2koVoqXjXS4rs/NM2dcOxmiIT/vul642sHOjD6WjWAog71JNTBBZ e+I54v8VEzrnt4JOHJ/6ESHXTYEW4nLW7QuX X-Google-Smtp-Source: AMrXdXsPTV8wAL3HB0CDu3ebq2kA2K+f6DQpth8uSUXBIyNYdm/1NhyPxBmBOU8/zxXfLKc51G6JBg== X-Received: by 2002:aa7:9467:0:b0:58b:aaaa:82a9 with SMTP id t7-20020aa79467000000b0058baaaa82a9mr26859532pfq.25.1674518450151; Mon, 23 Jan 2023 16:00:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 02/22] target/arm: Rewrite check_s2_mmu_setup Date: Mon, 23 Jan 2023 14:00:07 -1000 Message-Id: <20230124000027.3565716-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518495244100001 Content-Type: text/plain; charset="utf-8" Integrate neighboring code from get_phys_addr_lpae which computed starting level, as it is easier to validate when doing both at the same time. Mirror the checks at the start of AArch{64,32}.S2Walk, especially S2InvalidESL and S2InconsistentSL. This reverts 49ba115bb74, which was incorrect -- there is nothing in the ARM pseudocode that depends on TxSZ, i.e. outputsize; the pseudocode is consistent in referencing PAMax. Fixes: 49ba115bb74 ("target/arm: Pass outputsize down to check_s2_mmu_setup= ") Signed-off-by: Richard Henderson --- target/arm/ptw.c | 173 ++++++++++++++++++++++++++--------------------- 1 file changed, 97 insertions(+), 76 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index b0f8c59767..437f6fefa9 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1077,70 +1077,119 @@ static ARMVAParameters aa32_va_parameters(CPUARMSt= ate *env, uint32_t va, * check_s2_mmu_setup * @cpu: ARMCPU * @is_aa64: True if the translation regime is in AArch64 state - * @startlevel: Suggested starting level - * @inputsize: Bitsize of IPAs + * @tcr: VTCR_EL2 or VSTCR_EL2 + * @ds: Effective value of TCR.DS. + * @iasize: Bitsize of IPAs * @stride: Page-table stride (See the ARM ARM) * - * Returns true if the suggested S2 translation parameters are OK and - * false otherwise. + * Decode the starting level of the S2 lookup, returning INT_MIN if + * the configuration is invalid. */ -static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, - int inputsize, int stride, int outputsize) +static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr, + bool ds, int iasize, int stride) { - const int grainsize =3D stride + 3; - int startsizecheck; - - /* - * Negative levels are usually not allowed... - * Except for FEAT_LPA2, 4k page table, 52-bit address space, which - * begins with level -1. Note that previous feature tests will have - * eliminated this combination if it is not enabled. - */ - if (level < (inputsize =3D=3D 52 && stride =3D=3D 9 ? -1 : 0)) { - return false; - } - - startsizecheck =3D inputsize - ((3 - level) * stride + grainsize); - if (startsizecheck < 1 || startsizecheck > stride + 4) { - return false; - } + int sl0, sl2, startlevel, granulebits, levels; + int s1_min_iasize, s1_max_iasize; =20 + sl0 =3D extract32(tcr, 6, 2); if (is_aa64) { + /* + * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of + * get_phys_addr_lpae, that used aa64_va_parameters which apply + * to aarch64. If Stage1 is aarch32, the min_txsz is larger. + * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to + * inputsize is 64 - 24 =3D 40. + */ + if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) { + goto fail; + } + + /* + * AArch64.S2InvalidSL: Interpretation of SL depends on the page s= ize, + * so interleave AArch64.S2StartLevel. + */ switch (stride) { - case 13: /* 64KB Pages. */ - if (level =3D=3D 0 || (level =3D=3D 1 && outputsize <=3D 42)) { - return false; + case 9: /* 4KB */ + /* SL2 is RES0 unless DS=3D1 & 4KB granule. */ + sl2 =3D extract64(tcr, 33, 1); + if (ds && sl2) { + if (sl0 !=3D 0) { + goto fail; + } + startlevel =3D -1; + } else { + startlevel =3D 2 - sl0; + switch (sl0) { + case 2: + if (arm_pamax(cpu) < 44) { + goto fail; + } + break; + case 3: + if (!cpu_isar_feature(aa64_st, cpu)) { + goto fail; + } + startlevel =3D 3; + break; + } } break; - case 11: /* 16KB Pages. */ - if (level =3D=3D 0 || (level =3D=3D 1 && outputsize <=3D 40)) { - return false; + case 11: /* 16KB */ + switch (sl0) { + case 2: + if (arm_pamax(cpu) < 42) { + goto fail; + } + break; + case 3: + if (!ds) { + goto fail; + } + break; } + startlevel =3D 3 - sl0; break; - case 9: /* 4KB Pages. */ - if (level =3D=3D 0 && outputsize <=3D 42) { - return false; + case 13: /* 64KB */ + switch (sl0) { + case 2: + if (arm_pamax(cpu) < 44) { + goto fail; + } + break; + case 3: + goto fail; } + startlevel =3D 3 - sl0; break; default: g_assert_not_reached(); } - - /* Inputsize checks. */ - if (inputsize > outputsize && - (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) { - /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. = */ - return false; - } } else { - /* AArch32 only supports 4KB pages. Assert on that. */ + /* + * Things are simpler for AArch32 EL2, with only 4k pages. + * There is no separate S2InvalidSL function, but AArch32.S2Walk + * begins with walkparms.sl0 in {'1x'}. + */ assert(stride =3D=3D 9); - - if (level =3D=3D 0) { - return false; + if (sl0 >=3D 2) { + goto fail; } + startlevel =3D 2 - sl0; } - return true; + + /* AArch{64,32}.S2InconsistentSL are functionally equivalent. */ + levels =3D 3 - startlevel; + granulebits =3D stride + 3; + + s1_min_iasize =3D levels * stride + granulebits + 1; + s1_max_iasize =3D s1_min_iasize + (stride - 1) + 4; + + if (iasize >=3D s1_min_iasize && iasize <=3D s1_max_iasize) { + return startlevel; + } + + fail: + return INT_MIN; } =20 /** @@ -1296,38 +1345,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, */ level =3D 4 - (inputsize - 4) / stride; } else { - /* - * For stage 2 translations the starting level is specified by the - * VTCR_EL2.SL0 field (whose interpretation depends on the page si= ze) - */ - uint32_t sl0 =3D extract32(tcr, 6, 2); - uint32_t sl2 =3D extract64(tcr, 33, 1); - int32_t startlevel; - bool ok; - - /* SL2 is RES0 unless DS=3D1 & 4kb granule. */ - if (param.ds && stride =3D=3D 9 && sl2) { - if (sl0 !=3D 0) { - level =3D 0; - goto do_translation_fault; - } - startlevel =3D -1; - } else if (!aarch64 || stride =3D=3D 9) { - /* AArch32 or 4KB pages */ - startlevel =3D 2 - sl0; - - if (cpu_isar_feature(aa64_st, cpu)) { - startlevel &=3D 3; - } - } else { - /* 16KB or 64KB pages */ - startlevel =3D 3 - sl0; - } - - /* Check that the starting level is valid. */ - ok =3D check_s2_mmu_setup(cpu, aarch64, startlevel, - inputsize, stride, outputsize); - if (!ok) { + int startlevel =3D check_s2_mmu_setup(cpu, aarch64, tcr, param.ds, + inputsize, stride); + if (startlevel =3D=3D INT_MIN) { + level =3D 0; goto do_translation_fault; } level =3D startlevel; --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674518467; cv=none; d=zohomail.com; s=zohoarc; b=SmYuFNbZEsgF8J9+ILw8Uyyg2rZaRnPHDoH2THEM1zsmPJG/F/aRwlprnYcL7sY0GdHXsDR1k86LyAF5aTOwCHAMh2+wSCkGSPkSA800PcM/lzyr/JuJeIrEi9spSdmMN9JypHbCb+mmoxfBHqXgyCKRc2kKIjnfQL5DRSfumXo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674518467; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=roMq0cKqYUSuqmepPgcMOSqHad1ObHN98rGJI0Zfrfk=; b=ZuB2NN1g1NG7xa0sKItEZ9csuA1J5vnSO8ho/NOVaDRxUOK6JRsEp8g1BjhhmyC75V7BmrU8P/1ewbyDXk8WYqNYHAQhEBPQVwX5NGujS6XQYY6pqLCw1XywAzc2e6mDJQNGmm/61Y1D544dhCktYTQT0oZLq/AiqhPxQJcJupA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167451846794096.7397916701484; Mon, 23 Jan 2023 16:01:07 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pK6kD-00087R-Cb; Mon, 23 Jan 2023 19:00:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK6kB-00081t-OI for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:00:55 -0500 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK6k9-0001qq-CA for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:00:55 -0500 Received: by mail-pf1-x432.google.com with SMTP id i65so10136680pfc.0 for ; Mon, 23 Jan 2023 16:00:52 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.00.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:00:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=roMq0cKqYUSuqmepPgcMOSqHad1ObHN98rGJI0Zfrfk=; b=ZfJC03gq9ckBR1NFci4XY0r9zkl/MW5c1L0ShZw7t0ZlcqnHicBTjqd3paqp4D+7zH OWh3ibRbbB+IB6g9uorJlOhushVCZdgXpmlkNylnj1Uc3fT7N5I+JU3LVjn2CTkTz5YN 5DRa6CdmNHdugGHW7FP2Lt87Gj56HhxAXsudaacnMybZ5hNI6zhQiQumEYWAhL9mqr/K i7k40Jn0KYHoGGzWyvxJ5KkYxPh3qmCD7p6bo5018SFhuXa1tIqU+7IZZQIP08glbuiR WiXyD0yX4n7iEBtKFVrSIgXhinOMoQhOE0DLOvVsYu99jxSvk1SR9LbCv3Cn+Ryx1jRQ zDlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=roMq0cKqYUSuqmepPgcMOSqHad1ObHN98rGJI0Zfrfk=; b=al8x61EcfxoHNM5ZiY93IYsDZO+AXxDxEdN6t9r6wjsu1Y7b6plJRM/ior1J7ZnWfW wjiRuSFTfQLuhes0uO+tMek5Lv1Rm+uApjhf1KDiWK/AUC/IezYEgpbCO7mD1Btn4Ok5 orQjXjRLBJfSsLs+EFt6xGf+48TdUDIwVKD3WuJ1KMONpV9YQRRUYFZZxbMqKlc/Xtqe NeHRyROUqbf7RZM/LtdTDOyiZuiCKKhcQN0OI0dvWfaMHULOUCn1cqaHLvkSeeFieNq0 GpnyrcS35UL/rrPNOfq8gx0ZJxPHET1Gh92ImU2uNugo6Q5dIfypizUVENUQs/zMCmEQ l1yQ== X-Gm-Message-State: AFqh2kqifqxQ5QO5RTSmyAUItwcBq9TVXF4Z2Q9BdcLJjripQDsDmOCU WhsYWmxFoBA9I7F+yW6+PIRnApuKbfcragqV X-Google-Smtp-Source: AMrXdXu3xDLhZ/R4zYo3CWaOud9hN4QWeFpd6p86xW1EpWUug2JVN9rM+FM4VAnz7/ksgGEuggyjEQ== X-Received: by 2002:a05:6a00:3020:b0:58d:92ff:8a2a with SMTP id ay32-20020a056a00302000b0058d92ff8a2amr25340215pfb.23.1674518452051; Mon, 23 Jan 2023 16:00:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 03/22] target/arm: Add isar_feature_aa64_rme Date: Mon, 23 Jan 2023 14:00:08 -1000 Message-Id: <20230124000027.3565716-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518469005100005 Content-Type: text/plain; charset="utf-8" Add the missing field for ID_AA64PFR0, and the predicate. Disable it if EL3 is forced off by the board or command-line. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 6 ++++++ target/arm/cpu.c | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8cf70693be..81d5a51b62 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2178,6 +2178,7 @@ FIELD(ID_AA64PFR0, SEL2, 36, 4) FIELD(ID_AA64PFR0, MPAM, 40, 4) FIELD(ID_AA64PFR0, AMU, 44, 4) FIELD(ID_AA64PFR0, DIT, 48, 4) +FIELD(ID_AA64PFR0, RME, 52, 4) FIELD(ID_AA64PFR0, CSV2, 56, 4) FIELD(ID_AA64PFR0, CSV3, 60, 4) =20 @@ -4001,6 +4002,11 @@ static inline bool isar_feature_aa64_sel2(const ARMI= SARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) !=3D 0; } =20 +static inline bool isar_feature_aa64_rme(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) !=3D 0; +} + static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) !=3D 0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5f63316dbf..b10ace74cd 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1944,6 +1944,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSD= BG, 0); cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL3, 0); + + /* Disable the realm management extension, which requires EL3. */ + cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, RME, 0); } =20 if (!cpu->has_el2) { --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674518729; cv=none; d=zohomail.com; s=zohoarc; b=eFsHIGvxs40Fh2dTwqd05v+PvoGBH68B5Ug+RC6t1/FTlHo5McxwVxMstRILdgcLU8MheP9ufBCg6w4ojE8qwoI2w2RKcx4OMqHlNR6IB9M1t4JIT/yHWeFcot3B/FUCwGzgyTzbYHLkLeO5kmqDkUnBJdhMNSdv3btW/DsNbA4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674518729; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4KPCpSfOS3MJgxEieajg71yzTiyoHQkyPgf80iICoXk=; b=g3choEvw1yE4GivKXDzE0dA+0q/Z7b9MznXvxoiPU3f+PGmRhs63QPTygkOV6iYJRmF3xRttobymHrvMhaACDXRuHNK7IQhjl+2cUwRcLFfhBSXBnnsZOQZuCCLo6AiA5YcBn08178+z2jQi8geXTfgAbLM1iY5kOULc/y0zHrA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167451872977093.28079283751174; Mon, 23 Jan 2023 16:05:29 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pK6kK-0008Tf-CG; Mon, 23 Jan 2023 19:01:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK6kF-0008BW-PR for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:01 -0500 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK6kA-0001jO-Uj for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:00:59 -0500 Received: by mail-pf1-x434.google.com with SMTP id a184so10096355pfa.9 for ; Mon, 23 Jan 2023 16:00:54 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.00.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:00:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4KPCpSfOS3MJgxEieajg71yzTiyoHQkyPgf80iICoXk=; b=PQ15xiPemBcAFX7MBj1LRvs+4eHEz4bC9dqtgCa4H9FMD8CNyZff0+jn7G3RYoYrNS GJUTsrjedkyyygRoGSb4TudSqaYOPM2uH879/W2VYmINlMBwELjsEvYg4KyfLAjEQ2YN H4QjLlmxrAzlxZzEvdckLVZ0lsy5hwLvmNEuEWs2HnzbsUcOPKFgokT6qLF4tez+327n x8OxOXKFitlDGmJVI2hSHAziupH+6JF/PQywPDw0zZTxkhQ0/IrAOT3E2FfeS+95B62R 0rCoKdb6dy0ggHCcwLmU3SxHntV2pfFPLPXoeInNRXj+I6LCSi9kM/dO7E1TZiV+29oV e5Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4KPCpSfOS3MJgxEieajg71yzTiyoHQkyPgf80iICoXk=; b=pdyD02o7bWWXJEXGAFeH7h75VuD3+wisnOiDIaE9YE6PDwCMVu2lt2imUXwGMYWrRT 96yqQWBid5MJT+Cg7sUzJPsRgU0XflI5h+7HW8rxz0SBn89TMnOOj9it8yiIl9txo+Jf TfQUohs2cN510fibvuGG+hn1lezds1+WI/wrmJfa73gbcRAiaJ0pgeKk2/mBXOVDLZia i9oUq1qoKPz9OSKUHy6wtHWPJjl9OuvROnUZP2DrA4xnWB2p8sWzoynx1eRR+/XlYPNM bFImEh8I1MXxcP8r5PaWOWtRCurJamz73hEDxAOjk2WEqFZVLFkdzJatRDMnpBXquEw8 SAwQ== X-Gm-Message-State: AFqh2kqhsdfcxr/edLuAXWtgEs6Hlw/g7Otym0x7lUplgDdvbbO4j4AH LZcGBlM3SLrlrnw3FrvEuu6KRUrI9tR6AI9D X-Google-Smtp-Source: AMrXdXtbLoZ4YrFrdoUs3WMR/2YqC652jvQiGKyW2tA3Ilwn85/MB5Y9uh117CKqmmCAfdZ4Hr3waA== X-Received: by 2002:a05:6a00:430a:b0:574:35fd:379e with SMTP id cb10-20020a056a00430a00b0057435fd379emr25538922pfb.2.1674518453705; Mon, 23 Jan 2023 16:00:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 04/22] target/arm: Update SCR and HCR for RME Date: Mon, 23 Jan 2023 14:00:09 -1000 Message-Id: <20230124000027.3565716-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518730368100002 Content-Type: text/plain; charset="utf-8" Define the missing SCR and HCR bits, allow SCR_NSE and {SCR,HCR}_GPF to be set, and invalidate TLBs when NSE changes. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 5 +++-- target/arm/helper.c | 10 ++++++++-- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 81d5a51b62..9d1a6b346d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1638,7 +1638,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define HCR_TERR (1ULL << 36) #define HCR_TEA (1ULL << 37) #define HCR_MIOCNCE (1ULL << 38) -/* RES0 bit 39 */ +#define HCR_TME (1ULL << 39) #define HCR_APK (1ULL << 40) #define HCR_API (1ULL << 41) #define HCR_NV (1ULL << 42) @@ -1647,7 +1647,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define HCR_NV2 (1ULL << 45) #define HCR_FWB (1ULL << 46) #define HCR_FIEN (1ULL << 47) -/* RES0 bit 48 */ +#define HCR_GPF (1ULL << 48) #define HCR_TID4 (1ULL << 49) #define HCR_TICAB (1ULL << 50) #define HCR_AMVOFFEN (1ULL << 51) @@ -1712,6 +1712,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) #define SCR_GPF (1ULL << 48) +#define SCR_NSE (1ULL << 62) =20 #define HSTR_TTEE (1 << 16) #define HSTR_TJDBX (1 << 17) diff --git a/target/arm/helper.c b/target/arm/helper.c index 72b37b7cf1..293f8eda8c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1869,6 +1869,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_hcx, cpu)) { valid_mask |=3D SCR_HXEN; } + if (cpu_isar_feature(aa64_rme, cpu)) { + valid_mask |=3D SCR_NSE | SCR_GPF; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -1898,10 +1901,10 @@ static void scr_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) env->cp15.scr_el3 =3D value; =20 /* - * If SCR_EL3.NS changes, i.e. arm_is_secure_below_el3, then + * If SCR_EL3.{NS,NSE} changes, i.e. change of security state, * we must invalidate all TLBs below EL3. */ - if (changed & SCR_NS) { + if (changed & (SCR_NS | SCR_NSE)) { tlb_flush_by_mmuidx(env_cpu(env), (ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E10_1 | @@ -5578,6 +5581,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) if (cpu_isar_feature(aa64_fwb, cpu)) { valid_mask |=3D HCR_FWB; } + if (cpu_isar_feature(aa64_rme, cpu)) { + valid_mask |=3D HCR_GPF; + } } =20 if (cpu_isar_feature(any_evt, cpu)) { --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674518709; cv=none; d=zohomail.com; s=zohoarc; b=AtUh6Mh2+g7ZxZ94ogN4I03BpTGSpwgxV3K2L7MfNsMRaNjDSoYMF//HBicf/599dAGn0iQNJnY5bI30kr+A2ZAEZPFpQUuKEVQClBhMzibUTZlFYU1XC+h2dECVlY9VuUFylxeHXhxklJuoSiqza4it3473YmbvixsixTpQxlI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674518709; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Go52RyLr599mBvLq+RmbiVaK0sm0+xrVqrOqv+d33DY=; b=Arej6UxzxwibWQtcdEn0tKWfcS4AV06hLQPznT4C3GHgh62YnNm01cEmkW5C8NksLJGkP4bgr7C1P16v0xg+ehgzMzJS3XwEtq17H6xHxiq8fiZiYhmSGxoyp5V7SUzzMUXQJHMvsp6LfURAoQMrYwRjQ7j6MbudTUcHenDuRAs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674518709936772.9355968009688; Mon, 23 Jan 2023 16:05:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pK6kI-0008Ii-Fc; Mon, 23 Jan 2023 19:01:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK6kF-000897-1L for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:00:59 -0500 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK6kC-0001rr-Ta for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:00:58 -0500 Received: by mail-pg1-x52e.google.com with SMTP id q9so10246238pgq.5 for ; Mon, 23 Jan 2023 16:00:56 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.00.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:00:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Go52RyLr599mBvLq+RmbiVaK0sm0+xrVqrOqv+d33DY=; b=B6yo35Q5oDbiBExkcE+0oPzPlwG2fHDXd82K6zZcwQA7wWesDJwjMGY0/xGywzJLh7 krx9hQFh4HhKvMfRRp3wDT/rDk1623km8MTghWNB+DeVEoEb7YLz4k1q3VOICaDNKKEB lsuHnKu1lhnMjrY2T2lUPI9gjtnfxmqhXmRM1CXu89vO3T4qFCFfc6Y2iANU2JCrL1Ux GtvzQOOy51uHSlGj3lH3RrUMD/KIdGA3oMYA3+CJRjnPlYFxT23V281Y4HrlVTM5bhOQ +AHqNujRMlAwfjOi+qJtdjQXCIuu+ZmVGMouWxseYX9WtqXjnyQn/v1tMXw+pDVD+z4O bS5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Go52RyLr599mBvLq+RmbiVaK0sm0+xrVqrOqv+d33DY=; b=pksuDtjw7Z8DiJ33hgfm0+d4ADkCKJpkcfLG+kGsiCDLzYd4HPcmnowbFqHudhwIqe UqrF4SWwRt+5ZkLo6aqsSgsCkBspZjaNzaX4USHO1ok1Y+Sg0OH27IuPjyF9Fo8dzDwF 4ChnW4raTqYmPZHLdCZSCydWp+Eq/Hsi55tKsr5qR0PO3NGXwrc6ydIRZhwqmfExCfjK fHlLh6KdcYuQAXpV3piOFzUJ+nMFfxF0gHwGFbrlkYIRpgeUgZ0FyoWktAmx2Nw6/8le M5DEoGDBDDQcmCXrJdBFTuC0110TCvbmKr+FbPvNcSXH38X4BruiprXAHSep/Gpa+A8y v/tw== X-Gm-Message-State: AFqh2kpKcRvujPTOh1TEkYHGHLNaWIzLM5MxCBboJgKGHp+7JU9vE7FN 1Goajhc/njHKlr3zyAkrFZj/Ljc6BNR49h3s X-Google-Smtp-Source: AMrXdXswl+D8clLzRT0WQt0xWXZtx0+Ai+qlHXvQTVfY8h2zTQFbt9K2XjDsEFp5O1yl5PyJSdcRvA== X-Received: by 2002:a62:19cb:0:b0:58d:b2eb:86ef with SMTP id 194-20020a6219cb000000b0058db2eb86efmr24742583pfz.9.1674518455493; Mon, 23 Jan 2023 16:00:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 05/22] target/arm: SCR_EL3.NS may be RES1 Date: Mon, 23 Jan 2023 14:00:10 -1000 Message-Id: <20230124000027.3565716-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518710245100001 Content-Type: text/plain; charset="utf-8" With RME, SEL2 must also be present to support secure state. The NS bit is RES1 if SEL2 is not present. Signed-off-by: Richard Henderson --- target/arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 293f8eda8c..783b675bd1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1853,6 +1853,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) } if (cpu_isar_feature(aa64_sel2, cpu)) { valid_mask |=3D SCR_EEL2; + } else if (cpu_isar_feature(aa64_rme, cpu)) { + /* With RME and without SEL2, NS is RES1. */ + value |=3D SCR_NS; } if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |=3D SCR_ATA; --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674518729; cv=none; d=zohomail.com; s=zohoarc; b=N+ny5eBNrSkHnCr+8ABNdNHxcJesEzNC34oHhzv1lgbFxHD74cYLvgt994HizBSzFRrowAehkSCHy7yVTumoFVpEl10L8gyJDq2oZ4ZQ9MjTki7siNEJ30bEjKn0lNaIzVhTN+dEaNTA6+UWxctn1EJE2G+YX2nb3UV4qHlMHeU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674518729; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=F6JnjYYyfWuQ76nLJMJggCd96mltrDtBeLHdFG+/fn0=; b=Cuu+LCO+MztztG4fOGW0AJnmr+KAP8qp6tczqSmdE2T5iMRzBf/hB4Ycuz7e6kzpXNo1A5sWmv7JjlGZaB7fQGpNX/GrPH7odNQUBOGMcCa6SFgvj1LZap/bFGae0G6Yim33Czkvxf9nnmPNv5tOmq3n/bpCwBCoAN4ne8LWPeo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674518729868454.63187933118274; Mon, 23 Jan 2023 16:05:29 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pK6kK-0008UX-Km; Mon, 23 Jan 2023 19:01:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK6kG-0008BZ-T0 for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:01 -0500 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK6kD-0001qX-Um for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:00 -0500 Received: by mail-pg1-x52e.google.com with SMTP id b12so10242130pgj.6 for ; Mon, 23 Jan 2023 16:00:57 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.00.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:00:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F6JnjYYyfWuQ76nLJMJggCd96mltrDtBeLHdFG+/fn0=; b=ZH8SXapeW/ubErkQQ/SgQzs5hDrtcJWJfftxwX/CkHCCVYrX5vQB0t8gC/wBtMPHHf SNBoSM0YMU7KABdhHyd4XQiIEhhQYRuW+489A5RVdeSSU8N8MC0GOYiXIva9AeR5wvMr HmL3EveaJzWy01eomOF3Q5kRftrPUFkHJYukrZQV7j9G8YsqKg7aHWR329/Xo6hvMY7X Dp9PTRAIDfz3G0su1RNQGyaa4UtU0SnLm7XOtoHx5m/nxte+qIcY/FG/NW1a3kc7dIAv gTio2B9N9hpf4wAb1Q47xfXAeInwKzQRWn5mYYrnOHXV4y83HSC0cf2OyOPR3RpMdDNf 1Hig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F6JnjYYyfWuQ76nLJMJggCd96mltrDtBeLHdFG+/fn0=; b=jvUR/jfmfrMjzfLt2wal633npgWwVoKyHbEcQtaOvbc/C7qQ2ridF1YgwEG0VGhOtI HTxsZYWLfcejxDWef7E/PlJ0kYPpNsXlifgA+e8846xr0z63fYTKLpUb7tk2pYXCbTuv MtQcSwfvIVBBemAtCQL03IElGIwkbfj76heN1tbHfyXeFGhsiCEkKkh+wmizJNIJyIuN CUJLX1f0vzoAMwNxZ3/vNt973ydAim6XoQ1DS4WlXsTOjpsCNph+w4xBC+o7DCi/18tT 3r/Ym7mzhMCXCAix1UxmpLYR0KLAh53E9m6MEQfM38yHy2XMNjTFOkOOKM0VtYEFWdEg 8KEA== X-Gm-Message-State: AFqh2kopa8KVWInHNVYtrYmw4Io3PcBzhcXz9Jmj2A9tBl8nOa9Jc8cD tIX0st197Tq9FhfNJHd0bPpb9ny9+5CSdg1X X-Google-Smtp-Source: AMrXdXvkr9lM4IVWPoBbZZlENOkGazotbBHESV8Y0+V2WgsZaTEr8gfkB18GnTSs5zKEAHSyP1Z5Tg== X-Received: by 2002:a05:6a00:190e:b0:58b:c1a1:4006 with SMTP id y14-20020a056a00190e00b0058bc1a14006mr32861709pfi.18.1674518457191; Mon, 23 Jan 2023 16:00:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 06/22] target/arm: Add RME cpregs Date: Mon, 23 Jan 2023 14:00:11 -1000 Message-Id: <20230124000027.3565716-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518730336100001 Content-Type: text/plain; charset="utf-8" This includes GPCCR, GPTBR, MFAR, the TLB flush insns PAALL, PAALLOS, RPALOS, RPAOS, and the cache flush insn CIPAPA. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 19 ++++++++++++ target/arm/helper.c | 74 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 93 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9d1a6b346d..26bdd6e465 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -529,6 +529,11 @@ typedef struct CPUArchState { uint64_t disr_el1; uint64_t vdisr_el2; uint64_t vsesr_el2; + + /* RME registers */ + uint64_t gpccr_el3; + uint64_t gptbr_el3; + uint64_t mfar_el3; } cp15; =20 struct { @@ -1031,6 +1036,7 @@ struct ArchCPU { uint64_t reset_cbar; uint32_t reset_auxcr; bool reset_hivecs; + uint8_t reset_l0gptsz; =20 /* * Intermediate values used during property parsing. @@ -2324,6 +2330,19 @@ FIELD(MVFR1, SIMDFMAC, 28, 4) FIELD(MVFR2, SIMDMISC, 0, 4) FIELD(MVFR2, FPMISC, 4, 4) =20 +FIELD(GPCCR, PPS, 0, 3) +FIELD(GPCCR, IRGN, 8, 2) +FIELD(GPCCR, ORGN, 10, 2) +FIELD(GPCCR, SH, 12, 2) +FIELD(GPCCR, PGS, 14, 2) +FIELD(GPCCR, GPC, 16, 1) +FIELD(GPCCR, GPCP, 17, 1) +FIELD(GPCCR, L0GPTSZ, 20, 4) + +FIELD(MFAR, FPA, 12, 40) +FIELD(MFAR, NSE, 62, 1) +FIELD(MFAR, NS, 63, 1) + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=3D R_V7M_CSSELR_INDE= X_MASK); =20 /* If adding a feature bit which corresponds to a Linux ELF diff --git a/target/arm/helper.c b/target/arm/helper.c index 783b675bd1..7bd15e9d17 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6848,6 +6848,77 @@ static const ARMCPRegInfo sme_reginfo[] =3D { .access =3D PL2_RW, .accessfn =3D access_esm, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; + +static void tlbi_aa64_paall_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + + tlb_flush(cs); +} + +static void gpccr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* L0GPTSZ is RO; other bits not mentioned are RES0. */ + uint64_t rw_mask =3D R_GPCCR_PPS_MASK | R_GPCCR_IRGN_MASK | + R_GPCCR_ORGN_MASK | R_GPCCR_SH_MASK | R_GPCCR_PGS_MASK | + R_GPCCR_GPC_MASK | R_GPCCR_GPCP_MASK; + + env->cp15.gpccr_el3 =3D (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw= _mask); +} + +static void gpccr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + env->cp15.gpccr_el3 =3D FIELD_DP64(0, GPCCR, L0GPTSZ, + env_archcpu(env)->reset_l0gptsz); +} + +static void tlbi_aa64_paallos_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + + tlb_flush_all_cpus_synced(cs); +} + +static const ARMCPRegInfo rme_reginfo[] =3D { + { .name =3D "GPCCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 6, + .access =3D PL3_RW, .writefn =3D gpccr_write, .resetfn =3D gpccr_res= et, + .fieldoffset =3D offsetof(CPUARMState, cp15.gpccr_el3) }, + { .name =3D "GPTBR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 4, + .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.gptb= r_el3) }, + { .name =3D "MFAR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 6, .crm =3D 0, .opc2 =3D 5, + .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mfar= _el3) }, + { .name =3D "TLBI_PAALL", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 4, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_paall_write }, + { .name =3D "TLBI_PAALLOS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 4, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_paallos_write }, + /* + * QEMU does not have a way to invalidate by physical address, thus + * invalidating a range of physical addresses is accomplished by + * flushing all tlb entries in the outer sharable domain, + * just like PAALLOS. + */ + { .name =3D "TLBI_RPALOS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 4, .opc2 =3D 7, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_paallos_write }, + { .name =3D "TLBI_RPAOS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 4, .opc2 =3D 3, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_paallos_write }, + { .name =3D "DC_CIPAPA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NOP }, +}; #endif /* TARGET_AARCH64 */ =20 static void define_pmu_regs(ARMCPU *cpu) @@ -8915,6 +8986,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_tlbios, cpu)) { define_arm_cp_regs(cpu, tlbios_reginfo); } + if (cpu_isar_feature(aa64_rme, cpu)) { + define_arm_cp_regs(cpu, rme_reginfo); + } #ifndef CONFIG_USER_ONLY /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674518546; cv=none; d=zohomail.com; s=zohoarc; b=jM6fDUm3go6POQO9Ffc89X7BgotsMHfL705lk+e7GA5DaPMV/DYTPHGqBlsi+Lm8REFoOgZYAO0aY3q1Mv7RKqryURzSdtAatzbp/SmuFVAO++iWsPXhf7X9gIN/KCs9SuWYUt0B9kZtA0ZOBkBCN3UuX1PfUN3/e6+iO+NiqnY= ARC-Message-Signature: i=1; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.00.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:00:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4r5uXH4L8nGIwtYKHW9rJtEDV6tOU9ZjQj8r0cJYWOU=; b=rQc7qOHEqwS03yHpuF5src3a9lAbce51K6d4Cg2WlB4GXvIyTMDCU15R+EWI9UyQ1T xB/WjzWRE1WHUvk7bdcL5XY+xK/s0ikw23n+zJc38rjEEp31c+TsCi7ElnzF9ObjpwNe 5mlPP7cuFKgvQ1/zmlBiUIDq7nd8bQ/t71i7jrrGwXdKjUw7qONYSElZVhjejRayttbM WbV8ZhtJqR9q4y5g2Wp8eL6HVdhvydE7+3jVF6p4bm5H4D8M5I7XCRmG3cQL4XX8aqIU Tn1iJu1764njs0IBdpeHwlpdmguG5729n1XRQAHwv/Aa7avDMcvmwCLIpxtVleR+22fF nnTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4r5uXH4L8nGIwtYKHW9rJtEDV6tOU9ZjQj8r0cJYWOU=; b=g3xXO4SFxJc6PlTVFM+pyr2uavpVro9Yb0sgsiJGZFHwnCH8IIvDkNggvO2VmxY/WT jUUZ1qhkaI68gFXp+neTMHTEXZjyMo4xtjE4Gx7FIRzbwc+faJXD/AfoA2jeUT9YU0+y C9Ob5cfEUiIT4YxStIXU7UBnf14MSC90m0MbzyFsfd0vDLqtZ+hF5eVK0GcVkc+sOto/ AJaiv7Te9bQ9GaHdxxF9b/GEN8f4c2vqPMxbzwd1cRZ3cxdSLrwa2nm91X8bQOZknDI8 NJI5FPZU98ZiyszoiMOJSc0nlPjfPU3hG5fXZKr3Bp+B34CnU39y5yd/oflj9NmkhWc2 142g== X-Gm-Message-State: AFqh2krejApCBlNbsfzFX3hue35MtzhPFklbWcHTYToIqRa0IuTCIAIs k8NXK8z1EYa3czXIM1xppUJUycjiLM4W/IAF X-Google-Smtp-Source: AMrXdXvVx+r7aR9A3S8fbgCG/8YogtkAE9PpcxB/e+/zdl4AwX/E3l8gvMMQC+pcW1LsM/A0aHt59g== X-Received: by 2002:a05:6a00:26cc:b0:589:62bd:14d with SMTP id p12-20020a056a0026cc00b0058962bd014dmr25668975pfw.1.1674518458914; Mon, 23 Jan 2023 16:00:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 07/22] target/arm: Introduce ARMSecuritySpace Date: Mon, 23 Jan 2023 14:00:12 -1000 Message-Id: <20230124000027.3565716-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518547583100009 Content-Type: text/plain; charset="utf-8" Introduce both the enumeration and functions to retrieve the current state, and state outside of EL3. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 87 +++++++++++++++++++++++++++++++++++---------- target/arm/helper.c | 46 ++++++++++++++++++++++++ 2 files changed, 115 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 26bdd6e465..cfc62d60b0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2397,23 +2397,53 @@ static inline int arm_feature(CPUARMState *env, int= feature) =20 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); =20 +/* + * ARM v9 security states. + * The ordering of the enumeration corresponds to the low 2 bits + * of the GPI value, and (except for Root) the concat of NSE:NS. + */ + +typedef enum ARMSecuritySpace { + ARMSS_Secure =3D 0, + ARMSS_NonSecure =3D 1, + ARMSS_Root =3D 2, + ARMSS_Realm =3D 3, +} ARMSecuritySpace; + +/* Return true if @space is secure, in the pre-v9 sense. */ +static inline bool arm_space_is_secure(ARMSecuritySpace space) +{ + return space =3D=3D ARMSS_Secure || space =3D=3D ARMSS_Root; +} + +/* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ +static inline ARMSecuritySpace arm_secure_to_space(bool secure) +{ + return secure ? ARMSS_Secure : ARMSS_NonSecure; +} + #if !defined(CONFIG_USER_ONLY) -/* Return true if exception levels below EL3 are in secure state, - * or would be following an exception return to that level. - * Unlike arm_is_secure() (which is always a question about the - * _current_ state of the CPU) this doesn't care about the current - * EL or mode. +/** + * arm_security_space_below_el3: + * @env: cpu context + * + * Return the security space of exception levels below EL3, following + * an exception return to those levels. Unlike arm_security_space, + * this doesn't care about the current EL. + */ +ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); + +/** + * arm_is_secure_below_el3: + * @env: cpu context + * + * Return true if exception levels below EL3 are in secure state, + * or would be following an exception return to those levels. */ static inline bool arm_is_secure_below_el3(CPUARMState *env) { - if (arm_feature(env, ARM_FEATURE_EL3)) { - return !(env->cp15.scr_el3 & SCR_NS); - } else { - /* If EL3 is not supported then the secure state is implementation - * defined, in which case QEMU defaults to non-secure. - */ - return false; - } + ARMSecuritySpace ss =3D arm_security_space_below_el3(env); + return ss =3D=3D ARMSS_Secure; } =20 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ @@ -2432,13 +2462,24 @@ static inline bool arm_is_el3_or_mon(CPUARMState *e= nv) return false; } =20 -/* Return true if the processor is in secure state */ +/** + * arm_security_space: + * @env: cpu context + * + * Return the current security space of the cpu. + */ +ARMSecuritySpace arm_security_space(CPUARMState *env); + +/** + * arm_is_secure: + * @env: cpu context + * + * Return true if the processor is in secure state. + */ static inline bool arm_is_secure(CPUARMState *env) { - if (arm_is_el3_or_mon(env)) { - return true; - } - return arm_is_secure_below_el3(env); + ARMSecuritySpace ss =3D arm_security_space(env); + return ss =3D=3D ARMSS_Secure || ss =3D=3D ARMSS_Root; } =20 /* @@ -2457,11 +2498,21 @@ static inline bool arm_is_el2_enabled(CPUARMState *= env) } =20 #else +static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *e= nv) +{ + return ARMSS_NonSecure; +} + static inline bool arm_is_secure_below_el3(CPUARMState *env) { return false; } =20 +static inline ARMSecuritySpace arm_security_space(CPUARMState *env) +{ + return ARMSS_NonSecure; +} + static inline bool arm_is_secure(CPUARMState *env) { return false; diff --git a/target/arm/helper.c b/target/arm/helper.c index 7bd15e9d17..bf78a1d74e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12280,3 +12280,49 @@ void aarch64_sve_change_el(CPUARMState *env, int o= ld_el, } } #endif + +#ifndef CONFIG_USER_ONLY +ARMSecuritySpace arm_security_space(CPUARMState *env) +{ + if (!arm_feature(env, ARM_FEATURE_EL3)) { + return ARMSS_NonSecure; + } + + /* Check for AArch64 EL3 or AArch32 Mon. */ + if (is_a64(env)) { + if (extract32(env->pstate, 2, 2) =3D=3D 3) { + if (cpu_isar_feature(aa64_rme, env_archcpu(env))) { + return ARMSS_Root; + } else { + return ARMSS_Secure; + } + } + } else { + if ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_MON) { + return ARMSS_Secure; + } + } + + return arm_security_space_below_el3(env); +} + +ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) +{ + if (!arm_feature(env, ARM_FEATURE_EL3)) { + return ARMSS_NonSecure; + } + + /* + * Note NSE cannot be set without RME, and NSE & !NS is Reserved. + * Ignoring NSE when !NS retains consistency without having to + * modify other predicates. + */ + if (!(env->cp15.scr_el3 & SCR_NS)) { + return ARMSS_Secure; + } else if (env->cp15.scr_el3 & SCR_NSE) { + return ARMSS_Realm; + } else { + return ARMSS_NonSecure; + } +} +#endif /* !CONFIG_USER_ONLY */ --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.00.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:01:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hj6fBvSPjNRviyD+eR3MkAKCd+tfeKUJy3fWTvfYgwY=; b=BGdh8dm0A9s++gnulw9hROu3U99ekSdAjcUzLmC8vhV3gqwUJkezUB1K8pOe4pEQ+M NxzMWv6yx0tMmYiOT+KkzWTlGIzj2XHCcdY91h/19m0LICv0kbI1oDUz5Qmd2WXvHmtw g1shKs/klfNr6hRgAio6tSoB+RBojHRj7OIVVq+ZYutXD4MD2wYqnBQ8m0ExfNLPC3UV vq7+fR4GEyUDYI7zD9M/SUndgE3W8yRERedkMSvBHteoIVW78ege5efpe4xdxtV11Xeb Ef/UNSeEIcXw8mi2QQZ5pX87Dyhxc/rjAG9XIXGlBWesVo8UQctFLmweHmDzUsqsg/Hf qvbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hj6fBvSPjNRviyD+eR3MkAKCd+tfeKUJy3fWTvfYgwY=; b=ROdNU07HwglqbuWx6M8HzlBF7G/XD+b6l1Sr0mw4hthxSSHwFxgTp/NqhKPKrSmRS1 5R6eMh5inx413rpTLQdqouR9idunVYn8pcdALt3OLuqnJXRNajCa6nKi1r8xm011jaOt N/YRNXDr9uqVQJHYevTkPDxUYPRbwz79VugTveQtRbhqY/fhCKja2y8oLIWrbqHkbwRN CXTrMkR53LXe7RuFwMReY9bQTIajAaz1arWVeG6fgJC4yH43X3eKZPAeDn5QxnsQKm9a //MnZJhVGW+O6yDbLNuG6YD0emKNl5erMrVIjciXWoah2l8EmADoXKm2SdwHpTSdUFJP JXhg== X-Gm-Message-State: AFqh2kpV5WP5Q1vlL9tPvKGwGQpVninVeNGO9Ek2zx6gBebNz06gGoJM NLeqUqfdyuH4hvr5eyQ0PGcQBS27OeQjUX+V X-Google-Smtp-Source: AMrXdXtbfR00rbgO8nEVC8fDvBjRdpdBwgKEPIpIfhj/Fu105eEJasrp7H3bxwfvaZyOhw3D5VC6vg== X-Received: by 2002:a62:4e07:0:b0:588:89bc:7f75 with SMTP id c7-20020a624e07000000b0058889bc7f75mr26183980pfb.1.1674518460536; Mon, 23 Jan 2023 16:01:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 08/22] include/exec/memattrs: Add two bits of space to MemTxAttrs Date: Mon, 23 Jan 2023 14:00:13 -1000 Message-Id: <20230124000027.3565716-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518501376100001 Content-Type: text/plain; charset="utf-8" We will need 2 bits to represent ARMSecurityState. Do not attempt to replace or widen secure, even though it logically overlaps the new field -- there are uses within e.g. hw/block/pflash_cfi01.c, which don't know anything specific about ARM. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- include/exec/memattrs.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 9fb98bc1ef..d04170aa27 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -29,10 +29,17 @@ typedef struct MemTxAttrs { * "didn't specify" if necessary. */ unsigned int unspecified:1; - /* ARM/AMBA: TrustZone Secure access + /* + * ARM/AMBA: TrustZone Secure access * x86: System Management Mode access */ unsigned int secure:1; + /* + * ARM: ArmSecuritySpace. This partially overlaps secure, but it is + * easier to have both fields to assist code that does not understand + * ARMv9 RME, or no specific knowledge of ARM at all (e.g. pflash). + */ + unsigned int space:2; /* Memory access is usermode (unprivileged) */ unsigned int user:1; /* --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674518530; cv=none; d=zohomail.com; s=zohoarc; b=M3cZadohHlURgEl1nCfquYWFqoFPT0XK2lUp5Tw3TlLlgFbSZewbjiZcXKiH0MzGgTc/k1loEFfPmpJJ9aUDioaeZA3lIRNMpYVHlR4hotBc902Yd84qExoXcMlFsYYzmBsm2/WrTnbgx18zreuZJvom0+JvHd9K7ma+VxzQivQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674518530; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zT9ks933YUCHx0wzfAy0gOfp0dAuk0lKbcEhOOr94PI=; b=eBI3CpsTwAjqAu6v9kNnPNkgWmBhUgsVc9pLVmMIm0QcWUdPnuRLN+/l2wch21iep4j6cKM6ma7CdUYdOGNk1wJqllxUkxLq2eXPb+u6OAasOBidrWdMFcEYS9uCCJ8ZtLgR8ZHzYsD9ojJZs++sFsWdhvRfycUjcB7/62Bo+2Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674518530885688.0547043379524; Mon, 23 Jan 2023 16:02:10 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pK6kM-0000HA-Ss; Mon, 23 Jan 2023 19:01:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK6kL-0000BU-P2 for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:05 -0500 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK6kJ-0001td-Mg for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:05 -0500 Received: by mail-pg1-x535.google.com with SMTP id d10so10220361pgm.13 for ; Mon, 23 Jan 2023 16:01:03 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.01.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:01:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zT9ks933YUCHx0wzfAy0gOfp0dAuk0lKbcEhOOr94PI=; b=GgE/umvEtUJcw0PutPqsQC1Z4PPOlEnJxBjuXLX7wEn9Kf3Y1DHfxqq9x+lf//IaVr ciQvabzZXJegZ9Rl9yPTFMWcK0hJtAmZE6T0hprtUjOD4TMaVcaNjGcmqQ/7RG6p5vOE X9+knOAfs2nwEVW2KNJY1ywtC+/81QJbOuAjJM7aEX4YDmVbym1f0/pOSrYSUkkV5aB1 tdnMDFMVI8BPt2QCxMD7uEoH89/XD5LpSRUNiRMfAPDYtnBWjvzwWAXpfCmDU5c2+QuW oE7BsBXIWvZ6pQASmULUggJwbUMOLTkDM2BnrxTZfFzTV8qANi6OYqsfdcExqWPsuXf/ PZIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zT9ks933YUCHx0wzfAy0gOfp0dAuk0lKbcEhOOr94PI=; b=paNCucVW1vJiA4Hq1++4slaoW6HQLUMvTLNI4l+6/hvLHBLGpvhG6xLEKGwPqaymkt /ePFJWI8iblH5CZ3Vxnx+TUmUrWEkgP9HncVBQB5hvPvU8Kt5n2o3J674I2nIc122Jtw 3eIUihWk/wu33OKYXF40RHCVA8RcZDUtD/nh83dMRb22ydHuwQKwIjtulbHvjA9qCe+A YGTFUtQxzvMjRXI/T32pEf866+My0jE6ENx8cc3mvkSQghfyQhuh0r/URHIYHHDLY56e h/Uie7vH0xu5LfrWFqX/+rqa4oD3cIqn3vYjAMuz5LUA1DmwP82kTxjlpK+ZMgZGiSS8 OFAQ== X-Gm-Message-State: AFqh2krhneAgS57dcC4zkO7Pb0Unzu0dA9CgSlfk3B3ZzQEZ2zULwuzE 9XBG5qDRvYfbAFV3sQZqMO9MgByJpHo6DQnR X-Google-Smtp-Source: AMrXdXvuASAF5oodau2Cxma7+PKmy3J8xaqonLm6sR17ZfO2C6l4Fq1jXOgt88poGuVCmCJpWrPFTg== X-Received: by 2002:a62:1751:0:b0:56b:3758:a2d9 with SMTP id 78-20020a621751000000b0056b3758a2d9mr27115102pfx.21.1674518462315; Mon, 23 Jan 2023 16:01:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 09/22] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx Date: Mon, 23 Jan 2023 14:00:14 -1000 Message-Id: <20230124000027.3565716-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518531462100001 Content-Type: text/plain; charset="utf-8" It will be helpful to have ARMMMUIdx_Phys_* to be in the same relative order as ARMSecuritySpace enumerators. This requires the adjustment to the nstable check. While there, check for being in secure state rather than rely on clearing the low bit making no change to non-secure state. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 12 ++++++------ target/arm/ptw.c | 10 ++++------ 2 files changed, 10 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cfc62d60b0..0114e1ed87 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3057,18 +3057,18 @@ typedef enum ARMMMUIdx { ARMMMUIdx_E2 =3D 6 | ARM_MMU_IDX_A, ARMMMUIdx_E3 =3D 7 | ARM_MMU_IDX_A, =20 - /* TLBs with 1-1 mapping to the physical address spaces. */ - ARMMMUIdx_Phys_NS =3D 8 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_S =3D 9 | ARM_MMU_IDX_A, - /* * Used for second stage of an S12 page table walk, or for descriptor * loads during first stage of an S1 page table walk. Note that both * are in use simultaneously for SecureEL2: the security state for * the S2 ptw is selected by the NS bit from the S1 ptw. */ - ARMMMUIdx_Stage2 =3D 10 | ARM_MMU_IDX_A, - ARMMMUIdx_Stage2_S =3D 11 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2_S =3D 8 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2 =3D 9 | ARM_MMU_IDX_A, + + /* TLBs with 1-1 mapping to the physical address spaces. */ + ARMMMUIdx_Phys_S =3D 10 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_NS =3D 11 | ARM_MMU_IDX_A, =20 /* * These are not allocated TLBs and are used only for AT system diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 437f6fefa9..59cf64d0a6 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1410,16 +1410,14 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, descaddr |=3D (address >> (stride * (4 - level))) & indexmask; descaddr &=3D ~7ULL; nstable =3D extract32(tableattrs, 4, 1); - if (nstable) { + if (nstable && ptw->in_secure) { /* * Stage2_S -> Stage2 or Phys_S -> Phys_NS * Assert that the non-secure idx are even, and relative order. */ - QEMU_BUILD_BUG_ON((ARMMMUIdx_Phys_NS & 1) !=3D 0); - QEMU_BUILD_BUG_ON((ARMMMUIdx_Stage2 & 1) !=3D 0); - QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS + 1 !=3D ARMMMUIdx_Phys_S); - QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2 + 1 !=3D ARMMMUIdx_Stage2_S); - ptw->in_ptw_idx &=3D ~1; + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_S + 1 !=3D ARMMMUIdx_Phys_NS); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 !=3D ARMMMUIdx_Stage2); + ptw->in_ptw_idx +=3D 1; ptw->in_secure =3D false; } if (!S1_ptw_translate(env, ptw, descaddr, fi)) { --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674518505; cv=none; d=zohomail.com; s=zohoarc; b=CO4uZCi31RhNNDEDggCpe6jSD8xGddDUKg6xvQHkoYH8yUty31wWxd6waXz4xM3ETTaS9rbtvzNqaWNiHrM7jlktDSfgiC34mox//8AeoTvMtzwDRfxS8w5/YBJIcAb9lT3o9Aow6j4Axq/3M5OwrWlZrrc/Sqapd52dTuiYeyY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674518505; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=M9rvIn/r4gTk2g6Wh4QamIsNWYaqsyCXrvrErQwB2/A=; b=loaVSdl86gLWLfttawGiqegYK7+MneLQhTSYrtO1nEvX+SZRM2PQJ1dW2xvRyLn3BW/YYS+gEX0pIQwW15JE/gYOotqN89SijUKCOpG+e1sRoa2XU63mhPYAMxrUWIB/aCZunVTAP32b9YomLMk0Bdyov0sG9zZ3hUOrxtFhX3M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674518505276641.7469086853242; Mon, 23 Jan 2023 16:01:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pK6kP-0000Qy-Or; Mon, 23 Jan 2023 19:01:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK6kO-0000Ns-4R for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:08 -0500 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK6kL-0001uO-AA for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:07 -0500 Received: by mail-pg1-x52d.google.com with SMTP id d10so10220420pgm.13 for ; Mon, 23 Jan 2023 16:01:04 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.01.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:01:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=M9rvIn/r4gTk2g6Wh4QamIsNWYaqsyCXrvrErQwB2/A=; b=CdJI//h/XGjUavbRSiEhpoBZ9TOuVC/w0h1hXXeSuZjghGtZp/1p0hQsL+zJqL6Jmp wu8kuIQwrSkd0iK2ubUVV6B4++5MMs6IMYjbsz6Kc9f2HqxwRTuLJI5bC6vh+K0kiIFY q/uNQZxzl50ut+5lWf5SGNFHfr5/a5k2m7+kc7/dCcetp5MkGIC+Bquffta1OCOqZ2EU lDa0f+FKjylDipukxQ1iCWkyrNqQ+aF5Dl6lhUdQbmz63AhiN5+paXbkd1CTvMp8ea74 cogrSo+pwh7C815EF+vRsK0Ej1EfAkcLztQ3Z3sZWM4DaamPv0Iedr17WnktAsU82PsT Av5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M9rvIn/r4gTk2g6Wh4QamIsNWYaqsyCXrvrErQwB2/A=; b=pphAy4OsrqG1cCY1B0C+sgogV8Uyk/kUDZK/WFnerEuudodT0dfPvAgV58oggFxfix bgMyzbLp5Arbo2yv85Yy/u3q6cl7k3ZiY4ZqbRXff5/11TmGRHGuqXeH7/TKYW4fcPnB WmZAL06XI5g4VztnjgBz+MyxZkpPOMiG+TnI/YtxoIsolYnK4P/BrdoaSBQrGYLAQEcw sI1wf46hlU34ZdrN2Gd064dTmXgfM0JNWZfD0dv98+WCy2y1jb6G8By/6Efm0MlRH+B7 RiktpSlwyiEq2mPY4gPq9l6F8m/i6S7E+mz52VIiSnKG6iFFKhYQ79NPPXx38YHcu8Kt fpdg== X-Gm-Message-State: AFqh2krMh/sXTAD3T89kwtTDfS/kCQWtCMH0Crcr7EUXPe/BNY7URFjo o4FL5I8WZsZ5mSpch7Gv+aoVwTvU4aqYzgu7 X-Google-Smtp-Source: AMrXdXs71EZv9CSKvk4hxMOi8A0tsl8H+YbmyZJo8itSVyej2GbXXnfeCqAhf/GwH2TETWfB6+DyZw== X-Received: by 2002:aa7:9892:0:b0:583:4126:a09 with SMTP id r18-20020aa79892000000b0058341260a09mr26122410pfl.21.1674518463977; Mon, 23 Jan 2023 16:01:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 10/22] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root} Date: Mon, 23 Jan 2023 14:00:15 -1000 Message-Id: <20230124000027.3565716-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518507383100003 Content-Type: text/plain; charset="utf-8" With FEAT_RME, there are four physical address spaces. For now, just define the symbols, and mention them in the same spots as the other Phys indexes in ptw.c. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 17 +++++++++++++++-- target/arm/ptw.c | 10 ++++++++-- 3 files changed, 24 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 53cac9c89b..8dfd7a0bb6 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -47,6 +47,6 @@ bool guarded; #endif =20 -#define NB_MMU_MODES 12 +#define NB_MMU_MODES 14 =20 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0114e1ed87..21b9afb773 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3067,8 +3067,10 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage2 =3D 9 | ARM_MMU_IDX_A, =20 /* TLBs with 1-1 mapping to the physical address spaces. */ - ARMMMUIdx_Phys_S =3D 10 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_NS =3D 11 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_S =3D 10 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_NS =3D 11 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_Root =3D 12 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_Realm =3D 13 | ARM_MMU_IDX_A, =20 /* * These are not allocated TLBs and are used only for AT system @@ -3132,6 +3134,17 @@ typedef enum ARMASIdx { ARMASIdx_TagS =3D 3, } ARMASIdx; =20 +static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) +{ + return ARMMMUIdx_Phys_S + space; +} + +static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) +{ + assert(idx >=3D ARMMMUIdx_Phys_S && idx <=3D ARMMMUIdx_Phys_Realm); + return idx - ARMMMUIdx_Phys_S; +} + static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) { /* If all the CLIDR.Ctypem bits are 0 there are no caches, and diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 59cf64d0a6..49b8895a4e 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -182,8 +182,10 @@ static bool regime_translation_disabled(CPUARMState *e= nv, ARMMMUIdx mmu_idx, case ARMMMUIdx_E3: break; =20 - case ARMMMUIdx_Phys_NS: case ARMMMUIdx_Phys_S: + case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_Root: + case ARMMMUIdx_Phys_Realm: /* No translation for physical address spaces. */ return true; =20 @@ -2632,8 +2634,10 @@ static bool get_phys_addr_disabled(CPUARMState *env,= target_ulong address, switch (mmu_idx) { case ARMMMUIdx_Stage2: case ARMMMUIdx_Stage2_S: - case ARMMMUIdx_Phys_NS: case ARMMMUIdx_Phys_S: + case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_Root: + case ARMMMUIdx_Phys_Realm: break; =20 default: @@ -2830,6 +2834,8 @@ static bool get_phys_addr_with_struct(CPUARMState *en= v, S1Translate *ptw, switch (mmu_idx) { case ARMMMUIdx_Phys_S: case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_Root: + case ARMMMUIdx_Phys_Realm: /* Checking Phys early avoids special casing later vs regime_el. */ return get_phys_addr_disabled(env, address, access_type, mmu_idx, is_secure, result, fi); --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674518808; cv=none; d=zohomail.com; s=zohoarc; b=fqpGQINcZowfhb5BGoXphLF3YAm2z2VPCpMJ9b+OunH5BEgsUNYg8qZpO5L/a0H3zh80TqowYBoiMEY1izHL+ZXcZpsEUNlhRxNS3HM4Ippk3pG4tbEA7j2mgYYpKF8tLOsBaDq5SxdKxR/fYweqjwtGSOkzJx7lu/DDduDQt10= ARC-Message-Signature: i=1; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.01.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:01:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OQK/NGma/IRTWGPFRFtlz4+fHNaKcqiMvwODZAjxqzA=; b=JOw4wgQVGlCE4gCZCxb89V8g49qAjyHFz2j5iYd93EIwaL7QjQSr2FfOLkty/u3Sov kxtzuCLidvAAFDlrVAgq/BfapZAq5lsO+pbwvXoKwpZLFpcvo30lctV6wYqRM7xFgxzV zX3ZcJKwfrwrJYFTPzPYGKTG45U4nn51o0+3IPJZYssM//yCVyTK6+wgvXg3T3jjuZ9W dQG4YmH07XYEDRHp1mufr/e2tNZF+Ba9QiQO0jcF2F4fS0XUqkVqEu3UhUWvHT3MBIC1 k7x/mEv+Df7AmsfyIzt4MIdXIMvCDrV8hwzwHeKsoMfAEIHFZmscyUf9rnuKiYf+nyxw KA1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OQK/NGma/IRTWGPFRFtlz4+fHNaKcqiMvwODZAjxqzA=; b=FWQVsPckv2rN6s70H8Ozc6pvLRvW2YyGqc+JvU2u4+15Zo07ZXhkfrXwi5gP95mfWJ GWViajvUtGlke4FobI5Eu6PHtwefMbi4HNxJC9ELEvaM5+nK6LZqNvZpffBYXJV8eFMI CJpuvRhhdl3VwSfU5B80+5Z75cue/+eYD2d9lLirCMJngF3YA9RI6nk11D4eLJTAVig1 RhW66eok5x3LurYhpGgS2vQIsEzwJ5f1AtToEPp7ApfGYfrsxm/4c1xOYUUm4Z1QbmS0 A57IkEW8/iQ5oS71BSGPJyf8wjJycav0oaS+xpubXC7OURTI15uQ66gTpM7LqRW/8yMj t2GQ== X-Gm-Message-State: AFqh2koG1b5miy8dsqrx2zIvZ7xD/vZiIznlX6aQLCTFwkTlP2NEE8F0 HwE8D7LLUF3qwj48DxW2PzpS3Yggt+vVd5Hc X-Google-Smtp-Source: AMrXdXvXelBLzChrZ6x8CrFR1MvIPmnhVM8bMKz5VlLqDnQUShZDnh22B5tH9mQhcIE/4oMI4hGxHQ== X-Received: by 2002:a62:1448:0:b0:58d:9588:890b with SMTP id 69-20020a621448000000b0058d9588890bmr31795568pfu.0.1674518465648; Mon, 23 Jan 2023 16:01:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 11/22] target/arm: Pipe ARMSecuritySpace through ptw.c Date: Mon, 23 Jan 2023 14:00:16 -1000 Message-Id: <20230124000027.3565716-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518808834100002 Content-Type: text/plain; charset="utf-8" Add input and output space members to S1Translate. Set and adjust them in S1_ptw_translate, and the various points at which we drop secure state. Initialize the space in get_phys_addr; for now leave get_phys_addr_with_secure considering only secure vs non-secure spaces. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 95 ++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 76 insertions(+), 19 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 49b8895a4e..c1b0b8e610 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -19,11 +19,13 @@ typedef struct S1Translate { ARMMMUIdx in_mmu_idx; ARMMMUIdx in_ptw_idx; + ARMSecuritySpace in_space; bool in_secure; bool in_debug; bool out_secure; bool out_rw; bool out_be; + ARMSecuritySpace out_space; hwaddr out_virt; hwaddr out_phys; void *out_host; @@ -218,6 +220,7 @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t a= ttrs) static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, hwaddr addr, ARMMMUFaultInfo *fi) { + ARMSecuritySpace space =3D ptw->in_space; bool is_secure =3D ptw->in_secure; ARMMMUIdx mmu_idx =3D ptw->in_mmu_idx; ARMMMUIdx s2_mmu_idx =3D ptw->in_ptw_idx; @@ -234,7 +237,8 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl= ate *ptw, if (regime_is_stage2(s2_mmu_idx)) { S1Translate s2ptw =3D { .in_mmu_idx =3D s2_mmu_idx, - .in_ptw_idx =3D is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_P= hys_NS, + .in_ptw_idx =3D arm_space_to_phys(space), + .in_space =3D space, .in_secure =3D is_secure, .in_debug =3D true, }; @@ -292,10 +296,17 @@ static bool S1_ptw_translate(CPUARMState *env, S1Tran= slate *ptw, } =20 /* Check if page table walk is to secure or non-secure PA space. */ - ptw->out_secure =3D (is_secure - && !(pte_secure + if (is_secure) { + bool out_secure =3D !(pte_secure ? env->cp15.vstcr_el2 & VSTCR_SW - : env->cp15.vtcr_el2 & VTCR_NSW)); + : env->cp15.vtcr_el2 & VTCR_NSW); + if (!out_secure) { + is_secure =3D false; + space =3D ARMSS_NonSecure; + } + } + ptw->out_secure =3D is_secure; + ptw->out_space =3D space; ptw->out_be =3D regime_translation_big_endian(env, mmu_idx); return true; =20 @@ -326,7 +337,10 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, S1Transl= ate *ptw, } } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs =3D { .secure =3D ptw->out_secure }; + MemTxAttrs attrs =3D { + .secure =3D ptw->out_secure, + .space =3D ptw->out_space, + }; AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; =20 @@ -369,7 +383,10 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Transl= ate *ptw, #endif } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs =3D { .secure =3D ptw->out_secure }; + MemTxAttrs attrs =3D { + .secure =3D ptw->out_secure, + .space =3D ptw->out_space, + }; AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; =20 @@ -875,6 +892,7 @@ static bool get_phys_addr_v6(CPUARMState *env, S1Transl= ate *ptw, * regime, because the attribute will already be non-secure. */ result->f.attrs.secure =3D false; + result->f.attrs.space =3D ARMSS_NonSecure; } result->f.phys_addr =3D phys_addr; return false; @@ -1579,6 +1597,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, * regime, because the attribute will already be non-secure. */ result->f.attrs.secure =3D false; + result->f.attrs.space =3D ARMSS_NonSecure; } =20 /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. = */ @@ -2363,6 +2382,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, */ if (sattrs.ns) { result->f.attrs.secure =3D false; + result->f.attrs.space =3D ARMSS_NonSecure; } else if (!secure) { /* * NS access to S memory must fault. @@ -2712,6 +2732,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, bool is_secure =3D ptw->in_secure; bool ret, ipa_secure, s2walk_secure; ARMCacheAttrs cacheattrs1; + ARMSecuritySpace ipa_space, s2walk_space; bool is_el0; uint64_t hcr; =20 @@ -2724,20 +2745,24 @@ static bool get_phys_addr_twostage(CPUARMState *env= , S1Translate *ptw, =20 ipa =3D result->f.phys_addr; ipa_secure =3D result->f.attrs.secure; + ipa_space =3D result->f.attrs.space; if (is_secure) { /* Select TCR based on the NS bit from the S1 walk. */ s2walk_secure =3D !(ipa_secure ? env->cp15.vstcr_el2 & VSTCR_SW : env->cp15.vtcr_el2 & VTCR_NSW); + s2walk_space =3D arm_secure_to_space(s2walk_secure); } else { assert(!ipa_secure); s2walk_secure =3D false; + s2walk_space =3D ipa_space; } =20 is_el0 =3D ptw->in_mmu_idx =3D=3D ARMMMUIdx_Stage1_E0; ptw->in_mmu_idx =3D s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Sta= ge2; - ptw->in_ptw_idx =3D s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_= NS; + ptw->in_ptw_idx =3D arm_space_to_phys(s2walk_space); ptw->in_secure =3D s2walk_secure; + ptw->in_space =3D s2walk_space; =20 /* * S1 is done, now do S2 translation. @@ -2825,11 +2850,12 @@ static bool get_phys_addr_with_struct(CPUARMState *= env, S1Translate *ptw, ARMMMUIdx s1_mmu_idx; =20 /* - * The page table entries may downgrade secure to non-secure, but - * cannot upgrade an non-secure translation regime's attributes - * to secure. + * The page table entries may downgrade secure to NonSecure, but + * cannot upgrade a NonSecure translation regime's attributes + * to Secure or Realm. */ result->f.attrs.secure =3D is_secure; + result->f.attrs.space =3D ptw->in_space; =20 switch (mmu_idx) { case ARMMMUIdx_Phys_S: @@ -2871,7 +2897,7 @@ static bool get_phys_addr_with_struct(CPUARMState *en= v, S1Translate *ptw, =20 default: /* Single stage and second stage uses physical for ptw. */ - ptw->in_ptw_idx =3D is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_= NS; + ptw->in_ptw_idx =3D arm_space_to_phys(ptw->in_space); break; } =20 @@ -2946,6 +2972,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, S1Translate ptw =3D { .in_mmu_idx =3D mmu_idx, .in_secure =3D is_secure, + .in_space =3D arm_secure_to_space(is_secure), }; return get_phys_addr_with_struct(env, &ptw, address, access_type, result, fi); @@ -2955,7 +2982,10 @@ bool get_phys_addr(CPUARMState *env, target_ulong ad= dress, MMUAccessType access_type, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { - bool is_secure; + S1Translate ptw =3D { + .in_mmu_idx =3D mmu_idx, + }; + ARMSecuritySpace ss; =20 switch (mmu_idx) { case ARMMMUIdx_E10_0: @@ -2968,30 +2998,55 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E2: - is_secure =3D arm_is_secure_below_el3(env); + ss =3D arm_security_space_below_el3(env); break; case ARMMMUIdx_Stage2: + /* + * For Secure EL2, we need this index to be NonSecure; + * otherwise this will already be NonSecure or Realm. + */ + ss =3D arm_security_space_below_el3(env); + if (ss =3D=3D ARMSS_Secure) { + ss =3D ARMSS_NonSecure; + } + break; case ARMMMUIdx_Phys_NS: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: case ARMMMUIdx_MUser: - is_secure =3D false; + ss =3D ARMSS_NonSecure; break; - case ARMMMUIdx_E3: case ARMMMUIdx_Stage2_S: case ARMMMUIdx_Phys_S: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: case ARMMMUIdx_MSUser: - is_secure =3D true; + ss =3D ARMSS_Secure; + break; + case ARMMMUIdx_E3: + if (arm_feature(env, ARM_FEATURE_AARCH64) && + cpu_isar_feature(aa64_rme, env_archcpu(env))) { + ss =3D ARMSS_Root; + } else { + ss =3D ARMSS_Secure; + } + break; + case ARMMMUIdx_Phys_Root: + ss =3D ARMSS_Root; + break; + case ARMMMUIdx_Phys_Realm: + ss =3D ARMSS_Realm; break; default: g_assert_not_reached(); } - return get_phys_addr_with_secure(env, address, access_type, mmu_idx, - is_secure, result, fi); + + ptw.in_space =3D ss; + ptw.in_secure =3D arm_space_is_secure(ss); + return get_phys_addr_with_struct(env, &ptw, address, access_type, + result, fi); } =20 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, @@ -2999,9 +3054,11 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *c= s, vaddr addr, { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; + ARMSecuritySpace ss =3D arm_security_space(env); S1Translate ptw =3D { .in_mmu_idx =3D arm_mmu_idx(env), - .in_secure =3D arm_is_secure(env), + .in_space =3D ss, + .in_secure =3D arm_space_is_secure(ss), .in_debug =3D true, }; GetPhysAddrResult res =3D {}; --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.01.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:01:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LUf95rwr1zmpxbrt8VlVK1sP2Ifcp9yoQEapeTzLdPY=; b=eX/lxgo3zg6dhSxlEM6WNjB9u3GhW1AB6yXByxuWPTTc3kCMCR+eEecJRy/zq1JAyl noPtNqdW67wExKtPo/Cq6beVXxCVrhI/w1rQ5e6bFDWr/uz8pA6w46UQN1yFuUOhRIB8 qFDfz4Oc5l6HsJscHHTOwwAnp1SXRRiiT5767Jc8j3BIOmOd2ZMnUV+RW/F1Z4yT34T/ XeyMt+a1xglwsQvAKDGlrkVNsUgQzwQg2Md488L8EhV+wwfzliqMlb2HIJPQdO3nTNXk 9cWOB9WSIUjZj4ED5prU1qIVRgnV4xiUiIhu6Dy6RIz4272xNl7hoMBXJZFrCWfHBika KBrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LUf95rwr1zmpxbrt8VlVK1sP2Ifcp9yoQEapeTzLdPY=; b=eWM4Hf+fDVzuZPW0TSuP6LKgUvli3eyBxHmjZHa/kUEEAaGwJgZFPGp8j1UuoUf104 CN7OZAtCdWBmtjfjLCO3+ktq0twugbConzjIYsrMbVZA8cDUfp0le13t5j64bKvd9JKx IH6oQaTDQJDRoqo817Jk24OQ7GZEhyJMp3qe6b0i9YoxIgg+1yEEtOecNLa4Cs7MqWmg uzFxXrhgssYuJtLtkempbW6i8TkIA4KYveAWVxprIzIJnEZA0SQmm2+BSyYegBDLneWj 9iYZszjlEJDtajk9jtz+CKIjpOmDvvK5qJsyjFIT+le5ab/6YmsPbeZuoiiBGF2HWrUA QZ+w== X-Gm-Message-State: AFqh2kps6b1omQEhoUIOdsRgARTaNfoLPO7pc1TZNTBDXAkfu1+A96sk L7suGKtpo3Ir0kAK/Joe3Ft5mkJ7QDrrAU8U X-Google-Smtp-Source: AMrXdXuzsCnscctoTnzdxaear32uQTIHwDKzFEFF77LusWV6o7BO4EMCEbrIcwO6yQRdkp8xxGOB0Q== X-Received: by 2002:a62:148d:0:b0:58b:ca43:9c05 with SMTP id 135-20020a62148d000000b0058bca439c05mr23674453pfu.16.1674518467325; Mon, 23 Jan 2023 16:01:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 12/22] target/arm: NSTable is RES0 for the RME EL3 regime Date: Mon, 23 Jan 2023 14:00:17 -1000 Message-Id: <20230124000027.3565716-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518808824100001 Content-Type: text/plain; charset="utf-8" Test in_space instead of in_secure so that we don't switch out of Root space. Handle the output space change immediately, rather than try and combine the NSTable and NS bits later. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index c1b0b8e610..ddafb1f329 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1240,7 +1240,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, { ARMCPU *cpu =3D env_archcpu(env); ARMMMUIdx mmu_idx =3D ptw->in_mmu_idx; - bool is_secure =3D ptw->in_secure; int32_t level; ARMVAParameters param; uint64_t ttbr; @@ -1256,7 +1255,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); uint64_t descriptor, new_descriptor; - bool nstable; =20 /* TODO: This code does not support shareability levels. */ if (aarch64) { @@ -1417,29 +1415,29 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, descaddrmask =3D MAKE_64BIT_MASK(0, 40); } descaddrmask &=3D ~indexmask_grainsize; - - /* - * Secure accesses start with the page table in secure memory and - * can be downgraded to non-secure at any step. Non-secure accesses - * remain non-secure. We implement this by just ORing in the NSTable/NS - * bits at each step. - */ - tableattrs =3D is_secure ? 0 : (1 << 4); + tableattrs =3D 0; =20 next_level: descaddr |=3D (address >> (stride * (4 - level))) & indexmask; descaddr &=3D ~7ULL; - nstable =3D extract32(tableattrs, 4, 1); - if (nstable && ptw->in_secure) { - /* - * Stage2_S -> Stage2 or Phys_S -> Phys_NS - * Assert that the non-secure idx are even, and relative order. - */ + + /* + * Process the NSTable bit from the previous level. This changes + * the table address space and the output space from Secure to + * NonSecure. With RME, the EL3 translation regime does not change + * from Root to NonSecure. + */ + if (extract32(tableattrs, 4, 1) && ptw->in_space =3D=3D ARMSS_Secure) { + /* Stage2_S -> Stage2 or Phys_S -> Phys_NS */ QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_S + 1 !=3D ARMMMUIdx_Phys_NS); QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 !=3D ARMMMUIdx_Stage2); ptw->in_ptw_idx +=3D 1; ptw->in_secure =3D false; + ptw->in_space =3D ARMSS_NonSecure; + result->f.attrs.secure =3D false; + result->f.attrs.space =3D ARMSS_NonSecure; } + if (!S1_ptw_translate(env, ptw, descaddr, fi)) { goto do_fault; } @@ -1542,7 +1540,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, */ attrs =3D new_descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(5= 0, 14)); if (!regime_is_stage2(mmu_idx)) { - attrs |=3D nstable << 5; /* NS */ if (!param.hpd) { attrs |=3D extract64(tableattrs, 0, 2) << 53; /* XN, PXN */ /* --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674518776; cv=none; d=zohomail.com; s=zohoarc; b=jcD4Lza0xcHzYO+pNpQBlIUu4M50fhvwWbMYO1JVT8+egoDYnuphFpwZeSGoZBa0d/a+IHsm1wDmT7lPv3mrBWE1IAp5cGVwdZy/jUdlX7MuSX9lQ/E7kK3igA1XTl9vo+orNpkAK466Ob6C2aOyyo7kjUfUyi/KSORiPFH3pzU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674518776; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HLh9VmBezchTJLEcE+qN9RM6YfR7/kG+gCrSbag3gHU=; b=RhAReqAzo4TCKP7f62rCIaMECPnPKLXaP8K6BkqN+decSpwlZbtAIq3dV+qzHeI4VKEfdSRzyRC+wN+8h6Rz1Tn8hGXIa/FB87ErI1VrCn8koJJHw3vR19NtXW1ieVJJHkHyhzKoSIkG8YP+p0hECH4qhFNeLA49Mi9a6vuvr74= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674518776063895.2936876635176; Mon, 23 Jan 2023 16:06:16 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pK6kU-0000VM-1Z; Mon, 23 Jan 2023 19:01:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK6kS-0000Ub-Qd for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:13 -0500 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK6kP-0001uO-Vl for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:12 -0500 Received: by mail-pg1-x52d.google.com with SMTP id d10so10220545pgm.13 for ; Mon, 23 Jan 2023 16:01:09 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.01.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:01:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HLh9VmBezchTJLEcE+qN9RM6YfR7/kG+gCrSbag3gHU=; b=v6a4iZy2M5Z9E8Hw3HPddwCpsGwpnFIqA3DpNKxk7PkY+3Ne/qFYtfe/5SN9FxX5Pf nTPAuqHNQPAMxXAhF1PvdlF44YxN1jvusvPQqotuwmEywL6IlER0fcq96phkaMhbblhZ 2+KjXi8YiruEnPBXBSBUxrvBWXVESnkqpR4JjcJYN8WyN+Yb4fnUanOKcoCosZLKcjUQ GDlKfjL20R+cZx9kv+p9DH2ttfpygNsLgli8NMwPcV+aB1UzA4K0OmagdOBFyXXHGWVm 1F+Dc0pnEToViGkT06BS0/hKiCKmfeQf+YQs03xFja8R/N4EGLMRzStEXzzrPrAiosbA 7a4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HLh9VmBezchTJLEcE+qN9RM6YfR7/kG+gCrSbag3gHU=; b=0PWorcTky1gP4FU9fMP0o0Yci1hgueCXLfh6iWyDO4OTN0XQaove/5Eh+IojXJZBSV Mnz2VD5bSVVPtTnnUb1rybyrHmHfRn14X7o6xcA8t+1A12c3+Z15IglNSUaGgF+oXEd+ 7tliit0NgBris33lUzNUVwqsPdthOKRAurz/x5Xw9Cv1klCuAesQ+u4VYThKYumEnaNr D1nUyJZeINVIzPeIII9Olpmxgx9GUZ4HS2CjLOwxbsnuVJ1hRqYnYhWaDYXrNtlK2Zo1 oK/iMPfbbPeKzj7rbBM6o3ruNVpNcCnGG7fCKE4m7BQ6P6FlmEsXV56ctAJe0KDzAFuh MpRw== X-Gm-Message-State: AFqh2krUxtxNwaXz+AAD+8Xg3fKzckC6OqF/Y+H2rfXfMA98HPaZKjql FVNOTMS6jZl5jnyKbwRly/P/GPdkkupBk246 X-Google-Smtp-Source: AMrXdXvKJlXncOW+MhL+i2b2OM/JXSM37+n487B1Z0WsX1pAEpPzw9B+O6ikh150sDQyrM9x7XNJ8w== X-Received: by 2002:a62:63c6:0:b0:576:ddd4:6a02 with SMTP id x189-20020a6263c6000000b00576ddd46a02mr27348655pfb.22.1674518469141; Mon, 23 Jan 2023 16:01:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 13/22] target/arm: Handle Block and Page bits for security space Date: Mon, 23 Jan 2023 14:00:18 -1000 Message-Id: <20230124000027.3565716-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518776626100001 Content-Type: text/plain; charset="utf-8" With Realm security state, bit 55 of a block or page descriptor during the stage2 walk becomes the NS bit; during the stage1 walk the bit 5 NS bit is RES0. With Root security state, bit 11 of the block or page descriptor during the stage1 walk becomes the NSE bit. Rather than collecting an NS bit and applying it later, compute the output pa space from the input pa space and unconditionally assign. This means that we no longer need to adjust the output space earlier for the NSTable bit. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 74 +++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 60 insertions(+), 14 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index ddafb1f329..849f5e89ca 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1250,11 +1250,12 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, int32_t stride; int addrsize, inputsize, outputsize; uint64_t tcr =3D regime_tcr(env, mmu_idx); - int ap, ns, xn, pxn; + int ap, xn, pxn; uint32_t el =3D regime_el(env, mmu_idx); uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); uint64_t descriptor, new_descriptor; + ARMSecuritySpace out_space; =20 /* TODO: This code does not support shareability levels. */ if (aarch64) { @@ -1434,8 +1435,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, ptw->in_ptw_idx +=3D 1; ptw->in_secure =3D false; ptw->in_space =3D ARMSS_NonSecure; - result->f.attrs.secure =3D false; - result->f.attrs.space =3D ARMSS_NonSecure; } =20 if (!S1_ptw_translate(env, ptw, descaddr, fi)) { @@ -1552,12 +1551,66 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, } =20 ap =3D extract32(attrs, 6, 2); + out_space =3D ptw->in_space; if (regime_is_stage2(mmu_idx)) { - ns =3D mmu_idx =3D=3D ARMMMUIdx_Stage2; + /* + * R_GYNXY: For stage2 in Realm security state, bit 55 is NS. + * The bit remains ignored for other security states. + */ + if (out_space =3D=3D ARMSS_Realm && extract64(attrs, 55, 1)) { + out_space =3D ARMSS_NonSecure; + } xn =3D extract64(attrs, 53, 2); result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); } else { - ns =3D extract32(attrs, 5, 1); + int ns =3D extract32(attrs, 5, 1); + switch (out_space) { + case ARMSS_Root: + /* + * R_GVZML: Bit 11 becomes the NSE field in the EL3 regime. + * R_XTYPW: NSE and NS together select the output pa space. + */ + int nse =3D extract32(attrs, 11, 1); + out_space =3D (nse << 1) | ns; + if (out_space =3D=3D ARMSS_Secure && + !cpu_isar_feature(aa64_sel2, cpu)) { + out_space =3D ARMSS_NonSecure; + } + break; + case ARMSS_Secure: + if (ns) { + out_space =3D ARMSS_NonSecure; + } + break; + case ARMSS_Realm: + switch (mmu_idx) { + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: + /* I_CZPRF: For Realm EL1&0 stage1, NS bit is RES0. */ + break; + case ARMMMUIdx_E2: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + /* + * R_LYKFZ, R_WGRZN: For Realm EL2 and EL2&1, + * NS changes the output to non-secure space. + */ + if (ns) { + out_space =3D ARMSS_NonSecure; + } + break; + default: + g_assert_not_reached(); + } + break; + case ARMSS_NonSecure: + /* R_QRMFF: For NonSecure state, the NS bit is RES0. */ + break; + default: + g_assert_not_reached(); + } xn =3D extract64(attrs, 54, 1); pxn =3D extract64(attrs, 53, 1); result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, p= xn); @@ -1587,15 +1640,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, } } =20 - if (ns) { - /* - * The NS bit will (as required by the architecture) have no effec= t if - * the CPU doesn't support TZ or this is a non-secure translation - * regime, because the attribute will already be non-secure. - */ - result->f.attrs.secure =3D false; - result->f.attrs.space =3D ARMSS_NonSecure; - } + result->f.attrs.space =3D out_space; + result->f.attrs.secure =3D arm_space_is_secure(out_space); =20 /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. = */ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674518526; cv=none; d=zohomail.com; s=zohoarc; b=ZIRib0ZppMacd3L5S7Qth3B6cQaE+4VRYGwAocmbyV024JJm9YpdNP3kBHo3e0GXM9mA2a/Xr9p+DPHsbwXmWEYESOEhX+5gK+LVqZe3iEWfwhaRoruIQmzs0wkEGpASEVVIQ7vRe9hL4ATcHex9wj6NzngksMwvvilJQcP6kw8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674518526; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.01.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:01:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GokO7E+PxzQZL9dhXPIi+avIXtmrT5EfPM1E6UCpmSU=; b=AtLGLLm0VNXhoQl+fWX2w1b6J2GJYrByElwAWYKoc0eSgOU82wzIYoztLeTxjQQfeb NrobXzxXASDwbNW3tSAC/dgDcIrlAXnsgrtZyKorM7AcZnyR8q0zKDXG1aS1hjPs5ssO bPUPZ//v3+IhifGnSxALAi+k+S5g77hd6evYkAQwte2mVC/Ka2eiH+oY3bO7fSBLNn2W Eab6rMFvLOeJKojxkx1rGaPz9B85aDJzh1GTs21t1NQ0ZxbKWSfPVUj+GUGWwa6jyZ+U KCFI1Sf8b2WXHGSVud4UqqXWlD+xHpdAcbk8ofsXfvwlduNR9/vpBWFXWTcOTE77MzuU 4u0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GokO7E+PxzQZL9dhXPIi+avIXtmrT5EfPM1E6UCpmSU=; b=1yHNuYPRFzxYiJQ4f7+H0/eSnd2LWbVUrj7iqghVjk3+rtPdhxFiQeM8IitV8X+TXN ywaas4m1xFmxq1YM2C+c26gX46dHKKN7/Ju8R93Zg+1IbFwdX0FbUZE4h7JbujgW6mhD aouMc9UIicUpM2+gCvzLzaA4LdzaWJL1AYvbnROON2pd4IozWEj8pgmm55csyt9QYFEm yRw2KVx5vifhDY9PjutdhQz1fMV6PBIuzd4vBK52YJ6ygBjorBbK2Rc3R+SluBXL/iIS hGApybbGyuD+t+GwNerrgzlXm8+AlfS1d+4BZge2KKI+r1fxohXgMncCUS63mnrFkSkW XPIw== X-Gm-Message-State: AFqh2kqiqfNoRm7w6UVMUUJGihhQncRyDzIZsPKyFyC+5R158ZwbTBPm 2yZdye/duNVME5uwwCx53rzSJ+5Cjmk+zvmF X-Google-Smtp-Source: AMrXdXscoX5q7Yvc4F2mBBaHFEIhjNfazUXhb+vAM80+EHhUxVonYI+Vb09/rsb3uXTCFvCCSAeAyg== X-Received: by 2002:a05:6a20:8402:b0:b0:30d8:d53 with SMTP id c2-20020a056a20840200b000b030d80d53mr35077728pzd.19.1674518470827; Mon, 23 Jan 2023 16:01:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 14/22] target/arm: Handle no-execute for Realm and Root regimes Date: Mon, 23 Jan 2023 14:00:19 -1000 Message-Id: <20230124000027.3565716-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518527435100001 Content-Type: text/plain; charset="utf-8" While Root and Realm may read and write data from other spaces, neither may execute from other pa spaces. This happens for Stage1 EL3, EL2, EL2&0, but stage2 EL1&0. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 66 ++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 58 insertions(+), 8 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 849f5e89ca..6b6f8195eb 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -909,7 +909,7 @@ do_fault: * @xn: XN (execute-never) bits * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0 */ -static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) +static int get_S2prot_noexecute(int s2ap) { int prot =3D 0; =20 @@ -919,6 +919,12 @@ static int get_S2prot(CPUARMState *env, int s2ap, int = xn, bool s1_is_el0) if (s2ap & 2) { prot |=3D PAGE_WRITE; } + return prot; +} + +static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) +{ + int prot =3D get_S2prot_noexecute(s2ap); =20 if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) { switch (xn) { @@ -956,12 +962,14 @@ static int get_S2prot(CPUARMState *env, int s2ap, int= xn, bool s1_is_el0) * @mmu_idx: MMU index indicating required translation regime * @is_aa64: TRUE if AArch64 * @ap: The 2-bit simple AP (AP[2:1]) - * @ns: NS (non-secure) bit * @xn: XN (execute-never) bit * @pxn: PXN (privileged execute-never) bit + * @in_pa: The original input pa space + * @out_pa: The output pa space, modified by NSTable, NS, and NSE */ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, - int ap, int ns, int xn, int pxn) + int ap, int xn, int pxn, + ARMSecuritySpace in_pa, ARMSecuritySpace out_pa) { bool is_user =3D regime_is_user(env, mmu_idx); int prot_rw, user_rw; @@ -982,8 +990,39 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_= idx, bool is_aa64, } } =20 - if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { - return prot_rw; + if (in_pa !=3D out_pa) { + switch (in_pa) { + case ARMSS_Root: + /* + * R_ZWRVD: permission fault for insn fetched from non-Root, + * I_WWBFB: SIF has no effect in EL3. + */ + return prot_rw; + case ARMSS_Realm: + /* + * R_PKTDS: permission fault for insn fetched from non-Realm, + * for Realm EL2 or EL2&0. The corresponding fault for EL1&0 + * happens during any stage2 translation. + */ + switch (mmu_idx) { + case ARMMMUIdx_E2: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + return prot_rw; + default: + break; + } + break; + case ARMSS_Secure: + if (env->cp15.scr_el3 & SCR_SIF) { + return prot_rw; + } + break; + default: + /* Input NonSecure must have output NonSecure. */ + g_assert_not_reached(); + } } =20 /* TODO have_wxn should be replaced with @@ -1556,12 +1595,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, /* * R_GYNXY: For stage2 in Realm security state, bit 55 is NS. * The bit remains ignored for other security states. + * R_YMCSL: Executing an insn fetched from non-Realm causes + * a stage2 permission fault. */ if (out_space =3D=3D ARMSS_Realm && extract64(attrs, 55, 1)) { out_space =3D ARMSS_NonSecure; + result->f.prot =3D get_S2prot_noexecute(ap); + } else { + xn =3D extract64(attrs, 53, 2); + result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); } - xn =3D extract64(attrs, 53, 2); - result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); } else { int ns =3D extract32(attrs, 5, 1); switch (out_space) { @@ -1613,7 +1656,14 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, } xn =3D extract64(attrs, 54, 1); pxn =3D extract64(attrs, 53, 1); - result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, p= xn); + + /* + * Note that we modified ptw->in_space earlier for NSTable, + * and result->f.attrs was initialized by get_phys_addr, so + * that retains a copy of the original security space. + */ + result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, xn, pxn, + result->f.attrs.space, out_space); } =20 if (!(result->f.prot & (1 << access_type))) { --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674518664; cv=none; d=zohomail.com; s=zohoarc; b=gwZGeD762LutGVYI6D/cXBlxgoLnDMfcfut2/rWQHl7mns/FoLMtZpX9WW0uQ5SV62ycv92TKfiwAsEMUDJ0y1nMBm4fZh81SyUhFuaYZ33Twfkb/32Kwb/9f3kI/NgmeYaiAuGG/NHiL8GdIWNDsw/BKstDKBh+fksg8j4+1WI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674518664; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iCmbkLa0yYr0QBg1CfQR5sNbcMWAWJk89TMhy0bc8HA=; b=LtcqKsjfZbv/KOYiMBSCCHH+QYykDDDeYoPVXJTUXey6AXQA8crZh7mnfXrduwL8mypynusF0CzO9objpohOthKFVahRas3Vtnn6QuFTzwe5W7tYhluB66FLNfXVyoObx/T8WF7mi+bI+WwMfg4dRkr48OtIxWr+r6u1qYrDtTg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674518664679391.9847484228625; Mon, 23 Jan 2023 16:04:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pK6kc-0001F3-Hx; Mon, 23 Jan 2023 19:01:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK6kZ-00010G-T2 for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:20 -0500 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK6kT-0001xa-Rp for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:19 -0500 Received: by mail-pf1-x42e.google.com with SMTP id 200so10108948pfx.7 for ; Mon, 23 Jan 2023 16:01:13 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.01.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:01:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iCmbkLa0yYr0QBg1CfQR5sNbcMWAWJk89TMhy0bc8HA=; b=W1QFLQHUNk4auQyvGViV6iqYI7eysC7CXKLkFOJFx0wc+v8K6cqxnFf5WJ2Xif9tdd cNApj9VkWMtNMeV9obPZwB//Hjahx62jn9hGY/knjuPi1C26E+1yKAlrQKJ1ANvtVjaV Tuy6OZnV6H2gNV8sMqi2zpWDZ0ISD5GyNjyr4WryiO+pnFPjA8jFiSlPV7Y8pqgVX8A8 K0iSfdBmgHK7VuVdVhZhMmcJayycmXjqQ840R53TihEASppUWa3RnRFOhRQV5mp/1ZyU iA44pNlcOH6xX07Q0iJnhYbRC/4UlBBCGekES3vV4NZ7LDq6/becB5VWTukxT6iItn3D iPjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iCmbkLa0yYr0QBg1CfQR5sNbcMWAWJk89TMhy0bc8HA=; b=JMzWPtgC2G3m9/IgLBw6IuDzz6F8pPq8gBh9mvPQ9CPkl/2ViBBJMTe5hoE/S8Q0IP sQjCfGrkWJ9BnTBYK09fenMVEbFmL1gzZe2XNh4rN/jFlMFxCQ7WnlXJ40kT81QSDkjp hRvZo0JhJ6ydhYyJgFogAaDR0pLdRG8t0olOexFWwho91IToMx9V2Sf3pnCd0f90zmnd /2RGH0rtV97NeMyzgveZaFfNl38E8fgfLhMwjwzRtsmzbb577eJmsSZuGWyaCe9AsTxS vESda1RXQegc9O1YGPvuVAOdmXk897t93G/oyFViGG9qTTzbdrdn2cEnsjVREuYEfhXH pQCw== X-Gm-Message-State: AFqh2kqV8/3NBCCAXjfyLEhHEp7qZi7SK1C5E8aX4ePXyqxgYo0xXk6k ZfHTRUb10eUV9DieWdLhl2DwFoY3EYV164cv X-Google-Smtp-Source: AMrXdXtMCCFq72IvBju6RydlxAvVYXMbRrt9zeHI+IftANjm40L+RNpD2q/kGNN0MtC91jtTCs6HCw== X-Received: by 2002:a62:1ac9:0:b0:57a:7b74:4ec5 with SMTP id a192-20020a621ac9000000b0057a7b744ec5mr26366412pfa.13.1674518472501; Mon, 23 Jan 2023 16:01:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 15/22] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate Date: Mon, 23 Jan 2023 14:00:20 -1000 Message-Id: <20230124000027.3565716-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518666343100001 Content-Type: text/plain; charset="utf-8" Do not provide a fast-path for physical addresses, as those will need to be validated for GPC. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 35 ++++++++++++++--------------------- 1 file changed, 14 insertions(+), 21 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6b6f8195eb..37f5ff220c 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -234,29 +234,22 @@ static bool S1_ptw_translate(CPUARMState *env, S1Tran= slate *ptw, * From gdbstub, do not use softmmu so that we don't modify the * state of the cpu at all, including softmmu tlb contents. */ - if (regime_is_stage2(s2_mmu_idx)) { - S1Translate s2ptw =3D { - .in_mmu_idx =3D s2_mmu_idx, - .in_ptw_idx =3D arm_space_to_phys(space), - .in_space =3D space, - .in_secure =3D is_secure, - .in_debug =3D true, - }; - GetPhysAddrResult s2 =3D { }; + S1Translate s2ptw =3D { + .in_mmu_idx =3D s2_mmu_idx, + .in_ptw_idx =3D arm_space_to_phys(space), + .in_space =3D space, + .in_secure =3D is_secure, + .in_debug =3D true, + }; + GetPhysAddrResult s2 =3D { }; =20 - if (get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD, - false, &s2, fi)) { - goto fail; - } - ptw->out_phys =3D s2.f.phys_addr; - pte_attrs =3D s2.cacheattrs.attrs; - pte_secure =3D s2.f.attrs.secure; - } else { - /* Regime is physical. */ - ptw->out_phys =3D addr; - pte_attrs =3D 0; - pte_secure =3D is_secure; + if (get_phys_addr_with_struct(env, &s2ptw, addr, + MMU_DATA_LOAD, &s2, fi)) { + goto fail; } + ptw->out_phys =3D s2.f.phys_addr; + pte_attrs =3D s2.cacheattrs.attrs; + pte_secure =3D s2.f.attrs.secure; ptw->out_host =3D NULL; ptw->out_rw =3D false; } else { --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674518545; cv=none; d=zohomail.com; s=zohoarc; b=MAe6H/3URhq+lZU6QvjiUqxhrhwt4WX+fC8R8/0b9owxD+piSwWnLIqKkJJfRq6bSwUJco6KTIssNHyUELnjRV8qUOCN+PSs/6e6Olq6INPuWut+1LoDyqS80CLfHqt62sB5ko7QI4i55Az/Kf8KpMSFiQW5eU18Z6ljCnBS4dU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674518545; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HLC1b+miMYKSFpzmpb6sjN/lCOjEj7YzmRL1GMfHWWQ=; b=cQv8vr87y8a/RQD4tZWEzFwMiDSsNKc/IQzwqZK09VyRkYcc/c3tLHHPBdye6x0ue4TkO4N8luDYVl5bD1tOToS2EcyzmHNipcY8dxZeHMt2Lzmtn5L1EnAlCAzZWPo4KW4YP1zZNzVVqG5AEcKgmm+rOy3sTjK+dmGbRSdPYkE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674518545233902.1186736436262; Mon, 23 Jan 2023 16:02:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pK6kZ-0000wy-MA; Mon, 23 Jan 2023 19:01:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK6kY-0000pc-Am for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:18 -0500 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK6kW-0001xx-22 for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:18 -0500 Received: by mail-pg1-x534.google.com with SMTP id 36so10228464pgp.10 for ; Mon, 23 Jan 2023 16:01:15 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.01.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:01:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HLC1b+miMYKSFpzmpb6sjN/lCOjEj7YzmRL1GMfHWWQ=; b=va0D7Jo3HJRLKp7iICozOQigBIOgZRTIFMFFeG9lisAzsWlinksVjz7mmXIMXvlc8R aplebvAWzoNq5Soc4bU0qn3Jyi0Xcx1NOoE4E9E4Hb5V4jbv0RfE0uA9uc2BTraAC/4n ROJbbDFHY8W0gYYnqcqd6RaFPZxHg+qbsAAK7rwQHzOUb/g9zP4a80ZQ71S53C3/vxf3 S2CTTgWLyLAB8RoCBTTDgkH8STKWX/8FyHnIXugw2WgWEtbPPxLFG3Vwc1IFR9G7HIex ZyNSwNaR6Khi9mMZOusAHbwJLKtwF01K/LZZjJKyW5kTFFHdZ+MTi8Xohc3jd6MXWwoC 8MsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HLC1b+miMYKSFpzmpb6sjN/lCOjEj7YzmRL1GMfHWWQ=; b=C1OGrOBC6bZfu9gOtR4ggJOKkzOQR7x2xC9NLyrQEKMkqGSPWUECkMMDcrhXfq4ks0 T84klhYwLjhwbS1pYhzSkofXDxUZV5ipNyuH7NTbggzk81Qs7HqoPbNP5S/+jBO6YBWs rxI6TjjWWi2WYQwpo1+KC+BDqCUmZgNaFmDnsMxFIxOIhevUmHEXmZxHmmvr1Vqu2/9/ D7apAyOgbxdEoEQ8/Rj1wWLh3vKL9vdqifjeE1MWybViq5dL0wiAZ0Dql43EZZzqvzVy DTzwICqI4AK/2BMaxSp22iq7LOljZBmcAOK1FJvX9DYilMn13qWLrxO8IMzkjfolL46a yoMQ== X-Gm-Message-State: AFqh2kr3UtnooqB+K5UZijEQVk1ZP0KLP3gfzTEFjZ8SA7Pd1jNTUB4q j3c2nQ2Wx5lxZYAH9CdCY95auRoiRGfbPDxP X-Google-Smtp-Source: AMrXdXtJ2spXVYATb077xOO9IFKJerxx+cWgK8zeAjvi3Nzfd0gtmgfF7+gT9UrjYQAFA8Ji5XZ9CQ== X-Received: by 2002:a05:6a00:438d:b0:589:8fac:cfe5 with SMTP id bt13-20020a056a00438d00b005898faccfe5mr26236608pfb.13.1674518474227; Mon, 23 Jan 2023 16:01:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 16/22] target/arm: Move s1_is_El0 into S1Translate Date: Mon, 23 Jan 2023 14:00:21 -1000 Message-Id: <20230124000027.3565716-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518545497100003 Content-Type: text/plain; charset="utf-8" Instead of passing this to get_phys_addr_lpae, stash it in the S1Translate structure. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 37f5ff220c..eaa47f6b62 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -22,6 +22,7 @@ typedef struct S1Translate { ARMSecuritySpace in_space; bool in_secure; bool in_debug; + bool in_s1_is_el0; bool out_secure; bool out_rw; bool out_be; @@ -33,7 +34,7 @@ typedef struct S1Translate { =20 static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, uint64_t address, - MMUAccessType access_type, bool s1_is_el0, + MMUAccessType access_type, GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) __attribute__((nonnull)); =20 @@ -1257,17 +1258,12 @@ static int check_s2_mmu_setup(ARMCPU *cpu, bool is_= aa64, uint64_t tcr, * @ptw: Current and next stage parameters for the walk. * @address: virtual address to get physical address for * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH - * @s1_is_el0: if @ptw->in_mmu_idx is ARMMMUIdx_Stage2 - * (so this is a stage 2 page table walk), - * must be true if this is stage 2 of a stage 1+2 - * walk for an EL0 access. If @mmu_idx is anything else, - * @s1_is_el0 is ignored. * @result: set on translation success, * @fi: set to fault info if the translation fails */ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, uint64_t address, - MMUAccessType access_type, bool s1_is_el0, + MMUAccessType access_type, GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) { ARMCPU *cpu =3D env_archcpu(env); @@ -1596,7 +1592,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, result->f.prot =3D get_S2prot_noexecute(ap); } else { xn =3D extract64(attrs, 53, 2); - result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); + result->f.prot =3D get_S2prot(env, ap, xn, ptw->in_s1_is_el0); } } else { int ns =3D extract32(attrs, 5, 1); @@ -2819,7 +2815,6 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, bool ret, ipa_secure, s2walk_secure; ARMCacheAttrs cacheattrs1; ARMSecuritySpace ipa_space, s2walk_space; - bool is_el0; uint64_t hcr; =20 ret =3D get_phys_addr_with_struct(env, ptw, address, access_type, resu= lt, fi); @@ -2844,7 +2839,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, s2walk_space =3D ipa_space; } =20 - is_el0 =3D ptw->in_mmu_idx =3D=3D ARMMMUIdx_Stage1_E0; + ptw->in_s1_is_el0 =3D ptw->in_mmu_idx =3D=3D ARMMMUIdx_Stage1_E0; ptw->in_mmu_idx =3D s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Sta= ge2; ptw->in_ptw_idx =3D arm_space_to_phys(s2walk_space); ptw->in_secure =3D s2walk_secure; @@ -2863,8 +2858,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, ret =3D get_phys_addr_pmsav8(env, ipa, access_type, ptw->in_mmu_idx, s2walk_secure, result,= fi); } else { - ret =3D get_phys_addr_lpae(env, ptw, ipa, access_type, - is_el0, result, fi); + ret =3D get_phys_addr_lpae(env, ptw, ipa, access_type, result, fi); } fi->s2addr =3D ipa; =20 @@ -3040,8 +3034,7 @@ static bool get_phys_addr_with_struct(CPUARMState *en= v, S1Translate *ptw, } =20 if (regime_using_lpae_format(env, mmu_idx)) { - return get_phys_addr_lpae(env, ptw, address, access_type, false, - result, fi); + return get_phys_addr_lpae(env, ptw, address, access_type, result, = fi); } else if (arm_feature(env, ARM_FEATURE_V7) || regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, ptw, address, access_type, result, fi= ); --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674518762; cv=none; d=zohomail.com; s=zohoarc; b=h+xyEKF5iCNsOz7jhsMviJmOO+uoJBIHbJBud2v8W0IAcDbLFD30sL+ZxngQPLy1PHE7j4Tk7bhoffLKDwZ9hSm0mPOQU7L94VT6tOpl6ClTL8Hcu68/0B5TGWLJJr4GDHcHSWiirvQtEDUnWBNc+rW3ijp7BUnfvIK1mSQffQE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674518762; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mN9cAMzgJVhB9gjvwFWE29O2HsMxPZwiEF+AaYdvZqg=; b=OHbBrW4/68Xq0oP0pQz2kmoRQ7uJEqoAthXZmo5sI3E7WRn0n8qij6NaqnqESdBpFbX1m8Nv3M6PIhVHloQVlEbkAR9KW2r72OLMPwkx5AqmKWEqowaaWS9wmT+B3WbShb66CMpQZkm+PP6CRodHIgBdEtA3B1iCyZJSZ3rJs4k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167451876240011.794660374199566; Mon, 23 Jan 2023 16:06:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pK6kb-00016F-98; Mon, 23 Jan 2023 19:01:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK6kZ-0000zP-Sd for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:19 -0500 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK6kX-0001yR-9K for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:19 -0500 Received: by mail-pl1-x630.google.com with SMTP id a18so559306plm.2 for ; Mon, 23 Jan 2023 16:01:16 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.01.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:01:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mN9cAMzgJVhB9gjvwFWE29O2HsMxPZwiEF+AaYdvZqg=; b=iUOr2gxPtjgQ5rX94H68LLu0v0+vSNkJcOqIinvyBPsiQVY2TGTJJZ1QONkfMpnI1J cTfVhvUyyHE3c15c88dNtSOdYL6nApIrH3GWMf/F0i0WCD8FpUDW2ptEQWMGfQO2vwFn 0JtN6VgmsoOh0W+Xr2cfKIejLyMZkk0z3iKYk8a7z2/ChR2qpDrAN/Vtra2WIjc5AuKw G51UZMHtZy7ieD0pTTxmoKyHaXbqSaldhuynbowLr5MX3DrKiP3QTzuTRxniYEzSwwis nr7sbtEHUiljenhaW8Mo5DJV0wDGskuxIUHv45DxHJd8TSH6lsdLsVyx8Ue9C/TlYpSJ gERg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mN9cAMzgJVhB9gjvwFWE29O2HsMxPZwiEF+AaYdvZqg=; b=a35En8eH+K2YtLmrBSXo3lcPYQFcDNosf3P+zf1utUfI8FRWrC06tEtJiUjLeVJTkE 0CmXtAGsub/W4KZGDUfnQvbxsY0/lhl919OY3UL/KNiSC4CpL/RG8HgpuE293BgRH+F4 AEeThvaI8UgjM1cFeVfa1UrJ/FdBYgq+gkTl5dB2kN+1VKxka2sJi0MbvANSJgpGTRoP fD/CLMsLkBJmFJoF0df4PLFiGOzjRElI960gH+SIzve0vliLh3EqSUL6vtNo8YB/poXO kAe23D00nk8vddKOxe24N5nAkF+LK5oMhnuzMgXmdPnW4OtFT0JAo9GqUzUhYEYXUEm9 rDHA== X-Gm-Message-State: AFqh2ko4F60/zIkSHrpjPQpJsDDZF0/S5T3Z2engGGACnVVfLH8IWnWp lbvepA4TjlKt0N0Z+jybJYxWGgq4xxiX52Y7 X-Google-Smtp-Source: AMrXdXvbwhuX46VKmJaFxWIyy5KPppcXXM68AKXDjbJTgLaiMlKv1lgUcOkrhi4Sh8M9OSlJQiTbWQ== X-Received: by 2002:a05:6a20:4295:b0:b8:9c66:cd64 with SMTP id o21-20020a056a20429500b000b89c66cd64mr34076018pzj.14.1674518475853; Mon, 23 Jan 2023 16:01:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 17/22] target/arm: Use get_phys_addr_with_struct for stage2 Date: Mon, 23 Jan 2023 14:00:22 -1000 Message-Id: <20230124000027.3565716-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518764584100003 Content-Type: text/plain; charset="utf-8" This fixes a bug in which we failed to initialize the result attributes properly after the memset. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index eaa47f6b62..3205339957 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -32,12 +32,6 @@ typedef struct S1Translate { void *out_host; } S1Translate; =20 -static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, - uint64_t address, - MMUAccessType access_type, - GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) - __attribute__((nonnull)); - static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, target_ulong address, MMUAccessType access_type, @@ -2854,12 +2848,7 @@ static bool get_phys_addr_twostage(CPUARMState *env,= S1Translate *ptw, cacheattrs1 =3D result->cacheattrs; memset(result, 0, sizeof(*result)); =20 - if (arm_feature(env, ARM_FEATURE_PMSA)) { - ret =3D get_phys_addr_pmsav8(env, ipa, access_type, - ptw->in_mmu_idx, s2walk_secure, result,= fi); - } else { - ret =3D get_phys_addr_lpae(env, ptw, ipa, access_type, result, fi); - } + ret =3D get_phys_addr_with_struct(env, ptw, ipa, access_type, result, = fi); fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674518557; cv=none; d=zohomail.com; s=zohoarc; b=U+Vte8BGUXTwQPgfuDrFb6h3Z+jP8QA2mi0KYEQi/Fksf+q1b0ecMHBocQosQ0OheTxQR04GtblDlqyQWH299ZAq4h/8SemVpDWOFDiHaC6TbmBwhm6kCbD2ArtHrnDlDuEToc/kmZlLwiwoaWHzh+2No2B1KaSLPiMHnU+9Caw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674518557; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DNS5CavC6F+QLt2NSfLD1RbK1wX4rSbKBJ1kXmgpOIA=; b=ZZE/keHp7QSa05KpkstsPSHvTOAgtaHCv1vzX4fUgrjplpyeUF9gPUXnsNQ+jRkXNgxf2f107eATMZUPZvDpZLKuhVbEHFrX0EGo+ZA6JVXTdDvEPpQtSPXeZOPR7p+SfBuBm5haT2Gir+updGNY9Tb4uufahpsclf+q5KVOCfc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674518557097498.7898579439018; Mon, 23 Jan 2023 16:02:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pK6ke-0001MH-81; Mon, 23 Jan 2023 19:01:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK6kb-0001BI-Qp for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:21 -0500 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK6kY-0001yw-W0 for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:21 -0500 Received: by mail-pj1-x102a.google.com with SMTP id m11so1387642pji.0 for ; Mon, 23 Jan 2023 16:01:18 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.01.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:01:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DNS5CavC6F+QLt2NSfLD1RbK1wX4rSbKBJ1kXmgpOIA=; b=rt1Wx/kBl5utOTqE+Kg8fZ9T4MeJ4TgpBe1uLkW+N11ZZ+81cIyUbkE0tMFU2jQk9G 6ArR2fsq0aNDOUAhCB1y66tF4rcml5fjEwJjnkoFCsz11jGh+4DCcHwRpw6JzU7cf5T8 kPobgi50U4LQ1JzHwVCYVC7JlkJtvxZQVFl5tJxN9Pk3lhge6wyc9jlHUaVhAX4f9cWq 7jg7j98/0qxFJSXE8Vjmjd6sf0jucldpfiBQDKa5SBlK3U+pPDSk2nqBWWiM3gL395Ut Yj8Ry+4/4gg9zNsEACfcWzKaR2kNt0U0q13uk9yp5Ie9yzaLUN7T3DPqnVETKmaqel/j Yhmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DNS5CavC6F+QLt2NSfLD1RbK1wX4rSbKBJ1kXmgpOIA=; b=NVdGn0KHGAiozqOze9eyL3aVnkpleI4qpFjjr3D1wLGqBDFg954ceFxLZDr5vFWl9X FJlMjCr6HcHgUG8n+0+ENWtjZ5N201+4lD55teLJuKnqX0wGeT2U8GXdGg5x5hA3aJPL gOwnMdugwttTUH6OUvqMIzkCm5Tub27M0yykSeezb8vfbcEi+cGwCPr2wCSr85mLDEXf 8iA4LYSbJaIpuQJ0nO+0siJYWvngVsl/NHEWZXb+5ftLYsIlH8v+MMyftsZlMZEtZJtY gLJHAX4otTjNUI+cbyaSNxAN1aNw2d9jnc2aI/aB7J2oYmk1TkXjF+UDA8ifpwVS4OWC WGTw== X-Gm-Message-State: AFqh2krS3o54Uo9ajPR9o9xnJ5Zl6r6ySkhyZQ+w3+2OpzQoOeLP2jVK vHbrSBZsMyGtmQdlLMRoMLVSTI3Ge9p44LX+ X-Google-Smtp-Source: AMrXdXtTB92+bGsuwrYAPI2cqIzyVUUCoX1mXzTWy4GyX9wiDnNVKu2S1+8XGaO6om7dAJRpXzuspg== X-Received: by 2002:a05:6a20:b71b:b0:af:6f28:7c42 with SMTP id fg27-20020a056a20b71b00b000af6f287c42mr25354464pzb.62.1674518477525; Mon, 23 Jan 2023 16:01:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 18/22] target/arm: Add GPC syndrome Date: Mon, 23 Jan 2023 14:00:23 -1000 Message-Id: <20230124000027.3565716-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518557565100001 Content-Type: text/plain; charset="utf-8" The function takes the fields as filled in by the Arm ARM pseudocode for TakeGPCException. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/syndrome.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 73df5e3793..3fa926d115 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -49,6 +49,7 @@ enum arm_exception_class { EC_SYSTEMREGISTERTRAP =3D 0x18, EC_SVEACCESSTRAP =3D 0x19, EC_SMETRAP =3D 0x1d, + EC_GPC =3D 0x1e, EC_INSNABORT =3D 0x20, EC_INSNABORT_SAME_EL =3D 0x21, EC_PCALIGNMENT =3D 0x22, @@ -237,6 +238,14 @@ static inline uint32_t syn_bxjtrap(int cv, int cond, i= nt rm) (cv << 24) | (cond << 20) | rm; } =20 +static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, + int cm, int s1ptw, int wnr, int fsc) +{ + return (EC_GPC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (s2ptw << 21) + | (ind << 20) | (gpcsc << 14) | (cm << 8) | (s1ptw << 7) + | (wnr << 6) | fsc; +} + static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int = fsc) { return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674518568; cv=none; d=zohomail.com; s=zohoarc; b=gR/d0XStcoAbe7jLHCtzTl4VT7tCCD0QadtTnDqf68Y6AIWk+NWyughWRqUw0iENtwdBc+zeOpQlAte7dzux3UvU5okO7cPhIvDDFUJ93/OKlXSLuqFB8aXB9OuTW6p9wzlc/6MScWVM/rA/BUDmFQbdh7i1rkGTR4AItINX2z0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674518568; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ws2G4XMOp0lestkCd2/peNLCEqyj7X/oLG8H4z1egnA=; b=B0IZTf/6uzpEzHP4cqywE7PyJUCGty/CGvlz3yZmrybRXlm7POkRlA55mOfUO7n9smoGwba19photWs/HXMkK3KarrlUDJWTEu1D1vrSRJU4N8nnpuUEHSKX5zLAYAbfHR40FD03IBCTeDtxjDYKY5aKdZEVM3Rw542jwBnRsbM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674518568565623.2135060657663; Mon, 23 Jan 2023 16:02:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pK6kh-0001ZO-8y; Mon, 23 Jan 2023 19:01:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK6ke-0001Ov-NM for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:24 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK6kb-0001ze-2n for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:24 -0500 Received: by mail-pl1-x62d.google.com with SMTP id k13so13170898plg.0 for ; Mon, 23 Jan 2023 16:01:20 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.01.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:01:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ws2G4XMOp0lestkCd2/peNLCEqyj7X/oLG8H4z1egnA=; b=F1UsYk8YbUCHY9MKFjtXVLhh8m8ty0CppWkNqOBcAXgdNdclsUA3OvUbmplkm5F0Rq LVerCf7IQBc5TTPr/g0r26K5txGpW28P/VgO/hvYaRLb7kMko5nNPWJ52nQFqKtehDl+ t+FwyZrhd6QbErK3Y2z0bgPVcDHNTnGeTdHiITLsNA3Z42IyL74gFxk7+2XWWAZXaNN8 8xgGPYCbhJKALZ3zK/E+upP0eyS9vPqt9iynlfbTj6Zr4sxnGr0OQY3eFCQuGWr+K2Vz pQbyAgulLLImZ62ffDNEoFp4Zzyd0VAE0d07sQI6MfiP5zcJi9viEkq7m8vRBrEfCWFD Ngdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ws2G4XMOp0lestkCd2/peNLCEqyj7X/oLG8H4z1egnA=; b=ad6qpbMcT8XKUJJLjCPG5f8rMV9FCkvxeXg4m1DihPdRu7Pb8qRoDUFom+MHjJoiy1 BCq3Yux/PKUIEy0sNVA3ko8rF3aJK8qMZiHASz0M6TziczCh+7tDCk3xnrLQqRUmydJq 8e5KvPNgT7AceIR29KkfvBI1BPPtyrs5Njf9i38BNrMePtP7QuTDTtDmKw93PTH+M1g+ uma4bJTVRMLK0/a/yFSfi7zwBG+DxLpLCKZ9tj+/aaMyDe9+3ZdUKx8jNLnS/xoQ+cuk xirZAFoxsLgB5r9woLvpw8vqnUUH2TG/kcFOnIOzKWED6CLpfZvSxibBP9bdN2pwzmB6 CIcw== X-Gm-Message-State: AFqh2kptN/NzYBu0gGZp2EIW4TQ58KORHqkQHeBkPzC0uiuedV2Nn/XF BaS1R5aTHWr8kbT4aDI+vCV5OeF4VqlVQMyz X-Google-Smtp-Source: AMrXdXus2w0dg/qD6fEr3CQLH/0P2qHrNVVcV2eecWbjON/X7ORFgGHaD1ETTSkLt7k4m/iQ5AxEOw== X-Received: by 2002:a05:6a20:8e18:b0:ad:97cc:e957 with SMTP id y24-20020a056a208e1800b000ad97cce957mr65445314pzj.39.1674518479461; Mon, 23 Jan 2023 16:01:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 19/22] target/arm: Implement GPC exceptions Date: Mon, 23 Jan 2023 14:00:24 -1000 Message-Id: <20230124000027.3565716-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518569619100001 Content-Type: text/plain; charset="utf-8" Handle GPC Fault types in arm_deliver_fault, reporting as either a GPC exception at EL3, or falling through to insn or data aborts at various exception levels. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/internals.h | 27 ++++++++++++ target/arm/helper.c | 5 +++ target/arm/tlb_helper.c | 92 +++++++++++++++++++++++++++++++++++++++-- 4 files changed, 122 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 21b9afb773..7f6f157f54 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -57,6 +57,7 @@ #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ #define EXCP_VSERR 24 +#define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ =20 #define ARMV7M_EXCP_RESET 1 diff --git a/target/arm/internals.h b/target/arm/internals.h index d9555309df..c9137e814c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -352,14 +352,27 @@ typedef enum ARMFaultType { ARMFault_ICacheMaint, ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */ ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */ + ARMFault_GPCFOnWalk, + ARMFault_GPCFOnOutput, } ARMFaultType; =20 +typedef enum ARMGPCF { + GPCF_None, + GPCF_AddressSize, + GPCF_Walk, + GPCF_EABT, + GPCF_Fail, +} ARMGPCF; + /** * ARMMMUFaultInfo: Information describing an ARM MMU Fault * @type: Type of fault + * @gpcf: Subtype of ARMFault_GPCFOn{Walk,Output}. * @level: Table walk level (for translation, access flag and permission f= aults) * @domain: Domain of the fault address (for non-LPAE CPUs only) * @s2addr: Address that caused a fault at stage 2 + * @paddr: physical address that caused a fault for gpc + * @paddr_space: physical address space that caused a fault for gpc * @stage2: True if we faulted at stage 2 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table = walk * @s1ns: True if we faulted on a non-secure IPA while in secure state @@ -368,7 +381,10 @@ typedef enum ARMFaultType { typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; struct ARMMMUFaultInfo { ARMFaultType type; + ARMGPCF gpcf; target_ulong s2addr; + target_ulong paddr; + ARMSecuritySpace paddr_space; int level; int domain; bool stage2; @@ -542,6 +558,17 @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo = *fi) case ARMFault_Exclusive: fsc =3D 0x35; break; + case ARMFault_GPCFOnWalk: + assert(fi->level >=3D -1 && fi->level <=3D 3); + if (fi->level < 0) { + fsc =3D 0b100011; + } else { + fsc =3D 0b100100 | fi->level; + } + break; + case ARMFault_GPCFOnOutput: + fsc =3D 0b101000; + break; default: /* Other faults can't occur in a context that requires a * long-format status code. diff --git a/target/arm/helper.c b/target/arm/helper.c index bf78a1d74e..8d0b9a13c5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10014,6 +10014,7 @@ void arm_log_exception(CPUState *cs) [EXCP_UNALIGNED] =3D "v7M UNALIGNED UsageFault", [EXCP_DIVBYZERO] =3D "v7M DIVBYZERO UsageFault", [EXCP_VSERR] =3D "Virtual SERR", + [EXCP_GPC] =3D "Granule Protection Check", }; =20 if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { @@ -10740,6 +10741,10 @@ static void arm_cpu_do_interrupt_aarch64(CPUState = *cs) } =20 switch (cs->exception_index) { + case EXCP_GPC: + qemu_log_mask(CPU_LOG_INT, "...with MFAR 0x%" PRIx64 "\n", + env->cp15.mfar_el3); + /* fall through */ case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: /* diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 60abcbebe6..861dc0d566 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -109,17 +109,102 @@ static uint32_t compute_fsr_fsc(CPUARMState *env, AR= MMMUFaultInfo *fi, return fsr; } =20 +static bool report_as_gpc_exception(ARMCPU *cpu, int current_el, + ARMMMUFaultInfo *fi) +{ + bool ret; + + switch (fi->gpcf) { + case GPCF_None: + return false; + case GPCF_AddressSize: + case GPCF_Walk: + case GPCF_EABT: + /* R_PYTGX: GPT faults are reported as GPC. */ + ret =3D true; + break; + case GPCF_Fail: + /* + * R_BLYPM: A GPF at EL3 is reported as insn or data abort. + * R_VBZMW, R_LXHQR: A GPF at EL[0-2] is reported as a GPC + * if SCR_EL3.GPF is set, otherwise an insn or data abort. + */ + ret =3D (cpu->env.cp15.scr_el3 & SCR_GPF) && current_el !=3D 3; + break; + default: + g_assert_not_reached(); + } + + assert(cpu_isar_feature(aa64_rme, cpu)); + assert(fi->type =3D=3D ARMFault_GPCFOnWalk || + fi->type =3D=3D ARMFault_GPCFOnOutput); + assert(fi->level >=3D 0 && fi->level <=3D 1); + + return ret; +} + +static unsigned encode_gpcsc(ARMMMUFaultInfo *fi) +{ + static uint8_t const gpcsc[] =3D { + [GPCF_AddressSize] =3D 0b00000, + [GPCF_Walk] =3D 0b00010, + [GPCF_Fail] =3D 0b00110, + [GPCF_EABT] =3D 0b01010, + }; + + /* Note that we've validated fi->gpcf and fi->level above. */ + return gpcsc[fi->gpcf] | fi->level; +} + static G_NORETURN void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, ARMMMUFaultInfo *fi) { CPUARMState *env =3D &cpu->env; - int target_el; + int target_el =3D exception_target_el(env); + int current_el =3D arm_current_el(env); bool same_el; uint32_t syn, exc, fsr, fsc; =20 - target_el =3D exception_target_el(env); + if (report_as_gpc_exception(cpu, current_el, fi)) { + target_el =3D 3; + + fsr =3D compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); + + syn =3D syn_gpc(fi->stage2 && fi->type =3D=3D ARMFault_GPCFOnWalk, + access_type =3D=3D MMU_INST_FETCH, + encode_gpcsc(fi), 0, fi->s1ptw, + access_type =3D=3D MMU_DATA_STORE, fsc); + + env->cp15.mfar_el3 =3D fi->paddr; + switch (fi->paddr_space) { + case ARMSS_Secure: + break; + case ARMSS_NonSecure: + env->cp15.mfar_el3 |=3D R_MFAR_NS_MASK; + break; + case ARMSS_Root: + env->cp15.mfar_el3 |=3D R_MFAR_NSE_MASK; + break; + case ARMSS_Realm: + env->cp15.mfar_el3 |=3D R_MFAR_NSE_MASK | R_MFAR_NS_MASK; + break; + default: + g_assert_not_reached(); + } + + exc =3D EXCP_GPC; + goto do_raise; + } + + /* If SCR_EL3.GPF is unset, GPF may still be routed to EL2. */ + if (fi->gpcf =3D=3D GPCF_Fail && target_el < 2) { + if (arm_hcr_el2_eff(env) & HCR_GPF) { + target_el =3D 2; + } + } + if (fi->stage2) { target_el =3D 2; env->cp15.hpfar_el2 =3D extract64(fi->s2addr, 12, 47) << 4; @@ -127,8 +212,8 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, env->cp15.hpfar_el2 |=3D HPFAR_NS; } } - same_el =3D (arm_current_el(env) =3D=3D target_el); =20 + same_el =3D current_el =3D=3D target_el; fsr =3D compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); =20 if (access_type =3D=3D MMU_INST_FETCH) { @@ -146,6 +231,7 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, exc =3D EXCP_DATA_ABORT; } =20 + do_raise: env->exception.vaddress =3D addr; env->exception.fsr =3D fsr; raise_exception(env, exc, syn, target_el); --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674518537; cv=none; d=zohomail.com; s=zohoarc; b=MDJUR6Uf/qlP6l7ztI83HECpXn/OqoeheNwi+xYJ4af1D8NIpibZnfgBc0EFOfwGjqF7D9jE7f2Q7EzT4YtF6AbHqkzCvPce2i+9slVJjeyImNb1JVJuB06lAEhmjpcobyFkNOuyI3hTuVo3zb08D2srUNFUNK4vFAP6qICs0Us= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674518537; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.01.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:01:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/eIgTa7UHFn19je1HJebjrfYxmfGVZydPzeCHFnug+A=; b=QWpPPIr7ClAWtM7s0o08bGATOLMxWuFjIkZcERO/tL5RllP2GTyXhIADkfQg/cilAO Bcv4wfVpuTdSH+cpmwjhGAwq8ZBbm3vqqkZGCmUB7Flgu1St3CsPWxlIo0tFT2ZcDXtb 0MKZM9kHBmqMKd97w7AXqgSNlk9c88DBgFjIewc4oxQOK7HKEyirrL+mOkVqjIUyBab2 GxYKCWrQ4cjUw/BhbvstNfMQseEdbomJOV1W/7t4kNdSWaAP7Me/RUtbqy902gIohl9m y+6chu60MDFFPsPwCvzBvZcOET3mPVDL23p00Bol/GnqZ+tJyJP4A8CZqwF4/p8cOGWY gM2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/eIgTa7UHFn19je1HJebjrfYxmfGVZydPzeCHFnug+A=; b=SUvqtFOXOv+UsEULgYwjItnhWQknMWwsZvxKaRuJOSSX1paYox3V2f5ZVbkZYNY8N4 QW0kJ5Q+8g/iwSS6KB3sYc+1/KuvhihQ5pbJ53tUfZoNhTKvacYpSBDcjkqkrcYqzxUq lZy65dieFJCp55SceQvTpAOfBpDLK5R7P80n0AdQ69if4dp6kxU/faqU7u+hGEFHB+5O UyNXamCWvVzLq/bMeqA65Hmg4/vZGNp/k9INKzg4GeGoL2R1bzM3pdV5qxHgBWQG0dFt /G0PqCTAUJiP/8xT1tqt/Kp+SEGPqXntCEhT14Ga784ki6ulhIjmLJeEqXnUOq3Fuiha lSJw== X-Gm-Message-State: AFqh2kokR6rC/Y7NMMsjUHwQnd3GyNq1mcdChCtLgtflhmB3GrZlPtXT PbGh0ziNcugwp0SSsKg3H9CQvXDri/tOJx0W X-Google-Smtp-Source: AMrXdXthdElwpx8pym7x19Oo8cNkZ4wNuWEasCsfzFayHVl921n0QG9cz8tNg3T3iUMC4FbOBYzF4g== X-Received: by 2002:aa7:9e0c:0:b0:58d:ae6d:14d5 with SMTP id y12-20020aa79e0c000000b0058dae6d14d5mr27504572pfq.27.1674518481613; Mon, 23 Jan 2023 16:01:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 20/22] target/arm: Implement the granule protection check Date: Mon, 23 Jan 2023 14:00:25 -1000 Message-Id: <20230124000027.3565716-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518539481100003 Content-Type: text/plain; charset="utf-8" Place the check at the end of get_phys_addr_with_struct, so that we check all physical results. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/ptw.c | 253 +++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 234 insertions(+), 19 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 3205339957..8249d93326 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -32,11 +32,18 @@ typedef struct S1Translate { void *out_host; } S1Translate; =20 -static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, - target_ulong address, - MMUAccessType access_type, - GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) +static bool get_phys_addr_inner(CPUARMState *env, S1Translate *ptw, + target_ulong address, + MMUAccessType access_type, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) + __attribute__((nonnull)); + +static bool get_phys_addr_outer(CPUARMState *env, S1Translate *ptw, + target_ulong address, + MMUAccessType access_type, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) __attribute__((nonnull)); =20 /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. = */ @@ -193,6 +200,197 @@ static bool regime_translation_disabled(CPUARMState *= env, ARMMMUIdx mmu_idx, return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; } =20 +static bool granule_protection_check(CPUARMState *env, uint64_t paddress, + ARMSecuritySpace pspace, + ARMMMUFaultInfo *fi) +{ + MemTxAttrs attrs =3D { + .secure =3D true, + .space =3D ARMSS_Root, + }; + ARMCPU *cpu =3D env_archcpu(env); + uint64_t gpccr =3D env->cp15.gpccr_el3; + unsigned pps, pgs, l0gptsz, level =3D 0; + uint64_t tableaddr, pps_mask, align, entry, index; + AddressSpace *as; + MemTxResult result; + int gpi; + + if (!FIELD_EX64(gpccr, GPCCR, GPC)) { + return true; + } + + /* + * GPC Priority 1 (R_GMGRR): + * R_JWCSM: If the configuration of GPCCR_EL3 is invalid, + * the access fails as GPT walk fault at level 0. + */ + + /* + * Configuration of PPS to a value exceeding the implemented + * physical address size is invalid. + */ + pps =3D FIELD_EX64(gpccr, GPCCR, PPS); + if (pps > FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE)) { + goto fault_walk; + } + pps =3D pamax_map[pps]; + pps_mask =3D MAKE_64BIT_MASK(0, pps); + + switch (FIELD_EX64(gpccr, GPCCR, SH)) { + case 0b10: /* outer sharable */ + break; + case 0b00: /* non-sharable */ + case 0b11: /* inner sharable */ + /* Inner and Outer non-cacheable requires Outer sharable. */ + if (FIELD_EX64(gpccr, GPCCR, ORGN) =3D=3D 0 && + FIELD_EX64(gpccr, GPCCR, IRGN) =3D=3D 0) { + goto fault_walk; + } + break; + default: /* reserved */ + goto fault_walk; + } + + switch (FIELD_EX64(gpccr, GPCCR, PGS)) { + case 0b00: /* 4KB */ + pgs =3D 12; + break; + case 0b01: /* 64KB */ + pgs =3D 16; + break; + case 0b10: /* 16KB */ + pgs =3D 14; + break; + default: /* reserved */ + goto fault_walk; + } + + /* Note this field is read-only and fixed at reset. */ + l0gptsz =3D 30 + FIELD_EX64(gpccr, GPCCR, L0GPTSZ); + + /* + * GPC Priority 2: Secure, Realm or Root address exceeds PPS. + * R_CPDSB: A NonSecure physical address input exceeding PPS + * does not experience any fault. + */ + if (paddress & ~pps_mask) { + if (pspace =3D=3D ARMSS_NonSecure) { + return true; + } + goto fault_size; + } + + /* GPC Priority 3: the base address of GPTBR_EL3 exceeds PPS. */ + tableaddr =3D env->cp15.gptbr_el3 << 12; + if (tableaddr & ~pps_mask) { + goto fault_size; + } + + /* + * BADDR is aligned per a function of PPS and L0GPTSZ. + * These bits of GPTBR_EL3 are RES0, but are not a configuration error, + * unlike the RES0 bits of the GPT entries (R_XNKFZ). + */ + align =3D MAX(pps - l0gptsz + 3, 12); + align =3D MAKE_64BIT_MASK(0, align); + tableaddr &=3D ~align; + + as =3D arm_addressspace(env_cpu(env), attrs); + + /* Level 0 lookup. */ + index =3D extract64(paddress, l0gptsz, pps - l0gptsz); + tableaddr +=3D index * 8; + entry =3D address_space_ldq_le(as, tableaddr, attrs, &result); + if (result !=3D MEMTX_OK) { + goto fault_eabt; + } + + switch (extract32(entry, 0, 4)) { + case 1: /* block descriptor */ + if (entry >> 8) { + goto fault_walk; /* RES0 bits not 0 */ + } + gpi =3D extract32(entry, 4, 4); + goto found; + case 3: /* table descriptor */ + tableaddr =3D entry & ~0xf; + align =3D MAX(l0gptsz - pgs - 1, 12); + align =3D MAKE_64BIT_MASK(0, align); + if (tableaddr & (~pps_mask | align)) { + goto fault_walk; /* RES0 bits not 0 */ + } + break; + default: /* invalid */ + goto fault_walk; + } + + /* Level 1 lookup */ + level =3D 1; + index =3D extract64(paddress, pgs + 4, l0gptsz - pgs - 4); + tableaddr +=3D index * 8; + entry =3D address_space_ldq_le(as, tableaddr, attrs, &result); + if (result !=3D MEMTX_OK) { + goto fault_eabt; + } + + switch (extract32(entry, 0, 4)) { + case 1: /* contiguous descriptor */ + if (entry >> 10) { + goto fault_walk; /* RES0 bits not 0 */ + } + /* + * Because the softmmu tlb only works on units of TARGET_PAGE_SIZE, + * and because we cannot invalidate by pa, and thus will always + * flush entire tlbs, we don't actually care about the range here + * and can simply extract the GPI as the result. + */ + if (extract32(entry, 8, 2) =3D=3D 0) { + goto fault_walk; /* reserved contig */ + } + gpi =3D extract32(entry, 4, 4); + break; + default: + index =3D extract64(paddress, pgs, 4); + gpi =3D extract64(entry, index * 4, 4); + break; + } + + found: + switch (gpi) { + case 0b0000: /* no access */ + break; + case 0b1111: /* all access */ + return true; + case 0b1000: + case 0b1001: + case 0b1010: + case 0b1011: + if (pspace =3D=3D (gpi & 3)) { + return true; + } + break; + default: + goto fault_walk; /* reserved */ + } + + fi->gpcf =3D GPCF_Fail; + goto fault_common; + fault_eabt: + fi->gpcf =3D GPCF_EABT; + goto fault_common; + fault_size: + fi->gpcf =3D GPCF_AddressSize; + goto fault_common; + fault_walk: + fi->gpcf =3D GPCF_Walk; + fault_common: + fi->level =3D level; + fi->paddr =3D paddress; + fi->paddr_space =3D pspace; + return false; +} + static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) { /* @@ -238,8 +436,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl= ate *ptw, }; GetPhysAddrResult s2 =3D { }; =20 - if (get_phys_addr_with_struct(env, &s2ptw, addr, - MMU_DATA_LOAD, &s2, fi)) { + if (get_phys_addr_outer(env, &s2ptw, addr, MMU_DATA_LOAD, &s2, fi)= ) { goto fail; } ptw->out_phys =3D s2.f.phys_addr; @@ -300,6 +497,9 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl= ate *ptw, =20 fail: assert(fi->type !=3D ARMFault_None); + if (fi->type =3D=3D ARMFault_GPCFOnOutput) { + fi->type =3D ARMFault_GPCFOnWalk; + } fi->s2addr =3D addr; fi->stage2 =3D true; fi->s1ptw =3D true; @@ -2811,7 +3011,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, ARMSecuritySpace ipa_space, s2walk_space; uint64_t hcr; =20 - ret =3D get_phys_addr_with_struct(env, ptw, address, access_type, resu= lt, fi); + ret =3D get_phys_addr_inner(env, ptw, address, access_type, result, fi= ); =20 /* If S1 fails, return early. */ if (ret) { @@ -2848,7 +3048,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, cacheattrs1 =3D result->cacheattrs; memset(result, 0, sizeof(*result)); =20 - ret =3D get_phys_addr_with_struct(env, ptw, ipa, access_type, result, = fi); + ret =3D get_phys_addr_inner(env, ptw, ipa, access_type, result, fi); fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ @@ -2908,11 +3108,11 @@ static bool get_phys_addr_twostage(CPUARMState *env= , S1Translate *ptw, return false; } =20 -static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, - target_ulong address, - MMUAccessType access_type, - GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) +static bool get_phys_addr_inner(CPUARMState *env, S1Translate *ptw, + target_ulong address, + MMUAccessType access_type, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) { ARMMMUIdx mmu_idx =3D ptw->in_mmu_idx; bool is_secure =3D ptw->in_secure; @@ -3032,6 +3232,23 @@ static bool get_phys_addr_with_struct(CPUARMState *e= nv, S1Translate *ptw, } } =20 +static bool get_phys_addr_outer(CPUARMState *env, S1Translate *ptw, + target_ulong address, + MMUAccessType access_type, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) +{ + if (get_phys_addr_inner(env, ptw, address, access_type, result, fi)) { + return true; + } + if (!granule_protection_check(env, result->f.phys_addr, + result->f.attrs.space, fi)) { + fi->type =3D ARMFault_GPCFOnOutput; + return true; + } + return false; +} + bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, bool is_secure, GetPhysAddrResult *result, @@ -3042,8 +3259,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, .in_secure =3D is_secure, .in_space =3D arm_secure_to_space(is_secure), }; - return get_phys_addr_with_struct(env, &ptw, address, access_type, - result, fi); + return get_phys_addr_outer(env, &ptw, address, access_type, result, fi= ); } =20 bool get_phys_addr(CPUARMState *env, target_ulong address, @@ -3113,8 +3329,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, =20 ptw.in_space =3D ss; ptw.in_secure =3D arm_space_is_secure(ss); - return get_phys_addr_with_struct(env, &ptw, address, access_type, - result, fi); + return get_phys_addr_outer(env, &ptw, address, access_type, result, fi= ); } =20 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, @@ -3133,7 +3348,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs= , vaddr addr, ARMMMUFaultInfo fi =3D {}; bool ret; =20 - ret =3D get_phys_addr_with_struct(env, &ptw, addr, MMU_DATA_LOAD, &res= , &fi); + ret =3D get_phys_addr_outer(env, &ptw, addr, MMU_DATA_LOAD, &res, &fi); *attrs =3D res.f.attrs; =20 if (ret) { --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.01.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:01:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QK9QlABk5t9+fp8Dy6kIrYtuJQuby0NjdaBqhl+wHuM=; b=WvEXUHsm7KLRLg6Ywu9lX/WUlE2AG4kqp9QgslghcrYvDYgmMB7ajJf7QV/5HKmJ3w 0dnNpruT/qhxh/zS4oeJqtYP+livbdPaZE63m2iXQVSFtQ1TOgJ5WXhwC3MlpOjldKKJ MLhzI1olWBa+tG0YkQ1qflRfigwFDQe4FtTG9BCqiHkpDl4mSHC2wE7I+RQoE+uy3iiS ZnQ+YseiXuMEqlxiuLdEavBBNNElPAiPLPhrkNG99tIfOu7HeM+BhF95sMXHxKNbz33f OOJwUTaLWYjUF9JEsfglCIGrtgYB/S0u4PhniGMri9tPrNItQG8lqgrbnOkYjT3vLgRc Lhpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QK9QlABk5t9+fp8Dy6kIrYtuJQuby0NjdaBqhl+wHuM=; b=xuoW81flxHZHCbM3sQ5Rde3doRCAbJpIw2q6pm6o2osgKG4DaL1fwHi8Rk6sRSL1IU rO2G6dp5RB3gWYkmiomk6GTULJbylh8ttE8sOdlenrm9/OOO7xE6yoMxYmSt2bQg1xSP qs0HRs3kmff9Nu5yhTPVo2wBHO1TlMCzd7kSmtI5i4WbZBdkrDZ4J7lOs77Z8dzsKMb/ 1pRevTGYSbEjma/NaAnMTckZfcizTaUxBVKukiIUU8TvaJrPfnNjNfy/DJouawWBAMSJ x5UuVh/eHmlF/F6rD3spTX/3+a4XHlAYZt3ePkVkAmMtbscqtHfI9A7upBu37TLVgQXX 4i9w== X-Gm-Message-State: AFqh2ko2ZCt1NueAjQceV3aXTMyG77fD75sxW7P54JHhftRE3uCLfGG/ d37hGSSyPXZyUUQHublVFaWtVZRYsw73KmU/ X-Google-Smtp-Source: AMrXdXvgYb64dFjVNhqtkCSD6VDa+qiCE4xSN2z+hcvM8Y8EbravaKXHmAHwMaZ4r1dYgj/LEzCNGw== X-Received: by 2002:a05:6a00:1d23:b0:58a:9bef:5cd3 with SMTP id a35-20020a056a001d2300b0058a9bef5cd3mr24725396pfx.17.1674518483396; Mon, 23 Jan 2023 16:01:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [PATCH 21/22] target/arm: Enable RME for -cpu max Date: Mon, 23 Jan 2023 14:00:26 -1000 Message-Id: <20230124000027.3565716-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518804782100001 Content-Type: text/plain; charset="utf-8" Add a cpu property to set GPCCR_EL3.L0GPTSZ, for testing various possible configurations. Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0e021960fb..b9343004fb 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -672,6 +672,40 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) cpu->isar.id_aa64mmfr0 =3D t; } =20 +static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + uint32_t value; + + if (!visit_type_uint32(v, name, &value, errp)) { + return; + } + + /* Encode the value for the GPCCR_EL3 field. */ + switch (value) { + case 30: + case 34: + case 36: + case 39: + cpu->reset_l0gptsz =3D value - 30; + break; + default: + error_setg(errp, "invalid value for l0gptsz"); + error_append_hint(errp, "valid values are 30, 34, 36, 39\n"); + break; + } +} + +static void cpu_max_get_l0gptsz(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + uint32_t value =3D cpu->reset_l0gptsz + 30; + + visit_type_uint32(v, name, &value, errp); +} + static void aarch64_a57_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -1200,6 +1234,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ + t =3D FIELD_DP64(t, ID_AA64PFR0, RME, 1); /* FEAT_RME */ t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ cpu->isar.id_aa64pfr0 =3D t; @@ -1300,6 +1335,8 @@ static void aarch64_max_initfn(Object *obj) object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_v= q, cpu_max_set_sve_max_vq, NULL, NULL); qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); + object_property_add(obj, "l0gptsz", "uint32", cpu_max_get_l0gptsz, + cpu_max_set_l0gptsz, NULL, NULL); } =20 static const ARMCPUInfo aarch64_cpus[] =3D { --=20 2.34.1 From nobody Fri Nov 1 00:17:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1674518550; cv=none; d=zohomail.com; s=zohoarc; b=YcnOdl0BdYorAW0kNfaM4RCymVBObpQEOHkA3JEUVpZlsApLM7llg5lUSG05Zlh5g9sxSnsGD0ZAfTN4/GIBd4RT+/I/pWXe6dANBFh4b6ROHDyqmtkihJw7ju6Ubr190KMTZHWU79dxhejg7R+35ZV8i+HwLOOnrQuuQ77WvfA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1674518550; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Sxmu3I0hDA1CWS8XImZtEgPfNNeikAqJdreOIihUfNI=; b=lM9fV+9KZeNQEHGD2L+Dg3gPAXc/jvHGRoXMirYuyOmaMT2wBzq26YfYL4Y32UJezcVBuIDrabRE990h/Qq8VcwlJ9HL8j3ihKoLq4bSKQcv7fV6e3VPD2dVTAu0mKPmWjlSr4AVBI74DPxcpOU89979kp+Amue6pFo93BVh7HM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1674518550044435.37349618979067; Mon, 23 Jan 2023 16:02:30 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pK6km-0001vz-2h; Mon, 23 Jan 2023 19:01:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK6kk-0001kC-1I for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:30 -0500 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK6kg-00020v-QV for qemu-devel@nongnu.org; Mon, 23 Jan 2023 19:01:29 -0500 Received: by mail-pf1-x42c.google.com with SMTP id z31so7008008pfw.4 for ; Mon, 23 Jan 2023 16:01:26 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id x21-20020a056a00189500b0058bc37f3d13sm174104pfh.43.2023.01.23.16.01.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 16:01:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Sxmu3I0hDA1CWS8XImZtEgPfNNeikAqJdreOIihUfNI=; b=SDGSijOPYEtDNiSI+ZlIFXF6s8HyPmr7UoCJUY7LvR+h10YVsHpsOFqAsxYDZiWYWO x+y7TabBveA/99cBkFKYkTQ1CVopWjaqRixIoj8fVCAqZK6TtjxzWLI5WR5HBOAo8ce+ h6hl7r5/5T2cTaGXkcTXSeJ8tpELnWzN+21FMBzpXw06KTg9JJrgRjeHrZChqLmW71C9 mUbinCUvfP5QEmRB9bA0ytow5pq/Ky38SHWjcviS/9tz0hwyMN1oJ060+1U7NF2xidXe V5SV4bU2mIiv8kfCV23u/pnp0vZP23X/AeggNos1uD3wRBS/5ooYZZyF5kJduRocDAdI /phw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Sxmu3I0hDA1CWS8XImZtEgPfNNeikAqJdreOIihUfNI=; b=QEo2JwQbVY5uvJusXUIDxKY1Espsz38glV53Tb/nYm/L5eI3sYRtLrSSR58vhu+33t BPHxH42Pm0IZ68OpBlihzvFvVqJzdRT1UxoUUDJ+I2oN3VdjqxQB/WWk9dL80Je2ZHCu 4byrvgBA/fFU5B+A4GSIWu7y/cJxHt+L0m5GIqSZCagBaSu7HFawAj36EFXD+4r6hddv m1vbKYPSXsLvx5sVAyyNJ5ZgawnXpRgY0vAVD8F2iMWRgQpSUhJz80Ndn4NP68HluQZT bJHXAe/0srIthGKSDtqsFN/G8YQRWjbp56qvFCOgSTBh19v/xH7KYjX/WRTD/mqindVV p3gw== X-Gm-Message-State: AFqh2koSHSz9ad3xraiwEPV3TlqXL3tHOia4XHBp14AkwKHUm7mL7tAM txQ+npcP9Y5crx9E77irVoYRDewJV/tS2lvA X-Google-Smtp-Source: AMrXdXuarGOivnJEqJDKmL9V35HEdR1mZHK7Q+R4Ktf9n+7a+JvD/62IUpwYtcaDjMD5fZkis+3jqA== X-Received: by 2002:a05:6a00:4515:b0:575:d06d:1bfa with SMTP id cw21-20020a056a00451500b00575d06d1bfamr26572835pfb.2.1674518485100; Mon, 23 Jan 2023 16:01:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org Subject: [RFC PATCH 22/22] hw/arm/virt: Add some memory for Realm Management Monitor Date: Mon, 23 Jan 2023 14:00:27 -1000 Message-Id: <20230124000027.3565716-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230124000027.3565716-1-richard.henderson@linaro.org> References: <20230124000027.3565716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1674518551516100001 Content-Type: text/plain; charset="utf-8" This is arbitrary, but used by the Huawei TF-A test code. Signed-off-by: Richard Henderson --- include/hw/arm/virt.h | 2 ++ hw/arm/virt.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index c7dd59d7f1..bb7ac19358 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -86,6 +86,7 @@ enum { VIRT_ACPI_GED, VIRT_NVDIMM_ACPI, VIRT_PVTIME, + VIRT_RMM_MEM, VIRT_LOWMEMMAP_LAST, }; =20 @@ -154,6 +155,7 @@ struct VirtMachineState { bool virt; bool ras; bool mte; + bool rmm; bool dtb_randomness; OnOffAuto acpi; VirtGICType gic_version; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ea2413a0ba..5f1fddd210 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -158,6 +158,7 @@ static const MemMapEntry base_memmap[] =3D { /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that siz= e */ [VIRT_PLATFORM_BUS] =3D { 0x0c000000, 0x02000000 }, [VIRT_SECURE_MEM] =3D { 0x0e000000, 0x01000000 }, + [VIRT_RMM_MEM] =3D { 0x0f000000, 0x00100000 }, [VIRT_PCIE_MMIO] =3D { 0x10000000, 0x2eff0000 }, [VIRT_PCIE_PIO] =3D { 0x3eff0000, 0x00010000 }, [VIRT_PCIE_ECAM] =3D { 0x3f000000, 0x01000000 }, @@ -1601,6 +1602,25 @@ static void create_secure_ram(VirtMachineState *vms, g_free(nodename); } =20 +static void create_rmm_ram(VirtMachineState *vms, + MemoryRegion *sysmem, + MemoryRegion *tag_sysmem) +{ + MemoryRegion *rmm_ram =3D g_new(MemoryRegion, 1); + hwaddr base =3D vms->memmap[VIRT_RMM_MEM].base; + hwaddr size =3D vms->memmap[VIRT_RMM_MEM].size; + + memory_region_init_ram(rmm_ram, NULL, "virt.rmm-ram", size, + &error_fatal); + memory_region_add_subregion(sysmem, base, rmm_ram); + + /* do not fill in fdt to hide rmm from normal world guest */ + + if (tag_sysmem) { + create_tag_ram(tag_sysmem, base, size, "mach-virt.rmm-tag"); + } +} + static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) { const VirtMachineState *board =3D container_of(binfo, VirtMachineState, @@ -2273,6 +2293,10 @@ static void machvirt_init(MachineState *machine) machine->ram_size, "mach-virt.tag"); } =20 + if (vms->rmm) { + create_rmm_ram(vms, sysmem, tag_sysmem); + } + vms->highmem_ecam &=3D (!firmware_loaded || aarch64); =20 create_rtc(vms); @@ -2552,6 +2576,20 @@ static void virt_set_mte(Object *obj, bool value, Er= ror **errp) vms->mte =3D value; } =20 +static bool virt_get_rmm(Object *obj, Error **errp) +{ + VirtMachineState *vms =3D VIRT_MACHINE(obj); + + return vms->rmm; +} + +static void virt_set_rmm(Object *obj, bool value, Error **errp) +{ + VirtMachineState *vms =3D VIRT_MACHINE(obj); + + vms->rmm =3D value; +} + static char *virt_get_gic_version(Object *obj, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); @@ -3101,6 +3139,11 @@ static void virt_machine_class_init(ObjectClass *oc,= void *data) "guest CPU which implements the = ARM " "Memory Tagging Extension"); =20 + object_class_property_add_bool(oc, "rmm", virt_get_rmm, virt_set_rmm); + object_class_property_set_description(oc, "rmm", + "Set on/off to enable/disable ra= m " + "for the Realm Management Monito= r"); + object_class_property_add_bool(oc, "its", virt_get_its, virt_set_its); object_class_property_set_description(oc, "its", --=20 2.34.1