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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :x-mailer:message-id:date:subject:to:from; s=dkim; t=1674446278; x=1677038279; bh=FxoK4IQ1hDzxmuW2EbFKJk8WcNRVQ67PURdzoxUFdNg=; b= bnF0Xs1tw8Osn5skKiR/ZYDZUfoEC3cjXX4d3Pz5QJ8niRwZBRiiWYYxpnZ7zlnO +CQBb1ztPQucFxUuTjzb2MPDlcdi6MijU1qhT6wruUmZ5RWYlDnlEReYF89DPWPi ZnbHx1NIJnk7D3V+CPaPMKdDdZ9hP9/isXWoyADfQQzAygBkhKe7d7WkinBVdb6t chC1QfMu2czzM1mazpL7FcxSY/J6OyO4gxhBFvQmBiUzpdN9m+bMgqtmF8rj3yNs eCW8FKlODktCNnAI/ZyzGS2CYb87xcWxorst4fjAxCQP4GX8qx9ndzmb8wIRmzDP eZmeUJMEjKPCVEsslRwoXg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, Bin Meng , alistair23@gmail.com, bmeng.cn@gmail.com Subject: [PATCH] hw/riscv: boot: Don't use CSRs if they are disabled Date: Mon, 23 Jan 2023 13:57:54 +1000 Message-Id: <20230123035754.75553-1-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=380dee0ef=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1674446347094100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis If the CSRs and CSR instructions are disabled because the Zicsr extension isn't enabled then we want to make sure we don't run any CSR instructions in the boot ROM. This patches removes the CSR instructions from the reset-vec if the extension isn't enabled. We replace the instruction with a NOP instead. Note that we don't do this for the SiFive U machine, as we are modelling the hardware in that case. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1447 Signed-off-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 2594276223..cb27798a25 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -356,6 +356,15 @@ void riscv_setup_rom_reset_vec(MachineState *machine, = RISCVHartArrayState *harts reset_vec[4] =3D 0x0182b283; /* ld t0, 24(t0) */ } =20 + if (!harts->harts[0].cfg.ext_icsr) { + /* + * The Zicsr extension has been disabled, so let's ensure we don't + * run the CSR instruction. Let's fill the address with a non + * compressed nop. + */ + reset_vec[2] =3D 0x00000013; /* addi x0, x0, 0 */ + } + /* copy in the reset vector in little_endian byte order */ for (i =3D 0; i < ARRAY_SIZE(reset_vec); i++) { reset_vec[i] =3D cpu_to_le32(reset_vec[i]); --=20 2.39.0